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From: Ciara Power <ciara.power@intel.com>
To: dev@dpdk.org
Cc: gakhil@marvell.com, Ciara Power <ciara.power@intel.com>,
nishikanta.nayak@intel.com, Kai Ji <kai.ji@intel.com>
Subject: [PATCH] common/qat: fix undefined macro
Date: Tue, 5 Mar 2024 11:55:36 +0000
Message-Id: <20240305115537.3042539-1-ciara.power@intel.com>
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When using RTE_ENABLE_ASSERT and debug mode, an undefined
macro error appeared for ICP_QAT_FW_SYM_COMM_ADDR_SGL.
This was not being defined, but is now added to the header file.
Bugzilla ID: 1395
Fixes: e9271821e489 ("common/qat: support GEN LCE device")
Signed-off-by: Ciara Power <ciara.power@intel.com>
---
Cc: nishikanta.nayak@intel.com
---
drivers/common/qat/qat_adf/icp_qat_fw_la.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/common/qat/qat_adf/icp_qat_fw_la.h b/drivers/common/qat/qat_adf/icp_qat_fw_la.h
index 67fc25c919..fe32b66c50 100644
--- a/drivers/common/qat/qat_adf/icp_qat_fw_la.h
+++ b/drivers/common/qat/qat_adf/icp_qat_fw_la.h
@@ -111,6 +111,7 @@ struct icp_qat_fw_la_bulk_req {
#define ICP_QAT_FW_SYM_IV_IN_DESC_VALID 1
#define ICP_QAT_FW_SYM_DIRECTION_BITPOS 15
#define ICP_QAT_FW_SYM_DIRECTION_MASK 0x1
+#define ICP_QAT_FW_SYM_COMM_ADDR_SGL 1
/* In GEN_LCE AEAD AES GCM Algorithm has ID 0 */
#define QAT_LA_CRYPTO_AEAD_AES_GCM_GEN_LCE 0
--
2.25.1