From: Vidya Sagar Velumuri <vvelumuri@marvell.com>
To: Nithin Dabilpuram <ndabilpuram@marvell.com>,
Kiran Kumar K <kirankumark@marvell.com>,
Sunil Kumar Kori <skori@marvell.com>,
Satha Rao <skoteshwar@marvell.com>,
Harman Kalra <hkalra@marvell.com>,
Ankur Dwivedi <adwivedi@marvell.com>,
Anoob Joseph <anoobj@marvell.com>,
Tejasree Kondoj <ktejasree@marvell.com>
Cc: <gakhil@marvell.com>, <jerinj@marvell.com>,
<vvelumuri@marvell.com>, <asasidharan@marvell.com>,
<dev@dpdk.org>
Subject: [PATCH 11/12] crypto/cnxk: enable chachapoly capability for tls
Date: Thu, 14 Mar 2024 01:38:43 -0700 [thread overview]
Message-ID: <20240314083844.3319506-12-vvelumuri@marvell.com> (raw)
In-Reply-To: <20240314083844.3319506-1-vvelumuri@marvell.com>
Enable CHACHA20-POLY1305 support for TLS-1.3.
Signed-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>
---
drivers/common/cnxk/roc_ie_ot_tls.h | 1 +
drivers/crypto/cnxk/cn10k_tls.c | 40 ++++++++++++-------
drivers/crypto/cnxk/cnxk_cryptodev.h | 4 +-
.../crypto/cnxk/cnxk_cryptodev_capabilities.c | 31 ++++++++++++++
4 files changed, 60 insertions(+), 16 deletions(-)
diff --git a/drivers/common/cnxk/roc_ie_ot_tls.h b/drivers/common/cnxk/roc_ie_ot_tls.h
index 44850f7060..2d6a290d9b 100644
--- a/drivers/common/cnxk/roc_ie_ot_tls.h
+++ b/drivers/common/cnxk/roc_ie_ot_tls.h
@@ -39,6 +39,7 @@ enum roc_ie_ot_tls_cipher_type {
ROC_IE_OT_TLS_CIPHER_AES_CBC = 3,
ROC_IE_OT_TLS_CIPHER_AES_GCM = 7,
ROC_IE_OT_TLS_CIPHER_AES_CCM = 10,
+ ROC_IE_OT_TLS_CIPHER_CHACHA_POLY = 9,
};
enum roc_ie_ot_tls_ver {
diff --git a/drivers/crypto/cnxk/cn10k_tls.c b/drivers/crypto/cnxk/cn10k_tls.c
index 4b558ef365..7b73a58d2a 100644
--- a/drivers/crypto/cnxk/cn10k_tls.c
+++ b/drivers/crypto/cnxk/cn10k_tls.c
@@ -97,6 +97,9 @@ tls_xform_aead_verify(struct rte_security_tls_record_xform *tls_xform,
return 0;
}
+ if ((crypto_xform->aead.algo == RTE_CRYPTO_AEAD_CHACHA20_POLY1305) && (keylen == 32))
+ return 0;
+
return -EINVAL;
}
@@ -351,15 +354,20 @@ tls_read_sa_fill(struct roc_ie_ot_tls_read_sa *read_sa,
cipher_key = read_sa->cipher_key;
/* Set encryption algorithm */
- if ((crypto_xfrm->type == RTE_CRYPTO_SYM_XFORM_AEAD) &&
- (crypto_xfrm->aead.algo == RTE_CRYPTO_AEAD_AES_GCM)) {
- read_sa->w2.s.cipher_select = ROC_IE_OT_TLS_CIPHER_AES_GCM;
-
+ if (crypto_xfrm->type == RTE_CRYPTO_SYM_XFORM_AEAD) {
length = crypto_xfrm->aead.key.length;
- if (length == 16)
- read_sa->w2.s.aes_key_len = ROC_IE_OT_TLS_AES_KEY_LEN_128;
- else
+ if (crypto_xfrm->aead.algo == RTE_CRYPTO_AEAD_AES_GCM) {
+ read_sa->w2.s.cipher_select = ROC_IE_OT_TLS_CIPHER_AES_GCM;
+ if (length == 16)
+ read_sa->w2.s.aes_key_len = ROC_IE_OT_TLS_AES_KEY_LEN_128;
+ else
+ read_sa->w2.s.aes_key_len = ROC_IE_OT_TLS_AES_KEY_LEN_256;
+ }
+
+ if (crypto_xfrm->aead.algo == RTE_CRYPTO_AEAD_CHACHA20_POLY1305) {
+ read_sa->w2.s.cipher_select = ROC_IE_OT_TLS_CIPHER_CHACHA_POLY;
read_sa->w2.s.aes_key_len = ROC_IE_OT_TLS_AES_KEY_LEN_256;
+ }
key = crypto_xfrm->aead.key.data;
memcpy(cipher_key, key, length);
@@ -500,15 +508,19 @@ tls_write_sa_fill(struct roc_ie_ot_tls_write_sa *write_sa,
cipher_key = write_sa->cipher_key;
/* Set encryption algorithm */
- if ((crypto_xfrm->type == RTE_CRYPTO_SYM_XFORM_AEAD) &&
- (crypto_xfrm->aead.algo == RTE_CRYPTO_AEAD_AES_GCM)) {
- write_sa->w2.s.cipher_select = ROC_IE_OT_TLS_CIPHER_AES_GCM;
-
+ if (crypto_xfrm->type == RTE_CRYPTO_SYM_XFORM_AEAD) {
length = crypto_xfrm->aead.key.length;
- if (length == 16)
- write_sa->w2.s.aes_key_len = ROC_IE_OT_TLS_AES_KEY_LEN_128;
- else
+ if (crypto_xfrm->aead.algo == RTE_CRYPTO_AEAD_AES_GCM) {
+ write_sa->w2.s.cipher_select = ROC_IE_OT_TLS_CIPHER_AES_GCM;
+ if (length == 16)
+ write_sa->w2.s.aes_key_len = ROC_IE_OT_TLS_AES_KEY_LEN_128;
+ else
+ write_sa->w2.s.aes_key_len = ROC_IE_OT_TLS_AES_KEY_LEN_256;
+ }
+ if (crypto_xfrm->aead.algo == RTE_CRYPTO_AEAD_CHACHA20_POLY1305) {
+ write_sa->w2.s.cipher_select = ROC_IE_OT_TLS_CIPHER_CHACHA_POLY;
write_sa->w2.s.aes_key_len = ROC_IE_OT_TLS_AES_KEY_LEN_256;
+ }
key = crypto_xfrm->aead.key.data;
memcpy(cipher_key, key, length);
diff --git a/drivers/crypto/cnxk/cnxk_cryptodev.h b/drivers/crypto/cnxk/cnxk_cryptodev.h
index dccd563872..fffc4a47b4 100644
--- a/drivers/crypto/cnxk/cnxk_cryptodev.h
+++ b/drivers/crypto/cnxk/cnxk_cryptodev.h
@@ -13,9 +13,9 @@
#define CNXK_CPT_MAX_CAPS 55
#define CNXK_SEC_IPSEC_CRYPTO_MAX_CAPS 16
-#define CNXK_SEC_TLS_1_3_CRYPTO_MAX_CAPS 2
+#define CNXK_SEC_TLS_1_3_CRYPTO_MAX_CAPS 3
#define CNXK_SEC_TLS_1_2_CRYPTO_MAX_CAPS 7
-#define CNXK_SEC_MAX_CAPS 18
+#define CNXK_SEC_MAX_CAPS 19
/**
* Device private data
diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c b/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c
index 5bafa226e0..0d5d64b6e7 100644
--- a/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c
+++ b/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c
@@ -1693,6 +1693,37 @@ static const struct rte_cryptodev_capabilities sec_tls13_caps_aes[] = {
}, }
}, }
},
+ { /* CHACHA POLY */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AEAD,
+ {.aead = {
+ .algo = RTE_CRYPTO_AEAD_CHACHA20_POLY1305,
+ .block_size = 64,
+ .key_size = {
+ .min = 32,
+ .max = 32,
+ .increment = 0
+ },
+ .digest_size = {
+ .min = 16,
+ .max = 16,
+ .increment = 0
+ },
+ .aad_size = {
+ .min = 5,
+ .max = 5,
+ .increment = 0
+ },
+ .iv_size = {
+ .min = 0,
+ .max = 0,
+ .increment = 0
+ }
+ }, }
+ }, }
+ },
+
};
--
2.25.1
next prev parent reply other threads:[~2024-03-14 8:40 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-14 8:38 [PATCH 00/12] Add TLS features Vidya Sagar Velumuri
2024-03-14 8:38 ` [PATCH 01/12] crypto/cnxk: multi seg support block ciphers in tls Vidya Sagar Velumuri
2024-03-14 8:38 ` [PATCH 02/12] crypto/cnxk: enable sha384 capability for tls Vidya Sagar Velumuri
2024-03-14 8:38 ` [PATCH 03/12] crypto/cnxk: add support for session update for TLS Vidya Sagar Velumuri
2024-03-14 8:38 ` [PATCH 04/12] crypto/cnxk: avoid branches in datapath Vidya Sagar Velumuri
2024-03-14 8:38 ` [PATCH 05/12] crypto/cnxk: move metadata to second cacheline Vidya Sagar Velumuri
2024-03-14 8:38 ` [PATCH 06/12] crypto/cnxk: handle the extra len reported by microcode Vidya Sagar Velumuri
2024-03-14 8:38 ` [PATCH 07/12] crypto/cnxk: add support for padding verification in TLS Vidya Sagar Velumuri
2024-03-14 8:38 ` [PATCH 08/12] crypto/cnxk: add support for oop processing " Vidya Sagar Velumuri
2024-03-14 8:38 ` [PATCH 09/12] crypto/cnxk: update the context structure of tls Vidya Sagar Velumuri
2024-03-14 8:38 ` [PATCH 10/12] crypto/cnxk: use proper offset for context calculation Vidya Sagar Velumuri
2024-03-14 8:38 ` Vidya Sagar Velumuri [this message]
2024-03-14 8:38 ` [PATCH 12/12] crypto/cnxk: remove the response len handling for tls Vidya Sagar Velumuri
2024-03-14 9:46 ` [PATCH 00/12] Add TLS features Anoob Joseph
2024-03-14 14:48 ` Patrick Robb
2024-03-14 13:18 ` [PATCH v2 0/8] crypto/cnxk: fixes and minor updates for TLS Vidya Sagar Velumuri
2024-03-15 5:42 ` [PATCH v3 0/8] Fixes and minor improvements for Crypto cnxk Vidya Sagar Velumuri
2024-03-15 5:42 ` [PATCH v3 1/8] crypto/cnxk: multi seg support block ciphers in tls Vidya Sagar Velumuri
2024-03-15 5:42 ` [PATCH v3 2/8] crypto/cnxk: enable sha384 and chachapoly for tls Vidya Sagar Velumuri
2024-03-15 5:42 ` [PATCH v3 3/8] crypto/cnxk: add support for session update for TLS Vidya Sagar Velumuri
2024-03-15 5:42 ` [PATCH v3 4/8] crypto/cnxk: avoid branches in datapath Vidya Sagar Velumuri
2024-03-15 5:42 ` [PATCH v3 5/8] crypto/cnxk: move metadata to second cacheline Vidya Sagar Velumuri
2024-03-15 5:42 ` [PATCH v3 6/8] crypto/cnxk: add support for padding verification in TLS Vidya Sagar Velumuri
2024-03-15 5:42 ` [PATCH v3 7/8] crypto/cnxk: add support for oop processing " Vidya Sagar Velumuri
2024-03-15 5:42 ` [PATCH v3 8/8] crypto/cnxk: update the context structure of tls Vidya Sagar Velumuri
2024-03-15 6:45 ` [PATCH v4 0/8] Fixes and minor improvements for Crypto cnxk Vidya Sagar Velumuri
2024-03-15 6:45 ` [PATCH v4 1/8] crypto/cnxk: multi seg support block ciphers in tls Vidya Sagar Velumuri
2024-03-15 6:45 ` [PATCH v4 2/8] crypto/cnxk: enable sha384 and chachapoly for tls Vidya Sagar Velumuri
2024-03-15 6:45 ` [PATCH v4 3/8] crypto/cnxk: add support for session update for TLS Vidya Sagar Velumuri
2024-03-15 6:45 ` [PATCH v4 4/8] crypto/cnxk: avoid branches in datapath Vidya Sagar Velumuri
2024-03-15 6:45 ` [PATCH v4 5/8] crypto/cnxk: move metadata to second cacheline Vidya Sagar Velumuri
2024-03-15 6:45 ` [PATCH v4 6/8] crypto/cnxk: add support for padding verification in TLS Vidya Sagar Velumuri
2024-03-15 6:45 ` [PATCH v4 7/8] crypto/cnxk: add support for oop processing " Vidya Sagar Velumuri
2024-03-15 6:45 ` [PATCH v4 8/8] crypto/cnxk: update the context structure of tls Vidya Sagar Velumuri
2024-03-15 11:40 ` [PATCH v4 0/8] Fixes and minor improvements for Crypto cnxk Akhil Goyal
2024-03-14 13:18 ` [PATCH v2 1/8] crypto/cnxk: multi seg support block ciphers in tls Vidya Sagar Velumuri
2024-03-14 13:18 ` [PATCH v2 2/8] crypto/cnxk: enable sha384 and chachapoly for tls Vidya Sagar Velumuri
2024-03-14 13:18 ` [PATCH v2 3/8] crypto/cnxk: add support for session update for TLS Vidya Sagar Velumuri
2024-03-14 13:18 ` [PATCH v2 4/8] crypto/cnxk: avoid branches in datapath Vidya Sagar Velumuri
2024-03-14 13:18 ` [PATCH v2 5/8] crypto/cnxk: move metadata to second cacheline Vidya Sagar Velumuri
2024-03-14 13:18 ` [PATCH v2 6/8] crypto/cnxk: add support for padding verification in TLS Vidya Sagar Velumuri
2024-03-14 13:18 ` [PATCH v2 7/8] crypto/cnxk: add support for oop processing " Vidya Sagar Velumuri
2024-03-14 13:18 ` [PATCH v2 8/8] crypto/cnxk: update the context structure of tls Vidya Sagar Velumuri
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