From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 98F0343CA5; Thu, 14 Mar 2024 12:38:47 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 24DD040297; Thu, 14 Mar 2024 12:38:47 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id C67EE4028C for ; Thu, 14 Mar 2024 12:38:45 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 42DNMqR9016210; Thu, 14 Mar 2024 04:38:43 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type:content-transfer-encoding; s= pfpt0220; bh=GlKTeQHY5IQ/jJIsxdPAXDBw0CAcwimMZmdFfP+cElw=; b=PGB hWcDacXjGLNnzICEWyiFqeYwbaBIjvFz21PaNZ18omzfgh7b/vxcd41BRIbnBd4j jPDv4BNwFaJPb09KUApbBvN7p2pQmX3xFrMWZ6gyoep9hHrksjQ1UUsvxSV2ZXO1 KmO1q4gYFl73zLwJy9dhx53/KpolHtyslZx4vTvbIrgNaA/k7qtItNprm/bamKnX zV/8YpOBLXxr0cj3FbjbLdFMIISyzSHPNeD57853oJNmO6Twn7B5Vh1sIO5BSf3n UOmNCu8C6PQHgyYZaiUyOPRLytRt40z+cX+4X0HxAbvZp0wRxEV366x5CV2NjvfL pRWP1WGErEYgDnii48g== Received: from dc6wp-exch02.marvell.com ([4.21.29.225]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3wucg2vn7x-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Mar 2024 04:38:42 -0700 (PDT) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Thu, 14 Mar 2024 04:38:42 -0700 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Thu, 14 Mar 2024 04:38:41 -0700 Received: from MININT-80QBFE8.corp.innovium.com (MININT-80QBFE8.marvell.com [10.28.164.106]) by maili.marvell.com (Postfix) with ESMTP id A3AC73F7068; Thu, 14 Mar 2024 04:38:38 -0700 (PDT) From: To: , , , , Ruifeng Wang , "Bruce Richardson" CC: , Pavan Nikhilesh Subject: [PATCH v8 1/5] config/arm: avoid mcpu and march conflicts Date: Thu, 14 Mar 2024 17:08:25 +0530 Message-ID: <20240314113829.2511-1-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240306154957.750-1-pbhagavatula@marvell.com> References: <20240306154957.750-1-pbhagavatula@marvell.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: 7EmulXlil6HzoxQm58ih0sRh4KvltMus X-Proofpoint-GUID: 7EmulXlil6HzoxQm58ih0sRh4KvltMus X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-14_10,2024-03-13_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Pavan Nikhilesh The compiler options march and mtune are a subset of mcpu and will lead to conflicts if improper march is chosen for a given mcpu. To avoid conflicts, discard part number march when mcpu is available and is supported by the compiler. Example: march = armv9-a mcpu = neoverse-n2 mcpu supported, march supported machine_args = ['-mcpu=neoverse-n2'] mcpu supported, march not supported machine_args = ['-mcpu=neoverse-n2'] mcpu not supported, march supported machine_args = ['-march=armv9-a'] mcpu not supported, march not supported machine_args = ['-march=armv8.6-a'] Signed-off-by: Pavan Nikhilesh Reviewed-by: Juraj Linkeš --- v2 Changes: - Cleanup march inconsistencies. (Juraj Linkes) - Unify fallback march selection. (Juraj Linkes) - Tag along ARM WFE patch. v3 Changes: - Fix missing 'fallback_march' key check. v4 Changes: - Discard march when mcpu is supported. v5 Changes: - Consolidate mcpu and march checks. (Juraj Linkes) - Fix unintentionally skipping fallback march (Juraj Linkes) v6 Changes: - Remove compiler support check when march is forced. (Juraj Linkes) - Simplify fallback march configuration. v7 Changes: - Rebase on master. v8 Changes: - Split patches to be more explicit about changes. config/arm/meson.build | 115 ++++++++++++++++++++++++----------------- 1 file changed, 69 insertions(+), 46 deletions(-) diff --git a/config/arm/meson.build b/config/arm/meson.build index 9d6fb87d7f..4e7e072053 100644 --- a/config/arm/meson.build +++ b/config/arm/meson.build @@ -58,18 +58,18 @@ implementer_generic = { } part_number_config_arm = { - '0xd03': {'compiler_options': ['-mcpu=cortex-a53']}, - '0xd04': {'compiler_options': ['-mcpu=cortex-a35']}, - '0xd05': {'compiler_options': ['-mcpu=cortex-a55']}, - '0xd07': {'compiler_options': ['-mcpu=cortex-a57']}, - '0xd08': {'compiler_options': ['-mcpu=cortex-a72']}, - '0xd09': {'compiler_options': ['-mcpu=cortex-a73']}, - '0xd0a': {'compiler_options': ['-mcpu=cortex-a75']}, - '0xd0b': {'compiler_options': ['-mcpu=cortex-a76']}, + '0xd03': {'mcpu': 'cortex-a53'}, + '0xd04': {'mcpu': 'cortex-a35'}, + '0xd05': {'mcpu': 'cortex-a55'}, + '0xd07': {'mcpu': 'cortex-a57'}, + '0xd08': {'mcpu': 'cortex-a72'}, + '0xd09': {'mcpu': 'cortex-a73'}, + '0xd0a': {'mcpu': 'cortex-a75'}, + '0xd0b': {'mcpu': 'cortex-a76'}, '0xd0c': { 'march': 'armv8.2-a', 'march_features': ['crypto', 'rcpc'], - 'compiler_options': ['-mcpu=neoverse-n1'], + 'mcpu': 'neoverse-n1', 'flags': [ ['RTE_MACHINE', '"neoverse-n1"'], ['RTE_ARM_FEATURE_ATOMICS', true], @@ -81,7 +81,7 @@ part_number_config_arm = { '0xd40': { 'march': 'armv8.4-a', 'march_features': ['sve'], - 'compiler_options': ['-mcpu=neoverse-v1'], + 'mcpu': 'neoverse-v1', 'flags': [ ['RTE_MACHINE', '"neoverse-v1"'], ['RTE_ARM_FEATURE_ATOMICS', true], @@ -93,7 +93,7 @@ part_number_config_arm = { }, '0xd49': { 'march_features': ['sve2'], - 'compiler_options': ['-mcpu=neoverse-n2'], + 'mcpu': 'neoverse-n2', 'flags': [ ['RTE_MACHINE', '"neoverse-n2"'], ['RTE_ARM_FEATURE_ATOMICS', true], @@ -103,7 +103,7 @@ part_number_config_arm = { }, '0xd4f': { 'march_features': ['sve2'], - 'compiler_options': ['-mcpu=neoverse-v2'], + 'mcpu' : 'neoverse-v2', 'flags': [ ['RTE_MACHINE', '"neoverse-v2"'], ['RTE_ARM_FEATURE_ATOMICS', true], @@ -137,21 +137,23 @@ implementer_cavium = { ], 'part_number_config': { '0xa1': { - 'compiler_options': ['-mcpu=thunderxt88'], + 'mcpu': 'thunderxt88', 'flags': flags_part_number_thunderx }, '0xa2': { - 'compiler_options': ['-mcpu=thunderxt81'], + 'mcpu': 'thunderxt81', 'flags': flags_part_number_thunderx }, '0xa3': { - 'compiler_options': ['-march=armv8-a+crc', '-mcpu=thunderxt83'], + 'march': 'armv8-a', + 'march_features': ['crc'], + 'mcpu': 'thunderxt83', 'flags': flags_part_number_thunderx }, '0xaf': { 'march': 'armv8.1-a', 'march_features': ['crc', 'crypto'], - 'compiler_options': ['-mcpu=thunderx2t99'], + 'mcpu': 'thunderx2t99', 'flags': [ ['RTE_MACHINE', '"thunderx2"'], ['RTE_ARM_FEATURE_ATOMICS', true], @@ -163,7 +165,7 @@ implementer_cavium = { '0xb2': { 'march': 'armv8.2-a', 'march_features': ['crc', 'crypto', 'lse'], - 'compiler_options': ['-mcpu=octeontx2'], + 'mcpu': 'octeontx2', 'flags': [ ['RTE_MACHINE', '"cn9k"'], ['RTE_ARM_FEATURE_ATOMICS', true], @@ -186,7 +188,7 @@ implementer_ampere = { '0x0': { 'march': 'armv8-a', 'march_features': ['crc', 'crypto'], - 'compiler_options': ['-mtune=emag'], + 'mcpu': 'emag', 'flags': [ ['RTE_MACHINE', '"eMAG"'], ['RTE_MAX_LCORE', 32], @@ -196,7 +198,7 @@ implementer_ampere = { '0xac3': { 'march': 'armv8.6-a', 'march_features': ['crc', 'crypto'], - 'compiler_options': ['-mcpu=ampere1'], + 'mcpu': 'ampere1', 'flags': [ ['RTE_MACHINE', '"AmpereOne"'], ['RTE_MAX_LCORE', 320], @@ -216,7 +218,7 @@ implementer_hisilicon = { '0xd01': { 'march': 'armv8.2-a', 'march_features': ['crypto'], - 'compiler_options': ['-mtune=tsv110'], + 'mcpu': 'tsv110', 'flags': [ ['RTE_MACHINE', '"Kunpeng 920"'], ['RTE_ARM_FEATURE_ATOMICS', true], @@ -258,14 +260,14 @@ implementer_ionic = { ], 'part_number_config': { '0xc1': { - 'compiler_options': ['-mcpu=cortex-a72'], + 'mcpu' : 'cortex-a72', 'flags': [ ['RTE_MAX_LCORE', 4], ['RTE_LIBRTE_IONIC_PMD_BARRIER_ERRATA', true], ] }, '0xc2': { - 'compiler_options': ['-mcpu=cortex-a72'], + 'mcpu' : 'cortex-a72', 'flags': [ ['RTE_MAX_LCORE', 16], ['RTE_LIBRTE_IONIC_PMD_BARRIER_ERRATA', true], @@ -797,9 +799,31 @@ if update_flags machine_args = [] # Clear previous machine args - # probe supported archs and their features + march_features = [] + if part_number_config.has_key('march_features') + march_features += part_number_config['march_features'] + endif + if soc_config.has_key('extra_march_features') + march_features += soc_config['extra_march_features'] + endif + + candidate_mcpu = '' candidate_march = '' - if part_number_config.has_key('march') + + if (part_number_config.has_key('mcpu') and + cc.has_argument('-mcpu=' + part_number_config['mcpu'])) + candidate_mcpu = '-mcpu=' + part_number_config['mcpu'] + foreach feature: march_features + if cc.has_argument('+'.join([candidate_mcpu, feature])) + candidate_mcpu = '+'.join([candidate_mcpu, feature]) + else + warning('The compiler does not support feature @0@' + .format(feature)) + endif + endforeach + machine_args += candidate_mcpu + elif part_number_config.has_key('march') + # probe supported archs and their features if part_number_config.get('force_march', false) candidate_march = part_number_config['march'] else @@ -819,32 +843,31 @@ if update_flags endif endforeach endif - if candidate_march == '' - error('No suitable armv8 march version found.') - endif + if candidate_march != part_number_config['march'] - warning('Configuration march version is ' + - '@0@, but the compiler supports only @1@.' - .format(part_number_config['march'], candidate_march)) + warning('Configuration march version is @0@, not supported.' + .format(part_number_config['march'])) + if candidate_march != '' + warning('Using march version @0@.'.format(candidate_march)) + endif endif - candidate_march = '-march=' + candidate_march - march_features = [] - if part_number_config.has_key('march_features') - march_features += part_number_config['march_features'] - endif - if soc_config.has_key('extra_march_features') - march_features += soc_config['extra_march_features'] + if candidate_march != '' + candidate_march = '-march=' + candidate_march + foreach feature: march_features + if cc.has_argument('+'.join([candidate_march, feature])) + candidate_march = '+'.join([candidate_march, feature]) + else + warning('The compiler does not support feature @0@' + .format(feature)) + endif + endforeach + machine_args += candidate_march endif - foreach feature: march_features - if cc.has_argument('+'.join([candidate_march, feature])) - candidate_march = '+'.join([candidate_march, feature]) - else - warning('The compiler does not support feature @0@' - .format(feature)) - endif - endforeach - machine_args += candidate_march + endif + + if candidate_mcpu == '' and candidate_march == '' + error('No suitable ARM march/mcpu version found.') endif # apply supported compiler options -- 2.25.1