From: Vidya Sagar Velumuri <vvelumuri@marvell.com>
To: Ankur Dwivedi <adwivedi@marvell.com>,
Anoob Joseph <anoobj@marvell.com>,
Tejasree Kondoj <ktejasree@marvell.com>
Cc: <gakhil@marvell.com>, <jerinj@marvell.com>,
<vvelumuri@marvell.com>, <asasidharan@marvell.com>,
<dev@dpdk.org>
Subject: [PATCH v2 1/8] crypto/cnxk: multi seg support block ciphers in tls
Date: Thu, 14 Mar 2024 06:18:32 -0700 [thread overview]
Message-ID: <20240314131839.3362494-2-vvelumuri@marvell.com> (raw)
In-Reply-To: <20240314083844.3319506-1-vvelumuri@marvell.com>
Add support for Scatter-Gather mode for block ciphers in TLS-1.2
Signed-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>
---
drivers/crypto/cnxk/cn10k_cryptodev_sec.h | 3 +-
drivers/crypto/cnxk/cn10k_tls.c | 5 +++
drivers/crypto/cnxk/cn10k_tls_ops.h | 48 ++++++++++++++++++-----
3 files changed, 45 insertions(+), 11 deletions(-)
diff --git a/drivers/crypto/cnxk/cn10k_cryptodev_sec.h b/drivers/crypto/cnxk/cn10k_cryptodev_sec.h
index 1efed3c4cf..881a0276cc 100644
--- a/drivers/crypto/cnxk/cn10k_cryptodev_sec.h
+++ b/drivers/crypto/cnxk/cn10k_cryptodev_sec.h
@@ -33,7 +33,8 @@ struct cn10k_sec_session {
} ipsec;
struct {
uint8_t enable_padding : 1;
- uint8_t rvsd : 7;
+ uint8_t tail_fetch_len : 2;
+ uint8_t rvsd : 5;
bool is_write;
} tls;
};
diff --git a/drivers/crypto/cnxk/cn10k_tls.c b/drivers/crypto/cnxk/cn10k_tls.c
index 879e0ea978..b46904d3f8 100644
--- a/drivers/crypto/cnxk/cn10k_tls.c
+++ b/drivers/crypto/cnxk/cn10k_tls.c
@@ -639,6 +639,11 @@ cn10k_tls_read_sa_create(struct roc_cpt *roc_cpt, struct roc_cpt_lf *lf,
if ((sa_dptr->w2.s.version_select == ROC_IE_OT_TLS_VERSION_TLS_12) ||
(sa_dptr->w2.s.version_select == ROC_IE_OT_TLS_VERSION_DTLS_12)) {
inst_w4.s.opcode_major = ROC_IE_OT_TLS_MAJOR_OP_RECORD_DEC | ROC_IE_OT_INPLACE_BIT;
+ sec_sess->tls.tail_fetch_len = 0;
+ if (sa_dptr->w2.s.cipher_select == ROC_IE_OT_TLS_CIPHER_3DES)
+ sec_sess->tls.tail_fetch_len = 1;
+ else if (sa_dptr->w2.s.cipher_select == ROC_IE_OT_TLS_CIPHER_AES_CBC)
+ sec_sess->tls.tail_fetch_len = 2;
} else if (sa_dptr->w2.s.version_select == ROC_IE_OT_TLS_VERSION_TLS_13) {
inst_w4.s.opcode_major =
ROC_IE_OT_TLS13_MAJOR_OP_RECORD_DEC | ROC_IE_OT_INPLACE_BIT;
diff --git a/drivers/crypto/cnxk/cn10k_tls_ops.h b/drivers/crypto/cnxk/cn10k_tls_ops.h
index 7c8ac14ab2..6fd74927ee 100644
--- a/drivers/crypto/cnxk/cn10k_tls_ops.h
+++ b/drivers/crypto/cnxk/cn10k_tls_ops.h
@@ -234,7 +234,10 @@ process_tls_read(struct rte_crypto_op *cop, struct cn10k_sec_session *sess,
inst->w4.u64 = w4.u64;
} else if (is_sg_ver2 == false) {
struct roc_sglist_comp *scatter_comp, *gather_comp;
+ int tail_len = sess->tls.tail_fetch_len * 16;
+ int pkt_len = rte_pktmbuf_pkt_len(m_src);
uint32_t g_size_bytes, s_size_bytes;
+ uint16_t *sg_hdr;
uint32_t dlen;
int i;
@@ -244,16 +247,25 @@ process_tls_read(struct rte_crypto_op *cop, struct cn10k_sec_session *sess,
return -ENOMEM;
}
- in_buffer = (uint8_t *)m_data;
- ((uint16_t *)in_buffer)[0] = 0;
- ((uint16_t *)in_buffer)[1] = 0;
-
/* Input Gather List */
+ in_buffer = (uint8_t *)m_data;
+ sg_hdr = (uint16_t *)(in_buffer + 32);
+ gather_comp = (struct roc_sglist_comp *)((uint8_t *)sg_hdr + 8);
i = 0;
- gather_comp = (struct roc_sglist_comp *)((uint8_t *)in_buffer + 8);
+ /* Add the last blocks as first gather component for tail fetch. */
+ if (tail_len) {
+ const uint8_t *output;
+
+ output = rte_pktmbuf_read(m_src, pkt_len - tail_len, tail_len, in_buffer);
+ if (output != in_buffer)
+ rte_memcpy(in_buffer, output, tail_len);
+ i = fill_sg_comp(gather_comp, i, (uint64_t)in_buffer, tail_len);
+ }
+ sg_hdr[0] = 0;
+ sg_hdr[1] = 0;
i = fill_sg_comp_from_pkt(gather_comp, i, m_src);
- ((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
+ sg_hdr[2] = rte_cpu_to_be_16(i);
g_size_bytes = ((i + 3) / 4) * sizeof(struct roc_sglist_comp);
@@ -261,7 +273,7 @@ process_tls_read(struct rte_crypto_op *cop, struct cn10k_sec_session *sess,
scatter_comp = (struct roc_sglist_comp *)((uint8_t *)gather_comp + g_size_bytes);
i = fill_sg_comp_from_pkt(scatter_comp, i, m_src);
- ((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
+ sg_hdr[3] = rte_cpu_to_be_16(i);
s_size_bytes = ((i + 3) / 4) * sizeof(struct roc_sglist_comp);
@@ -273,10 +285,12 @@ process_tls_read(struct rte_crypto_op *cop, struct cn10k_sec_session *sess,
w4.u64 = sess->inst.w4;
w4.s.dlen = dlen;
w4.s.opcode_major |= (uint64_t)ROC_DMA_MODE_SG;
- w4.s.param1 = rte_pktmbuf_pkt_len(m_src);
+ w4.s.param1 = pkt_len;
inst->w4.u64 = w4.u64;
} else {
struct roc_sg2list_comp *scatter_comp, *gather_comp;
+ int tail_len = sess->tls.tail_fetch_len * 16;
+ int pkt_len = rte_pktmbuf_pkt_len(m_src);
union cpt_inst_w5 cpt_inst_w5;
union cpt_inst_w6 cpt_inst_w6;
uint32_t g_size_bytes;
@@ -292,7 +306,21 @@ process_tls_read(struct rte_crypto_op *cop, struct cn10k_sec_session *sess,
/* Input Gather List */
i = 0;
- gather_comp = (struct roc_sg2list_comp *)((uint8_t *)in_buffer);
+ /* First 32 bytes in m_data are rsvd for tail fetch.
+ * SG list start from 32 byte onwards.
+ */
+ gather_comp = (struct roc_sg2list_comp *)((uint8_t *)(in_buffer + 32));
+
+ /* Add the last blocks as first gather component for tail fetch. */
+ if (tail_len) {
+ const uint8_t *output;
+
+ output = rte_pktmbuf_read(m_src, pkt_len - tail_len, tail_len, in_buffer);
+ if (output != in_buffer)
+ rte_memcpy(in_buffer, output, tail_len);
+ i = fill_sg2_comp(gather_comp, i, (uint64_t)in_buffer, tail_len);
+ }
+
i = fill_sg2_comp_from_pkt(gather_comp, i, m_src);
cpt_inst_w5.s.gather_sz = ((i + 2) / 3);
@@ -311,7 +339,7 @@ process_tls_read(struct rte_crypto_op *cop, struct cn10k_sec_session *sess,
inst->w5.u64 = cpt_inst_w5.u64;
inst->w6.u64 = cpt_inst_w6.u64;
w4.u64 = sess->inst.w4;
- w4.s.dlen = rte_pktmbuf_pkt_len(m_src);
+ w4.s.dlen = pkt_len + tail_len;
w4.s.param1 = w4.s.dlen;
w4.s.opcode_major &= (~(ROC_IE_OT_INPLACE_BIT));
inst->w4.u64 = w4.u64;
--
2.25.1
next prev parent reply other threads:[~2024-03-14 13:20 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-14 8:38 [PATCH 00/12] Add TLS features Vidya Sagar Velumuri
2024-03-14 8:38 ` [PATCH 01/12] crypto/cnxk: multi seg support block ciphers in tls Vidya Sagar Velumuri
2024-03-14 8:38 ` [PATCH 02/12] crypto/cnxk: enable sha384 capability for tls Vidya Sagar Velumuri
2024-03-14 8:38 ` [PATCH 03/12] crypto/cnxk: add support for session update for TLS Vidya Sagar Velumuri
2024-03-14 8:38 ` [PATCH 04/12] crypto/cnxk: avoid branches in datapath Vidya Sagar Velumuri
2024-03-14 8:38 ` [PATCH 05/12] crypto/cnxk: move metadata to second cacheline Vidya Sagar Velumuri
2024-03-14 8:38 ` [PATCH 06/12] crypto/cnxk: handle the extra len reported by microcode Vidya Sagar Velumuri
2024-03-14 8:38 ` [PATCH 07/12] crypto/cnxk: add support for padding verification in TLS Vidya Sagar Velumuri
2024-03-14 8:38 ` [PATCH 08/12] crypto/cnxk: add support for oop processing " Vidya Sagar Velumuri
2024-03-14 8:38 ` [PATCH 09/12] crypto/cnxk: update the context structure of tls Vidya Sagar Velumuri
2024-03-14 8:38 ` [PATCH 10/12] crypto/cnxk: use proper offset for context calculation Vidya Sagar Velumuri
2024-03-14 8:38 ` [PATCH 11/12] crypto/cnxk: enable chachapoly capability for tls Vidya Sagar Velumuri
2024-03-14 8:38 ` [PATCH 12/12] crypto/cnxk: remove the response len handling " Vidya Sagar Velumuri
2024-03-14 9:46 ` [PATCH 00/12] Add TLS features Anoob Joseph
2024-03-14 14:48 ` Patrick Robb
2024-03-14 13:18 ` [PATCH v2 0/8] crypto/cnxk: fixes and minor updates for TLS Vidya Sagar Velumuri
2024-03-15 5:42 ` [PATCH v3 0/8] Fixes and minor improvements for Crypto cnxk Vidya Sagar Velumuri
2024-03-15 5:42 ` [PATCH v3 1/8] crypto/cnxk: multi seg support block ciphers in tls Vidya Sagar Velumuri
2024-03-15 5:42 ` [PATCH v3 2/8] crypto/cnxk: enable sha384 and chachapoly for tls Vidya Sagar Velumuri
2024-03-15 5:42 ` [PATCH v3 3/8] crypto/cnxk: add support for session update for TLS Vidya Sagar Velumuri
2024-03-15 5:42 ` [PATCH v3 4/8] crypto/cnxk: avoid branches in datapath Vidya Sagar Velumuri
2024-03-15 5:42 ` [PATCH v3 5/8] crypto/cnxk: move metadata to second cacheline Vidya Sagar Velumuri
2024-03-15 5:42 ` [PATCH v3 6/8] crypto/cnxk: add support for padding verification in TLS Vidya Sagar Velumuri
2024-03-15 5:42 ` [PATCH v3 7/8] crypto/cnxk: add support for oop processing " Vidya Sagar Velumuri
2024-03-15 5:42 ` [PATCH v3 8/8] crypto/cnxk: update the context structure of tls Vidya Sagar Velumuri
2024-03-15 6:45 ` [PATCH v4 0/8] Fixes and minor improvements for Crypto cnxk Vidya Sagar Velumuri
2024-03-15 6:45 ` [PATCH v4 1/8] crypto/cnxk: multi seg support block ciphers in tls Vidya Sagar Velumuri
2024-03-15 6:45 ` [PATCH v4 2/8] crypto/cnxk: enable sha384 and chachapoly for tls Vidya Sagar Velumuri
2024-03-15 6:45 ` [PATCH v4 3/8] crypto/cnxk: add support for session update for TLS Vidya Sagar Velumuri
2024-03-15 6:45 ` [PATCH v4 4/8] crypto/cnxk: avoid branches in datapath Vidya Sagar Velumuri
2024-03-15 6:45 ` [PATCH v4 5/8] crypto/cnxk: move metadata to second cacheline Vidya Sagar Velumuri
2024-03-15 6:45 ` [PATCH v4 6/8] crypto/cnxk: add support for padding verification in TLS Vidya Sagar Velumuri
2024-03-15 6:45 ` [PATCH v4 7/8] crypto/cnxk: add support for oop processing " Vidya Sagar Velumuri
2024-03-15 6:45 ` [PATCH v4 8/8] crypto/cnxk: update the context structure of tls Vidya Sagar Velumuri
2024-03-15 11:40 ` [PATCH v4 0/8] Fixes and minor improvements for Crypto cnxk Akhil Goyal
2024-03-14 13:18 ` Vidya Sagar Velumuri [this message]
2024-03-14 13:18 ` [PATCH v2 2/8] crypto/cnxk: enable sha384 and chachapoly for tls Vidya Sagar Velumuri
2024-03-14 13:18 ` [PATCH v2 3/8] crypto/cnxk: add support for session update for TLS Vidya Sagar Velumuri
2024-03-14 13:18 ` [PATCH v2 4/8] crypto/cnxk: avoid branches in datapath Vidya Sagar Velumuri
2024-03-14 13:18 ` [PATCH v2 5/8] crypto/cnxk: move metadata to second cacheline Vidya Sagar Velumuri
2024-03-14 13:18 ` [PATCH v2 6/8] crypto/cnxk: add support for padding verification in TLS Vidya Sagar Velumuri
2024-03-14 13:18 ` [PATCH v2 7/8] crypto/cnxk: add support for oop processing " Vidya Sagar Velumuri
2024-03-14 13:18 ` [PATCH v2 8/8] crypto/cnxk: update the context structure of tls Vidya Sagar Velumuri
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