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From: Dengdui Huang <huangdengdui@huawei.com>
To: <dev@dpdk.org>
Cc: <ferruh.yigit@amd.com>, <aman.deep.singh@intel.com>,
	<yuying.zhang@intel.com>, <thomas@monjalon.net>,
	<andrew.rybchenko@oktetlabs.ru>,
	<damodharam.ammepalli@broadcom.com>, <stephen@networkplumber.org>,
	<jerinjacobk@gmail.com>, <ajit.khaparde@broadcom.com>,
	<liuyonglong@huawei.com>, <fengchengwen@huawei.com>,
	<haijie1@huawei.com>, <lihuisong@huawei.com>
Subject: [PATCH v2 3/6] ethdev: add function to parse link mode info
Date: Fri, 22 Mar 2024 15:09:20 +0800	[thread overview]
Message-ID: <20240322070923.244417-4-huangdengdui@huawei.com> (raw)
In-Reply-To: <20240322070923.244417-1-huangdengdui@huawei.com>

Added function rte_eth_link_mode_parse() to parse
the speed number, lanes and duplex parameters
from the Link speed apabilities bitmap flags.

Signed-off-by: Dengdui Huang <huangdengdui@huawei.com>
---
 doc/guides/rel_notes/release_24_03.rst |   3 +
 lib/ethdev/rte_ethdev.c                | 199 +++++++++++++++++++++++++
 lib/ethdev/rte_ethdev.h                |  29 ++++
 lib/ethdev/version.map                 |   1 +
 4 files changed, 232 insertions(+)

diff --git a/doc/guides/rel_notes/release_24_03.rst b/doc/guides/rel_notes/release_24_03.rst
index 4621689c68..b41b0028b2 100644
--- a/doc/guides/rel_notes/release_24_03.rst
+++ b/doc/guides/rel_notes/release_24_03.rst
@@ -78,6 +78,9 @@ New Features
 
 * **Support setting lanes for ethdev.**
   * Support setting lanes by extended ``RTE_ETH_LINK_SPEED_*``.
+  * Added function to parse the speed number, lanes and duplex parameters from
+  * the Link speed apabilities bitmap flags:
+  ``rte_eth_link_mode_parse()``
 
 * **Added hash calculation of an encapsulated packet as done by the HW.**
 
diff --git a/lib/ethdev/rte_ethdev.c b/lib/ethdev/rte_ethdev.c
index 6571116fbf..bac7c652be 100644
--- a/lib/ethdev/rte_ethdev.c
+++ b/lib/ethdev/rte_ethdev.c
@@ -1105,6 +1105,205 @@ rte_eth_dev_rx_offload_name(uint64_t offload)
 	return name;
 }
 
+int
+rte_eth_link_mode_parse(uint32_t link_speed,
+			struct rte_eth_link_mode_info *mode_onfo)
+{
+	const struct {
+		uint32_t speed_capa;
+		struct rte_eth_link_mode_info mode_onfo;
+	} speed_mode_onfo_map[] = {
+		{
+			RTE_ETH_LINK_SPEED_10M_HD,
+				{
+					RTE_ETH_SPEED_NUM_10M,
+					RTE_ETH_LANES_1,
+					RTE_ETH_LINK_HALF_DUPLEX
+				}
+		},
+		{
+			RTE_ETH_LINK_SPEED_10M,
+				{
+					RTE_ETH_SPEED_NUM_10M,
+					RTE_ETH_LANES_1,
+					RTE_ETH_LINK_FULL_DUPLEX
+				}
+		},
+		{
+			RTE_ETH_LINK_SPEED_100M_HD,
+				{
+					RTE_ETH_SPEED_NUM_100M,
+					RTE_ETH_LANES_1,
+					RTE_ETH_LINK_HALF_DUPLEX
+				}
+		},
+		{
+			RTE_ETH_LINK_SPEED_100M,
+				{
+					RTE_ETH_SPEED_NUM_100M,
+					RTE_ETH_LANES_1,
+					RTE_ETH_LINK_FULL_DUPLEX
+				}
+		},
+		{
+			RTE_ETH_LINK_SPEED_1G,
+				{
+					RTE_ETH_SPEED_NUM_1G,
+					RTE_ETH_LANES_1,
+					RTE_ETH_LINK_FULL_DUPLEX
+				}
+		},
+		{
+			RTE_ETH_LINK_SPEED_2_5G,
+				{
+					RTE_ETH_SPEED_NUM_2_5G,
+					RTE_ETH_LANES_1,
+					RTE_ETH_LINK_FULL_DUPLEX
+				}
+		},
+		{
+			RTE_ETH_LINK_SPEED_5G,
+				{
+					RTE_ETH_SPEED_NUM_5G,
+					RTE_ETH_LANES_1,
+					RTE_ETH_LINK_FULL_DUPLEX
+				}
+		},
+		{
+			RTE_ETH_LINK_SPEED_10G,
+				{
+					RTE_ETH_SPEED_NUM_10G,
+					RTE_ETH_LANES_1,
+					RTE_ETH_LINK_FULL_DUPLEX
+				}
+		},
+		{
+			RTE_ETH_LINK_SPEED_20G_2LANES,
+				{
+					RTE_ETH_SPEED_NUM_20G,
+					RTE_ETH_LANES_2,
+					RTE_ETH_LINK_FULL_DUPLEX
+				}
+		},
+		{
+			RTE_ETH_LINK_SPEED_25G,
+				{
+					RTE_ETH_SPEED_NUM_25G,
+					RTE_ETH_LANES_1,
+					RTE_ETH_LINK_FULL_DUPLEX
+				}
+		},
+		{
+			RTE_ETH_LINK_SPEED_40G_4LANES,
+				{
+					RTE_ETH_SPEED_NUM_40G,
+					RTE_ETH_LANES_4,
+					RTE_ETH_LINK_FULL_DUPLEX
+				}
+		},
+		{
+			RTE_ETH_LINK_SPEED_50G,
+				{
+					RTE_ETH_SPEED_NUM_50G,
+					RTE_ETH_LANES_1,
+					RTE_ETH_LINK_FULL_DUPLEX
+				}
+		},
+		{
+			RTE_ETH_LINK_SPEED_56G_4LANES,
+				{
+					RTE_ETH_SPEED_NUM_56G,
+					RTE_ETH_LANES_4,
+					RTE_ETH_LINK_FULL_DUPLEX
+				}
+		},
+		{
+			RTE_ETH_LINK_SPEED_100G,
+				{
+					RTE_ETH_SPEED_NUM_100G,
+					RTE_ETH_LANES_1,
+					RTE_ETH_LINK_FULL_DUPLEX
+				}
+		},
+		{
+			RTE_ETH_LINK_SPEED_200G_4LANES,
+				{
+					RTE_ETH_SPEED_NUM_200G,
+					RTE_ETH_LANES_4,
+					RTE_ETH_LINK_FULL_DUPLEX
+				}
+		},
+		{
+			RTE_ETH_LINK_SPEED_400G_4LANES,
+				{
+					RTE_ETH_SPEED_NUM_400G,
+					RTE_ETH_LANES_4,
+					RTE_ETH_LINK_FULL_DUPLEX
+				}
+		},
+		{
+			RTE_ETH_LINK_SPEED_10G_4LANES,
+				{
+					RTE_ETH_SPEED_NUM_10G,
+					RTE_ETH_LANES_4,
+					RTE_ETH_LINK_FULL_DUPLEX
+				}
+		},
+		{
+			RTE_ETH_LINK_SPEED_50G_2LANES,
+				{
+					RTE_ETH_SPEED_NUM_50G,
+					RTE_ETH_LANES_2,
+					RTE_ETH_LINK_FULL_DUPLEX
+				}
+		},
+		{
+			RTE_ETH_LINK_SPEED_100G_2LANES,
+				{
+					RTE_ETH_SPEED_NUM_100G,
+					RTE_ETH_LANES_2,
+					RTE_ETH_LINK_FULL_DUPLEX
+				}
+		},
+		{
+			RTE_ETH_LINK_SPEED_100G_4LANES,
+				{
+					RTE_ETH_SPEED_NUM_100G,
+					RTE_ETH_LANES_4,
+					RTE_ETH_LINK_FULL_DUPLEX
+				}
+		},
+		{
+			RTE_ETH_LINK_SPEED_200G_2LANES,
+				{
+					RTE_ETH_SPEED_NUM_200G,
+					RTE_ETH_LANES_2,
+					RTE_ETH_LINK_FULL_DUPLEX
+				}
+		},
+		{
+			RTE_ETH_LINK_SPEED_400G_8LANES,
+				{
+					RTE_ETH_SPEED_NUM_400G,
+					RTE_ETH_LANES_8,
+					RTE_ETH_LINK_FULL_DUPLEX
+				}
+		}
+	};
+	uint32_t i;
+
+	for (i = 0; i < RTE_DIM(speed_mode_onfo_map); i++) {
+		if (link_speed == speed_mode_onfo_map[i].speed_capa) {
+			mode_onfo->speed_num = speed_mode_onfo_map[i].mode_onfo.speed_num;
+			mode_onfo->lanes = speed_mode_onfo_map[i].mode_onfo.lanes;
+			mode_onfo->duplex = speed_mode_onfo_map[i].mode_onfo.duplex;
+			return 0;
+		}
+	}
+
+	return -EINVAL;
+}
+
 const char *
 rte_eth_dev_tx_offload_name(uint64_t offload)
 {
diff --git a/lib/ethdev/rte_ethdev.h b/lib/ethdev/rte_ethdev.h
index 123b771046..b7aacf6da8 100644
--- a/lib/ethdev/rte_ethdev.h
+++ b/lib/ethdev/rte_ethdev.h
@@ -355,6 +355,15 @@ struct rte_eth_stats {
 #define RTE_ETH_LANES_8          8 /**< 8 lanes */
 /**@}*/
 
+/**
+ * A structure used to store information of link mode.
+ */
+struct rte_eth_link_mode_info {
+	uint32_t speed_num;        /**< RTE_ETH_SPEED_NUM_ */
+	uint8_t  lanes;        /**< RTE_ETH_LANES_ */
+	uint8_t  duplex;       /**< RTE_ETH_LINK_[HALF/FULL]_DUPLEX */
+};
+
 /**
  * A structure used to retrieve link-level information of an Ethernet port.
  */
@@ -2345,6 +2354,26 @@ uint16_t rte_eth_dev_count_total(void);
  */
 uint32_t rte_eth_speed_bitflag(uint32_t speed, uint8_t lanes, int duplex);
 
+/**
+ * @warning
+ * @b EXPERIMENTAL: this API may change, or be removed, without prior notice
+ *
+ * Parse the speed number, lanes and duplex parameters from the Link speed
+ * capabilities bitmap flags.
+ *
+ * @param link_speed
+ *   speed capabilities bitmap flag (RTE_ETH_LINK_SPEED_)
+ * @param mode_onfo
+ *   A pointer to a structure of type *rte_eth_link_mode_info* to be filled
+ *   with the information of link mode.
+ * @return
+ *   - (0) if successful.
+ *   - (-EINVAL) if bad parameter.
+ */
+__rte_experimental
+int rte_eth_link_mode_parse(uint32_t link_speed,
+			    struct rte_eth_link_mode_info *mode_info);
+
 /**
  * Get RTE_ETH_RX_OFFLOAD_* flag name.
  *
diff --git a/lib/ethdev/version.map b/lib/ethdev/version.map
index 9fa2439976..5726498dd1 100644
--- a/lib/ethdev/version.map
+++ b/lib/ethdev/version.map
@@ -326,6 +326,7 @@ EXPERIMENTAL {
 	# added in 24.03
 	__rte_eth_trace_tx_queue_count;
 	rte_eth_find_rss_algo;
+	rte_eth_link_mode_parse;
 	rte_flow_async_update_resized;
 	rte_flow_calc_encap_hash;
 	rte_flow_template_table_resizable;
-- 
2.33.0


  parent reply	other threads:[~2024-03-22  7:09 UTC|newest]

Thread overview: 51+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-03-12  7:52 [PATCH 0/3] support setting lanes Dengdui Huang
2024-03-12  7:52 ` [PATCH 1/3] ethdev: " Dengdui Huang
2024-03-19  3:02   ` Stephen Hemminger
2024-03-20  1:16     ` huangdengdui
2024-03-12  7:52 ` [PATCH 2/3] net/hns3: " Dengdui Huang
2024-03-12  7:52 ` [PATCH 3/3] app/testpmd: " Dengdui Huang
2024-03-15 21:47   ` Damodharam Ammepalli
2024-03-19  2:38     ` huangdengdui
2024-03-22  7:09   ` [PATCH v2 0/6] " Dengdui Huang
2024-03-22  7:09     ` [PATCH v2 1/6] ethdev: " Dengdui Huang
2024-03-22 13:58       ` Thomas Monjalon
2024-03-22 15:15         ` Ajit Khaparde
2024-03-22 17:32           ` Tyler Retzlaff
2024-03-22 22:30             ` Damodharam Ammepalli
2024-03-25  6:24         ` huangdengdui
2024-03-25  9:30           ` Thomas Monjalon
2024-03-25 21:14             ` Damodharam Ammepalli
2024-03-26  1:42             ` lihuisong (C)
2024-03-26  3:45               ` Ajit Khaparde
2024-03-26 10:30               ` Thomas Monjalon
2024-03-26 11:15                 ` lihuisong (C)
2024-03-26 13:47                   ` Ajit Khaparde
2024-03-26 18:11                     ` Ajit Khaparde
2024-03-26 18:21                       ` Damodharam Ammepalli
2024-03-30 11:38                         ` huangdengdui
2024-04-01 20:07                           ` Thomas Monjalon
2024-04-01 22:29                             ` Damodharam Ammepalli
2024-04-02  8:37                             ` huangdengdui
2024-04-02 15:28                               ` Stephen Hemminger
2024-04-04 13:45                               ` Ferruh Yigit
2024-03-29  3:25                     ` lihuisong (C)
2024-03-22  7:09     ` [PATCH v2 2/6] test: updated UT for " Dengdui Huang
2024-03-22  7:09     ` Dengdui Huang [this message]
2024-03-22  7:09     ` [PATCH v2 4/6] net/hns3: use parse link mode info function Dengdui Huang
2024-03-22  7:09     ` [PATCH v2 5/6] net/hns3: support setting lanes Dengdui Huang
2024-03-22  7:09     ` [PATCH v2 6/6] app/testpmd: " Dengdui Huang
2024-04-04 13:58     ` [PATCH v2 0/6] " Ferruh Yigit
2024-03-18 14:56 ` [PATCH 0/3] " Thomas Monjalon
2024-03-18 21:26   ` Damodharam Ammepalli
2024-03-18 21:42     ` Stephen Hemminger
2024-03-18 22:55       ` Ajit Khaparde
2024-03-20 11:41     ` Thomas Monjalon
2024-03-20 12:31     ` Ferruh Yigit
2024-03-21  2:02       ` huangdengdui
2024-03-21  8:28         ` Thomas Monjalon
2024-03-22  2:28           ` huangdengdui
2024-03-22  4:38             ` Jerin Jacob
2024-03-22  5:25               ` Ajit Khaparde
2024-03-22  5:51                 ` Jerin Jacob
2024-03-22 13:51                   ` Thomas Monjalon
2024-03-25 14:04                     ` Jerin Jacob

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