From: Chengwen Feng <fengchengwen@huawei.com>
To: <thomas@monjalon.net>, <dev@dpdk.org>
Subject: [PATCH] dma/hisilicon: remove support for HIP09 platform
Date: Wed, 8 May 2024 08:29:44 +0000 [thread overview]
Message-ID: <20240508082944.24564-1-fengchengwen@huawei.com> (raw)
The DMA for HIP09 is no longer available, so delete it.
Cc: stable@dpdk.org
Signed-off-by: Chengwen Feng <fengchengwen@huawei.com>
---
doc/guides/dmadevs/hisilicon.rst | 1 -
doc/guides/rel_notes/release_24_07.rst | 2 ++
drivers/dma/hisilicon/hisi_dmadev.c | 40 +-------------------------
drivers/dma/hisilicon/hisi_dmadev.h | 35 +---------------------
4 files changed, 4 insertions(+), 74 deletions(-)
diff --git a/doc/guides/dmadevs/hisilicon.rst b/doc/guides/dmadevs/hisilicon.rst
index 8c1f0f8886..974bc49376 100644
--- a/doc/guides/dmadevs/hisilicon.rst
+++ b/doc/guides/dmadevs/hisilicon.rst
@@ -13,7 +13,6 @@ Supported Kunpeng SoCs
----------------------
* Kunpeng 920
-* Kunpeng 930
Device Setup
diff --git a/doc/guides/rel_notes/release_24_07.rst b/doc/guides/rel_notes/release_24_07.rst
index a69f24cf99..4b27e5dbe8 100644
--- a/doc/guides/rel_notes/release_24_07.rst
+++ b/doc/guides/rel_notes/release_24_07.rst
@@ -68,6 +68,8 @@ Removed Items
Also, make sure to start the actual text at the margin.
=======================================================
+* dma/hisilicon: remove support for HIP09 platform
+
API Changes
-----------
diff --git a/drivers/dma/hisilicon/hisi_dmadev.c b/drivers/dma/hisilicon/hisi_dmadev.c
index 22303e7bef..067c9513f6 100644
--- a/drivers/dma/hisilicon/hisi_dmadev.c
+++ b/drivers/dma/hisilicon/hisi_dmadev.c
@@ -39,8 +39,6 @@ hisi_dma_queue_base(struct hisi_dma_dev *hw)
{
if (hw->reg_layout == HISI_DMA_REG_LAYOUT_HIP08)
return HISI_DMA_HIP08_QUEUE_BASE;
- else if (hw->reg_layout == HISI_DMA_REG_LAYOUT_HIP09)
- return HISI_DMA_HIP09_QUEUE_BASE;
else
return 0;
}
@@ -216,25 +214,6 @@ hisi_dma_init_hw(struct hisi_dma_dev *hw)
HISI_DMA_HIP08_QUEUE_INT_MASK_M, true);
hisi_dma_update_queue_mbit(hw, HISI_DMA_QUEUE_INT_MASK_REG,
HISI_DMA_HIP08_QUEUE_INT_MASK_M, true);
- } else if (hw->reg_layout == HISI_DMA_REG_LAYOUT_HIP09) {
- hisi_dma_update_queue_mbit(hw, HISI_DMA_QUEUE_CTRL0_REG,
- HISI_DMA_HIP09_QUEUE_CTRL0_ERR_ABORT_M, false);
- hisi_dma_update_queue_mbit(hw, HISI_DMA_QUEUE_INT_STATUS_REG,
- HISI_DMA_HIP09_QUEUE_INT_MASK_M, true);
- hisi_dma_update_queue_mbit(hw, HISI_DMA_QUEUE_INT_MASK_REG,
- HISI_DMA_HIP09_QUEUE_INT_MASK_M, true);
- hisi_dma_update_queue_mbit(hw,
- HISI_DMA_HIP09_QUEUE_ERR_INT_STATUS_REG,
- HISI_DMA_HIP09_QUEUE_ERR_INT_MASK_M, true);
- hisi_dma_update_queue_mbit(hw,
- HISI_DMA_HIP09_QUEUE_ERR_INT_MASK_REG,
- HISI_DMA_HIP09_QUEUE_ERR_INT_MASK_M, true);
- hisi_dma_update_queue_bit(hw, HISI_DMA_QUEUE_CTRL1_REG,
- HISI_DMA_HIP09_QUEUE_CTRL1_VA_ENABLE_B, true);
- hisi_dma_update_bit(hw,
- HISI_DMA_HIP09_QUEUE_CFG_REG(hw->queue_id),
- HISI_DMA_HIP09_QUEUE_CFG_LINK_DOWN_MASK_B,
- true);
}
}
@@ -256,8 +235,6 @@ hisi_dma_reg_layout(uint8_t revision)
{
if (revision == HISI_DMA_REVISION_HIP08B)
return HISI_DMA_REG_LAYOUT_HIP08;
- else if (revision >= HISI_DMA_REVISION_HIP09A)
- return HISI_DMA_REG_LAYOUT_HIP09;
else
return HISI_DMA_REG_LAYOUT_INVALID;
}
@@ -328,14 +305,11 @@ hisi_dma_info_get(const struct rte_dma_dev *dev,
struct rte_dma_info *dev_info,
uint32_t info_sz)
{
- struct hisi_dma_dev *hw = dev->data->dev_private;
+ RTE_SET_USED(dev);
RTE_SET_USED(info_sz);
dev_info->dev_capa = RTE_DMA_CAPA_MEM_TO_MEM |
RTE_DMA_CAPA_OPS_COPY;
- if (hw->reg_layout == HISI_DMA_REG_LAYOUT_HIP09)
- dev_info->dev_capa |= RTE_DMA_CAPA_HANDLES_ERRORS;
-
dev_info->max_vchans = 1;
dev_info->max_desc = HISI_DMA_MAX_DESC_NUM;
dev_info->min_desc = HISI_DMA_MIN_DESC_NUM;
@@ -514,18 +488,6 @@ hisi_dma_dump_common(struct hisi_dma_dev *hw, FILE *f)
{ HISI_DMA_REG_LAYOUT_HIP08,
HISI_DMA_HIP08_DUMP_START_REG,
HISI_DMA_HIP08_DUMP_END_REG },
- { HISI_DMA_REG_LAYOUT_HIP09,
- HISI_DMA_HIP09_DUMP_REGION_A_START_REG,
- HISI_DMA_HIP09_DUMP_REGION_A_END_REG },
- { HISI_DMA_REG_LAYOUT_HIP09,
- HISI_DMA_HIP09_DUMP_REGION_B_START_REG,
- HISI_DMA_HIP09_DUMP_REGION_B_END_REG },
- { HISI_DMA_REG_LAYOUT_HIP09,
- HISI_DMA_HIP09_DUMP_REGION_C_START_REG,
- HISI_DMA_HIP09_DUMP_REGION_C_END_REG },
- { HISI_DMA_REG_LAYOUT_HIP09,
- HISI_DMA_HIP09_DUMP_REGION_D_START_REG,
- HISI_DMA_HIP09_DUMP_REGION_D_END_REG },
};
uint32_t i;
diff --git a/drivers/dma/hisilicon/hisi_dmadev.h b/drivers/dma/hisilicon/hisi_dmadev.h
index 5a17f9f69e..a57b5c759a 100644
--- a/drivers/dma/hisilicon/hisi_dmadev.h
+++ b/drivers/dma/hisilicon/hisi_dmadev.h
@@ -25,22 +25,14 @@
#define HISI_DMA_DEVICE_ID 0xA122
#define HISI_DMA_PCI_REVISION_ID_REG 0x08
#define HISI_DMA_REVISION_HIP08B 0x21
-#define HISI_DMA_REVISION_HIP09A 0x30
#define HISI_DMA_MAX_HW_QUEUES 4
#define HISI_DMA_MAX_DESC_NUM 8192
#define HISI_DMA_MIN_DESC_NUM 32
-/**
- * The HIP08B(HiSilicon IP08) and HIP09B(HiSilicon IP09) are DMA iEPs, they
- * have the same pci device id but different pci revision.
- * Unfortunately, they have different register layouts, so two layout
- * enumerations are defined.
- */
enum {
HISI_DMA_REG_LAYOUT_INVALID = 0,
- HISI_DMA_REG_LAYOUT_HIP08,
- HISI_DMA_REG_LAYOUT_HIP09
+ HISI_DMA_REG_LAYOUT_HIP08
};
/**
@@ -69,9 +61,6 @@ enum {
* length of queue-region. The global offset for a single queue register is
* calculated by:
* offset = queue-base + (queue-id * queue-region) + reg-offset-in-region.
- *
- * The first part of queue region is basically the same for HIP08 and HIP09
- * register layouts, therefore, HISI_QUEUE_* registers are defined for it.
*/
#define HISI_DMA_QUEUE_SQ_BASE_L_REG 0x0
#define HISI_DMA_QUEUE_SQ_BASE_H_REG 0x4
@@ -110,28 +99,6 @@ enum {
#define HISI_DMA_HIP08_DUMP_START_REG 0x2000
#define HISI_DMA_HIP08_DUMP_END_REG 0x2280
-/**
- * HiSilicon IP09 DMA register and field define:
- */
-#define HISI_DMA_HIP09_QUEUE_BASE 0x2000
-#define HISI_DMA_HIP09_QUEUE_CTRL0_ERR_ABORT_M GENMASK(31, 28)
-#define HISI_DMA_HIP09_QUEUE_CTRL1_VA_ENABLE_B 2
-#define HISI_DMA_HIP09_QUEUE_INT_MASK_M 0x1
-#define HISI_DMA_HIP09_QUEUE_ERR_INT_STATUS_REG 0x48
-#define HISI_DMA_HIP09_QUEUE_ERR_INT_MASK_REG 0x4C
-#define HISI_DMA_HIP09_QUEUE_ERR_INT_MASK_M GENMASK(18, 1)
-#define HISI_DMA_HIP09_QUEUE_CFG_REG(queue_id) (0x800 + \
- (queue_id) * 0x20)
-#define HISI_DMA_HIP09_QUEUE_CFG_LINK_DOWN_MASK_B 16
-#define HISI_DMA_HIP09_DUMP_REGION_A_START_REG 0x0
-#define HISI_DMA_HIP09_DUMP_REGION_A_END_REG 0x368
-#define HISI_DMA_HIP09_DUMP_REGION_B_START_REG 0x800
-#define HISI_DMA_HIP09_DUMP_REGION_B_END_REG 0xA08
-#define HISI_DMA_HIP09_DUMP_REGION_C_START_REG 0x1800
-#define HISI_DMA_HIP09_DUMP_REGION_C_END_REG 0x1A4C
-#define HISI_DMA_HIP09_DUMP_REGION_D_START_REG 0x1C00
-#define HISI_DMA_HIP09_DUMP_REGION_D_END_REG 0x1CC4
-
/**
* In fact, there are multiple states, but it need to pay attention to
* the following three states for the driver:
--
2.17.1
reply other threads:[~2024-05-08 8:32 UTC|newest]
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