From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 097BE4401F; Tue, 14 May 2024 17:39:03 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B24624067E; Tue, 14 May 2024 17:38:58 +0200 (CEST) Received: from mail-pl1-f176.google.com (mail-pl1-f176.google.com [209.85.214.176]) by mails.dpdk.org (Postfix) with ESMTP id 36FA240156 for ; Tue, 14 May 2024 17:38:57 +0200 (CEST) Received: by mail-pl1-f176.google.com with SMTP id d9443c01a7336-1ec41d82b8bso54310655ad.2 for ; Tue, 14 May 2024 08:38:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=networkplumber-org.20230601.gappssmtp.com; s=20230601; t=1715701136; x=1716305936; darn=dpdk.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yudQh+9cAzAvlmI5mUHDk5m+pZwFbqBbRBe/82Qf28c=; b=Pv8nZhpByRcVU6PD6rGWZWkqgT2Wtm6f4FKp3vGdbGzJD/E6d3cWPE4443HlTHJW92 LxIYqzGmtWWY0U39QXYOTFvv3/+1lhheDbqkc15cj/e48GbI1LoeT+ivIvI1LX5OwNfM YZhyK9ewahlm8c3zl5ygdxrs52QBS32M0AGXHHQr2hAZOIEC2VJNonjoxJ8lsnxa9yfs NDk4AU5iLkAlLqAfVu0Y6WEMvkmfvH+m9ZrXjO8uNv+tqCAES41yu2HUriFuW166iqjO CeswsuSMJtufXyrcyAe7UEfpN1/Ctm811+sHyeuGVlhrQkIeuKCj2qSLE9VaIBa3s8nQ 587w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715701136; x=1716305936; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yudQh+9cAzAvlmI5mUHDk5m+pZwFbqBbRBe/82Qf28c=; b=R9qvt6sNdd9YQYLaU9ZaSFqBi85obMFtsU0nE2Audv0CHxRhbIw9tsZXu9IdlVXae0 lIQDJDtK2/Hmh+gTZ/woWqUHevnvZemH77Tru3LQQCjHqT7IDZAFYm4dfxKLlPpQP19E RF355QcCCv+HemNIU0VwF6MIp3+JFOlhorEDGbCmXTCo+1PqohOrvLujNYHeiUQb+v2e JUcCIDtf+tnIXpvwH02VGCt2iyG1jMIC1P975/qhQ7kPMyK2hVk8odMSHO6iwbKsxuG2 wrqFEppPZjr+yjZwpsnyrnNEXUvj5lo3HMPQEgtBAHlV8/2yDEmbmlGJ36ioNNHWm4do niGw== X-Gm-Message-State: AOJu0YyYM+WhYmkYw5FivYs2Xr8K2626Jo1m5QjnA87eM73xFBHDHGKn PXeVyVjF0dz4mJ1TnNeO0ATIT0T40LRhGYoXXt21vqWu4Hk6gu1NiuHCSaBms0eWBfs/M/hCCfA IeLY= X-Google-Smtp-Source: AGHT+IG1FoCf4q/qEmo+oIN6DbS/1PEa6WyKDSKXGB2AscTzaC7+4rUEW4p3BoVL3K2WpgbuEDR3Kg== X-Received: by 2002:a17:902:6bcb:b0:1e4:c75e:aae2 with SMTP id d9443c01a7336-1ef4404fbc3mr139139685ad.59.1715701136379; Tue, 14 May 2024 08:38:56 -0700 (PDT) Received: from hermes.local (204-195-96-226.wavecable.com. [204.195.96.226]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1ef0c137f14sm99256415ad.259.2024.05.14.08.38.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 May 2024 08:38:56 -0700 (PDT) From: Stephen Hemminger To: dev@dpdk.org Cc: Stephen Hemminger , =?UTF-8?q?Morten=20Br=C3=B8rup?= Subject: [PATCH v3 1/7] eal: generic 64 bit counter Date: Tue, 14 May 2024 08:35:04 -0700 Message-ID: <20240514153845.42489-2-stephen@networkplumber.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240514153845.42489-1-stephen@networkplumber.org> References: <20240510050507.14381-1-stephen@networkplumber.org> <20240514153845.42489-1-stephen@networkplumber.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This header implements 64 bit counters that are NOT atomic but are safe against load/store splits on 32 bit platforms. Signed-off-by: Stephen Hemminger Acked-by: Morten Brørup --- lib/eal/include/meson.build | 1 + lib/eal/include/rte_counter.h | 91 +++++++++++++++++++++++++++++++++++ 2 files changed, 92 insertions(+) create mode 100644 lib/eal/include/rte_counter.h diff --git a/lib/eal/include/meson.build b/lib/eal/include/meson.build index e94b056d46..c070dd0079 100644 --- a/lib/eal/include/meson.build +++ b/lib/eal/include/meson.build @@ -12,6 +12,7 @@ headers += files( 'rte_class.h', 'rte_common.h', 'rte_compat.h', + 'rte_counter.h', 'rte_debug.h', 'rte_dev.h', 'rte_devargs.h', diff --git a/lib/eal/include/rte_counter.h b/lib/eal/include/rte_counter.h new file mode 100644 index 0000000000..8068d6d26e --- /dev/null +++ b/lib/eal/include/rte_counter.h @@ -0,0 +1,91 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (c) Stephen Hemminger + */ + +#ifndef _RTE_COUNTER_H_ +#define _RTE_COUNTER_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @file + * RTE Counter + * + * A counter is 64 bit value that is safe from split read/write + * on 32 bit platforms. It assumes that only one cpu at a time + * will update the counter, and another CPU may want to read it. + * + * This is a much weaker guarantee than full atomic variables + * but is faster since no locked operations are required for update. + */ + +#include + +#ifdef RTE_ARCH_64 +/* + * On a platform that can support native 64 bit type, no special handling. + * These are just wrapper around 64 bit value. + */ +typedef uint64_t rte_counter64_t; + +/** + * Add value to counter. + */ +__rte_experimental +static inline void +rte_counter64_add(rte_counter64_t *counter, uint32_t val) +{ + *counter += val; +} + +__rte_experimental +static inline uint64_t +rte_counter64_fetch(const rte_counter64_t *counter) +{ + return *counter; +} + +__rte_experimental +static inline void +rte_counter64_reset(rte_counter64_t *counter) +{ + *counter = 0; +} + +#else +/* + * On a 32 bit platform need to use atomic to force the compler to not + * split 64 bit read/write. + */ +typedef RTE_ATOMIC(uint64_t) rte_counter64_t; + +__rte_experimental +static inline void +rte_counter64_add(rte_counter64_t *counter, uint32_t val) +{ + rte_atomic_fetch_add_explicit(counter, val, rte_memory_order_relaxed); +} + +__rte_experimental +static inline uint64_t +rte_counter64_fetch(const rte_counter64_t *counter) +{ + return rte_atomic_load_explicit(counter, rte_memory_order_relaxed); +} + +__rte_experimental +static inline void +rte_counter64_reset(rte_counter64_t *counter) +{ + rte_atomic_store_explicit(counter, 0, rte_memory_order_relaxed); +} +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_COUNTER_H_ */ -- 2.43.0