From mboxrd@z Thu Jan  1 00:00:00 1970
Return-Path: <dev-bounces@dpdk.org>
Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124])
	by inbox.dpdk.org (Postfix) with ESMTP id 5EA8F43F81;
	Thu, 16 May 2024 17:43:46 +0200 (CEST)
Received: from mails.dpdk.org (localhost [127.0.0.1])
	by mails.dpdk.org (Postfix) with ESMTP id 59D2B40648;
	Thu, 16 May 2024 17:43:41 +0200 (CEST)
Received: from mail-pf1-f171.google.com (mail-pf1-f171.google.com
 [209.85.210.171])
 by mails.dpdk.org (Postfix) with ESMTP id 4CE644029B
 for <dev@dpdk.org>; Thu, 16 May 2024 17:43:39 +0200 (CEST)
Received: by mail-pf1-f171.google.com with SMTP id
 d2e1a72fcca58-6f4302187c0so276841b3a.1
 for <dev@dpdk.org>; Thu, 16 May 2024 08:43:39 -0700 (PDT)
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
 d=networkplumber-org.20230601.gappssmtp.com; s=20230601; t=1715874218;
 x=1716479018; darn=dpdk.org; 
 h=content-transfer-encoding:mime-version:references:in-reply-to
 :message-id:date:subject:cc:to:from:from:to:cc:subject:date
 :message-id:reply-to;
 bh=it8vQ7zCnyKycuWg3oTjgKRI/75M1tfp8aWkSfvtLSE=;
 b=e4NCYv9m1ZYc/Fc6023a4HyX6Hv090gMh2Gj0+KPI7wbiVnIJJT3gr0L0hwPaAqaRI
 5Ik0Bu6Yd8SK6kQL2UF9IT7Zm8P2+R6amSAdeBo9faayL3fXNJMPO25dWFZwMGZf/eKj
 aPGW7l+DX07PHMpyo67N3JxM3G0muuv5r2UwVNOi2ZlCqIwOikRyBr6lmPCtogUmUYsd
 0KY0+Em6wB5slEqH6Kt6xOid913clrUBzPnySntzrshn1go3YmTl+5d9P1+2b+NnuGPP
 gNJo3hUAgv21dv6MgIupYfhX0fPDjy7OffAS0kXH9gFjbE5NRagP9WBoMkVvWyFgZYvq
 Xslg==
X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
 d=1e100.net; s=20230601; t=1715874218; x=1716479018;
 h=content-transfer-encoding:mime-version:references:in-reply-to
 :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc
 :subject:date:message-id:reply-to;
 bh=it8vQ7zCnyKycuWg3oTjgKRI/75M1tfp8aWkSfvtLSE=;
 b=qRwIbrBpqNMbFFMHvv8VeKnJrZXdy15NVkQLqfjaNF9KtNubb6oZr4VSzDGQM5bIq4
 uXK24aRft390TE5PCfipziepuRaR8D1LGje0H41f/4wo81I0ENctEuFO1yXfcxK9gUf/
 GhQmAEz8sL744Y6wQyUikrrKdfftszbbdnT8GUcN8SmSwzTLqPPn7ivzde9/iggx9U93
 qgYhXLsdWfUQ5X9xGeC/K5vMl3WVYGysFbxheY+jM9qoH7S+sKt4WRh8LZDEm6k5AMe/
 n5jnpPSDEccvMD16WJWMR8cindOdBpEdZIgcKOBDyUSMzhopHbhkvBWaYIYrUIzctoOH
 NX7w==
X-Gm-Message-State: AOJu0YwHIaEluKp9uVjZeUMUwSQ1EeBKhLNb+VXiZvFOhEef6c6/waYb
 +NwU1JRGHoiWneHRLexfOM39jGLOncUDy/zlxIBEBXoBuQaq43M9oiyZdzaS1LJUNPwSdcpNC2T
 bI9E=
X-Google-Smtp-Source: AGHT+IG7rVyDzEPCy2qVapPmsbepGzxroyiyqllB2pgKkUHiIEhQPtvXy/9pU0ZHSSNMPEAYCjwY8A==
X-Received: by 2002:a05:6a20:728d:b0:1a9:509c:eba6 with SMTP id
 adf61e73a8af0-1afde1c043fmr29486532637.25.1715874218392; 
 Thu, 16 May 2024 08:43:38 -0700 (PDT)
Received: from hermes.local (204-195-96-226.wavecable.com. [204.195.96.226])
 by smtp.gmail.com with ESMTPSA id
 d2e1a72fcca58-6f67b526b44sm2457430b3a.149.2024.05.16.08.43.37
 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);
 Thu, 16 May 2024 08:43:37 -0700 (PDT)
From: Stephen Hemminger <stephen@networkplumber.org>
To: dev@dpdk.org
Cc: Stephen Hemminger <stephen@networkplumber.org>,
 =?UTF-8?q?Morten=20Br=C3=B8rup?= <mb@smartsharesystems.com>
Subject: [PATCH v5 1/9] eal: generic 64 bit counter
Date: Thu, 16 May 2024 08:40:37 -0700
Message-ID: <20240516154327.64104-2-stephen@networkplumber.org>
X-Mailer: git-send-email 2.43.0
In-Reply-To: <20240516154327.64104-1-stephen@networkplumber.org>
References: <20240510050507.14381-1-stephen@networkplumber.org>
 <20240516154327.64104-1-stephen@networkplumber.org>
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
X-BeenThere: dev@dpdk.org
X-Mailman-Version: 2.1.29
Precedence: list
List-Id: DPDK patches and discussions <dev.dpdk.org>
List-Unsubscribe: <https://mails.dpdk.org/options/dev>,
 <mailto:dev-request@dpdk.org?subject=unsubscribe>
List-Archive: <http://mails.dpdk.org/archives/dev/>
List-Post: <mailto:dev@dpdk.org>
List-Help: <mailto:dev-request@dpdk.org?subject=help>
List-Subscribe: <https://mails.dpdk.org/listinfo/dev>,
 <mailto:dev-request@dpdk.org?subject=subscribe>
Errors-To: dev-bounces@dpdk.org

This header implements 64 bit counters that are NOT atomic
but are safe against load/store splits on 32 bit platforms.

Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
Acked-by: Morten Brørup <mb@smartsharesystems.com>
---
 lib/eal/include/meson.build   |  1 +
 lib/eal/include/rte_counter.h | 98 +++++++++++++++++++++++++++++++++++
 2 files changed, 99 insertions(+)
 create mode 100644 lib/eal/include/rte_counter.h

diff --git a/lib/eal/include/meson.build b/lib/eal/include/meson.build
index e94b056d46..c070dd0079 100644
--- a/lib/eal/include/meson.build
+++ b/lib/eal/include/meson.build
@@ -12,6 +12,7 @@ headers += files(
         'rte_class.h',
         'rte_common.h',
         'rte_compat.h',
+        'rte_counter.h',
         'rte_debug.h',
         'rte_dev.h',
         'rte_devargs.h',
diff --git a/lib/eal/include/rte_counter.h b/lib/eal/include/rte_counter.h
new file mode 100644
index 0000000000..d623195d63
--- /dev/null
+++ b/lib/eal/include/rte_counter.h
@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (c) Stephen Hemminger <stephen@networkplumber.org>
+ */
+
+#ifndef _RTE_COUNTER_H_
+#define _RTE_COUNTER_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @file
+ * RTE Counter
+ *
+ * A counter is 64 bit value that is safe from split read/write
+ * on 32 bit platforms. It assumes that only one cpu at a time
+ * will update the counter, and another CPU may want to read it.
+ *
+ * This is a much weaker guarantee than full atomic variables
+ * but is faster since no locked operations are required for update.
+ */
+
+#ifdef RTE_ARCH_64
+/*
+ * On a platform that can support native 64 bit type, no special handling.
+ * These are just wrapper around 64 bit value.
+ */
+typedef uint64_t rte_counter64_t;
+
+/**
+ * Add value to counter.
+ */
+__rte_experimental
+static inline void
+rte_counter64_add(rte_counter64_t *counter, uint32_t val)
+{
+	*counter += val;
+}
+
+__rte_experimental
+static inline uint64_t
+rte_counter64_fetch(const rte_counter64_t *counter)
+{
+	return *counter;
+}
+
+__rte_experimental
+static inline void
+rte_counter64_set(rte_counter64_t *counter, uint64_t val)
+{
+	*counter = val;
+}
+
+#else
+
+#include <rte_stdatomic.h>
+
+/*
+ * On a 32 bit platform need to use atomic to force the compler to not
+ * split 64 bit read/write.
+ */
+typedef RTE_ATOMIC(uint64_t) rte_counter64_t;
+
+__rte_experimental
+static inline void
+rte_counter64_add(rte_counter64_t *counter, uint32_t val)
+{
+	rte_atomic_fetch_add_explicit(counter, val, rte_memory_order_relaxed);
+}
+
+__rte_experimental
+static inline uint64_t
+rte_counter64_fetch(const rte_counter64_t *counter)
+{
+	return rte_atomic_load_explicit(counter, rte_memory_order_consume);
+}
+
+__rte_experimental
+static inline void
+rte_counter64_set(rte_counter64_t *counter, uint64_t val)
+{
+	rte_atomic_store_explicit(counter, val, rte_memory_order_release);
+}
+#endif
+
+__rte_experimental
+static inline void
+rte_counter64_reset(rte_counter64_t *counter)
+{
+	rte_counter64_set(counter, 0);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_COUNTER_H_ */
-- 
2.43.0