From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E5D3844048; Fri, 17 May 2024 09:45:37 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C2795406FF; Fri, 17 May 2024 09:45:13 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 250E84069D for ; Fri, 17 May 2024 09:45:12 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 44GLNBjI025156 for ; Fri, 17 May 2024 00:45:11 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= pfpt0220; bh=35t8+JYutPqn5AS4qH401jkFWYG8semthp7Px5QVGhs=; b=eIG v+BheGIjGWBs81quqO5i5Rj6PVLlcCz/EUGSLcTzdLTnW03f7Bvb2G1paA4k9eZb FPMZvpWpXJ3ipWaklh4zcdBtrUv0X8qZdsTRJilkjAQXwg4AQ/pm2SwC/NdDM/47 uDqoKLBa7Vb3bxiRI1DB5dQiDLKIP6xBmGrYCrQJlkBJ9JocdRJcruXaS0GWUBIE 2FclZH/lanN0nfcXw9q64lJv9OgmE8L/fR+NfBSs1PtrQuMQBUy8qRO3Yi1yt06h QkqS8AK0+K3psg1MC9b13mpSyUarGcIH7pfztUzRIJsYDNoLYC9AX0TavPAbbKrQ +QKTypCcsEugypA3xdw== Received: from dc5-exch05.marvell.com ([199.233.59.128]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3y5t0vhc3c-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Fri, 17 May 2024 00:45:11 -0700 (PDT) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 17 May 2024 00:45:10 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Fri, 17 May 2024 00:45:10 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id EF91B3F7059; Fri, 17 May 2024 00:45:07 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Harman Kalra CC: , Subject: [PATCH 06/10] net/cnxk: add option to disable custom meta aura Date: Fri, 17 May 2024 13:14:44 +0530 Message-ID: <20240517074448.3146611-6-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240517074448.3146611-1-ndabilpuram@marvell.com> References: <20240517074448.3146611-1-ndabilpuram@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: n3PAj3sYVn-pWu97mv2ZF4dlVTdpj-zb X-Proofpoint-GUID: n3PAj3sYVn-pWu97mv2ZF4dlVTdpj-zb X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.11.176.26 definitions=2024-05-16_07,2024-05-15_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add option to explicitly disable custom meta aura. Currently custom meta aura is enabled automatically when inl_cpt_channel is set i.e inline dev is masking CHAN field in IPsec rules. Also decouple the custom meta aura feature from custom sa action so that the custom sa action can independently be used. Signed-off-by: Nithin Dabilpuram --- doc/guides/nics/cnxk.rst | 13 +++++++++++++ drivers/common/cnxk/roc_nix_inl.c | 19 +++++++++++++------ drivers/common/cnxk/roc_nix_inl.h | 1 + drivers/common/cnxk/version.map | 1 + drivers/net/cnxk/cnxk_ethdev.c | 5 +++++ drivers/net/cnxk/cnxk_ethdev.h | 3 +++ drivers/net/cnxk/cnxk_ethdev_devargs.c | 8 +++++++- 7 files changed, 43 insertions(+), 7 deletions(-) diff --git a/doc/guides/nics/cnxk.rst b/doc/guides/nics/cnxk.rst index f5f296ee36..99ad224efd 100644 --- a/doc/guides/nics/cnxk.rst +++ b/doc/guides/nics/cnxk.rst @@ -444,6 +444,19 @@ Runtime Config Options With the above configuration, driver would enable packet inject from ARM cores to crypto to process and send back in Rx path. +- ``Disable custom meta aura feature`` (default ``0``) + + Custom meta aura i.e 1:N meta aura is enabled for second pass traffic by default when + ``inl_cpt_channel`` devarg is provided. Provide an option to disable the custom + meta aura feature by setting devarg ``custom_meta_aura_dis`` to ``1``. + + For example:: + + -a 0002:02:00.0,custom_meta_aura_dis=1 + + With the above configuration, driver would disable custom meta aura feature for + ``0002:02:00.0`` ethdev. + .. note:: Above devarg parameters are configurable per device, user needs to pass the diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c index 7dbeae5017..74a688abbd 100644 --- a/drivers/common/cnxk/roc_nix_inl.c +++ b/drivers/common/cnxk/roc_nix_inl.c @@ -872,7 +872,6 @@ roc_nix_inl_inb_init(struct roc_nix *roc_nix) struct nix *nix = roc_nix_to_nix_priv(roc_nix); struct roc_cpt_inline_ipsec_inb_cfg cfg; struct idev_cfg *idev = idev_get_cfg(); - struct nix_inl_dev *inl_dev; uint16_t bpids[ROC_NIX_MAX_BPID_CNT]; struct roc_cpt *roc_cpt; int rc; @@ -929,11 +928,6 @@ roc_nix_inl_inb_init(struct roc_nix *roc_nix) if (rc) return rc; - inl_dev = idev->nix_inl_dev; - - roc_nix->custom_meta_aura_ena = (roc_nix->local_meta_aura_ena && - ((inl_dev && inl_dev->is_multi_channel) || - roc_nix->custom_sa_action)); if (!roc_model_is_cn9k() && !roc_errata_nix_no_meta_aura()) { nix->need_meta_aura = true; if (!roc_nix->local_meta_aura_ena || roc_nix->custom_meta_aura_ena) @@ -1245,6 +1239,19 @@ roc_nix_inl_dev_is_probed(void) return !!idev->nix_inl_dev; } +bool +roc_nix_inl_dev_is_multi_channel(void) +{ + struct idev_cfg *idev = idev_get_cfg(); + struct nix_inl_dev *inl_dev; + + if (idev == NULL || !idev->nix_inl_dev) + return false; + + inl_dev = idev->nix_inl_dev; + return inl_dev->is_multi_channel; +} + bool roc_nix_inl_inb_is_enabled(struct roc_nix *roc_nix) { diff --git a/drivers/common/cnxk/roc_nix_inl.h b/drivers/common/cnxk/roc_nix_inl.h index 8acd7e0545..ab0965e512 100644 --- a/drivers/common/cnxk/roc_nix_inl.h +++ b/drivers/common/cnxk/roc_nix_inl.h @@ -115,6 +115,7 @@ int __roc_api roc_nix_inl_dev_stats_get(struct roc_nix_stats *stats); uint16_t __roc_api roc_nix_inl_dev_pffunc_get(void); int __roc_api roc_nix_inl_dev_cpt_setup(bool use_inl_dev_sso); int __roc_api roc_nix_inl_dev_cpt_release(void); +bool __roc_api roc_nix_inl_dev_is_multi_channel(void); /* NIX Inline Inbound API */ int __roc_api roc_nix_inl_inb_init(struct roc_nix *roc_nix); diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 424ad7f484..e8d32b331e 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -238,6 +238,7 @@ INTERNAL { roc_nix_inl_dev_dump; roc_nix_inl_dev_fini; roc_nix_inl_dev_init; + roc_nix_inl_dev_is_multi_channel; roc_nix_inl_dev_is_probed; roc_nix_inl_dev_stats_get; roc_nix_inl_dev_lock; diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c index 1bccebad9f..db8feca620 100644 --- a/drivers/net/cnxk/cnxk_ethdev.c +++ b/drivers/net/cnxk/cnxk_ethdev.c @@ -107,6 +107,11 @@ nix_security_setup(struct cnxk_eth_dev *dev) nix->ipsec_in_min_spi = dev->inb.no_inl_dev ? dev->inb.min_spi : 0; nix->ipsec_in_max_spi = dev->inb.no_inl_dev ? dev->inb.max_spi : 1; + /* Enable custom meta aura when multi-chan is used */ + if (nix->local_meta_aura_ena && roc_nix_inl_dev_is_multi_channel() && + !dev->inb.custom_meta_aura_dis) + nix->custom_meta_aura_ena = true; + /* Setup Inline Inbound */ rc = roc_nix_inl_inb_init(nix); if (rc) { diff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h index 5e040643ab..687c60c27d 100644 --- a/drivers/net/cnxk/cnxk_ethdev.h +++ b/drivers/net/cnxk/cnxk_ethdev.h @@ -257,6 +257,9 @@ struct cnxk_eth_dev_sec_inb { /* Lock to synchronize sa setup/release */ rte_spinlock_t lock; + + /* Disable custom meta aura */ + bool custom_meta_aura_dis; }; /* Outbound security data */ diff --git a/drivers/net/cnxk/cnxk_ethdev_devargs.c b/drivers/net/cnxk/cnxk_ethdev_devargs.c index 1bab19fc23..3454295d7d 100644 --- a/drivers/net/cnxk/cnxk_ethdev_devargs.c +++ b/drivers/net/cnxk/cnxk_ethdev_devargs.c @@ -280,6 +280,7 @@ parse_val_u16(const char *key, const char *value, void *extra_args) #define CNXK_NIX_META_BUF_SZ "meta_buf_sz" #define CNXK_FLOW_AGING_POLL_FREQ "aging_poll_freq" #define CNXK_NIX_RX_INJ_ENABLE "rx_inj_ena" +#define CNXK_CUSTOM_META_AURA_DIS "custom_meta_aura_dis" int cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev) @@ -291,6 +292,7 @@ cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev) uint32_t ipsec_in_max_spi = BIT(8) - 1; uint16_t sqb_slack = ROC_NIX_SQB_SLACK; uint32_t ipsec_out_max_sa = BIT(12); + uint16_t custom_meta_aura_dis = 0; uint16_t flow_prealloc_size = 1; uint16_t switch_header_type = 0; uint16_t flow_max_priority = 3; @@ -358,6 +360,8 @@ cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev) rte_kvargs_process(kvlist, CNXK_FLOW_AGING_POLL_FREQ, &parse_val_u16, &aging_thread_poll_freq); rte_kvargs_process(kvlist, CNXK_NIX_RX_INJ_ENABLE, &parse_flag, &rx_inj_ena); + rte_kvargs_process(kvlist, CNXK_CUSTOM_META_AURA_DIS, &parse_flag, + &custom_meta_aura_dis); rte_kvargs_free(kvlist); null_devargs: @@ -366,6 +370,7 @@ cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev) dev->inb.no_inl_dev = !!no_inl_dev; dev->inb.min_spi = ipsec_in_min_spi; dev->inb.max_spi = ipsec_in_max_spi; + dev->inb.custom_meta_aura_dis = custom_meta_aura_dis; dev->outb.max_sa = ipsec_out_max_sa; dev->outb.nb_desc = outb_nb_desc; dev->outb.nb_crypto_qs = outb_nb_crypto_qs; @@ -415,4 +420,5 @@ RTE_PMD_REGISTER_PARAM_STRING(net_cnxk, CNXK_CUSTOM_SA_ACT "=1" CNXK_SQB_SLACK "=<12-512>" CNXK_FLOW_AGING_POLL_FREQ "=<10-65535>" - CNXK_NIX_RX_INJ_ENABLE "=1"); + CNXK_NIX_RX_INJ_ENABLE "=1" + CNXK_CUSTOM_META_AURA_DIS "=1"); -- 2.25.1