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Signed-off-by: Serhii Iliushyk --- .../ntnic/include/clock_profiles_structs.h | 69 +++++++ .../net/ntnic/include/common_adapter_defs.h | 15 ++ drivers/net/ntnic/include/fpga_model.h | 153 +++++++++++++++ drivers/net/ntnic/include/nt4ga_adapter.h | 105 ++++++++++ drivers/net/ntnic/include/nt4ga_pci_ta_tg.h | 42 ++++ drivers/net/ntnic/include/nt4ga_tfg.h | 18 ++ drivers/net/ntnic/include/ntdrv_4ga.h | 33 ++++ drivers/net/ntnic/include/nthw_bus.h | 20 ++ drivers/net/ntnic/include/ntos_drv.h | 180 ++++++++++++++++++ drivers/net/ntnic/include/ntos_system.h | 25 +++ drivers/net/ntnic/include/ntoss_virt_queue.h | 163 ++++++++++++++++ 11 files changed, 823 insertions(+) create mode 100644 drivers/net/ntnic/include/clock_profiles_structs.h create mode 100644 drivers/net/ntnic/include/common_adapter_defs.h create mode 100644 drivers/net/ntnic/include/fpga_model.h create mode 100644 drivers/net/ntnic/include/nt4ga_adapter.h create mode 100644 drivers/net/ntnic/include/nt4ga_pci_ta_tg.h create mode 100644 drivers/net/ntnic/include/nt4ga_tfg.h create mode 100644 drivers/net/ntnic/include/ntdrv_4ga.h create mode 100644 drivers/net/ntnic/include/nthw_bus.h create mode 100644 drivers/net/ntnic/include/ntos_drv.h create mode 100644 drivers/net/ntnic/include/ntos_system.h create mode 100644 drivers/net/ntnic/include/ntoss_virt_queue.h diff --git a/drivers/net/ntnic/include/clock_profiles_structs.h b/drivers/net/ntnic/include/clock_profiles_structs.h new file mode 100644 index 0000000000..0f967453aa --- /dev/null +++ b/drivers/net/ntnic/include/clock_profiles_structs.h @@ -0,0 +1,69 @@ +/* */ +/* clock_profiles_structs.h */ +/* */ + +/* + * %NT_SOFTWARE_LICENSE% + */ + +#ifndef _NT_CLOCK_PROFILES_STRUCTS_H_ +#define _NT_CLOCK_PROFILES_STRUCTS_H_ + +/* */ +/* */ +/* */ +#include + +/* */ +/* */ +/* */ +#define GET_VAR_NAME(var) #var + +#define clk_profile_size_error_msg "Size test failed" + +/* */ +/* */ +/* */ +struct clk_profile_data_fmt0_s { + unsigned char reg_addr; + unsigned char reg_val; + unsigned char reg_mask; +}; + +struct clk_profile_data_fmt1_s { + uint16_t reg_addr; + uint8_t reg_val; +}; + +struct clk_profile_data_fmt2_s { + unsigned int reg_addr; + unsigned char reg_val; +}; + +struct clk_profile_data_fmt3_s { + unsigned int address; + unsigned int data; +}; + +typedef struct clk_profile_data_fmt0_s clk_profile_data_fmt0_t; +typedef struct clk_profile_data_fmt1_s clk_profile_data_fmt1_t; +typedef struct clk_profile_data_fmt2_s clk_profile_data_fmt2_t; +typedef struct clk_profile_data_fmt3_s clk_profile_data_fmt3_t; + +enum clk_profile_data_fmt_e { + clk_profile_data_fmt_0, + clk_profile_data_fmt_1, + clk_profile_data_fmt_2, + clk_profile_data_fmt_3, +}; + +typedef enum clk_profile_data_fmt_e clk_profile_data_fmt_t; + +/* */ +/* */ +/* */ +#endif /* _NT_CLOCK_PROFILES_STRUCTS_H_ */ + +/* */ +/* EOF */ +/* */ diff --git a/drivers/net/ntnic/include/common_adapter_defs.h b/drivers/net/ntnic/include/common_adapter_defs.h new file mode 100644 index 0000000000..6ed9121f0f --- /dev/null +++ b/drivers/net/ntnic/include/common_adapter_defs.h @@ -0,0 +1,15 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#ifndef _COMMON_ADAPTER_DEFS_H_ +#define _COMMON_ADAPTER_DEFS_H_ + +/* + * Declarations shared by NT adapter types. + */ +#define NUM_ADAPTER_MAX (8) +#define NUM_ADAPTER_PORTS_MAX (128) + +#endif /* _COMMON_ADAPTER_DEFS_H_ */ diff --git a/drivers/net/ntnic/include/fpga_model.h b/drivers/net/ntnic/include/fpga_model.h new file mode 100644 index 0000000000..3d6610a41b --- /dev/null +++ b/drivers/net/ntnic/include/fpga_model.h @@ -0,0 +1,153 @@ +/* */ +/* fpga_model.h */ +/* */ + +#ifndef _FPGA_MODEL_H_ +#define _FPGA_MODEL_H_ + +/* */ +/* */ +/* */ +#ifdef __cplusplus +#include +#else +#ifndef __KERNEL__ +#include +#include +#include +#else +#include +#endif /* __KERNEL__ */ +#endif /* __cplusplus */ + +/* */ +/* */ +/* */ + +typedef uint32_t nthw_id_t; + +/* */ +/* */ +/* */ +enum nthw_fpga_bus_type { + NTHW_FPGA_BUS_TYPE_UNKNOWN = + 0, /* Unknown/uninitialized - keep this as the first enum element */ + NTHW_FPGA_BUS_TYPE_BAR, + NTHW_FPGA_BUS_TYPE_PCI, + NTHW_FPGA_BUS_TYPE_CCIP, + NTHW_FPGA_BUS_TYPE_RAB0, + NTHW_FPGA_BUS_TYPE_RAB1, + NTHW_FPGA_BUS_TYPE_RAB2, + NTHW_FPGA_BUS_TYPE_NMB, + NTHW_FPGA_BUS_TYPE_NDM, + NTHW_FPGA_BUS_TYPE_SPI0, + NTHW_FPGA_BUS_TYPE_SPI = NTHW_FPGA_BUS_TYPE_SPI0, +}; + +typedef enum nthw_fpga_bus_type nthw_fpga_bus_type_e; + +/* */ +/* */ +/* */ +enum nthw_fpga_register_type { + NTHW_FPGA_REG_TYPE_UNKNOWN = + 0, /* Unknown/uninitialized - keep this as the first enum element */ + NTHW_FPGA_REG_TYPE_RW, + NTHW_FPGA_REG_TYPE_RO, + NTHW_FPGA_REG_TYPE_WO, + NTHW_FPGA_REG_TYPE_RC1, + NTHW_FPGA_REG_TYPE_MIXED, +}; + +typedef enum nthw_fpga_register_type nthw_fpga_register_type_e; + +/* */ +/* */ +/* */ +struct nthw_fpga_field_init { + nthw_id_t id; + /* */ + uint16_t bw; + uint16_t low; + uint64_t reset_val; +}; + +typedef struct nthw_fpga_field_init nthw_fpga_field_init_s; + +/* */ +/* */ +/* */ +struct nthw_fpga_register_init { + nthw_id_t id; + /* */ + uint32_t addr_rel; + uint16_t bw; + nthw_fpga_register_type_e type; + uint64_t reset_val; + /* */ + int nb_fields; + struct nthw_fpga_field_init *fields; +}; + +typedef struct nthw_fpga_register_init nthw_fpga_register_init_s; + +/* */ +/* */ +/* */ +struct nthw_fpga_module_init { + nthw_id_t id; + int instance; + /* */ + nthw_id_t def_id; + int major_version; + int minor_version; + /* */ + nthw_fpga_bus_type_e bus_id; + uint32_t addr_base; + /* */ + int nb_registers; + struct nthw_fpga_register_init *registers; +}; + +typedef struct nthw_fpga_module_init nthw_fpga_module_init_s; + +/* */ +/* */ +/* */ +struct nthw_fpga_prod_param { + const nthw_id_t id; + const int value; +}; + +typedef struct nthw_fpga_prod_param nthw_fpga_prod_param_s; + +/* */ +/* */ +/* */ +struct nthw_fpga_prod_init { + int fpga_item_id; + int fpga_product_id; + int fpga_version; + int fpga_revision; + int fpga_patch_no; + int fpga_build_no; + uint32_t fpga_build_time; + /* */ + int nb_prod_params; + struct nthw_fpga_prod_param *product_params; + /* */ + int nb_modules; + struct nthw_fpga_module_init *modules; +}; + +typedef struct nthw_fpga_prod_init nthw_fpga_prod_init_s; + +/* */ +/* */ +/* */ + +#endif /* _FPGA_MODEL_H_ */ + +/* */ +/* EOF */ +/* */ diff --git a/drivers/net/ntnic/include/nt4ga_adapter.h b/drivers/net/ntnic/include/nt4ga_adapter.h new file mode 100644 index 0000000000..0722829529 --- /dev/null +++ b/drivers/net/ntnic/include/nt4ga_adapter.h @@ -0,0 +1,105 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#ifndef _NT4GA_ADAPTER_H_ +#define _NT4GA_ADAPTER_H_ + +#include "common_adapter_defs.h" + +struct adapter_info_s; + +/* + * DN-0060 section 9 + */ +typedef struct hw_info_s { + /* pciids */ + uint16_t pci_vendor_id; + uint16_t pci_device_id; + uint16_t pci_sub_vendor_id; + uint16_t pci_sub_device_id; + uint16_t pci_class_id; + + /* Derived from pciid */ + nthw_adapter_id_t n_nthw_adapter_id; + int hw_platform_id; + int hw_product_type; + int hw_reserved1; +} hw_info_t; + +/* + * Services provided by the adapter module + */ +#include "nt4ga_pci_ta_tg.h" +#include "nt4ga_filter.h" +#include "ntnic_stat.h" +#include "nt4ga_tfg.h" +#include "nt4ga_link.h" + +#include "nthw_spi_v3.h" +#include "ntnic_nim.h" + +#include "ntnic_sensor.h" + +typedef struct adapter_info_s { + struct nt4ga_pci_ta_tg_s nt4ga_pci_ta_tg; + struct nt4ga_stat_s nt4ga_stat; + struct nt4ga_filter_s nt4ga_filter; + struct nt4ga_tfg_s nt4ga_tfg; + struct nt4ga_link_s nt4ga_link; + + struct nthw_mcu *mp_nthw_mcu; + + struct hw_info_s hw_info; + struct fpga_info_s fpga_info; + + uint16_t adapter_sensors_cnt; + uint16_t nim_sensors_cnt[NUM_ADAPTER_PORTS_MAX]; + struct nt_sensor_group *adapter_sensors; + struct nim_sensor_group *nim_sensors[NUM_ADAPTER_PORTS_MAX]; + + char *mp_port_id_str[NUM_ADAPTER_PORTS_MAX]; + char *mp_adapter_id_str; + char *p_dev_name; + volatile bool *pb_shutdown; + + int adapter_no; + int n_rx_host_buffers; + int n_tx_host_buffers; +} adapter_info_t; + +/* + * Monitor task operations. This structure defines the management hooks for + * Napatech network devices. The following hooks can be defined; unless noted + * otherwise, they are optional and can be filled with a null pointer. + * + * int (*mto_open)(int adapter, int port); + * The function to call when a network device transitions to the up state, + * e.g., `ip link set up`. + * + * int (*mto_stop)(int adapter, int port); + * The function to call when a network device transitions to the down state, + * e.g., `ip link set down`. + */ +struct monitor_task_ops { + int (*mto_open)(int adapter, int port); + int (*mto_stop)(int adapter, int port); +}; + +#include +#include + +/* The file nt4ga_adapter.c defines the next four variables. */ +extern pthread_t monitor_tasks[NUM_ADAPTER_MAX]; +extern volatile int monitor_task_is_running[NUM_ADAPTER_MAX]; + +/* + * Function that sets up signal handler(s) that stop the monitoring tasks. + */ +int set_up_signal_handlers_to_stop_monitoring_tasks(void); + +/* SPI for sensors reading */ +nthw_spis_t *new_sensors_t_spi(struct nthw_fpga_s *p_fpga); + +#endif /* _NT4GA_ADAPTER_H_ */ diff --git a/drivers/net/ntnic/include/nt4ga_pci_ta_tg.h b/drivers/net/ntnic/include/nt4ga_pci_ta_tg.h new file mode 100644 index 0000000000..b445a22930 --- /dev/null +++ b/drivers/net/ntnic/include/nt4ga_pci_ta_tg.h @@ -0,0 +1,42 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#ifndef _NT4GA_PCI_TA_TG_H_ +#define _NT4GA_PCI_TA_TG_H_ + +#include + +#define TA_TG_DBG_SHOW_SUMMARY (1) + +#define TG_NUM_PACKETS (8) +#define TG_PKT_SIZE (2048 * 1) +#define TG_AREA_SIZE (TG_NUM_PACKETS * TG_PKT_SIZE) + +#define TG_DELAY (200000) /* usec */ + +/* Struct predefinitions */ +struct adapter_info_s; +struct nthw_hif_end_point_counters; + +struct nt4ga_pci_ta_tg_s { + struct nthw_pci_rd_tg *mp_nthw_pci_rd_tg; + struct nthw_pci_wr_tg *mp_nthw_pci_wr_tg; + struct nthw_pci_ta *mp_nthw_pci_ta; +}; + +typedef struct nt4ga_pci_ta_tg_s nt4ga_pci_ta_tg_t; +typedef struct nt4ga_pci_ta_tg_s nt4ga_pci_ta_tg; + +int nt4ga_pci_ta_tg_init(struct adapter_info_s *p_adapter_info); + +int nt4ga_pci_ta_tg_measure_throughput_run(struct adapter_info_s *p_adapter_info, + struct nthw_hif_end_point_counters *pri, + struct nthw_hif_end_point_counters *sla); +int nt4ga_pci_ta_tg_measure_throughput_main(struct adapter_info_s *p_adapter_info, + const uint8_t numa_node, const int direction, + const int n_pkt_size, const int n_batch_count, + const int n_delay); + +#endif /* _NT4GA_PCI_TA_TG_H_ */ diff --git a/drivers/net/ntnic/include/nt4ga_tfg.h b/drivers/net/ntnic/include/nt4ga_tfg.h new file mode 100644 index 0000000000..9797403dec --- /dev/null +++ b/drivers/net/ntnic/include/nt4ga_tfg.h @@ -0,0 +1,18 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#ifndef NT4GA_TFG_H_ +#define NT4GA_TFG_H_ + +typedef struct nt4ga_tfg_s { + nthw_mac_tfg_t *mp_nthw_mac_tfg; +} nt4ga_tfg_t; + +int nt4ga_tfg_init(struct adapter_info_s *p_adapter_info); +int nt4ga_tfg_setup(struct adapter_info_s *p_adapter_info, const int n_intf_no, + const int n_cmd_start_stop, const int n_frame_count, const int n_frame_size, + const int n_frame_fill_mode, const int n_frame_stream_id); + +#endif /* NT4GA_TFG_H_ */ diff --git a/drivers/net/ntnic/include/ntdrv_4ga.h b/drivers/net/ntnic/include/ntdrv_4ga.h new file mode 100644 index 0000000000..cae25ecfa6 --- /dev/null +++ b/drivers/net/ntnic/include/ntdrv_4ga.h @@ -0,0 +1,33 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#ifndef __NTDRV_4GA_H__ +#define __NTDRV_4GA_H__ + +#include +#include +#include "nthw_drv.h" +#include "nt4ga_adapter.h" +#include "nthw_platform_drv.h" + +typedef struct ntdrv_4ga_s { + uint32_t pciident; + struct adapter_info_s adapter_info; + char *p_drv_name; + + volatile bool b_shutdown; + pthread_mutex_t stat_lck; +#if RTE_VERSION_NUM(23, 11, 0, 0) < RTE_VERSION + rte_thread_t stat_thread; + rte_thread_t flm_thread; + rte_thread_t port_event_thread; +#else + pthread_t stat_thread; + pthread_t flm_thread; + pthread_t port_event_thread; +#endif +} ntdrv_4ga_t; + +#endif /* __NTDRV_4GA_H__ */ diff --git a/drivers/net/ntnic/include/nthw_bus.h b/drivers/net/ntnic/include/nthw_bus.h new file mode 100644 index 0000000000..9d1532335b --- /dev/null +++ b/drivers/net/ntnic/include/nthw_bus.h @@ -0,0 +1,20 @@ +/* */ +/* nthw_bus.h */ +/* */ + +/* */ +/* */ +/* */ +#ifndef __NTHW_BUS_H__ +#define __NTHW_BUS_H__ + +/* */ +/* */ +/* */ +typedef uint8_t nthw_rab_bus_id_t; + +#endif /* __NTHW_BUS_H__ */ + +/* */ +/* EOF */ +/* */ diff --git a/drivers/net/ntnic/include/ntos_drv.h b/drivers/net/ntnic/include/ntos_drv.h new file mode 100644 index 0000000000..a181676593 --- /dev/null +++ b/drivers/net/ntnic/include/ntos_drv.h @@ -0,0 +1,180 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#ifndef __NTOS_DRV_H__ +#define __NTOS_DRV_H__ + +#include +#include +#include +#include +#include + +#include /* RTE_VERSION, RTE_VERSION_NUM */ +#include + +#include "stream_binary_flow_api.h" +#include "nthw_drv.h" +#include "nthw_profile.h" + +#define NUM_MAC_ADDRS_PER_PORT (16U) +#define NUM_MULTICAST_ADDRS_PER_PORT (16U) + +/* Max RSS queues */ +#define MAX_QUEUES 125 + +/* Structs: */ +#define SG_HDR_SIZE 12 + +struct _pkt_hdr_rx { + uint32_t cap_len : 14; + uint32_t fid : 10; + uint32_t ofs1 : 8; + uint32_t ip_prot : 8; + uint32_t port : 13; + uint32_t descr : 8; + uint32_t descr_12b : 1; + uint32_t color_type : 2; + uint32_t color : 32; +}; + +struct _pkt_hdr_tx { + uint32_t cap_len : 14; + uint32_t lso_cso0 : 9; + uint32_t lso_cso1 : 9; + uint32_t lso_cso2 : 8; + /* all 1's : use implicit in-port. 0-127 queue index. 0x80 + phy-port to phy */ + uint32_t bypass_port : 13; + uint32_t descr : 8; + uint32_t descr_12b : 1; + uint32_t color_type : 2; + uint32_t color : 32; +}; + +/* Total max ports per NT NFV NIC */ +#define MAX_NTNIC_PORTS 2 + +/* Total max VDPA ports */ +#define MAX_VDPA_PORTS 128UL + +struct nthw_memory_descriptor { + void *phys_addr; + void *virt_addr; + uint32_t len; +}; + +struct hwq_s { + int vf_num; + struct nthw_memory_descriptor virt_queues_ctrl; + struct nthw_memory_descriptor *pkt_buffers; +}; + +struct ntnic_rx_queue { + struct flow_queue_id_s queue; /* queue info - user id and hw queue index */ + + struct rte_mempool *mb_pool; /* mbuf memory pool */ + uint16_t buf_size; /* Size of data area in mbuf */ + unsigned long rx_pkts; /* Rx packet statistics */ + unsigned long rx_bytes; /* Rx bytes statistics */ + unsigned long err_pkts; /* Rx error packet statistics */ + int enabled; /* Enabling/disabling of this queue */ + + struct hwq_s hwq; + struct nthw_virt_queue *vq; + int nb_hw_rx_descr; + nt_meta_port_type_t type; + uint32_t port; /* Rx port for this queue */ + enum fpga_info_profile profile; /* Vswitch / Inline / Capture */ + +} __rte_cache_aligned; + +struct ntnic_tx_queue { + struct flow_queue_id_s queue; /* queue info - user id and hw queue index */ + struct hwq_s hwq; + struct nthw_virt_queue *vq; + int nb_hw_tx_descr; + /* Used for bypass in NTDVIO0 header on Tx - pre calculated */ + int target_id; + nt_meta_port_type_t type; + /* only used for exception tx queue from OVS SW switching */ + int rss_target_id; + + uint32_t port; /* Tx port for this queue */ + unsigned long tx_pkts; /* Tx packet statistics */ + unsigned long tx_bytes; /* Tx bytes statistics */ + unsigned long err_pkts; /* Tx error packet stat */ + int enabled; /* Enabling/disabling of this queue */ + enum fpga_info_profile profile; /* Vswitch / Inline / Capture */ +} __rte_cache_aligned; + +struct nt_mtr_profile { + LIST_ENTRY(nt_mtr_profile) next; + uint32_t profile_id; + struct rte_mtr_meter_profile profile; +}; + +struct nt_mtr { + LIST_ENTRY(nt_mtr) next; + uint32_t mtr_id; + int shared; + struct nt_mtr_profile *profile; +}; + +enum virt_port_comm { + VIRT_PORT_NEGOTIATED_NONE, + VIRT_PORT_NEGOTIATED_SPLIT, + VIRT_PORT_NEGOTIATED_PACKED, + VIRT_PORT_USE_RELAY +}; + +struct pmd_internals { + const struct rte_pci_device *pci_dev; + + struct flow_eth_dev *flw_dev; + + char name[20]; + char vhost_path[MAX_PATH_LEN]; + + int n_intf_no; + int if_index; + + int lpbk_mode; + + uint8_t ts_multiplier; + uint16_t min_tx_pkt_size; + uint16_t max_tx_pkt_size; + + unsigned int nb_rx_queues; /* Number of Rx queues configured */ + unsigned int nb_tx_queues; /* Number of Tx queues configured */ + uint32_t port; + uint32_t port_id; + uint8_t vf_offset; /* Offset of the VF from the PF */ + + nt_meta_port_type_t type; + struct flow_queue_id_s vpq[MAX_QUEUES]; + unsigned int vpq_nb_vq; + int vhid; /* if a virtual port type - the vhid */ + enum virt_port_comm vport_comm; /* link and how split,packed,relay */ + uint32_t vlan; + + struct ntnic_rx_queue rxq_scg[MAX_QUEUES]; /* Array of Rx queues */ + struct ntnic_tx_queue txq_scg[MAX_QUEUES]; /* Array of Tx queues */ + + struct drv_s *p_drv; + /* Ethernet (MAC) addresses. Element number zero denotes default address. */ + struct rte_ether_addr eth_addrs[NUM_MAC_ADDRS_PER_PORT]; + /* Multicast ethernet (MAC) addresses. */ + struct rte_ether_addr mc_addrs[NUM_MULTICAST_ADDRS_PER_PORT]; + + LIST_HEAD(_profiles, nt_mtr_profile) mtr_profiles; + LIST_HEAD(_mtrs, nt_mtr) mtrs; + + uint64_t last_stat_rtc; + uint64_t rx_missed; + + struct pmd_internals *next; +}; + +#endif /* __NTOS_DRV_H__ */ diff --git a/drivers/net/ntnic/include/ntos_system.h b/drivers/net/ntnic/include/ntos_system.h new file mode 100644 index 0000000000..cf4768799d --- /dev/null +++ b/drivers/net/ntnic/include/ntos_system.h @@ -0,0 +1,25 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#ifndef __NTOS_SYSTEM_H__ +#define __NTOS_SYSTEM_H__ + +#include "include/ntdrv_4ga.h" + +/* + * struct drv_s for DPDK (clone of kernel struct) + * keep it as close as possible to original kernel struct + */ +struct drv_s { + int adapter_no; + struct rte_pci_device *p_dev; + struct ntdrv_4ga_s ntdrv; + + int n_eth_dev_init_count; + int probe_finished; + int setup_finished; +}; + +#endif /* __NTOS_SYSTEM_H__ */ diff --git a/drivers/net/ntnic/include/ntoss_virt_queue.h b/drivers/net/ntnic/include/ntoss_virt_queue.h new file mode 100644 index 0000000000..03d652066a --- /dev/null +++ b/drivers/net/ntnic/include/ntoss_virt_queue.h @@ -0,0 +1,163 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#ifndef __NTOSS_VIRT_QUEUE_H__ +#define __NTOSS_VIRT_QUEUE_H__ + +#include +#include + +#include "ntos_drv.h" +struct nthw_virt_queue; + +#define ule64 uint64_t +#define ule32 uint32_t +#define ule16 uint16_t + +#define MAX_MSIX_VECTORS_PR_VF 8 + +#define SPLIT_RING 0 +#define PACKED_RING 1 +#define IN_ORDER 1 +#define NO_ORDER_REQUIRED 0 + +/* + * SPLIT : This marks a buffer as continuing via the next field. + * PACKED: This marks a buffer as continuing. (packed does not have a next field, so must be + * contiguous) In Used descriptors it must be ignored + */ +#define VIRTQ_DESC_F_NEXT 1 +/* + * SPLIT : This marks a buffer as device write-only (otherwise device read-only). + * PACKED: This marks a descriptor as device write-only (otherwise device read-only). + * PACKED: In a used descriptor, this bit is used to specify whether any data has been written by + * the device into any parts of the buffer. + */ +#define VIRTQ_DESC_F_WRITE 2 +/* + * SPLIT : This means the buffer contains a list of buffer descriptors. + * PACKED: This means the element contains a table of descriptors. + */ +#define VIRTQ_DESC_F_INDIRECT 4 + +/* + * Split Ring virtq Descriptor + */ +#pragma pack(1) +struct virtq_desc { + /* Address (guest-physical). */ + ule64 addr; + /* Length. */ + ule32 len; + /* The flags as indicated above. */ + ule16 flags; + /* Next field if flags & NEXT */ + ule16 next; +}; +#pragma pack() + +/* + * Packed Ring special structures and defines + */ + +#define MAX_PACKED_RING_ELEMENTS (1 << 15) /* 32768 */ + +/* additional packed ring flags */ +#define VIRTQ_DESC_F_AVAIL (1 << 7) +#define VIRTQ_DESC_F_USED (1 << 15) + +/* descr phys address must be 16 byte aligned */ +#pragma pack(push, 16) +struct pvirtq_desc { + /* Buffer Address. */ + ule64 addr; + /* Buffer Length. */ + ule32 len; + /* Buffer ID. */ + ule16 id; + /* The flags depending on descriptor type. */ + ule16 flags; +}; +#pragma pack(pop) + +/* Enable events */ +#define RING_EVENT_FLAGS_ENABLE 0x0 +/* Disable events */ +#define RING_EVENT_FLAGS_DISABLE 0x1 +/* + * Enable events for a specific descriptor + * (as specified by Descriptor Ring Change Event Offset/Wrap Counter). + * Only valid if VIRTIO_F_RING_EVENT_IDX has been negotiated. + */ +#define RING_EVENT_FLAGS_DESC 0x2 +/* The value 0x3 is reserved */ + +struct pvirtq_event_suppress { + union { + struct { + /* Descriptor Ring Change Event Offset */ + ule16 desc_event_off : 15; + /* Descriptor Ring Change Event Wrap Counter */ + ule16 desc_event_wrap : 1; + }; + /* If desc_event_flags set to RING_EVENT_FLAGS_DESC */ + ule16 desc; + }; + + /* phys address must be 4 byte aligned */ +#pragma pack(push, 16) + union { + struct { + ule16 desc_event_flags : 2; /* Descriptor Ring Change Event Flags */ + ule16 reserved : 14; /* Reserved, set to 0 */ + }; + ule16 flags; + }; +}; +#pragma pack(pop) + +/* + * Common virtq descr + */ +#define vq_set_next(vq, index, nxt) \ + do { \ + struct nthw_cvirtq_desc *temp_vq = (vq); \ + if (temp_vq->vq_type == SPLIT_RING) \ + temp_vq->s[index].next = nxt; \ + } while (0) + +#define vq_set_flags(vq, index, flgs) \ + do { \ + struct nthw_cvirtq_desc *temp_vq = (vq); \ + uint32_t temp_flags = (flgs); \ + uint32_t temp_index = (index); \ + if ((temp_vq)->vq_type == SPLIT_RING) \ + (temp_vq)->s[temp_index].flags = temp_flags; \ + else if ((temp_vq)->vq_type == PACKED_RING) \ + (temp_vq)->p[temp_index].flags = temp_flags; \ + } while (0) + +struct nthw_virtq_desc_buf { + /* Address (guest-physical). */ + alignas(16) ule64 addr; + /* Length. */ + ule32 len; +}; + +struct nthw_cvirtq_desc { + union { + struct nthw_virtq_desc_buf *b; /* buffer part as is common */ + struct virtq_desc *s; /* SPLIT */ + struct pvirtq_desc *p; /* PACKED */ + }; + uint16_t vq_type; +}; + +struct nthw_received_packets { + void *addr; + uint32_t len; +}; + +#endif /* __NTOSS_VIRT_QUEUE_H__ */ -- 2.44.0