From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id EAA6244119; Fri, 31 May 2024 05:52:24 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 476FB41144; Fri, 31 May 2024 05:52:21 +0200 (CEST) Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2064.outbound.protection.outlook.com [40.107.223.64]) by mails.dpdk.org (Postfix) with ESMTP id ABE194027D for ; Fri, 31 May 2024 05:52:17 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=LlLvOM9W9BcQaTYcID3eRyJdBSQcJI22OPBstnE8hI5lhRlzqgkOA8BS0ARksX+oRlRXSDAiaEMy2mc8pOXw6IkfA9SzuxIRbV8erSXxC2VqFtdnOgTCqhWtTp5nyw+NFGpegrPBA68thGqmnKHsZz1mECSVn0vf8zRk+FxwaH2z5LE5yHkGzV2i1avD45iEXvvUEmu1OgBwu94UetiNHnNLsNIKWKbxBgsbI/IA3dL6n3PtLTnGuL+McV59+CactT5oFcEgB74bKuahF0fuvkNbnoiTyaARBq1XoHn/6MCLaPMny2DjMIbuUex86zwNBeWQIj/X2Q7snm/s7oV2DA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=mw4NqXRKj40WG2coq+BAVZKf0mon9nNRjNUB9YF9XUM=; b=DMxur7gv/IbnaoyiBN9DwyQFFDbFSCYFnz7UhAh8y+5kxP6G7YbSIQse8q8TOTncGg4PzjLXWFZMryohlQlfoypUDtr6+lmjJsaiB3dCa28iOr5ceRErO3UTh7Qo4p4AAC44+LBquZft0IdCw6509tzbsvSfmQBktc37UvYurGnzlkXHqfaY976GfrmIKzmdOnQ0YzgWb5lopfGkEMcYCCydcvEWmRq5cxvebJvHltIXJ9Z0gCY2QmDUj81GDc8yWJvwHIKXXC3x/IVRzVeXe2D0yulsKaDUTATdvdw9mFU7GkDa3/7y5JG0IDFwpRNZstC3br/UGGL300aa/AsGew== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=mw4NqXRKj40WG2coq+BAVZKf0mon9nNRjNUB9YF9XUM=; b=sVec3RAKBiPPgsIB/jbSFfyDAgLE8hl5zGfWRtXWq/YkMavYLtSTL76Shr5HpBtUONjAJe8krfVwwPWqFtnmedSZMVgDnHrxSUQ1czuiABa9WY65rNd84Tu22uhbYf7XiQzWdR9i7YBUo37jywb89k+bAh0iuw0vfN+B4fjjaOwqR/xty8b3mTGOTJShkbMoIGEmjXo3s2GYKNMiYUxsARN/akGEOeqQy5IOlAqO9W+diP7CLgI6+ydof/kO3qbxt+xPTdogzrI3UGYDDt0LIHaxBxQwhUZKBA+G5eaAHKg6Vrw8URBksxTG2Md1Ga3PxJTmGxAlRyzNDPNAFyjGXg== Received: from BL0PR02CA0011.namprd02.prod.outlook.com (2603:10b6:207:3c::24) by CH3PR12MB7570.namprd12.prod.outlook.com (2603:10b6:610:149::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7633.22; Fri, 31 May 2024 03:52:15 +0000 Received: from BL6PEPF0001AB71.namprd02.prod.outlook.com (2603:10b6:207:3c:cafe::2e) by BL0PR02CA0011.outlook.office365.com (2603:10b6:207:3c::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7633.22 via Frontend Transport; Fri, 31 May 2024 03:52:14 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by BL6PEPF0001AB71.mail.protection.outlook.com (10.167.242.164) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7633.15 via Frontend Transport; Fri, 31 May 2024 03:52:14 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 30 May 2024 20:52:02 -0700 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 30 May 2024 20:52:00 -0700 From: Suanming Mou To: Dariusz Sosnowski , Viacheslav Ovsiienko , Ori Kam , Matan Azrad CC: , Subject: [PATCH 2/2] net/mlx5/hws: add match with switch manager Date: Fri, 31 May 2024 11:51:44 +0800 Message-ID: <20240531035144.1732054-2-suanmingm@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240531035144.1732054-1-suanmingm@nvidia.com> References: <20240531035144.1732054-1-suanmingm@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB71:EE_|CH3PR12MB7570:EE_ X-MS-Office365-Filtering-Correlation-Id: 2afafa2b-0dd9-4e14-f7f4-08dc81250f42 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230031|82310400017|1800799015|376005|36860700004; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?uT0zod2yQzsHqzfwhHCBocMpn6+mntmIqmmdIUJf3yz9EpvSdB4pVc/vKR88?= =?us-ascii?Q?g2mbkuqvkHEM11xqL/a6zWFkH9hzSzYErCG72ci3FZlxr/b/qgRFCAPEDF7p?= =?us-ascii?Q?6FVcj6v6Be32m5MD3VLBtIwyR5tfjnuxLMmKQUm/Zqw1sTvccjeKEz2B/UYm?= =?us-ascii?Q?wVNWl8MXJIYYLCAHYXC1C5g8OdGuJuePch4qn50Uw92Z4p1w6RnbFYkmwJm7?= =?us-ascii?Q?5R0MJGkFHKBbspB3YMQf+BfiUeUUP7akyTKuOCOfv7obpR1eiDCEODAkbAqq?= =?us-ascii?Q?Xc335RHwC4GuvXt+0f2D1IyNFas4/VE6u/45nTvBAyGXKkxyyb4v9gDodEd8?= =?us-ascii?Q?Vb+PZv4aJCYO2Xge09181kmrnNA7g+h/ysh4y0E8kiPv90jCcP5WfzHXV9zG?= =?us-ascii?Q?F9iR3qyCDJor00Kyvb1kiS+kFWYJUzvm5ECyxTsEAZksL3KeWHzNuZjRIp0m?= =?us-ascii?Q?h8Piv1BJdyqRTW1PnSOy4+/vzhByqveNfONzTLbzSzdLQKcv1MoKDBw6zrKr?= =?us-ascii?Q?3mhFLQ2LOircqkuOVbLrJ3RYfTsnlsCTAis+g7SWH3gzvwq5dvTKZJIWezIe?= =?us-ascii?Q?kuPlRVKGMBpQKw+tw8srNJMW6Cw8bOsack6UcGb9qOEHbpYSuyCCVRID6pCg?= =?us-ascii?Q?LF2EO5zH6X3dp1IQeik+cFk8/LO+QQvXQZ/FRIUHsocVHdJyX0zRTeLN6a0r?= =?us-ascii?Q?D6H7AnOV9nC0GTccZ7RnDBEltgNx+dTwKW5uQWic4Es2N3Th2J3oTCboGdFj?= =?us-ascii?Q?MdklQvT2nsfdOD8y/QrTbNziwBrR0HDxV22iClpWbWPKgwmdHEUi1UCsflGJ?= =?us-ascii?Q?/4YO3hnveJjv8rSYrv3NTEVlbv1nx2TQi3oHaOsCHV7P2KHT10881wxUrr2B?= =?us-ascii?Q?L9W474083Vs79XkjA9wWSp6IAmeNf0ryOHozqAOxckdf5uIYPdYtQ5biruRd?= =?us-ascii?Q?dDimC3At6LXdp8B06HkB8nEjjxIF3FxmrovbmCpBQzfMAKbZhHwIPhgyD+73?= =?us-ascii?Q?q1TazPVQ6aFYHCUIyhWDcd3tQ/V49jTJgql2To3S7hTPRdOJgAvbzY3CiPe/?= =?us-ascii?Q?l4SbnTfvCbuJ9PbU2jpxGO38J9r2BFUO4MIWvH408EWW7+y5nQmFeBTtBhW6?= =?us-ascii?Q?2ud1TjnpdBWkCCMwzJAgeCyqWtK9LltNAe+z/WYnQ9zeaDufPd7NBPsBNETF?= =?us-ascii?Q?sKO5GQ/j5w6XzHqR/Vl+1R/2Ng/2GkJ+DlTePYwbhTPkLTOyASl0ZlxX+KvH?= =?us-ascii?Q?641DjUl8nTv41uA/G76qcVGzbz5AJ04kK/0SljKkHw5TB9GyAwZkDq/8rqF+?= =?us-ascii?Q?p8DrSoqENzEBK42TifqvfmfWGrchjvMzVBX5GdjcO8LGQf3ewPvfv19Od41d?= =?us-ascii?Q?VIEl2amkGCnRdhb+l22OZ4vuVVVs?= X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230031)(82310400017)(1800799015)(376005)(36860700004); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 May 2024 03:52:14.7556 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2afafa2b-0dd9-4e14-f7f4-08dc81250f42 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB71.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB7570 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This commit adds HWS layer match with switch manager code. Signed-off-by: Suanming Mou --- drivers/net/mlx5/hws/mlx5dr_definer.c | 3 ++- drivers/net/mlx5/hws/mlx5dr_definer.h | 5 ++++- drivers/net/mlx5/hws/mlx5dr_rule.c | 2 +- drivers/net/mlx5/mlx5_flow.h | 30 +++++++++++++++++++++++++-- 4 files changed, 35 insertions(+), 5 deletions(-) diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c index bc128c7b99..4be9012e25 100644 --- a/drivers/net/mlx5/hws/mlx5dr_definer.c +++ b/drivers/net/mlx5/hws/mlx5dr_definer.c @@ -721,7 +721,7 @@ mlx5dr_definer_vport_set(struct mlx5dr_definer_fc *fc, const struct flow_hw_port_info *port_info; uint32_t regc_value; - port_info = flow_hw_conv_port_id(v->port_id); + port_info = flow_hw_conv_port_id(fc->dr_ctx, v->port_id); if (unlikely(!port_info)) regc_value = BAD_PORT; else @@ -1548,6 +1548,7 @@ mlx5dr_definer_conv_item_port(struct mlx5dr_definer_conv_data *cd, DR_CALC_SET_HDR(fc, registers, register_c_0); fc->bit_off = __builtin_ctz(caps->wire_regc_mask); fc->bit_mask = caps->wire_regc_mask >> fc->bit_off; + fc->dr_ctx = cd->ctx; } else { DR_LOG(ERR, "Pord ID item mask must specify ID mask"); rte_errno = EINVAL; diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.h b/drivers/net/mlx5/hws/mlx5dr_definer.h index 463e22732e..b583f78943 100644 --- a/drivers/net/mlx5/hws/mlx5dr_definer.h +++ b/drivers/net/mlx5/hws/mlx5dr_definer.h @@ -223,9 +223,12 @@ enum mlx5dr_definer_type { struct mlx5dr_definer_fc { uint8_t item_idx; uint8_t is_range; - uint16_t extra_data; uint8_t compare_idx; bool compare_set_base; + union { + uint32_t extra_data; + void *dr_ctx; + }; uint32_t byte_off; int bit_off; uint32_t bit_mask; diff --git a/drivers/net/mlx5/hws/mlx5dr_rule.c b/drivers/net/mlx5/hws/mlx5dr_rule.c index 171a0bff38..ea30c37270 100644 --- a/drivers/net/mlx5/hws/mlx5dr_rule.c +++ b/drivers/net/mlx5/hws/mlx5dr_rule.c @@ -28,7 +28,7 @@ static void mlx5dr_rule_skip(struct mlx5dr_matcher *matcher, if (mt->item_flags & MLX5_FLOW_ITEM_REPRESENTED_PORT) { v = items[mt->vport_item_id].spec; - vport = flow_hw_conv_port_id(v->port_id); + vport = flow_hw_conv_port_id(matcher->tbl->ctx, v->port_id); if (unlikely(!vport)) { DR_LOG(ERR, "Fail to map port ID %d, ignoring", v->port_id); return; diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index 0a6d33f8ee..9619985450 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -2003,15 +2003,41 @@ flow_hw_get_port_id(void *dr_ctx) return UINT16_MAX; } +/* + * Get given eswitch manager id. + * Used in HWS match with port creation. + */ +static __rte_always_inline const struct flow_hw_port_info * +flow_hw_get_esw_mgr_id(void *dr_ctx) +{ +#if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) + uint16_t port_id; + + MLX5_ETH_FOREACH_DEV(port_id, NULL) { + struct mlx5_priv *priv; + + priv = rte_eth_devices[port_id].data->dev_private; + if (priv->dr_ctx == dr_ctx) + return &priv->sh->dev_cap.esw_info; + } +#else + RTE_SET_USED(dr_ctx); +#endif + return NULL; +} + /* * Get metadata match tag and mask for given rte_eth_dev port. * Used in HWS rule creation. */ static __rte_always_inline const struct flow_hw_port_info * -flow_hw_conv_port_id(const uint16_t port_id) +flow_hw_conv_port_id(void *ctx, const uint16_t port_id) { struct flow_hw_port_info *port_info; + if (port_id == UINT16_MAX && ctx) + return flow_hw_get_esw_mgr_id(ctx); + if (port_id >= RTE_MAX_ETHPORTS) return NULL; port_info = &mlx5_flow_hw_port_infos[port_id]; @@ -2037,7 +2063,7 @@ flow_hw_get_wire_port(struct ibv_context *ibctx) struct ibv_context *port_ibctx = priv->sh->cdev->ctx; if (port_ibctx->device == ibdev) - return flow_hw_conv_port_id(port_id); + return flow_hw_conv_port_id(priv->dr_ctx, port_id); } } return NULL; -- 2.34.1