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([10.145.170.182]) by orviesa004.jf.intel.com with ESMTP; 04 Jun 2024 01:48:47 -0700 From: Soumyadeep Hore To: bruce.richardson@intel.com, anatoly.burakov@intel.com Cc: dev@dpdk.org Subject: [PATCH v2 06/21] common/idpf: use BIT ULL for large bitmaps Date: Tue, 4 Jun 2024 08:05:56 +0000 Message-ID: <20240604080611.2197835-7-soumyadeep.hore@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240604080611.2197835-1-soumyadeep.hore@intel.com> References: <20240528072839.867100-1-soumyadeep.hore@intel.com> <20240604080611.2197835-1-soumyadeep.hore@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org For bitmaps greater than 32 bits, use BIT_ULL instead of BIT macro as reported by compiler. Signed-off-by: Soumyadeep Hore --- drivers/common/idpf/base/virtchnl2.h | 70 ++++++++++++++-------------- 1 file changed, 35 insertions(+), 35 deletions(-) diff --git a/drivers/common/idpf/base/virtchnl2.h b/drivers/common/idpf/base/virtchnl2.h index 6eff0f1ea1..851c6629dd 100644 --- a/drivers/common/idpf/base/virtchnl2.h +++ b/drivers/common/idpf/base/virtchnl2.h @@ -175,20 +175,20 @@ /* VIRTCHNL2_RSS_FLOW_TYPE_CAPS * Receive Side Scaling Flow type capability flags */ -#define VIRTCHNL2_CAP_RSS_IPV4_TCP BIT(0) -#define VIRTCHNL2_CAP_RSS_IPV4_UDP BIT(1) -#define VIRTCHNL2_CAP_RSS_IPV4_SCTP BIT(2) -#define VIRTCHNL2_CAP_RSS_IPV4_OTHER BIT(3) -#define VIRTCHNL2_CAP_RSS_IPV6_TCP BIT(4) -#define VIRTCHNL2_CAP_RSS_IPV6_UDP BIT(5) -#define VIRTCHNL2_CAP_RSS_IPV6_SCTP BIT(6) -#define VIRTCHNL2_CAP_RSS_IPV6_OTHER BIT(7) -#define VIRTCHNL2_CAP_RSS_IPV4_AH BIT(8) -#define VIRTCHNL2_CAP_RSS_IPV4_ESP BIT(9) -#define VIRTCHNL2_CAP_RSS_IPV4_AH_ESP BIT(10) -#define VIRTCHNL2_CAP_RSS_IPV6_AH BIT(11) -#define VIRTCHNL2_CAP_RSS_IPV6_ESP BIT(12) -#define VIRTCHNL2_CAP_RSS_IPV6_AH_ESP BIT(13) +#define VIRTCHNL2_CAP_RSS_IPV4_TCP BIT_ULL(0) +#define VIRTCHNL2_CAP_RSS_IPV4_UDP BIT_ULL(1) +#define VIRTCHNL2_CAP_RSS_IPV4_SCTP BIT_ULL(2) +#define VIRTCHNL2_CAP_RSS_IPV4_OTHER BIT_ULL(3) +#define VIRTCHNL2_CAP_RSS_IPV6_TCP BIT_ULL(4) +#define VIRTCHNL2_CAP_RSS_IPV6_UDP BIT_ULL(5) +#define VIRTCHNL2_CAP_RSS_IPV6_SCTP BIT_ULL(6) +#define VIRTCHNL2_CAP_RSS_IPV6_OTHER BIT_ULL(7) +#define VIRTCHNL2_CAP_RSS_IPV4_AH BIT_ULL(8) +#define VIRTCHNL2_CAP_RSS_IPV4_ESP BIT_ULL(9) +#define VIRTCHNL2_CAP_RSS_IPV4_AH_ESP BIT_ULL(10) +#define VIRTCHNL2_CAP_RSS_IPV6_AH BIT_ULL(11) +#define VIRTCHNL2_CAP_RSS_IPV6_ESP BIT_ULL(12) +#define VIRTCHNL2_CAP_RSS_IPV6_AH_ESP BIT_ULL(13) /* VIRTCHNL2_HEADER_SPLIT_CAPS * Header split capability flags @@ -214,32 +214,32 @@ * TX_VLAN: VLAN tag insertion * RX_VLAN: VLAN tag stripping */ -#define VIRTCHNL2_CAP_RDMA BIT(0) -#define VIRTCHNL2_CAP_SRIOV BIT(1) -#define VIRTCHNL2_CAP_MACFILTER BIT(2) -#define VIRTCHNL2_CAP_FLOW_DIRECTOR BIT(3) -#define VIRTCHNL2_CAP_SPLITQ_QSCHED BIT(4) -#define VIRTCHNL2_CAP_CRC BIT(5) -#define VIRTCHNL2_CAP_INLINE_FLOW_STEER BIT(6) -#define VIRTCHNL2_CAP_WB_ON_ITR BIT(7) -#define VIRTCHNL2_CAP_PROMISC BIT(8) -#define VIRTCHNL2_CAP_LINK_SPEED BIT(9) -#define VIRTCHNL2_CAP_INLINE_IPSEC BIT(10) -#define VIRTCHNL2_CAP_LARGE_NUM_QUEUES BIT(11) +#define VIRTCHNL2_CAP_RDMA BIT_ULL(0) +#define VIRTCHNL2_CAP_SRIOV BIT_ULL(1) +#define VIRTCHNL2_CAP_MACFILTER BIT_ULL(2) +#define VIRTCHNL2_CAP_FLOW_DIRECTOR BIT_ULL(3) +#define VIRTCHNL2_CAP_SPLITQ_QSCHED BIT_ULL(4) +#define VIRTCHNL2_CAP_CRC BIT_ULL(5) +#define VIRTCHNL2_CAP_INLINE_FLOW_STEER BIT_ULL(6) +#define VIRTCHNL2_CAP_WB_ON_ITR BIT_ULL(7) +#define VIRTCHNL2_CAP_PROMISC BIT_ULL(8) +#define VIRTCHNL2_CAP_LINK_SPEED BIT_ULL(9) +#define VIRTCHNL2_CAP_INLINE_IPSEC BIT_ULL(10) +#define VIRTCHNL2_CAP_LARGE_NUM_QUEUES BIT_ULL(11) /* require additional info */ -#define VIRTCHNL2_CAP_VLAN BIT(12) -#define VIRTCHNL2_CAP_PTP BIT(13) -#define VIRTCHNL2_CAP_ADV_RSS BIT(15) -#define VIRTCHNL2_CAP_FDIR BIT(16) -#define VIRTCHNL2_CAP_RX_FLEX_DESC BIT(17) -#define VIRTCHNL2_CAP_PTYPE BIT(18) -#define VIRTCHNL2_CAP_LOOPBACK BIT(19) +#define VIRTCHNL2_CAP_VLAN BIT_ULL(12) +#define VIRTCHNL2_CAP_PTP BIT_ULL(13) +#define VIRTCHNL2_CAP_ADV_RSS BIT_ULL(15) +#define VIRTCHNL2_CAP_FDIR BIT_ULL(16) +#define VIRTCHNL2_CAP_RX_FLEX_DESC BIT_ULL(17) +#define VIRTCHNL2_CAP_PTYPE BIT_ULL(18) +#define VIRTCHNL2_CAP_LOOPBACK BIT_ULL(19) /* Enable miss completion types plus ability to detect a miss completion if a * reserved bit is set in a standared completion's tag. */ -#define VIRTCHNL2_CAP_MISS_COMPL_TAG BIT(20) +#define VIRTCHNL2_CAP_MISS_COMPL_TAG BIT_ULL(20) /* this must be the last capability */ -#define VIRTCHNL2_CAP_OEM BIT(63) +#define VIRTCHNL2_CAP_OEM BIT_ULL(63) /* VIRTCHNL2_TXQ_SCHED_MODE * Transmit Queue Scheduling Modes - Queue mode is the legacy mode i.e. inorder -- 2.43.0