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From: Venkat Kumar Ande <venkatkumar.ande@amd.com>
To: <dev@dpdk.org>
Cc: <Selwin.Sebastian@amd.com>,
	Venkat Kumar Ande <VenkatKumar.Ande@amd.com>,
	 Selwin Sebastian <selwin.sebastian@amd.com>
Subject: [PATCH v3 21/25] net/axgbe: replace mii generic macro for c45 with AXGBE
Date: Tue, 4 Jun 2024 17:41:53 +0530	[thread overview]
Message-ID: <20240604121157.3052-21-venkatkumar.ande@amd.com> (raw)
In-Reply-To: <20240604121157.3052-1-venkatkumar.ande@amd.com>

From: Venkat Kumar Ande <VenkatKumar.Ande@amd.com>

The axgbe driver reuses MII_ADDR_C45 for its own purpose. The values
derived with it are never passed to phylib or a linux MDIO bus driver.
In order that MII_ADDR_C45 can be removed, add AXGBE specific macro.

Signed-off-by: Venkat Kumar Ande <VenkatKumar.Ande@amd.com>
Acked-by: Selwin Sebastian <selwin.sebastian@amd.com>
---
 drivers/net/axgbe/axgbe_common.h | 4 ++--
 drivers/net/axgbe/axgbe_dev.c    | 8 ++++----
 drivers/net/axgbe/axgbe_phy.h    | 2 +-
 3 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h
index 51532fb34a..1a43192630 100644
--- a/drivers/net/axgbe/axgbe_common.h
+++ b/drivers/net/axgbe/axgbe_common.h
@@ -1732,14 +1732,14 @@ do {									\
  */
 #define XMDIO_READ(_pdata, _mmd, _reg)					\
 	((_pdata)->hw_if.read_mmd_regs((_pdata), 0,			\
-		MII_ADDR_C45 | ((_mmd) << 16) | ((_reg) & 0xffff)))
+		AXGBE_ADDR_C45 | ((_mmd) << 16) | ((_reg) & 0xffff)))
 
 #define XMDIO_READ_BITS(_pdata, _mmd, _reg, _mask)			\
 	(XMDIO_READ((_pdata), _mmd, _reg) & _mask)
 
 #define XMDIO_WRITE(_pdata, _mmd, _reg, _val)				\
 	((_pdata)->hw_if.write_mmd_regs((_pdata), 0,			\
-		MII_ADDR_C45 | ((_mmd) << 16) | ((_reg) & 0xffff), (_val)))
+		AXGBE_ADDR_C45 | ((_mmd) << 16) | ((_reg) & 0xffff), (_val)))
 
 #define XMDIO_WRITE_BITS(_pdata, _mmd, _reg, _mask, _val)		\
 do {									\
diff --git a/drivers/net/axgbe/axgbe_dev.c b/drivers/net/axgbe/axgbe_dev.c
index fa7324efa7..ebe64295aa 100644
--- a/drivers/net/axgbe/axgbe_dev.c
+++ b/drivers/net/axgbe/axgbe_dev.c
@@ -207,8 +207,8 @@ static int axgbe_read_mmd_regs_v2(struct axgbe_port *pdata,
 	unsigned int mmd_address, index, offset;
 	int mmd_data;
 
-	if (mmd_reg & MII_ADDR_C45)
-		mmd_address = mmd_reg & ~MII_ADDR_C45;
+	if (mmd_reg & AXGBE_ADDR_C45)
+		mmd_address = mmd_reg & ~AXGBE_ADDR_C45;
 	else
 		mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff);
 
@@ -241,8 +241,8 @@ static void axgbe_write_mmd_regs_v2(struct axgbe_port *pdata,
 {
 	unsigned int mmd_address, index, offset;
 
-	if (mmd_reg & MII_ADDR_C45)
-		mmd_address = mmd_reg & ~MII_ADDR_C45;
+	if (mmd_reg & AXGBE_ADDR_C45)
+		mmd_address = mmd_reg & ~AXGBE_ADDR_C45;
 	else
 		mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff);
 
diff --git a/drivers/net/axgbe/axgbe_phy.h b/drivers/net/axgbe/axgbe_phy.h
index 5b844e81cd..eee3afc370 100644
--- a/drivers/net/axgbe/axgbe_phy.h
+++ b/drivers/net/axgbe/axgbe_phy.h
@@ -16,7 +16,7 @@
 /* Or MII_ADDR_C45 into regnum for read/write on mii_bus to enable the 21 bit
  * IEEE 802.3ae clause 45 addressing mode used by 10GIGE phy chips.
  */
-#define MII_ADDR_C45 (1 << 30)
+#define AXGBE_ADDR_C45  (1 << 30)
 
 /* Basic mode status register. */
 #define BMSR_LSTATUS            0x0004  /* Link status */
-- 
2.34.1


  parent reply	other threads:[~2024-06-04 12:14 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <20240507124305.2318-1-VenkatKumar.Ande@amd.com>
2024-06-04 12:11 ` [PATCH v3 01/25] net/axgbe: fix mdio access for non-zero ports and CL45 PHYs Venkat Kumar Ande
2024-06-04 12:11   ` [PATCH v3 02/25] net/axgbe: reset link when the link never comes back Venkat Kumar Ande
2024-06-04 12:11   ` [PATCH v3 03/25] net/axgbe: fix fluctuations for 1G BELFUSE SFP Venkat Kumar Ande
2024-06-04 12:11   ` [PATCH v3 04/25] net/axgbe: update DMA coherency values Venkat Kumar Ande
2024-06-04 12:11   ` [PATCH v3 05/25] net/axgbe: disable interrupts during device removal Venkat Kumar Ande
2024-06-04 12:11   ` [PATCH v3 06/25] net/axgbe: yellow carp devices do not need rrc Venkat Kumar Ande
2024-06-04 12:11   ` [PATCH v3 07/25] net/axgbe: enable PLL control for fixed PHY modes only Venkat Kumar Ande
2024-06-04 12:11   ` [PATCH v3 08/25] net/axgbe: fix the SFP codes check for DAC cables Venkat Kumar Ande
2024-06-04 12:11   ` [PATCH v3 09/25] net/axgbe: fix logic around active and passive cables Venkat Kumar Ande
2024-06-04 12:11   ` [PATCH v3 10/25] net/axgbe: check only the minimum speed for cables Venkat Kumar Ande
2024-06-04 12:11   ` [PATCH v3 11/25] net/axgbe: flow Tx Ctrl Registers are h/w version dependent Venkat Kumar Ande
2024-06-04 12:11   ` [PATCH v3 12/25] net/axgbe: delay AN timeout during KR training Venkat Kumar Ande
2024-06-04 12:11   ` [PATCH v3 13/25] net/axgbe: fix the false linkup in axgbe PHY status Venkat Kumar Ande
2024-06-04 12:11   ` [PATCH v3 14/25] net/axgbe: remove use of comm owned field Venkat Kumar Ande
2024-06-04 12:11   ` [PATCH v3 15/25] net/axgbe: remove field of SFP diagnostic support Venkat Kumar Ande
2024-06-04 12:11   ` [PATCH v3 16/25] net/axgbe: improve SFP 100Mbps auto-negotiation Venkat Kumar Ande
2024-06-04 12:11   ` [PATCH v3 17/25] net/axgbe: remove unnecessary conversion to bool Venkat Kumar Ande
2024-06-04 12:11   ` [PATCH v3 18/25] net/axgbe: use definitions for mailbox commands Venkat Kumar Ande
2024-06-04 12:11   ` [PATCH v3 19/25] net/axgbe: add support for 10 Mbps speed Venkat Kumar Ande
2024-06-04 12:11   ` [PATCH v3 20/25] net/axgbe: separate C22 and C45 transactions Venkat Kumar Ande
2024-06-04 12:11   ` Venkat Kumar Ande [this message]
2024-06-04 12:11   ` [PATCH v3 22/25] net/axgbe: add 2.5GbE support to 10G BaseT mode Venkat Kumar Ande
2024-06-04 12:11   ` [PATCH v3 23/25] net/axgbe: add support for Rx adaptation Venkat Kumar Ande
2024-06-04 12:11   ` [PATCH v3 24/25] net/axgbe: extend 10Mbps support to MAC version 21H Venkat Kumar Ande
2024-06-04 12:11   ` [PATCH v3 25/25] net/axgbe: modify debug messages Venkat Kumar Ande
2024-06-05 17:07   ` [PATCH v3 01/25] net/axgbe: fix mdio access for non-zero ports and CL45 PHYs Ferruh Yigit

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