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CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(82310400017)(1800799015)(376005)(36860700004); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Jun 2024 12:13:28.6935 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 880ede96-0330-4e56-e03a-08dc848fbe48 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B372.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8510 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Venkat Kumar Ande The axgbe driver reuses MII_ADDR_C45 for its own purpose. The values derived with it are never passed to phylib or a linux MDIO bus driver. In order that MII_ADDR_C45 can be removed, add AXGBE specific macro. Signed-off-by: Venkat Kumar Ande Acked-by: Selwin Sebastian --- drivers/net/axgbe/axgbe_common.h | 4 ++-- drivers/net/axgbe/axgbe_dev.c | 8 ++++---- drivers/net/axgbe/axgbe_phy.h | 2 +- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h index 51532fb34a..1a43192630 100644 --- a/drivers/net/axgbe/axgbe_common.h +++ b/drivers/net/axgbe/axgbe_common.h @@ -1732,14 +1732,14 @@ do { \ */ #define XMDIO_READ(_pdata, _mmd, _reg) \ ((_pdata)->hw_if.read_mmd_regs((_pdata), 0, \ - MII_ADDR_C45 | ((_mmd) << 16) | ((_reg) & 0xffff))) + AXGBE_ADDR_C45 | ((_mmd) << 16) | ((_reg) & 0xffff))) #define XMDIO_READ_BITS(_pdata, _mmd, _reg, _mask) \ (XMDIO_READ((_pdata), _mmd, _reg) & _mask) #define XMDIO_WRITE(_pdata, _mmd, _reg, _val) \ ((_pdata)->hw_if.write_mmd_regs((_pdata), 0, \ - MII_ADDR_C45 | ((_mmd) << 16) | ((_reg) & 0xffff), (_val))) + AXGBE_ADDR_C45 | ((_mmd) << 16) | ((_reg) & 0xffff), (_val))) #define XMDIO_WRITE_BITS(_pdata, _mmd, _reg, _mask, _val) \ do { \ diff --git a/drivers/net/axgbe/axgbe_dev.c b/drivers/net/axgbe/axgbe_dev.c index fa7324efa7..ebe64295aa 100644 --- a/drivers/net/axgbe/axgbe_dev.c +++ b/drivers/net/axgbe/axgbe_dev.c @@ -207,8 +207,8 @@ static int axgbe_read_mmd_regs_v2(struct axgbe_port *pdata, unsigned int mmd_address, index, offset; int mmd_data; - if (mmd_reg & MII_ADDR_C45) - mmd_address = mmd_reg & ~MII_ADDR_C45; + if (mmd_reg & AXGBE_ADDR_C45) + mmd_address = mmd_reg & ~AXGBE_ADDR_C45; else mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); @@ -241,8 +241,8 @@ static void axgbe_write_mmd_regs_v2(struct axgbe_port *pdata, { unsigned int mmd_address, index, offset; - if (mmd_reg & MII_ADDR_C45) - mmd_address = mmd_reg & ~MII_ADDR_C45; + if (mmd_reg & AXGBE_ADDR_C45) + mmd_address = mmd_reg & ~AXGBE_ADDR_C45; else mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); diff --git a/drivers/net/axgbe/axgbe_phy.h b/drivers/net/axgbe/axgbe_phy.h index 5b844e81cd..eee3afc370 100644 --- a/drivers/net/axgbe/axgbe_phy.h +++ b/drivers/net/axgbe/axgbe_phy.h @@ -16,7 +16,7 @@ /* Or MII_ADDR_C45 into regnum for read/write on mii_bus to enable the 21 bit * IEEE 802.3ae clause 45 addressing mode used by 10GIGE phy chips. */ -#define MII_ADDR_C45 (1 << 30) +#define AXGBE_ADDR_C45 (1 << 30) /* Basic mode status register. */ #define BMSR_LSTATUS 0x0004 /* Link status */ -- 2.34.1