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([85.172.100.87]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-52ca28720a1sm1030208e87.141.2024.06.16.10.39.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Jun 2024 10:39:13 -0700 (PDT) From: Igor Gutorov To: dsosnowski@nvidia.com, viacheslavo@nvidia.com, orika@nvidia.com, suanmingm@nvidia.com, matan@nvidia.com Cc: dev@dpdk.org, Igor Gutorov Subject: [PATCH 1/1] net/mlx5: show rx/tx descriptor ring limitations in rte_eth_dev_info Date: Sun, 16 Jun 2024 20:38:03 +0300 Message-ID: <20240616173803.424025-2-igootorov@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240616173803.424025-1-igootorov@gmail.com> References: <20240616173803.424025-1-igootorov@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Currently, rte_eth_dev_info.rx_desc_lim.nb_max shows 65535 as a limit, which results in a few problems: * It is an incorrect value * Allocating an RX queue and passing `rx_desc_lim.nb_max` results in an integer overflow and 0 ring size: ``` rte_eth_rx_queue_setup(0, 0, rx_desc_lim.nb_max, 0, NULL, mb_pool); ``` Which overflows ring size and generates the following log: ``` mlx5_net: port 0 increased number of descriptors in Rx queue 0 to the next power of two (0) ``` This patch fixes these issues. Signed-off-by: Igor Gutorov --- drivers/net/mlx5/mlx5_defs.h | 3 +++ drivers/net/mlx5/mlx5_ethdev.c | 5 ++++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/net/mlx5/mlx5_defs.h b/drivers/net/mlx5/mlx5_defs.h index dc5216cb24..df608f0921 100644 --- a/drivers/net/mlx5/mlx5_defs.h +++ b/drivers/net/mlx5/mlx5_defs.h @@ -84,6 +84,9 @@ #define MLX5_RX_DEFAULT_BURST 64U #define MLX5_TX_DEFAULT_BURST 64U +/* Maximum number of descriptors in an RX/TX ring */ +#define MLX5_MAX_RING_DESC 8192 + /* Number of packets vectorized Rx can simultaneously process in a loop. */ #define MLX5_VPMD_DESCS_PER_LOOP 4 diff --git a/drivers/net/mlx5/mlx5_ethdev.c b/drivers/net/mlx5/mlx5_ethdev.c index aea799341c..d5be1ff1aa 100644 --- a/drivers/net/mlx5/mlx5_ethdev.c +++ b/drivers/net/mlx5/mlx5_ethdev.c @@ -22,6 +22,7 @@ #include +#include "mlx5_defs.h" #include "mlx5_rxtx.h" #include "mlx5_rx.h" #include "mlx5_tx.h" @@ -345,6 +346,8 @@ mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info) info->flow_type_rss_offloads = ~MLX5_RSS_HF_MASK; mlx5_set_default_params(dev, info); mlx5_set_txlimit_params(dev, info); + info->rx_desc_lim.nb_max = MLX5_MAX_RING_DESC; + info->tx_desc_lim.nb_max = MLX5_MAX_RING_DESC; if (priv->sh->cdev->config.hca_attr.mem_rq_rmp && priv->obj_ops.rxq_obj_new == devx_obj_ops.rxq_obj_new) info->dev_capa |= RTE_ETH_DEV_CAPA_RXQ_SHARE; @@ -774,7 +777,7 @@ mlx5_hairpin_cap_get(struct rte_eth_dev *dev, struct rte_eth_hairpin_cap *cap) cap->max_nb_queues = UINT16_MAX; cap->max_rx_2_tx = 1; cap->max_tx_2_rx = 1; - cap->max_nb_desc = 8192; + cap->max_nb_desc = MLX5_MAX_RING_DESC; hca_attr = &priv->sh->cdev->config.hca_attr; cap->rx_cap.locked_device_memory = hca_attr->hairpin_data_buffer_locked; cap->rx_cap.rte_memory = 0; -- 2.45.2