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From: Daniel Gregory <daniel.gregory@bytedance.com>
To: Stanislaw Kardach <stanislaw.kardach@gmail.com>,
Bruce Richardson <bruce.richardson@intel.com>
Cc: dev@dpdk.org, Liang Ma <liangma@liangbit.com>,
Punit Agrawal <punit.agrawal@bytedance.com>,
Pengcheng Wang <wangpengcheng.pp@bytedance.com>,
Chunsong Feng <fengchunsong@bytedance.com>,
Daniel Gregory <daniel.gregory@bytedance.com>
Subject: [PATCH 1/5] config/riscv: add flag for using Zbc extension
Date: Tue, 18 Jun 2024 18:41:29 +0100
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The RISC-V Zbc extension adds carry-less multiply instructions we can
use to implement more efficient CRC hashing algorithms.
Signed-off-by: Daniel Gregory <daniel.gregory@bytedance.com>
---
config/riscv/meson.build | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/config/riscv/meson.build b/config/riscv/meson.build
index 07d7d9da23..4bda4089bd 100644
--- a/config/riscv/meson.build
+++ b/config/riscv/meson.build
@@ -26,6 +26,13 @@ flags_common = [
# read from /proc/device-tree/cpus/timebase-frequency. This property is
# guaranteed on Linux, as riscv time_init() requires it.
['RTE_RISCV_TIME_FREQ', 0],
+
+ # Use RISC-V Carry-less multiplication extension (Zbc) for hardware
+ # implementations of CRC-32C (lib/hash/rte_crc_riscv64.h), CRC-32 and CRC-16
+ # (lib/net/net_crc_zbc.c). Requires intrinsics available in GCC 14.1.0+ and
+ # Clang 18.1.0+
+ # Make sure to add '_zbc' to your target's -march below
+ ['RTE_RISCV_ZBC', false],
]
## SoC-specific options.
--
2.39.2