From: Wathsala Vithanage <wathsala.vithanage@arm.com>
To: Thomas Monjalon <thomas@monjalon.net>,
Tyler Retzlaff <roretzla@linux.microsoft.com>,
Ruifeng Wang <ruifeng.wang@arm.com>
Cc: dev@dpdk.org, nd@arm.com,
Wathsala Vithanage <wathsala.vithanage@arm.com>,
Dhruv Tripathi <dhruv.tripathi@arm.com>,
Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>,
Jack Bond-Preston <jack.bond-preston@foss.arm.com>,
Nick Connolly <nick.connolly@arm.com>,
Vinod Krishna <vinod.krishna@arm.com>
Subject: [PATCH v2 2/2] eal: add Arm WFET in power management intrinsics
Date: Wed, 19 Jun 2024 06:45:28 +0000 [thread overview]
Message-ID: <20240619064529.619526-2-wathsala.vithanage@arm.com> (raw)
In-Reply-To: <20240619064529.619526-1-wathsala.vithanage@arm.com>
Wait for event with timeout (WFET) puts the CPU in a low power
mode and stays there until an event is signalled (SEV), loss of
an exclusive monitor or a timeout.
WFET is enabled selectively by checking FEAT_WFxT in Linux
auxiliary vector. If FEAT_WFxT is not available power management
will fallback to WFE.
RTE_ARM_USE_WFE macro is not required to enable WFE feature for
PMD power monitoring.
Signed-off-by: Wathsala Vithanage <wathsala.vithanage@arm.com>
Reviewed-by: Dhruv Tripathi <dhruv.tripathi@arm.com>
Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
Reviewed-by: Jack Bond-Preston <jack.bond-preston@foss.arm.com>
Reviewed-by: Nick Connolly <nick.connolly@arm.com>
Reviewed-by: Vinod Krishna <vinod.krishna@arm.com>
---
.mailmap | 2 ++
app/test/test_cpuflags.c | 3 ++
lib/eal/arm/include/rte_cpuflags_64.h | 1 +
lib/eal/arm/include/rte_pause_64.h | 21 ++++++++++---
lib/eal/arm/rte_cpuflags.c | 3 +-
lib/eal/arm/rte_power_intrinsics.c | 45 +++++++++++++++++----------
6 files changed, 52 insertions(+), 23 deletions(-)
diff --git a/.mailmap b/.mailmap
index 3843868716..31995d492d 100644
--- a/.mailmap
+++ b/.mailmap
@@ -332,6 +332,7 @@ Dexia Li <dexia.li@jaguarmicro.com>
Dexuan Cui <decui@microsoft.com>
Dharmik Thakkar <dharmikjayesh.thakkar@arm.com> <dharmik.thakkar@arm.com>
Dheemanth Mallikarjun <dheemanthm@vmware.com>
+Dhruv Tripathi <dhruv.tripathi@arm.com>
Diana Wang <na.wang@corigine.com>
Didier Pallard <didier.pallard@6wind.com>
Dilshod Urazov <dilshod.urazov@oktetlabs.ru>
@@ -1516,6 +1517,7 @@ Vincent Jardin <vincent.jardin@6wind.com>
Vincent Li <vincent.mc.li@gmail.com>
Vincent S. Cojot <vcojot@redhat.com>
Vinh Tran <vinh.t.tran10@gmail.com>
+Vinod Krishna <vinod.krishna@arm.com>
Vipin Varghese <vipin.varghese@amd.com> <vipin.varghese@intel.com>
Vipul Ashri <vipul.ashri@oracle.com>
Visa Hankala <visa@hankala.org>
diff --git a/app/test/test_cpuflags.c b/app/test/test_cpuflags.c
index a0ff74720c..22ab4dff0a 100644
--- a/app/test/test_cpuflags.c
+++ b/app/test/test_cpuflags.c
@@ -156,6 +156,9 @@ test_cpuflags(void)
printf("Check for SVEBF16:\t");
CHECK_FOR_FLAG(RTE_CPUFLAG_SVEBF16);
+
+ printf("Check for WFXT:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_WFXT);
#endif
#if defined(RTE_ARCH_X86_64) || defined(RTE_ARCH_I686)
diff --git a/lib/eal/arm/include/rte_cpuflags_64.h b/lib/eal/arm/include/rte_cpuflags_64.h
index afe70209c3..1945a97ca1 100644
--- a/lib/eal/arm/include/rte_cpuflags_64.h
+++ b/lib/eal/arm/include/rte_cpuflags_64.h
@@ -36,6 +36,7 @@ enum rte_cpu_flag_t {
RTE_CPUFLAG_SVEF64MM,
RTE_CPUFLAG_SVEBF16,
RTE_CPUFLAG_AARCH64,
+ RTE_CPUFLAG_WFXT,
};
#include "generic/rte_cpuflags.h"
diff --git a/lib/eal/arm/include/rte_pause_64.h b/lib/eal/arm/include/rte_pause_64.h
index 5cb8b59056..f732407425 100644
--- a/lib/eal/arm/include/rte_pause_64.h
+++ b/lib/eal/arm/include/rte_pause_64.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: BSD-3-Clause
* Copyright(c) 2017 Cavium, Inc
- * Copyright(c) 2019 Arm Limited
+ * Copyright(c) 2024 Arm Limited
*/
#ifndef _RTE_PAUSE_ARM64_H_
@@ -23,17 +23,28 @@ static inline void rte_pause(void)
asm volatile("yield" ::: "memory");
}
-#ifdef RTE_WAIT_UNTIL_EQUAL_ARCH_DEFINED
-/* Send a local event to quit WFE. */
+/* Send a local event to quit WFE/WFxT. */
#define __RTE_ARM_SEVL() { asm volatile("sevl" : : : "memory"); }
-/* Send a global event to quit WFE for all cores. */
+/* Send a global event to quit WFE/WFxT for all cores. */
#define __RTE_ARM_SEV() { asm volatile("sev" : : : "memory"); }
/* Put processor into low power WFE(Wait For Event) state. */
#define __RTE_ARM_WFE() { asm volatile("wfe" : : : "memory"); }
+/* Put processor into low power WFET (WFE with Timeout) state. */
+#ifdef RTE_ARM_FEATURE_WFXT
+#define __RTE_ARM_WFET(t) { \
+ asm volatile("wfet %x[to]" \
+ : \
+ : [to] "r" (t) \
+ : "memory"); \
+ }
+#else
+#define __RTE_ARM_WFET(t) { RTE_SET_USED(t); }
+#endif
+
/*
* Atomic exclusive load from addr, it returns the 8-bit content of
* *addr while making it 'monitored', when it is written by someone
@@ -147,6 +158,8 @@ static inline void rte_pause(void)
__RTE_ARM_LOAD_EXC_128(src, dst, memorder) \
}
+#ifdef RTE_WAIT_UNTIL_EQUAL_ARCH_DEFINED
+
static __rte_always_inline void
rte_wait_until_equal_16(volatile uint16_t *addr, uint16_t expected,
int memorder)
diff --git a/lib/eal/arm/rte_cpuflags.c b/lib/eal/arm/rte_cpuflags.c
index 7ba4f8ba97..ad76f2448b 100644
--- a/lib/eal/arm/rte_cpuflags.c
+++ b/lib/eal/arm/rte_cpuflags.c
@@ -115,6 +115,7 @@ const struct feature_entry rte_cpu_feature_table[] = {
FEAT_DEF(SVEF32MM, REG_HWCAP2, 10)
FEAT_DEF(SVEF64MM, REG_HWCAP2, 11)
FEAT_DEF(SVEBF16, REG_HWCAP2, 12)
+ FEAT_DEF(WFXT, REG_HWCAP2, 31)
FEAT_DEF(AARCH64, REG_PLATFORM, 0)
};
#endif /* RTE_ARCH */
@@ -163,7 +164,5 @@ void
rte_cpu_get_intrinsics_support(struct rte_cpu_intrinsics *intrinsics)
{
memset(intrinsics, 0, sizeof(*intrinsics));
-#ifdef RTE_ARM_USE_WFE
intrinsics->power_monitor = 1;
-#endif
}
diff --git a/lib/eal/arm/rte_power_intrinsics.c b/lib/eal/arm/rte_power_intrinsics.c
index f54cf59e80..fc7a0c61f0 100644
--- a/lib/eal/arm/rte_power_intrinsics.c
+++ b/lib/eal/arm/rte_power_intrinsics.c
@@ -4,20 +4,31 @@
#include <errno.h>
+#include "rte_cpuflags.h"
#include "rte_power_intrinsics.h"
/**
- * This function uses WFE instruction to make lcore suspend
+ * Set wfet_en if WFET is supported
+ */
+uint8_t wfet_en;
+
+RTE_INIT(rte_power_intrinsics_init)
+{
+#ifdef RTE_ARCH_64
+ if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_WFXT))
+ wfet_en = 1;
+#endif
+}
+
+/**
+ * This function uses WFE/WFET instruction to make lcore suspend
* execution on ARM.
- * Note that timestamp based timeout is not supported yet.
*/
int
rte_power_monitor(const struct rte_power_monitor_cond *pmc,
const uint64_t tsc_timestamp)
{
- RTE_SET_USED(tsc_timestamp);
-
-#ifdef RTE_ARM_USE_WFE
+#ifdef RTE_ARCH_64
const unsigned int lcore_id = rte_lcore_id();
uint64_t cur_value;
@@ -33,28 +44,30 @@ rte_power_monitor(const struct rte_power_monitor_cond *pmc,
switch (pmc->size) {
case sizeof(uint8_t):
- __RTE_ARM_LOAD_EXC_8(pmc->addr, cur_value, rte_memory_order_relaxed)
- __RTE_ARM_WFE()
+ __RTE_ARM_LOAD_EXC_8(pmc->addr, cur_value, rte_memory_order_relaxed);
break;
case sizeof(uint16_t):
- __RTE_ARM_LOAD_EXC_16(pmc->addr, cur_value, rte_memory_order_relaxed)
- __RTE_ARM_WFE()
+ __RTE_ARM_LOAD_EXC_16(pmc->addr, cur_value, rte_memory_order_relaxed);
break;
case sizeof(uint32_t):
- __RTE_ARM_LOAD_EXC_32(pmc->addr, cur_value, rte_memory_order_relaxed)
- __RTE_ARM_WFE()
+ __RTE_ARM_LOAD_EXC_32(pmc->addr, cur_value, rte_memory_order_relaxed);
break;
case sizeof(uint64_t):
- __RTE_ARM_LOAD_EXC_64(pmc->addr, cur_value, rte_memory_order_relaxed)
- __RTE_ARM_WFE()
+ __RTE_ARM_LOAD_EXC_64(pmc->addr, cur_value, rte_memory_order_relaxed);
break;
default:
return -EINVAL; /* unexpected size */
}
+ if (wfet_en)
+ __RTE_ARM_WFET(tsc_timestamp)
+ else
+ __RTE_ARM_WFE()
+
return 0;
#else
RTE_SET_USED(pmc);
+ RTE_SET_USED(tsc_timestamp);
return -ENOTSUP;
#endif
@@ -80,10 +93,8 @@ int
rte_power_monitor_wakeup(const unsigned int lcore_id)
{
RTE_SET_USED(lcore_id);
-
-#ifdef RTE_ARM_USE_WFE
- __RTE_ARM_SEV()
-
+#ifdef RTE_ARCH_64
+ __RTE_ARM_SEV();
return 0;
#else
return -ENOTSUP;
--
2.34.1
next prev parent reply other threads:[~2024-06-19 6:46 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-04 4:44 [PATCH 1/2] config/arm: adds Arm Neoverse N3 SoC Wathsala Vithanage
2024-06-04 4:44 ` [PATCH 2/2] eal: add Arm WFET in power management intrinsics Wathsala Vithanage
2024-06-04 15:41 ` Stephen Hemminger
2024-06-19 6:45 ` [PATCH v2 1/2] config/arm: adds Arm Neoverse N3 SoC Wathsala Vithanage
2024-06-19 6:45 ` Wathsala Vithanage [this message]
2024-06-27 15:30 ` [PATCH v2 2/2] eal: add Arm WFET in power management intrinsics Thomas Monjalon
2024-07-01 21:34 ` Wathsala Wathawana Vithanage
2024-07-02 8:29 ` Thomas Monjalon
2024-07-03 13:27 ` Wathsala Wathawana Vithanage
2024-07-03 13:33 ` Thomas Monjalon
2024-07-03 16:58 ` Wathsala Wathawana Vithanage
2024-07-04 10:55 ` Pavan Nikhilesh Bhagavatula
2024-07-04 14:14 ` Thomas Monjalon
2024-07-04 14:55 ` Stephen Hemminger
2024-07-04 18:59 ` Thomas Monjalon
2024-07-05 16:10 ` [EXTERNAL] " Pavan Nikhilesh Bhagavatula
2024-07-07 17:37 ` [EXTERNAL] " Honnappa Nagarahalli
2024-07-05 16:01 ` Wathsala Wathawana Vithanage
2024-07-05 16:11 ` Pavan Nikhilesh Bhagavatula
2024-07-05 16:25 ` Wathsala Wathawana Vithanage
2024-07-03 16:19 ` Wathsala Wathawana Vithanage
2024-07-15 22:53 ` [PATCH v3 1/4] eal: expand the availability of WFE and related instructions Wathsala Vithanage
2024-07-15 22:53 ` [PATCH v3 2/4] config/arm: adds Arm Neoverse N3 SoC Wathsala Vithanage
2024-07-16 1:52 ` Honnappa Nagarahalli
2024-07-15 22:53 ` [PATCH v3 3/4] eal: add Arm WFET in power management intrinsics Wathsala Vithanage
2024-07-15 22:53 ` [PATCH v3 4/4] eal: describe Arm CPU features including WFXT Wathsala Vithanage
2024-07-16 1:02 ` Honnappa Nagarahalli
2024-07-26 17:15 ` [PATCH v4 1/4] eal: expand the availability of WFE and related instructions Wathsala Vithanage
2024-07-26 17:15 ` [PATCH v4 2/4] config/arm: adds Arm Neoverse N3 SoC Wathsala Vithanage
2024-07-26 17:15 ` [PATCH v4 3/4] eal: add Arm WFET in power management intrinsics Wathsala Vithanage
2024-10-10 17:01 ` Thomas Monjalon
2024-07-26 17:15 ` [PATCH v4 4/4] eal: describe Arm CPU features including WFXT Wathsala Vithanage
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