From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id DDB31454A7; Mon, 24 Jun 2024 08:32:17 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6F3E240691; Mon, 24 Jun 2024 08:31:39 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 88ADC4027B for ; Mon, 24 Jun 2024 08:24:23 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 45NMnWjR008017 for ; Sun, 23 Jun 2024 23:24:23 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=a TTQcuQo2SoOp91Df3kBi0eMhRJCylEaSuEIs4wUckc=; b=UHP6RQycXK3q84h22 +pIk6BgLF1XmABsIrPO0IBCZxHoRla51E9670I61TZS1myX/vVrKMfQqo29ZSiZc tUk6sJ0BsDQ+vnfgbfluLA7x9Rv4VhDA1HLr1JlcPtenlcKYQn8iAthbHDM2yZRR KUWbOjpDIPNJVAHPDmj2NRd6MkGL0kaStF4oUTx0Zt0JeDZWewnng3f/l3/B7A5h dzWmwsxS77XQnf+AbbnmeEonNaS80i6mw9ZOLsZGBn/C9OVzk+DZ1dJZ0LwxqMlY Ks828qCN6/qR5Kp05vMILJJniASu21HNRvL4WEnBDpPq/NUqf/q1GWN9i8FURuNs VbQyw== Received: from dc5-exch05.marvell.com ([199.233.59.128]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3ywx4gbp78-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Sun, 23 Jun 2024 23:24:22 -0700 (PDT) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Sun, 23 Jun 2024 23:24:21 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Sun, 23 Jun 2024 23:24:21 -0700 Received: from localhost.localdomain (unknown [10.28.36.177]) by maili.marvell.com (Postfix) with ESMTP id F3BA53F7040; Sun, 23 Jun 2024 23:24:18 -0700 (PDT) From: Aakash Sasidharan To: Ankur Dwivedi , Anoob Joseph , Tejasree Kondoj CC: , , , , Subject: [PATCH v2 05/12] crypto/cnxk: use SSO PF func of inline device in inst Date: Mon, 24 Jun 2024 11:53:54 +0530 Message-ID: <20240624062401.4143606-6-asasidharan@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240624062401.4143606-1-asasidharan@marvell.com> References: <20240620145848.3461844-1-asasidharan@marvell.com> <20240624062401.4143606-1-asasidharan@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: _FKqBnwDl2UwrxsFjgsHLAHsNwgh1-Sh X-Proofpoint-ORIG-GUID: _FKqBnwDl2UwrxsFjgsHLAHsNwgh1-Sh X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-24_05,2024-06-21_01,2024-05-17_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Anoob Joseph RVU PF FUNC of the CPT LF need not be set as the hardware would determine that. Instead SSO PF FUNC need to be set as inline device so that critical errors would reach inline device. Signed-off-by: Anoob Joseph --- drivers/crypto/cnxk/cn10k_cryptodev_ops.c | 2 +- drivers/crypto/cnxk/cnxk_cryptodev.h | 2 +- drivers/crypto/cnxk/cnxk_cryptodev_ops.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c index 9f1c074925..f2980399c5 100644 --- a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c +++ b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c @@ -1418,7 +1418,7 @@ cn10k_cryptodev_sec_inb_rx_inject(void *dev, struct rte_mbuf **pkts, fc_addr = vf->rx_inj_lmtline.fc_addr; ROC_LMT_BASE_ID_GET(lmt_base, lmt_id); - pf_func = vf->rx_inj_pf_func; + pf_func = vf->rx_inj_sso_pf_func; const uint32_t fc_thresh = vf->rx_inj_lmtline.fc_thresh; diff --git a/drivers/crypto/cnxk/cnxk_cryptodev.h b/drivers/crypto/cnxk/cnxk_cryptodev.h index fffc4a47b4..4000e84a7e 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev.h +++ b/drivers/crypto/cnxk/cnxk_cryptodev.h @@ -22,7 +22,7 @@ */ struct cnxk_cpt_vf { struct roc_cpt_lmtline rx_inj_lmtline; - uint16_t rx_inj_pf_func; + uint16_t rx_inj_sso_pf_func; uint16_t *rx_chan_base; struct roc_cpt cpt; struct rte_cryptodev_capabilities crypto_caps[CNXK_CPT_MAX_CAPS]; diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c index d7f5780637..51369309c5 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c +++ b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c @@ -483,7 +483,7 @@ cnxk_cpt_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id, goto exit; } - vf->rx_inj_pf_func = qp->lf.pf_func; + vf->rx_inj_sso_pf_func = roc_idev_nix_inl_dev_pffunc_get(); /* Block the queue for other submissions */ qp->pend_q.pq_mask = 0; -- 2.25.1