From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C01A4454A7; Mon, 24 Jun 2024 08:32:25 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9B1AD40A87; Mon, 24 Jun 2024 08:31:40 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id C34B54027B for ; Mon, 24 Jun 2024 08:24:26 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 45NMe8IW025560 for ; Sun, 23 Jun 2024 23:24:26 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=7 wf5vZFMdC7Jnn+O4xZg8c9VDxVNddLoGsazSIkGqyg=; b=XLWS3kiIg1WWPWNqE Pl1p9amyiaxG4gRZI6Ibv0LamFafDEp9q0MxryWGknXnp16VR2QX2yqBkRuJv6R3 mkVya12YIFBGtV/J7VFznzPKpjcegUPZ6kdTHRvhGrr13Nq0LWSNdielZeeK0ARz EqxByt6CJbxGYZZ3fDMVRs2O+2w1EoQehV0rnzB5lOBXt+5t9HliSOnkdJOHpmLA pZDxwZUPCn7DH/wVKqOPmBbqp2iWnu8oqmA/d7WV4K3edw6MeyCw8zgCWBn/rhT3 OdmOkVfVjM5gkGdFfuc+ekaCWuAbsNAW/jud/6LuR7PIKrVX2HCIaYzQqMKb2tOQ twq1w== Received: from dc5-exch05.marvell.com ([199.233.59.128]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3ywx4gbp7g-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Sun, 23 Jun 2024 23:24:26 -0700 (PDT) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Sun, 23 Jun 2024 23:24:24 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Sun, 23 Jun 2024 23:24:24 -0700 Received: from localhost.localdomain (unknown [10.28.36.177]) by maili.marvell.com (Postfix) with ESMTP id 19BB23F7040; Sun, 23 Jun 2024 23:24:21 -0700 (PDT) From: Aakash Sasidharan To: Ankur Dwivedi , Anoob Joseph , Tejasree Kondoj CC: , , , , Subject: [PATCH v2 06/12] crypto/cnxk: use NEON for Rx inject inst preparation Date: Mon, 24 Jun 2024 11:53:55 +0530 Message-ID: <20240624062401.4143606-7-asasidharan@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240624062401.4143606-1-asasidharan@marvell.com> References: <20240620145848.3461844-1-asasidharan@marvell.com> <20240624062401.4143606-1-asasidharan@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: SUtQIhRHTzP81GKq2GVrEZTymrs94YR0 X-Proofpoint-ORIG-GUID: SUtQIhRHTzP81GKq2GVrEZTymrs94YR0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-24_05,2024-06-21_01,2024-05-17_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Anoob Joseph Use NEON instructions for Rx inject instruction preparation. Signed-off-by: Anoob Joseph Signed-off-by: Aakash Sasidharan --- drivers/crypto/cnxk/cn10k_cryptodev_ops.c | 62 +++++++++++++++++------ 1 file changed, 46 insertions(+), 16 deletions(-) diff --git a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c index f2980399c5..446a3c3fd8 100644 --- a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c +++ b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c @@ -7,6 +7,7 @@ #include #include #include +#include #include @@ -1390,15 +1391,17 @@ cn10k_cpt_dequeue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops) return i; } +#if defined(RTE_ARCH_ARM64) uint16_t __rte_hot cn10k_cryptodev_sec_inb_rx_inject(void *dev, struct rte_mbuf **pkts, struct rte_security_session **sess, uint16_t nb_pkts) { - uint16_t l2_len, pf_func, lmt_id, count = 0; - uint64_t lmt_base, lmt_arg, io_addr; + uint64_t lmt_base, lmt_arg, io_addr, u64_0, u64_1, l2_len, pf_func; + uint64x2_t inst_01, inst_23, inst_45, inst_67; struct cn10k_sec_session *sec_sess; struct rte_cryptodev *cdev = dev; union cpt_res_s *hw_res = NULL; + uint16_t lmt_id, count = 0; struct cpt_inst_s *inst; union cpt_fc_write_s fc; struct cnxk_cpt_vf *vf; @@ -1456,26 +1459,41 @@ cn10k_cryptodev_sec_inb_rx_inject(void *dev, struct rte_mbuf **pkts, hw_res = RTE_PTR_ALIGN_CEIL(hw_res, 16); /* Prepare CPT instruction */ - inst->w0.u64 = 0; - inst->w2.u64 = 0; - inst->w2.s.rvu_pf_func = pf_func; - inst->w3.u64 = (((uint64_t)m + sizeof(struct rte_mbuf)) >> 3) << 3 | 1; - inst->w4.u64 = sec_sess->inst.w4 | (rte_pktmbuf_pkt_len(m)); + /* Word 0 and 1 */ + inst_01 = vdupq_n_u64(0); + u64_0 = pf_func << 48 | *(vf->rx_chan_base + m->port) << 4 | (l2_len - 2) << 24 | + l2_len << 16; + inst_01 = vsetq_lane_u64(u64_0, inst_01, 0); + inst_01 = vsetq_lane_u64((uint64_t)hw_res, inst_01, 1); + vst1q_u64(&inst->w0.u64, inst_01); + + /* Word 2 and 3 */ + inst_23 = vdupq_n_u64(0); + u64_1 = (((uint64_t)m + sizeof(struct rte_mbuf)) >> 3) << 3 | 1; + inst_23 = vsetq_lane_u64(u64_1, inst_23, 1); + vst1q_u64(&inst->w2.u64, inst_23); + + /* Word 4 and 5 */ + inst_45 = vdupq_n_u64(0); + u64_0 = sec_sess->inst.w4 | (rte_pktmbuf_pkt_len(m)); + inst_45 = vsetq_lane_u64(u64_0, inst_45, 0); dptr = (uint64_t)rte_pktmbuf_iova(m); - inst->dptr = dptr; - inst->rptr = dptr; - - inst->w0.hw_s.chan = *(vf->rx_chan_base + m->port); - inst->w0.hw_s.l2_len = l2_len; - inst->w0.hw_s.et_offset = l2_len - 2; + u64_1 = dptr; + inst_45 = vsetq_lane_u64(u64_1, inst_45, 1); + vst1q_u64(&inst->w4.u64, inst_45); + + /* Word 6 and 7 */ + inst_67 = vdupq_n_u64(0); + u64_0 = dptr; + u64_1 = sec_sess->inst.w7; + inst_67 = vsetq_lane_u64(u64_0, inst_67, 0); + inst_67 = vsetq_lane_u64(u64_1, inst_67, 1); + vst1q_u64(&inst->w6.u64, inst_67); - inst->res_addr = (uint64_t)hw_res; rte_atomic_store_explicit((unsigned long __rte_atomic *)&hw_res->u64[0], res.u64[0], rte_memory_order_relaxed); - inst->w7.u64 = sec_sess->inst.w7; - inst += 2; } @@ -1503,6 +1521,18 @@ cn10k_cryptodev_sec_inb_rx_inject(void *dev, struct rte_mbuf **pkts, exit: return count + i; } +#else +uint16_t __rte_hot +cn10k_cryptodev_sec_inb_rx_inject(void *dev, struct rte_mbuf **pkts, + struct rte_security_session **sess, uint16_t nb_pkts) +{ + RTE_SET_USED(dev); + RTE_SET_USED(pkts); + RTE_SET_USED(sess); + RTE_SET_USED(nb_pkts); + return 0; +} +#endif void cn10k_cpt_set_enqdeq_fns(struct rte_cryptodev *dev, struct cnxk_cpt_vf *vf) -- 2.25.1