From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3CF07454FA; Wed, 26 Jun 2024 08:03:41 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2BC8742E4D; Wed, 26 Jun 2024 08:03:41 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) by mails.dpdk.org (Postfix) with ESMTP id 6C23542E4B for ; Wed, 26 Jun 2024 08:03:39 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719381819; x=1750917819; h=from:to:subject:date:message-id:mime-version: content-transfer-encoding; bh=BSaLlRLZclBHW1L+URpWQURBPM2mLF2YTnDh1rzharw=; b=F14tdg1D7i1CI81ACqXJZb/Xsir63LPeSJG0ijczBTYkpuUhr2Sb2nz7 AQW3eHyqqsSOTvhaOuNbhI129HSe91YPEZ0KFrGcgZcLFAzCN1gb+0Zq6 iOGmbto/ag5PwM5XnY/6IHR6id1qh9BhQO5RTnmsxN2J565F4HaWekYxw Of3fz4j/Xhf6AGSH/G1hYNOk35olTfBguLpr4oC5srjLZlNXIgC2LWQs/ /7O7AKd84u74ORRmrmG4dbcMpqkBFwtPQ7dVFm6al1q+ebuLZrsOE8Ky5 l1Q4oXHHYdYGEmX72IIZgr0tJw+5c5IyX5b7aJtUVW0c1TWEzeIvXh0M6 A==; X-CSE-ConnectionGUID: li+g5u3iRoiozZJBqkbuNw== X-CSE-MsgGUID: CsFNjHJaRFCYnKo75PPWgw== X-IronPort-AV: E=McAfee;i="6700,10204,11114"; a="27840805" X-IronPort-AV: E=Sophos;i="6.08,266,1712646000"; d="scan'208";a="27840805" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jun 2024 23:03:38 -0700 X-CSE-ConnectionGUID: kzPLrn9JR7elIT6GvYTmeQ== X-CSE-MsgGUID: YuE4SXVRTs+rDwyAFk19jw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,266,1712646000"; d="scan'208";a="43782794" Received: from npg-npf-wlpr-srv02.iind.intel.com (HELO npg-npfwlpr-srv02..) ([10.145.170.184]) by orviesa010.jf.intel.com with ESMTP; 25 Jun 2024 23:03:38 -0700 From: Shaiq Wani To: dev@dpdk.org, bruce.richardson@intel.com Subject: [PATCH] dma/idxd: set defaults for GRPCFG traffic class Date: Wed, 26 Jun 2024 05:45:23 +0000 Message-Id: <20240626054523.3042796-1-shaiq.wani@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Set GRPCFG traffic class to value of 1 for best performance on current generation of accelerators. Applicable to gen1 and gen2 devices. Signed-off-by: Shaiq Wani --- drivers/dma/idxd/idxd_pci.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/dma/idxd/idxd_pci.c b/drivers/dma/idxd/idxd_pci.c index 81637d9420..e551b2232d 100644 --- a/drivers/dma/idxd/idxd_pci.c +++ b/drivers/dma/idxd/idxd_pci.c @@ -12,6 +12,14 @@ #define IDXD_VENDOR_ID 0x8086 #define IDXD_DEVICE_ID_SPR 0x0B25 +#define DEVICE_VERSION_1 0x100 +#define DEVICE_VERSION_2 0x200 +/* + * Set bits for Traffic Class A & B + * TC-A (Bits 2:0) and TC-B (Bits 5:3) + */ +#define IDXD_SET_TC_A_B 0x9 + #define IDXD_PMD_DMADEV_NAME_PCI dmadev_idxd_pci const struct rte_pci_id pci_id_idxd_map[] = { @@ -177,6 +185,7 @@ init_pci_device(struct rte_pci_device *dev, struct idxd_dmadev *idxd, uint16_t grp_offset, wq_offset; /* how far into bar0 the regs are */ uint16_t wq_size, total_wq_size; uint8_t lg2_max_batch, lg2_max_copy_size; + uint32_t version; unsigned int i, err_code; pci = rte_malloc(NULL, sizeof(*pci), 0); @@ -190,6 +199,7 @@ init_pci_device(struct rte_pci_device *dev, struct idxd_dmadev *idxd, /* assign the bar registers, and then configure device */ pci->regs = dev->mem_resource[0].addr; + version = pci->regs->version; grp_offset = (uint16_t)pci->regs->offsets[0]; pci->grp_regs = RTE_PTR_ADD(pci->regs, grp_offset * 0x100); wq_offset = (uint16_t)(pci->regs->offsets[0] >> 16); @@ -234,6 +244,8 @@ init_pci_device(struct rte_pci_device *dev, struct idxd_dmadev *idxd, for (i = 0; i < nb_groups; i++) { pci->grp_regs[i].grpengcfg = 0; pci->grp_regs[i].grpwqcfg[0] = 0; + if (version <= DEVICE_VERSION_2) + pci->grp_regs[i].grpflags |= IDXD_SET_TC_A_B; } for (i = 0; i < nb_wqs; i++) idxd_get_wq_cfg(pci, i)[0] = 0; @@ -278,6 +290,7 @@ init_pci_device(struct rte_pci_device *dev, struct idxd_dmadev *idxd, (lg2_max_batch << WQ_BATCH_SZ_SHIFT); } + IDXD_PMD_DEBUG(" Device Version: %"PRIx32, version); /* dump the group configuration to output */ for (i = 0; i < nb_groups; i++) { IDXD_PMD_DEBUG("## Group %d", i); -- 2.34.1