DPDK patches and discussions
 help / color / mirror / Atom feed
* [PATCH v1 01/17] net/ntnic: Add registers for NapaTech SmartNiC
@ 2024-05-30 14:48 Serhii Iliushyk
  2024-05-30 14:48 ` [PATCH v1 02/17] net/ntnic: add core platform functionality Serhii Iliushyk
                   ` (24 more replies)
  0 siblings, 25 replies; 238+ messages in thread
From: Serhii Iliushyk @ 2024-05-30 14:48 UTC (permalink / raw)
  To: dev; +Cc: mko-plv, ckm, andrew.rybchenko, ferruh.yigit

The NTNIC PMD does not rely on a kernel space Napatech driver,
thus all defines related to the register layout is part of the PMD
code, which will be added in later commits.

Signed-off-by: Serhii Iliushyk <sil-plv@napatech.com>
---
 .../supported/nthw_fpga_9563_055_039_0000.c   | 3488 +++++++++++++++++
 .../nthw/supported/nthw_fpga_instances.c      |    6 +
 .../nthw/supported/nthw_fpga_instances.h      |    7 +
 .../ntnic/nthw/supported/nthw_fpga_mod_defs.h |   93 +
 .../nthw/supported/nthw_fpga_mod_str_map.c    |   78 +
 .../nthw/supported/nthw_fpga_mod_str_map.h    |   11 +
 .../nthw/supported/nthw_fpga_param_defs.h     |  232 ++
 .../ntnic/nthw/supported/nthw_fpga_reg_defs.h |   94 +
 .../nthw/supported/nthw_fpga_reg_defs_cat.h   |  237 ++
 .../nthw/supported/nthw_fpga_reg_defs_cb.h    |   73 +
 .../nthw/supported/nthw_fpga_reg_defs_cor.h   |   81 +
 .../nthw/supported/nthw_fpga_reg_defs_cpy.h   |  112 +
 .../nthw/supported/nthw_fpga_reg_defs_csu.h   |   30 +
 .../nthw/supported/nthw_fpga_reg_defs_dbs.h   |  144 +
 .../nthw/supported/nthw_fpga_reg_defs_ddp.h   |   34 +
 .../nthw/supported/nthw_fpga_reg_defs_epp.h   |   64 +
 .../nthw/supported/nthw_fpga_reg_defs_eqm.h   |   45 +
 .../nthw/supported/nthw_fpga_reg_defs_fhm.h   |   48 +
 .../nthw/supported/nthw_fpga_reg_defs_flm.h   |  237 ++
 .../nthw/supported/nthw_fpga_reg_defs_gfg.h   |  126 +
 .../nthw/supported/nthw_fpga_reg_defs_gmf.h   |   68 +
 .../supported/nthw_fpga_reg_defs_gpio_phy.h   |   48 +
 .../nthw_fpga_reg_defs_gpio_phy_ports.h       |   72 +
 .../supported/nthw_fpga_reg_defs_gpio_sfpp.h  |   34 +
 .../nthw/supported/nthw_fpga_reg_defs_hfu.h   |   48 +
 .../nthw/supported/nthw_fpga_reg_defs_hif.h   |   79 +
 .../nthw/supported/nthw_fpga_reg_defs_hsh.h   |   49 +
 .../nthw/supported/nthw_fpga_reg_defs_i2cm.h  |   38 +
 .../nthw/supported/nthw_fpga_reg_defs_ifr.h   |   41 +
 .../nthw/supported/nthw_fpga_reg_defs_igam.h  |   28 +
 .../nthw/supported/nthw_fpga_reg_defs_iic.h   |   96 +
 .../nthw/supported/nthw_fpga_reg_defs_ins.h   |   29 +
 .../nthw/supported/nthw_fpga_reg_defs_ioa.h   |   44 +
 .../nthw/supported/nthw_fpga_reg_defs_ipf.h   |   84 +
 .../nthw/supported/nthw_fpga_reg_defs_km.h    |  125 +
 .../nthw/supported/nthw_fpga_reg_defs_mac.h   |  177 +
 .../supported/nthw_fpga_reg_defs_mac_pcs.h    |  298 ++
 .../nthw_fpga_reg_defs_mac_pcs_xxv.h          | 1092 ++++++
 .../supported/nthw_fpga_reg_defs_mac_rx.h     |   90 +
 .../supported/nthw_fpga_reg_defs_mac_tfg.h    |   42 +
 .../supported/nthw_fpga_reg_defs_mac_tx.h     |   70 +
 .../nthw/supported/nthw_fpga_reg_defs_msk.h   |   42 +
 .../supported/nthw_fpga_reg_defs_pci_rd_tg.h  |   37 +
 .../supported/nthw_fpga_reg_defs_pci_ta.h     |   32 +
 .../supported/nthw_fpga_reg_defs_pci_wr_tg.h  |   40 +
 .../nthw/supported/nthw_fpga_reg_defs_pcie3.h |  281 ++
 .../nthw_fpga_reg_defs_pcm_nt400dxx.h         |   19 +
 .../nthw_fpga_reg_defs_pcm_nt50b01_01.h       |   19 +
 .../nthw/supported/nthw_fpga_reg_defs_pcs.h   |   92 +
 .../supported/nthw_fpga_reg_defs_pcs100.h     |   90 +
 .../nthw/supported/nthw_fpga_reg_defs_pdb.h   |   47 +
 .../nthw/supported/nthw_fpga_reg_defs_pdi.h   |   48 +
 .../supported/nthw_fpga_reg_defs_phy_tile.h   |  196 +
 .../nthw_fpga_reg_defs_prm_nt400dxx.h         |   19 +
 .../nthw_fpga_reg_defs_prm_nt50b01_01.h       |   19 +
 .../nthw/supported/nthw_fpga_reg_defs_qsl.h   |   65 +
 .../nthw/supported/nthw_fpga_reg_defs_qspi.h  |   89 +
 .../nthw/supported/nthw_fpga_reg_defs_r2drp.h |   29 +
 .../nthw/supported/nthw_fpga_reg_defs_rac.h   |   72 +
 .../nthw/supported/nthw_fpga_reg_defs_rfd.h   |   37 +
 .../nthw/supported/nthw_fpga_reg_defs_rmc.h   |   35 +
 .../nthw/supported/nthw_fpga_reg_defs_roa.h   |   67 +
 .../nthw/supported/nthw_fpga_reg_defs_rpf.h   |   30 +
 .../nthw/supported/nthw_fpga_reg_defs_rpl.h   |   42 +
 .../supported/nthw_fpga_reg_defs_rpp_lr.h     |   36 +
 .../supported/nthw_fpga_reg_defs_rst9563.h    |   59 +
 .../nthw/supported/nthw_fpga_reg_defs_sdc.h   |   44 +
 .../nthw/supported/nthw_fpga_reg_defs_slc.h   |   33 +
 .../supported/nthw_fpga_reg_defs_slc_lr.h     |   22 +
 .../nthw/supported/nthw_fpga_reg_defs_spim.h  |   75 +
 .../nthw/supported/nthw_fpga_reg_defs_spis.h  |   50 +
 .../nthw/supported/nthw_fpga_reg_defs_sta.h   |   59 +
 .../supported/nthw_fpga_reg_defs_tempmon.h    |   29 +
 .../nthw/supported/nthw_fpga_reg_defs_tint.h  |   27 +
 .../nthw/supported/nthw_fpga_reg_defs_tsm.h   |  294 ++
 .../supported/nthw_fpga_reg_defs_tx_cpy.h     |   22 +
 .../supported/nthw_fpga_reg_defs_tx_csi.h     |   22 +
 .../supported/nthw_fpga_reg_defs_tx_cso.h     |   22 +
 .../supported/nthw_fpga_reg_defs_tx_ins.h     |   22 +
 .../supported/nthw_fpga_reg_defs_tx_rpl.h     |   22 +
 80 files changed, 10177 insertions(+)
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_039_0000.c
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_instances.c
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_instances.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_mod_str_map.c
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_mod_str_map.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_param_defs.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_cat.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_cb.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_cor.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_cpy.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_csu.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_dbs.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_ddp.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_epp.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_eqm.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_fhm.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_flm.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gfg.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gmf.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gpio_phy.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gpio_phy_ports.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gpio_sfpp.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_hfu.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_hif.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_hsh.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_i2cm.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_ifr.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_igam.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_iic.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_ins.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_ioa.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_ipf.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_km.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_pcs.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_pcs_xxv.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_rx.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_tfg.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_tx.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_msk.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pci_rd_tg.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pci_ta.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pci_wr_tg.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcie3.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcm_nt400dxx.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcm_nt50b01_01.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcs.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcs100.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pdb.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pdi.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_phy_tile.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_prm_nt400dxx.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_prm_nt50b01_01.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_qsl.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_qspi.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_r2drp.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rac.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rfd.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rmc.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_roa.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rpf.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rpl.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rpp_lr.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rst9563.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_sdc.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_slc.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_slc_lr.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_spim.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_spis.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_sta.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tempmon.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tint.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tsm.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_cpy.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_csi.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_cso.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_ins.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_rpl.h

diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_039_0000.c b/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_039_0000.c
new file mode 100644
index 0000000000..a7ee892007
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_039_0000.c
@@ -0,0 +1,3488 @@
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+#include "nthw_register.h"
+
+static nthw_fpga_field_init_s cat_cct_ctrl_fields[] = {
+	{ CAT_CCT_CTRL_ADR, 8, 0, 0x0000 },
+	{ CAT_CCT_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s cat_cct_data_fields[] = {
+	{ CAT_CCT_DATA_COLOR, 32, 0, 0x0000 },
+	{ CAT_CCT_DATA_KM, 4, 32, 0x0000 },
+};
+
+static nthw_fpga_field_init_s cat_cfn_ctrl_fields[] = {
+	{ CAT_CFN_CTRL_ADR, 6, 0, 0x0000 },
+	{ CAT_CFN_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s cat_cfn_data_fields[] = {
+	{ CAT_CFN_DATA_ENABLE, 1, 0, 0x0000 },
+	{ CAT_CFN_DATA_ERR_CV, 2, 99, 0x0000 },
+	{ CAT_CFN_DATA_ERR_FCS, 2, 101, 0x0000 },
+	{ CAT_CFN_DATA_ERR_INV, 1, 98, 0x0000 },
+	{ CAT_CFN_DATA_ERR_L3_CS, 2, 105, 0x0000 },
+	{ CAT_CFN_DATA_ERR_L4_CS, 2, 107, 0x0000 },
+	{ CAT_CFN_DATA_ERR_TNL_L3_CS, 2, 109, 0x0000 },
+	{ CAT_CFN_DATA_ERR_TNL_L4_CS, 2, 111, 0x0000 },
+	{ CAT_CFN_DATA_ERR_TNL_TTL_EXP, 2, 115, 0x0000 },
+	{ CAT_CFN_DATA_ERR_TRUNC, 2, 103, 0x0000 },
+	{ CAT_CFN_DATA_ERR_TTL_EXP, 2, 113, 0x0000 },
+	{ CAT_CFN_DATA_INV, 1, 1, 0x0000 },
+	{ CAT_CFN_DATA_KM0_OR, 3, 173, 0x0000 },
+	{ CAT_CFN_DATA_KM1_OR, 3, 176, 0x0000 },
+	{ CAT_CFN_DATA_LC, 8, 164, 0x0000 },
+	{ CAT_CFN_DATA_LC_INV, 1, 172, 0x0000 },
+	{ CAT_CFN_DATA_MAC_PORT, 2, 117, 0x0000 },
+	{ CAT_CFN_DATA_PM_AND_INV, 1, 161, 0x0000 },
+	{ CAT_CFN_DATA_PM_CMB, 4, 157, 0x0000 },
+	{ CAT_CFN_DATA_PM_CMP, 32, 119, 0x0000 },
+	{ CAT_CFN_DATA_PM_DCT, 2, 151, 0x0000 },
+	{ CAT_CFN_DATA_PM_EXT_INV, 4, 153, 0x0000 },
+	{ CAT_CFN_DATA_PM_INV, 1, 163, 0x0000 },
+	{ CAT_CFN_DATA_PM_OR_INV, 1, 162, 0x0000 },
+	{ CAT_CFN_DATA_PTC_CFP, 2, 5, 0x0000 },
+	{ CAT_CFN_DATA_PTC_FRAG, 4, 36, 0x0000 },
+	{ CAT_CFN_DATA_PTC_INV, 1, 2, 0x0000 },
+	{ CAT_CFN_DATA_PTC_IP_PROT, 8, 40, 0x0000 },
+	{ CAT_CFN_DATA_PTC_ISL, 2, 3, 0x0000 },
+	{ CAT_CFN_DATA_PTC_L2, 7, 12, 0x0000 },
+	{ CAT_CFN_DATA_PTC_L3, 3, 33, 0x0000 },
+	{ CAT_CFN_DATA_PTC_L4, 5, 48, 0x0000 },
+	{ CAT_CFN_DATA_PTC_MAC, 5, 7, 0x0000 },
+	{ CAT_CFN_DATA_PTC_MPLS, 8, 25, 0x0000 },
+	{ CAT_CFN_DATA_PTC_TNL_FRAG, 4, 81, 0x0000 },
+	{ CAT_CFN_DATA_PTC_TNL_IP_PROT, 8, 85, 0x0000 },
+	{ CAT_CFN_DATA_PTC_TNL_L2, 2, 64, 0x0000 },
+	{ CAT_CFN_DATA_PTC_TNL_L3, 3, 78, 0x0000 },
+	{ CAT_CFN_DATA_PTC_TNL_L4, 5, 93, 0x0000 },
+	{ CAT_CFN_DATA_PTC_TNL_MPLS, 8, 70, 0x0000 },
+	{ CAT_CFN_DATA_PTC_TNL_VLAN, 4, 66, 0x0000 },
+	{ CAT_CFN_DATA_PTC_TUNNEL, 11, 53, 0x0000 },
+	{ CAT_CFN_DATA_PTC_VLAN, 4, 21, 0x0000 },
+	{ CAT_CFN_DATA_PTC_VNTAG, 2, 19, 0x0000 },
+};
+
+static nthw_fpga_field_init_s cat_cot_ctrl_fields[] = {
+	{ CAT_COT_CTRL_ADR, 6, 0, 0x0000 },
+	{ CAT_COT_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s cat_cot_data_fields[] = {
+	{ CAT_COT_DATA_COLOR, 32, 0, 0x0000 },
+	{ CAT_COT_DATA_KM, 4, 32, 0x0000 },
+};
+
+static nthw_fpga_field_init_s cat_cte_ctrl_fields[] = {
+	{ CAT_CTE_CTRL_ADR, 6, 0, 0x0000 },
+	{ CAT_CTE_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s cat_cte_data_fields[] = {
+	{ CAT_CTE_DATA_COL_ENABLE, 1, 0, 0x0000 }, { CAT_CTE_DATA_COR_ENABLE, 1, 1, 0x0000 },
+	{ CAT_CTE_DATA_EPP_ENABLE, 1, 9, 0x0000 }, { CAT_CTE_DATA_HSH_ENABLE, 1, 2, 0x0000 },
+	{ CAT_CTE_DATA_HST_ENABLE, 1, 8, 0x0000 }, { CAT_CTE_DATA_IPF_ENABLE, 1, 4, 0x0000 },
+	{ CAT_CTE_DATA_MSK_ENABLE, 1, 7, 0x0000 }, { CAT_CTE_DATA_PDB_ENABLE, 1, 6, 0x0000 },
+	{ CAT_CTE_DATA_QSL_ENABLE, 1, 3, 0x0000 }, { CAT_CTE_DATA_SLC_ENABLE, 1, 5, 0x0000 },
+	{ CAT_CTE_DATA_TPE_ENABLE, 1, 10, 0x0000 },
+};
+
+static nthw_fpga_field_init_s cat_cts_ctrl_fields[] = {
+	{ CAT_CTS_CTRL_ADR, 9, 0, 0x0000 },
+	{ CAT_CTS_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s cat_cts_data_fields[] = {
+	{ CAT_CTS_DATA_CAT_A, 6, 0, 0x0000 },
+	{ CAT_CTS_DATA_CAT_B, 6, 6, 0x0000 },
+};
+
+static nthw_fpga_field_init_s cat_dct_ctrl_fields[] = {
+	{ CAT_DCT_CTRL_ADR, 13, 0, 0x0000 },
+	{ CAT_DCT_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s cat_dct_data_fields[] = {
+	{ CAT_DCT_DATA_RES, 16, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s cat_dct_sel_fields[] = {
+	{ CAT_DCT_SEL_LU, 2, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s cat_exo_ctrl_fields[] = {
+	{ CAT_EXO_CTRL_ADR, 2, 0, 0x0000 },
+	{ CAT_EXO_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s cat_exo_data_fields[] = {
+	{ CAT_EXO_DATA_DYN, 5, 0, 0x0000 },
+	{ CAT_EXO_DATA_OFS, 11, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s cat_fte0_ctrl_fields[] = {
+	{ CAT_FTE0_CTRL_ADR, 9, 0, 0x0000 },
+	{ CAT_FTE0_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s cat_fte0_data_fields[] = {
+	{ CAT_FTE0_DATA_ENABLE, 8, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s cat_fte1_ctrl_fields[] = {
+	{ CAT_FTE1_CTRL_ADR, 9, 0, 0x0000 },
+	{ CAT_FTE1_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s cat_fte1_data_fields[] = {
+	{ CAT_FTE1_DATA_ENABLE, 8, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s cat_join_fields[] = {
+	{ CAT_JOIN_J1, 2, 0, 0x0000 },
+	{ CAT_JOIN_J2, 1, 8, 0x0000 },
+};
+
+static nthw_fpga_field_init_s cat_kcc_ctrl_fields[] = {
+	{ CAT_KCC_CTRL_ADR, 11, 0, 0x0000 },
+	{ CAT_KCC_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s cat_kcc_data_fields[] = {
+	{ CAT_KCC_DATA_CATEGORY, 8, 64, 0x0000 },
+	{ CAT_KCC_DATA_ID, 12, 72, 0x0000 },
+	{ CAT_KCC_DATA_KEY, 64, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s cat_kce0_ctrl_fields[] = {
+	{ CAT_KCE0_CTRL_ADR, 3, 0, 0x0000 },
+	{ CAT_KCE0_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s cat_kce0_data_fields[] = {
+	{ CAT_KCE0_DATA_ENABLE, 8, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s cat_kce1_ctrl_fields[] = {
+	{ CAT_KCE1_CTRL_ADR, 3, 0, 0x0000 },
+	{ CAT_KCE1_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s cat_kce1_data_fields[] = {
+	{ CAT_KCE1_DATA_ENABLE, 8, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s cat_kcs0_ctrl_fields[] = {
+	{ CAT_KCS0_CTRL_ADR, 6, 0, 0x0000 },
+	{ CAT_KCS0_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s cat_kcs0_data_fields[] = {
+	{ CAT_KCS0_DATA_CATEGORY, 6, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s cat_kcs1_ctrl_fields[] = {
+	{ CAT_KCS1_CTRL_ADR, 6, 0, 0x0000 },
+	{ CAT_KCS1_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s cat_kcs1_data_fields[] = {
+	{ CAT_KCS1_DATA_CATEGORY, 6, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s cat_len_ctrl_fields[] = {
+	{ CAT_LEN_CTRL_ADR, 3, 0, 0x0000 },
+	{ CAT_LEN_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s cat_len_data_fields[] = {
+	{ CAT_LEN_DATA_DYN1, 5, 28, 0x0000 }, { CAT_LEN_DATA_DYN2, 5, 33, 0x0000 },
+	{ CAT_LEN_DATA_INV, 1, 38, 0x0000 }, { CAT_LEN_DATA_LOWER, 14, 0, 0x0000 },
+	{ CAT_LEN_DATA_UPPER, 14, 14, 0x0000 },
+};
+
+static nthw_fpga_field_init_s cat_rck_ctrl_fields[] = {
+	{ CAT_RCK_CTRL_ADR, 8, 0, 0x0000 },
+	{ CAT_RCK_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s cat_rck_data_fields[] = {
+	{ CAT_RCK_DATA_CM0U, 1, 1, 0x0000 }, { CAT_RCK_DATA_CM1U, 1, 5, 0x0000 },
+	{ CAT_RCK_DATA_CM2U, 1, 9, 0x0000 }, { CAT_RCK_DATA_CM3U, 1, 13, 0x0000 },
+	{ CAT_RCK_DATA_CM4U, 1, 17, 0x0000 }, { CAT_RCK_DATA_CM5U, 1, 21, 0x0000 },
+	{ CAT_RCK_DATA_CM6U, 1, 25, 0x0000 }, { CAT_RCK_DATA_CM7U, 1, 29, 0x0000 },
+	{ CAT_RCK_DATA_CML0, 1, 0, 0x0000 }, { CAT_RCK_DATA_CML1, 1, 4, 0x0000 },
+	{ CAT_RCK_DATA_CML2, 1, 8, 0x0000 }, { CAT_RCK_DATA_CML3, 1, 12, 0x0000 },
+	{ CAT_RCK_DATA_CML4, 1, 16, 0x0000 }, { CAT_RCK_DATA_CML5, 1, 20, 0x0000 },
+	{ CAT_RCK_DATA_CML6, 1, 24, 0x0000 }, { CAT_RCK_DATA_CML7, 1, 28, 0x0000 },
+	{ CAT_RCK_DATA_SEL0, 1, 2, 0x0000 }, { CAT_RCK_DATA_SEL1, 1, 6, 0x0000 },
+	{ CAT_RCK_DATA_SEL2, 1, 10, 0x0000 }, { CAT_RCK_DATA_SEL3, 1, 14, 0x0000 },
+	{ CAT_RCK_DATA_SEL4, 1, 18, 0x0000 }, { CAT_RCK_DATA_SEL5, 1, 22, 0x0000 },
+	{ CAT_RCK_DATA_SEL6, 1, 26, 0x0000 }, { CAT_RCK_DATA_SEL7, 1, 30, 0x0000 },
+	{ CAT_RCK_DATA_SEU0, 1, 3, 0x0000 }, { CAT_RCK_DATA_SEU1, 1, 7, 0x0000 },
+	{ CAT_RCK_DATA_SEU2, 1, 11, 0x0000 }, { CAT_RCK_DATA_SEU3, 1, 15, 0x0000 },
+	{ CAT_RCK_DATA_SEU4, 1, 19, 0x0000 }, { CAT_RCK_DATA_SEU5, 1, 23, 0x0000 },
+	{ CAT_RCK_DATA_SEU6, 1, 27, 0x0000 }, { CAT_RCK_DATA_SEU7, 1, 31, 0x0000 },
+};
+
+static nthw_fpga_register_init_s cat_registers[] = {
+	{ CAT_CCT_CTRL, 30, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, cat_cct_ctrl_fields },
+	{ CAT_CCT_DATA, 31, 36, NTHW_FPGA_REG_TYPE_WO, 0, 2, cat_cct_data_fields },
+	{ CAT_CFN_CTRL, 10, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, cat_cfn_ctrl_fields },
+	{ CAT_CFN_DATA, 11, 179, NTHW_FPGA_REG_TYPE_WO, 0, 44, cat_cfn_data_fields },
+	{ CAT_COT_CTRL, 28, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, cat_cot_ctrl_fields },
+	{ CAT_COT_DATA, 29, 36, NTHW_FPGA_REG_TYPE_WO, 0, 2, cat_cot_data_fields },
+	{ CAT_CTE_CTRL, 24, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, cat_cte_ctrl_fields },
+	{ CAT_CTE_DATA, 25, 11, NTHW_FPGA_REG_TYPE_WO, 0, 11, cat_cte_data_fields },
+	{ CAT_CTS_CTRL, 26, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, cat_cts_ctrl_fields },
+	{ CAT_CTS_DATA, 27, 12, NTHW_FPGA_REG_TYPE_WO, 0, 2, cat_cts_data_fields },
+	{ CAT_DCT_CTRL, 6, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, cat_dct_ctrl_fields },
+	{ CAT_DCT_DATA, 7, 16, NTHW_FPGA_REG_TYPE_WO, 0, 1, cat_dct_data_fields },
+	{ CAT_DCT_SEL, 4, 2, NTHW_FPGA_REG_TYPE_WO, 0, 1, cat_dct_sel_fields },
+	{ CAT_EXO_CTRL, 0, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, cat_exo_ctrl_fields },
+	{ CAT_EXO_DATA, 1, 27, NTHW_FPGA_REG_TYPE_WO, 0, 2, cat_exo_data_fields },
+	{ CAT_FTE0_CTRL, 16, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, cat_fte0_ctrl_fields },
+	{ CAT_FTE0_DATA, 17, 8, NTHW_FPGA_REG_TYPE_WO, 0, 1, cat_fte0_data_fields },
+	{ CAT_FTE1_CTRL, 22, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, cat_fte1_ctrl_fields },
+	{ CAT_FTE1_DATA, 23, 8, NTHW_FPGA_REG_TYPE_WO, 0, 1, cat_fte1_data_fields },
+	{ CAT_JOIN, 5, 9, NTHW_FPGA_REG_TYPE_WO, 0, 2, cat_join_fields },
+	{ CAT_KCC_CTRL, 32, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, cat_kcc_ctrl_fields },
+	{ CAT_KCC_DATA, 33, 84, NTHW_FPGA_REG_TYPE_WO, 0, 3, cat_kcc_data_fields },
+	{ CAT_KCE0_CTRL, 12, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, cat_kce0_ctrl_fields },
+	{ CAT_KCE0_DATA, 13, 8, NTHW_FPGA_REG_TYPE_WO, 0, 1, cat_kce0_data_fields },
+	{ CAT_KCE1_CTRL, 18, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, cat_kce1_ctrl_fields },
+	{ CAT_KCE1_DATA, 19, 8, NTHW_FPGA_REG_TYPE_WO, 0, 1, cat_kce1_data_fields },
+	{ CAT_KCS0_CTRL, 14, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, cat_kcs0_ctrl_fields },
+	{ CAT_KCS0_DATA, 15, 6, NTHW_FPGA_REG_TYPE_WO, 0, 1, cat_kcs0_data_fields },
+	{ CAT_KCS1_CTRL, 20, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, cat_kcs1_ctrl_fields },
+	{ CAT_KCS1_DATA, 21, 6, NTHW_FPGA_REG_TYPE_WO, 0, 1, cat_kcs1_data_fields },
+	{ CAT_LEN_CTRL, 8, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, cat_len_ctrl_fields },
+	{ CAT_LEN_DATA, 9, 39, NTHW_FPGA_REG_TYPE_WO, 0, 5, cat_len_data_fields },
+	{ CAT_RCK_CTRL, 2, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, cat_rck_ctrl_fields },
+	{ CAT_RCK_DATA, 3, 32, NTHW_FPGA_REG_TYPE_WO, 0, 32, cat_rck_data_fields },
+};
+
+static nthw_fpga_field_init_s cpy_packet_reader0_ctrl_fields[] = {
+	{ CPY_PACKET_READER0_CTRL_ADR, 4, 0, 0x0000 },
+	{ CPY_PACKET_READER0_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s cpy_packet_reader0_data_fields[] = {
+	{ CPY_PACKET_READER0_DATA_DYN, 5, 10, 0x0000 },
+	{ CPY_PACKET_READER0_DATA_OFS, 10, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s cpy_writer0_ctrl_fields[] = {
+	{ CPY_WRITER0_CTRL_ADR, 4, 0, 0x0000 },
+	{ CPY_WRITER0_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s cpy_writer0_data_fields[] = {
+	{ CPY_WRITER0_DATA_DYN, 5, 17, 0x0000 }, { CPY_WRITER0_DATA_LEN, 5, 22, 0x0000 },
+	{ CPY_WRITER0_DATA_MASK_POINTER, 4, 27, 0x0000 }, { CPY_WRITER0_DATA_OFS, 14, 3, 0x0000 },
+	{ CPY_WRITER0_DATA_READER_SELECT, 3, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s cpy_writer0_mask_ctrl_fields[] = {
+	{ CPY_WRITER0_MASK_CTRL_ADR, 4, 0, 0x0000 },
+	{ CPY_WRITER0_MASK_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s cpy_writer0_mask_data_fields[] = {
+	{ CPY_WRITER0_MASK_DATA_BYTE_MASK, 16, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s cpy_writer1_ctrl_fields[] = {
+	{ CPY_WRITER1_CTRL_ADR, 4, 0, 0x0000 },
+	{ CPY_WRITER1_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s cpy_writer1_data_fields[] = {
+	{ CPY_WRITER1_DATA_DYN, 5, 17, 0x0000 }, { CPY_WRITER1_DATA_LEN, 5, 22, 0x0000 },
+	{ CPY_WRITER1_DATA_MASK_POINTER, 4, 27, 0x0000 }, { CPY_WRITER1_DATA_OFS, 14, 3, 0x0000 },
+	{ CPY_WRITER1_DATA_READER_SELECT, 3, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s cpy_writer1_mask_ctrl_fields[] = {
+	{ CPY_WRITER1_MASK_CTRL_ADR, 4, 0, 0x0000 },
+	{ CPY_WRITER1_MASK_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s cpy_writer1_mask_data_fields[] = {
+	{ CPY_WRITER1_MASK_DATA_BYTE_MASK, 16, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s cpy_writer2_ctrl_fields[] = {
+	{ CPY_WRITER2_CTRL_ADR, 4, 0, 0x0000 },
+	{ CPY_WRITER2_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s cpy_writer2_data_fields[] = {
+	{ CPY_WRITER2_DATA_DYN, 5, 17, 0x0000 }, { CPY_WRITER2_DATA_LEN, 5, 22, 0x0000 },
+	{ CPY_WRITER2_DATA_MASK_POINTER, 4, 27, 0x0000 }, { CPY_WRITER2_DATA_OFS, 14, 3, 0x0000 },
+	{ CPY_WRITER2_DATA_READER_SELECT, 3, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s cpy_writer2_mask_ctrl_fields[] = {
+	{ CPY_WRITER2_MASK_CTRL_ADR, 4, 0, 0x0000 },
+	{ CPY_WRITER2_MASK_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s cpy_writer2_mask_data_fields[] = {
+	{ CPY_WRITER2_MASK_DATA_BYTE_MASK, 16, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s cpy_writer3_ctrl_fields[] = {
+	{ CPY_WRITER3_CTRL_ADR, 4, 0, 0x0000 },
+	{ CPY_WRITER3_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s cpy_writer3_data_fields[] = {
+	{ CPY_WRITER3_DATA_DYN, 5, 17, 0x0000 }, { CPY_WRITER3_DATA_LEN, 5, 22, 0x0000 },
+	{ CPY_WRITER3_DATA_MASK_POINTER, 4, 27, 0x0000 }, { CPY_WRITER3_DATA_OFS, 14, 3, 0x0000 },
+	{ CPY_WRITER3_DATA_READER_SELECT, 3, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s cpy_writer3_mask_ctrl_fields[] = {
+	{ CPY_WRITER3_MASK_CTRL_ADR, 4, 0, 0x0000 },
+	{ CPY_WRITER3_MASK_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s cpy_writer3_mask_data_fields[] = {
+	{ CPY_WRITER3_MASK_DATA_BYTE_MASK, 16, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s cpy_writer4_ctrl_fields[] = {
+	{ CPY_WRITER4_CTRL_ADR, 4, 0, 0x0000 },
+	{ CPY_WRITER4_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s cpy_writer4_data_fields[] = {
+	{ CPY_WRITER4_DATA_DYN, 5, 17, 0x0000 }, { CPY_WRITER4_DATA_LEN, 5, 22, 0x0000 },
+	{ CPY_WRITER4_DATA_MASK_POINTER, 4, 27, 0x0000 }, { CPY_WRITER4_DATA_OFS, 14, 3, 0x0000 },
+	{ CPY_WRITER4_DATA_READER_SELECT, 3, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s cpy_writer4_mask_ctrl_fields[] = {
+	{ CPY_WRITER4_MASK_CTRL_ADR, 4, 0, 0x0000 },
+	{ CPY_WRITER4_MASK_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s cpy_writer4_mask_data_fields[] = {
+	{ CPY_WRITER4_MASK_DATA_BYTE_MASK, 16, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s cpy_writer5_ctrl_fields[] = {
+	{ CPY_WRITER5_CTRL_ADR, 4, 0, 0x0000 },
+	{ CPY_WRITER5_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s cpy_writer5_data_fields[] = {
+	{ CPY_WRITER5_DATA_DYN, 5, 17, 0x0000 }, { CPY_WRITER5_DATA_LEN, 5, 22, 0x0000 },
+	{ CPY_WRITER5_DATA_MASK_POINTER, 4, 27, 0x0000 }, { CPY_WRITER5_DATA_OFS, 14, 3, 0x0000 },
+	{ CPY_WRITER5_DATA_READER_SELECT, 3, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s cpy_writer5_mask_ctrl_fields[] = {
+	{ CPY_WRITER5_MASK_CTRL_ADR, 4, 0, 0x0000 },
+	{ CPY_WRITER5_MASK_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s cpy_writer5_mask_data_fields[] = {
+	{ CPY_WRITER5_MASK_DATA_BYTE_MASK, 16, 0, 0x0000 },
+};
+
+static nthw_fpga_register_init_s cpy_registers[] = {
+	{
+		CPY_PACKET_READER0_CTRL, 24, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2,
+		cpy_packet_reader0_ctrl_fields
+	},
+	{
+		CPY_PACKET_READER0_DATA, 25, 15, NTHW_FPGA_REG_TYPE_WO, 0, 2,
+		cpy_packet_reader0_data_fields
+	},
+	{ CPY_WRITER0_CTRL, 0, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, cpy_writer0_ctrl_fields },
+	{ CPY_WRITER0_DATA, 1, 31, NTHW_FPGA_REG_TYPE_WO, 0, 5, cpy_writer0_data_fields },
+	{
+		CPY_WRITER0_MASK_CTRL, 2, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2,
+		cpy_writer0_mask_ctrl_fields
+	},
+	{
+		CPY_WRITER0_MASK_DATA, 3, 16, NTHW_FPGA_REG_TYPE_WO, 0, 1,
+		cpy_writer0_mask_data_fields
+	},
+	{ CPY_WRITER1_CTRL, 4, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, cpy_writer1_ctrl_fields },
+	{ CPY_WRITER1_DATA, 5, 31, NTHW_FPGA_REG_TYPE_WO, 0, 5, cpy_writer1_data_fields },
+	{
+		CPY_WRITER1_MASK_CTRL, 6, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2,
+		cpy_writer1_mask_ctrl_fields
+	},
+	{
+		CPY_WRITER1_MASK_DATA, 7, 16, NTHW_FPGA_REG_TYPE_WO, 0, 1,
+		cpy_writer1_mask_data_fields
+	},
+	{ CPY_WRITER2_CTRL, 8, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, cpy_writer2_ctrl_fields },
+	{ CPY_WRITER2_DATA, 9, 31, NTHW_FPGA_REG_TYPE_WO, 0, 5, cpy_writer2_data_fields },
+	{
+		CPY_WRITER2_MASK_CTRL, 10, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2,
+		cpy_writer2_mask_ctrl_fields
+	},
+	{
+		CPY_WRITER2_MASK_DATA, 11, 16, NTHW_FPGA_REG_TYPE_WO, 0, 1,
+		cpy_writer2_mask_data_fields
+	},
+	{ CPY_WRITER3_CTRL, 12, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, cpy_writer3_ctrl_fields },
+	{ CPY_WRITER3_DATA, 13, 31, NTHW_FPGA_REG_TYPE_WO, 0, 5, cpy_writer3_data_fields },
+	{
+		CPY_WRITER3_MASK_CTRL, 14, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2,
+		cpy_writer3_mask_ctrl_fields
+	},
+	{
+		CPY_WRITER3_MASK_DATA, 15, 16, NTHW_FPGA_REG_TYPE_WO, 0, 1,
+		cpy_writer3_mask_data_fields
+	},
+	{ CPY_WRITER4_CTRL, 16, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, cpy_writer4_ctrl_fields },
+	{ CPY_WRITER4_DATA, 17, 31, NTHW_FPGA_REG_TYPE_WO, 0, 5, cpy_writer4_data_fields },
+	{
+		CPY_WRITER4_MASK_CTRL, 18, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2,
+		cpy_writer4_mask_ctrl_fields
+	},
+	{
+		CPY_WRITER4_MASK_DATA, 19, 16, NTHW_FPGA_REG_TYPE_WO, 0, 1,
+		cpy_writer4_mask_data_fields
+	},
+	{ CPY_WRITER5_CTRL, 20, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, cpy_writer5_ctrl_fields },
+	{ CPY_WRITER5_DATA, 21, 31, NTHW_FPGA_REG_TYPE_WO, 0, 5, cpy_writer5_data_fields },
+	{
+		CPY_WRITER5_MASK_CTRL, 22, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2,
+		cpy_writer5_mask_ctrl_fields
+	},
+	{
+		CPY_WRITER5_MASK_DATA, 23, 16, NTHW_FPGA_REG_TYPE_WO, 0, 1,
+		cpy_writer5_mask_data_fields
+	},
+};
+
+static nthw_fpga_field_init_s csu_rcp_ctrl_fields[] = {
+	{ CSU_RCP_CTRL_ADR, 4, 0, 0x0000 },
+	{ CSU_RCP_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s csu_rcp_data_fields[] = {
+	{ CSU_RCP_DATA_IL3_CMD, 2, 5, 0x0000 },
+	{ CSU_RCP_DATA_IL4_CMD, 3, 7, 0x0000 },
+	{ CSU_RCP_DATA_OL3_CMD, 2, 0, 0x0000 },
+	{ CSU_RCP_DATA_OL4_CMD, 3, 2, 0x0000 },
+};
+
+static nthw_fpga_register_init_s csu_registers[] = {
+	{ CSU_RCP_CTRL, 1, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, csu_rcp_ctrl_fields },
+	{ CSU_RCP_DATA, 2, 10, NTHW_FPGA_REG_TYPE_WO, 0, 4, csu_rcp_data_fields },
+};
+
+static nthw_fpga_field_init_s dbs_rx_am_ctrl_fields[] = {
+	{ DBS_RX_AM_CTRL_ADR, 7, 0, 0x0000 },
+	{ DBS_RX_AM_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s dbs_rx_am_data_fields[] = {
+	{ DBS_RX_AM_DATA_ENABLE, 1, 72, 0x0000 }, { DBS_RX_AM_DATA_GPA, 64, 0, 0x0000 },
+	{ DBS_RX_AM_DATA_HID, 8, 64, 0x0000 }, { DBS_RX_AM_DATA_INT, 1, 74, 0x0000 },
+	{ DBS_RX_AM_DATA_PCKED, 1, 73, 0x0000 },
+};
+
+static nthw_fpga_field_init_s dbs_rx_control_fields[] = {
+	{ DBS_RX_CONTROL_AME, 1, 7, 0 }, { DBS_RX_CONTROL_AMS, 4, 8, 8 },
+	{ DBS_RX_CONTROL_LQ, 7, 0, 0 }, { DBS_RX_CONTROL_QE, 1, 17, 0 },
+	{ DBS_RX_CONTROL_UWE, 1, 12, 0 }, { DBS_RX_CONTROL_UWS, 4, 13, 5 },
+};
+
+static nthw_fpga_field_init_s dbs_rx_dr_ctrl_fields[] = {
+	{ DBS_RX_DR_CTRL_ADR, 7, 0, 0x0000 },
+	{ DBS_RX_DR_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s dbs_rx_dr_data_fields[] = {
+	{ DBS_RX_DR_DATA_GPA, 64, 0, 0x0000 }, { DBS_RX_DR_DATA_HDR, 1, 88, 0x0000 },
+	{ DBS_RX_DR_DATA_HID, 8, 64, 0x0000 }, { DBS_RX_DR_DATA_PCKED, 1, 87, 0x0000 },
+	{ DBS_RX_DR_DATA_QS, 15, 72, 0x0000 },
+};
+
+static nthw_fpga_field_init_s dbs_rx_idle_fields[] = {
+	{ DBS_RX_IDLE_BUSY, 1, 8, 0 },
+	{ DBS_RX_IDLE_IDLE, 1, 0, 0x0000 },
+	{ DBS_RX_IDLE_QUEUE, 7, 1, 0x0000 },
+};
+
+static nthw_fpga_field_init_s dbs_rx_init_fields[] = {
+	{ DBS_RX_INIT_BUSY, 1, 8, 0 },
+	{ DBS_RX_INIT_INIT, 1, 0, 0x0000 },
+	{ DBS_RX_INIT_QUEUE, 7, 1, 0x0000 },
+};
+
+static nthw_fpga_field_init_s dbs_rx_init_val_fields[] = {
+	{ DBS_RX_INIT_VAL_IDX, 16, 0, 0x0000 },
+	{ DBS_RX_INIT_VAL_PTR, 15, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s dbs_rx_ptr_fields[] = {
+	{ DBS_RX_PTR_PTR, 16, 0, 0x0000 },
+	{ DBS_RX_PTR_QUEUE, 7, 16, 0x0000 },
+	{ DBS_RX_PTR_VALID, 1, 23, 0x0000 },
+};
+
+static nthw_fpga_field_init_s dbs_rx_uw_ctrl_fields[] = {
+	{ DBS_RX_UW_CTRL_ADR, 7, 0, 0x0000 },
+	{ DBS_RX_UW_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s dbs_rx_uw_data_fields[] = {
+	{ DBS_RX_UW_DATA_GPA, 64, 0, 0x0000 }, { DBS_RX_UW_DATA_HID, 8, 64, 0x0000 },
+	{ DBS_RX_UW_DATA_INT, 1, 88, 0x0000 }, { DBS_RX_UW_DATA_ISTK, 1, 92, 0x0000 },
+	{ DBS_RX_UW_DATA_PCKED, 1, 87, 0x0000 }, { DBS_RX_UW_DATA_QS, 15, 72, 0x0000 },
+	{ DBS_RX_UW_DATA_VEC, 3, 89, 0x0000 },
+};
+
+static nthw_fpga_field_init_s dbs_tx_am_ctrl_fields[] = {
+	{ DBS_TX_AM_CTRL_ADR, 7, 0, 0x0000 },
+	{ DBS_TX_AM_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s dbs_tx_am_data_fields[] = {
+	{ DBS_TX_AM_DATA_ENABLE, 1, 72, 0x0000 }, { DBS_TX_AM_DATA_GPA, 64, 0, 0x0000 },
+	{ DBS_TX_AM_DATA_HID, 8, 64, 0x0000 }, { DBS_TX_AM_DATA_INT, 1, 74, 0x0000 },
+	{ DBS_TX_AM_DATA_PCKED, 1, 73, 0x0000 },
+};
+
+static nthw_fpga_field_init_s dbs_tx_control_fields[] = {
+	{ DBS_TX_CONTROL_AME, 1, 7, 0 }, { DBS_TX_CONTROL_AMS, 4, 8, 5 },
+	{ DBS_TX_CONTROL_LQ, 7, 0, 0 }, { DBS_TX_CONTROL_QE, 1, 17, 0 },
+	{ DBS_TX_CONTROL_UWE, 1, 12, 0 }, { DBS_TX_CONTROL_UWS, 4, 13, 8 },
+};
+
+static nthw_fpga_field_init_s dbs_tx_dr_ctrl_fields[] = {
+	{ DBS_TX_DR_CTRL_ADR, 7, 0, 0x0000 },
+	{ DBS_TX_DR_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s dbs_tx_dr_data_fields[] = {
+	{ DBS_TX_DR_DATA_GPA, 64, 0, 0x0000 }, { DBS_TX_DR_DATA_HDR, 1, 88, 0x0000 },
+	{ DBS_TX_DR_DATA_HID, 8, 64, 0x0000 }, { DBS_TX_DR_DATA_PCKED, 1, 87, 0x0000 },
+	{ DBS_TX_DR_DATA_PORT, 1, 89, 0x0000 }, { DBS_TX_DR_DATA_QS, 15, 72, 0x0000 },
+};
+
+static nthw_fpga_field_init_s dbs_tx_idle_fields[] = {
+	{ DBS_TX_IDLE_BUSY, 1, 8, 0 },
+	{ DBS_TX_IDLE_IDLE, 1, 0, 0x0000 },
+	{ DBS_TX_IDLE_QUEUE, 7, 1, 0x0000 },
+};
+
+static nthw_fpga_field_init_s dbs_tx_init_fields[] = {
+	{ DBS_TX_INIT_BUSY, 1, 8, 0 },
+	{ DBS_TX_INIT_INIT, 1, 0, 0x0000 },
+	{ DBS_TX_INIT_QUEUE, 7, 1, 0x0000 },
+};
+
+static nthw_fpga_field_init_s dbs_tx_init_val_fields[] = {
+	{ DBS_TX_INIT_VAL_IDX, 16, 0, 0x0000 },
+	{ DBS_TX_INIT_VAL_PTR, 15, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s dbs_tx_ptr_fields[] = {
+	{ DBS_TX_PTR_PTR, 16, 0, 0x0000 },
+	{ DBS_TX_PTR_QUEUE, 7, 16, 0x0000 },
+	{ DBS_TX_PTR_VALID, 1, 23, 0x0000 },
+};
+
+static nthw_fpga_field_init_s dbs_tx_qos_ctrl_fields[] = {
+	{ DBS_TX_QOS_CTRL_ADR, 1, 0, 0x0000 },
+	{ DBS_TX_QOS_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s dbs_tx_qos_data_fields[] = {
+	{ DBS_TX_QOS_DATA_BS, 27, 17, 0x0000 },
+	{ DBS_TX_QOS_DATA_EN, 1, 0, 0x0000 },
+	{ DBS_TX_QOS_DATA_IR, 16, 1, 0x0000 },
+};
+
+static nthw_fpga_field_init_s dbs_tx_qos_rate_fields[] = {
+	{ DBS_TX_QOS_RATE_DIV, 19, 16, 2 },
+	{ DBS_TX_QOS_RATE_MUL, 16, 0, 1 },
+};
+
+static nthw_fpga_field_init_s dbs_tx_qp_ctrl_fields[] = {
+	{ DBS_TX_QP_CTRL_ADR, 7, 0, 0x0000 },
+	{ DBS_TX_QP_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s dbs_tx_qp_data_fields[] = {
+	{ DBS_TX_QP_DATA_VPORT, 1, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s dbs_tx_uw_ctrl_fields[] = {
+	{ DBS_TX_UW_CTRL_ADR, 7, 0, 0x0000 },
+	{ DBS_TX_UW_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s dbs_tx_uw_data_fields[] = {
+	{ DBS_TX_UW_DATA_GPA, 64, 0, 0x0000 }, { DBS_TX_UW_DATA_HID, 8, 64, 0x0000 },
+	{ DBS_TX_UW_DATA_INO, 1, 93, 0x0000 }, { DBS_TX_UW_DATA_INT, 1, 88, 0x0000 },
+	{ DBS_TX_UW_DATA_ISTK, 1, 92, 0x0000 }, { DBS_TX_UW_DATA_PCKED, 1, 87, 0x0000 },
+	{ DBS_TX_UW_DATA_QS, 15, 72, 0x0000 }, { DBS_TX_UW_DATA_VEC, 3, 89, 0x0000 },
+};
+
+static nthw_fpga_register_init_s dbs_registers[] = {
+	{ DBS_RX_AM_CTRL, 10, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, dbs_rx_am_ctrl_fields },
+	{ DBS_RX_AM_DATA, 11, 75, NTHW_FPGA_REG_TYPE_WO, 0, 5, dbs_rx_am_data_fields },
+	{ DBS_RX_CONTROL, 0, 18, NTHW_FPGA_REG_TYPE_RW, 43008, 6, dbs_rx_control_fields },
+	{ DBS_RX_DR_CTRL, 18, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, dbs_rx_dr_ctrl_fields },
+	{ DBS_RX_DR_DATA, 19, 89, NTHW_FPGA_REG_TYPE_WO, 0, 5, dbs_rx_dr_data_fields },
+	{ DBS_RX_IDLE, 8, 9, NTHW_FPGA_REG_TYPE_MIXED, 0, 3, dbs_rx_idle_fields },
+	{ DBS_RX_INIT, 2, 9, NTHW_FPGA_REG_TYPE_MIXED, 0, 3, dbs_rx_init_fields },
+	{ DBS_RX_INIT_VAL, 3, 31, NTHW_FPGA_REG_TYPE_WO, 0, 2, dbs_rx_init_val_fields },
+	{ DBS_RX_PTR, 4, 24, NTHW_FPGA_REG_TYPE_MIXED, 0, 3, dbs_rx_ptr_fields },
+	{ DBS_RX_UW_CTRL, 14, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, dbs_rx_uw_ctrl_fields },
+	{ DBS_RX_UW_DATA, 15, 93, NTHW_FPGA_REG_TYPE_WO, 0, 7, dbs_rx_uw_data_fields },
+	{ DBS_TX_AM_CTRL, 12, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, dbs_tx_am_ctrl_fields },
+	{ DBS_TX_AM_DATA, 13, 75, NTHW_FPGA_REG_TYPE_WO, 0, 5, dbs_tx_am_data_fields },
+	{ DBS_TX_CONTROL, 1, 18, NTHW_FPGA_REG_TYPE_RW, 66816, 6, dbs_tx_control_fields },
+	{ DBS_TX_DR_CTRL, 20, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, dbs_tx_dr_ctrl_fields },
+	{ DBS_TX_DR_DATA, 21, 90, NTHW_FPGA_REG_TYPE_WO, 0, 6, dbs_tx_dr_data_fields },
+	{ DBS_TX_IDLE, 9, 9, NTHW_FPGA_REG_TYPE_MIXED, 0, 3, dbs_tx_idle_fields },
+	{ DBS_TX_INIT, 5, 9, NTHW_FPGA_REG_TYPE_MIXED, 0, 3, dbs_tx_init_fields },
+	{ DBS_TX_INIT_VAL, 6, 31, NTHW_FPGA_REG_TYPE_WO, 0, 2, dbs_tx_init_val_fields },
+	{ DBS_TX_PTR, 7, 24, NTHW_FPGA_REG_TYPE_MIXED, 0, 3, dbs_tx_ptr_fields },
+	{ DBS_TX_QOS_CTRL, 24, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, dbs_tx_qos_ctrl_fields },
+	{ DBS_TX_QOS_DATA, 25, 44, NTHW_FPGA_REG_TYPE_WO, 0, 3, dbs_tx_qos_data_fields },
+	{ DBS_TX_QOS_RATE, 26, 35, NTHW_FPGA_REG_TYPE_RW, 131073, 2, dbs_tx_qos_rate_fields },
+	{ DBS_TX_QP_CTRL, 22, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, dbs_tx_qp_ctrl_fields },
+	{ DBS_TX_QP_DATA, 23, 1, NTHW_FPGA_REG_TYPE_WO, 0, 1, dbs_tx_qp_data_fields },
+	{ DBS_TX_UW_CTRL, 16, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, dbs_tx_uw_ctrl_fields },
+	{ DBS_TX_UW_DATA, 17, 94, NTHW_FPGA_REG_TYPE_WO, 0, 8, dbs_tx_uw_data_fields },
+};
+
+static nthw_fpga_field_init_s flm_buf_ctrl_fields[] = {
+	{ FLM_BUF_CTRL_INF_AVAIL, 16, 16, 0x0000 },
+	{ FLM_BUF_CTRL_LRN_FREE, 16, 0, 0x0000 },
+	{ FLM_BUF_CTRL_STA_AVAIL, 16, 32, 0x0000 },
+};
+
+static nthw_fpga_field_init_s flm_control_fields[] = {
+	{ FLM_CONTROL_CRCRD, 1, 12, 0x0000 }, { FLM_CONTROL_CRCWR, 1, 11, 0x0000 },
+	{ FLM_CONTROL_EAB, 5, 18, 0 }, { FLM_CONTROL_ENABLE, 1, 0, 0 },
+	{ FLM_CONTROL_INIT, 1, 1, 0x0000 }, { FLM_CONTROL_LDS, 1, 2, 0x0000 },
+	{ FLM_CONTROL_LFS, 1, 3, 0x0000 }, { FLM_CONTROL_LIS, 1, 4, 0x0000 },
+	{ FLM_CONTROL_PDS, 1, 9, 0x0000 }, { FLM_CONTROL_PIS, 1, 10, 0x0000 },
+	{ FLM_CONTROL_RBL, 4, 13, 0 }, { FLM_CONTROL_RDS, 1, 7, 0x0000 },
+	{ FLM_CONTROL_RIS, 1, 8, 0x0000 }, { FLM_CONTROL_SPLIT_SDRAM_USAGE, 5, 23, 16 },
+	{ FLM_CONTROL_UDS, 1, 5, 0x0000 }, { FLM_CONTROL_UIS, 1, 6, 0x0000 },
+	{ FLM_CONTROL_WPD, 1, 17, 0 },
+};
+
+static nthw_fpga_field_init_s flm_inf_data_fields[] = {
+	{ FLM_INF_DATA_BYTES, 64, 0, 0x0000 }, { FLM_INF_DATA_CAUSE, 3, 264, 0x0000 },
+	{ FLM_INF_DATA_EOR, 1, 287, 0x0000 }, { FLM_INF_DATA_ID, 72, 192, 0x0000 },
+	{ FLM_INF_DATA_PACKETS, 64, 64, 0x0000 }, { FLM_INF_DATA_TS, 64, 128, 0x0000 },
+};
+
+static nthw_fpga_field_init_s flm_load_aps_fields[] = {
+	{ FLM_LOAD_APS_APS, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s flm_load_bin_fields[] = {
+	{ FLM_LOAD_BIN_BIN, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s flm_load_lps_fields[] = {
+	{ FLM_LOAD_LPS_LPS, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s flm_lrn_data_fields[] = {
+	{ FLM_LRN_DATA_ADJ, 32, 480, 0x0000 }, { FLM_LRN_DATA_COLOR, 32, 448, 0x0000 },
+	{ FLM_LRN_DATA_DSCP, 6, 734, 0x0000 }, { FLM_LRN_DATA_ENT, 1, 729, 0x0000 },
+	{ FLM_LRN_DATA_EOR, 1, 767, 0x0000 }, { FLM_LRN_DATA_FILL, 12, 584, 0x0000 },
+	{ FLM_LRN_DATA_FT, 4, 596, 0x0000 }, { FLM_LRN_DATA_FT_MBR, 4, 600, 0x0000 },
+	{ FLM_LRN_DATA_FT_MISS, 4, 604, 0x0000 }, { FLM_LRN_DATA_ID, 72, 512, 0x0000 },
+	{ FLM_LRN_DATA_KID, 8, 328, 0x0000 }, { FLM_LRN_DATA_MBR_ID1, 28, 608, 0x0000 },
+	{ FLM_LRN_DATA_MBR_ID2, 28, 636, 0x0000 }, { FLM_LRN_DATA_MBR_ID3, 28, 664, 0x0000 },
+	{ FLM_LRN_DATA_MBR_ID4, 28, 692, 0x0000 }, { FLM_LRN_DATA_NAT_EN, 1, 747, 0x0000 },
+	{ FLM_LRN_DATA_NAT_IP, 32, 336, 0x0000 }, { FLM_LRN_DATA_NAT_PORT, 16, 400, 0x0000 },
+	{ FLM_LRN_DATA_NOFI, 1, 752, 0x0000 }, { FLM_LRN_DATA_OP, 4, 730, 0x0000 },
+	{ FLM_LRN_DATA_PRIO, 2, 727, 0x0000 }, { FLM_LRN_DATA_PROT, 8, 320, 0x0000 },
+	{ FLM_LRN_DATA_QFI, 6, 740, 0x0000 }, { FLM_LRN_DATA_QW0, 128, 192, 0x0000 },
+	{ FLM_LRN_DATA_QW4, 128, 64, 0x0000 }, { FLM_LRN_DATA_RATE, 16, 416, 0x0000 },
+	{ FLM_LRN_DATA_RQI, 1, 746, 0x0000 }, { FLM_LRN_DATA_SCRUB_PROF, 4, 748, 0x0000 },
+	{ FLM_LRN_DATA_SIZE, 16, 432, 0x0000 }, { FLM_LRN_DATA_STAT_PROF, 4, 723, 0x0000 },
+	{ FLM_LRN_DATA_SW8, 32, 32, 0x0000 }, { FLM_LRN_DATA_SW9, 32, 0, 0x0000 },
+	{ FLM_LRN_DATA_TEID, 32, 368, 0x0000 }, { FLM_LRN_DATA_VOL_IDX, 3, 720, 0x0000 },
+};
+
+static nthw_fpga_field_init_s flm_prio_fields[] = {
+	{ FLM_PRIO_FT0, 4, 4, 1 }, { FLM_PRIO_FT1, 4, 12, 1 }, { FLM_PRIO_FT2, 4, 20, 1 },
+	{ FLM_PRIO_FT3, 4, 28, 1 }, { FLM_PRIO_LIMIT0, 4, 0, 0 }, { FLM_PRIO_LIMIT1, 4, 8, 0 },
+	{ FLM_PRIO_LIMIT2, 4, 16, 0 }, { FLM_PRIO_LIMIT3, 4, 24, 0 },
+};
+
+static nthw_fpga_field_init_s flm_pst_ctrl_fields[] = {
+	{ FLM_PST_CTRL_ADR, 4, 0, 0x0000 },
+	{ FLM_PST_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s flm_pst_data_fields[] = {
+	{ FLM_PST_DATA_BP, 5, 0, 0x0000 },
+	{ FLM_PST_DATA_PP, 5, 5, 0x0000 },
+	{ FLM_PST_DATA_TP, 5, 10, 0x0000 },
+};
+
+static nthw_fpga_field_init_s flm_rcp_ctrl_fields[] = {
+	{ FLM_RCP_CTRL_ADR, 5, 0, 0x0000 },
+	{ FLM_RCP_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s flm_rcp_data_fields[] = {
+	{ FLM_RCP_DATA_AUTO_IPV4_MASK, 1, 402, 0x0000 },
+	{ FLM_RCP_DATA_BYT_DYN, 5, 387, 0x0000 },
+	{ FLM_RCP_DATA_BYT_OFS, 8, 392, 0x0000 },
+	{ FLM_RCP_DATA_IPN, 1, 386, 0x0000 },
+	{ FLM_RCP_DATA_KID, 8, 377, 0x0000 },
+	{ FLM_RCP_DATA_LOOKUP, 1, 0, 0x0000 },
+	{ FLM_RCP_DATA_MASK, 320, 57, 0x0000 },
+	{ FLM_RCP_DATA_OPN, 1, 385, 0x0000 },
+	{ FLM_RCP_DATA_QW0_DYN, 5, 1, 0x0000 },
+	{ FLM_RCP_DATA_QW0_OFS, 8, 6, 0x0000 },
+	{ FLM_RCP_DATA_QW0_SEL, 2, 14, 0x0000 },
+	{ FLM_RCP_DATA_QW4_DYN, 5, 16, 0x0000 },
+	{ FLM_RCP_DATA_QW4_OFS, 8, 21, 0x0000 },
+	{ FLM_RCP_DATA_SW8_DYN, 5, 29, 0x0000 },
+	{ FLM_RCP_DATA_SW8_OFS, 8, 34, 0x0000 },
+	{ FLM_RCP_DATA_SW8_SEL, 2, 42, 0x0000 },
+	{ FLM_RCP_DATA_SW9_DYN, 5, 44, 0x0000 },
+	{ FLM_RCP_DATA_SW9_OFS, 8, 49, 0x0000 },
+	{ FLM_RCP_DATA_TXPLM, 2, 400, 0x0000 },
+};
+
+static nthw_fpga_field_init_s flm_scan_fields[] = {
+	{ FLM_SCAN_I, 16, 0, 0 },
+};
+
+static nthw_fpga_field_init_s flm_scrub_ctrl_fields[] = {
+	{ FLM_SCRUB_CTRL_ADR, 4, 0, 0x0000 },
+	{ FLM_SCRUB_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s flm_scrub_data_fields[] = {
+	{ FLM_SCRUB_DATA_T, 32, 0, 0 },
+};
+
+static nthw_fpga_field_init_s flm_status_fields[] = {
+	{ FLM_STATUS_CALIBDONE, 1, 0, 0x0000 }, { FLM_STATUS_CRCERR, 1, 5, 0x0000 },
+	{ FLM_STATUS_CRITICAL, 1, 3, 0x0000 }, { FLM_STATUS_EFT_BP, 1, 6, 0x0000 },
+	{ FLM_STATUS_IDLE, 1, 2, 0x0000 }, { FLM_STATUS_INITDONE, 1, 1, 0x0000 },
+	{ FLM_STATUS_PANIC, 1, 4, 0x0000 },
+};
+
+static nthw_fpga_field_init_s flm_stat_aul_done_fields[] = {
+	{ FLM_STAT_AUL_DONE_CNT, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s flm_stat_aul_fail_fields[] = {
+	{ FLM_STAT_AUL_FAIL_CNT, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s flm_stat_aul_ignore_fields[] = {
+	{ FLM_STAT_AUL_IGNORE_CNT, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s flm_stat_csh_hit_fields[] = {
+	{ FLM_STAT_CSH_HIT_CNT, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s flm_stat_csh_miss_fields[] = {
+	{ FLM_STAT_CSH_MISS_CNT, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s flm_stat_csh_unh_fields[] = {
+	{ FLM_STAT_CSH_UNH_CNT, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s flm_stat_cuc_move_fields[] = {
+	{ FLM_STAT_CUC_MOVE_CNT, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s flm_stat_cuc_start_fields[] = {
+	{ FLM_STAT_CUC_START_CNT, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s flm_stat_flows_fields[] = {
+	{ FLM_STAT_FLOWS_CNT, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s flm_stat_inf_done_fields[] = {
+	{ FLM_STAT_INF_DONE_CNT, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s flm_stat_inf_skip_fields[] = {
+	{ FLM_STAT_INF_SKIP_CNT, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s flm_stat_lrn_done_fields[] = {
+	{ FLM_STAT_LRN_DONE_CNT, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s flm_stat_lrn_fail_fields[] = {
+	{ FLM_STAT_LRN_FAIL_CNT, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s flm_stat_lrn_ignore_fields[] = {
+	{ FLM_STAT_LRN_IGNORE_CNT, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s flm_stat_pck_dis_fields[] = {
+	{ FLM_STAT_PCK_DIS_CNT, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s flm_stat_pck_hit_fields[] = {
+	{ FLM_STAT_PCK_HIT_CNT, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s flm_stat_pck_miss_fields[] = {
+	{ FLM_STAT_PCK_MISS_CNT, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s flm_stat_pck_unh_fields[] = {
+	{ FLM_STAT_PCK_UNH_CNT, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s flm_stat_prb_done_fields[] = {
+	{ FLM_STAT_PRB_DONE_CNT, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s flm_stat_prb_ignore_fields[] = {
+	{ FLM_STAT_PRB_IGNORE_CNT, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s flm_stat_rel_done_fields[] = {
+	{ FLM_STAT_REL_DONE_CNT, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s flm_stat_rel_ignore_fields[] = {
+	{ FLM_STAT_REL_IGNORE_CNT, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s flm_stat_sta_done_fields[] = {
+	{ FLM_STAT_STA_DONE_CNT, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s flm_stat_tul_done_fields[] = {
+	{ FLM_STAT_TUL_DONE_CNT, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s flm_stat_unl_done_fields[] = {
+	{ FLM_STAT_UNL_DONE_CNT, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s flm_stat_unl_ignore_fields[] = {
+	{ FLM_STAT_UNL_IGNORE_CNT, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s flm_sta_data_fields[] = {
+	{ FLM_STA_DATA_EOR, 1, 95, 0x0000 }, { FLM_STA_DATA_ID, 72, 0, 0x0000 },
+	{ FLM_STA_DATA_LDS, 1, 72, 0x0000 }, { FLM_STA_DATA_LFS, 1, 73, 0x0000 },
+	{ FLM_STA_DATA_LIS, 1, 74, 0x0000 }, { FLM_STA_DATA_PDS, 1, 79, 0x0000 },
+	{ FLM_STA_DATA_PIS, 1, 80, 0x0000 }, { FLM_STA_DATA_RDS, 1, 77, 0x0000 },
+	{ FLM_STA_DATA_RIS, 1, 78, 0x0000 }, { FLM_STA_DATA_UDS, 1, 75, 0x0000 },
+	{ FLM_STA_DATA_UIS, 1, 76, 0x0000 },
+};
+
+static nthw_fpga_register_init_s flm_registers[] = {
+	{ FLM_BUF_CTRL, 14, 48, NTHW_FPGA_REG_TYPE_RW, 0, 3, flm_buf_ctrl_fields },
+	{ FLM_CONTROL, 0, 28, NTHW_FPGA_REG_TYPE_MIXED, 134217728, 17, flm_control_fields },
+	{ FLM_INF_DATA, 16, 288, NTHW_FPGA_REG_TYPE_RO, 0, 6, flm_inf_data_fields },
+	{ FLM_LOAD_APS, 5, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, flm_load_aps_fields },
+	{ FLM_LOAD_BIN, 3, 32, NTHW_FPGA_REG_TYPE_WO, 0, 1, flm_load_bin_fields },
+	{ FLM_LOAD_LPS, 4, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, flm_load_lps_fields },
+	{ FLM_LRN_DATA, 15, 768, NTHW_FPGA_REG_TYPE_WO, 0, 34, flm_lrn_data_fields },
+	{ FLM_PRIO, 6, 32, NTHW_FPGA_REG_TYPE_WO, 269488144, 8, flm_prio_fields },
+	{ FLM_PST_CTRL, 12, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, flm_pst_ctrl_fields },
+	{ FLM_PST_DATA, 13, 15, NTHW_FPGA_REG_TYPE_WO, 0, 3, flm_pst_data_fields },
+	{ FLM_RCP_CTRL, 8, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, flm_rcp_ctrl_fields },
+	{ FLM_RCP_DATA, 9, 403, NTHW_FPGA_REG_TYPE_WO, 0, 19, flm_rcp_data_fields },
+	{ FLM_SCAN, 2, 16, NTHW_FPGA_REG_TYPE_WO, 0, 1, flm_scan_fields },
+	{ FLM_SCRUB_CTRL, 10, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, flm_scrub_ctrl_fields },
+	{ FLM_SCRUB_DATA, 11, 32, NTHW_FPGA_REG_TYPE_WO, 0, 1, flm_scrub_data_fields },
+	{ FLM_STATUS, 1, 12, NTHW_FPGA_REG_TYPE_MIXED, 0, 7, flm_status_fields },
+	{ FLM_STAT_AUL_DONE, 41, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, flm_stat_aul_done_fields },
+	{ FLM_STAT_AUL_FAIL, 43, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, flm_stat_aul_fail_fields },
+	{ FLM_STAT_AUL_IGNORE, 42, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, flm_stat_aul_ignore_fields },
+	{ FLM_STAT_CSH_HIT, 52, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, flm_stat_csh_hit_fields },
+	{ FLM_STAT_CSH_MISS, 53, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, flm_stat_csh_miss_fields },
+	{ FLM_STAT_CSH_UNH, 54, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, flm_stat_csh_unh_fields },
+	{ FLM_STAT_CUC_MOVE, 56, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, flm_stat_cuc_move_fields },
+	{ FLM_STAT_CUC_START, 55, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, flm_stat_cuc_start_fields },
+	{ FLM_STAT_FLOWS, 18, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, flm_stat_flows_fields },
+	{ FLM_STAT_INF_DONE, 46, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, flm_stat_inf_done_fields },
+	{ FLM_STAT_INF_SKIP, 47, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, flm_stat_inf_skip_fields },
+	{ FLM_STAT_LRN_DONE, 32, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, flm_stat_lrn_done_fields },
+	{ FLM_STAT_LRN_FAIL, 34, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, flm_stat_lrn_fail_fields },
+	{ FLM_STAT_LRN_IGNORE, 33, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, flm_stat_lrn_ignore_fields },
+	{ FLM_STAT_PCK_DIS, 51, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, flm_stat_pck_dis_fields },
+	{ FLM_STAT_PCK_HIT, 48, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, flm_stat_pck_hit_fields },
+	{ FLM_STAT_PCK_MISS, 49, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, flm_stat_pck_miss_fields },
+	{ FLM_STAT_PCK_UNH, 50, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, flm_stat_pck_unh_fields },
+	{ FLM_STAT_PRB_DONE, 39, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, flm_stat_prb_done_fields },
+	{ FLM_STAT_PRB_IGNORE, 40, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, flm_stat_prb_ignore_fields },
+	{ FLM_STAT_REL_DONE, 37, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, flm_stat_rel_done_fields },
+	{ FLM_STAT_REL_IGNORE, 38, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, flm_stat_rel_ignore_fields },
+	{ FLM_STAT_STA_DONE, 45, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, flm_stat_sta_done_fields },
+	{ FLM_STAT_TUL_DONE, 44, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, flm_stat_tul_done_fields },
+	{ FLM_STAT_UNL_DONE, 35, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, flm_stat_unl_done_fields },
+	{ FLM_STAT_UNL_IGNORE, 36, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, flm_stat_unl_ignore_fields },
+	{ FLM_STA_DATA, 17, 96, NTHW_FPGA_REG_TYPE_RO, 0, 11, flm_sta_data_fields },
+};
+
+static nthw_fpga_field_init_s gfg_burstsize0_fields[] = {
+	{ GFG_BURSTSIZE0_VAL, 24, 0, 0 },
+};
+
+static nthw_fpga_field_init_s gfg_burstsize1_fields[] = {
+	{ GFG_BURSTSIZE1_VAL, 24, 0, 0 },
+};
+
+static nthw_fpga_field_init_s gfg_ctrl0_fields[] = {
+	{ GFG_CTRL0_ENABLE, 1, 0, 0 },
+	{ GFG_CTRL0_MODE, 3, 1, 0 },
+	{ GFG_CTRL0_PRBS_EN, 1, 4, 0 },
+	{ GFG_CTRL0_SIZE, 14, 16, 64 },
+};
+
+static nthw_fpga_field_init_s gfg_ctrl1_fields[] = {
+	{ GFG_CTRL1_ENABLE, 1, 0, 0 },
+	{ GFG_CTRL1_MODE, 3, 1, 0 },
+	{ GFG_CTRL1_PRBS_EN, 1, 4, 0 },
+	{ GFG_CTRL1_SIZE, 14, 16, 64 },
+};
+
+static nthw_fpga_field_init_s gfg_run0_fields[] = {
+	{ GFG_RUN0_RUN, 1, 0, 0 },
+};
+
+static nthw_fpga_field_init_s gfg_run1_fields[] = {
+	{ GFG_RUN1_RUN, 1, 0, 0 },
+};
+
+static nthw_fpga_field_init_s gfg_sizemask0_fields[] = {
+	{ GFG_SIZEMASK0_VAL, 14, 0, 0 },
+};
+
+static nthw_fpga_field_init_s gfg_sizemask1_fields[] = {
+	{ GFG_SIZEMASK1_VAL, 14, 0, 0 },
+};
+
+static nthw_fpga_field_init_s gfg_streamid0_fields[] = {
+	{ GFG_STREAMID0_VAL, 8, 0, 0 },
+};
+
+static nthw_fpga_field_init_s gfg_streamid1_fields[] = {
+	{ GFG_STREAMID1_VAL, 8, 0, 1 },
+};
+
+static nthw_fpga_register_init_s gfg_registers[] = {
+	{ GFG_BURSTSIZE0, 3, 24, NTHW_FPGA_REG_TYPE_WO, 0, 1, gfg_burstsize0_fields },
+	{ GFG_BURSTSIZE1, 8, 24, NTHW_FPGA_REG_TYPE_WO, 0, 1, gfg_burstsize1_fields },
+	{ GFG_CTRL0, 0, 30, NTHW_FPGA_REG_TYPE_WO, 4194304, 4, gfg_ctrl0_fields },
+	{ GFG_CTRL1, 5, 30, NTHW_FPGA_REG_TYPE_WO, 4194304, 4, gfg_ctrl1_fields },
+	{ GFG_RUN0, 1, 1, NTHW_FPGA_REG_TYPE_WO, 0, 1, gfg_run0_fields },
+	{ GFG_RUN1, 6, 1, NTHW_FPGA_REG_TYPE_WO, 0, 1, gfg_run1_fields },
+	{ GFG_SIZEMASK0, 4, 14, NTHW_FPGA_REG_TYPE_WO, 0, 1, gfg_sizemask0_fields },
+	{ GFG_SIZEMASK1, 9, 14, NTHW_FPGA_REG_TYPE_WO, 0, 1, gfg_sizemask1_fields },
+	{ GFG_STREAMID0, 2, 8, NTHW_FPGA_REG_TYPE_WO, 0, 1, gfg_streamid0_fields },
+	{ GFG_STREAMID1, 7, 8, NTHW_FPGA_REG_TYPE_WO, 1, 1, gfg_streamid1_fields },
+};
+
+static nthw_fpga_field_init_s gmf_ctrl_fields[] = {
+	{ GMF_CTRL_ENABLE, 1, 0, 0 },
+	{ GMF_CTRL_FCS_ALWAYS, 1, 1, 0 },
+	{ GMF_CTRL_IFG_AUTO_ADJUST_ENABLE, 1, 7, 0 },
+	{ GMF_CTRL_IFG_ENABLE, 1, 2, 0 },
+	{ GMF_CTRL_IFG_TX_NOW_ALWAYS, 1, 3, 0 },
+	{ GMF_CTRL_IFG_TX_NOW_ON_TS_ENABLE, 1, 5, 0 },
+	{ GMF_CTRL_IFG_TX_ON_TS_ADJUST_ON_SET_CLOCK, 1, 6, 0 },
+	{ GMF_CTRL_IFG_TX_ON_TS_ALWAYS, 1, 4, 0 },
+	{ GMF_CTRL_TS_INJECT_ALWAYS, 1, 8, 0 },
+	{ GMF_CTRL_TS_INJECT_DUAL_STEP, 1, 9, 0 },
+};
+
+static nthw_fpga_field_init_s gmf_debug_lane_marker_fields[] = {
+	{ GMF_DEBUG_LANE_MARKER_COMPENSATION, 16, 0, 16384 },
+};
+
+static nthw_fpga_field_init_s gmf_ifg_max_adjust_slack_fields[] = {
+	{ GMF_IFG_MAX_ADJUST_SLACK_SLACK, 64, 0, 0 },
+};
+
+static nthw_fpga_field_init_s gmf_ifg_set_clock_delta_fields[] = {
+	{ GMF_IFG_SET_CLOCK_DELTA_DELTA, 64, 0, 0 },
+};
+
+static nthw_fpga_field_init_s gmf_ifg_set_clock_delta_adjust_fields[] = {
+	{ GMF_IFG_SET_CLOCK_DELTA_ADJUST_DELTA, 64, 0, 0 },
+};
+
+static nthw_fpga_field_init_s gmf_ifg_tx_now_on_ts_fields[] = {
+	{ GMF_IFG_TX_NOW_ON_TS_TS, 64, 0, 0 },
+};
+
+static nthw_fpga_field_init_s gmf_speed_fields[] = {
+	{ GMF_SPEED_IFG_SPEED, 64, 0, 0 },
+};
+
+static nthw_fpga_field_init_s gmf_stat_data_buffer_fields[] = {
+	{ GMF_STAT_DATA_BUFFER_USED, 15, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s gmf_stat_max_delayed_pkt_fields[] = {
+	{ GMF_STAT_MAX_DELAYED_PKT_NS, 64, 0, 0 },
+};
+
+static nthw_fpga_field_init_s gmf_stat_next_pkt_fields[] = {
+	{ GMF_STAT_NEXT_PKT_NS, 64, 0, 0 },
+};
+
+static nthw_fpga_field_init_s gmf_stat_sticky_fields[] = {
+	{ GMF_STAT_STICKY_DATA_UNDERFLOWED, 1, 0, 0 },
+	{ GMF_STAT_STICKY_IFG_ADJUSTED, 1, 1, 0 },
+};
+
+static nthw_fpga_field_init_s gmf_ts_inject_fields[] = {
+	{ GMF_TS_INJECT_OFFSET, 14, 0, 0 },
+	{ GMF_TS_INJECT_POS, 2, 14, 0 },
+};
+
+static nthw_fpga_register_init_s gmf_registers[] = {
+	{ GMF_CTRL, 0, 10, NTHW_FPGA_REG_TYPE_WO, 0, 10, gmf_ctrl_fields },
+	{
+		GMF_DEBUG_LANE_MARKER, 7, 16, NTHW_FPGA_REG_TYPE_WO, 16384, 1,
+		gmf_debug_lane_marker_fields
+	},
+	{
+		GMF_IFG_MAX_ADJUST_SLACK, 4, 64, NTHW_FPGA_REG_TYPE_WO, 0, 1,
+		gmf_ifg_max_adjust_slack_fields
+	},
+	{
+		GMF_IFG_SET_CLOCK_DELTA, 2, 64, NTHW_FPGA_REG_TYPE_WO, 0, 1,
+		gmf_ifg_set_clock_delta_fields
+	},
+	{
+		GMF_IFG_SET_CLOCK_DELTA_ADJUST, 3, 64, NTHW_FPGA_REG_TYPE_WO, 0, 1,
+		gmf_ifg_set_clock_delta_adjust_fields
+	},
+	{ GMF_IFG_TX_NOW_ON_TS, 5, 64, NTHW_FPGA_REG_TYPE_WO, 0, 1, gmf_ifg_tx_now_on_ts_fields },
+	{ GMF_SPEED, 1, 64, NTHW_FPGA_REG_TYPE_WO, 0, 1, gmf_speed_fields },
+	{ GMF_STAT_DATA_BUFFER, 9, 15, NTHW_FPGA_REG_TYPE_RO, 0, 1, gmf_stat_data_buffer_fields },
+	{
+		GMF_STAT_MAX_DELAYED_PKT, 11, 64, NTHW_FPGA_REG_TYPE_RC1, 0, 1,
+		gmf_stat_max_delayed_pkt_fields
+	},
+	{ GMF_STAT_NEXT_PKT, 10, 64, NTHW_FPGA_REG_TYPE_RO, 0, 1, gmf_stat_next_pkt_fields },
+	{ GMF_STAT_STICKY, 8, 2, NTHW_FPGA_REG_TYPE_RC1, 0, 2, gmf_stat_sticky_fields },
+	{ GMF_TS_INJECT, 6, 16, NTHW_FPGA_REG_TYPE_WO, 0, 2, gmf_ts_inject_fields },
+};
+
+static nthw_fpga_field_init_s gpio_phy_cfg_fields[] = {
+	{ GPIO_PHY_CFG_E_PORT0_RXLOS, 1, 8, 0 }, { GPIO_PHY_CFG_E_PORT1_RXLOS, 1, 9, 0 },
+	{ GPIO_PHY_CFG_PORT0_INT_B, 1, 1, 1 }, { GPIO_PHY_CFG_PORT0_LPMODE, 1, 0, 0 },
+	{ GPIO_PHY_CFG_PORT0_MODPRS_B, 1, 3, 1 }, { GPIO_PHY_CFG_PORT0_RESET_B, 1, 2, 0 },
+	{ GPIO_PHY_CFG_PORT1_INT_B, 1, 5, 1 }, { GPIO_PHY_CFG_PORT1_LPMODE, 1, 4, 0 },
+	{ GPIO_PHY_CFG_PORT1_MODPRS_B, 1, 7, 1 }, { GPIO_PHY_CFG_PORT1_RESET_B, 1, 6, 0 },
+};
+
+static nthw_fpga_field_init_s gpio_phy_gpio_fields[] = {
+	{ GPIO_PHY_GPIO_E_PORT0_RXLOS, 1, 8, 0 }, { GPIO_PHY_GPIO_E_PORT1_RXLOS, 1, 9, 0 },
+	{ GPIO_PHY_GPIO_PORT0_INT_B, 1, 1, 0x0000 }, { GPIO_PHY_GPIO_PORT0_LPMODE, 1, 0, 1 },
+	{ GPIO_PHY_GPIO_PORT0_MODPRS_B, 1, 3, 0x0000 }, { GPIO_PHY_GPIO_PORT0_RESET_B, 1, 2, 0 },
+	{ GPIO_PHY_GPIO_PORT1_INT_B, 1, 5, 0x0000 }, { GPIO_PHY_GPIO_PORT1_LPMODE, 1, 4, 1 },
+	{ GPIO_PHY_GPIO_PORT1_MODPRS_B, 1, 7, 0x0000 }, { GPIO_PHY_GPIO_PORT1_RESET_B, 1, 6, 0 },
+};
+
+static nthw_fpga_register_init_s gpio_phy_registers[] = {
+	{ GPIO_PHY_CFG, 0, 10, NTHW_FPGA_REG_TYPE_RW, 170, 10, gpio_phy_cfg_fields },
+	{ GPIO_PHY_GPIO, 1, 10, NTHW_FPGA_REG_TYPE_RW, 17, 10, gpio_phy_gpio_fields },
+};
+
+static nthw_fpga_field_init_s hfu_rcp_ctrl_fields[] = {
+	{ HFU_RCP_CTRL_ADR, 6, 0, 0x0000 },
+	{ HFU_RCP_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s hfu_rcp_data_fields[] = {
+	{ HFU_RCP_DATA_LEN_A_ADD_DYN, 5, 15, 0x0000 },
+	{ HFU_RCP_DATA_LEN_A_ADD_OFS, 8, 20, 0x0000 },
+	{ HFU_RCP_DATA_LEN_A_OL4LEN, 1, 1, 0x0000 },
+	{ HFU_RCP_DATA_LEN_A_POS_DYN, 5, 2, 0x0000 },
+	{ HFU_RCP_DATA_LEN_A_POS_OFS, 8, 7, 0x0000 },
+	{ HFU_RCP_DATA_LEN_A_SUB_DYN, 5, 28, 0x0000 },
+	{ HFU_RCP_DATA_LEN_A_WR, 1, 0, 0x0000 },
+	{ HFU_RCP_DATA_LEN_B_ADD_DYN, 5, 47, 0x0000 },
+	{ HFU_RCP_DATA_LEN_B_ADD_OFS, 8, 52, 0x0000 },
+	{ HFU_RCP_DATA_LEN_B_POS_DYN, 5, 34, 0x0000 },
+	{ HFU_RCP_DATA_LEN_B_POS_OFS, 8, 39, 0x0000 },
+	{ HFU_RCP_DATA_LEN_B_SUB_DYN, 5, 60, 0x0000 },
+	{ HFU_RCP_DATA_LEN_B_WR, 1, 33, 0x0000 },
+	{ HFU_RCP_DATA_LEN_C_ADD_DYN, 5, 79, 0x0000 },
+	{ HFU_RCP_DATA_LEN_C_ADD_OFS, 8, 84, 0x0000 },
+	{ HFU_RCP_DATA_LEN_C_POS_DYN, 5, 66, 0x0000 },
+	{ HFU_RCP_DATA_LEN_C_POS_OFS, 8, 71, 0x0000 },
+	{ HFU_RCP_DATA_LEN_C_SUB_DYN, 5, 92, 0x0000 },
+	{ HFU_RCP_DATA_LEN_C_WR, 1, 65, 0x0000 },
+	{ HFU_RCP_DATA_TTL_POS_DYN, 5, 98, 0x0000 },
+	{ HFU_RCP_DATA_TTL_POS_OFS, 8, 103, 0x0000 },
+	{ HFU_RCP_DATA_TTL_WR, 1, 97, 0x0000 },
+};
+
+static nthw_fpga_register_init_s hfu_registers[] = {
+	{ HFU_RCP_CTRL, 0, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, hfu_rcp_ctrl_fields },
+	{ HFU_RCP_DATA, 1, 111, NTHW_FPGA_REG_TYPE_WO, 0, 22, hfu_rcp_data_fields },
+};
+
+static nthw_fpga_field_init_s hif_build_time_fields[] = {
+	{ HIF_BUILD_TIME_TIME, 32, 0, 1713859545 },
+};
+
+static nthw_fpga_field_init_s hif_config_fields[] = {
+	{ HIF_CONFIG_EXT_TAG, 1, 6, 0x0000 },
+	{ HIF_CONFIG_MAX_READ, 3, 3, 0x0000 },
+	{ HIF_CONFIG_MAX_TLP, 3, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s hif_control_fields[] = {
+	{ HIF_CONTROL_BLESSED, 8, 4, 0 },
+	{ HIF_CONTROL_FSR, 1, 12, 1 },
+	{ HIF_CONTROL_WRAW, 4, 0, 1 },
+};
+
+static nthw_fpga_field_init_s hif_prod_id_ex_fields[] = {
+	{ HIF_PROD_ID_EX_LAYOUT, 1, 31, 0 },
+	{ HIF_PROD_ID_EX_LAYOUT_VERSION, 8, 0, 1 },
+	{ HIF_PROD_ID_EX_RESERVED, 23, 8, 0 },
+};
+
+static nthw_fpga_field_init_s hif_prod_id_lsb_fields[] = {
+	{ HIF_PROD_ID_LSB_GROUP_ID, 16, 16, 9563 },
+	{ HIF_PROD_ID_LSB_REV_ID, 8, 0, 39 },
+	{ HIF_PROD_ID_LSB_VER_ID, 8, 8, 55 },
+};
+
+static nthw_fpga_field_init_s hif_prod_id_msb_fields[] = {
+	{ HIF_PROD_ID_MSB_BUILD_NO, 10, 12, 0 },
+	{ HIF_PROD_ID_MSB_TYPE_ID, 12, 0, 200 },
+};
+
+static nthw_fpga_field_init_s hif_sample_time_fields[] = {
+	{ HIF_SAMPLE_TIME_SAMPLE_TIME, 1, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s hif_status_fields[] = {
+	{ HIF_STATUS_RD_ERR, 1, 9, 0 },
+	{ HIF_STATUS_TAGS_IN_USE, 8, 0, 0 },
+	{ HIF_STATUS_WR_ERR, 1, 8, 0 },
+};
+
+static nthw_fpga_field_init_s hif_stat_ctrl_fields[] = {
+	{ HIF_STAT_CTRL_STAT_ENA, 1, 1, 0 },
+	{ HIF_STAT_CTRL_STAT_REQ, 1, 0, 0 },
+};
+
+static nthw_fpga_field_init_s hif_stat_refclk_fields[] = {
+	{ HIF_STAT_REFCLK_REFCLK250, 32, 0, 0 },
+};
+
+static nthw_fpga_field_init_s hif_stat_rx_fields[] = {
+	{ HIF_STAT_RX_COUNTER, 32, 0, 0 },
+};
+
+static nthw_fpga_field_init_s hif_stat_tx_fields[] = {
+	{ HIF_STAT_TX_COUNTER, 32, 0, 0 },
+};
+
+static nthw_fpga_field_init_s hif_test0_fields[] = {
+	{ HIF_TEST0_DATA, 32, 0, 287454020 },
+};
+
+static nthw_fpga_field_init_s hif_test1_fields[] = {
+	{ HIF_TEST1_DATA, 32, 0, 2864434397 },
+};
+
+static nthw_fpga_field_init_s hif_uuid0_fields[] = {
+	{ HIF_UUID0_UUID0, 32, 0, 1237800326 },
+};
+
+static nthw_fpga_field_init_s hif_uuid1_fields[] = {
+	{ HIF_UUID1_UUID1, 32, 0, 3057550372 },
+};
+
+static nthw_fpga_field_init_s hif_uuid2_fields[] = {
+	{ HIF_UUID2_UUID2, 32, 0, 2445752330 },
+};
+
+static nthw_fpga_field_init_s hif_uuid3_fields[] = {
+	{ HIF_UUID3_UUID3, 32, 0, 1864147557 },
+};
+
+static nthw_fpga_register_init_s hif_registers[] = {
+	{ HIF_BUILD_TIME, 16, 32, NTHW_FPGA_REG_TYPE_RO, 1713859545, 1, hif_build_time_fields },
+	{ HIF_CONFIG, 24, 7, NTHW_FPGA_REG_TYPE_RW, 0, 3, hif_config_fields },
+	{ HIF_CONTROL, 40, 13, NTHW_FPGA_REG_TYPE_MIXED, 4097, 3, hif_control_fields },
+	{ HIF_PROD_ID_EX, 112, 32, NTHW_FPGA_REG_TYPE_RO, 1, 3, hif_prod_id_ex_fields },
+	{ HIF_PROD_ID_LSB, 0, 32, NTHW_FPGA_REG_TYPE_RO, 626734887, 3, hif_prod_id_lsb_fields },
+	{ HIF_PROD_ID_MSB, 8, 22, NTHW_FPGA_REG_TYPE_RO, 200, 2, hif_prod_id_msb_fields },
+	{ HIF_SAMPLE_TIME, 96, 1, NTHW_FPGA_REG_TYPE_WO, 0, 1, hif_sample_time_fields },
+	{ HIF_STATUS, 32, 10, NTHW_FPGA_REG_TYPE_MIXED, 0, 3, hif_status_fields },
+	{ HIF_STAT_CTRL, 64, 2, NTHW_FPGA_REG_TYPE_WO, 0, 2, hif_stat_ctrl_fields },
+	{ HIF_STAT_REFCLK, 72, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, hif_stat_refclk_fields },
+	{ HIF_STAT_RX, 88, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, hif_stat_rx_fields },
+	{ HIF_STAT_TX, 80, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, hif_stat_tx_fields },
+	{ HIF_TEST0, 48, 32, NTHW_FPGA_REG_TYPE_RW, 287454020, 1, hif_test0_fields },
+	{ HIF_TEST1, 56, 32, NTHW_FPGA_REG_TYPE_RW, 2864434397, 1, hif_test1_fields },
+	{ HIF_UUID0, 128, 32, NTHW_FPGA_REG_TYPE_RO, 1237800326, 1, hif_uuid0_fields },
+	{ HIF_UUID1, 144, 32, NTHW_FPGA_REG_TYPE_RO, 3057550372, 1, hif_uuid1_fields },
+	{ HIF_UUID2, 160, 32, NTHW_FPGA_REG_TYPE_RO, 2445752330, 1, hif_uuid2_fields },
+	{ HIF_UUID3, 176, 32, NTHW_FPGA_REG_TYPE_RO, 1864147557, 1, hif_uuid3_fields },
+};
+
+static nthw_fpga_field_init_s hsh_rcp_ctrl_fields[] = {
+	{ HSH_RCP_CTRL_ADR, 4, 0, 0x0000 },
+	{ HSH_RCP_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s hsh_rcp_data_fields[] = {
+	{ HSH_RCP_DATA_AUTO_IPV4_MASK, 1, 742, 0x0000 },
+	{ HSH_RCP_DATA_HSH_TYPE, 5, 416, 0x0000 },
+	{ HSH_RCP_DATA_HSH_VALID, 1, 415, 0x0000 },
+	{ HSH_RCP_DATA_K, 320, 422, 0x0000 },
+	{ HSH_RCP_DATA_LOAD_DIST_TYPE, 2, 0, 0x0000 },
+	{ HSH_RCP_DATA_MAC_PORT_MASK, 2, 2, 0x0000 },
+	{ HSH_RCP_DATA_P_MASK, 1, 61, 0x0000 },
+	{ HSH_RCP_DATA_QW0_OFS, 8, 11, 0x0000 },
+	{ HSH_RCP_DATA_QW0_PE, 5, 6, 0x0000 },
+	{ HSH_RCP_DATA_QW4_OFS, 8, 24, 0x0000 },
+	{ HSH_RCP_DATA_QW4_PE, 5, 19, 0x0000 },
+	{ HSH_RCP_DATA_SEED, 32, 382, 0x0000 },
+	{ HSH_RCP_DATA_SORT, 2, 4, 0x0000 },
+	{ HSH_RCP_DATA_TNL_P, 1, 414, 0x0000 },
+	{ HSH_RCP_DATA_TOEPLITZ, 1, 421, 0x0000 },
+	{ HSH_RCP_DATA_W8_OFS, 8, 37, 0x0000 },
+	{ HSH_RCP_DATA_W8_PE, 5, 32, 0x0000 },
+	{ HSH_RCP_DATA_W8_SORT, 1, 45, 0x0000 },
+	{ HSH_RCP_DATA_W9_OFS, 8, 51, 0x0000 },
+	{ HSH_RCP_DATA_W9_P, 1, 60, 0x0000 },
+	{ HSH_RCP_DATA_W9_PE, 5, 46, 0x0000 },
+	{ HSH_RCP_DATA_W9_SORT, 1, 59, 0x0000 },
+	{ HSH_RCP_DATA_WORD_MASK, 320, 62, 0x0000 },
+};
+
+static nthw_fpga_register_init_s hsh_registers[] = {
+	{ HSH_RCP_CTRL, 0, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, hsh_rcp_ctrl_fields },
+	{ HSH_RCP_DATA, 1, 743, NTHW_FPGA_REG_TYPE_WO, 0, 23, hsh_rcp_data_fields },
+};
+
+static nthw_fpga_field_init_s ifr_counters_ctrl_fields[] = {
+	{ IFR_COUNTERS_CTRL_ADR, 4, 0, 0x0000 },
+	{ IFR_COUNTERS_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s ifr_counters_data_fields[] = {
+	{ IFR_COUNTERS_DATA_DROP, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s ifr_df_buf_ctrl_fields[] = {
+	{ IFR_DF_BUF_CTRL_AVAILABLE, 11, 0, 0x0000 },
+	{ IFR_DF_BUF_CTRL_MTU_PROFILE, 16, 11, 0x0000 },
+};
+
+static nthw_fpga_field_init_s ifr_df_buf_data_fields[] = {
+	{ IFR_DF_BUF_DATA_FIFO_DAT, 128, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s ifr_rcp_ctrl_fields[] = {
+	{ IFR_RCP_CTRL_ADR, 4, 0, 0x0000 },
+	{ IFR_RCP_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s ifr_rcp_data_fields[] = {
+	{ IFR_RCP_DATA_IPV4_DF_DROP, 1, 17, 0x0000 }, { IFR_RCP_DATA_IPV4_EN, 1, 0, 0x0000 },
+	{ IFR_RCP_DATA_IPV6_DROP, 1, 16, 0x0000 }, { IFR_RCP_DATA_IPV6_EN, 1, 1, 0x0000 },
+	{ IFR_RCP_DATA_MTU, 14, 2, 0x0000 },
+};
+
+static nthw_fpga_register_init_s ifr_registers[] = {
+	{ IFR_COUNTERS_CTRL, 4, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, ifr_counters_ctrl_fields },
+	{ IFR_COUNTERS_DATA, 5, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, ifr_counters_data_fields },
+	{ IFR_DF_BUF_CTRL, 2, 27, NTHW_FPGA_REG_TYPE_RO, 0, 2, ifr_df_buf_ctrl_fields },
+	{ IFR_DF_BUF_DATA, 3, 128, NTHW_FPGA_REG_TYPE_RO, 0, 1, ifr_df_buf_data_fields },
+	{ IFR_RCP_CTRL, 0, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, ifr_rcp_ctrl_fields },
+	{ IFR_RCP_DATA, 1, 18, NTHW_FPGA_REG_TYPE_WO, 0, 5, ifr_rcp_data_fields },
+};
+
+static nthw_fpga_field_init_s iic_adr_fields[] = {
+	{ IIC_ADR_SLV_ADR, 7, 1, 0 },
+};
+
+static nthw_fpga_field_init_s iic_cr_fields[] = {
+	{ IIC_CR_EN, 1, 0, 0 }, { IIC_CR_GC_EN, 1, 6, 0 }, { IIC_CR_MSMS, 1, 2, 0 },
+	{ IIC_CR_RST, 1, 7, 0 }, { IIC_CR_RSTA, 1, 5, 0 }, { IIC_CR_TX, 1, 3, 0 },
+	{ IIC_CR_TXAK, 1, 4, 0 }, { IIC_CR_TXFIFO_RESET, 1, 1, 0 },
+};
+
+static nthw_fpga_field_init_s iic_dgie_fields[] = {
+	{ IIC_DGIE_GIE, 1, 31, 0 },
+};
+
+static nthw_fpga_field_init_s iic_gpo_fields[] = {
+	{ IIC_GPO_GPO_VAL, 1, 0, 0 },
+};
+
+static nthw_fpga_field_init_s iic_ier_fields[] = {
+	{ IIC_IER_INT0, 1, 0, 0 }, { IIC_IER_INT1, 1, 1, 0 }, { IIC_IER_INT2, 1, 2, 0 },
+	{ IIC_IER_INT3, 1, 3, 0 }, { IIC_IER_INT4, 1, 4, 0 }, { IIC_IER_INT5, 1, 5, 0 },
+	{ IIC_IER_INT6, 1, 6, 0 }, { IIC_IER_INT7, 1, 7, 0 },
+};
+
+static nthw_fpga_field_init_s iic_isr_fields[] = {
+	{ IIC_ISR_INT0, 1, 0, 0 }, { IIC_ISR_INT1, 1, 1, 0 }, { IIC_ISR_INT2, 1, 2, 0 },
+	{ IIC_ISR_INT3, 1, 3, 0 }, { IIC_ISR_INT4, 1, 4, 0 }, { IIC_ISR_INT5, 1, 5, 0 },
+	{ IIC_ISR_INT6, 1, 6, 0 }, { IIC_ISR_INT7, 1, 7, 0 },
+};
+
+static nthw_fpga_field_init_s iic_rx_fifo_fields[] = {
+	{ IIC_RX_FIFO_RXDATA, 8, 0, 0 },
+};
+
+static nthw_fpga_field_init_s iic_rx_fifo_ocy_fields[] = {
+	{ IIC_RX_FIFO_OCY_OCY_VAL, 4, 0, 0 },
+};
+
+static nthw_fpga_field_init_s iic_rx_fifo_pirq_fields[] = {
+	{ IIC_RX_FIFO_PIRQ_CMP_VAL, 4, 0, 0 },
+};
+
+static nthw_fpga_field_init_s iic_softr_fields[] = {
+	{ IIC_SOFTR_RKEY, 4, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s iic_sr_fields[] = {
+	{ IIC_SR_AAS, 1, 1, 0 }, { IIC_SR_ABGC, 1, 0, 0 }, { IIC_SR_BB, 1, 2, 0 },
+	{ IIC_SR_RXFIFO_EMPTY, 1, 6, 1 }, { IIC_SR_RXFIFO_FULL, 1, 5, 0 }, { IIC_SR_SRW, 1, 3, 0 },
+	{ IIC_SR_TXFIFO_EMPTY, 1, 7, 1 }, { IIC_SR_TXFIFO_FULL, 1, 4, 0 },
+};
+
+static nthw_fpga_field_init_s iic_tbuf_fields[] = {
+	{ IIC_TBUF_TBUF_VAL, 32, 0, 0 },
+};
+
+static nthw_fpga_field_init_s iic_ten_adr_fields[] = {
+	{ IIC_TEN_ADR_MSB_SLV_ADR, 3, 0, 0 },
+};
+
+static nthw_fpga_field_init_s iic_thddat_fields[] = {
+	{ IIC_THDDAT_THDDAT_VAL, 32, 0, 0 },
+};
+
+static nthw_fpga_field_init_s iic_thdsta_fields[] = {
+	{ IIC_THDSTA_THDSTA_VAL, 32, 0, 0 },
+};
+
+static nthw_fpga_field_init_s iic_thigh_fields[] = {
+	{ IIC_THIGH_THIGH_VAL, 32, 0, 0 },
+};
+
+static nthw_fpga_field_init_s iic_tlow_fields[] = {
+	{ IIC_TLOW_TLOW_VAL, 32, 0, 0 },
+};
+
+static nthw_fpga_field_init_s iic_tsudat_fields[] = {
+	{ IIC_TSUDAT_TSUDAT_VAL, 32, 0, 0 },
+};
+
+static nthw_fpga_field_init_s iic_tsusta_fields[] = {
+	{ IIC_TSUSTA_TSUSTA_VAL, 32, 0, 0 },
+};
+
+static nthw_fpga_field_init_s iic_tsusto_fields[] = {
+	{ IIC_TSUSTO_TSUSTO_VAL, 32, 0, 0 },
+};
+
+static nthw_fpga_field_init_s iic_tx_fifo_fields[] = {
+	{ IIC_TX_FIFO_START, 1, 8, 0 },
+	{ IIC_TX_FIFO_STOP, 1, 9, 0 },
+	{ IIC_TX_FIFO_TXDATA, 8, 0, 0 },
+};
+
+static nthw_fpga_field_init_s iic_tx_fifo_ocy_fields[] = {
+	{ IIC_TX_FIFO_OCY_OCY_VAL, 4, 0, 0 },
+};
+
+static nthw_fpga_register_init_s iic_registers[] = {
+	{ IIC_ADR, 68, 8, NTHW_FPGA_REG_TYPE_RW, 0, 1, iic_adr_fields },
+	{ IIC_CR, 64, 8, NTHW_FPGA_REG_TYPE_RW, 0, 8, iic_cr_fields },
+	{ IIC_DGIE, 7, 32, NTHW_FPGA_REG_TYPE_RW, 0, 1, iic_dgie_fields },
+	{ IIC_GPO, 73, 1, NTHW_FPGA_REG_TYPE_RW, 0, 1, iic_gpo_fields },
+	{ IIC_IER, 10, 8, NTHW_FPGA_REG_TYPE_RW, 0, 8, iic_ier_fields },
+	{ IIC_ISR, 8, 8, NTHW_FPGA_REG_TYPE_RW, 0, 8, iic_isr_fields },
+	{ IIC_RX_FIFO, 67, 8, NTHW_FPGA_REG_TYPE_RO, 0, 1, iic_rx_fifo_fields },
+	{ IIC_RX_FIFO_OCY, 70, 4, NTHW_FPGA_REG_TYPE_RO, 0, 1, iic_rx_fifo_ocy_fields },
+	{ IIC_RX_FIFO_PIRQ, 72, 4, NTHW_FPGA_REG_TYPE_RW, 0, 1, iic_rx_fifo_pirq_fields },
+	{ IIC_SOFTR, 16, 4, NTHW_FPGA_REG_TYPE_WO, 0, 1, iic_softr_fields },
+	{ IIC_SR, 65, 8, NTHW_FPGA_REG_TYPE_RO, 192, 8, iic_sr_fields },
+	{ IIC_TBUF, 78, 32, NTHW_FPGA_REG_TYPE_RW, 0, 1, iic_tbuf_fields },
+	{ IIC_TEN_ADR, 71, 3, NTHW_FPGA_REG_TYPE_RO, 0, 1, iic_ten_adr_fields },
+	{ IIC_THDDAT, 81, 32, NTHW_FPGA_REG_TYPE_RW, 0, 1, iic_thddat_fields },
+	{ IIC_THDSTA, 76, 32, NTHW_FPGA_REG_TYPE_RW, 0, 1, iic_thdsta_fields },
+	{ IIC_THIGH, 79, 32, NTHW_FPGA_REG_TYPE_RW, 0, 1, iic_thigh_fields },
+	{ IIC_TLOW, 80, 32, NTHW_FPGA_REG_TYPE_RW, 0, 1, iic_tlow_fields },
+	{ IIC_TSUDAT, 77, 32, NTHW_FPGA_REG_TYPE_RW, 0, 1, iic_tsudat_fields },
+	{ IIC_TSUSTA, 74, 32, NTHW_FPGA_REG_TYPE_RW, 0, 1, iic_tsusta_fields },
+	{ IIC_TSUSTO, 75, 32, NTHW_FPGA_REG_TYPE_RW, 0, 1, iic_tsusto_fields },
+	{ IIC_TX_FIFO, 66, 10, NTHW_FPGA_REG_TYPE_WO, 0, 3, iic_tx_fifo_fields },
+	{ IIC_TX_FIFO_OCY, 69, 4, NTHW_FPGA_REG_TYPE_RO, 0, 1, iic_tx_fifo_ocy_fields },
+};
+
+static nthw_fpga_field_init_s ins_rcp_ctrl_fields[] = {
+	{ INS_RCP_CTRL_ADR, 4, 0, 0x0000 },
+	{ INS_RCP_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s ins_rcp_data_fields[] = {
+	{ INS_RCP_DATA_DYN, 5, 0, 0x0000 },
+	{ INS_RCP_DATA_LEN, 8, 15, 0x0000 },
+	{ INS_RCP_DATA_OFS, 10, 5, 0x0000 },
+};
+
+static nthw_fpga_register_init_s ins_registers[] = {
+	{ INS_RCP_CTRL, 0, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, ins_rcp_ctrl_fields },
+	{ INS_RCP_DATA, 1, 23, NTHW_FPGA_REG_TYPE_WO, 0, 3, ins_rcp_data_fields },
+};
+
+static nthw_fpga_field_init_s km_cam_ctrl_fields[] = {
+	{ KM_CAM_CTRL_ADR, 13, 0, 0x0000 },
+	{ KM_CAM_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s km_cam_data_fields[] = {
+	{ KM_CAM_DATA_FT0, 4, 192, 0x0000 }, { KM_CAM_DATA_FT1, 4, 196, 0x0000 },
+	{ KM_CAM_DATA_FT2, 4, 200, 0x0000 }, { KM_CAM_DATA_FT3, 4, 204, 0x0000 },
+	{ KM_CAM_DATA_FT4, 4, 208, 0x0000 }, { KM_CAM_DATA_FT5, 4, 212, 0x0000 },
+	{ KM_CAM_DATA_W0, 32, 0, 0x0000 }, { KM_CAM_DATA_W1, 32, 32, 0x0000 },
+	{ KM_CAM_DATA_W2, 32, 64, 0x0000 }, { KM_CAM_DATA_W3, 32, 96, 0x0000 },
+	{ KM_CAM_DATA_W4, 32, 128, 0x0000 }, { KM_CAM_DATA_W5, 32, 160, 0x0000 },
+};
+
+static nthw_fpga_field_init_s km_rcp_ctrl_fields[] = {
+	{ KM_RCP_CTRL_ADR, 5, 0, 0x0000 },
+	{ KM_RCP_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s km_rcp_data_fields[] = {
+	{ KM_RCP_DATA_BANK_A, 12, 694, 0x0000 }, { KM_RCP_DATA_BANK_B, 12, 706, 0x0000 },
+	{ KM_RCP_DATA_DUAL, 1, 651, 0x0000 }, { KM_RCP_DATA_DW0_B_DYN, 5, 729, 0x0000 },
+	{ KM_RCP_DATA_DW0_B_OFS, 8, 734, 0x0000 }, { KM_RCP_DATA_DW10_DYN, 5, 55, 0x0000 },
+	{ KM_RCP_DATA_DW10_OFS, 8, 60, 0x0000 }, { KM_RCP_DATA_DW10_SEL_A, 2, 68, 0x0000 },
+	{ KM_RCP_DATA_DW10_SEL_B, 2, 70, 0x0000 }, { KM_RCP_DATA_DW2_B_DYN, 5, 742, 0x0000 },
+	{ KM_RCP_DATA_DW2_B_OFS, 8, 747, 0x0000 }, { KM_RCP_DATA_DW8_DYN, 5, 36, 0x0000 },
+	{ KM_RCP_DATA_DW8_OFS, 8, 41, 0x0000 }, { KM_RCP_DATA_DW8_SEL_A, 3, 49, 0x0000 },
+	{ KM_RCP_DATA_DW8_SEL_B, 3, 52, 0x0000 }, { KM_RCP_DATA_EL_A, 4, 653, 0x0000 },
+	{ KM_RCP_DATA_EL_B, 3, 657, 0x0000 }, { KM_RCP_DATA_FTM_A, 16, 662, 0x0000 },
+	{ KM_RCP_DATA_FTM_B, 16, 678, 0x0000 }, { KM_RCP_DATA_INFO_A, 1, 660, 0x0000 },
+	{ KM_RCP_DATA_INFO_B, 1, 661, 0x0000 }, { KM_RCP_DATA_KEYWAY_A, 1, 725, 0x0000 },
+	{ KM_RCP_DATA_KEYWAY_B, 1, 726, 0x0000 }, { KM_RCP_DATA_KL_A, 4, 718, 0x0000 },
+	{ KM_RCP_DATA_KL_B, 3, 722, 0x0000 }, { KM_RCP_DATA_MASK_A, 384, 75, 0x0000 },
+	{ KM_RCP_DATA_MASK_B, 192, 459, 0x0000 }, { KM_RCP_DATA_PAIRED, 1, 652, 0x0000 },
+	{ KM_RCP_DATA_QW0_DYN, 5, 0, 0x0000 }, { KM_RCP_DATA_QW0_OFS, 8, 5, 0x0000 },
+	{ KM_RCP_DATA_QW0_SEL_A, 3, 13, 0x0000 }, { KM_RCP_DATA_QW0_SEL_B, 3, 16, 0x0000 },
+	{ KM_RCP_DATA_QW4_DYN, 5, 19, 0x0000 }, { KM_RCP_DATA_QW4_OFS, 8, 24, 0x0000 },
+	{ KM_RCP_DATA_QW4_SEL_A, 2, 32, 0x0000 }, { KM_RCP_DATA_QW4_SEL_B, 2, 34, 0x0000 },
+	{ KM_RCP_DATA_SW4_B_DYN, 5, 755, 0x0000 }, { KM_RCP_DATA_SW4_B_OFS, 8, 760, 0x0000 },
+	{ KM_RCP_DATA_SW5_B_DYN, 5, 768, 0x0000 }, { KM_RCP_DATA_SW5_B_OFS, 8, 773, 0x0000 },
+	{ KM_RCP_DATA_SWX_CCH, 1, 72, 0x0000 }, { KM_RCP_DATA_SWX_SEL_A, 1, 73, 0x0000 },
+	{ KM_RCP_DATA_SWX_SEL_B, 1, 74, 0x0000 }, { KM_RCP_DATA_SYNERGY_MODE, 2, 727, 0x0000 },
+};
+
+static nthw_fpga_field_init_s km_status_fields[] = {
+	{ KM_STATUS_TCQ_RDY, 1, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s km_tcam_ctrl_fields[] = {
+	{ KM_TCAM_CTRL_ADR, 14, 0, 0x0000 },
+	{ KM_TCAM_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s km_tcam_data_fields[] = {
+	{ KM_TCAM_DATA_T, 72, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s km_tci_ctrl_fields[] = {
+	{ KM_TCI_CTRL_ADR, 10, 0, 0x0000 },
+	{ KM_TCI_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s km_tci_data_fields[] = {
+	{ KM_TCI_DATA_COLOR, 32, 0, 0x0000 },
+	{ KM_TCI_DATA_FT, 4, 32, 0x0000 },
+};
+
+static nthw_fpga_field_init_s km_tcq_ctrl_fields[] = {
+	{ KM_TCQ_CTRL_ADR, 7, 0, 0x0000 },
+	{ KM_TCQ_CTRL_CNT, 5, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s km_tcq_data_fields[] = {
+	{ KM_TCQ_DATA_BANK_MASK, 12, 0, 0x0000 },
+	{ KM_TCQ_DATA_QUAL, 3, 12, 0x0000 },
+};
+
+static nthw_fpga_register_init_s km_registers[] = {
+	{ KM_CAM_CTRL, 2, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, km_cam_ctrl_fields },
+	{ KM_CAM_DATA, 3, 216, NTHW_FPGA_REG_TYPE_WO, 0, 12, km_cam_data_fields },
+	{ KM_RCP_CTRL, 0, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, km_rcp_ctrl_fields },
+	{ KM_RCP_DATA, 1, 781, NTHW_FPGA_REG_TYPE_WO, 0, 44, km_rcp_data_fields },
+	{ KM_STATUS, 10, 1, NTHW_FPGA_REG_TYPE_RO, 0, 1, km_status_fields },
+	{ KM_TCAM_CTRL, 4, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, km_tcam_ctrl_fields },
+	{ KM_TCAM_DATA, 5, 72, NTHW_FPGA_REG_TYPE_WO, 0, 1, km_tcam_data_fields },
+	{ KM_TCI_CTRL, 6, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, km_tci_ctrl_fields },
+	{ KM_TCI_DATA, 7, 36, NTHW_FPGA_REG_TYPE_WO, 0, 2, km_tci_data_fields },
+	{ KM_TCQ_CTRL, 8, 21, NTHW_FPGA_REG_TYPE_WO, 0, 2, km_tcq_ctrl_fields },
+	{ KM_TCQ_DATA, 9, 15, NTHW_FPGA_REG_TYPE_WO, 0, 2, km_tcq_data_fields },
+};
+
+static nthw_fpga_field_init_s mac_pcs_bad_code_fields[] = {
+	{ MAC_PCS_BAD_CODE_CODE_ERR, 16, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_bip_err_fields[] = {
+	{ MAC_PCS_BIP_ERR_BIP_ERR, 640, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_block_lock_fields[] = {
+	{ MAC_PCS_BLOCK_LOCK_LOCK, 20, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_block_lock_chg_fields[] = {
+	{ MAC_PCS_BLOCK_LOCK_CHG_LOCK_CHG, 20, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_debounce_ctrl_fields[] = {
+	{ MAC_PCS_DEBOUNCE_CTRL_NT_DEBOUNCE_LATENCY, 8, 8, 10 },
+	{ MAC_PCS_DEBOUNCE_CTRL_NT_FORCE_LINK_DOWN, 1, 16, 0 },
+	{ MAC_PCS_DEBOUNCE_CTRL_NT_LINKUP_LATENCY, 8, 0, 10 },
+	{ MAC_PCS_DEBOUNCE_CTRL_NT_PORT_CTRL, 2, 17, 2 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_drp_ctrl_fields[] = {
+	{ MAC_PCS_DRP_CTRL_ADR, 10, 16, 0 }, { MAC_PCS_DRP_CTRL_DATA, 16, 0, 0 },
+	{ MAC_PCS_DRP_CTRL_DBG_BUSY, 1, 30, 0x0000 }, { MAC_PCS_DRP_CTRL_DONE, 1, 31, 0x0000 },
+	{ MAC_PCS_DRP_CTRL_MOD_ADR, 3, 26, 0 }, { MAC_PCS_DRP_CTRL_WREN, 1, 29, 0 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_fec_ctrl_fields[] = {
+	{ MAC_PCS_FEC_CTRL_RS_FEC_CTRL_IN, 5, 0, 0 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_fec_cw_cnt_fields[] = {
+	{ MAC_PCS_FEC_CW_CNT_CW_CNT, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_fec_err_cnt_0_fields[] = {
+	{ MAC_PCS_FEC_ERR_CNT_0_ERR_CNT, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_fec_err_cnt_1_fields[] = {
+	{ MAC_PCS_FEC_ERR_CNT_1_ERR_CNT, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_fec_err_cnt_2_fields[] = {
+	{ MAC_PCS_FEC_ERR_CNT_2_ERR_CNT, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_fec_err_cnt_3_fields[] = {
+	{ MAC_PCS_FEC_ERR_CNT_3_ERR_CNT, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_fec_lane_dly_0_fields[] = {
+	{ MAC_PCS_FEC_LANE_DLY_0_DLY, 14, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_fec_lane_dly_1_fields[] = {
+	{ MAC_PCS_FEC_LANE_DLY_1_DLY, 14, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_fec_lane_dly_2_fields[] = {
+	{ MAC_PCS_FEC_LANE_DLY_2_DLY, 14, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_fec_lane_dly_3_fields[] = {
+	{ MAC_PCS_FEC_LANE_DLY_3_DLY, 14, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_fec_lane_map_fields[] = {
+	{ MAC_PCS_FEC_LANE_MAP_MAPPING, 8, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_fec_stat_fields[] = {
+	{ MAC_PCS_FEC_STAT_AM_LOCK, 1, 10, 0x0000 },
+	{ MAC_PCS_FEC_STAT_AM_LOCK_0, 1, 3, 0x0000 },
+	{ MAC_PCS_FEC_STAT_AM_LOCK_1, 1, 4, 0x0000 },
+	{ MAC_PCS_FEC_STAT_AM_LOCK_2, 1, 5, 0x0000 },
+	{ MAC_PCS_FEC_STAT_AM_LOCK_3, 1, 6, 0x0000 },
+	{ MAC_PCS_FEC_STAT_BLOCK_LOCK, 1, 9, 0x0000 },
+	{ MAC_PCS_FEC_STAT_BYPASS, 1, 0, 0x0000 },
+	{ MAC_PCS_FEC_STAT_FEC_LANE_ALGN, 1, 7, 0x0000 },
+	{ MAC_PCS_FEC_STAT_HI_SER, 1, 2, 0x0000 },
+	{ MAC_PCS_FEC_STAT_PCS_LANE_ALGN, 1, 8, 0x0000 },
+	{ MAC_PCS_FEC_STAT_VALID, 1, 1, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_fec_ucw_cnt_fields[] = {
+	{ MAC_PCS_FEC_UCW_CNT_UCW_CNT, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_gty_ctl_rx_fields[] = {
+	{ MAC_PCS_GTY_CTL_RX_CDR_HOLD_0, 1, 24, 0 }, { MAC_PCS_GTY_CTL_RX_CDR_HOLD_1, 1, 25, 0 },
+	{ MAC_PCS_GTY_CTL_RX_CDR_HOLD_2, 1, 26, 0 }, { MAC_PCS_GTY_CTL_RX_CDR_HOLD_3, 1, 27, 0 },
+	{ MAC_PCS_GTY_CTL_RX_EQUA_RST_0, 1, 20, 0 }, { MAC_PCS_GTY_CTL_RX_EQUA_RST_1, 1, 21, 0 },
+	{ MAC_PCS_GTY_CTL_RX_EQUA_RST_2, 1, 22, 0 }, { MAC_PCS_GTY_CTL_RX_EQUA_RST_3, 1, 23, 0 },
+	{ MAC_PCS_GTY_CTL_RX_LPM_EN_0, 1, 16, 0 }, { MAC_PCS_GTY_CTL_RX_LPM_EN_1, 1, 17, 0 },
+	{ MAC_PCS_GTY_CTL_RX_LPM_EN_2, 1, 18, 0 }, { MAC_PCS_GTY_CTL_RX_LPM_EN_3, 1, 19, 0 },
+	{ MAC_PCS_GTY_CTL_RX_POLARITY_0, 1, 0, 0 }, { MAC_PCS_GTY_CTL_RX_POLARITY_1, 1, 1, 0 },
+	{ MAC_PCS_GTY_CTL_RX_POLARITY_2, 1, 2, 0 }, { MAC_PCS_GTY_CTL_RX_POLARITY_3, 1, 3, 0 },
+	{ MAC_PCS_GTY_CTL_RX_RATE_0, 3, 4, 0 }, { MAC_PCS_GTY_CTL_RX_RATE_1, 3, 7, 0 },
+	{ MAC_PCS_GTY_CTL_RX_RATE_2, 3, 10, 0 }, { MAC_PCS_GTY_CTL_RX_RATE_3, 3, 13, 0 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_gty_ctl_tx_fields[] = {
+	{ MAC_PCS_GTY_CTL_TX_INHIBIT_0, 1, 4, 0 }, { MAC_PCS_GTY_CTL_TX_INHIBIT_1, 1, 5, 0 },
+	{ MAC_PCS_GTY_CTL_TX_INHIBIT_2, 1, 6, 0 }, { MAC_PCS_GTY_CTL_TX_INHIBIT_3, 1, 7, 0 },
+	{ MAC_PCS_GTY_CTL_TX_POLARITY_0, 1, 0, 0 }, { MAC_PCS_GTY_CTL_TX_POLARITY_1, 1, 1, 0 },
+	{ MAC_PCS_GTY_CTL_TX_POLARITY_2, 1, 2, 0 }, { MAC_PCS_GTY_CTL_TX_POLARITY_3, 1, 3, 0 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_gty_diff_ctl_fields[] = {
+	{ MAC_PCS_GTY_DIFF_CTL_TX_DIFF_CTL_0, 5, 0, 24 },
+	{ MAC_PCS_GTY_DIFF_CTL_TX_DIFF_CTL_1, 5, 5, 24 },
+	{ MAC_PCS_GTY_DIFF_CTL_TX_DIFF_CTL_2, 5, 10, 24 },
+	{ MAC_PCS_GTY_DIFF_CTL_TX_DIFF_CTL_3, 5, 15, 24 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_gty_loop_fields[] = {
+	{ MAC_PCS_GTY_LOOP_GT_LOOP_0, 3, 0, 0 },
+	{ MAC_PCS_GTY_LOOP_GT_LOOP_1, 3, 3, 0 },
+	{ MAC_PCS_GTY_LOOP_GT_LOOP_2, 3, 6, 0 },
+	{ MAC_PCS_GTY_LOOP_GT_LOOP_3, 3, 9, 0 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_gty_post_cursor_fields[] = {
+	{ MAC_PCS_GTY_POST_CURSOR_TX_POST_CSR_0, 5, 0, 20 },
+	{ MAC_PCS_GTY_POST_CURSOR_TX_POST_CSR_1, 5, 5, 20 },
+	{ MAC_PCS_GTY_POST_CURSOR_TX_POST_CSR_2, 5, 10, 20 },
+	{ MAC_PCS_GTY_POST_CURSOR_TX_POST_CSR_3, 5, 15, 20 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_gty_prbs_sel_fields[] = {
+	{ MAC_PCS_GTY_PRBS_SEL_RX_PRBS_SEL_0, 4, 16, 0 },
+	{ MAC_PCS_GTY_PRBS_SEL_RX_PRBS_SEL_1, 4, 20, 0 },
+	{ MAC_PCS_GTY_PRBS_SEL_RX_PRBS_SEL_2, 4, 24, 0 },
+	{ MAC_PCS_GTY_PRBS_SEL_RX_PRBS_SEL_3, 4, 28, 0 },
+	{ MAC_PCS_GTY_PRBS_SEL_TX_PRBS_SEL_0, 4, 0, 0 },
+	{ MAC_PCS_GTY_PRBS_SEL_TX_PRBS_SEL_1, 4, 4, 0 },
+	{ MAC_PCS_GTY_PRBS_SEL_TX_PRBS_SEL_2, 4, 8, 0 },
+	{ MAC_PCS_GTY_PRBS_SEL_TX_PRBS_SEL_3, 4, 12, 0 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_gty_pre_cursor_fields[] = {
+	{ MAC_PCS_GTY_PRE_CURSOR_TX_PRE_CSR_0, 5, 0, 0 },
+	{ MAC_PCS_GTY_PRE_CURSOR_TX_PRE_CSR_1, 5, 5, 0 },
+	{ MAC_PCS_GTY_PRE_CURSOR_TX_PRE_CSR_2, 5, 10, 0 },
+	{ MAC_PCS_GTY_PRE_CURSOR_TX_PRE_CSR_3, 5, 15, 0 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_gty_rx_buf_stat_fields[] = {
+	{ MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_0, 3, 0, 0x0000 },
+	{ MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_1, 3, 3, 0x0000 },
+	{ MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_2, 3, 6, 0x0000 },
+	{ MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_3, 3, 9, 0x0000 },
+	{ MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_CHANGED_0, 3, 12, 0x0000 },
+	{ MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_CHANGED_1, 3, 15, 0x0000 },
+	{ MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_CHANGED_2, 3, 18, 0x0000 },
+	{ MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_CHANGED_3, 3, 21, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_gty_scan_ctl_fields[] = {
+	{ MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_RST_0, 1, 0, 0 },
+	{ MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_RST_1, 1, 1, 0 },
+	{ MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_RST_2, 1, 2, 0 },
+	{ MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_RST_3, 1, 3, 0 },
+	{ MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_TRG_0, 1, 4, 0 },
+	{ MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_TRG_1, 1, 5, 0 },
+	{ MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_TRG_2, 1, 6, 0 },
+	{ MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_TRG_3, 1, 7, 0 },
+	{ MAC_PCS_GTY_SCAN_CTL_PRBS_ERR_INS_0, 1, 12, 0 },
+	{ MAC_PCS_GTY_SCAN_CTL_PRBS_ERR_INS_1, 1, 13, 0 },
+	{ MAC_PCS_GTY_SCAN_CTL_PRBS_ERR_INS_2, 1, 14, 0 },
+	{ MAC_PCS_GTY_SCAN_CTL_PRBS_ERR_INS_3, 1, 15, 0 },
+	{ MAC_PCS_GTY_SCAN_CTL_PRBS_RST_0, 1, 8, 0 },
+	{ MAC_PCS_GTY_SCAN_CTL_PRBS_RST_1, 1, 9, 0 },
+	{ MAC_PCS_GTY_SCAN_CTL_PRBS_RST_2, 1, 10, 0 },
+	{ MAC_PCS_GTY_SCAN_CTL_PRBS_RST_3, 1, 11, 0 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_gty_scan_stat_fields[] = {
+	{ MAC_PCS_GTY_SCAN_STAT_EYE_SCAN_ERR_0, 1, 0, 0x0000 },
+	{ MAC_PCS_GTY_SCAN_STAT_EYE_SCAN_ERR_1, 1, 1, 0x0000 },
+	{ MAC_PCS_GTY_SCAN_STAT_EYE_SCAN_ERR_2, 1, 2, 0x0000 },
+	{ MAC_PCS_GTY_SCAN_STAT_EYE_SCAN_ERR_3, 1, 3, 0x0000 },
+	{ MAC_PCS_GTY_SCAN_STAT_PRBS_ERR_0, 1, 4, 0x0000 },
+	{ MAC_PCS_GTY_SCAN_STAT_PRBS_ERR_1, 1, 5, 0x0000 },
+	{ MAC_PCS_GTY_SCAN_STAT_PRBS_ERR_2, 1, 6, 0x0000 },
+	{ MAC_PCS_GTY_SCAN_STAT_PRBS_ERR_3, 1, 7, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_gty_stat_fields[] = {
+	{ MAC_PCS_GTY_STAT_RX_RST_DONE_0, 1, 4, 0x0000 },
+	{ MAC_PCS_GTY_STAT_RX_RST_DONE_1, 1, 5, 0x0000 },
+	{ MAC_PCS_GTY_STAT_RX_RST_DONE_2, 1, 6, 0x0000 },
+	{ MAC_PCS_GTY_STAT_RX_RST_DONE_3, 1, 7, 0x0000 },
+	{ MAC_PCS_GTY_STAT_TX_BUF_STAT_0, 2, 8, 0x0000 },
+	{ MAC_PCS_GTY_STAT_TX_BUF_STAT_1, 2, 10, 0x0000 },
+	{ MAC_PCS_GTY_STAT_TX_BUF_STAT_2, 2, 12, 0x0000 },
+	{ MAC_PCS_GTY_STAT_TX_BUF_STAT_3, 2, 14, 0x0000 },
+	{ MAC_PCS_GTY_STAT_TX_RST_DONE_0, 1, 0, 0x0000 },
+	{ MAC_PCS_GTY_STAT_TX_RST_DONE_1, 1, 1, 0x0000 },
+	{ MAC_PCS_GTY_STAT_TX_RST_DONE_2, 1, 2, 0x0000 },
+	{ MAC_PCS_GTY_STAT_TX_RST_DONE_3, 1, 3, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_link_summary_fields[] = {
+	{ MAC_PCS_LINK_SUMMARY_ABS, 1, 0, 0x0000 },
+	{ MAC_PCS_LINK_SUMMARY_LH_ABS, 1, 2, 0x0000 },
+	{ MAC_PCS_LINK_SUMMARY_LH_LOCAL_FAULT, 1, 13, 0 },
+	{ MAC_PCS_LINK_SUMMARY_LH_REMOTE_FAULT, 1, 14, 0 },
+	{ MAC_PCS_LINK_SUMMARY_LINK_DOWN_CNT, 8, 4, 0 },
+	{ MAC_PCS_LINK_SUMMARY_LL_PHY_LINK_STATE, 1, 3, 0x0000 },
+	{ MAC_PCS_LINK_SUMMARY_LOCAL_FAULT, 1, 17, 0x0000 },
+	{ MAC_PCS_LINK_SUMMARY_NIM_INTERR, 1, 12, 0x0000 },
+	{ MAC_PCS_LINK_SUMMARY_NT_PHY_LINK_STATE, 1, 1, 0x0000 },
+	{ MAC_PCS_LINK_SUMMARY_REMOTE_FAULT, 1, 18, 0x0000 },
+	{ MAC_PCS_LINK_SUMMARY_RESERVED, 2, 15, 0 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_mac_pcs_config_fields[] = {
+	{ MAC_PCS_MAC_PCS_CONFIG_RX_CORE_RST, 1, 3, 0 },
+	{ MAC_PCS_MAC_PCS_CONFIG_RX_ENABLE, 1, 5, 0 },
+	{ MAC_PCS_MAC_PCS_CONFIG_RX_FORCE_RESYNC, 1, 6, 0 },
+	{ MAC_PCS_MAC_PCS_CONFIG_RX_PATH_RST, 1, 1, 0 },
+	{ MAC_PCS_MAC_PCS_CONFIG_RX_TEST_PATTERN, 1, 7, 0 },
+	{ MAC_PCS_MAC_PCS_CONFIG_TX_CORE_RST, 1, 2, 0 },
+	{ MAC_PCS_MAC_PCS_CONFIG_TX_ENABLE, 1, 8, 1 },
+	{ MAC_PCS_MAC_PCS_CONFIG_TX_FCS_REMOVE, 1, 4, 1 },
+	{ MAC_PCS_MAC_PCS_CONFIG_TX_PATH_RST, 1, 0, 0 },
+	{ MAC_PCS_MAC_PCS_CONFIG_TX_SEND_IDLE, 1, 9, 0 },
+	{ MAC_PCS_MAC_PCS_CONFIG_TX_SEND_RFI, 1, 10, 0 },
+	{ MAC_PCS_MAC_PCS_CONFIG_TX_TEST_PATTERN, 1, 11, 0 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_max_pkt_len_fields[] = {
+	{ MAC_PCS_MAX_PKT_LEN_MAX_LEN, 14, 0, 10000 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_phymac_misc_fields[] = {
+	{ MAC_PCS_PHYMAC_MISC_TS_EOP, 1, 3, 1 },
+	{ MAC_PCS_PHYMAC_MISC_TX_MUX_STATE, 4, 4, 0x0000 },
+	{ MAC_PCS_PHYMAC_MISC_TX_SEL_HOST, 1, 0, 1 },
+	{ MAC_PCS_PHYMAC_MISC_TX_SEL_RX_LOOP, 1, 2, 0 },
+	{ MAC_PCS_PHYMAC_MISC_TX_SEL_TFG, 1, 1, 0 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_phy_stat_fields[] = {
+	{ MAC_PCS_PHY_STAT_ALARM, 1, 2, 0x0000 },
+	{ MAC_PCS_PHY_STAT_MOD_PRS, 1, 1, 0x0000 },
+	{ MAC_PCS_PHY_STAT_RX_LOS, 1, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_stat_pcs_rx_fields[] = {
+	{ MAC_PCS_STAT_PCS_RX_ALIGNED, 1, 1, 0x0000 },
+	{ MAC_PCS_STAT_PCS_RX_ALIGNED_ERR, 1, 2, 0x0000 },
+	{ MAC_PCS_STAT_PCS_RX_GOT_SIGNAL_OS, 1, 9, 0x0000 },
+	{ MAC_PCS_STAT_PCS_RX_HI_BER, 1, 8, 0x0000 },
+	{ MAC_PCS_STAT_PCS_RX_INTERNAL_LOCAL_FAULT, 1, 4, 0x0000 },
+	{ MAC_PCS_STAT_PCS_RX_LOCAL_FAULT, 1, 6, 0x0000 },
+	{ MAC_PCS_STAT_PCS_RX_MISALIGNED, 1, 3, 0x0000 },
+	{ MAC_PCS_STAT_PCS_RX_RECEIVED_LOCAL_FAULT, 1, 5, 0x0000 },
+	{ MAC_PCS_STAT_PCS_RX_REMOTE_FAULT, 1, 7, 0x0000 },
+	{ MAC_PCS_STAT_PCS_RX_STATUS, 1, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_stat_pcs_rx_latch_fields[] = {
+	{ MAC_PCS_STAT_PCS_RX_LATCH_ALIGNED, 1, 1, 0x0000 },
+	{ MAC_PCS_STAT_PCS_RX_LATCH_ALIGNED_ERR, 1, 2, 0x0000 },
+	{ MAC_PCS_STAT_PCS_RX_LATCH_GOT_SIGNAL_OS, 1, 9, 0x0000 },
+	{ MAC_PCS_STAT_PCS_RX_LATCH_HI_BER, 1, 8, 0x0000 },
+	{ MAC_PCS_STAT_PCS_RX_LATCH_INTERNAL_LOCAL_FAULT, 1, 4, 0x0000 },
+	{ MAC_PCS_STAT_PCS_RX_LATCH_LOCAL_FAULT, 1, 6, 0x0000 },
+	{ MAC_PCS_STAT_PCS_RX_LATCH_MISALIGNED, 1, 3, 0x0000 },
+	{ MAC_PCS_STAT_PCS_RX_LATCH_RECEIVED_LOCAL_FAULT, 1, 5, 0x0000 },
+	{ MAC_PCS_STAT_PCS_RX_LATCH_REMOTE_FAULT, 1, 7, 0x0000 },
+	{ MAC_PCS_STAT_PCS_RX_LATCH_STATUS, 1, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_stat_pcs_tx_fields[] = {
+	{ MAC_PCS_STAT_PCS_TX_LOCAL_FAULT, 1, 0, 0x0000 },
+	{ MAC_PCS_STAT_PCS_TX_LOCAL_FAULT_CHANGED, 1, 5, 0x0000 },
+	{ MAC_PCS_STAT_PCS_TX_PTP_FIFO_READ_ERROR, 1, 4, 0x0000 },
+	{ MAC_PCS_STAT_PCS_TX_PTP_FIFO_READ_ERROR_CHANGED, 1, 9, 0x0000 },
+	{ MAC_PCS_STAT_PCS_TX_PTP_FIFO_WRITE_ERROR, 1, 3, 0x0000 },
+	{ MAC_PCS_STAT_PCS_TX_PTP_FIFO_WRITE_ERROR_CHANGED, 1, 8, 0x0000 },
+	{ MAC_PCS_STAT_PCS_TX_TX_OVFOUT, 1, 2, 0x0000 },
+	{ MAC_PCS_STAT_PCS_TX_TX_OVFOUT_CHANGED, 1, 7, 0x0000 },
+	{ MAC_PCS_STAT_PCS_TX_TX_UNFOUT, 1, 1, 0x0000 },
+	{ MAC_PCS_STAT_PCS_TX_TX_UNFOUT_CHANGED, 1, 6, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_synced_fields[] = {
+	{ MAC_PCS_SYNCED_SYNC, 20, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_synced_err_fields[] = {
+	{ MAC_PCS_SYNCED_ERR_SYNC_ERROR, 20, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_test_err_fields[] = {
+	{ MAC_PCS_TEST_ERR_CODE_ERR, 16, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_timestamp_comp_fields[] = {
+	{ MAC_PCS_TIMESTAMP_COMP_RX_DLY, 16, 0, 1451 },
+	{ MAC_PCS_TIMESTAMP_COMP_TX_DLY, 16, 16, 1440 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_vl_demuxed_fields[] = {
+	{ MAC_PCS_VL_DEMUXED_LOCK, 20, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_vl_demuxed_chg_fields[] = {
+	{ MAC_PCS_VL_DEMUXED_CHG_LOCK_CHG, 20, 0, 0x0000 },
+};
+
+static nthw_fpga_register_init_s mac_pcs_registers[] = {
+	{ MAC_PCS_BAD_CODE, 26, 16, NTHW_FPGA_REG_TYPE_RO, 0, 1, mac_pcs_bad_code_fields },
+	{ MAC_PCS_BIP_ERR, 31, 640, NTHW_FPGA_REG_TYPE_RO, 0, 1, mac_pcs_bip_err_fields },
+	{ MAC_PCS_BLOCK_LOCK, 27, 20, NTHW_FPGA_REG_TYPE_RO, 0, 1, mac_pcs_block_lock_fields },
+	{
+		MAC_PCS_BLOCK_LOCK_CHG, 28, 20, NTHW_FPGA_REG_TYPE_RO, 0, 1,
+		mac_pcs_block_lock_chg_fields
+	},
+	{
+		MAC_PCS_DEBOUNCE_CTRL, 1, 19, NTHW_FPGA_REG_TYPE_RW, 264714, 4,
+		mac_pcs_debounce_ctrl_fields
+	},
+	{ MAC_PCS_DRP_CTRL, 43, 32, NTHW_FPGA_REG_TYPE_MIXED, 0, 6, mac_pcs_drp_ctrl_fields },
+	{ MAC_PCS_FEC_CTRL, 2, 5, NTHW_FPGA_REG_TYPE_RW, 0, 1, mac_pcs_fec_ctrl_fields },
+	{ MAC_PCS_FEC_CW_CNT, 9, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, mac_pcs_fec_cw_cnt_fields },
+	{
+		MAC_PCS_FEC_ERR_CNT_0, 11, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1,
+		mac_pcs_fec_err_cnt_0_fields
+	},
+	{
+		MAC_PCS_FEC_ERR_CNT_1, 12, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1,
+		mac_pcs_fec_err_cnt_1_fields
+	},
+	{
+		MAC_PCS_FEC_ERR_CNT_2, 13, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1,
+		mac_pcs_fec_err_cnt_2_fields
+	},
+	{
+		MAC_PCS_FEC_ERR_CNT_3, 14, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1,
+		mac_pcs_fec_err_cnt_3_fields
+	},
+	{
+		MAC_PCS_FEC_LANE_DLY_0, 5, 14, NTHW_FPGA_REG_TYPE_RO, 0, 1,
+		mac_pcs_fec_lane_dly_0_fields
+	},
+	{
+		MAC_PCS_FEC_LANE_DLY_1, 6, 14, NTHW_FPGA_REG_TYPE_RO, 0, 1,
+		mac_pcs_fec_lane_dly_1_fields
+	},
+	{
+		MAC_PCS_FEC_LANE_DLY_2, 7, 14, NTHW_FPGA_REG_TYPE_RO, 0, 1,
+		mac_pcs_fec_lane_dly_2_fields
+	},
+	{
+		MAC_PCS_FEC_LANE_DLY_3, 8, 14, NTHW_FPGA_REG_TYPE_RO, 0, 1,
+		mac_pcs_fec_lane_dly_3_fields
+	},
+	{ MAC_PCS_FEC_LANE_MAP, 4, 8, NTHW_FPGA_REG_TYPE_RO, 0, 1, mac_pcs_fec_lane_map_fields },
+	{ MAC_PCS_FEC_STAT, 3, 11, NTHW_FPGA_REG_TYPE_RO, 0, 11, mac_pcs_fec_stat_fields },
+	{ MAC_PCS_FEC_UCW_CNT, 10, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, mac_pcs_fec_ucw_cnt_fields },
+	{ MAC_PCS_GTY_CTL_RX, 38, 28, NTHW_FPGA_REG_TYPE_RW, 0, 20, mac_pcs_gty_ctl_rx_fields },
+	{ MAC_PCS_GTY_CTL_TX, 39, 8, NTHW_FPGA_REG_TYPE_RW, 0, 8, mac_pcs_gty_ctl_tx_fields },
+	{
+		MAC_PCS_GTY_DIFF_CTL, 35, 20, NTHW_FPGA_REG_TYPE_RW, 811800, 4,
+		mac_pcs_gty_diff_ctl_fields
+	},
+	{ MAC_PCS_GTY_LOOP, 20, 12, NTHW_FPGA_REG_TYPE_RW, 0, 4, mac_pcs_gty_loop_fields },
+	{
+		MAC_PCS_GTY_POST_CURSOR, 36, 20, NTHW_FPGA_REG_TYPE_RW, 676500, 4,
+		mac_pcs_gty_post_cursor_fields
+	},
+	{ MAC_PCS_GTY_PRBS_SEL, 40, 32, NTHW_FPGA_REG_TYPE_RW, 0, 8, mac_pcs_gty_prbs_sel_fields },
+	{
+		MAC_PCS_GTY_PRE_CURSOR, 37, 20, NTHW_FPGA_REG_TYPE_RW, 0, 4,
+		mac_pcs_gty_pre_cursor_fields
+	},
+	{
+		MAC_PCS_GTY_RX_BUF_STAT, 34, 24, NTHW_FPGA_REG_TYPE_RO, 0, 8,
+		mac_pcs_gty_rx_buf_stat_fields
+	},
+	{
+		MAC_PCS_GTY_SCAN_CTL, 41, 16, NTHW_FPGA_REG_TYPE_RW, 0, 16,
+		mac_pcs_gty_scan_ctl_fields
+	},
+	{
+		MAC_PCS_GTY_SCAN_STAT, 42, 8, NTHW_FPGA_REG_TYPE_RO, 0, 8,
+		mac_pcs_gty_scan_stat_fields
+	},
+	{ MAC_PCS_GTY_STAT, 33, 16, NTHW_FPGA_REG_TYPE_RO, 0, 12, mac_pcs_gty_stat_fields },
+	{ MAC_PCS_LINK_SUMMARY, 0, 19, NTHW_FPGA_REG_TYPE_RO, 0, 11, mac_pcs_link_summary_fields },
+	{
+		MAC_PCS_MAC_PCS_CONFIG, 19, 12, NTHW_FPGA_REG_TYPE_RW, 272, 12,
+		mac_pcs_mac_pcs_config_fields
+	},
+	{
+		MAC_PCS_MAX_PKT_LEN, 17, 14, NTHW_FPGA_REG_TYPE_RW, 10000, 1,
+		mac_pcs_max_pkt_len_fields
+	},
+	{ MAC_PCS_PHYMAC_MISC, 16, 8, NTHW_FPGA_REG_TYPE_MIXED, 9, 5, mac_pcs_phymac_misc_fields },
+	{ MAC_PCS_PHY_STAT, 15, 3, NTHW_FPGA_REG_TYPE_RO, 0, 3, mac_pcs_phy_stat_fields },
+	{ MAC_PCS_STAT_PCS_RX, 21, 10, NTHW_FPGA_REG_TYPE_RO, 0, 10, mac_pcs_stat_pcs_rx_fields },
+	{
+		MAC_PCS_STAT_PCS_RX_LATCH, 22, 10, NTHW_FPGA_REG_TYPE_RO, 0, 10,
+		mac_pcs_stat_pcs_rx_latch_fields
+	},
+	{ MAC_PCS_STAT_PCS_TX, 23, 10, NTHW_FPGA_REG_TYPE_RO, 0, 10, mac_pcs_stat_pcs_tx_fields },
+	{ MAC_PCS_SYNCED, 24, 20, NTHW_FPGA_REG_TYPE_RO, 0, 1, mac_pcs_synced_fields },
+	{ MAC_PCS_SYNCED_ERR, 25, 20, NTHW_FPGA_REG_TYPE_RO, 0, 1, mac_pcs_synced_err_fields },
+	{ MAC_PCS_TEST_ERR, 32, 16, NTHW_FPGA_REG_TYPE_RO, 0, 1, mac_pcs_test_err_fields },
+	{
+		MAC_PCS_TIMESTAMP_COMP, 18, 32, NTHW_FPGA_REG_TYPE_RW, 94373291, 2,
+		mac_pcs_timestamp_comp_fields
+	},
+	{ MAC_PCS_VL_DEMUXED, 29, 20, NTHW_FPGA_REG_TYPE_RO, 0, 1, mac_pcs_vl_demuxed_fields },
+	{
+		MAC_PCS_VL_DEMUXED_CHG, 30, 20, NTHW_FPGA_REG_TYPE_RO, 0, 1,
+		mac_pcs_vl_demuxed_chg_fields
+	},
+};
+
+static nthw_fpga_field_init_s mac_rx_bad_fcs_fields[] = {
+	{ MAC_RX_BAD_FCS_COUNT, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_rx_fragment_fields[] = {
+	{ MAC_RX_FRAGMENT_COUNT, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_rx_packet_bad_fcs_fields[] = {
+	{ MAC_RX_PACKET_BAD_FCS_COUNT, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_rx_packet_small_fields[] = {
+	{ MAC_RX_PACKET_SMALL_COUNT, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_rx_total_bytes_fields[] = {
+	{ MAC_RX_TOTAL_BYTES_COUNT, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_rx_total_good_bytes_fields[] = {
+	{ MAC_RX_TOTAL_GOOD_BYTES_COUNT, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_rx_total_good_packets_fields[] = {
+	{ MAC_RX_TOTAL_GOOD_PACKETS_COUNT, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_rx_total_packets_fields[] = {
+	{ MAC_RX_TOTAL_PACKETS_COUNT, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_rx_undersize_fields[] = {
+	{ MAC_RX_UNDERSIZE_COUNT, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_register_init_s mac_rx_registers[] = {
+	{ MAC_RX_BAD_FCS, 0, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, mac_rx_bad_fcs_fields },
+	{ MAC_RX_FRAGMENT, 6, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, mac_rx_fragment_fields },
+	{
+		MAC_RX_PACKET_BAD_FCS, 7, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1,
+		mac_rx_packet_bad_fcs_fields
+	},
+	{ MAC_RX_PACKET_SMALL, 3, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, mac_rx_packet_small_fields },
+	{ MAC_RX_TOTAL_BYTES, 4, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, mac_rx_total_bytes_fields },
+	{
+		MAC_RX_TOTAL_GOOD_BYTES, 5, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1,
+		mac_rx_total_good_bytes_fields
+	},
+	{
+		MAC_RX_TOTAL_GOOD_PACKETS, 2, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1,
+		mac_rx_total_good_packets_fields
+	},
+	{ MAC_RX_TOTAL_PACKETS, 1, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, mac_rx_total_packets_fields },
+	{ MAC_RX_UNDERSIZE, 8, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, mac_rx_undersize_fields },
+};
+
+static nthw_fpga_field_init_s mac_tx_packet_small_fields[] = {
+	{ MAC_TX_PACKET_SMALL_COUNT, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_tx_total_bytes_fields[] = {
+	{ MAC_TX_TOTAL_BYTES_COUNT, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_tx_total_good_bytes_fields[] = {
+	{ MAC_TX_TOTAL_GOOD_BYTES_COUNT, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_tx_total_good_packets_fields[] = {
+	{ MAC_TX_TOTAL_GOOD_PACKETS_COUNT, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_tx_total_packets_fields[] = {
+	{ MAC_TX_TOTAL_PACKETS_COUNT, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_register_init_s mac_tx_registers[] = {
+	{ MAC_TX_PACKET_SMALL, 2, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, mac_tx_packet_small_fields },
+	{ MAC_TX_TOTAL_BYTES, 3, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, mac_tx_total_bytes_fields },
+	{
+		MAC_TX_TOTAL_GOOD_BYTES, 4, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1,
+		mac_tx_total_good_bytes_fields
+	},
+	{
+		MAC_TX_TOTAL_GOOD_PACKETS, 1, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1,
+		mac_tx_total_good_packets_fields
+	},
+	{ MAC_TX_TOTAL_PACKETS, 0, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, mac_tx_total_packets_fields },
+};
+
+static nthw_fpga_field_init_s pci_rd_tg_tg_ctrl_fields[] = {
+	{ PCI_RD_TG_TG_CTRL_TG_RD_RDY, 1, 0, 0 },
+};
+
+static nthw_fpga_field_init_s pci_rd_tg_tg_rdaddr_fields[] = {
+	{ PCI_RD_TG_TG_RDADDR_RAM_ADDR, 9, 0, 0 },
+};
+
+static nthw_fpga_field_init_s pci_rd_tg_tg_rddata0_fields[] = {
+	{ PCI_RD_TG_TG_RDDATA0_PHYS_ADDR_LOW, 32, 0, 0 },
+};
+
+static nthw_fpga_field_init_s pci_rd_tg_tg_rddata1_fields[] = {
+	{ PCI_RD_TG_TG_RDDATA1_PHYS_ADDR_HIGH, 32, 0, 0 },
+};
+
+static nthw_fpga_field_init_s pci_rd_tg_tg_rddata2_fields[] = {
+	{ PCI_RD_TG_TG_RDDATA2_REQ_HID, 6, 22, 0 },
+	{ PCI_RD_TG_TG_RDDATA2_REQ_SIZE, 22, 0, 0 },
+	{ PCI_RD_TG_TG_RDDATA2_WAIT, 1, 30, 0 },
+	{ PCI_RD_TG_TG_RDDATA2_WRAP, 1, 31, 0 },
+};
+
+static nthw_fpga_field_init_s pci_rd_tg_tg_rd_run_fields[] = {
+	{ PCI_RD_TG_TG_RD_RUN_RD_ITERATION, 16, 0, 0 },
+};
+
+static nthw_fpga_register_init_s pci_rd_tg_registers[] = {
+	{ PCI_RD_TG_TG_CTRL, 5, 1, NTHW_FPGA_REG_TYPE_RO, 0, 1, pci_rd_tg_tg_ctrl_fields },
+	{ PCI_RD_TG_TG_RDADDR, 3, 9, NTHW_FPGA_REG_TYPE_WO, 0, 1, pci_rd_tg_tg_rdaddr_fields },
+	{ PCI_RD_TG_TG_RDDATA0, 0, 32, NTHW_FPGA_REG_TYPE_WO, 0, 1, pci_rd_tg_tg_rddata0_fields },
+	{ PCI_RD_TG_TG_RDDATA1, 1, 32, NTHW_FPGA_REG_TYPE_WO, 0, 1, pci_rd_tg_tg_rddata1_fields },
+	{ PCI_RD_TG_TG_RDDATA2, 2, 32, NTHW_FPGA_REG_TYPE_WO, 0, 4, pci_rd_tg_tg_rddata2_fields },
+	{ PCI_RD_TG_TG_RD_RUN, 4, 16, NTHW_FPGA_REG_TYPE_WO, 0, 1, pci_rd_tg_tg_rd_run_fields },
+};
+
+static nthw_fpga_field_init_s pci_ta_control_fields[] = {
+	{ PCI_TA_CONTROL_ENABLE, 1, 0, 0 },
+};
+
+static nthw_fpga_field_init_s pci_ta_length_error_fields[] = {
+	{ PCI_TA_LENGTH_ERROR_AMOUNT, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s pci_ta_packet_bad_fields[] = {
+	{ PCI_TA_PACKET_BAD_AMOUNT, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s pci_ta_packet_good_fields[] = {
+	{ PCI_TA_PACKET_GOOD_AMOUNT, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s pci_ta_payload_error_fields[] = {
+	{ PCI_TA_PAYLOAD_ERROR_AMOUNT, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_register_init_s pci_ta_registers[] = {
+	{ PCI_TA_CONTROL, 0, 1, NTHW_FPGA_REG_TYPE_WO, 0, 1, pci_ta_control_fields },
+	{ PCI_TA_LENGTH_ERROR, 3, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, pci_ta_length_error_fields },
+	{ PCI_TA_PACKET_BAD, 2, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, pci_ta_packet_bad_fields },
+	{ PCI_TA_PACKET_GOOD, 1, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, pci_ta_packet_good_fields },
+	{ PCI_TA_PAYLOAD_ERROR, 4, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, pci_ta_payload_error_fields },
+};
+
+static nthw_fpga_field_init_s pci_wr_tg_tg_ctrl_fields[] = {
+	{ PCI_WR_TG_TG_CTRL_TG_WR_RDY, 1, 0, 0 },
+};
+
+static nthw_fpga_field_init_s pci_wr_tg_tg_seq_fields[] = {
+	{ PCI_WR_TG_TG_SEQ_SEQUENCE, 16, 0, 0 },
+};
+
+static nthw_fpga_field_init_s pci_wr_tg_tg_wraddr_fields[] = {
+	{ PCI_WR_TG_TG_WRADDR_RAM_ADDR, 9, 0, 0 },
+};
+
+static nthw_fpga_field_init_s pci_wr_tg_tg_wrdata0_fields[] = {
+	{ PCI_WR_TG_TG_WRDATA0_PHYS_ADDR_LOW, 32, 0, 0 },
+};
+
+static nthw_fpga_field_init_s pci_wr_tg_tg_wrdata1_fields[] = {
+	{ PCI_WR_TG_TG_WRDATA1_PHYS_ADDR_HIGH, 32, 0, 0 },
+};
+
+static nthw_fpga_field_init_s pci_wr_tg_tg_wrdata2_fields[] = {
+	{ PCI_WR_TG_TG_WRDATA2_INC_MODE, 1, 29, 0 }, { PCI_WR_TG_TG_WRDATA2_REQ_HID, 6, 22, 0 },
+	{ PCI_WR_TG_TG_WRDATA2_REQ_SIZE, 22, 0, 0 }, { PCI_WR_TG_TG_WRDATA2_WAIT, 1, 30, 0 },
+	{ PCI_WR_TG_TG_WRDATA2_WRAP, 1, 31, 0 },
+};
+
+static nthw_fpga_field_init_s pci_wr_tg_tg_wr_run_fields[] = {
+	{ PCI_WR_TG_TG_WR_RUN_WR_ITERATION, 16, 0, 0 },
+};
+
+static nthw_fpga_register_init_s pci_wr_tg_registers[] = {
+	{ PCI_WR_TG_TG_CTRL, 5, 1, NTHW_FPGA_REG_TYPE_RO, 0, 1, pci_wr_tg_tg_ctrl_fields },
+	{ PCI_WR_TG_TG_SEQ, 6, 16, NTHW_FPGA_REG_TYPE_RW, 0, 1, pci_wr_tg_tg_seq_fields },
+	{ PCI_WR_TG_TG_WRADDR, 3, 9, NTHW_FPGA_REG_TYPE_WO, 0, 1, pci_wr_tg_tg_wraddr_fields },
+	{ PCI_WR_TG_TG_WRDATA0, 0, 32, NTHW_FPGA_REG_TYPE_WO, 0, 1, pci_wr_tg_tg_wrdata0_fields },
+	{ PCI_WR_TG_TG_WRDATA1, 1, 32, NTHW_FPGA_REG_TYPE_WO, 0, 1, pci_wr_tg_tg_wrdata1_fields },
+	{ PCI_WR_TG_TG_WRDATA2, 2, 32, NTHW_FPGA_REG_TYPE_WO, 0, 5, pci_wr_tg_tg_wrdata2_fields },
+	{ PCI_WR_TG_TG_WR_RUN, 4, 16, NTHW_FPGA_REG_TYPE_WO, 0, 1, pci_wr_tg_tg_wr_run_fields },
+};
+
+static nthw_fpga_field_init_s pdb_config_fields[] = {
+	{ PDB_CONFIG_PORT_OFS, 6, 3, 0 },
+	{ PDB_CONFIG_TS_FORMAT, 3, 0, 0 },
+};
+
+static nthw_fpga_field_init_s pdb_rcp_ctrl_fields[] = {
+	{ PDB_RCP_CTRL_ADR, 4, 0, 0x0000 },
+	{ PDB_RCP_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s pdb_rcp_data_fields[] = {
+	{ PDB_RCP_DATA_ALIGN, 1, 17, 0x0000 },
+	{ PDB_RCP_DATA_CRC_OVERWRITE, 1, 16, 0x0000 },
+	{ PDB_RCP_DATA_DESCRIPTOR, 4, 0, 0x0000 },
+	{ PDB_RCP_DATA_DESC_LEN, 5, 4, 0 },
+	{ PDB_RCP_DATA_DUPLICATE_BIT, 5, 61, 0x0000 },
+	{ PDB_RCP_DATA_DUPLICATE_EN, 1, 60, 0x0000 },
+	{ PDB_RCP_DATA_IP_PROT_TNL, 1, 57, 0x0000 },
+	{ PDB_RCP_DATA_OFS0_DYN, 5, 18, 0x0000 },
+	{ PDB_RCP_DATA_OFS0_REL, 8, 23, 0x0000 },
+	{ PDB_RCP_DATA_OFS1_DYN, 5, 31, 0x0000 },
+	{ PDB_RCP_DATA_OFS1_REL, 8, 36, 0x0000 },
+	{ PDB_RCP_DATA_OFS2_DYN, 5, 44, 0x0000 },
+	{ PDB_RCP_DATA_OFS2_REL, 8, 49, 0x0000 },
+	{ PDB_RCP_DATA_PCAP_KEEP_FCS, 1, 66, 0x0000 },
+	{ PDB_RCP_DATA_PPC_HSH, 2, 58, 0x0000 },
+	{ PDB_RCP_DATA_TX_IGNORE, 1, 14, 0x0000 },
+	{ PDB_RCP_DATA_TX_NOW, 1, 15, 0x0000 },
+	{ PDB_RCP_DATA_TX_PORT, 5, 9, 0x0000 },
+};
+
+static nthw_fpga_register_init_s pdb_registers[] = {
+	{ PDB_CONFIG, 2, 10, NTHW_FPGA_REG_TYPE_WO, 0, 2, pdb_config_fields },
+	{ PDB_RCP_CTRL, 0, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, pdb_rcp_ctrl_fields },
+	{ PDB_RCP_DATA, 1, 67, NTHW_FPGA_REG_TYPE_WO, 0, 18, pdb_rcp_data_fields },
+};
+
+static nthw_fpga_field_init_s pdi_cr_fields[] = {
+	{ PDI_CR_EN, 1, 0, 0 }, { PDI_CR_PARITY, 1, 4, 0 }, { PDI_CR_RST, 1, 1, 0 },
+	{ PDI_CR_RXRST, 1, 2, 0 }, { PDI_CR_STOP, 1, 5, 0 }, { PDI_CR_TXRST, 1, 3, 0 },
+};
+
+static nthw_fpga_field_init_s pdi_drr_fields[] = {
+	{ PDI_DRR_DRR, 8, 0, 0 },
+};
+
+static nthw_fpga_field_init_s pdi_dtr_fields[] = {
+	{ PDI_DTR_DTR, 8, 0, 0 },
+};
+
+static nthw_fpga_field_init_s pdi_pre_fields[] = {
+	{ PDI_PRE_PRE, 7, 0, 3 },
+};
+
+static nthw_fpga_field_init_s pdi_sr_fields[] = {
+	{ PDI_SR_DISABLE_BUSY, 1, 2, 0 }, { PDI_SR_DONE, 1, 0, 0 },
+	{ PDI_SR_ENABLE_BUSY, 1, 1, 0 }, { PDI_SR_FRAME_ERR, 1, 5, 0 },
+	{ PDI_SR_OVERRUN_ERR, 1, 7, 0 }, { PDI_SR_PARITY_ERR, 1, 6, 0 },
+	{ PDI_SR_RXLVL, 7, 8, 0 }, { PDI_SR_RX_BUSY, 1, 4, 0 },
+	{ PDI_SR_TXLVL, 7, 15, 0 }, { PDI_SR_TX_BUSY, 1, 3, 0 },
+};
+
+static nthw_fpga_field_init_s pdi_srr_fields[] = {
+	{ PDI_SRR_RST, 4, 0, 0 },
+};
+
+static nthw_fpga_register_init_s pdi_registers[] = {
+	{ PDI_CR, 1, 6, NTHW_FPGA_REG_TYPE_WO, 0, 6, pdi_cr_fields },
+	{ PDI_DRR, 4, 8, NTHW_FPGA_REG_TYPE_RO, 0, 1, pdi_drr_fields },
+	{ PDI_DTR, 3, 8, NTHW_FPGA_REG_TYPE_WO, 0, 1, pdi_dtr_fields },
+	{ PDI_PRE, 5, 7, NTHW_FPGA_REG_TYPE_WO, 3, 1, pdi_pre_fields },
+	{ PDI_SR, 2, 22, NTHW_FPGA_REG_TYPE_RO, 0, 10, pdi_sr_fields },
+	{ PDI_SRR, 0, 4, NTHW_FPGA_REG_TYPE_WO, 0, 1, pdi_srr_fields },
+};
+
+static nthw_fpga_field_init_s qsl_qen_ctrl_fields[] = {
+	{ QSL_QEN_CTRL_ADR, 5, 0, 0x0000 },
+	{ QSL_QEN_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s qsl_qen_data_fields[] = {
+	{ QSL_QEN_DATA_EN, 4, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s qsl_qst_ctrl_fields[] = {
+	{ QSL_QST_CTRL_ADR, 12, 0, 0x0000 },
+	{ QSL_QST_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s qsl_qst_data_fields[] = {
+	{ QSL_QST_DATA_LRE, 1, 9, 0x0000 }, { QSL_QST_DATA_QEN, 1, 7, 0x0000 },
+	{ QSL_QST_DATA_QUEUE, 7, 0, 0x0000 }, { QSL_QST_DATA_TCI, 16, 10, 0x0000 },
+	{ QSL_QST_DATA_TX_PORT, 1, 8, 0x0000 }, { QSL_QST_DATA_VEN, 1, 26, 0x0000 },
+};
+
+static nthw_fpga_field_init_s qsl_rcp_ctrl_fields[] = {
+	{ QSL_RCP_CTRL_ADR, 5, 0, 0x0000 },
+	{ QSL_RCP_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s qsl_rcp_data_fields[] = {
+	{ QSL_RCP_DATA_DISCARD, 1, 0, 0x0000 }, { QSL_RCP_DATA_DROP, 2, 1, 0x0000 },
+	{ QSL_RCP_DATA_LR, 2, 51, 0x0000 }, { QSL_RCP_DATA_TBL_HI, 12, 15, 0x0000 },
+	{ QSL_RCP_DATA_TBL_IDX, 12, 27, 0x0000 }, { QSL_RCP_DATA_TBL_LO, 12, 3, 0x0000 },
+	{ QSL_RCP_DATA_TBL_MSK, 12, 39, 0x0000 }, { QSL_RCP_DATA_TSA, 1, 53, 0x0000 },
+	{ QSL_RCP_DATA_VLI, 2, 54, 0x0000 },
+};
+
+static nthw_fpga_field_init_s qsl_unmq_ctrl_fields[] = {
+	{ QSL_UNMQ_CTRL_ADR, 1, 0, 0x0000 },
+	{ QSL_UNMQ_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s qsl_unmq_data_fields[] = {
+	{ QSL_UNMQ_DATA_DEST_QUEUE, 7, 0, 0x0000 },
+	{ QSL_UNMQ_DATA_EN, 1, 7, 0x0000 },
+};
+
+static nthw_fpga_register_init_s qsl_registers[] = {
+	{ QSL_QEN_CTRL, 4, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, qsl_qen_ctrl_fields },
+	{ QSL_QEN_DATA, 5, 4, NTHW_FPGA_REG_TYPE_WO, 0, 1, qsl_qen_data_fields },
+	{ QSL_QST_CTRL, 2, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, qsl_qst_ctrl_fields },
+	{ QSL_QST_DATA, 3, 27, NTHW_FPGA_REG_TYPE_WO, 0, 6, qsl_qst_data_fields },
+	{ QSL_RCP_CTRL, 0, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, qsl_rcp_ctrl_fields },
+	{ QSL_RCP_DATA, 1, 56, NTHW_FPGA_REG_TYPE_WO, 0, 9, qsl_rcp_data_fields },
+	{ QSL_UNMQ_CTRL, 6, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, qsl_unmq_ctrl_fields },
+	{ QSL_UNMQ_DATA, 7, 8, NTHW_FPGA_REG_TYPE_WO, 0, 2, qsl_unmq_data_fields },
+};
+
+static nthw_fpga_field_init_s qspi_cr_fields[] = {
+	{ QSPI_CR_CPHA, 1, 4, 0 }, { QSPI_CR_CPOL, 1, 3, 0 },
+	{ QSPI_CR_LOOP, 1, 0, 0 }, { QSPI_CR_LSBF, 1, 9, 0 },
+	{ QSPI_CR_MSSAE, 1, 7, 1 }, { QSPI_CR_MST, 1, 2, 0 },
+	{ QSPI_CR_MTI, 1, 8, 1 }, { QSPI_CR_RXFIFO_RST, 1, 6, 0 },
+	{ QSPI_CR_SPE, 1, 1, 0 }, { QSPI_CR_TXFIFO_RST, 1, 5, 0 },
+};
+
+static nthw_fpga_field_init_s qspi_dgie_fields[] = {
+	{ QSPI_DGIE_GIE, 1, 31, 0 },
+};
+
+static nthw_fpga_field_init_s qspi_drr_fields[] = {
+	{ QSPI_DRR_DATA_VAL, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s qspi_dtr_fields[] = {
+	{ QSPI_DTR_DATA_VAL, 32, 0, 0 },
+};
+
+static nthw_fpga_field_init_s qspi_ier_fields[] = {
+	{ QSPI_IER_CMD_ERR, 1, 13, 0 }, { QSPI_IER_CPOL_CPHA_ERR, 1, 9, 0 },
+	{ QSPI_IER_DRR_FULL, 1, 4, 0 }, { QSPI_IER_DRR_NEMPTY, 1, 8, 0 },
+	{ QSPI_IER_DRR_OR, 1, 5, 0 }, { QSPI_IER_DTR_EMPTY, 1, 2, 0 },
+	{ QSPI_IER_DTR_UR, 1, 3, 0 }, { QSPI_IER_LOOP_ERR, 1, 12, 0 },
+	{ QSPI_IER_MODF, 1, 0, 0 }, { QSPI_IER_MSB_ERR, 1, 11, 0 },
+	{ QSPI_IER_SLV_ERR, 1, 10, 0 }, { QSPI_IER_SLV_MODF, 1, 1, 0 },
+	{ QSPI_IER_SLV_MS, 1, 7, 0 }, { QSPI_IER_TXFIFO_HEMPTY, 1, 6, 0 },
+};
+
+static nthw_fpga_field_init_s qspi_isr_fields[] = {
+	{ QSPI_ISR_CMD_ERR, 1, 13, 0 }, { QSPI_ISR_CPOL_CPHA_ERR, 1, 9, 0 },
+	{ QSPI_ISR_DRR_FULL, 1, 4, 0 }, { QSPI_ISR_DRR_NEMPTY, 1, 8, 0 },
+	{ QSPI_ISR_DRR_OR, 1, 5, 0 }, { QSPI_ISR_DTR_EMPTY, 1, 2, 0 },
+	{ QSPI_ISR_DTR_UR, 1, 3, 0 }, { QSPI_ISR_LOOP_ERR, 1, 12, 0 },
+	{ QSPI_ISR_MODF, 1, 0, 0 }, { QSPI_ISR_MSB_ERR, 1, 11, 0 },
+	{ QSPI_ISR_SLV_ERR, 1, 10, 0 }, { QSPI_ISR_SLV_MODF, 1, 1, 0 },
+	{ QSPI_ISR_SLV_MS, 1, 7, 0 }, { QSPI_ISR_TXFIFO_HEMPTY, 1, 6, 0 },
+};
+
+static nthw_fpga_field_init_s qspi_rx_fifo_ocy_fields[] = {
+	{ QSPI_RX_FIFO_OCY_OCY_VAL, 32, 0, 0 },
+};
+
+static nthw_fpga_field_init_s qspi_sr_fields[] = {
+	{ QSPI_SR_CMD_ERR, 1, 10, 0 }, { QSPI_SR_CPOL_CPHA_ERR, 1, 6, 0 },
+	{ QSPI_SR_LOOP_ERR, 1, 9, 0 }, { QSPI_SR_MODF, 1, 4, 0 },
+	{ QSPI_SR_MSB_ERR, 1, 8, 0 }, { QSPI_SR_RXEMPTY, 1, 0, 1 },
+	{ QSPI_SR_RXFULL, 1, 1, 0 }, { QSPI_SR_SLVMS, 1, 5, 1 },
+	{ QSPI_SR_SLV_ERR, 1, 7, 0 }, { QSPI_SR_TXEMPTY, 1, 2, 1 },
+	{ QSPI_SR_TXFULL, 1, 3, 0 },
+};
+
+static nthw_fpga_field_init_s qspi_srr_fields[] = {
+	{ QSPI_SRR_RST, 4, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s qspi_ssr_fields[] = {
+	{ QSPI_SSR_SEL_SLV, 32, 0, 4294967295 },
+};
+
+static nthw_fpga_field_init_s qspi_tx_fifo_ocy_fields[] = {
+	{ QSPI_TX_FIFO_OCY_OCY_VAL, 32, 0, 0 },
+};
+
+static nthw_fpga_register_init_s qspi_registers[] = {
+	{ QSPI_CR, 24, 10, NTHW_FPGA_REG_TYPE_RW, 384, 10, qspi_cr_fields },
+	{ QSPI_DGIE, 7, 32, NTHW_FPGA_REG_TYPE_RW, 0, 1, qspi_dgie_fields },
+	{ QSPI_DRR, 27, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, qspi_drr_fields },
+	{ QSPI_DTR, 26, 32, NTHW_FPGA_REG_TYPE_WO, 0, 1, qspi_dtr_fields },
+	{ QSPI_IER, 10, 14, NTHW_FPGA_REG_TYPE_RW, 0, 14, qspi_ier_fields },
+	{ QSPI_ISR, 8, 14, NTHW_FPGA_REG_TYPE_RW, 0, 14, qspi_isr_fields },
+	{ QSPI_RX_FIFO_OCY, 30, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, qspi_rx_fifo_ocy_fields },
+	{ QSPI_SR, 25, 11, NTHW_FPGA_REG_TYPE_RO, 37, 11, qspi_sr_fields },
+	{ QSPI_SRR, 16, 4, NTHW_FPGA_REG_TYPE_WO, 0, 1, qspi_srr_fields },
+	{ QSPI_SSR, 28, 32, NTHW_FPGA_REG_TYPE_RW, 4294967295, 1, qspi_ssr_fields },
+	{ QSPI_TX_FIFO_OCY, 29, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, qspi_tx_fifo_ocy_fields },
+};
+
+static nthw_fpga_field_init_s rac_dbg_ctrl_fields[] = {
+	{ RAC_DBG_CTRL_C, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s rac_dbg_data_fields[] = {
+	{ RAC_DBG_DATA_D, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s rac_rab_buf_free_fields[] = {
+	{ RAC_RAB_BUF_FREE_IB_FREE, 9, 0, 511 }, { RAC_RAB_BUF_FREE_IB_OVF, 1, 12, 0 },
+	{ RAC_RAB_BUF_FREE_OB_FREE, 9, 16, 511 }, { RAC_RAB_BUF_FREE_OB_OVF, 1, 28, 0 },
+	{ RAC_RAB_BUF_FREE_TIMEOUT, 1, 31, 0 },
+};
+
+static nthw_fpga_field_init_s rac_rab_buf_used_fields[] = {
+	{ RAC_RAB_BUF_USED_FLUSH, 1, 31, 0 },
+	{ RAC_RAB_BUF_USED_IB_USED, 9, 0, 0 },
+	{ RAC_RAB_BUF_USED_OB_USED, 9, 16, 0 },
+};
+
+static nthw_fpga_field_init_s rac_rab_dma_ib_hi_fields[] = {
+	{ RAC_RAB_DMA_IB_HI_PHYADDR, 32, 0, 0 },
+};
+
+static nthw_fpga_field_init_s rac_rab_dma_ib_lo_fields[] = {
+	{ RAC_RAB_DMA_IB_LO_PHYADDR, 32, 0, 0 },
+};
+
+static nthw_fpga_field_init_s rac_rab_dma_ib_rd_fields[] = {
+	{ RAC_RAB_DMA_IB_RD_PTR, 16, 0, 0 },
+};
+
+static nthw_fpga_field_init_s rac_rab_dma_ib_wr_fields[] = {
+	{ RAC_RAB_DMA_IB_WR_PTR, 16, 0, 0 },
+};
+
+static nthw_fpga_field_init_s rac_rab_dma_ob_hi_fields[] = {
+	{ RAC_RAB_DMA_OB_HI_PHYADDR, 32, 0, 0 },
+};
+
+static nthw_fpga_field_init_s rac_rab_dma_ob_lo_fields[] = {
+	{ RAC_RAB_DMA_OB_LO_PHYADDR, 32, 0, 0 },
+};
+
+static nthw_fpga_field_init_s rac_rab_dma_ob_wr_fields[] = {
+	{ RAC_RAB_DMA_OB_WR_PTR, 16, 0, 0 },
+};
+
+static nthw_fpga_field_init_s rac_rab_ib_data_fields[] = {
+	{ RAC_RAB_IB_DATA_D, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s rac_rab_init_fields[] = {
+	{ RAC_RAB_INIT_RAB, 3, 0, 7 },
+};
+
+static nthw_fpga_field_init_s rac_rab_ob_data_fields[] = {
+	{ RAC_RAB_OB_DATA_D, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_register_init_s rac_registers[] = {
+	{ RAC_DBG_CTRL, 4200, 32, NTHW_FPGA_REG_TYPE_RW, 0, 1, rac_dbg_ctrl_fields },
+	{ RAC_DBG_DATA, 4208, 32, NTHW_FPGA_REG_TYPE_RW, 0, 1, rac_dbg_data_fields },
+	{
+		RAC_RAB_BUF_FREE, 4176, 32, NTHW_FPGA_REG_TYPE_MIXED, 33489407, 5,
+		rac_rab_buf_free_fields
+	},
+	{ RAC_RAB_BUF_USED, 4184, 32, NTHW_FPGA_REG_TYPE_MIXED, 0, 3, rac_rab_buf_used_fields },
+	{ RAC_RAB_DMA_IB_HI, 4360, 32, NTHW_FPGA_REG_TYPE_WO, 0, 1, rac_rab_dma_ib_hi_fields },
+	{ RAC_RAB_DMA_IB_LO, 4352, 32, NTHW_FPGA_REG_TYPE_WO, 0, 1, rac_rab_dma_ib_lo_fields },
+	{ RAC_RAB_DMA_IB_RD, 4424, 16, NTHW_FPGA_REG_TYPE_RO, 0, 1, rac_rab_dma_ib_rd_fields },
+	{ RAC_RAB_DMA_IB_WR, 4416, 16, NTHW_FPGA_REG_TYPE_WO, 0, 1, rac_rab_dma_ib_wr_fields },
+	{ RAC_RAB_DMA_OB_HI, 4376, 32, NTHW_FPGA_REG_TYPE_WO, 0, 1, rac_rab_dma_ob_hi_fields },
+	{ RAC_RAB_DMA_OB_LO, 4368, 32, NTHW_FPGA_REG_TYPE_WO, 0, 1, rac_rab_dma_ob_lo_fields },
+	{ RAC_RAB_DMA_OB_WR, 4480, 16, NTHW_FPGA_REG_TYPE_RO, 0, 1, rac_rab_dma_ob_wr_fields },
+	{ RAC_RAB_IB_DATA, 4160, 32, NTHW_FPGA_REG_TYPE_WO, 0, 1, rac_rab_ib_data_fields },
+	{ RAC_RAB_INIT, 4192, 3, NTHW_FPGA_REG_TYPE_RW, 7, 1, rac_rab_init_fields },
+	{ RAC_RAB_OB_DATA, 4168, 32, NTHW_FPGA_REG_TYPE_RC1, 0, 1, rac_rab_ob_data_fields },
+};
+
+static nthw_fpga_field_init_s rfd_ctrl_fields[] = {
+	{ RFD_CTRL_CFP, 1, 2, 1 },
+	{ RFD_CTRL_ISL, 1, 0, 1 },
+	{ RFD_CTRL_PWMCW, 1, 1, 1 },
+};
+
+static nthw_fpga_field_init_s rfd_max_frame_size_fields[] = {
+	{ RFD_MAX_FRAME_SIZE_MAX, 14, 0, 9018 },
+};
+
+static nthw_fpga_field_init_s rfd_tnl_vlan_fields[] = {
+	{ RFD_TNL_VLAN_TPID0, 16, 0, 33024 },
+	{ RFD_TNL_VLAN_TPID1, 16, 16, 33024 },
+};
+
+static nthw_fpga_field_init_s rfd_vlan_fields[] = {
+	{ RFD_VLAN_TPID0, 16, 0, 33024 },
+	{ RFD_VLAN_TPID1, 16, 16, 33024 },
+};
+
+static nthw_fpga_field_init_s rfd_vxlan_fields[] = {
+	{ RFD_VXLAN_DP0, 16, 0, 4789 },
+	{ RFD_VXLAN_DP1, 16, 16, 4789 },
+};
+
+static nthw_fpga_register_init_s rfd_registers[] = {
+	{ RFD_CTRL, 0, 3, NTHW_FPGA_REG_TYPE_WO, 7, 3, rfd_ctrl_fields },
+	{ RFD_MAX_FRAME_SIZE, 1, 14, NTHW_FPGA_REG_TYPE_WO, 9018, 1, rfd_max_frame_size_fields },
+	{ RFD_TNL_VLAN, 3, 32, NTHW_FPGA_REG_TYPE_WO, 2164293888, 2, rfd_tnl_vlan_fields },
+	{ RFD_VLAN, 2, 32, NTHW_FPGA_REG_TYPE_WO, 2164293888, 2, rfd_vlan_fields },
+	{ RFD_VXLAN, 4, 32, NTHW_FPGA_REG_TYPE_WO, 313856693, 2, rfd_vxlan_fields },
+};
+
+static nthw_fpga_field_init_s rmc_ctrl_fields[] = {
+	{ RMC_CTRL_BLOCK_KEEPA, 1, 1, 1 }, { RMC_CTRL_BLOCK_MAC_PORT, 2, 8, 3 },
+	{ RMC_CTRL_BLOCK_RPP_SLICE, 8, 10, 0 }, { RMC_CTRL_BLOCK_STATT, 1, 0, 1 },
+	{ RMC_CTRL_LAG_PHY_ODD_EVEN, 1, 24, 0 },
+};
+
+static nthw_fpga_field_init_s rmc_dbg_fields[] = {
+	{ RMC_DBG_MERGE, 31, 0, 0 },
+};
+
+static nthw_fpga_field_init_s rmc_mac_if_fields[] = {
+	{ RMC_MAC_IF_ERR, 31, 0, 0 },
+};
+
+static nthw_fpga_field_init_s rmc_status_fields[] = {
+	{ RMC_STATUS_DESCR_FIFO_OF, 1, 16, 0 },
+	{ RMC_STATUS_SF_RAM_OF, 1, 0, 0 },
+};
+
+static nthw_fpga_register_init_s rmc_registers[] = {
+	{ RMC_CTRL, 0, 25, NTHW_FPGA_REG_TYPE_RW, 771, 5, rmc_ctrl_fields },
+	{ RMC_DBG, 2, 31, NTHW_FPGA_REG_TYPE_RO, 0, 1, rmc_dbg_fields },
+	{ RMC_MAC_IF, 3, 31, NTHW_FPGA_REG_TYPE_RO, 0, 1, rmc_mac_if_fields },
+	{ RMC_STATUS, 1, 17, NTHW_FPGA_REG_TYPE_RO, 0, 2, rmc_status_fields },
+};
+
+static nthw_fpga_field_init_s rpl_ext_ctrl_fields[] = {
+	{ RPL_EXT_CTRL_ADR, 10, 0, 0x0000 },
+	{ RPL_EXT_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s rpl_ext_data_fields[] = {
+	{ RPL_EXT_DATA_RPL_PTR, 12, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s rpl_rcp_ctrl_fields[] = {
+	{ RPL_RCP_CTRL_ADR, 4, 0, 0x0000 },
+	{ RPL_RCP_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s rpl_rcp_data_fields[] = {
+	{ RPL_RCP_DATA_DYN, 5, 0, 0x0000 }, { RPL_RCP_DATA_ETH_TYPE_WR, 1, 36, 0x0000 },
+	{ RPL_RCP_DATA_EXT_PRIO, 1, 35, 0x0000 }, { RPL_RCP_DATA_LEN, 8, 15, 0x0000 },
+	{ RPL_RCP_DATA_OFS, 10, 5, 0x0000 }, { RPL_RCP_DATA_RPL_PTR, 12, 23, 0x0000 },
+};
+
+static nthw_fpga_field_init_s rpl_rpl_ctrl_fields[] = {
+	{ RPL_RPL_CTRL_ADR, 12, 0, 0x0000 },
+	{ RPL_RPL_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s rpl_rpl_data_fields[] = {
+	{ RPL_RPL_DATA_VALUE, 128, 0, 0x0000 },
+};
+
+static nthw_fpga_register_init_s rpl_registers[] = {
+	{ RPL_EXT_CTRL, 2, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, rpl_ext_ctrl_fields },
+	{ RPL_EXT_DATA, 3, 12, NTHW_FPGA_REG_TYPE_WO, 0, 1, rpl_ext_data_fields },
+	{ RPL_RCP_CTRL, 0, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, rpl_rcp_ctrl_fields },
+	{ RPL_RCP_DATA, 1, 37, NTHW_FPGA_REG_TYPE_WO, 0, 6, rpl_rcp_data_fields },
+	{ RPL_RPL_CTRL, 4, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, rpl_rpl_ctrl_fields },
+	{ RPL_RPL_DATA, 5, 128, NTHW_FPGA_REG_TYPE_WO, 0, 1, rpl_rpl_data_fields },
+};
+
+static nthw_fpga_field_init_s rpp_lr_ifr_rcp_ctrl_fields[] = {
+	{ RPP_LR_IFR_RCP_CTRL_ADR, 4, 0, 0x0000 },
+	{ RPP_LR_IFR_RCP_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s rpp_lr_ifr_rcp_data_fields[] = {
+	{ RPP_LR_IFR_RCP_DATA_IPV4_DF_DROP, 1, 17, 0x0000 },
+	{ RPP_LR_IFR_RCP_DATA_IPV4_EN, 1, 0, 0x0000 },
+	{ RPP_LR_IFR_RCP_DATA_IPV6_DROP, 1, 16, 0x0000 },
+	{ RPP_LR_IFR_RCP_DATA_IPV6_EN, 1, 1, 0x0000 },
+	{ RPP_LR_IFR_RCP_DATA_MTU, 14, 2, 0x0000 },
+};
+
+static nthw_fpga_field_init_s rpp_lr_rcp_ctrl_fields[] = {
+	{ RPP_LR_RCP_CTRL_ADR, 4, 0, 0x0000 },
+	{ RPP_LR_RCP_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s rpp_lr_rcp_data_fields[] = {
+	{ RPP_LR_RCP_DATA_EXP, 14, 0, 0x0000 },
+};
+
+static nthw_fpga_register_init_s rpp_lr_registers[] = {
+	{ RPP_LR_IFR_RCP_CTRL, 2, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, rpp_lr_ifr_rcp_ctrl_fields },
+	{ RPP_LR_IFR_RCP_DATA, 3, 18, NTHW_FPGA_REG_TYPE_WO, 0, 5, rpp_lr_ifr_rcp_data_fields },
+	{ RPP_LR_RCP_CTRL, 0, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, rpp_lr_rcp_ctrl_fields },
+	{ RPP_LR_RCP_DATA, 1, 14, NTHW_FPGA_REG_TYPE_WO, 0, 1, rpp_lr_rcp_data_fields },
+};
+
+static nthw_fpga_field_init_s rst9563_ctrl_fields[] = {
+	{ RST9563_CTRL_PTP_MMCM_CLKSEL, 1, 2, 1 },
+	{ RST9563_CTRL_TS_CLKSEL, 1, 1, 1 },
+	{ RST9563_CTRL_TS_CLKSEL_OVERRIDE, 1, 0, 1 },
+};
+
+static nthw_fpga_field_init_s rst9563_power_fields[] = {
+	{ RST9563_POWER_PU_NSEB, 1, 1, 0 },
+	{ RST9563_POWER_PU_PHY, 1, 0, 0 },
+};
+
+static nthw_fpga_field_init_s rst9563_rst_fields[] = {
+	{ RST9563_RST_CORE_MMCM, 1, 15, 0 }, { RST9563_RST_DDR4, 3, 3, 7 },
+	{ RST9563_RST_MAC_RX, 2, 9, 3 }, { RST9563_RST_PERIPH, 1, 13, 0 },
+	{ RST9563_RST_PHY, 2, 7, 3 }, { RST9563_RST_PTP, 1, 11, 1 },
+	{ RST9563_RST_PTP_MMCM, 1, 16, 0 }, { RST9563_RST_RPP, 1, 2, 1 },
+	{ RST9563_RST_SDC, 1, 6, 1 }, { RST9563_RST_SYS, 1, 0, 1 },
+	{ RST9563_RST_SYS_MMCM, 1, 14, 0 }, { RST9563_RST_TMC, 1, 1, 1 },
+	{ RST9563_RST_TS, 1, 12, 1 }, { RST9563_RST_TS_MMCM, 1, 17, 0 },
+};
+
+static nthw_fpga_field_init_s rst9563_stat_fields[] = {
+	{ RST9563_STAT_CORE_MMCM_LOCKED, 1, 5, 0x0000 },
+	{ RST9563_STAT_DDR4_MMCM_LOCKED, 1, 2, 0x0000 },
+	{ RST9563_STAT_DDR4_PLL_LOCKED, 1, 3, 0x0000 },
+	{ RST9563_STAT_PTP_MMCM_LOCKED, 1, 0, 0x0000 },
+	{ RST9563_STAT_SYS_MMCM_LOCKED, 1, 4, 0x0000 },
+	{ RST9563_STAT_TS_MMCM_LOCKED, 1, 1, 0x0000 },
+};
+
+static nthw_fpga_field_init_s rst9563_sticky_fields[] = {
+	{ RST9563_STICKY_CORE_MMCM_UNLOCKED, 1, 5, 0x0000 },
+	{ RST9563_STICKY_DDR4_MMCM_UNLOCKED, 1, 2, 0x0000 },
+	{ RST9563_STICKY_DDR4_PLL_UNLOCKED, 1, 3, 0x0000 },
+	{ RST9563_STICKY_PTP_MMCM_UNLOCKED, 1, 0, 0x0000 },
+	{ RST9563_STICKY_SYS_MMCM_UNLOCKED, 1, 4, 0x0000 },
+	{ RST9563_STICKY_TS_MMCM_UNLOCKED, 1, 1, 0x0000 },
+};
+
+static nthw_fpga_register_init_s rst9563_registers[] = {
+	{ RST9563_CTRL, 1, 3, NTHW_FPGA_REG_TYPE_RW, 7, 3, rst9563_ctrl_fields },
+	{ RST9563_POWER, 4, 2, NTHW_FPGA_REG_TYPE_RW, 0, 2, rst9563_power_fields },
+	{ RST9563_RST, 0, 18, NTHW_FPGA_REG_TYPE_RW, 8191, 14, rst9563_rst_fields },
+	{ RST9563_STAT, 2, 6, NTHW_FPGA_REG_TYPE_RO, 0, 6, rst9563_stat_fields },
+	{ RST9563_STICKY, 3, 6, NTHW_FPGA_REG_TYPE_RC1, 0, 6, rst9563_sticky_fields },
+};
+
+static nthw_fpga_field_init_s slc_rcp_ctrl_fields[] = {
+	{ SLC_RCP_CTRL_ADR, 6, 0, 0x0000 },
+	{ SLC_RCP_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s slc_rcp_data_fields[] = {
+	{ SLC_RCP_DATA_HEAD_DYN, 5, 1, 0x0000 }, { SLC_RCP_DATA_HEAD_OFS, 8, 6, 0x0000 },
+	{ SLC_RCP_DATA_HEAD_SLC_EN, 1, 0, 0x0000 }, { SLC_RCP_DATA_PCAP, 1, 35, 0x0000 },
+	{ SLC_RCP_DATA_TAIL_DYN, 5, 15, 0x0000 }, { SLC_RCP_DATA_TAIL_OFS, 15, 20, 0x0000 },
+	{ SLC_RCP_DATA_TAIL_SLC_EN, 1, 14, 0x0000 },
+};
+
+static nthw_fpga_register_init_s slc_registers[] = {
+	{ SLC_RCP_CTRL, 0, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, slc_rcp_ctrl_fields },
+	{ SLC_RCP_DATA, 1, 36, NTHW_FPGA_REG_TYPE_WO, 0, 7, slc_rcp_data_fields },
+};
+
+static nthw_fpga_field_init_s spim_cfg_fields[] = {
+	{ SPIM_CFG_PRE, 3, 0, 5 },
+};
+
+static nthw_fpga_field_init_s spim_cfg_clk_fields[] = {
+	{ SPIM_CFG_CLK_MODE, 2, 0, 0 },
+};
+
+static nthw_fpga_field_init_s spim_cr_fields[] = {
+	{ SPIM_CR_EN, 1, 1, 0 },
+	{ SPIM_CR_LOOP, 1, 0, 0 },
+	{ SPIM_CR_RXRST, 1, 3, 0 },
+	{ SPIM_CR_TXRST, 1, 2, 0 },
+};
+
+static nthw_fpga_field_init_s spim_drr_fields[] = {
+	{ SPIM_DRR_DRR, 32, 0, 0 },
+};
+
+static nthw_fpga_field_init_s spim_dtr_fields[] = {
+	{ SPIM_DTR_DTR, 32, 0, 0 },
+};
+
+static nthw_fpga_field_init_s spim_sr_fields[] = {
+	{ SPIM_SR_DONE, 1, 0, 0 }, { SPIM_SR_RXEMPTY, 1, 2, 1 }, { SPIM_SR_RXFULL, 1, 4, 0 },
+	{ SPIM_SR_RXLVL, 8, 16, 0 }, { SPIM_SR_TXEMPTY, 1, 1, 1 }, { SPIM_SR_TXFULL, 1, 3, 0 },
+	{ SPIM_SR_TXLVL, 8, 8, 0 },
+};
+
+static nthw_fpga_field_init_s spim_srr_fields[] = {
+	{ SPIM_SRR_RST, 4, 0, 0 },
+};
+
+static nthw_fpga_register_init_s spim_registers[] = {
+	{ SPIM_CFG, 5, 3, NTHW_FPGA_REG_TYPE_WO, 5, 1, spim_cfg_fields },
+	{ SPIM_CFG_CLK, 6, 2, NTHW_FPGA_REG_TYPE_WO, 0, 1, spim_cfg_clk_fields },
+	{ SPIM_CR, 1, 4, NTHW_FPGA_REG_TYPE_WO, 0, 4, spim_cr_fields },
+	{ SPIM_DRR, 4, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, spim_drr_fields },
+	{ SPIM_DTR, 3, 32, NTHW_FPGA_REG_TYPE_WO, 0, 1, spim_dtr_fields },
+	{ SPIM_SR, 2, 24, NTHW_FPGA_REG_TYPE_RO, 6, 7, spim_sr_fields },
+	{ SPIM_SRR, 0, 4, NTHW_FPGA_REG_TYPE_WO, 0, 1, spim_srr_fields },
+};
+
+static nthw_fpga_field_init_s spis_cr_fields[] = {
+	{ SPIS_CR_DEBUG, 1, 4, 0 }, { SPIS_CR_EN, 1, 1, 0 }, { SPIS_CR_LOOP, 1, 0, 0 },
+	{ SPIS_CR_RXRST, 1, 3, 0 }, { SPIS_CR_TXRST, 1, 2, 0 },
+};
+
+static nthw_fpga_field_init_s spis_drr_fields[] = {
+	{ SPIS_DRR_DRR, 32, 0, 0 },
+};
+
+static nthw_fpga_field_init_s spis_dtr_fields[] = {
+	{ SPIS_DTR_DTR, 32, 0, 0 },
+};
+
+static nthw_fpga_field_init_s spis_ram_ctrl_fields[] = {
+	{ SPIS_RAM_CTRL_ADR, 6, 0, 0 },
+	{ SPIS_RAM_CTRL_CNT, 6, 6, 0 },
+};
+
+static nthw_fpga_field_init_s spis_ram_data_fields[] = {
+	{ SPIS_RAM_DATA_DATA, 32, 0, 0 },
+};
+
+static nthw_fpga_field_init_s spis_sr_fields[] = {
+	{ SPIS_SR_DONE, 1, 0, 0 }, { SPIS_SR_FRAME_ERR, 1, 24, 0 },
+	{ SPIS_SR_READ_ERR, 1, 25, 0 }, { SPIS_SR_RXEMPTY, 1, 2, 1 },
+	{ SPIS_SR_RXFULL, 1, 4, 0 }, { SPIS_SR_RXLVL, 8, 16, 0 },
+	{ SPIS_SR_TXEMPTY, 1, 1, 1 }, { SPIS_SR_TXFULL, 1, 3, 0 },
+	{ SPIS_SR_TXLVL, 8, 8, 0 }, { SPIS_SR_WRITE_ERR, 1, 26, 0 },
+};
+
+static nthw_fpga_field_init_s spis_srr_fields[] = {
+	{ SPIS_SRR_RST, 4, 0, 0 },
+};
+
+static nthw_fpga_register_init_s spis_registers[] = {
+	{ SPIS_CR, 1, 5, NTHW_FPGA_REG_TYPE_WO, 0, 5, spis_cr_fields },
+	{ SPIS_DRR, 4, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, spis_drr_fields },
+	{ SPIS_DTR, 3, 32, NTHW_FPGA_REG_TYPE_WO, 0, 1, spis_dtr_fields },
+	{ SPIS_RAM_CTRL, 5, 12, NTHW_FPGA_REG_TYPE_RW, 0, 2, spis_ram_ctrl_fields },
+	{ SPIS_RAM_DATA, 6, 32, NTHW_FPGA_REG_TYPE_RW, 0, 1, spis_ram_data_fields },
+	{ SPIS_SR, 2, 27, NTHW_FPGA_REG_TYPE_RO, 6, 10, spis_sr_fields },
+	{ SPIS_SRR, 0, 4, NTHW_FPGA_REG_TYPE_WO, 0, 1, spis_srr_fields },
+};
+
+static nthw_fpga_field_init_s sta_byte_fields[] = {
+	{ STA_BYTE_CNT, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s sta_cfg_fields[] = {
+	{ STA_CFG_CNT_CLEAR, 1, 1, 0 },
+	{ STA_CFG_DMA_ENA, 1, 0, 0 },
+};
+
+static nthw_fpga_field_init_s sta_cv_err_fields[] = {
+	{ STA_CV_ERR_CNT, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s sta_fcs_err_fields[] = {
+	{ STA_FCS_ERR_CNT, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s sta_host_adr_lsb_fields[] = {
+	{ STA_HOST_ADR_LSB_LSB, 32, 0, 0 },
+};
+
+static nthw_fpga_field_init_s sta_host_adr_msb_fields[] = {
+	{ STA_HOST_ADR_MSB_MSB, 32, 0, 0 },
+};
+
+static nthw_fpga_field_init_s sta_load_bin_fields[] = {
+	{ STA_LOAD_BIN_BIN, 32, 0, 8388607 },
+};
+
+static nthw_fpga_field_init_s sta_load_bps_rx_0_fields[] = {
+	{ STA_LOAD_BPS_RX_0_BPS, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s sta_load_bps_rx_1_fields[] = {
+	{ STA_LOAD_BPS_RX_1_BPS, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s sta_load_bps_tx_0_fields[] = {
+	{ STA_LOAD_BPS_TX_0_BPS, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s sta_load_bps_tx_1_fields[] = {
+	{ STA_LOAD_BPS_TX_1_BPS, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s sta_load_pps_rx_0_fields[] = {
+	{ STA_LOAD_PPS_RX_0_PPS, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s sta_load_pps_rx_1_fields[] = {
+	{ STA_LOAD_PPS_RX_1_PPS, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s sta_load_pps_tx_0_fields[] = {
+	{ STA_LOAD_PPS_TX_0_PPS, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s sta_load_pps_tx_1_fields[] = {
+	{ STA_LOAD_PPS_TX_1_PPS, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s sta_pckt_fields[] = {
+	{ STA_PCKT_CNT, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s sta_status_fields[] = {
+	{ STA_STATUS_STAT_TOGGLE_MISSED, 1, 0, 0x0000 },
+};
+
+static nthw_fpga_register_init_s sta_registers[] = {
+	{ STA_BYTE, 4, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, sta_byte_fields },
+	{ STA_CFG, 0, 2, NTHW_FPGA_REG_TYPE_RW, 0, 2, sta_cfg_fields },
+	{ STA_CV_ERR, 5, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, sta_cv_err_fields },
+	{ STA_FCS_ERR, 6, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, sta_fcs_err_fields },
+	{ STA_HOST_ADR_LSB, 1, 32, NTHW_FPGA_REG_TYPE_WO, 0, 1, sta_host_adr_lsb_fields },
+	{ STA_HOST_ADR_MSB, 2, 32, NTHW_FPGA_REG_TYPE_WO, 0, 1, sta_host_adr_msb_fields },
+	{ STA_LOAD_BIN, 8, 32, NTHW_FPGA_REG_TYPE_WO, 8388607, 1, sta_load_bin_fields },
+	{ STA_LOAD_BPS_RX_0, 11, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, sta_load_bps_rx_0_fields },
+	{ STA_LOAD_BPS_RX_1, 13, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, sta_load_bps_rx_1_fields },
+	{ STA_LOAD_BPS_TX_0, 15, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, sta_load_bps_tx_0_fields },
+	{ STA_LOAD_BPS_TX_1, 17, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, sta_load_bps_tx_1_fields },
+	{ STA_LOAD_PPS_RX_0, 10, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, sta_load_pps_rx_0_fields },
+	{ STA_LOAD_PPS_RX_1, 12, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, sta_load_pps_rx_1_fields },
+	{ STA_LOAD_PPS_TX_0, 14, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, sta_load_pps_tx_0_fields },
+	{ STA_LOAD_PPS_TX_1, 16, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, sta_load_pps_tx_1_fields },
+	{ STA_PCKT, 3, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, sta_pckt_fields },
+	{ STA_STATUS, 7, 1, NTHW_FPGA_REG_TYPE_RC1, 0, 1, sta_status_fields },
+};
+
+static nthw_fpga_field_init_s tempmon_alarms_fields[] = {
+	{ TEMPMON_ALARMS_OT, 1, 1, 0x0000 },
+	{ TEMPMON_ALARMS_OT_OVERWR, 1, 2, 0 },
+	{ TEMPMON_ALARMS_OT_OVERWRVAL, 1, 3, 0 },
+	{ TEMPMON_ALARMS_TEMP, 1, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s tempmon_stat_fields[] = {
+	{ TEMPMON_STAT_TEMP, 12, 0, 0x0000 },
+};
+
+static nthw_fpga_register_init_s tempmon_registers[] = {
+	{ TEMPMON_ALARMS, 1, 4, NTHW_FPGA_REG_TYPE_MIXED, 0, 4, tempmon_alarms_fields },
+	{ TEMPMON_STAT, 0, 12, NTHW_FPGA_REG_TYPE_RO, 0, 1, tempmon_stat_fields },
+};
+
+static nthw_fpga_field_init_s tint_ctrl_fields[] = {
+	{ TINT_CTRL_INTERVAL, 32, 0, 0 },
+};
+
+static nthw_fpga_field_init_s tint_status_fields[] = {
+	{ TINT_STATUS_DELAYED, 8, 8, 0 },
+	{ TINT_STATUS_SKIPPED, 8, 0, 0 },
+};
+
+static nthw_fpga_register_init_s tint_registers[] = {
+	{ TINT_CTRL, 0, 32, NTHW_FPGA_REG_TYPE_WO, 0, 1, tint_ctrl_fields },
+	{ TINT_STATUS, 1, 16, NTHW_FPGA_REG_TYPE_RC1, 0, 2, tint_status_fields },
+};
+
+static nthw_fpga_field_init_s tsm_con0_config_fields[] = {
+	{ TSM_CON0_CONFIG_BLIND, 5, 8, 9 }, { TSM_CON0_CONFIG_DC_SRC, 3, 5, 0 },
+	{ TSM_CON0_CONFIG_PORT, 3, 0, 0 }, { TSM_CON0_CONFIG_PPSIN_2_5V, 1, 13, 0 },
+	{ TSM_CON0_CONFIG_SAMPLE_EDGE, 2, 3, 2 },
+};
+
+static nthw_fpga_field_init_s tsm_con0_interface_fields[] = {
+	{ TSM_CON0_INTERFACE_EX_TERM, 2, 0, 3 }, { TSM_CON0_INTERFACE_IN_REF_PWM, 8, 12, 128 },
+	{ TSM_CON0_INTERFACE_PWM_ENA, 1, 2, 0 }, { TSM_CON0_INTERFACE_RESERVED, 1, 3, 0 },
+	{ TSM_CON0_INTERFACE_VTERM_PWM, 8, 4, 0 },
+};
+
+static nthw_fpga_field_init_s tsm_con0_sample_hi_fields[] = {
+	{ TSM_CON0_SAMPLE_HI_SEC, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s tsm_con0_sample_lo_fields[] = {
+	{ TSM_CON0_SAMPLE_LO_NS, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s tsm_con1_config_fields[] = {
+	{ TSM_CON1_CONFIG_BLIND, 5, 8, 9 }, { TSM_CON1_CONFIG_DC_SRC, 3, 5, 0 },
+	{ TSM_CON1_CONFIG_PORT, 3, 0, 0 }, { TSM_CON1_CONFIG_PPSIN_2_5V, 1, 13, 0 },
+	{ TSM_CON1_CONFIG_SAMPLE_EDGE, 2, 3, 2 },
+};
+
+static nthw_fpga_field_init_s tsm_con1_sample_hi_fields[] = {
+	{ TSM_CON1_SAMPLE_HI_SEC, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s tsm_con1_sample_lo_fields[] = {
+	{ TSM_CON1_SAMPLE_LO_NS, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s tsm_con2_config_fields[] = {
+	{ TSM_CON2_CONFIG_BLIND, 5, 8, 9 }, { TSM_CON2_CONFIG_DC_SRC, 3, 5, 0 },
+	{ TSM_CON2_CONFIG_PORT, 3, 0, 0 }, { TSM_CON2_CONFIG_PPSIN_2_5V, 1, 13, 0 },
+	{ TSM_CON2_CONFIG_SAMPLE_EDGE, 2, 3, 2 },
+};
+
+static nthw_fpga_field_init_s tsm_con2_sample_hi_fields[] = {
+	{ TSM_CON2_SAMPLE_HI_SEC, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s tsm_con2_sample_lo_fields[] = {
+	{ TSM_CON2_SAMPLE_LO_NS, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s tsm_con3_config_fields[] = {
+	{ TSM_CON3_CONFIG_BLIND, 5, 5, 26 },
+	{ TSM_CON3_CONFIG_PORT, 3, 0, 1 },
+	{ TSM_CON3_CONFIG_SAMPLE_EDGE, 2, 3, 1 },
+};
+
+static nthw_fpga_field_init_s tsm_con3_sample_hi_fields[] = {
+	{ TSM_CON3_SAMPLE_HI_SEC, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s tsm_con3_sample_lo_fields[] = {
+	{ TSM_CON3_SAMPLE_LO_NS, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s tsm_con4_config_fields[] = {
+	{ TSM_CON4_CONFIG_BLIND, 5, 5, 26 },
+	{ TSM_CON4_CONFIG_PORT, 3, 0, 1 },
+	{ TSM_CON4_CONFIG_SAMPLE_EDGE, 2, 3, 1 },
+};
+
+static nthw_fpga_field_init_s tsm_con4_sample_hi_fields[] = {
+	{ TSM_CON4_SAMPLE_HI_SEC, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s tsm_con4_sample_lo_fields[] = {
+	{ TSM_CON4_SAMPLE_LO_NS, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s tsm_con5_config_fields[] = {
+	{ TSM_CON5_CONFIG_BLIND, 5, 5, 26 },
+	{ TSM_CON5_CONFIG_PORT, 3, 0, 1 },
+	{ TSM_CON5_CONFIG_SAMPLE_EDGE, 2, 3, 1 },
+};
+
+static nthw_fpga_field_init_s tsm_con5_sample_hi_fields[] = {
+	{ TSM_CON5_SAMPLE_HI_SEC, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s tsm_con5_sample_lo_fields[] = {
+	{ TSM_CON5_SAMPLE_LO_TIME, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s tsm_con6_config_fields[] = {
+	{ TSM_CON6_CONFIG_BLIND, 5, 5, 26 },
+	{ TSM_CON6_CONFIG_PORT, 3, 0, 1 },
+	{ TSM_CON6_CONFIG_SAMPLE_EDGE, 2, 3, 1 },
+};
+
+static nthw_fpga_field_init_s tsm_con6_sample_hi_fields[] = {
+	{ TSM_CON6_SAMPLE_HI_SEC, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s tsm_con6_sample_lo_fields[] = {
+	{ TSM_CON6_SAMPLE_LO_NS, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s tsm_con7_host_sample_hi_fields[] = {
+	{ TSM_CON7_HOST_SAMPLE_HI_SEC, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s tsm_con7_host_sample_lo_fields[] = {
+	{ TSM_CON7_HOST_SAMPLE_LO_NS, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s tsm_config_fields[] = {
+	{ TSM_CONFIG_NTTS_SRC, 2, 5, 0 }, { TSM_CONFIG_NTTS_SYNC, 1, 4, 0 },
+	{ TSM_CONFIG_TIMESET_EDGE, 2, 8, 1 }, { TSM_CONFIG_TIMESET_SRC, 3, 10, 0 },
+	{ TSM_CONFIG_TIMESET_UP, 1, 7, 0 }, { TSM_CONFIG_TS_FORMAT, 4, 0, 1 },
+};
+
+static nthw_fpga_field_init_s tsm_int_config_fields[] = {
+	{ TSM_INT_CONFIG_AUTO_DISABLE, 1, 0, 0 },
+	{ TSM_INT_CONFIG_MASK, 19, 1, 0 },
+};
+
+static nthw_fpga_field_init_s tsm_int_stat_fields[] = {
+	{ TSM_INT_STAT_CAUSE, 19, 1, 0 },
+	{ TSM_INT_STAT_ENABLE, 1, 0, 0 },
+};
+
+static nthw_fpga_field_init_s tsm_led_fields[] = {
+	{ TSM_LED_LED0_BG_COLOR, 2, 3, 0 }, { TSM_LED_LED0_COLOR, 2, 1, 0 },
+	{ TSM_LED_LED0_MODE, 1, 0, 0 }, { TSM_LED_LED0_SRC, 4, 5, 0 },
+	{ TSM_LED_LED1_BG_COLOR, 2, 12, 0 }, { TSM_LED_LED1_COLOR, 2, 10, 0 },
+	{ TSM_LED_LED1_MODE, 1, 9, 0 }, { TSM_LED_LED1_SRC, 4, 14, 1 },
+	{ TSM_LED_LED2_BG_COLOR, 2, 21, 0 }, { TSM_LED_LED2_COLOR, 2, 19, 0 },
+	{ TSM_LED_LED2_MODE, 1, 18, 0 }, { TSM_LED_LED2_SRC, 4, 23, 2 },
+};
+
+static nthw_fpga_field_init_s tsm_ntts_config_fields[] = {
+	{ TSM_NTTS_CONFIG_AUTO_HARDSET, 1, 5, 1 },
+	{ TSM_NTTS_CONFIG_EXT_CLK_ADJ, 1, 6, 0 },
+	{ TSM_NTTS_CONFIG_HIGH_SAMPLE, 1, 4, 0 },
+	{ TSM_NTTS_CONFIG_TS_SRC_FORMAT, 4, 0, 0 },
+};
+
+static nthw_fpga_field_init_s tsm_ntts_ext_stat_fields[] = {
+	{ TSM_NTTS_EXT_STAT_MASTER_ID, 8, 16, 0x0000 },
+	{ TSM_NTTS_EXT_STAT_MASTER_REV, 8, 24, 0x0000 },
+	{ TSM_NTTS_EXT_STAT_MASTER_STAT, 16, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s tsm_ntts_limit_hi_fields[] = {
+	{ TSM_NTTS_LIMIT_HI_SEC, 16, 0, 0 },
+};
+
+static nthw_fpga_field_init_s tsm_ntts_limit_lo_fields[] = {
+	{ TSM_NTTS_LIMIT_LO_NS, 32, 0, 100000 },
+};
+
+static nthw_fpga_field_init_s tsm_ntts_offset_fields[] = {
+	{ TSM_NTTS_OFFSET_NS, 30, 0, 0 },
+};
+
+static nthw_fpga_field_init_s tsm_ntts_sample_hi_fields[] = {
+	{ TSM_NTTS_SAMPLE_HI_SEC, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s tsm_ntts_sample_lo_fields[] = {
+	{ TSM_NTTS_SAMPLE_LO_NS, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s tsm_ntts_stat_fields[] = {
+	{ TSM_NTTS_STAT_NTTS_VALID, 1, 0, 0 },
+	{ TSM_NTTS_STAT_SIGNAL_LOST, 8, 1, 0 },
+	{ TSM_NTTS_STAT_SYNC_LOST, 8, 9, 0 },
+};
+
+static nthw_fpga_field_init_s tsm_ntts_ts_t0_hi_fields[] = {
+	{ TSM_NTTS_TS_T0_HI_TIME, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s tsm_ntts_ts_t0_lo_fields[] = {
+	{ TSM_NTTS_TS_T0_LO_TIME, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s tsm_ntts_ts_t0_offset_fields[] = {
+	{ TSM_NTTS_TS_T0_OFFSET_COUNT, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s tsm_pb_ctrl_fields[] = {
+	{ TSM_PB_CTRL_INSTMEM_WR, 1, 1, 0 },
+	{ TSM_PB_CTRL_RST, 1, 0, 0 },
+};
+
+static nthw_fpga_field_init_s tsm_pb_instmem_fields[] = {
+	{ TSM_PB_INSTMEM_MEM_ADDR, 14, 0, 0 },
+	{ TSM_PB_INSTMEM_MEM_DATA, 18, 14, 0 },
+};
+
+static nthw_fpga_field_init_s tsm_pi_ctrl_i_fields[] = {
+	{ TSM_PI_CTRL_I_VAL, 32, 0, 0 },
+};
+
+static nthw_fpga_field_init_s tsm_pi_ctrl_ki_fields[] = {
+	{ TSM_PI_CTRL_KI_GAIN, 24, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s tsm_pi_ctrl_kp_fields[] = {
+	{ TSM_PI_CTRL_KP_GAIN, 24, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s tsm_pi_ctrl_shl_fields[] = {
+	{ TSM_PI_CTRL_SHL_VAL, 4, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s tsm_stat_fields[] = {
+	{ TSM_STAT_HARD_SYNC, 8, 8, 0 }, { TSM_STAT_LINK_CON0, 1, 0, 0 },
+	{ TSM_STAT_LINK_CON1, 1, 1, 0 }, { TSM_STAT_LINK_CON2, 1, 2, 0 },
+	{ TSM_STAT_LINK_CON3, 1, 3, 0 }, { TSM_STAT_LINK_CON4, 1, 4, 0 },
+	{ TSM_STAT_LINK_CON5, 1, 5, 0 }, { TSM_STAT_NTTS_INSYNC, 1, 6, 0 },
+	{ TSM_STAT_PTP_MI_PRESENT, 1, 7, 0 },
+};
+
+static nthw_fpga_field_init_s tsm_timer_ctrl_fields[] = {
+	{ TSM_TIMER_CTRL_TIMER_EN_T0, 1, 0, 0 },
+	{ TSM_TIMER_CTRL_TIMER_EN_T1, 1, 1, 0 },
+};
+
+static nthw_fpga_field_init_s tsm_timer_t0_fields[] = {
+	{ TSM_TIMER_T0_MAX_COUNT, 30, 0, 50000 },
+};
+
+static nthw_fpga_field_init_s tsm_timer_t1_fields[] = {
+	{ TSM_TIMER_T1_MAX_COUNT, 30, 0, 50000 },
+};
+
+static nthw_fpga_field_init_s tsm_time_hardset_hi_fields[] = {
+	{ TSM_TIME_HARDSET_HI_TIME, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s tsm_time_hardset_lo_fields[] = {
+	{ TSM_TIME_HARDSET_LO_TIME, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s tsm_time_hi_fields[] = {
+	{ TSM_TIME_HI_SEC, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s tsm_time_lo_fields[] = {
+	{ TSM_TIME_LO_NS, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s tsm_time_rate_adj_fields[] = {
+	{ TSM_TIME_RATE_ADJ_FRACTION, 29, 0, 0 },
+};
+
+static nthw_fpga_field_init_s tsm_ts_hi_fields[] = {
+	{ TSM_TS_HI_TIME, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s tsm_ts_lo_fields[] = {
+	{ TSM_TS_LO_TIME, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s tsm_ts_offset_fields[] = {
+	{ TSM_TS_OFFSET_NS, 30, 0, 0 },
+};
+
+static nthw_fpga_field_init_s tsm_ts_stat_fields[] = {
+	{ TSM_TS_STAT_OVERRUN, 1, 16, 0 },
+	{ TSM_TS_STAT_SAMPLES, 16, 0, 0 },
+};
+
+static nthw_fpga_field_init_s tsm_ts_stat_hi_offset_fields[] = {
+	{ TSM_TS_STAT_HI_OFFSET_NS, 32, 0, 0 },
+};
+
+static nthw_fpga_field_init_s tsm_ts_stat_lo_offset_fields[] = {
+	{ TSM_TS_STAT_LO_OFFSET_NS, 32, 0, 0 },
+};
+
+static nthw_fpga_field_init_s tsm_ts_stat_tar_hi_fields[] = {
+	{ TSM_TS_STAT_TAR_HI_SEC, 32, 0, 0 },
+};
+
+static nthw_fpga_field_init_s tsm_ts_stat_tar_lo_fields[] = {
+	{ TSM_TS_STAT_TAR_LO_NS, 32, 0, 0 },
+};
+
+static nthw_fpga_field_init_s tsm_ts_stat_x_fields[] = {
+	{ TSM_TS_STAT_X_NS, 32, 0, 0 },
+};
+
+static nthw_fpga_field_init_s tsm_ts_stat_x2_hi_fields[] = {
+	{ TSM_TS_STAT_X2_HI_NS, 16, 0, 0 },
+};
+
+static nthw_fpga_field_init_s tsm_ts_stat_x2_lo_fields[] = {
+	{ TSM_TS_STAT_X2_LO_NS, 32, 0, 0 },
+};
+
+static nthw_fpga_field_init_s tsm_utc_offset_fields[] = {
+	{ TSM_UTC_OFFSET_SEC, 8, 0, 0 },
+};
+
+static nthw_fpga_register_init_s tsm_registers[] = {
+	{ TSM_CON0_CONFIG, 24, 14, NTHW_FPGA_REG_TYPE_RW, 2320, 5, tsm_con0_config_fields },
+	{
+		TSM_CON0_INTERFACE, 25, 20, NTHW_FPGA_REG_TYPE_RW, 524291, 5,
+		tsm_con0_interface_fields
+	},
+	{ TSM_CON0_SAMPLE_HI, 27, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, tsm_con0_sample_hi_fields },
+	{ TSM_CON0_SAMPLE_LO, 26, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, tsm_con0_sample_lo_fields },
+	{ TSM_CON1_CONFIG, 28, 14, NTHW_FPGA_REG_TYPE_RW, 2320, 5, tsm_con1_config_fields },
+	{ TSM_CON1_SAMPLE_HI, 30, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, tsm_con1_sample_hi_fields },
+	{ TSM_CON1_SAMPLE_LO, 29, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, tsm_con1_sample_lo_fields },
+	{ TSM_CON2_CONFIG, 31, 14, NTHW_FPGA_REG_TYPE_RW, 2320, 5, tsm_con2_config_fields },
+	{ TSM_CON2_SAMPLE_HI, 33, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, tsm_con2_sample_hi_fields },
+	{ TSM_CON2_SAMPLE_LO, 32, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, tsm_con2_sample_lo_fields },
+	{ TSM_CON3_CONFIG, 34, 10, NTHW_FPGA_REG_TYPE_RW, 841, 3, tsm_con3_config_fields },
+	{ TSM_CON3_SAMPLE_HI, 36, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, tsm_con3_sample_hi_fields },
+	{ TSM_CON3_SAMPLE_LO, 35, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, tsm_con3_sample_lo_fields },
+	{ TSM_CON4_CONFIG, 37, 10, NTHW_FPGA_REG_TYPE_RW, 841, 3, tsm_con4_config_fields },
+	{ TSM_CON4_SAMPLE_HI, 39, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, tsm_con4_sample_hi_fields },
+	{ TSM_CON4_SAMPLE_LO, 38, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, tsm_con4_sample_lo_fields },
+	{ TSM_CON5_CONFIG, 40, 10, NTHW_FPGA_REG_TYPE_RW, 841, 3, tsm_con5_config_fields },
+	{ TSM_CON5_SAMPLE_HI, 42, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, tsm_con5_sample_hi_fields },
+	{ TSM_CON5_SAMPLE_LO, 41, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, tsm_con5_sample_lo_fields },
+	{ TSM_CON6_CONFIG, 43, 10, NTHW_FPGA_REG_TYPE_RW, 841, 3, tsm_con6_config_fields },
+	{ TSM_CON6_SAMPLE_HI, 45, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, tsm_con6_sample_hi_fields },
+	{ TSM_CON6_SAMPLE_LO, 44, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, tsm_con6_sample_lo_fields },
+	{
+		TSM_CON7_HOST_SAMPLE_HI, 47, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1,
+		tsm_con7_host_sample_hi_fields
+	},
+	{
+		TSM_CON7_HOST_SAMPLE_LO, 46, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1,
+		tsm_con7_host_sample_lo_fields
+	},
+	{ TSM_CONFIG, 0, 13, NTHW_FPGA_REG_TYPE_RW, 257, 6, tsm_config_fields },
+	{ TSM_INT_CONFIG, 2, 20, NTHW_FPGA_REG_TYPE_RW, 0, 2, tsm_int_config_fields },
+	{ TSM_INT_STAT, 3, 20, NTHW_FPGA_REG_TYPE_MIXED, 0, 2, tsm_int_stat_fields },
+	{ TSM_LED, 4, 27, NTHW_FPGA_REG_TYPE_RW, 16793600, 12, tsm_led_fields },
+	{ TSM_NTTS_CONFIG, 13, 7, NTHW_FPGA_REG_TYPE_RW, 32, 4, tsm_ntts_config_fields },
+	{ TSM_NTTS_EXT_STAT, 15, 32, NTHW_FPGA_REG_TYPE_MIXED, 0, 3, tsm_ntts_ext_stat_fields },
+	{ TSM_NTTS_LIMIT_HI, 23, 16, NTHW_FPGA_REG_TYPE_RW, 0, 1, tsm_ntts_limit_hi_fields },
+	{ TSM_NTTS_LIMIT_LO, 22, 32, NTHW_FPGA_REG_TYPE_RW, 100000, 1, tsm_ntts_limit_lo_fields },
+	{ TSM_NTTS_OFFSET, 21, 30, NTHW_FPGA_REG_TYPE_RW, 0, 1, tsm_ntts_offset_fields },
+	{ TSM_NTTS_SAMPLE_HI, 19, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, tsm_ntts_sample_hi_fields },
+	{ TSM_NTTS_SAMPLE_LO, 18, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, tsm_ntts_sample_lo_fields },
+	{ TSM_NTTS_STAT, 14, 17, NTHW_FPGA_REG_TYPE_RO, 0, 3, tsm_ntts_stat_fields },
+	{ TSM_NTTS_TS_T0_HI, 17, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, tsm_ntts_ts_t0_hi_fields },
+	{ TSM_NTTS_TS_T0_LO, 16, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, tsm_ntts_ts_t0_lo_fields },
+	{
+		TSM_NTTS_TS_T0_OFFSET, 20, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1,
+		tsm_ntts_ts_t0_offset_fields
+	},
+	{ TSM_PB_CTRL, 63, 2, NTHW_FPGA_REG_TYPE_WO, 0, 2, tsm_pb_ctrl_fields },
+	{ TSM_PB_INSTMEM, 64, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, tsm_pb_instmem_fields },
+	{ TSM_PI_CTRL_I, 54, 32, NTHW_FPGA_REG_TYPE_WO, 0, 1, tsm_pi_ctrl_i_fields },
+	{ TSM_PI_CTRL_KI, 52, 24, NTHW_FPGA_REG_TYPE_RW, 0, 1, tsm_pi_ctrl_ki_fields },
+	{ TSM_PI_CTRL_KP, 51, 24, NTHW_FPGA_REG_TYPE_RW, 0, 1, tsm_pi_ctrl_kp_fields },
+	{ TSM_PI_CTRL_SHL, 53, 4, NTHW_FPGA_REG_TYPE_WO, 0, 1, tsm_pi_ctrl_shl_fields },
+	{ TSM_STAT, 1, 16, NTHW_FPGA_REG_TYPE_RO, 0, 9, tsm_stat_fields },
+	{ TSM_TIMER_CTRL, 48, 2, NTHW_FPGA_REG_TYPE_RW, 0, 2, tsm_timer_ctrl_fields },
+	{ TSM_TIMER_T0, 49, 30, NTHW_FPGA_REG_TYPE_RW, 50000, 1, tsm_timer_t0_fields },
+	{ TSM_TIMER_T1, 50, 30, NTHW_FPGA_REG_TYPE_RW, 50000, 1, tsm_timer_t1_fields },
+	{ TSM_TIME_HARDSET_HI, 12, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, tsm_time_hardset_hi_fields },
+	{ TSM_TIME_HARDSET_LO, 11, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, tsm_time_hardset_lo_fields },
+	{ TSM_TIME_HI, 9, 32, NTHW_FPGA_REG_TYPE_RW, 0, 1, tsm_time_hi_fields },
+	{ TSM_TIME_LO, 8, 32, NTHW_FPGA_REG_TYPE_RW, 0, 1, tsm_time_lo_fields },
+	{ TSM_TIME_RATE_ADJ, 10, 29, NTHW_FPGA_REG_TYPE_RW, 0, 1, tsm_time_rate_adj_fields },
+	{ TSM_TS_HI, 6, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, tsm_ts_hi_fields },
+	{ TSM_TS_LO, 5, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, tsm_ts_lo_fields },
+	{ TSM_TS_OFFSET, 7, 30, NTHW_FPGA_REG_TYPE_RW, 0, 1, tsm_ts_offset_fields },
+	{ TSM_TS_STAT, 55, 17, NTHW_FPGA_REG_TYPE_RO, 0, 2, tsm_ts_stat_fields },
+	{
+		TSM_TS_STAT_HI_OFFSET, 62, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1,
+		tsm_ts_stat_hi_offset_fields
+	},
+	{
+		TSM_TS_STAT_LO_OFFSET, 61, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1,
+		tsm_ts_stat_lo_offset_fields
+	},
+	{ TSM_TS_STAT_TAR_HI, 57, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, tsm_ts_stat_tar_hi_fields },
+	{ TSM_TS_STAT_TAR_LO, 56, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, tsm_ts_stat_tar_lo_fields },
+	{ TSM_TS_STAT_X, 58, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, tsm_ts_stat_x_fields },
+	{ TSM_TS_STAT_X2_HI, 60, 16, NTHW_FPGA_REG_TYPE_RO, 0, 1, tsm_ts_stat_x2_hi_fields },
+	{ TSM_TS_STAT_X2_LO, 59, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, tsm_ts_stat_x2_lo_fields },
+	{ TSM_UTC_OFFSET, 65, 8, NTHW_FPGA_REG_TYPE_RW, 0, 1, tsm_utc_offset_fields },
+};
+
+static nthw_fpga_module_init_s fpga_modules[] = {
+	{ MOD_CAT, 0, MOD_CAT, 0, 21, NTHW_FPGA_BUS_TYPE_RAB1, 768, 34, cat_registers },
+	{ MOD_CSU, 0, MOD_CSU, 0, 0, NTHW_FPGA_BUS_TYPE_RAB1, 9728, 2, csu_registers },
+	{ MOD_DBS, 0, MOD_DBS, 0, 11, NTHW_FPGA_BUS_TYPE_RAB2, 12832, 27, dbs_registers },
+	{ MOD_FLM, 0, MOD_FLM, 0, 23, NTHW_FPGA_BUS_TYPE_RAB1, 1280, 43, flm_registers },
+	{ MOD_GFG, 0, MOD_GFG, 1, 1, NTHW_FPGA_BUS_TYPE_RAB2, 8704, 10, gfg_registers },
+	{ MOD_GMF, 0, MOD_GMF, 2, 5, NTHW_FPGA_BUS_TYPE_RAB2, 9216, 12, gmf_registers },
+	{ MOD_GMF, 1, MOD_GMF, 2, 5, NTHW_FPGA_BUS_TYPE_RAB2, 9728, 12, gmf_registers },
+	{
+		MOD_GPIO_PHY, 0, MOD_GPIO_PHY, 1, 0, NTHW_FPGA_BUS_TYPE_RAB0, 16386, 2,
+		gpio_phy_registers
+	},
+	{ MOD_HFU, 0, MOD_HFU, 0, 2, NTHW_FPGA_BUS_TYPE_RAB1, 9472, 2, hfu_registers },
+	{ MOD_HIF, 0, MOD_HIF, 0, 0, NTHW_FPGA_BUS_TYPE_PCI, 0, 18, hif_registers },
+	{ MOD_HSH, 0, MOD_HSH, 0, 5, NTHW_FPGA_BUS_TYPE_RAB1, 1536, 2, hsh_registers },
+	{ MOD_IFR, 0, MOD_IFR, 0, 7, NTHW_FPGA_BUS_TYPE_RAB1, 9984, 6, ifr_registers },
+	{ MOD_IIC, 0, MOD_IIC, 0, 1, NTHW_FPGA_BUS_TYPE_RAB0, 768, 22, iic_registers },
+	{ MOD_IIC, 1, MOD_IIC, 0, 1, NTHW_FPGA_BUS_TYPE_RAB0, 896, 22, iic_registers },
+	{ MOD_IIC, 2, MOD_IIC, 0, 1, NTHW_FPGA_BUS_TYPE_RAB0, 24832, 22, iic_registers },
+	{ MOD_IIC, 3, MOD_IIC, 0, 1, NTHW_FPGA_BUS_TYPE_RAB0, 24960, 22, iic_registers },
+	{ MOD_KM, 0, MOD_KM, 0, 7, NTHW_FPGA_BUS_TYPE_RAB1, 1024, 11, km_registers },
+	{
+		MOD_MAC_PCS, 0, MOD_MAC_PCS, 0, 2, NTHW_FPGA_BUS_TYPE_RAB2, 10240, 44,
+		mac_pcs_registers
+	},
+	{
+		MOD_MAC_PCS, 1, MOD_MAC_PCS, 0, 2, NTHW_FPGA_BUS_TYPE_RAB2, 11776, 44,
+		mac_pcs_registers
+	},
+	{ MOD_MAC_RX, 0, MOD_MAC_RX, 0, 0, NTHW_FPGA_BUS_TYPE_RAB2, 10752, 9, mac_rx_registers },
+	{ MOD_MAC_RX, 1, MOD_MAC_RX, 0, 0, NTHW_FPGA_BUS_TYPE_RAB2, 12288, 9, mac_rx_registers },
+	{ MOD_MAC_TX, 0, MOD_MAC_TX, 0, 0, NTHW_FPGA_BUS_TYPE_RAB2, 11264, 5, mac_tx_registers },
+	{ MOD_MAC_TX, 1, MOD_MAC_TX, 0, 0, NTHW_FPGA_BUS_TYPE_RAB2, 12800, 5, mac_tx_registers },
+	{
+		MOD_PCI_RD_TG, 0, MOD_PCI_RD_TG, 0, 1, NTHW_FPGA_BUS_TYPE_RAB0, 2320, 6,
+		pci_rd_tg_registers
+	},
+	{ MOD_PCI_TA, 0, MOD_PCI_TA, 0, 0, NTHW_FPGA_BUS_TYPE_RAB0, 2336, 5, pci_ta_registers },
+	{
+		MOD_PCI_WR_TG, 0, MOD_PCI_WR_TG, 0, 1, NTHW_FPGA_BUS_TYPE_RAB0, 2304, 7,
+		pci_wr_tg_registers
+	},
+	{ MOD_PDB, 0, MOD_PDB, 0, 9, NTHW_FPGA_BUS_TYPE_RAB1, 2560, 3, pdb_registers },
+	{ MOD_PDI, 0, MOD_PDI, 1, 1, NTHW_FPGA_BUS_TYPE_RAB0, 64, 6, pdi_registers },
+	{ MOD_QSL, 0, MOD_QSL, 0, 7, NTHW_FPGA_BUS_TYPE_RAB1, 1792, 8, qsl_registers },
+	{ MOD_QSPI, 0, MOD_QSPI, 0, 0, NTHW_FPGA_BUS_TYPE_RAB0, 512, 11, qspi_registers },
+	{ MOD_RAC, 0, MOD_RAC, 3, 0, NTHW_FPGA_BUS_TYPE_PCI, 8192, 14, rac_registers },
+	{ MOD_RFD, 0, MOD_RFD, 0, 4, NTHW_FPGA_BUS_TYPE_RAB1, 256, 5, rfd_registers },
+	{ MOD_RMC, 0, MOD_RMC, 1, 3, NTHW_FPGA_BUS_TYPE_RAB0, 12288, 4, rmc_registers },
+	{ MOD_RPP_LR, 0, MOD_RPP_LR, 0, 2, NTHW_FPGA_BUS_TYPE_RAB1, 2304, 4, rpp_lr_registers },
+	{ MOD_RST9563, 0, MOD_RST9563, 0, 5, NTHW_FPGA_BUS_TYPE_RAB0, 1024, 5, rst9563_registers },
+	{ MOD_SLC_LR, 0, MOD_SLC, 0, 2, NTHW_FPGA_BUS_TYPE_RAB1, 2048, 2, slc_registers },
+	{ MOD_SPIM, 0, MOD_SPIM, 1, 1, NTHW_FPGA_BUS_TYPE_RAB0, 80, 7, spim_registers },
+	{ MOD_SPIS, 0, MOD_SPIS, 1, 0, NTHW_FPGA_BUS_TYPE_RAB0, 256, 7, spis_registers },
+	{ MOD_STA, 0, MOD_STA, 0, 9, NTHW_FPGA_BUS_TYPE_RAB0, 2048, 17, sta_registers },
+	{
+		MOD_TEMPMON, 0, MOD_TEMPMON, 0, 0, NTHW_FPGA_BUS_TYPE_RAB0, 16384, 2,
+		tempmon_registers
+	},
+	{ MOD_TINT, 0, MOD_TINT, 0, 0, NTHW_FPGA_BUS_TYPE_RAB0, 1280, 2, tint_registers },
+	{ MOD_TSM, 0, MOD_TSM, 0, 8, NTHW_FPGA_BUS_TYPE_RAB2, 1024, 66, tsm_registers },
+	{ MOD_TX_CPY, 0, MOD_CPY, 0, 4, NTHW_FPGA_BUS_TYPE_RAB1, 9216, 26, cpy_registers },
+	{ MOD_TX_INS, 0, MOD_INS, 0, 2, NTHW_FPGA_BUS_TYPE_RAB1, 8704, 2, ins_registers },
+	{ MOD_TX_RPL, 0, MOD_RPL, 0, 4, NTHW_FPGA_BUS_TYPE_RAB1, 8960, 6, rpl_registers },
+};
+
+static nthw_fpga_prod_param_s product_parameters[] = {
+	{ NT_BUILD_NUMBER, 0 },
+	{ NT_BUILD_TIME, 1713859545 },
+	{ NT_CATEGORIES, 64 },
+	{ NT_CAT_DCT_PRESENT, 0 },
+	{ NT_CAT_END_OFS_SUPPORT, 0 },
+	{ NT_CAT_FUNCS, 64 },
+	{ NT_CAT_KCC_BANKS, 3 },
+	{ NT_CAT_KCC_PRESENT, 0 },
+	{ NT_CAT_KCC_SIZE, 1536 },
+	{ NT_CAT_KM_IF_CNT, 2 },
+	{ NT_CAT_KM_IF_M0, 0 },
+	{ NT_CAT_KM_IF_M1, 1 },
+	{ NT_CAT_N_CMP, 8 },
+	{ NT_CAT_N_EXT, 4 },
+	{ NT_CAT_N_LEN, 8 },
+	{ NT_CB_DEBUG, 0 },
+	{ NT_COR_CATEGORIES, 16 },
+	{ NT_COR_PRESENT, 0 },
+	{ NT_CSU_PRESENT, 1 },
+	{ NT_DBS_PRESENT, 1 },
+	{ NT_DBS_RX_QUEUES, 128 },
+	{ NT_DBS_TX_PORTS, 2 },
+	{ NT_DBS_TX_QUEUES, 128 },
+	{ NT_DDP_PRESENT, 0 },
+	{ NT_DDP_TBL_DEPTH, 4096 },
+	{ NT_EMI_SPLIT_STEPS, 16 },
+	{ NT_EOF_TIMESTAMP_ONLY, 1 },
+	{ NT_EPP_CATEGORIES, 32 },
+	{ NT_FLM_CACHE, 1 },
+	{ NT_FLM_CATEGORIES, 32 },
+	{ NT_FLM_ENTRY_SIZE, 64 },
+	{ NT_FLM_LOAD_APS_MAX, 260000000 },
+	{ NT_FLM_LOAD_LPS_MAX, 300000000 },
+	{ NT_FLM_PRESENT, 1 },
+	{ NT_FLM_PRIOS, 4 },
+	{ NT_FLM_PST_PROFILES, 16 },
+	{ NT_FLM_SCRUB_PROFILES, 16 },
+	{ NT_FLM_SIZE_MB, 12288 },
+	{ NT_FLM_STATEFUL, 1 },
+	{ NT_FLM_VARIANT, 2 },
+	{ NT_GFG_PRESENT, 1 },
+	{ NT_GFG_TX_LIVE_RECONFIG_SUPPORT, 1 },
+	{ NT_GMF_FCS_PRESENT, 0 },
+	{ NT_GMF_IFG_SPEED_DIV, 33 },
+	{ NT_GMF_IFG_SPEED_DIV100G, 33 },
+	{ NT_GMF_IFG_SPEED_MUL, 20 },
+	{ NT_GMF_IFG_SPEED_MUL100G, 20 },
+	{ NT_GROUP_ID, 9563 },
+	{ NT_HFU_PRESENT, 1 },
+	{ NT_HIF_MSIX_BAR, 1 },
+	{ NT_HIF_MSIX_PBA_OFS, 8192 },
+	{ NT_HIF_MSIX_PRESENT, 1 },
+	{ NT_HIF_MSIX_TBL_OFS, 0 },
+	{ NT_HIF_MSIX_TBL_SIZE, 8 },
+	{ NT_HIF_PER_PS, 4000 },
+	{ NT_HIF_SRIOV_PRESENT, 1 },
+	{ NT_HIF_VF_OFFSET, 4 },
+	{ NT_HSH_CATEGORIES, 16 },
+	{ NT_HSH_TOEPLITZ, 1 },
+	{ NT_HST_CATEGORIES, 32 },
+	{ NT_HST_PRESENT, 0 },
+	{ NT_IOA_CATEGORIES, 1024 },
+	{ NT_IOA_PRESENT, 0 },
+	{ NT_IPF_PRESENT, 0 },
+	{ NT_KM_CAM_BANKS, 3 },
+	{ NT_KM_CAM_RECORDS, 2048 },
+	{ NT_KM_CAM_REC_WORDS, 6 },
+	{ NT_KM_CATEGORIES, 32 },
+	{ NT_KM_END_OFS_SUPPORT, 0 },
+	{ NT_KM_EXT_EXTRACTORS, 1 },
+	{ NT_KM_FLOW_TYPES, 16 },
+	{ NT_KM_PRESENT, 1 },
+	{ NT_KM_SWX_PRESENT, 0 },
+	{ NT_KM_SYNERGY_MATCH, 0 },
+	{ NT_KM_TCAM_BANKS, 12 },
+	{ NT_KM_TCAM_BANK_WIDTH, 72 },
+	{ NT_KM_TCAM_HIT_QUAL, 0 },
+	{ NT_KM_TCAM_KEYWAY, 1 },
+	{ NT_KM_WIDE, 1 },
+	{ NT_LR_PRESENT, 1 },
+	{ NT_MCU_PRESENT, 0 },
+	{ NT_MDG_DEBUG_FLOW_CONTROL, 0 },
+	{ NT_MDG_DEBUG_REG_READ_BACK, 0 },
+	{ NT_MSK_CATEGORIES, 32 },
+	{ NT_MSK_PRESENT, 0 },
+	{ NT_NFV_OVS_PRODUCT, 0 },
+	{ NT_NIMS, 2 },
+	{ NT_PCI_DEVICE_ID, 453 },
+	{ NT_PCI_TA_TG_PRESENT, 1 },
+	{ NT_PCI_VENDOR_ID, 6388 },
+	{ NT_PDB_CATEGORIES, 16 },
+	{ NT_PHY_ANEG_PRESENT, 0 },
+	{ NT_PHY_KRFEC_PRESENT, 0 },
+	{ NT_PHY_PORTS, 2 },
+	{ NT_PHY_PORTS_PER_QUAD, 1 },
+	{ NT_PHY_QUADS, 2 },
+	{ NT_PHY_RSFEC_PRESENT, 1 },
+	{ NT_QM_CELLS, 2097152 },
+	{ NT_QM_CELL_SIZE, 6144 },
+	{ NT_QM_PRESENT, 0 },
+	{ NT_QSL_CATEGORIES, 32 },
+	{ NT_QSL_COLOR_SEL_BW, 7 },
+	{ NT_QSL_QST_SIZE, 4096 },
+	{ NT_QUEUES, 128 },
+	{ NT_RAC_RAB_INTERFACES, 3 },
+	{ NT_RAC_RAB_OB_UPDATE, 0 },
+	{ NT_REVISION_ID, 39 },
+	{ NT_RMC_LAG_GROUPS, 1 },
+	{ NT_RMC_PRESENT, 1 },
+	{ NT_ROA_CATEGORIES, 1024 },
+	{ NT_ROA_PRESENT, 0 },
+	{ NT_RPF_MATURING_DEL_DEFAULT, -150 },
+	{ NT_RPF_PRESENT, 0 },
+	{ NT_RPP_PER_PS, 3333 },
+	{ NT_RTX_PRESENT, 0 },
+	{ NT_RX_HOST_BUFFERS, 128 },
+	{ NT_RX_PORTS, 2 },
+	{ NT_RX_PORT_REPLICATE, 0 },
+	{ NT_SLB_PRESENT, 0 },
+	{ NT_SLC_LR_PRESENT, 1 },
+	{ NT_SLC_PRESENT, 0 },
+	{ NT_STA_COLORS, 64 },
+	{ NT_STA_LOAD_AVG_RX, 1 },
+	{ NT_STA_LOAD_AVG_TX, 1 },
+	{ NT_STA_RX_PORTS, 2 },
+	{ NT_TBH_DEBUG_DLN, 1 },
+	{ NT_TBH_PRESENT, 0 },
+	{ NT_TFD_PRESENT, 1 },
+	{ NT_TPE_CATEGORIES, 16 },
+	{ NT_TSM_OST_ONLY, 0 },
+	{ NT_TS_APPEND, 0 },
+	{ NT_TS_INJECT_PRESENT, 0 },
+	{ NT_TX_CPY_PACKET_READERS, 0 },
+	{ NT_TX_CPY_PRESENT, 1 },
+	{ NT_TX_CPY_SIDEBAND_READERS, 7 },
+	{ NT_TX_CPY_VARIANT, 0 },
+	{ NT_TX_CPY_WRITERS, 6 },
+	{ NT_TX_HOST_BUFFERS, 128 },
+	{ NT_TX_INS_OFS_ZERO, 1 },
+	{ NT_TX_INS_PRESENT, 1 },
+	{ NT_TX_MTU_PROFILE_IFR, 16 },
+	{ NT_TX_ON_TIMESTAMP, 1 },
+	{ NT_TX_PORTS, 2 },
+	{ NT_TX_PORT_REPLICATE, 1 },
+	{ NT_TX_RPL_DEPTH, 4096 },
+	{ NT_TX_RPL_EXT_CATEGORIES, 1024 },
+	{ NT_TX_RPL_OFS_ZERO, 1 },
+	{ NT_TX_RPL_PRESENT, 1 },
+	{ NT_TYPE_ID, 200 },
+	{ NT_USE_TRIPLE_SPEED, 0 },
+	{ NT_VERSION_ID, 55 },
+	{ NT_VLI_PRESENT, 0 },
+	{ 0, -1 },	/* END */
+};
+
+nthw_fpga_prod_init_s nthw_fpga_9563_055_039_0000 = {
+	200, 9563, 55, 39, 0, 0, 1713859545, 152, product_parameters, 45, fpga_modules,
+};
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_instances.c b/drivers/net/ntnic/nthw/supported/nthw_fpga_instances.c
new file mode 100644
index 0000000000..ea731ae979
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_instances.c
@@ -0,0 +1,6 @@
+
+
+#include "nthw_fpga_instances.h"
+nthw_fpga_prod_init_s *nthw_fpga_instances[] = { &nthw_fpga_9563_055_039_0000, NULL };
+
+/* EOF */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_instances.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_instances.h
new file mode 100644
index 0000000000..c19b43c19b
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_instances.h
@@ -0,0 +1,7 @@
+
+
+#include "fpga_model.h"
+extern nthw_fpga_prod_init_s *nthw_fpga_instances[];
+extern nthw_fpga_prod_init_s nthw_fpga_9563_055_039_0000;
+
+/* EOF */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h
new file mode 100644
index 0000000000..f2dba47488
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h
@@ -0,0 +1,93 @@
+/*
+ * nthw_fpga_mod_defs.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_MOD_DEFS_H_
+#define _NTHW_FPGA_MOD_DEFS_H_
+
+#define MOD_UNKNOWN (0L)/* Unknown/uninitialized - keep this as the first element */
+#define MOD_CAT (0x30b447c2UL)
+#define MOD_CB (0x97db0a27UL)
+#define MOD_COR (0x4754cf79UL)
+#define MOD_CPY (0x1ddc186fUL)
+#define MOD_CSU (0x3f470787UL)
+#define MOD_DBS (0x80b29727UL)
+#define MOD_DDP (0x4fe1611bUL)
+#define MOD_EPP (0x608ddc79UL)
+#define MOD_EQM (0x1a9081e1UL)
+#define MOD_FHM (0x83d696a0UL)
+#define MOD_FLM (0xe7ba53a4UL)
+#define MOD_GFG (0xfc423807UL)
+#define MOD_GMF (0x68b1d15aUL)
+#define MOD_GPIO_PHY (0xbbe81659UL)
+#define MOD_GPIO_PHY_PORTS (0xea12bddaUL)
+#define MOD_GPIO_SFPP (0x628c8692UL)
+#define MOD_HFU (0x4a70e72UL)
+#define MOD_HIF (0x7815363UL)
+#define MOD_HSH (0x501484bfUL)
+#define MOD_I2CM (0x93bc7780UL)
+#define MOD_IFR (0x9b01f1e6UL)
+#define MOD_IGAM (0xf3b0bfb9UL)
+#define MOD_IIC (0x7629cddbUL)
+#define MOD_INS (0x24df4b78UL)
+#define MOD_IOA (0xce7d0b71UL)
+#define MOD_IPF (0x9d43904cUL)
+#define MOD_KM (0xcfbd9dbeUL)
+#define MOD_MAC (0xb9f9ef0fUL)
+#define MOD_MAC_PCS (0x7abe24c7UL)
+#define MOD_MAC_PCS_XXV (0x3ea7bfeaUL)
+#define MOD_MAC_RX (0x6347b490UL)
+#define MOD_MAC_TFG (0x1a1aac23UL)
+#define MOD_MAC_TX (0x351d1316UL)
+#define MOD_MSK (0xcfd617eeUL)
+#define MOD_PCIE3 (0xfbc48c18UL)
+#define MOD_PCI_RD_TG (0x9ad9eed2UL)
+#define MOD_PCI_TA (0xfb431997UL)
+#define MOD_PCI_WR_TG (0x274b69e1UL)
+#define MOD_PCS (0x8286adcaUL)
+#define MOD_PCS100 (0xa03da74fUL)
+#define MOD_PDB (0xa7771bffUL)
+#define MOD_PDI (0x30a5c277UL)
+#define MOD_PHY_TILE (0x4e0aef6eUL)
+#define MOD_QSL (0x448ed859UL)
+#define MOD_QSPI (0x29862c6cUL)
+#define MOD_R2DRP (0x8b673fa6UL)
+#define MOD_RAC (0xae830b42UL)
+#define MOD_RFD (0x7fa60826UL)
+#define MOD_RMC (0x236444eUL)
+#define MOD_ROA (0xde0e47e0UL)
+#define MOD_RPF (0x8d30dcddUL)
+#define MOD_RPL (0x6de535c3UL)
+#define MOD_RPP_LR (0xba7f945cUL)
+#define MOD_RST9563 (0x385d6d1dUL)
+#define MOD_SDC (0xd2369530UL)
+#define MOD_SLC (0x1aef1f38UL)
+#define MOD_SLC_LR (0x969fc50bUL)
+#define MOD_SPIM (0x1da437bfUL)
+#define MOD_SPIS (0xe7ab0adcUL)
+#define MOD_STA (0x76fae64dUL)
+#define MOD_TEMPMON (0x2f77020dUL)
+#define MOD_TINT (0xb8aea9feUL)
+#define MOD_TSM (0x35422a24UL)
+#define MOD_TX_CPY (0x60acf217UL)
+#define MOD_TX_CSI (0x5636b1b0UL)
+#define MOD_TX_CSO (0xbf551485UL)
+#define MOD_TX_INS (0x59afa100UL)
+#define MOD_TX_RPL (0x1095dfbbUL)
+#define MOD_IDX_COUNT (69)
+
+/* aliases - only aliases go below this point */
+#define MOD_MAC10 (MOD_MAC10G)	/* alias */
+
+#endif	/* _NTHW_FPGA_MOD_DEFS_H_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_str_map.c b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_str_map.c
new file mode 100644
index 0000000000..51e5cf4649
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_str_map.c
@@ -0,0 +1,78 @@
+
+
+#include "nthw_fpga_mod_str_map.h"
+const struct nthw_fpga_mod_str_s sa_nthw_fpga_mod_str_map[] = { { MOD_CAT, "CAT" },
+	{ MOD_CB, "CB" },
+	{ MOD_COR, "COR" },
+	{ MOD_CPY, "CPY" },
+	{ MOD_CSU, "CSU" },
+	{ MOD_DBS, "DBS" },
+	{ MOD_DDP, "DDP" },
+	{ MOD_EPP, "EPP" },
+	{ MOD_EQM, "EQM" },
+	{ MOD_FHM, "FHM" },
+	{ MOD_FLM, "FLM" },
+	{ MOD_GFG, "GFG" },
+	{ MOD_GMF, "GMF" },
+	{ MOD_GPIO_PHY, "GPIO_PHY" },
+	{
+		MOD_GPIO_PHY_PORTS,
+		"GPIO_PHY_PORTS"
+	},
+	{ MOD_GPIO_SFPP, "GPIO_SFPP" },
+	{ MOD_HFU, "HFU" },
+	{ MOD_HIF, "HIF" },
+	{ MOD_HSH, "HSH" },
+	{ MOD_I2CM, "I2CM" },
+	{ MOD_IFR, "IFR" },
+	{ MOD_IGAM, "IGAM" },
+	{ MOD_IIC, "IIC" },
+	{ MOD_INS, "INS" },
+	{ MOD_IOA, "IOA" },
+	{ MOD_IPF, "IPF" },
+	{ MOD_KM, "KM" },
+	{ MOD_MAC, "MAC" },
+	{ MOD_MAC_PCS, "MAC_PCS" },
+	{ MOD_MAC_PCS_XXV, "MAC_PCS_XXV" },
+	{ MOD_MAC_RX, "MAC_RX" },
+	{ MOD_MAC_TFG, "MAC_TFG" },
+	{ MOD_MAC_TX, "MAC_TX" },
+	{ MOD_MSK, "MSK" },
+	{ MOD_PCIE3, "PCIE3" },
+	{ MOD_PCI_RD_TG, "PCI_RD_TG" },
+	{ MOD_PCI_TA, "PCI_TA" },
+	{ MOD_PCI_WR_TG, "PCI_WR_TG" },
+	{ MOD_PCS, "PCS" },
+	{ MOD_PCS100, "PCS100" },
+	{ MOD_PDB, "PDB" },
+	{ MOD_PDI, "PDI" },
+	{ MOD_PHY_TILE, "PHY_TILE" },
+	{ MOD_QSL, "QSL" },
+	{ MOD_QSPI, "QSPI" },
+	{ MOD_R2DRP, "R2DRP" },
+	{ MOD_RAC, "RAC" },
+	{ MOD_RFD, "RFD" },
+	{ MOD_RMC, "RMC" },
+	{ MOD_ROA, "ROA" },
+	{ MOD_RPF, "RPF" },
+	{ MOD_RPL, "RPL" },
+	{ MOD_RPP_LR, "RPP_LR" },
+	{ MOD_RST9563, "RST9563" },
+	{ MOD_SDC, "SDC" },
+	{ MOD_SLC, "SLC" },
+	{ MOD_SLC_LR, "SLC_LR" },
+	{ MOD_SPIM, "SPIM" },
+	{ MOD_SPIS, "SPIS" },
+	{ MOD_STA, "STA" },
+	{ MOD_TEMPMON, "TEMPMON" },
+	{ MOD_TINT, "TINT" },
+	{ MOD_TSM, "TSM" },
+	{ MOD_TX_CPY, "TX_CPY" },
+	{ MOD_TX_CSI, "TX_CSI" },
+	{ MOD_TX_CSO, "TX_CSO" },
+	{ MOD_TX_INS, "TX_INS" },
+	{ MOD_TX_RPL, "TX_RPL" },
+	{ 0UL, NULL }
+};
+
+/* EOF */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_str_map.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_str_map.h
new file mode 100644
index 0000000000..6bebe56329
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_str_map.h
@@ -0,0 +1,11 @@
+
+
+#include "nthw_fpga_mod_defs.h"
+#include "fpga_model.h"
+struct nthw_fpga_mod_str_s {
+	const nthw_id_t a;
+	const char *b;
+};
+extern const struct nthw_fpga_mod_str_s sa_nthw_fpga_mod_str_map[];
+
+/* EOF */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_param_defs.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_param_defs.h
new file mode 100644
index 0000000000..a51d8b3888
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_param_defs.h
@@ -0,0 +1,232 @@
+/*
+ * nthw_fpga_param_defs.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_PARAM_DEFS_
+#define _NTHW_FPGA_PARAM_DEFS_
+
+#define NTHW_PARAM_UNKNOWN (0UL)
+#define NT_BUILD_NUMBER (0x489b50fbUL)
+#define NT_BUILD_TIME (0x6e66771fUL)
+#define NT_CATEGORIES (0xfdbcebdcUL)
+#define NT_CAT_CCT_SIZE (0x3a505ddaUL)
+#define NT_CAT_CTE_SIZE (0x50a32ea4UL)
+#define NT_CAT_CTS_SIZE (0x852ccf22UL)
+#define NT_CAT_DCT_PRESENT (0x898c5638UL)
+#define NT_CAT_DCT_SIZE (0x309554c3UL)
+#define NT_CAT_END_OFS_SUPPORT (0x925f11d9UL)
+#define NT_CAT_FPC (0x417fd17bUL)
+#define NT_CAT_FTE_SIZE (0x184320c0UL)
+#define NT_CAT_FUNCS (0x6af66e16UL)
+#define NT_CAT_KCC_BANKS (0x426534f3UL)
+#define NT_CAT_KCC_PRESENT (0xd2d58d46UL)
+#define NT_CAT_KCC_SIZE (0xf766744cUL)
+#define NT_CAT_KCE_SIZE (0x213f9751UL)
+#define NT_CAT_KM_IF_CNT (0x8c934524UL)
+#define NT_CAT_KM_IF_M0 (0x666dd699UL)
+#define NT_CAT_KM_IF_M1 (0x116ae60fUL)
+#define NT_CAT_N_CMP (0x3a692ad4UL)
+#define NT_CAT_N_EXT (0xe3c746bUL)
+#define NT_CAT_N_LEN (0x3e3da82UL)
+#define NT_CAT_RCK_SIZE (0x78c1dc21UL)
+#define NT_CAT_VALUES (0xec523dbbUL)
+#define NT_CB_DEBUG (0xa0bccd31UL)
+#define NT_COR_CATEGORIES (0x7392b58dUL)
+#define NT_COR_PRESENT (0xbe0d1fdeUL)
+#define NT_CPY_MASK_MEM (0x24f85e48UL)
+#define NT_CSU_PRESENT (0xe7fe1371UL)
+#define NT_DBS_PRESENT (0x75b395aeUL)
+#define NT_DBS_RX_QUEUES (0x927069fUL)
+#define NT_DBS_TX_PORTS (0xae2d6250UL)
+#define NT_DBS_TX_QUEUES (0x7a3d7f15UL)
+#define NT_DDP_PRESENT (0x4120d92cUL)
+#define NT_DDP_TBL_DEPTH (0xf52e011UL)
+#define NT_EMI_SPLIT_STEPS (0xe4b3210fUL)
+#define NT_EOF_TIMESTAMP_ONLY (0xe476891bUL)
+#define NT_EPP_CATEGORIES (0xf41c134bUL)
+#define NT_EXT_MEM_NUM (0x43a48169UL)
+#define NT_EXT_MEM_SINGLE_SIZE_GB (0x1817e71eUL)
+#define NT_FLM_CACHE (0x414157e4UL)
+#define NT_FLM_CATEGORIES (0x3477c5a3UL)
+#define NT_FLM_ENTRY_SIZE (0x9ca7f0b6UL)
+#define NT_FLM_LOAD_APS_MAX (0xe4d4f4edUL)
+#define NT_FLM_LOAD_LPS_MAX (0x8503952dUL)
+#define NT_FLM_PRESENT (0x5714853fUL)
+#define NT_FLM_PRIOS (0x92afe487UL)
+#define NT_FLM_PST_PROFILES (0xf4a0d627UL)
+#define NT_FLM_SCRUB_PROFILES (0x6b6f6b21UL)
+#define NT_FLM_SIZE_MB (0x5667a5deUL)
+#define NT_FLM_STATEFUL (0xc8bf17a8UL)
+#define NT_FLM_VARIANT (0x5beb9485UL)
+#define NT_GFG_PRESENT (0x149640a8UL)
+#define NT_GFG_TX_LIVE_RECONFIG_SUPPORT (0x7b5ad1e0UL)
+#define NT_GMF_FCS_PRESENT (0xc15365efUL)
+#define NT_GMF_IFG_SPEED_DIV (0xc06cdcbdUL)
+#define NT_GMF_IFG_SPEED_DIV100G (0x43e1fb80UL)
+#define NT_GMF_IFG_SPEED_DIV100M (0xa334129eUL)
+#define NT_GMF_IFG_SPEED_DIV10G (0x49197e96UL)
+#define NT_GMF_IFG_SPEED_DIV1G (0xb1324f18UL)
+#define NT_GMF_IFG_SPEED_DIV2 (0xafc51de0UL)
+#define NT_GMF_IFG_SPEED_DIV25G (0x3628348aUL)
+#define NT_GMF_IFG_SPEED_DIV3 (0xd8c22d76UL)
+#define NT_GMF_IFG_SPEED_DIV4 (0x46a6b8d5UL)
+#define NT_GMF_IFG_SPEED_DIV40G (0x4fd2bc7dUL)
+#define NT_GMF_IFG_SPEED_DIV50G (0x4e10d64aUL)
+#define NT_GMF_IFG_SPEED_MUL (0xd4a84315UL)
+#define NT_GMF_IFG_SPEED_MUL100G (0x883df390UL)
+#define NT_GMF_IFG_SPEED_MUL100M (0x68e81a8eUL)
+#define NT_GMF_IFG_SPEED_MUL10G (0xf4a2e226UL)
+#define NT_GMF_IFG_SPEED_MUL1G (0xb75ce3e8UL)
+#define NT_GMF_IFG_SPEED_MUL2 (0x77dcf2a5UL)
+#define NT_GMF_IFG_SPEED_MUL25G (0x8b93a83aUL)
+#define NT_GMF_IFG_SPEED_MUL3 (0xdbc233UL)
+#define NT_GMF_IFG_SPEED_MUL4 (0x9ebf5790UL)
+#define NT_GMF_IFG_SPEED_MUL40G (0xf26920cdUL)
+#define NT_GMF_IFG_SPEED_MUL50G (0xf3ab4afaUL)
+#define NT_GROUP_ID (0x113978c5UL)
+#define NT_HFU_PRESENT (0x558de99UL)
+#define NT_HIF_MSIX_BAR (0xc10014e9UL)
+#define NT_HIF_MSIX_PBA_OFS (0x900307fbUL)
+#define NT_HIF_MSIX_PRESENT (0x77a98665UL)
+#define NT_HIF_MSIX_TBL_OFS (0x9cdce759UL)
+#define NT_HIF_MSIX_TBL_SIZE (0x6ce7b76UL)
+#define NT_HIF_PER_PS (0x38c954b1UL)
+#define NT_HIF_SRIOV_PRESENT (0x49f8c203UL)
+#define NT_HIF_VF_OFFSET (0x9fb3c9b0UL)
+#define NT_HSH_CATEGORIES (0xf43894dcUL)
+#define NT_HSH_TOEPLITZ (0x603f96a3UL)
+#define NT_HST_CATEGORIES (0xfd2a34a1UL)
+#define NT_HST_PRESENT (0xd3a48076UL)
+#define NT_IOA_CATEGORIES (0xda23501aUL)
+#define NT_IOA_PRESENT (0xc9ef39eeUL)
+#define NT_IPF_PRESENT (0x7b2b8e42UL)
+#define NT_KM_CAM_BANKS (0x3cad3371UL)
+#define NT_KM_CAM_RECORDS (0x24256ab5UL)
+#define NT_KM_CAM_REC_WORDS (0xe8e0ef3UL)
+#define NT_KM_CATEGORIES (0x4d2a4c96UL)
+#define NT_KM_END_OFS_SUPPORT (0x4a90ff33UL)
+#define NT_KM_EXT_EXTRACTORS (0xf135193cUL)
+#define NT_KM_FLOW_SETS (0x359cddf3UL)
+#define NT_KM_FLOW_TYPES (0xb79ff984UL)
+#define NT_KM_PRESENT (0xb54eaee3UL)
+#define NT_KM_SWX_PRESENT (0x2715aebeUL)
+#define NT_KM_SYNERGY_MATCH (0x935e5b7fUL)
+#define NT_KM_TCAM_BANKS (0x6f6f0894UL)
+#define NT_KM_TCAM_BANK_WIDTH (0x4c5015aeUL)
+#define NT_KM_TCAM_HIT_QUAL (0xd3fb2aafUL)
+#define NT_KM_TCAM_KEYWAY (0x45318c61UL)
+#define NT_KM_WIDE (0x7ba773c4UL)
+#define NT_LR_PRESENT (0x24eb383aUL)
+#define NT_LTX_CATEGORIES (0x9cfff063UL)
+#define NT_MCU_DRAM_SIZE (0xe33d7922UL)
+#define NT_MCU_PRESENT (0x9226b99fUL)
+#define NT_MCU_TYPE (0xce45b840UL)
+#define NT_MDG_DEBUG_FLOW_CONTROL (0x4f199a18UL)
+#define NT_MDG_DEBUG_REG_READ_BACK (0xc674095UL)
+#define NT_MSK_CATEGORIES (0x7052841UL)
+#define NT_MSK_PRESENT (0xd18aa194UL)
+#define NT_NAME (0x224bb693UL)
+#define NT_NFV_OVS_PRODUCT (0xd8223124UL)
+#define NT_NIMS (0xd88c527aUL)
+#define NT_PATCH_NUMBER (0xecd14417UL)
+#define NT_PCI_DEVICE_ID (0x254dede8UL)
+#define NT_PCI_INT_AVR (0x40c50ef1UL)
+#define NT_PCI_INT_EQM (0x85853d1fUL)
+#define NT_PCI_INT_IIC0 (0xbf363717UL)
+#define NT_PCI_INT_IIC1 (0xc8310781UL)
+#define NT_PCI_INT_IIC2 (0x5138563bUL)
+#define NT_PCI_INT_IIC3 (0x263f66adUL)
+#define NT_PCI_INT_IIC4 (0xb85bf30eUL)
+#define NT_PCI_INT_IIC5 (0xcf5cc398UL)
+#define NT_PCI_INT_PORT (0x8facd5e1UL)
+#define NT_PCI_INT_PORT0 (0x2359a11aUL)
+#define NT_PCI_INT_PORT1 (0x545e918cUL)
+#define NT_PCI_INT_PPS (0x7c7c50a6UL)
+#define NT_PCI_INT_QSPI (0x731ce6cbUL)
+#define NT_PCI_INT_SPIM (0x473efd18UL)
+#define NT_PCI_INT_SPIS (0xbd31c07bUL)
+#define NT_PCI_INT_STA (0xe9ef5ab3UL)
+#define NT_PCI_INT_TIMER (0x14ad9f2fUL)
+#define NT_PCI_INT_TINT (0xe2346359UL)
+#define NT_PCI_TA_TG_PRESENT (0x3cc176a0UL)
+#define NT_PCI_VENDOR_ID (0x47eac44fUL)
+#define NT_PDB_CATEGORIES (0x8290fe65UL)
+#define NT_PHY_ANEG_PRESENT (0x626ddda5UL)
+#define NT_PHY_KRFEC_PRESENT (0x8ab2cf25UL)
+#define NT_PHY_PORTS (0x41986112UL)
+#define NT_PHY_PORTS_PER_QUAD (0xf4b396e6UL)
+#define NT_PHY_QUADS (0x17fef021UL)
+#define NT_PHY_RSFEC_PRESENT (0x22852f78UL)
+#define NT_PORTS (0x32e8ff06UL)
+#define NT_PROD_ID_LAYOUT_VERSION (0x42106495UL)
+#define NT_QM_BLOCKS (0xb735e210UL)
+#define NT_QM_CELLS (0x510e07f1UL)
+#define NT_QM_CELL_SIZE (0xbddf0f74UL)
+#define NT_QM_PRESENT (0x85c2bfc2UL)
+#define NT_QSL_CATEGORIES (0x3fda6c8fUL)
+#define NT_QSL_COLOR_SEL_BW (0x549c264dUL)
+#define NT_QSL_QST_SIZE (0x41d03837UL)
+#define NT_QUEUES (0xf8a94e49UL)
+#define NT_RAC_RAB_INTERFACES (0x7b742b2bUL)
+#define NT_RAC_RAB_OB_UPDATE (0x3a44d066UL)
+#define NT_REVISION_ID (0xd212229fUL)
+#define NT_RMC_LAG_GROUPS (0xa7d5b2fbUL)
+#define NT_RMC_PRESENT (0x6e3b82daUL)
+#define NT_ROA_CATEGORIES (0xf3a9579bUL)
+#define NT_ROA_PRESENT (0x44387a61UL)
+#define NT_RPF_MATURING_DEL_DEFAULT (0xd4e7e4d2UL)
+#define NT_RPF_PRESENT (0xf6fccdcdUL)
+#define NT_RPP_PER_PS (0xb2f28916UL)
+#define NT_RTX_PRESENT (0x9b15f454UL)
+#define NT_RX_HOST_BUFFERS (0x9207c413UL)
+#define NT_RX_PORTS (0x3639a86eUL)
+#define NT_RX_PORT_REPLICATE (0xed09d794UL)
+#define NT_SLB_PRESENT (0x570c2267UL)
+#define NT_SLC_LR_PRESENT (0xe600975aUL)
+#define NT_SLC_PRESENT (0x40773624UL)
+#define NT_STA_COLORS (0xe1e90b5bUL)
+#define NT_STA_LOAD_AVG_RX (0x94efbfa1UL)
+#define NT_STA_LOAD_AVG_TX (0xc2b51827UL)
+#define NT_STA_RX_PORTS (0x75da30f9UL)
+#define NT_TBH_DEBUG_DLN (0x1faf2e1dUL)
+#define NT_TBH_PRESENT (0xf5d08dc9UL)
+#define NT_TFD_PRESENT (0x1a0fdea7UL)
+#define NT_TPE_CATEGORIES (0x9b1a54bdUL)
+#define NT_TSM_OST_ONLY (0x4899103aUL)
+#define NT_TS_APPEND (0x4544c692UL)
+#define NT_TS_INJECT_PRESENT (0xb2aa4f0eUL)
+#define NT_TX_CPY_PACKET_READERS (0x37f470f0UL)
+#define NT_TX_CPY_PRESENT (0xe54af81cUL)
+#define NT_TX_CPY_SIDEBAND_READERS (0x52220d68UL)
+#define NT_TX_CPY_VARIANT (0xe9b5e9a6UL)
+#define NT_TX_CPY_WRITERS (0xd9dbd4UL)
+#define NT_TX_HOST_BUFFERS (0xb0fd10e1UL)
+#define NT_TX_INS_OFS_ZERO (0x5510aa2dUL)
+#define NT_TX_INS_PRESENT (0xabac9b5dUL)
+#define NT_TX_MTU_PROFILE_IFR (0x8d313bc2UL)
+#define NT_TX_ON_TIMESTAMP (0x51d7fce0UL)
+#define NT_TX_PORTS (0xf056a1e9UL)
+#define NT_TX_PORT_REPLICATE (0x4a3d609cUL)
+#define NT_TX_RPL_DEPTH (0x61f86eb9UL)
+#define NT_TX_RPL_EXT_CATEGORIES (0x421e973cUL)
+#define NT_TX_RPL_OFS_ZERO (0x2bfd677UL)
+#define NT_TX_RPL_PRESENT (0x6c65e429UL)
+#define NT_TYPE_ID (0xd03446b2UL)
+#define NT_USE_TRIPLE_SPEED (0x54350589UL)
+#define NT_UUID (0xad179833UL)
+#define NT_VERSION (0x92295f02UL)
+#define NT_VERSION_ID (0xb4becc51UL)
+#define NT_VLI_PRESENT (0xa40e10f8UL)
+
+#endif	/* _NTHW_FPGA_PARAM_DEFS_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h
new file mode 100644
index 0000000000..9b24398183
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h
@@ -0,0 +1,94 @@
+/*
+ * nthw_fpga_reg_defs.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_
+#define _NTHW_FPGA_REG_DEFS_
+
+#include "nthw_fpga_reg_defs_cat.h"
+#include "nthw_fpga_reg_defs_cb.h"
+#include "nthw_fpga_reg_defs_cor.h"
+#include "nthw_fpga_reg_defs_cpy.h"
+#include "nthw_fpga_reg_defs_csu.h"
+#include "nthw_fpga_reg_defs_dbs.h"
+#include "nthw_fpga_reg_defs_ddp.h"
+#include "nthw_fpga_reg_defs_epp.h"
+#include "nthw_fpga_reg_defs_eqm.h"
+#include "nthw_fpga_reg_defs_fhm.h"
+#include "nthw_fpga_reg_defs_flm.h"
+#include "nthw_fpga_reg_defs_gfg.h"
+#include "nthw_fpga_reg_defs_gmf.h"
+#include "nthw_fpga_reg_defs_gpio_phy.h"
+#include "nthw_fpga_reg_defs_gpio_phy_ports.h"
+#include "nthw_fpga_reg_defs_gpio_sfpp.h"
+#include "nthw_fpga_reg_defs_hfu.h"
+#include "nthw_fpga_reg_defs_hif.h"
+#include "nthw_fpga_reg_defs_hsh.h"
+#include "nthw_fpga_reg_defs_i2cm.h"
+#include "nthw_fpga_reg_defs_ifr.h"
+#include "nthw_fpga_reg_defs_igam.h"
+#include "nthw_fpga_reg_defs_iic.h"
+#include "nthw_fpga_reg_defs_ins.h"
+#include "nthw_fpga_reg_defs_ioa.h"
+#include "nthw_fpga_reg_defs_ipf.h"
+#include "nthw_fpga_reg_defs_km.h"
+#include "nthw_fpga_reg_defs_mac.h"
+#include "nthw_fpga_reg_defs_mac_pcs.h"
+#include "nthw_fpga_reg_defs_mac_pcs_xxv.h"
+#include "nthw_fpga_reg_defs_mac_rx.h"
+#include "nthw_fpga_reg_defs_mac_tfg.h"
+#include "nthw_fpga_reg_defs_mac_tx.h"
+#include "nthw_fpga_reg_defs_msk.h"
+#include "nthw_fpga_reg_defs_pcie3.h"
+#include "nthw_fpga_reg_defs_pci_rd_tg.h"
+#include "nthw_fpga_reg_defs_pci_ta.h"
+#include "nthw_fpga_reg_defs_pci_wr_tg.h"
+#include "nthw_fpga_reg_defs_pcm_nt400dxx.h"
+#include "nthw_fpga_reg_defs_pcm_nt50b01_01.h"
+#include "nthw_fpga_reg_defs_pcs.h"
+#include "nthw_fpga_reg_defs_pcs100.h"
+#include "nthw_fpga_reg_defs_pdb.h"
+#include "nthw_fpga_reg_defs_pdi.h"
+#include "nthw_fpga_reg_defs_phy_tile.h"
+#include "nthw_fpga_reg_defs_prm_nt400dxx.h"
+#include "nthw_fpga_reg_defs_prm_nt50b01_01.h"
+#include "nthw_fpga_reg_defs_qsl.h"
+#include "nthw_fpga_reg_defs_qspi.h"
+#include "nthw_fpga_reg_defs_r2drp.h"
+#include "nthw_fpga_reg_defs_rac.h"
+#include "nthw_fpga_reg_defs_rfd.h"
+#include "nthw_fpga_reg_defs_rmc.h"
+#include "nthw_fpga_reg_defs_roa.h"
+#include "nthw_fpga_reg_defs_rpf.h"
+#include "nthw_fpga_reg_defs_rpl.h"
+#include "nthw_fpga_reg_defs_rpp_lr.h"
+#include "nthw_fpga_reg_defs_rst9563.h"
+#include "nthw_fpga_reg_defs_sdc.h"
+#include "nthw_fpga_reg_defs_slc.h"
+#include "nthw_fpga_reg_defs_slc_lr.h"
+#include "nthw_fpga_reg_defs_spim.h"
+#include "nthw_fpga_reg_defs_spis.h"
+#include "nthw_fpga_reg_defs_sta.h"
+#include "nthw_fpga_reg_defs_tempmon.h"
+#include "nthw_fpga_reg_defs_tint.h"
+#include "nthw_fpga_reg_defs_tsm.h"
+#include "nthw_fpga_reg_defs_tx_cpy.h"
+#include "nthw_fpga_reg_defs_tx_csi.h"
+#include "nthw_fpga_reg_defs_tx_cso.h"
+#include "nthw_fpga_reg_defs_tx_ins.h"
+#include "nthw_fpga_reg_defs_tx_rpl.h"
+
+/* aliases */
+
+#endif	/* NTHW_FPGA_REG_DEFS_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_cat.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_cat.h
new file mode 100644
index 0000000000..1748a6cbb5
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_cat.h
@@ -0,0 +1,237 @@
+/*
+ * nthw_fpga_reg_defs_cat.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_CAT_
+#define _NTHW_FPGA_REG_DEFS_CAT_
+
+/* CAT */
+#define NTHW_MOD_CAT (0x30b447c2UL)
+#define CAT_CCT_CTRL (0x234d3a78UL)
+#define CAT_CCT_CTRL_ADR (0x6146f230UL)
+#define CAT_CCT_CTRL_CNT (0x714e6be1UL)
+#define CAT_CCT_DATA (0x8c9cb861UL)
+#define CAT_CCT_DATA_COLOR (0x27e29b73UL)
+#define CAT_CCT_DATA_KM (0x4ac2435fUL)
+#define CAT_CFN_CTRL (0xd3383422UL)
+#define CAT_CFN_CTRL_ADR (0x209d4f53UL)
+#define CAT_CFN_CTRL_CNT (0x3095d682UL)
+#define CAT_CFN_DATA (0x7ce9b63bUL)
+#define CAT_CFN_DATA_ENABLE (0xd2ae88e2UL)
+#define CAT_CFN_DATA_ERR_CV (0x22ca6722UL)
+#define CAT_CFN_DATA_ERR_FCS (0xc45c40bfUL)
+#define CAT_CFN_DATA_ERR_INV (0xac48d40UL)
+#define CAT_CFN_DATA_ERR_L3_CS (0x55fb7895UL)
+#define CAT_CFN_DATA_ERR_L4_CS (0xc82c402cUL)
+#define CAT_CFN_DATA_ERR_TNL_L3_CS (0x51e668edUL)
+#define CAT_CFN_DATA_ERR_TNL_L4_CS (0xcc315054UL)
+#define CAT_CFN_DATA_ERR_TNL_TTL_EXP (0x948d9686UL)
+#define CAT_CFN_DATA_ERR_TRUNC (0x237fdf4fUL)
+#define CAT_CFN_DATA_ERR_TTL_EXP (0x6edc7101UL)
+#define CAT_CFN_DATA_FLM_OR (0xd82cf0b3UL)
+#define CAT_CFN_DATA_INV (0xc2e6afa4UL)
+#define CAT_CFN_DATA_KM0_OR (0xc087b29cUL)
+#define CAT_CFN_DATA_KM1_OR (0x783bd5f9UL)
+#define CAT_CFN_DATA_KM_OR (0x58fbb39eUL)
+#define CAT_CFN_DATA_LC (0x3dfcfb34UL)
+#define CAT_CFN_DATA_LC_INV (0x72af18aUL)
+#define CAT_CFN_DATA_MAC_PORT (0xcd340483UL)
+#define CAT_CFN_DATA_PM_AND_INV (0x3ae1c6afUL)
+#define CAT_CFN_DATA_PM_CMB (0xf06e8f63UL)
+#define CAT_CFN_DATA_PM_CMP (0x3d7fe2bUL)
+#define CAT_CFN_DATA_PM_DCT (0x9f760139UL)
+#define CAT_CFN_DATA_PM_EXT_INV (0x7bc194b8UL)
+#define CAT_CFN_DATA_PM_INV (0xcc0e8d0bUL)
+#define CAT_CFN_DATA_PM_OR_INV (0x7790b2fUL)
+#define CAT_CFN_DATA_PTC_CFP (0x98d6c9edUL)
+#define CAT_CFN_DATA_PTC_FRAG (0x9bb1ab3cUL)
+#define CAT_CFN_DATA_PTC_INV (0xb4fb6306UL)
+#define CAT_CFN_DATA_PTC_IP_PROT (0xfee4889bUL)
+#define CAT_CFN_DATA_PTC_ISL (0xb6f5f660UL)
+#define CAT_CFN_DATA_PTC_L2 (0xdb7388deUL)
+#define CAT_CFN_DATA_PTC_L3 (0xac74b848UL)
+#define CAT_CFN_DATA_PTC_L4 (0x32102debUL)
+#define CAT_CFN_DATA_PTC_MAC (0x59b733feUL)
+#define CAT_CFN_DATA_PTC_MPLS (0xe0405263UL)
+#define CAT_CFN_DATA_PTC_TNL_FRAG (0x76e4a788UL)
+#define CAT_CFN_DATA_PTC_TNL_IP_PROT (0x8b0734cdUL)
+#define CAT_CFN_DATA_PTC_TNL_L2 (0xec64285eUL)
+#define CAT_CFN_DATA_PTC_TNL_L3 (0x9b6318c8UL)
+#define CAT_CFN_DATA_PTC_TNL_L4 (0x5078d6bUL)
+#define CAT_CFN_DATA_PTC_TNL_MPLS (0xd155ed7UL)
+#define CAT_CFN_DATA_PTC_TNL_VLAN (0x4999c6c9UL)
+#define CAT_CFN_DATA_PTC_TUNNEL (0x2ac66873UL)
+#define CAT_CFN_DATA_PTC_VLAN (0xa4ccca7dUL)
+#define CAT_CFN_DATA_PTC_VNTAG (0x23d64f2aUL)
+#define CAT_COT_CTRL (0xe4ed500cUL)
+#define CAT_COT_CTRL_ADR (0x6b5c60f7UL)
+#define CAT_COT_CTRL_CNT (0x7b54f926UL)
+#define CAT_COT_DATA (0x4b3cd215UL)
+#define CAT_COT_DATA_COLOR (0xbd582288UL)
+#define CAT_COT_DATA_KM (0x50fea3d1UL)
+#define CAT_COT_DATA_NFV_SB (0x2219c864UL)
+#define CAT_CTE_CTRL (0x49be4906UL)
+#define CAT_CTE_CTRL_ADR (0x2ee7c9aeUL)
+#define CAT_CTE_CTRL_CNT (0x3eef507fUL)
+#define CAT_CTE_DATA (0xe66fcb1fUL)
+#define CAT_CTE_DATA_COL_ENABLE (0xa9ca226bUL)
+#define CAT_CTE_DATA_COR_ENABLE (0xc0fb0172UL)
+#define CAT_CTE_DATA_EPP_ENABLE (0xfcb9fbe8UL)
+#define CAT_CTE_DATA_HSH_ENABLE (0x9f946603UL)
+#define CAT_CTE_DATA_HST_ENABLE (0xb4804267UL)
+#define CAT_CTE_DATA_IPF_ENABLE (0x5c5123caUL)
+#define CAT_CTE_DATA_MSK_ENABLE (0xf732aaa4UL)
+#define CAT_CTE_DATA_PDB_ENABLE (0xf28c946fUL)
+#define CAT_CTE_DATA_QSL_ENABLE (0xc065c2dbUL)
+#define CAT_CTE_DATA_SLC_ENABLE (0x6ec98deaUL)
+#define CAT_CTE_DATA_TPE_ENABLE (0x8e2e71UL)
+#define CAT_CTE_DATA_TX_INS_ENABLE (0x585922e3UL)
+#define CAT_CTE_DATA_TX_RPL_ENABLE (0x468ee298UL)
+#define CAT_CTS_CTRL (0x9c31a880UL)
+#define CAT_CTS_CTRL_ADR (0x4573801UL)
+#define CAT_CTS_CTRL_CNT (0x145fa1d0UL)
+#define CAT_CTS_DATA (0x33e02a99UL)
+#define CAT_CTS_DATA_CAT_A (0xa698040aUL)
+#define CAT_CTS_DATA_CAT_B (0x3f9155b0UL)
+#define CAT_DCT_CTRL (0x29883361UL)
+#define CAT_DCT_CTRL_ADR (0x15de1bbfUL)
+#define CAT_DCT_CTRL_CNT (0x5d6826eUL)
+#define CAT_DCT_DATA (0x8659b178UL)
+#define CAT_DCT_DATA_RES (0x74489a9dUL)
+#define CAT_DCT_SEL (0xeb603410UL)
+#define CAT_DCT_SEL_LU (0x60e126beUL)
+#define CAT_EXO_CTRL (0xe9ea0993UL)
+#define CAT_EXO_CTRL_ADR (0xdce26e40UL)
+#define CAT_EXO_CTRL_CNT (0xcceaf791UL)
+#define CAT_EXO_DATA (0x463b8b8aUL)
+#define CAT_EXO_DATA_DYN (0x20ae0124UL)
+#define CAT_EXO_DATA_OFS (0x82a78c82UL)
+#define CAT_FCE_CTRL (0xa327e522UL)
+#define CAT_FCE_CTRL_ADR (0x31896ff6UL)
+#define CAT_FCE_CTRL_CNT (0x2181f627UL)
+#define CAT_FCE_DATA (0xcf6673bUL)
+#define CAT_FCE_DATA_ENABLE (0x8243e7a7UL)
+#define CAT_FCS_CTRL (0x76a804a4UL)
+#define CAT_FCS_CTRL_ADR (0x1b399e59UL)
+#define CAT_FCS_CTRL_CNT (0xb310788UL)
+#define CAT_FCS_DATA (0xd97986bdUL)
+#define CAT_FCS_DATA_CATEGORY (0x69d964f3UL)
+#define CAT_FTE0_CTRL (0x4f655742UL)
+#define CAT_FTE0_CTRL_ADR (0xa786315fUL)
+#define CAT_FTE0_CTRL_CNT (0xb78ea88eUL)
+#define CAT_FTE0_DATA (0xe0b4d55bUL)
+#define CAT_FTE0_DATA_ENABLE (0xe06dec95UL)
+#define CAT_FTE1_CTRL (0x843984e7UL)
+#define CAT_FTE1_CTRL_ADR (0x48445a61UL)
+#define CAT_FTE1_CTRL_CNT (0x584cc3b0UL)
+#define CAT_FTE1_DATA (0x2be806feUL)
+#define CAT_FTE1_DATA_ENABLE (0x3dfb3510UL)
+#define CAT_FTE_CTRL (0x15e4762UL)
+#define CAT_FTE_CTRL_ADR (0xb644bebeUL)
+#define CAT_FTE_CTRL_CNT (0xa64c276fUL)
+#define CAT_FTE_DATA (0xae8fc57bUL)
+#define CAT_FTE_DATA_ENABLE (0x813c710bUL)
+#define CAT_FTE_FLM_CTRL (0x4a63f99eUL)
+#define CAT_FTE_FLM_CTRL_ADR (0x3ed2141dUL)
+#define CAT_FTE_FLM_CTRL_CNT (0x2eda8dccUL)
+#define CAT_FTE_FLM_DATA (0xe5b27b87UL)
+#define CAT_FTE_FLM_DATA_ENABLE (0x1786f0a8UL)
+#define CAT_JOIN (0xf643707UL)
+#define CAT_JOIN_J1 (0x494d06b2UL)
+#define CAT_JOIN_J2 (0xd0445708UL)
+#define CAT_KCC (0x26068f04UL)
+#define CAT_KCC_CTRL (0xee7b13eeUL)
+#define CAT_KCC_CTRL_ADR (0xa2381e5fUL)
+#define CAT_KCC_CTRL_CNT (0xb230878eUL)
+#define CAT_KCC_DATA (0x41aa91f7UL)
+#define CAT_KCC_DATA_CATEGORY (0x3f0558aeUL)
+#define CAT_KCC_DATA_ID (0x734a5784UL)
+#define CAT_KCC_DATA_KEY (0x308cee9cUL)
+#define CAT_KCE0_CTRL (0xc8548827UL)
+#define CAT_KCE0_CTRL_ADR (0x982a5552UL)
+#define CAT_KCE0_CTRL_CNT (0x8822cc83UL)
+#define CAT_KCE0_DATA (0x67850a3eUL)
+#define CAT_KCE0_DATA_ENABLE (0x36443e99UL)
+#define CAT_KCE1_CTRL (0x3085b82UL)
+#define CAT_KCE1_CTRL_ADR (0x77e83e6cUL)
+#define CAT_KCE1_CTRL_CNT (0x67e0a7bdUL)
+#define CAT_KCE1_DATA (0xacd9d99bUL)
+#define CAT_KCE1_DATA_ENABLE (0xebd2e71cUL)
+#define CAT_KCE_CTRL (0x3822f0f3UL)
+#define CAT_KCE_CTRL_ADR (0xaf266e18UL)
+#define CAT_KCE_CTRL_CNT (0xbf2ef7c9UL)
+#define CAT_KCE_DATA (0x97f372eaUL)
+#define CAT_KCE_DATA_ENABLE (0x7e4d95abUL)
+#define CAT_KCS0_CTRL (0xcc5a21d3UL)
+#define CAT_KCS0_CTRL_ADR (0xde695bdaUL)
+#define CAT_KCS0_CTRL_CNT (0xce61c20bUL)
+#define CAT_KCS0_DATA (0x638ba3caUL)
+#define CAT_KCS0_DATA_CATEGORY (0x43dbd3eUL)
+#define CAT_KCS1_CTRL (0x706f276UL)
+#define CAT_KCS1_CTRL_ADR (0x31ab30e4UL)
+#define CAT_KCS1_CTRL_CNT (0x21a3a935UL)
+#define CAT_KCS1_DATA (0xa8d7706fUL)
+#define CAT_KCS1_DATA_CATEGORY (0xbdc666d6UL)
+#define CAT_KCS_CTRL (0xedad1175UL)
+#define CAT_KCS_CTRL_ADR (0x85969fb7UL)
+#define CAT_KCS_CTRL_CNT (0x959e0666UL)
+#define CAT_KCS_DATA (0x427c936cUL)
+#define CAT_KCS_DATA_CATEGORY (0x7b67c7e1UL)
+#define CAT_LEN_CTRL (0x3bf03c13UL)
+#define CAT_LEN_CTRL_ADR (0xcbebb623UL)
+#define CAT_LEN_CTRL_CNT (0xdbe32ff2UL)
+#define CAT_LEN_DATA (0x9421be0aUL)
+#define CAT_LEN_DATA_DYN1 (0x6b539c5dUL)
+#define CAT_LEN_DATA_DYN2 (0xf25acde7UL)
+#define CAT_LEN_DATA_INV (0x299056d4UL)
+#define CAT_LEN_DATA_LOWER (0x5f70c60fUL)
+#define CAT_LEN_DATA_UPPER (0x3fb562b0UL)
+#define CAT_RCK_CTRL (0x61dcbb83UL)
+#define CAT_RCK_CTRL_ADR (0x205e89c6UL)
+#define CAT_RCK_CTRL_CNT (0x30561017UL)
+#define CAT_RCK_DATA (0xce0d399aUL)
+#define CAT_RCK_DATA_CM0U (0xc643fdb9UL)
+#define CAT_RCK_DATA_CM1U (0xdf58ccf8UL)
+#define CAT_RCK_DATA_CM2U (0xf4759f3bUL)
+#define CAT_RCK_DATA_CM3U (0xed6eae7aUL)
+#define CAT_RCK_DATA_CM4U (0xa22f38bdUL)
+#define CAT_RCK_DATA_CM5U (0xbb3409fcUL)
+#define CAT_RCK_DATA_CM6U (0x90195a3fUL)
+#define CAT_RCK_DATA_CM7U (0x89026b7eUL)
+#define CAT_RCK_DATA_CML0 (0x78115e94UL)
+#define CAT_RCK_DATA_CML1 (0xf166e02UL)
+#define CAT_RCK_DATA_CML2 (0x961f3fb8UL)
+#define CAT_RCK_DATA_CML3 (0xe1180f2eUL)
+#define CAT_RCK_DATA_CML4 (0x7f7c9a8dUL)
+#define CAT_RCK_DATA_CML5 (0x87baa1bUL)
+#define CAT_RCK_DATA_CML6 (0x9172fba1UL)
+#define CAT_RCK_DATA_CML7 (0xe675cb37UL)
+#define CAT_RCK_DATA_SEL0 (0x261b58b3UL)
+#define CAT_RCK_DATA_SEL1 (0x511c6825UL)
+#define CAT_RCK_DATA_SEL2 (0xc815399fUL)
+#define CAT_RCK_DATA_SEL3 (0xbf120909UL)
+#define CAT_RCK_DATA_SEL4 (0x21769caaUL)
+#define CAT_RCK_DATA_SEL5 (0x5671ac3cUL)
+#define CAT_RCK_DATA_SEL6 (0xcf78fd86UL)
+#define CAT_RCK_DATA_SEL7 (0xb87fcd10UL)
+#define CAT_RCK_DATA_SEU0 (0xbd1bf1abUL)
+#define CAT_RCK_DATA_SEU1 (0xca1cc13dUL)
+#define CAT_RCK_DATA_SEU2 (0x53159087UL)
+#define CAT_RCK_DATA_SEU3 (0x2412a011UL)
+#define CAT_RCK_DATA_SEU4 (0xba7635b2UL)
+#define CAT_RCK_DATA_SEU5 (0xcd710524UL)
+#define CAT_RCK_DATA_SEU6 (0x5478549eUL)
+#define CAT_RCK_DATA_SEU7 (0x237f6408UL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_CAT_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_cb.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_cb.h
new file mode 100644
index 0000000000..6389754e68
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_cb.h
@@ -0,0 +1,73 @@
+/*
+ * nthw_fpga_reg_defs_cb.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_CB_
+#define _NTHW_FPGA_REG_DEFS_CB_
+
+/* CB */
+#define NTHW_MOD_CB (0x97db0a27UL)
+#define CB_CTRL (0xea0f0d6UL)
+#define CB_CTRL_BP (0x2fd8c552UL)
+#define CB_CTRL_BYPASS (0xe1a5ba2dUL)
+#define CB_CTRL_ENABLE (0xfd0df46bUL)
+#define CB_CTRL_QMA (0xb79f07a3UL)
+#define CB_CTRL_QME (0xb0f2c3baUL)
+#define CB_DBG_BP (0x92018b7UL)
+#define CB_DBG_BP_CNT (0x6f41db03UL)
+#define CB_DBG_DQ (0x287d8fa7UL)
+#define CB_DBG_DQ_MAX (0xc86c40UL)
+#define CB_DBG_EGS_QUEUE (0x98831815UL)
+#define CB_DBG_EGS_QUEUE_ADD (0x6edd6af5UL)
+#define CB_DBG_EGS_QUEUE_AND (0x9432827fUL)
+#define CB_DBG_FREE1200 (0x3ca31ccUL)
+#define CB_DBG_FREE1200_CNT (0xa0a77389UL)
+#define CB_DBG_FREE1800 (0xe5db41aUL)
+#define CB_DBG_FREE1800_CNT (0x4d72cc7UL)
+#define CB_DBG_FREE600 (0x44c0c493UL)
+#define CB_DBG_FREE600_CNT (0x9291e1ffUL)
+#define CB_DBG_H16 (0x39c5a313UL)
+#define CB_DBG_H16_CNT (0x619373a5UL)
+#define CB_DBG_H32 (0xc9e0588UL)
+#define CB_DBG_H32_CNT (0xd9db746eUL)
+#define CB_DBG_H64 (0x988a54f8UL)
+#define CB_DBG_H64_CNT (0x656107dUL)
+#define CB_DBG_HAVE (0x613fdd18UL)
+#define CB_DBG_HAVE_CNT (0x631e610fUL)
+#define CB_DBG_IGS_QUEUE (0x7eb7eb01UL)
+#define CB_DBG_IGS_QUEUE_ADD (0xf467d30eUL)
+#define CB_DBG_IGS_QUEUE_AND (0xe883b84UL)
+#define CB_DBG_QM_CELL_CNT (0x72b9e681UL)
+#define CB_DBG_QM_CELL_CNT_CNT (0x620fbb43UL)
+#define CB_DBG_QM_CELL_XOR (0x92b23e64UL)
+#define CB_DBG_QM_CELL_XOR_XOR (0xa3c18d97UL)
+#define CB_QPM_CTRL (0xd4e2d7ecUL)
+#define CB_QPM_CTRL_ADR (0xf81800a9UL)
+#define CB_QPM_CTRL_CNT (0xe8109978UL)
+#define CB_QPM_DATA (0x7b3355f5UL)
+#define CB_QPM_DATA_P (0x537f8197UL)
+#define CB_QUEUE_MAX (0x3edbf10bUL)
+#define CB_QUEUE_MAX_MAX (0x55932199UL)
+#define CB_STATUS (0x4de72da7UL)
+#define CB_STATUS_BP (0xa6c5a817UL)
+#define CB_STATUS_DB (0x3267ed9UL)
+#define CB_STATUS_EMPTY (0xdb77607dUL)
+#define CB_STATUS_IDLE (0xa0322cdUL)
+#define CB_STATUS_OVF (0x904a7f92UL)
+#define CB_TS_RATE (0xea3c6e96UL)
+#define CB_TS_RATE_CNT (0xf8c7e925UL)
+#define CB_TS_SAVE (0x60b66b71UL)
+#define CB_TS_SAVE_MAX (0xfd15355eUL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_CB_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_cor.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_cor.h
new file mode 100644
index 0000000000..e033672590
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_cor.h
@@ -0,0 +1,81 @@
+/*
+ * nthw_fpga_reg_defs_cor.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_COR_
+#define _NTHW_FPGA_REG_DEFS_COR_
+
+/* COR */
+#define NTHW_MOD_COR (0x4754cf79UL)
+#define COR_CTRL (0xa34106eaUL)
+#define COR_CTRL_EN (0x220ce67aUL)
+#define COR_DBG_COR_CNT (0xeb30470fUL)
+#define COR_DBG_COR_CNT_VAL (0x5ab8a0fcUL)
+#define COR_DBG_COR_ID (0x2b214123UL)
+#define COR_DBG_COR_ID_VAL (0x7c6c2d68UL)
+#define COR_DBG_COR_LO (0xc1846ceeUL)
+#define COR_DBG_COR_LO_VAL (0x5b718dcaUL)
+#define COR_DBG_COR_UP (0xd78cc803UL)
+#define COR_DBG_COR_UP_VAL (0x9d18decaUL)
+#define COR_DCEO (0xbb755e8aUL)
+#define COR_DCEO_VAL (0x75ad94beUL)
+#define COR_DCSO (0xa7edeb5dUL)
+#define COR_DCSO_VAL (0xa0227538UL)
+#define COR_DEEO (0xbff82238UL)
+#define COR_DEEO_VAL (0x167da184UL)
+#define COR_DEO (0xc7fcb744UL)
+#define COR_DEO_VAL (0xf6fef8b1UL)
+#define COR_DESO (0xa36097efUL)
+#define COR_DESO_VAL (0xc3f24002UL)
+#define COR_DSEO (0xa753fdfaUL)
+#define COR_DSEO_VAL (0x12730870UL)
+#define COR_DSO (0xdb640293UL)
+#define COR_DSO_VAL (0x23711937UL)
+#define COR_DSSO (0xbbcb482dUL)
+#define COR_DSSO_VAL (0xc7fce9f6UL)
+#define COR_RCP_CTRL (0x57a5129aUL)
+#define COR_RCP_CTRL_ADR (0xeaa1a01aUL)
+#define COR_RCP_CTRL_CNT (0xfaa939cbUL)
+#define COR_RCP_DATA (0xf8749083UL)
+#define COR_RCP_DATA_CBM1 (0x92fe79a8UL)
+#define COR_RCP_DATA_EN (0x14a2ff31UL)
+#define COR_RCP_DATA_END_PROT (0xd9954b3eUL)
+#define COR_RCP_DATA_END_STATIC (0xc6775c54UL)
+#define COR_RCP_DATA_IP_CHK (0xc1aee6c3UL)
+#define COR_RCP_DATA_IP_DSCP (0xfeb87db5UL)
+#define COR_RCP_DATA_IP_DST (0xe0df3629UL)
+#define COR_RCP_DATA_IP_ECN (0x56bdb735UL)
+#define COR_RCP_DATA_IP_FLAGS (0xef2854ecUL)
+#define COR_RCP_DATA_IP_FLOW (0x711a8bdcUL)
+#define COR_RCP_DATA_IP_HOP (0x8df5609UL)
+#define COR_RCP_DATA_IP_IDENT (0xe0636de4UL)
+#define COR_RCP_DATA_IP_NXTHDR (0xee1f8e7bUL)
+#define COR_RCP_DATA_IP_SRC (0x637e375aUL)
+#define COR_RCP_DATA_IP_TC (0x52c0454dUL)
+#define COR_RCP_DATA_IP_TTL (0xa0d49bc8UL)
+#define COR_RCP_DATA_MAX_LEN (0x4c6afabeUL)
+#define COR_RCP_DATA_PROT_OFS1 (0x875455efUL)
+#define COR_RCP_DATA_START_PROT (0xaf6a6510UL)
+#define COR_RCP_DATA_START_STATIC (0x11a62e48UL)
+#define COR_RCP_DATA_STTC_OFS1 (0x3bc9abaUL)
+#define COR_RCP_DATA_TCP_CHK (0xd0c0496UL)
+#define COR_RCP_DATA_TCP_DST (0x2c7dd47cUL)
+#define COR_RCP_DATA_TCP_SEQ (0x59e620d1UL)
+#define COR_RCP_DATA_TCP_SRC (0xafdcd50fUL)
+#define COR_RCP_DATA_TNL (0xe14689b4UL)
+#define COR_RCP_DATA_UDP_CHK (0xb67e3f9aUL)
+#define COR_RCP_DATA_UDP_DST (0x970fef70UL)
+#define COR_RCP_DATA_UDP_SRC (0x14aeee03UL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_COR_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_cpy.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_cpy.h
new file mode 100644
index 0000000000..88b23c3de1
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_cpy.h
@@ -0,0 +1,112 @@
+/*
+ * nthw_fpga_reg_defs_cpy.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_CPY_
+#define _NTHW_FPGA_REG_DEFS_CPY_
+
+/* CPY */
+#define NTHW_MOD_CPY (0x1ddc186fUL)
+#define CPY_PACKET_READER0_CTRL (0x59359b7UL)
+#define CPY_PACKET_READER0_CTRL_ADR (0xc84f1475UL)
+#define CPY_PACKET_READER0_CTRL_CNT (0xd8478da4UL)
+#define CPY_PACKET_READER0_DATA (0xaa42dbaeUL)
+#define CPY_PACKET_READER0_DATA_DYN (0x34037b11UL)
+#define CPY_PACKET_READER0_DATA_OFS (0x960af6b7UL)
+#define CPY_WRITER0_CTRL (0xe9b3268eUL)
+#define CPY_WRITER0_CTRL_ADR (0x26f906c2UL)
+#define CPY_WRITER0_CTRL_CNT (0x36f19f13UL)
+#define CPY_WRITER0_DATA (0x4662a497UL)
+#define CPY_WRITER0_DATA_DYN (0xdab569a6UL)
+#define CPY_WRITER0_DATA_LEN (0x32d16543UL)
+#define CPY_WRITER0_DATA_MASK_POINTER (0x64db2b2dUL)
+#define CPY_WRITER0_DATA_OFS (0x78bce400UL)
+#define CPY_WRITER0_DATA_READER_SELECT (0x63a38cf9UL)
+#define CPY_WRITER0_MASK_CTRL (0xed52c5f9UL)
+#define CPY_WRITER0_MASK_CTRL_ADR (0x3bbdf6aaUL)
+#define CPY_WRITER0_MASK_CTRL_CNT (0x2bb56f7bUL)
+#define CPY_WRITER0_MASK_DATA (0x428347e0UL)
+#define CPY_WRITER0_MASK_DATA_BYTE_MASK (0xd1d0e256UL)
+#define CPY_WRITER1_CTRL (0x22eff52bUL)
+#define CPY_WRITER1_CTRL_ADR (0xc93b6dfcUL)
+#define CPY_WRITER1_CTRL_CNT (0xd933f42dUL)
+#define CPY_WRITER1_DATA (0x8d3e7732UL)
+#define CPY_WRITER1_DATA_DYN (0x35770298UL)
+#define CPY_WRITER1_DATA_LEN (0xdd130e7dUL)
+#define CPY_WRITER1_DATA_MASK_POINTER (0xb339ab75UL)
+#define CPY_WRITER1_DATA_OFS (0x977e8f3eUL)
+#define CPY_WRITER1_DATA_READER_SELECT (0x6c4b7bfUL)
+#define CPY_WRITER1_MASK_CTRL (0x2cdc1a39UL)
+#define CPY_WRITER1_MASK_CTRL_ADR (0x82462d42UL)
+#define CPY_WRITER1_MASK_CTRL_CNT (0x924eb493UL)
+#define CPY_WRITER1_MASK_DATA (0x830d9820UL)
+#define CPY_WRITER1_MASK_DATA_BYTE_MASK (0x4e0a61c8UL)
+#define CPY_WRITER2_CTRL (0xa47b8785UL)
+#define CPY_WRITER2_CTRL_ADR (0x220cd6ffUL)
+#define CPY_WRITER2_CTRL_CNT (0x32044f2eUL)
+#define CPY_WRITER2_DATA (0xbaa059cUL)
+#define CPY_WRITER2_DATA_DYN (0xde40b99bUL)
+#define CPY_WRITER2_DATA_LEN (0x3624b57eUL)
+#define CPY_WRITER2_DATA_MASK_POINTER (0x106f2ddcUL)
+#define CPY_WRITER2_DATA_OFS (0x7c49343dUL)
+#define CPY_WRITER2_DATA_READER_SELECT (0xa96dfa75UL)
+#define CPY_WRITER2_MASK_CTRL (0xb53e7c38UL)
+#define CPY_WRITER2_MASK_CTRL_ADR (0x933b473bUL)
+#define CPY_WRITER2_MASK_CTRL_CNT (0x8333deeaUL)
+#define CPY_WRITER2_MASK_DATA (0x1aeffe21UL)
+#define CPY_WRITER2_MASK_DATA_BYTE_MASK (0x3514e32bUL)
+#define CPY_WRITER3_CTRL (0x6f275420UL)
+#define CPY_WRITER3_CTRL_ADR (0xcdcebdc1UL)
+#define CPY_WRITER3_CTRL_CNT (0xddc62410UL)
+#define CPY_WRITER3_DATA (0xc0f6d639UL)
+#define CPY_WRITER3_DATA_DYN (0x3182d2a5UL)
+#define CPY_WRITER3_DATA_LEN (0xd9e6de40UL)
+#define CPY_WRITER3_DATA_MASK_POINTER (0xc78dad84UL)
+#define CPY_WRITER3_DATA_OFS (0x938b5f03UL)
+#define CPY_WRITER3_DATA_READER_SELECT (0xcc0ac133UL)
+#define CPY_WRITER3_MASK_CTRL (0x74b0a3f8UL)
+#define CPY_WRITER3_MASK_CTRL_ADR (0x2ac09cd3UL)
+#define CPY_WRITER3_MASK_CTRL_CNT (0x3ac80502UL)
+#define CPY_WRITER3_MASK_DATA (0xdb6121e1UL)
+#define CPY_WRITER3_MASK_DATA_BYTE_MASK (0xaace60b5UL)
+#define CPY_WRITER4_CTRL (0x72226498UL)
+#define CPY_WRITER4_CTRL_ADR (0x2f12a6b8UL)
+#define CPY_WRITER4_CTRL_CNT (0x3f1a3f69UL)
+#define CPY_WRITER4_DATA (0xddf3e681UL)
+#define CPY_WRITER4_DATA_DYN (0xd35ec9dcUL)
+#define CPY_WRITER4_DATA_LEN (0x3b3ac539UL)
+#define CPY_WRITER4_DATA_MASK_POINTER (0x8db326cfUL)
+#define CPY_WRITER4_DATA_OFS (0x7157447aUL)
+#define CPY_WRITER4_DATA_READER_SELECT (0x2d4e67a0UL)
+#define CPY_WRITER4_MASK_CTRL (0x5d8bb67bUL)
+#define CPY_WRITER4_MASK_CTRL_ADR (0xb1c193c9UL)
+#define CPY_WRITER4_MASK_CTRL_CNT (0xa1c90a18UL)
+#define CPY_WRITER4_MASK_DATA (0xf25a3462UL)
+#define CPY_WRITER4_MASK_DATA_BYTE_MASK (0xc329e6edUL)
+#define CPY_WRITER5_CTRL (0xb97eb73dUL)
+#define CPY_WRITER5_CTRL_ADR (0xc0d0cd86UL)
+#define CPY_WRITER5_CTRL_CNT (0xd0d85457UL)
+#define CPY_WRITER5_DATA (0x16af3524UL)
+#define CPY_WRITER5_DATA_DYN (0x3c9ca2e2UL)
+#define CPY_WRITER5_DATA_LEN (0xd4f8ae07UL)
+#define CPY_WRITER5_DATA_MASK_POINTER (0x5a51a697UL)
+#define CPY_WRITER5_DATA_OFS (0x9e952f44UL)
+#define CPY_WRITER5_DATA_READER_SELECT (0x48295ce6UL)
+#define CPY_WRITER5_MASK_CTRL (0x9c0569bbUL)
+#define CPY_WRITER5_MASK_CTRL_ADR (0x83a4821UL)
+#define CPY_WRITER5_MASK_CTRL_CNT (0x1832d1f0UL)
+#define CPY_WRITER5_MASK_DATA (0x33d4eba2UL)
+#define CPY_WRITER5_MASK_DATA_BYTE_MASK (0x5cf36573UL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_CPY_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_csu.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_csu.h
new file mode 100644
index 0000000000..eb68ccab33
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_csu.h
@@ -0,0 +1,30 @@
+/*
+ * nthw_fpga_reg_defs_csu.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_CSU_
+#define _NTHW_FPGA_REG_DEFS_CSU_
+
+/* CSU */
+#define NTHW_MOD_CSU (0x3f470787UL)
+#define CSU_RCP_CTRL (0x11955fefUL)
+#define CSU_RCP_CTRL_ADR (0x8efb3c71UL)
+#define CSU_RCP_CTRL_CNT (0x9ef3a5a0UL)
+#define CSU_RCP_DATA (0xbe44ddf6UL)
+#define CSU_RCP_DATA_IL3_CMD (0xdbac8e0dUL)
+#define CSU_RCP_DATA_IL4_CMD (0x698c521dUL)
+#define CSU_RCP_DATA_OL3_CMD (0xb87cbb37UL)
+#define CSU_RCP_DATA_OL4_CMD (0xa5c6727UL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_CSU_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_dbs.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_dbs.h
new file mode 100644
index 0000000000..2ff31fdf4d
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_dbs.h
@@ -0,0 +1,144 @@
+/*
+ * nthw_fpga_reg_defs_dbs.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_DBS_
+#define _NTHW_FPGA_REG_DEFS_DBS_
+
+/* DBS */
+#define NTHW_MOD_DBS (0x80b29727UL)
+#define DBS_RX_AM_CTRL (0x7359feUL)
+#define DBS_RX_AM_CTRL_ADR (0x4704a1UL)
+#define DBS_RX_AM_CTRL_CNT (0x104f9d70UL)
+#define DBS_RX_AM_DATA (0xafa2dbe7UL)
+#define DBS_RX_AM_DATA_ENABLE (0x11658278UL)
+#define DBS_RX_AM_DATA_GPA (0xbf307344UL)
+#define DBS_RX_AM_DATA_HID (0x5f0669eeUL)
+#define DBS_RX_AM_DATA_INT (0xc32857aUL)
+#define DBS_RX_AM_DATA_PCKED (0x7d840fb4UL)
+#define DBS_RX_CONTROL (0xb18b2866UL)
+#define DBS_RX_CONTROL_AME (0x1f9219acUL)
+#define DBS_RX_CONTROL_AMS (0xeb46acfdUL)
+#define DBS_RX_CONTROL_LQ (0xe65f90b2UL)
+#define DBS_RX_CONTROL_QE (0x3e928d3UL)
+#define DBS_RX_CONTROL_UWE (0xb490e8dbUL)
+#define DBS_RX_CONTROL_UWS (0x40445d8aUL)
+#define DBS_RX_DR_CTRL (0xa0cbc617UL)
+#define DBS_RX_DR_CTRL_ADR (0xa7b57286UL)
+#define DBS_RX_DR_CTRL_CNT (0xb7bdeb57UL)
+#define DBS_RX_DR_DATA (0xf1a440eUL)
+#define DBS_RX_DR_DATA_GPA (0x18c20563UL)
+#define DBS_RX_DR_DATA_HDR (0xb98ed4d5UL)
+#define DBS_RX_DR_DATA_HID (0xf8f41fc9UL)
+#define DBS_RX_DR_DATA_PCKED (0x1e27ce2aUL)
+#define DBS_RX_DR_DATA_QS (0xffb980ddUL)
+#define DBS_RX_IDLE (0x93c723bfUL)
+#define DBS_RX_IDLE_BUSY (0x8e043b5bUL)
+#define DBS_RX_IDLE_IDLE (0x9dba27ccUL)
+#define DBS_RX_IDLE_QUEUE (0xbbddab49UL)
+#define DBS_RX_INIT (0x899772deUL)
+#define DBS_RX_INIT_BUSY (0x8576d90aUL)
+#define DBS_RX_INIT_INIT (0x8c9894fcUL)
+#define DBS_RX_INIT_QUEUE (0xa7bab8c9UL)
+#define DBS_RX_INIT_VAL (0x7789b4d8UL)
+#define DBS_RX_INIT_VAL_IDX (0xead0e2beUL)
+#define DBS_RX_INIT_VAL_PTR (0x5330810eUL)
+#define DBS_RX_PTR (0x628ce523UL)
+#define DBS_RX_PTR_PTR (0x7f834481UL)
+#define DBS_RX_PTR_QUEUE (0x4f3fa6d1UL)
+#define DBS_RX_PTR_VALID (0xbcc5ec4dUL)
+#define DBS_RX_UW_CTRL (0x31afc0deUL)
+#define DBS_RX_UW_CTRL_ADR (0x2ee4a2c9UL)
+#define DBS_RX_UW_CTRL_CNT (0x3eec3b18UL)
+#define DBS_RX_UW_DATA (0x9e7e42c7UL)
+#define DBS_RX_UW_DATA_GPA (0x9193d52cUL)
+#define DBS_RX_UW_DATA_HID (0x71a5cf86UL)
+#define DBS_RX_UW_DATA_INT (0x22912312UL)
+#define DBS_RX_UW_DATA_ISTK (0xd469a7ddUL)
+#define DBS_RX_UW_DATA_PCKED (0xef15c665UL)
+#define DBS_RX_UW_DATA_QS (0x7d422f44UL)
+#define DBS_RX_UW_DATA_VEC (0x55cc9b53UL)
+#define DBS_STATUS (0xb5f35220UL)
+#define DBS_STATUS_OK (0xcf09a30fUL)
+#define DBS_TX_AM_CTRL (0xd6d29b9UL)
+#define DBS_TX_AM_CTRL_ADR (0xf8854f17UL)
+#define DBS_TX_AM_CTRL_CNT (0xe88dd6c6UL)
+#define DBS_TX_AM_DATA (0xa2bcaba0UL)
+#define DBS_TX_AM_DATA_ENABLE (0xb6513570UL)
+#define DBS_TX_AM_DATA_GPA (0x47f238f2UL)
+#define DBS_TX_AM_DATA_HID (0xa7c42258UL)
+#define DBS_TX_AM_DATA_INT (0xf4f0ceccUL)
+#define DBS_TX_AM_DATA_PCKED (0x2e156650UL)
+#define DBS_TX_CONTROL (0xbc955821UL)
+#define DBS_TX_CONTROL_AME (0xe750521aUL)
+#define DBS_TX_CONTROL_AMS (0x1384e74bUL)
+#define DBS_TX_CONTROL_LQ (0x46ba4f6fUL)
+#define DBS_TX_CONTROL_QE (0xa30cf70eUL)
+#define DBS_TX_CONTROL_UWE (0x4c52a36dUL)
+#define DBS_TX_CONTROL_UWS (0xb886163cUL)
+#define DBS_TX_DR_CTRL (0xadd5b650UL)
+#define DBS_TX_DR_CTRL_ADR (0x5f773930UL)
+#define DBS_TX_DR_CTRL_CNT (0x4f7fa0e1UL)
+#define DBS_TX_DR_DATA (0x2043449UL)
+#define DBS_TX_DR_DATA_GPA (0xe0004ed5UL)
+#define DBS_TX_DR_DATA_HDR (0x414c9f63UL)
+#define DBS_TX_DR_DATA_HID (0x36547fUL)
+#define DBS_TX_DR_DATA_PCKED (0x4db6a7ceUL)
+#define DBS_TX_DR_DATA_PORT (0xf306968cUL)
+#define DBS_TX_DR_DATA_QS (0x5f5c5f00UL)
+#define DBS_TX_IDLE (0xf0171685UL)
+#define DBS_TX_IDLE_BUSY (0x61399ebbUL)
+#define DBS_TX_IDLE_IDLE (0x7287822cUL)
+#define DBS_TX_IDLE_QUEUE (0x1b387494UL)
+#define DBS_TX_INIT (0xea4747e4UL)
+#define DBS_TX_INIT_BUSY (0x6a4b7ceaUL)
+#define DBS_TX_INIT_INIT (0x63a5311cUL)
+#define DBS_TX_INIT_QUEUE (0x75f6714UL)
+#define DBS_TX_INIT_VAL (0x9f3c7e9bUL)
+#define DBS_TX_INIT_VAL_IDX (0xc82a364cUL)
+#define DBS_TX_INIT_VAL_PTR (0x71ca55fcUL)
+#define DBS_TX_PTR (0xb4d5063eUL)
+#define DBS_TX_PTR_PTR (0x729d34c6UL)
+#define DBS_TX_PTR_QUEUE (0xa0020331UL)
+#define DBS_TX_PTR_VALID (0x53f849adUL)
+#define DBS_TX_QOS_CTRL (0x3b2c3286UL)
+#define DBS_TX_QOS_CTRL_ADR (0x666600acUL)
+#define DBS_TX_QOS_CTRL_CNT (0x766e997dUL)
+#define DBS_TX_QOS_DATA (0x94fdb09fUL)
+#define DBS_TX_QOS_DATA_BS (0x2c394071UL)
+#define DBS_TX_QOS_DATA_EN (0x7eba6fUL)
+#define DBS_TX_QOS_DATA_IR (0xb8caa92cUL)
+#define DBS_TX_QOS_DATA_MUL (0xd7407a67UL)
+#define DBS_TX_QOS_RATE (0xe6e27cc5UL)
+#define DBS_TX_QOS_RATE_DIV (0x8cd07ba3UL)
+#define DBS_TX_QOS_RATE_MUL (0x9814e40bUL)
+#define DBS_TX_QP_CTRL (0xd5fba432UL)
+#define DBS_TX_QP_CTRL_ADR (0x84238184UL)
+#define DBS_TX_QP_CTRL_CNT (0x942b1855UL)
+#define DBS_TX_QP_DATA (0x7a2a262bUL)
+#define DBS_TX_QP_DATA_VPORT (0xda741d67UL)
+#define DBS_TX_UW_CTRL (0x3cb1b099UL)
+#define DBS_TX_UW_CTRL_ADR (0xd626e97fUL)
+#define DBS_TX_UW_CTRL_CNT (0xc62e70aeUL)
+#define DBS_TX_UW_DATA (0x93603280UL)
+#define DBS_TX_UW_DATA_GPA (0x69519e9aUL)
+#define DBS_TX_UW_DATA_HID (0x89678430UL)
+#define DBS_TX_UW_DATA_INO (0x5036a148UL)
+#define DBS_TX_UW_DATA_INT (0xda5368a4UL)
+#define DBS_TX_UW_DATA_ISTK (0xf693732fUL)
+#define DBS_TX_UW_DATA_PCKED (0xbc84af81UL)
+#define DBS_TX_UW_DATA_QS (0xdda7f099UL)
+#define DBS_TX_UW_DATA_VEC (0xad0ed0e5UL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_DBS_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_ddp.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_ddp.h
new file mode 100644
index 0000000000..88ed30f494
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_ddp.h
@@ -0,0 +1,34 @@
+/*
+ * nthw_fpga_reg_defs_ddp.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_DDP_
+#define _NTHW_FPGA_REG_DEFS_DDP_
+
+/* DDP */
+#define NTHW_MOD_DDP (0x4fe1611bUL)
+#define DDP_AGING_CTRL (0x85ef88bbUL)
+#define DDP_AGING_CTRL_AGING_RATE (0x410fda66UL)
+#define DDP_AGING_CTRL_MAX_CNT (0x2d5ac5adUL)
+#define DDP_CTRL (0xe64bfa02UL)
+#define DDP_CTRL_INIT (0x8e86234cUL)
+#define DDP_CTRL_INIT_DONE (0x14a11a6bUL)
+#define DDP_RCP_CTRL (0x4e9ac6cUL)
+#define DDP_RCP_CTRL_ADR (0x28c23a3cUL)
+#define DDP_RCP_CTRL_CNT (0x38caa3edUL)
+#define DDP_RCP_DATA (0xab382e75UL)
+#define DDP_RCP_DATA_EN (0xa0c77e8dUL)
+#define DDP_RCP_DATA_GROUPID (0xc71ed409UL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_DDP_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_epp.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_epp.h
new file mode 100644
index 0000000000..fc181e461b
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_epp.h
@@ -0,0 +1,64 @@
+/*
+ * nthw_fpga_reg_defs_epp.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_EPP_
+#define _NTHW_FPGA_REG_DEFS_EPP_
+
+/* EPP */
+#define NTHW_MOD_EPP (0x608ddc79UL)
+#define EPP_QUEUE_MTU_CTRL (0xcfd3b1a4UL)
+#define EPP_QUEUE_MTU_CTRL_ADR (0xa6da09b7UL)
+#define EPP_QUEUE_MTU_CTRL_CNT (0xb6d29066UL)
+#define EPP_QUEUE_MTU_DATA (0x600233bdUL)
+#define EPP_QUEUE_MTU_DATA_MAX_MTU (0x4e1d70c4UL)
+#define EPP_QUEUE_VPORT_CTRL (0x5daeb386UL)
+#define EPP_QUEUE_VPORT_CTRL_ADR (0x2bf54fbfUL)
+#define EPP_QUEUE_VPORT_CTRL_CNT (0x3bfdd66eUL)
+#define EPP_QUEUE_VPORT_DATA (0xf27f319fUL)
+#define EPP_QUEUE_VPORT_DATA_VPORT (0x9a1ab23eUL)
+#define EPP_RCP_CTRL (0x8163574aUL)
+#define EPP_RCP_CTRL_ADR (0x48b45181UL)
+#define EPP_RCP_CTRL_CNT (0x58bcc850UL)
+#define EPP_RCP_DATA (0x2eb2d553UL)
+#define EPP_RCP_DATA_FIXED_18B_L2_MTU (0xf188c234UL)
+#define EPP_RCP_DATA_QUEUE_MTU_EPP_EN (0x6ff74333UL)
+#define EPP_RCP_DATA_QUEUE_QOS_EPP_EN (0xba9ff77eUL)
+#define EPP_RCP_DATA_SIZE_ADJUST_TXP (0xd4e82cc4UL)
+#define EPP_RCP_DATA_SIZE_ADJUST_VPORT (0x90128d47UL)
+#define EPP_RCP_DATA_TX_MTU_EPP_EN (0x377c3d8bUL)
+#define EPP_RCP_DATA_TX_QOS_EPP_EN (0xe21489c6UL)
+#define EPP_TXP_MTU_CTRL (0x30a7bec7UL)
+#define EPP_TXP_MTU_CTRL_ADR (0xe2444518UL)
+#define EPP_TXP_MTU_CTRL_CNT (0xf24cdcc9UL)
+#define EPP_TXP_MTU_DATA (0x9f763cdeUL)
+#define EPP_TXP_MTU_DATA_MAX_MTU (0xbce62f2eUL)
+#define EPP_TXP_QOS_CTRL (0xa833b18aUL)
+#define EPP_TXP_QOS_CTRL_ADR (0x6b9fd6adUL)
+#define EPP_TXP_QOS_CTRL_CNT (0x7b974f7cUL)
+#define EPP_TXP_QOS_DATA (0x7e23393UL)
+#define EPP_TXP_QOS_DATA_BS (0xb8857ffbUL)
+#define EPP_TXP_QOS_DATA_EN (0x94c285e5UL)
+#define EPP_TXP_QOS_DATA_IR (0x2c7696a6UL)
+#define EPP_TXP_QOS_DATA_IR_FRACTION (0x972b2506UL)
+#define EPP_VPORT_QOS_CTRL (0x24c5b00eUL)
+#define EPP_VPORT_QOS_CTRL_ADR (0xae8e14c6UL)
+#define EPP_VPORT_QOS_CTRL_CNT (0xbe868d17UL)
+#define EPP_VPORT_QOS_DATA (0x8b143217UL)
+#define EPP_VPORT_QOS_DATA_BS (0x137caa43UL)
+#define EPP_VPORT_QOS_DATA_EN (0x3f3b505dUL)
+#define EPP_VPORT_QOS_DATA_IR (0x878f431eUL)
+#define EPP_VPORT_QOS_DATA_IR_FRACTION (0xa857a1dcUL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_EPP_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_eqm.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_eqm.h
new file mode 100644
index 0000000000..5f1fa85001
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_eqm.h
@@ -0,0 +1,45 @@
+/*
+ * nthw_fpga_reg_defs_eqm.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_EQM_
+#define _NTHW_FPGA_REG_DEFS_EQM_
+
+/* EQM */
+#define NTHW_MOD_EQM (0x1a9081e1UL)
+#define EQM_CTRL (0xa04f58b0UL)
+#define EQM_CTRL_DBG_CRC_ERR (0xbe59fcc9UL)
+#define EQM_CTRL_DBG_FORCE_ERR (0x1195289fUL)
+#define EQM_CTRL_DBG_RMT_ERR (0x5fb0906fUL)
+#define EQM_CTRL_DBG_SYNC_ERR (0xf49ef23fUL)
+#define EQM_CTRL_ENABLE (0xe714200fUL)
+#define EQM_CTRL_MODE (0xf3774a36UL)
+#define EQM_CTRL_PP_RST (0x60d53774UL)
+#define EQM_DBG (0x3edaff33UL)
+#define EQM_DBG_FIFO_OF (0x29e8a88aUL)
+#define EQM_DBG_LCL_EGS_QKA_OF (0x3074364UL)
+#define EQM_DBG_LCL_EGS_QLVL_OF (0x47ec3248UL)
+#define EQM_DBG_QBLK_CREDITS (0xcf0f2e3eUL)
+#define EQM_STATUS (0xa64d64b3UL)
+#define EQM_STATUS_LCL_EGS_OF_ERR (0x613933faUL)
+#define EQM_STATUS_NIF_CRC_ERR (0x916ce965UL)
+#define EQM_STATUS_NIF_PP_LOOP_LCK (0xffa2b3c4UL)
+#define EQM_STATUS_NIF_RX_OF_ERR (0xa81de080UL)
+#define EQM_STATUS_NIF_SYNC_ERR (0x2bd128e9UL)
+#define EQM_STATUS_QM_CRC_ERR (0xd4dbf0f2UL)
+#define EQM_STATUS_RMT_EGS_OF_ERR (0x3ce2cda4UL)
+#define EQM_STATUS_RMT_ERR (0xc037b2cdUL)
+#define EQM_STATUS_RMT_IGS_OF_ERR (0x26de2d2aUL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_EQM_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_fhm.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_fhm.h
new file mode 100644
index 0000000000..26da7100b3
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_fhm.h
@@ -0,0 +1,48 @@
+/*
+ * nthw_fpga_reg_defs_fhm.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_FHM_
+#define _NTHW_FPGA_REG_DEFS_FHM_
+
+/* FHM */
+#define NTHW_MOD_FHM (0x83d696a0UL)
+#define FHM_BACK_PRESSURE (0x7eeb6d04UL)
+#define FHM_BACK_PRESSURE_NIF (0x60f30e0aUL)
+#define FHM_BACK_PRESSURE_RMC (0x61c96595UL)
+#define FHM_BACK_PRESSURE_RMC_S (0xbf76d96bUL)
+#define FHM_CRC_ERROR_NIF (0x7b140652UL)
+#define FHM_CRC_ERROR_NIF_CNT (0x9d790794UL)
+#define FHM_CRC_ERROR_SDC (0xaa2ebcb3UL)
+#define FHM_CRC_ERROR_SDC_CNT (0xef0e6634UL)
+#define FHM_CTRL (0xdc86864eUL)
+#define FHM_CTRL_CNT_CLR (0x6fdab4c8UL)
+#define FHM_CTRL_ENABLE (0x3e8d895aUL)
+#define FHM_CTRL_MODE (0xdf0cf195UL)
+#define FHM_DEBUG_CRC (0xdaa801daUL)
+#define FHM_DEBUG_CRC_FORCE_ERROR (0xebcc0719UL)
+#define FHM_DEBUG_SDRAM_SIZE (0x13b07f7bUL)
+#define FHM_DEBUG_SDRAM_SIZE_MASK (0xc9824976UL)
+#define FHM_FILL_LEVEL (0x7244a4d9UL)
+#define FHM_FILL_LEVEL_CELLS (0x1b463c75UL)
+#define FHM_MAC_MICRO_DROP (0x643f5329UL)
+#define FHM_MAC_MICRO_DROP_CNT (0xb0483cceUL)
+#define FHM_MAX_FILL_LEVEL (0x7a5980a6UL)
+#define FHM_MAX_FILL_LEVEL_CELLS (0x7913d45fUL)
+#define FHM_PKT_DROP (0xa8f4d538UL)
+#define FHM_PKT_DROP_CNT (0x789eb18UL)
+#define FHM_PKT_DROP_BYTES (0xbba69523UL)
+#define FHM_PKT_DROP_BYTES_CNT (0xfc38c84eUL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_FHM_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_flm.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_flm.h
new file mode 100644
index 0000000000..67f9a5c1e9
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_flm.h
@@ -0,0 +1,237 @@
+/*
+ * nthw_fpga_reg_defs_flm.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_FLM_
+#define _NTHW_FPGA_REG_DEFS_FLM_
+
+/* FLM */
+#define NTHW_MOD_FLM (0xe7ba53a4UL)
+#define FLM_BUF_CTRL (0x2d7ba0b7UL)
+#define FLM_BUF_CTRL_INF_AVAIL (0x55993c46UL)
+#define FLM_BUF_CTRL_LRN_FREE (0x60b97a24UL)
+#define FLM_BUF_CTRL_STA_AVAIL (0x44abe7c4UL)
+#define FLM_CONTROL (0xdbb393a2UL)
+#define FLM_CONTROL_CRCRD (0x35ba7f13UL)
+#define FLM_CONTROL_CRCWR (0xbc193e07UL)
+#define FLM_CONTROL_EAB (0xa09637c2UL)
+#define FLM_CONTROL_ENABLE (0x5d80d95eUL)
+#define FLM_CONTROL_INIT (0x69b06e85UL)
+#define FLM_CONTROL_LDS (0xb880d8faUL)
+#define FLM_CONTROL_LFS (0x8ab6ba78UL)
+#define FLM_CONTROL_LIS (0xd2ea6b7UL)
+#define FLM_CONTROL_PDS (0xadbc82eeUL)
+#define FLM_CONTROL_PIS (0x1812fca3UL)
+#define FLM_CONTROL_RBL (0x756afcf3UL)
+#define FLM_CONTROL_RDS (0xae385680UL)
+#define FLM_CONTROL_RIS (0x1b9628cdUL)
+#define FLM_CONTROL_SPLIT_SDRAM_USAGE (0x71e7a8a4UL)
+#define FLM_CONTROL_UDS (0xab774005UL)
+#define FLM_CONTROL_UIS (0x1ed93e48UL)
+#define FLM_CONTROL_WPD (0x58ec6f9UL)
+#define FLM_INF_DATA (0xba19f6ccUL)
+#define FLM_INF_DATA_BYTES (0x480dab67UL)
+#define FLM_INF_DATA_BYT_A (0xb9920f4UL)
+#define FLM_INF_DATA_BYT_B (0x9290714eUL)
+#define FLM_INF_DATA_CAUSE (0x94e9716UL)
+#define FLM_INF_DATA_EOR (0xd81a867eUL)
+#define FLM_INF_DATA_ID (0x23a04258UL)
+#define FLM_INF_DATA_PACKETS (0x33a4ab9eUL)
+#define FLM_INF_DATA_PCK_A (0x3967b7a0UL)
+#define FLM_INF_DATA_PCK_B (0xa06ee61aUL)
+#define FLM_INF_DATA_RTX_A (0x900996cfUL)
+#define FLM_INF_DATA_RTX_B (0x900c775UL)
+#define FLM_INF_DATA_TCP_A (0xdc945df1UL)
+#define FLM_INF_DATA_TCP_B (0x459d0c4bUL)
+#define FLM_INF_DATA_TS (0x5f1fab83UL)
+#define FLM_LOAD_APS (0x4e7601e5UL)
+#define FLM_LOAD_APS_APS (0x504ad426UL)
+#define FLM_LOAD_BIN (0xb4367a7dUL)
+#define FLM_LOAD_BIN_BIN (0x274bb543UL)
+#define FLM_LOAD_LPS (0x46ae92b6UL)
+#define FLM_LOAD_LPS_LPS (0x394526b5UL)
+#define FLM_LRN_CTRL (0x11050e66UL)
+#define FLM_LRN_CTRL_FREE (0x4193813dUL)
+#define FLM_LRN_DATA (0xbed48c7fUL)
+#define FLM_LRN_DATA_ADJ (0x130ed7UL)
+#define FLM_LRN_DATA_COLOR (0x33d0a7f2UL)
+#define FLM_LRN_DATA_DSCP (0x5eab148eUL)
+#define FLM_LRN_DATA_ENT (0x7fa73e2UL)
+#define FLM_LRN_DATA_EOR (0xf782e796UL)
+#define FLM_LRN_DATA_FILL (0x768aba23UL)
+#define FLM_LRN_DATA_FT (0x4e9221cfUL)
+#define FLM_LRN_DATA_FT_MBR (0x48f095acUL)
+#define FLM_LRN_DATA_FT_MISS (0xea062e35UL)
+#define FLM_LRN_DATA_GFI (0xafa1415dUL)
+#define FLM_LRN_DATA_ID (0xd4bd2d64UL)
+#define FLM_LRN_DATA_KID (0x5f92d84bUL)
+#define FLM_LRN_DATA_MBR_ID1 (0x9931440eUL)
+#define FLM_LRN_DATA_MBR_ID2 (0x3815b4UL)
+#define FLM_LRN_DATA_MBR_ID3 (0x773f2522UL)
+#define FLM_LRN_DATA_MBR_ID4 (0xe95bb081UL)
+#define FLM_LRN_DATA_NAT_EN (0x9f4035a4UL)
+#define FLM_LRN_DATA_NAT_IP (0xc9fa47cbUL)
+#define FLM_LRN_DATA_NAT_PORT (0x5f8f57d0UL)
+#define FLM_LRN_DATA_NOFI (0x3d36f27bUL)
+#define FLM_LRN_DATA_OP (0x983d5e9fUL)
+#define FLM_LRN_DATA_PRIO (0xf7f55b0eUL)
+#define FLM_LRN_DATA_PROT (0x2bca3564UL)
+#define FLM_LRN_DATA_QFI (0xb70a9e9fUL)
+#define FLM_LRN_DATA_QW0 (0xcd0a7417UL)
+#define FLM_LRN_DATA_QW4 (0xca67b00eUL)
+#define FLM_LRN_DATA_RATE (0x5c250baeUL)
+#define FLM_LRN_DATA_RQI (0xb0cfa450UL)
+#define FLM_LRN_DATA_SCRUB_PROF (0xc3730f6bUL)
+#define FLM_LRN_DATA_SIZE (0x740910fdUL)
+#define FLM_LRN_DATA_STAT_PROF (0xded894eaUL)
+#define FLM_LRN_DATA_SW8 (0xc055284bUL)
+#define FLM_LRN_DATA_SW9 (0xb75218ddUL)
+#define FLM_LRN_DATA_TAU (0xea8196fcUL)
+#define FLM_LRN_DATA_TEID (0xf62ca024UL)
+#define FLM_LRN_DATA_TTL (0xb95fd828UL)
+#define FLM_LRN_DATA_VOL_IDX (0xabc86ffbUL)
+#define FLM_PRIO (0x5ed7bcbeUL)
+#define FLM_PRIO_FT0 (0x9ef34f69UL)
+#define FLM_PRIO_FT1 (0xe9f47fffUL)
+#define FLM_PRIO_FT2 (0x70fd2e45UL)
+#define FLM_PRIO_FT3 (0x7fa1ed3UL)
+#define FLM_PRIO_LIMIT0 (0xcce9cfe8UL)
+#define FLM_PRIO_LIMIT1 (0xbbeeff7eUL)
+#define FLM_PRIO_LIMIT2 (0x22e7aec4UL)
+#define FLM_PRIO_LIMIT3 (0x55e09e52UL)
+#define FLM_PST_CTRL (0x3e2b004bUL)
+#define FLM_PST_CTRL_ADR (0xfa8565c1UL)
+#define FLM_PST_CTRL_CNT (0xea8dfc10UL)
+#define FLM_PST_DATA (0x91fa8252UL)
+#define FLM_PST_DATA_BP (0x5f53d50fUL)
+#define FLM_PST_DATA_PP (0x27a7a5dcUL)
+#define FLM_PST_DATA_TP (0x43cb60d8UL)
+#define FLM_RCP_CTRL (0x8041d9eeUL)
+#define FLM_RCP_CTRL_ADR (0xb1a39fefUL)
+#define FLM_RCP_CTRL_CNT (0xa1ab063eUL)
+#define FLM_RCP_DATA (0x2f905bf7UL)
+#define FLM_RCP_DATA_A (0xec41ba43UL)
+#define FLM_RCP_DATA_AUTO_IPV4_MASK (0xa7818261UL)
+#define FLM_RCP_DATA_B (0x7548ebf9UL)
+#define FLM_RCP_DATA_BYT_DYN (0x28334583UL)
+#define FLM_RCP_DATA_BYT_OFS (0x8a3ac825UL)
+#define FLM_RCP_DATA_IPN (0x94f5d891UL)
+#define FLM_RCP_DATA_ITF (0xfe4295a7UL)
+#define FLM_RCP_DATA_KID (0xeca44cf9UL)
+#define FLM_RCP_DATA_LOOKUP (0x5d0f2e84UL)
+#define FLM_RCP_DATA_MASK (0xd97a1393UL)
+#define FLM_RCP_DATA_OPN (0x9078a423UL)
+#define FLM_RCP_DATA_QW0_DYN (0x28bd732dUL)
+#define FLM_RCP_DATA_QW0_OFS (0x8ab4fe8bUL)
+#define FLM_RCP_DATA_QW0_SEL (0x39adfaa9UL)
+#define FLM_RCP_DATA_QW4_DYN (0xdd3dd5edUL)
+#define FLM_RCP_DATA_QW4_OFS (0x7f34584bUL)
+#define FLM_RCP_DATA_SW8_DYN (0x8f5229c5UL)
+#define FLM_RCP_DATA_SW8_OFS (0x2d5ba463UL)
+#define FLM_RCP_DATA_SW8_SEL (0x9e42a041UL)
+#define FLM_RCP_DATA_SW9_DYN (0xb2320075UL)
+#define FLM_RCP_DATA_SW9_OFS (0x103b8dd3UL)
+#define FLM_RCP_DATA_TXPLM (0xbe56af35UL)
+#define FLM_SCAN (0xee586089UL)
+#define FLM_SCAN_I (0xe22d4ee5UL)
+#define FLM_SCRUB (0x690c7a66UL)
+#define FLM_SCRUB_I (0xc6a9dfe8UL)
+#define FLM_SCRUB_CTRL (0xc647074aUL)
+#define FLM_SCRUB_CTRL_ADR (0x3d584aa4UL)
+#define FLM_SCRUB_CTRL_CNT (0x2d50d375UL)
+#define FLM_SCRUB_DATA (0x69968553UL)
+#define FLM_SCRUB_DATA_T (0x2a9c9e90UL)
+#define FLM_STAT (0xa532c06UL)
+#define FLM_STAT_I (0x215c23d1UL)
+#define FLM_STATUS (0x10f57a96UL)
+#define FLM_STATUS_CALIBDONE (0x47680c22UL)
+#define FLM_STATUS_CRCERR (0xcd852b33UL)
+#define FLM_STATUS_CRITICAL (0xe9e1b478UL)
+#define FLM_STATUS_EFT_BP (0xf60fc391UL)
+#define FLM_STATUS_EFT_EVICT_BP (0xf4dd216fUL)
+#define FLM_STATUS_IDLE (0xd02fd0e7UL)
+#define FLM_STATUS_INITDONE (0xdd6bdbd8UL)
+#define FLM_STATUS_PANIC (0xf676390fUL)
+#define FLM_STAT_AUL_DONE (0x747800bbUL)
+#define FLM_STAT_AUL_DONE_CNT (0x6b744caeUL)
+#define FLM_STAT_AUL_FAIL (0xe272cb59UL)
+#define FLM_STAT_AUL_FAIL_CNT (0x697b6247UL)
+#define FLM_STAT_AUL_IGNORE (0x49aa46f4UL)
+#define FLM_STAT_AUL_IGNORE_CNT (0x37721e3bUL)
+#define FLM_STAT_CSH_HIT (0xd0dca28cUL)
+#define FLM_STAT_CSH_HIT_CNT (0xc7a41ba4UL)
+#define FLM_STAT_CSH_MISS (0xbc219a9fUL)
+#define FLM_STAT_CSH_MISS_CNT (0x4a66e57eUL)
+#define FLM_STAT_CSH_UNH (0x9f625827UL)
+#define FLM_STAT_CSH_UNH_CNT (0x79b8ac91UL)
+#define FLM_STAT_CUC_MOVE (0x381862c0UL)
+#define FLM_STAT_CUC_MOVE_CNT (0x868e1261UL)
+#define FLM_STAT_CUC_START (0x617a68acUL)
+#define FLM_STAT_CUC_START_CNT (0xbf953f79UL)
+#define FLM_STAT_FLOWS (0x3072544fUL)
+#define FLM_STAT_FLOWS_CNT (0x829b2631UL)
+#define FLM_STAT_INF_DONE (0x63dff05cUL)
+#define FLM_STAT_INF_DONE_CNT (0xf78de916UL)
+#define FLM_STAT_INF_SKIP (0x8b84458aUL)
+#define FLM_STAT_INF_SKIP_CNT (0xc0b9dd7dUL)
+#define FLM_STAT_LRN_DONE (0x67128aefUL)
+#define FLM_STAT_LRN_DONE_CNT (0xd81588feUL)
+#define FLM_STAT_LRN_FAIL (0xf118410dUL)
+#define FLM_STAT_LRN_FAIL_CNT (0xda1aa617UL)
+#define FLM_STAT_LRN_IGNORE (0x9a10a7f0UL)
+#define FLM_STAT_LRN_IGNORE_CNT (0x11c0f6a7UL)
+#define FLM_STAT_PCK_DIS (0x55e23053UL)
+#define FLM_STAT_PCK_DIS_CNT (0x9b13b227UL)
+#define FLM_STAT_PCK_HIT (0xc29c5c94UL)
+#define FLM_STAT_PCK_HIT_CNT (0xee930443UL)
+#define FLM_STAT_PCK_MISS (0xaf5f4237UL)
+#define FLM_STAT_PCK_MISS_CNT (0x7421a5baUL)
+#define FLM_STAT_PCK_UNH (0x8d22a63fUL)
+#define FLM_STAT_PCK_UNH_CNT (0x508fb376UL)
+#define FLM_STAT_PRB_DONE (0x3bc46ef0UL)
+#define FLM_STAT_PRB_DONE_CNT (0xcb3bc80dUL)
+#define FLM_STAT_PRB_IGNORE (0xf02dd3d9UL)
+#define FLM_STAT_PRB_IGNORE_CNT (0x588d1667UL)
+#define FLM_STAT_REL_DONE (0xe192aabdUL)
+#define FLM_STAT_REL_DONE_CNT (0xbe04b769UL)
+#define FLM_STAT_REL_IGNORE (0x29f33e6eUL)
+#define FLM_STAT_REL_IGNORE_CNT (0x99a6a156UL)
+#define FLM_STAT_STA_DONE (0x500f2e87UL)
+#define FLM_STAT_STA_DONE_CNT (0xbf276bbdUL)
+#define FLM_STAT_TUL_DONE (0x40233ff4UL)
+#define FLM_STAT_TUL_DONE_CNT (0xffcfd642UL)
+#define FLM_STAT_UNL_DONE (0xe950f75eUL)
+#define FLM_STAT_UNL_DONE_CNT (0xe9bdd9a2UL)
+#define FLM_STAT_UNL_IGNORE (0x497abbcaUL)
+#define FLM_STAT_UNL_IGNORE_CNT (0x1ba2b435UL)
+#define FLM_STA_DATA (0x89c92817UL)
+#define FLM_STA_DATA_EOR (0x90b004d5UL)
+#define FLM_STA_DATA_ID (0x3b14a2ffUL)
+#define FLM_STA_DATA_LDS (0xb92d607UL)
+#define FLM_STA_DATA_LFS (0x39a4b485UL)
+#define FLM_STA_DATA_LIS (0xbe3ca84aUL)
+#define FLM_STA_DATA_PDS (0x1eae8c13UL)
+#define FLM_STA_DATA_PIS (0xab00f25eUL)
+#define FLM_STA_DATA_RDS (0x1d2a587dUL)
+#define FLM_STA_DATA_RIS (0xa8842630UL)
+#define FLM_STA_DATA_UDS (0x18654ef8UL)
+#define FLM_STA_DATA_UIS (0xadcb30b5UL)
+#define FLM_TIMEOUT (0xb729ca7bUL)
+#define FLM_TIMEOUT_T (0x91a2b284UL)
+#define FLM_TRSWIN (0xff97af47UL)
+#define FLM_TRSWIN_S (0x41ed83b1UL)
+#define FLM_TRTWIN (0x624097feUL)
+#define FLM_TRTWIN_T (0xc28c26aaUL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_FLM_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gfg.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gfg.h
new file mode 100644
index 0000000000..6ee75c571e
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gfg.h
@@ -0,0 +1,126 @@
+/*
+ * nthw_fpga_reg_defs_gfg.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_GFG_
+#define _NTHW_FPGA_REG_DEFS_GFG_
+
+/* GFG */
+#define NTHW_MOD_GFG (0xfc423807UL)
+#define GFG_BURSTSIZE0 (0xd62af404UL)
+#define GFG_BURSTSIZE0_VAL (0xa2e4d17eUL)
+#define GFG_BURSTSIZE1 (0xa12dc492UL)
+#define GFG_BURSTSIZE1_VAL (0x9f84f8ceUL)
+#define GFG_BURSTSIZE2 (0x38249528UL)
+#define GFG_BURSTSIZE2_VAL (0xd824821eUL)
+#define GFG_BURSTSIZE3 (0x4f23a5beUL)
+#define GFG_BURSTSIZE3_VAL (0xe544abaeUL)
+#define GFG_BURSTSIZE4 (0xd147301dUL)
+#define GFG_BURSTSIZE4_VAL (0x576477beUL)
+#define GFG_BURSTSIZE5 (0xa640008bUL)
+#define GFG_BURSTSIZE5_VAL (0x6a045e0eUL)
+#define GFG_BURSTSIZE6 (0x3f495131UL)
+#define GFG_BURSTSIZE6_VAL (0x2da424deUL)
+#define GFG_BURSTSIZE7 (0x484e61a7UL)
+#define GFG_BURSTSIZE7_VAL (0x10c40d6eUL)
+#define GFG_CTRL0 (0xc3e26c0fUL)
+#define GFG_CTRL0_ENABLE (0xfe65937UL)
+#define GFG_CTRL0_MODE (0x81d94c52UL)
+#define GFG_CTRL0_PRBS_EN (0xb43e6c6UL)
+#define GFG_CTRL0_SIZE (0xe1d32f93UL)
+#define GFG_CTRL1 (0xb4e55c99UL)
+#define GFG_CTRL1_ENABLE (0xc34c59a9UL)
+#define GFG_CTRL1_MODE (0x4a859ff7UL)
+#define GFG_CTRL1_PRBS_EN (0x1c38f285UL)
+#define GFG_CTRL1_SIZE (0x2a8ffc36UL)
+#define GFG_CTRL2 (0x2dec0d23UL)
+#define GFG_CTRL2_ENABLE (0x4dc35e4aUL)
+#define GFG_CTRL2_MODE (0xcc11ed59UL)
+#define GFG_CTRL2_PRBS_EN (0x25b5ce40UL)
+#define GFG_CTRL2_SIZE (0xac1b8e98UL)
+#define GFG_CTRL3 (0x5aeb3db5UL)
+#define GFG_CTRL3_ENABLE (0x81695ed4UL)
+#define GFG_CTRL3_MODE (0x74d3efcUL)
+#define GFG_CTRL3_PRBS_EN (0x32ceda03UL)
+#define GFG_CTRL3_SIZE (0x67475d3dUL)
+#define GFG_CTRL4 (0xc48fa816UL)
+#define GFG_CTRL4_ENABLE (0x8bac57cdUL)
+#define GFG_CTRL4_MODE (0x1a480e44UL)
+#define GFG_CTRL4_PRBS_EN (0x56afb7caUL)
+#define GFG_CTRL4_SIZE (0x7a426d85UL)
+#define GFG_CTRL5 (0xb3889880UL)
+#define GFG_CTRL5_ENABLE (0x47065753UL)
+#define GFG_CTRL5_MODE (0xd114dde1UL)
+#define GFG_CTRL5_PRBS_EN (0x41d4a389UL)
+#define GFG_CTRL5_SIZE (0xb11ebe20UL)
+#define GFG_CTRL6 (0x2a81c93aUL)
+#define GFG_CTRL6_ENABLE (0xc98950b0UL)
+#define GFG_CTRL6_MODE (0x5780af4fUL)
+#define GFG_CTRL6_PRBS_EN (0x78599f4cUL)
+#define GFG_CTRL6_SIZE (0x378acc8eUL)
+#define GFG_CTRL7 (0x5d86f9acUL)
+#define GFG_CTRL7_ENABLE (0x523502eUL)
+#define GFG_CTRL7_MODE (0x9cdc7ceaUL)
+#define GFG_CTRL7_PRBS_EN (0x6f228b0fUL)
+#define GFG_CTRL7_SIZE (0xfcd61f2bUL)
+#define GFG_RUN0 (0xb72be46cUL)
+#define GFG_RUN0_RUN (0xa457d3c8UL)
+#define GFG_RUN1 (0xc02cd4faUL)
+#define GFG_RUN1_RUN (0x9937fa78UL)
+#define GFG_RUN2 (0x59258540UL)
+#define GFG_RUN2_RUN (0xde9780a8UL)
+#define GFG_RUN3 (0x2e22b5d6UL)
+#define GFG_RUN3_RUN (0xe3f7a918UL)
+#define GFG_RUN4 (0xb0462075UL)
+#define GFG_RUN4_RUN (0x51d77508UL)
+#define GFG_RUN5 (0xc74110e3UL)
+#define GFG_RUN5_RUN (0x6cb75cb8UL)
+#define GFG_RUN6 (0x5e484159UL)
+#define GFG_RUN6_RUN (0x2b172668UL)
+#define GFG_RUN7 (0x294f71cfUL)
+#define GFG_RUN7_RUN (0x16770fd8UL)
+#define GFG_SIZEMASK0 (0x7015abe3UL)
+#define GFG_SIZEMASK0_VAL (0xe9c7ed93UL)
+#define GFG_SIZEMASK1 (0x7129b75UL)
+#define GFG_SIZEMASK1_VAL (0xd4a7c423UL)
+#define GFG_SIZEMASK2 (0x9e1bcacfUL)
+#define GFG_SIZEMASK2_VAL (0x9307bef3UL)
+#define GFG_SIZEMASK3 (0xe91cfa59UL)
+#define GFG_SIZEMASK3_VAL (0xae679743UL)
+#define GFG_SIZEMASK4 (0x77786ffaUL)
+#define GFG_SIZEMASK4_VAL (0x1c474b53UL)
+#define GFG_SIZEMASK5 (0x7f5f6cUL)
+#define GFG_SIZEMASK5_VAL (0x212762e3UL)
+#define GFG_SIZEMASK6 (0x99760ed6UL)
+#define GFG_SIZEMASK6_VAL (0x66871833UL)
+#define GFG_SIZEMASK7 (0xee713e40UL)
+#define GFG_SIZEMASK7_VAL (0x5be73183UL)
+#define GFG_STREAMID0 (0xbd4ba9aeUL)
+#define GFG_STREAMID0_VAL (0x42d077caUL)
+#define GFG_STREAMID1 (0xca4c9938UL)
+#define GFG_STREAMID1_VAL (0x7fb05e7aUL)
+#define GFG_STREAMID2 (0x5345c882UL)
+#define GFG_STREAMID2_VAL (0x381024aaUL)
+#define GFG_STREAMID3 (0x2442f814UL)
+#define GFG_STREAMID3_VAL (0x5700d1aUL)
+#define GFG_STREAMID4 (0xba266db7UL)
+#define GFG_STREAMID4_VAL (0xb750d10aUL)
+#define GFG_STREAMID5 (0xcd215d21UL)
+#define GFG_STREAMID5_VAL (0x8a30f8baUL)
+#define GFG_STREAMID6 (0x54280c9bUL)
+#define GFG_STREAMID6_VAL (0xcd90826aUL)
+#define GFG_STREAMID7 (0x232f3c0dUL)
+#define GFG_STREAMID7_VAL (0xf0f0abdaUL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_GFG_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gmf.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gmf.h
new file mode 100644
index 0000000000..be3c12d177
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gmf.h
@@ -0,0 +1,68 @@
+/*
+ * nthw_fpga_reg_defs_gmf.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_GMF_
+#define _NTHW_FPGA_REG_DEFS_GMF_
+
+/* GMF */
+#define NTHW_MOD_GMF (0x68b1d15aUL)
+#define GMF_CTRL (0x28d359b4UL)
+#define GMF_CTRL_ENABLE (0xe41c837cUL)
+#define GMF_CTRL_FCS_ALWAYS (0x8f36cec1UL)
+#define GMF_CTRL_IFG_AUTO_ADJUST_ENABLE (0x5b5669b0UL)
+#define GMF_CTRL_IFG_ENABLE (0x995f1bfbUL)
+#define GMF_CTRL_IFG_TX_NOW_ALWAYS (0xb11744c2UL)
+#define GMF_CTRL_IFG_TX_NOW_ON_TS_ENABLE (0xe9e4ee2aUL)
+#define GMF_CTRL_IFG_TX_ON_TS_ADJUST_ON_SET_CLOCK (0x32dc6426UL)
+#define GMF_CTRL_IFG_TX_ON_TS_ALWAYS (0x21dcad67UL)
+#define GMF_CTRL_TS_INJECT_ALWAYS (0x353fa4aaUL)
+#define GMF_CTRL_TS_INJECT_DUAL_STEP (0xc4c0195cUL)
+#define GMF_DEBUG_LANE_MARKER (0xa51eb8a9UL)
+#define GMF_DEBUG_LANE_MARKER_COMPENSATION (0x4f44f92aUL)
+#define GMF_IFG_MAX_ADJUST_SLACK (0xe49f3408UL)
+#define GMF_IFG_MAX_ADJUST_SLACK_SLACK (0x9a2de1f7UL)
+#define GMF_IFG_SET_CLOCK_DELTA (0x8a614d6fUL)
+#define GMF_IFG_SET_CLOCK_DELTA_DELTA (0x1da821d6UL)
+#define GMF_IFG_SET_CLOCK_DELTA_ADJUST (0xaa468304UL)
+#define GMF_IFG_SET_CLOCK_DELTA_ADJUST_DELTA (0x2c165992UL)
+#define GMF_IFG_TX_NOW_ON_TS (0xd32fab5eUL)
+#define GMF_IFG_TX_NOW_ON_TS_TS (0x612771f4UL)
+#define GMF_SPEED (0x48bec0a1UL)
+#define GMF_SPEED_IFG_SPEED (0x273c8281UL)
+#define GMF_STAT (0xa49d7efUL)
+#define GMF_STAT_CTRL_EMPTY (0x3f6e8adcUL)
+#define GMF_STAT_DATA_CTRL_EMPTY (0xc18fc6e9UL)
+#define GMF_STAT_SB_EMPTY (0x99314d52UL)
+#define GMF_STAT_CTRL (0xfd31633eUL)
+#define GMF_STAT_CTRL_FILL_LEVEL (0xe8cd56d6UL)
+#define GMF_STAT_DATA0 (0x51838aabUL)
+#define GMF_STAT_DATA0_EMPTY (0xcfcad9c0UL)
+#define GMF_STAT_DATA1 (0x2684ba3dUL)
+#define GMF_STAT_DATA1_EMPTY (0x69bdd274UL)
+#define GMF_STAT_DATA_BUFFER (0xa6431f34UL)
+#define GMF_STAT_DATA_BUFFER_FREE (0x3476e461UL)
+#define GMF_STAT_DATA_BUFFER_USED (0x1f46b1UL)
+#define GMF_STAT_MAX_DELAYED_PKT (0x3fb5c76dUL)
+#define GMF_STAT_MAX_DELAYED_PKT_NS (0x2eb58efbUL)
+#define GMF_STAT_NEXT_PKT (0x558ee30dUL)
+#define GMF_STAT_NEXT_PKT_NS (0x26814d33UL)
+#define GMF_STAT_STICKY (0x5a0f2ef7UL)
+#define GMF_STAT_STICKY_DATA_UNDERFLOWED (0x9a3dfcb6UL)
+#define GMF_STAT_STICKY_IFG_ADJUSTED (0xea849a5fUL)
+#define GMF_TS_INJECT (0x66e57281UL)
+#define GMF_TS_INJECT_OFFSET (0x8c2c9cb6UL)
+#define GMF_TS_INJECT_POS (0xdded481UL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_GMF_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gpio_phy.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gpio_phy.h
new file mode 100644
index 0000000000..6574263d50
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gpio_phy.h
@@ -0,0 +1,48 @@
+/*
+ * nthw_fpga_reg_defs_gpio_phy.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_GPIO_PHY_
+#define _NTHW_FPGA_REG_DEFS_GPIO_PHY_
+
+/* GPIO_PHY */
+#define NTHW_MOD_GPIO_PHY (0xbbe81659UL)
+#define GPIO_PHY_CFG (0x39548432UL)
+#define GPIO_PHY_CFG_E_PORT0_RXLOS (0x2dfe5bUL)
+#define GPIO_PHY_CFG_E_PORT1_RXLOS (0xa65af5efUL)
+#define GPIO_PHY_CFG_PORT0_INT_B (0xa882887cUL)
+#define GPIO_PHY_CFG_PORT0_LPMODE (0x65df41beUL)
+#define GPIO_PHY_CFG_PORT0_MODPRS_B (0x6aef8e94UL)
+#define GPIO_PHY_CFG_PORT0_PLL_INTR (0xbf1f8c5dUL)
+#define GPIO_PHY_CFG_PORT0_RESET_B (0x1ef06a6cUL)
+#define GPIO_PHY_CFG_PORT1_INT_B (0xef583c8UL)
+#define GPIO_PHY_CFG_PORT1_LPMODE (0xa9754120UL)
+#define GPIO_PHY_CFG_PORT1_MODPRS_B (0x852de5aaUL)
+#define GPIO_PHY_CFG_PORT1_PLL_INTR (0x50dde763UL)
+#define GPIO_PHY_CFG_PORT1_RESET_B (0x98b7e2fUL)
+#define GPIO_PHY_GPIO (0xf5c5d393UL)
+#define GPIO_PHY_GPIO_E_PORT0_RXLOS (0xfb05c9faUL)
+#define GPIO_PHY_GPIO_E_PORT1_RXLOS (0x5d72c24eUL)
+#define GPIO_PHY_GPIO_PORT0_INT_B (0x6aceab27UL)
+#define GPIO_PHY_GPIO_PORT0_LPMODE (0x99a485e1UL)
+#define GPIO_PHY_GPIO_PORT0_MODPRS_B (0xcbc535ddUL)
+#define GPIO_PHY_GPIO_PORT0_PLL_INTR (0x1e353714UL)
+#define GPIO_PHY_GPIO_PORT0_RESET_B (0xe5d85dcdUL)
+#define GPIO_PHY_GPIO_PORT1_INT_B (0xccb9a093UL)
+#define GPIO_PHY_GPIO_PORT1_LPMODE (0x550e857fUL)
+#define GPIO_PHY_GPIO_PORT1_MODPRS_B (0x24075ee3UL)
+#define GPIO_PHY_GPIO_PORT1_PLL_INTR (0xf1f75c2aUL)
+#define GPIO_PHY_GPIO_PORT1_RESET_B (0xf2a3498eUL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_GPIO_PHY_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gpio_phy_ports.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gpio_phy_ports.h
new file mode 100644
index 0000000000..c90a4d3209
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gpio_phy_ports.h
@@ -0,0 +1,72 @@
+/*
+ * nthw_fpga_reg_defs_gpio_phy_ports.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_GPIO_PHY_PORTS_
+#define _NTHW_FPGA_REG_DEFS_GPIO_PHY_PORTS_
+
+/* GPIO_PHY_PORTS */
+#define NTHW_MOD_GPIO_PHY_PORTS (0xea12bddaUL)
+#define GPIO_PHY_PORTS_CFG (0xe1aa4733UL)
+#define GPIO_PHY_PORTS_CFG_E_PORT0_RXLOS (0x252ff3abUL)
+#define GPIO_PHY_PORTS_CFG_E_PORT0_TXDISABLE (0xc9d467abUL)
+#define GPIO_PHY_PORTS_CFG_E_PORT0_TXFAULT (0xd56642aaUL)
+#define GPIO_PHY_PORTS_CFG_E_PORT1_RXLOS (0x8358f81fUL)
+#define GPIO_PHY_PORTS_CFG_E_PORT1_TXDISABLE (0x85ab86bUL)
+#define GPIO_PHY_PORTS_CFG_E_PORT1_TXFAULT (0xc21d56e9UL)
+#define GPIO_PHY_PORTS_CFG_E_PORT2_RXLOS (0xb2b0e282UL)
+#define GPIO_PHY_PORTS_CFG_E_PORT2_TXDISABLE (0x91b8de6aUL)
+#define GPIO_PHY_PORTS_CFG_E_PORT2_TXFAULT (0xfb906a2cUL)
+#define GPIO_PHY_PORTS_CFG_E_PORT3_RXLOS (0x14c7e936UL)
+#define GPIO_PHY_PORTS_CFG_E_PORT3_TXDISABLE (0x503601aaUL)
+#define GPIO_PHY_PORTS_CFG_E_PORT3_TXFAULT (0xeceb7e6fUL)
+#define GPIO_PHY_PORTS_CFG_E_PORT4_RXLOS (0xd160d7b8UL)
+#define GPIO_PHY_PORTS_CFG_E_PORT4_TXDISABLE (0x790d1429UL)
+#define GPIO_PHY_PORTS_CFG_E_PORT4_TXFAULT (0x888a13a6UL)
+#define GPIO_PHY_PORTS_CFG_E_PORT5_RXLOS (0x7717dc0cUL)
+#define GPIO_PHY_PORTS_CFG_E_PORT5_TXDISABLE (0xb883cbe9UL)
+#define GPIO_PHY_PORTS_CFG_E_PORT5_TXFAULT (0x9ff107e5UL)
+#define GPIO_PHY_PORTS_CFG_E_PORT6_RXLOS (0x46ffc691UL)
+#define GPIO_PHY_PORTS_CFG_E_PORT6_TXDISABLE (0x2161ade8UL)
+#define GPIO_PHY_PORTS_CFG_E_PORT6_TXFAULT (0xa67c3b20UL)
+#define GPIO_PHY_PORTS_CFG_E_PORT7_RXLOS (0xe088cd25UL)
+#define GPIO_PHY_PORTS_CFG_E_PORT7_TXDISABLE (0xe0ef7228UL)
+#define GPIO_PHY_PORTS_CFG_E_PORT7_TXFAULT (0xb1072f63UL)
+#define GPIO_PHY_PORTS_GPIO (0x821a1dc6UL)
+#define GPIO_PHY_PORTS_GPIO_E_PORT0_RXLOS (0x469d39ebUL)
+#define GPIO_PHY_PORTS_GPIO_E_PORT0_TXDISABLE (0xccb0d0d8UL)
+#define GPIO_PHY_PORTS_GPIO_E_PORT0_TXFAULT (0x5eae45b3UL)
+#define GPIO_PHY_PORTS_GPIO_E_PORT1_RXLOS (0xe0ea325fUL)
+#define GPIO_PHY_PORTS_GPIO_E_PORT1_TXDISABLE (0xd3e0f18UL)
+#define GPIO_PHY_PORTS_GPIO_E_PORT1_TXFAULT (0x49d551f0UL)
+#define GPIO_PHY_PORTS_GPIO_E_PORT2_RXLOS (0xd10228c2UL)
+#define GPIO_PHY_PORTS_GPIO_E_PORT2_TXDISABLE (0x94dc6919UL)
+#define GPIO_PHY_PORTS_GPIO_E_PORT2_TXFAULT (0x70586d35UL)
+#define GPIO_PHY_PORTS_GPIO_E_PORT3_RXLOS (0x77752376UL)
+#define GPIO_PHY_PORTS_GPIO_E_PORT3_TXDISABLE (0x5552b6d9UL)
+#define GPIO_PHY_PORTS_GPIO_E_PORT3_TXFAULT (0x67237976UL)
+#define GPIO_PHY_PORTS_GPIO_E_PORT4_RXLOS (0xb2d21df8UL)
+#define GPIO_PHY_PORTS_GPIO_E_PORT4_TXDISABLE (0x7c69a35aUL)
+#define GPIO_PHY_PORTS_GPIO_E_PORT4_TXFAULT (0x34214bfUL)
+#define GPIO_PHY_PORTS_GPIO_E_PORT5_RXLOS (0x14a5164cUL)
+#define GPIO_PHY_PORTS_GPIO_E_PORT5_TXDISABLE (0xbde77c9aUL)
+#define GPIO_PHY_PORTS_GPIO_E_PORT5_TXFAULT (0x143900fcUL)
+#define GPIO_PHY_PORTS_GPIO_E_PORT6_RXLOS (0x254d0cd1UL)
+#define GPIO_PHY_PORTS_GPIO_E_PORT6_TXDISABLE (0x24051a9bUL)
+#define GPIO_PHY_PORTS_GPIO_E_PORT6_TXFAULT (0x2db43c39UL)
+#define GPIO_PHY_PORTS_GPIO_E_PORT7_RXLOS (0x833a0765UL)
+#define GPIO_PHY_PORTS_GPIO_E_PORT7_TXDISABLE (0xe58bc55bUL)
+#define GPIO_PHY_PORTS_GPIO_E_PORT7_TXFAULT (0x3acf287aUL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_GPIO_PHY_PORTS_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gpio_sfpp.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gpio_sfpp.h
new file mode 100644
index 0000000000..f271b0cd46
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gpio_sfpp.h
@@ -0,0 +1,34 @@
+/*
+ * nthw_fpga_reg_defs_gpio_sfpp.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_GPIO_SFPP_
+#define _NTHW_FPGA_REG_DEFS_GPIO_SFPP_
+
+/* GPIO_SFPP */
+#define NTHW_MOD_GPIO_SFPP (0x628c8692UL)
+#define GPIO_SFPP_CFG (0x9b959116UL)
+#define GPIO_SFPP_CFG_ABS (0xc2942338UL)
+#define GPIO_SFPP_CFG_RS (0x47e98ea9UL)
+#define GPIO_SFPP_CFG_RXLOS (0x7e3cf082UL)
+#define GPIO_SFPP_CFG_TXDISABLE (0x8bfef0a8UL)
+#define GPIO_SFPP_CFG_TXFAULT (0x829d7e8UL)
+#define GPIO_SFPP_GPIO (0xc964f657UL)
+#define GPIO_SFPP_GPIO_ABS (0x246621e1UL)
+#define GPIO_SFPP_GPIO_RS (0xd6b756e6UL)
+#define GPIO_SFPP_GPIO_RXLOS (0xc0c8090aUL)
+#define GPIO_SFPP_GPIO_TXDISABLE (0x450f9c11UL)
+#define GPIO_SFPP_GPIO_TXFAULT (0x3f1231e7UL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_GPIO_SFPP_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_hfu.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_hfu.h
new file mode 100644
index 0000000000..19589f7900
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_hfu.h
@@ -0,0 +1,48 @@
+/*
+ * nthw_fpga_reg_defs_hfu.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_HFU_
+#define _NTHW_FPGA_REG_DEFS_HFU_
+
+/* HFU */
+#define NTHW_MOD_HFU (0x4a70e72UL)
+#define HFU_RCP_CTRL (0xbfa69368UL)
+#define HFU_RCP_CTRL_ADR (0xa3c53608UL)
+#define HFU_RCP_CTRL_CNT (0xb3cdafd9UL)
+#define HFU_RCP_DATA (0x10771171UL)
+#define HFU_RCP_DATA_LEN_A_ADD_DYN (0xf48e5cadUL)
+#define HFU_RCP_DATA_LEN_A_ADD_OFS (0x5687d10bUL)
+#define HFU_RCP_DATA_LEN_A_OL4LEN (0xb06eaffcUL)
+#define HFU_RCP_DATA_LEN_A_POS_DYN (0x8d207086UL)
+#define HFU_RCP_DATA_LEN_A_POS_OFS (0x2f29fd20UL)
+#define HFU_RCP_DATA_LEN_A_SUB_DYN (0x4305f5d4UL)
+#define HFU_RCP_DATA_LEN_A_WR (0x22d5466UL)
+#define HFU_RCP_DATA_LEN_B_ADD_DYN (0xcd036068UL)
+#define HFU_RCP_DATA_LEN_B_ADD_OFS (0x6f0aedceUL)
+#define HFU_RCP_DATA_LEN_B_POS_DYN (0xb4ad4c43UL)
+#define HFU_RCP_DATA_LEN_B_POS_OFS (0x16a4c1e5UL)
+#define HFU_RCP_DATA_LEN_B_SUB_DYN (0x7a88c911UL)
+#define HFU_RCP_DATA_LEN_B_WR (0x1098fb88UL)
+#define HFU_RCP_DATA_LEN_C_ADD_DYN (0xda78742bUL)
+#define HFU_RCP_DATA_LEN_C_ADD_OFS (0x7871f98dUL)
+#define HFU_RCP_DATA_LEN_C_POS_DYN (0xa3d65800UL)
+#define HFU_RCP_DATA_LEN_C_POS_OFS (0x1dfd5a6UL)
+#define HFU_RCP_DATA_LEN_C_SUB_DYN (0x6df3dd52UL)
+#define HFU_RCP_DATA_LEN_C_WR (0xa8249cedUL)
+#define HFU_RCP_DATA_TTL_POS_DYN (0x92a70913UL)
+#define HFU_RCP_DATA_TTL_POS_OFS (0x30ae84b5UL)
+#define HFU_RCP_DATA_TTL_WR (0x7a1aaf7UL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_HFU_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_hif.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_hif.h
new file mode 100644
index 0000000000..4bd2ca52c9
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_hif.h
@@ -0,0 +1,79 @@
+/*
+ * nthw_fpga_reg_defs_hif.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_HIF_
+#define _NTHW_FPGA_REG_DEFS_HIF_
+
+/* HIF */
+#define NTHW_MOD_HIF (0x7815363UL)
+#define HIF_BUILD_TIME (0x1eaf6ab8UL)
+#define HIF_BUILD_TIME_TIME (0xb2dfbda5UL)
+#define HIF_CONFIG (0xb64b595cUL)
+#define HIF_CONFIG_EXT_TAG (0x57e685bUL)
+#define HIF_CONFIG_MAX_READ (0x7d56ce45UL)
+#define HIF_CONFIG_MAX_TLP (0xe1c563e4UL)
+#define HIF_CONTROL (0xedb9ed3dUL)
+#define HIF_CONTROL_BLESSED (0x680018b7UL)
+#define HIF_CONTROL_FSR (0x498a2097UL)
+#define HIF_CONTROL_WRAW (0xc1a7bc42UL)
+#define HIF_PROD_ID_EX (0xc9c9efb2UL)
+#define HIF_PROD_ID_EX_LAYOUT (0xc6564c80UL)
+#define HIF_PROD_ID_EX_LAYOUT_VERSION (0x9803a0e2UL)
+#define HIF_PROD_ID_EX_RESERVED (0x1189af8aUL)
+#define HIF_PROD_ID_EXT (0x9ba2612fUL)
+#define HIF_PROD_ID_EXT_LAYOUT (0xe315afa1UL)
+#define HIF_PROD_ID_EXT_LAYOUT_VERSION (0x1f7aa616UL)
+#define HIF_PROD_ID_EXT_RESERVED (0xa4152ce8UL)
+#define HIF_PROD_ID_LSB (0x8353363aUL)
+#define HIF_PROD_ID_LSB_GROUP_ID (0xbb9614f7UL)
+#define HIF_PROD_ID_LSB_REV_ID (0x5458192eUL)
+#define HIF_PROD_ID_LSB_VER_ID (0x40abcc6fUL)
+#define HIF_PROD_ID_MSB (0x82915c0dUL)
+#define HIF_PROD_ID_MSB_BUILD_NO (0x1135f11bUL)
+#define HIF_PROD_ID_MSB_PATCH_NO (0xcbf446bcUL)
+#define HIF_PROD_ID_MSB_TYPE_ID (0xb49af41cUL)
+#define HIF_SAMPLE_TIME (0xad0472aaUL)
+#define HIF_SAMPLE_TIME_SAMPLE_TIME (0x56bd0a0bUL)
+#define HIF_STATUS (0x19c1133cUL)
+#define HIF_STATUS_RD_ERR (0x15e9f376UL)
+#define HIF_STATUS_TAGS_IN_USE (0x9789b255UL)
+#define HIF_STATUS_WR_ERR (0xaa8400e7UL)
+#define HIF_STAT_CTRL (0xd9478d74UL)
+#define HIF_STAT_CTRL_STAT_ENA (0xf26c834cUL)
+#define HIF_STAT_CTRL_STAT_REQ (0x1546ff16UL)
+#define HIF_STAT_REFCLK (0x656cf83fUL)
+#define HIF_STAT_REFCLK_REFCLK250 (0xb9dd01fcUL)
+#define HIF_STAT_RX (0x8c483f48UL)
+#define HIF_STAT_RX_COUNTER (0xd99bc360UL)
+#define HIF_STAT_TX (0xda1298ceUL)
+#define HIF_STAT_TX_COUNTER (0xd485b327UL)
+#define HIF_TEST0 (0xdab033c0UL)
+#define HIF_TEST0_DATA (0xb7f3cba2UL)
+#define HIF_TEST1 (0xadb70356UL)
+#define HIF_TEST1_DATA (0x7caf1807UL)
+#define HIF_TEST2 (0x34be52ecUL)
+#define HIF_TEST2_DATA (0xfa3b6aa9UL)
+#define HIF_TEST3 (0x43b9627aUL)
+#define HIF_TEST3_DATA (0x3167b90cUL)
+#define HIF_UUID0 (0xecba7918UL)
+#define HIF_UUID0_UUID0 (0x84b3f35eUL)
+#define HIF_UUID1 (0x9bbd498eUL)
+#define HIF_UUID1_UUID1 (0x55c3c87cUL)
+#define HIF_UUID2 (0x2b41834UL)
+#define HIF_UUID2_UUID2 (0xfd22835bUL)
+#define HIF_UUID3 (0x75b328a2UL)
+#define HIF_UUID3_UUID3 (0x2c52b879UL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_HIF_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_hsh.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_hsh.h
new file mode 100644
index 0000000000..9066e20dc9
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_hsh.h
@@ -0,0 +1,49 @@
+/*
+ * nthw_fpga_reg_defs_hsh.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_HSH_
+#define _NTHW_FPGA_REG_DEFS_HSH_
+
+/* HSH */
+#define NTHW_MOD_HSH (0x501484bfUL)
+#define HSH_RCP_CTRL (0xb257f1b9UL)
+#define HSH_RCP_CTRL_ADR (0x5685bfbUL)
+#define HSH_RCP_CTRL_CNT (0x1560c22aUL)
+#define HSH_RCP_DATA (0x1d8673a0UL)
+#define HSH_RCP_DATA_AUTO_IPV4_MASK (0xa0d4de3bUL)
+#define HSH_RCP_DATA_HSH_TYPE (0x14cd0865UL)
+#define HSH_RCP_DATA_HSH_VALID (0xc89b0bd3UL)
+#define HSH_RCP_DATA_K (0xccdb0222UL)
+#define HSH_RCP_DATA_LOAD_DIST_TYPE (0x152a0a87UL)
+#define HSH_RCP_DATA_MAC_PORT_MASK (0x5160b288UL)
+#define HSH_RCP_DATA_P_MASK (0x8a555abbUL)
+#define HSH_RCP_DATA_QW0_OFS (0x276b79cfUL)
+#define HSH_RCP_DATA_QW0_PE (0x32014a20UL)
+#define HSH_RCP_DATA_QW4_OFS (0xd2ebdf0fUL)
+#define HSH_RCP_DATA_QW4_PE (0xbd63dd77UL)
+#define HSH_RCP_DATA_SEED (0xf8fc2c1cUL)
+#define HSH_RCP_DATA_SORT (0xed5f3d38UL)
+#define HSH_RCP_DATA_TNL_P (0x6e56b51eUL)
+#define HSH_RCP_DATA_TOEPLITZ (0xc1864a45UL)
+#define HSH_RCP_DATA_W8_OFS (0x68150d02UL)
+#define HSH_RCP_DATA_W8_PE (0x9387d583UL)
+#define HSH_RCP_DATA_W8_SORT (0x5c67eca8UL)
+#define HSH_RCP_DATA_W9_OFS (0x557524b2UL)
+#define HSH_RCP_DATA_W9_P (0x808204d9UL)
+#define HSH_RCP_DATA_W9_PE (0x2b3bb2e6UL)
+#define HSH_RCP_DATA_W9_SORT (0x973b3f0dUL)
+#define HSH_RCP_DATA_WORD_MASK (0x55c53a1fUL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_HSH_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_i2cm.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_i2cm.h
new file mode 100644
index 0000000000..56248d5261
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_i2cm.h
@@ -0,0 +1,38 @@
+/*
+ * nthw_fpga_reg_defs_i2cm.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_I2CM_
+#define _NTHW_FPGA_REG_DEFS_I2CM_
+
+/* I2CM */
+#define NTHW_MOD_I2CM (0x93bc7780UL)
+#define I2CM_CMD_STATUS (0xcb66305bUL)
+#define I2CM_CMD_STATUS_CMD_STATUS (0x9c9460a9UL)
+#define I2CM_CTRL (0x7c06d3b0UL)
+#define I2CM_CTRL_EN (0x57d0a8aaUL)
+#define I2CM_CTRL_IEN (0x9fdc39ebUL)
+#define I2CM_DATA (0xd3d751a9UL)
+#define I2CM_DATA_DATA (0x2ea487faUL)
+#define I2CM_IO_EXP (0xe8dfa320UL)
+#define I2CM_IO_EXP_INT_B (0x85e5ff3fUL)
+#define I2CM_IO_EXP_RST (0x207c9928UL)
+#define I2CM_PRER_HIGH (0xf1139b49UL)
+#define I2CM_PRER_HIGH_PRER_HIGH (0xc6ff6431UL)
+#define I2CM_PRER_LOW (0x84f76481UL)
+#define I2CM_PRER_LOW_PRER_LOW (0x396755aaUL)
+#define I2CM_SELECT (0xecd56d8eUL)
+#define I2CM_SELECT_SELECT (0xb9d992d8UL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_I2CM_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_ifr.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_ifr.h
new file mode 100644
index 0000000000..fcf9193b7d
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_ifr.h
@@ -0,0 +1,41 @@
+/*
+ * nthw_fpga_reg_defs_ifr.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_IFR_
+#define _NTHW_FPGA_REG_DEFS_IFR_
+
+/* IFR */
+#define NTHW_MOD_IFR (0x9b01f1e6UL)
+#define IFR_COUNTERS_CTRL (0x92ba13e6UL)
+#define IFR_COUNTERS_CTRL_ADR (0xecdeeda8UL)
+#define IFR_COUNTERS_CTRL_CNT (0xfcd67479UL)
+#define IFR_COUNTERS_DATA (0x3d6b91ffUL)
+#define IFR_COUNTERS_DATA_DROP (0x3ee57cc0UL)
+#define IFR_DF_BUF_CTRL (0xf60805e4UL)
+#define IFR_DF_BUF_CTRL_AVAILABLE (0x158f09c3UL)
+#define IFR_DF_BUF_CTRL_MTU_PROFILE (0x7cb4bc5aUL)
+#define IFR_DF_BUF_DATA (0x59d987fdUL)
+#define IFR_DF_BUF_DATA_FIFO_DAT (0xdbfdf650UL)
+#define IFR_RCP_CTRL (0xc6dfc47eUL)
+#define IFR_RCP_CTRL_ADR (0x68600d59UL)
+#define IFR_RCP_CTRL_CNT (0x78689488UL)
+#define IFR_RCP_DATA (0x690e4667UL)
+#define IFR_RCP_DATA_IPV4_DF_DROP (0xbfd1ca18UL)
+#define IFR_RCP_DATA_IPV4_EN (0xb48ee13aUL)
+#define IFR_RCP_DATA_IPV6_DROP (0x4fbf34a2UL)
+#define IFR_RCP_DATA_IPV6_EN (0x1e8729b1UL)
+#define IFR_RCP_DATA_MTU (0xa436ee13UL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_IFR_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_igam.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_igam.h
new file mode 100644
index 0000000000..45c7516a48
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_igam.h
@@ -0,0 +1,28 @@
+/*
+ * nthw_fpga_reg_defs_igam.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_IGAM_
+#define _NTHW_FPGA_REG_DEFS_IGAM_
+
+/* IGAM */
+#define NTHW_MOD_IGAM (0xf3b0bfb9UL)
+#define IGAM_BASE (0xcdbfd276UL)
+#define IGAM_BASE_BUSY (0x2a018901UL)
+#define IGAM_BASE_CMD (0x61c2922dUL)
+#define IGAM_BASE_PTR (0x1076934dUL)
+#define IGAM_DATA (0xa0f8df74UL)
+#define IGAM_DATA_DATA (0x6544d6f2UL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_IGAM_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_iic.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_iic.h
new file mode 100644
index 0000000000..42a60cff12
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_iic.h
@@ -0,0 +1,96 @@
+/*
+ * nthw_fpga_reg_defs_iic.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_IIC_
+#define _NTHW_FPGA_REG_DEFS_IIC_
+
+/* IIC */
+#define NTHW_MOD_IIC (0x7629cddbUL)
+#define IIC_ADR (0x94832a56UL)
+#define IIC_ADR_SLV_ADR (0xe34a95b4UL)
+#define IIC_CR (0x2e99752eUL)
+#define IIC_CR_EN (0x38b0a8b8UL)
+#define IIC_CR_GC_EN (0x6a93c608UL)
+#define IIC_CR_MSMS (0xd3370cefUL)
+#define IIC_CR_RST (0x9d83289fUL)
+#define IIC_CR_RSTA (0xb3f49376UL)
+#define IIC_CR_TX (0x9fbd3ef9UL)
+#define IIC_CR_TXAK (0x4daa2c41UL)
+#define IIC_CR_TXFIFO_RESET (0x9d442d45UL)
+#define IIC_DGIE (0xca86a888UL)
+#define IIC_DGIE_GIE (0xda9f5b68UL)
+#define IIC_GPO (0xdda6ed68UL)
+#define IIC_GPO_GPO_VAL (0x6c51285eUL)
+#define IIC_IER (0x838b4aafUL)
+#define IIC_IER_INT0 (0x27d5f60eUL)
+#define IIC_IER_INT1 (0x50d2c698UL)
+#define IIC_IER_INT2 (0xc9db9722UL)
+#define IIC_IER_INT3 (0xbedca7b4UL)
+#define IIC_IER_INT4 (0x20b83217UL)
+#define IIC_IER_INT5 (0x57bf0281UL)
+#define IIC_IER_INT6 (0xceb6533bUL)
+#define IIC_IER_INT7 (0xb9b163adUL)
+#define IIC_ISR (0x9f13ff78UL)
+#define IIC_ISR_INT0 (0x23db5ffaUL)
+#define IIC_ISR_INT1 (0x54dc6f6cUL)
+#define IIC_ISR_INT2 (0xcdd53ed6UL)
+#define IIC_ISR_INT3 (0xbad20e40UL)
+#define IIC_ISR_INT4 (0x24b69be3UL)
+#define IIC_ISR_INT5 (0x53b1ab75UL)
+#define IIC_ISR_INT6 (0xcab8facfUL)
+#define IIC_ISR_INT7 (0xbdbfca59UL)
+#define IIC_RX_FIFO (0x46f255afUL)
+#define IIC_RX_FIFO_RXDATA (0x90c24f9dUL)
+#define IIC_RX_FIFO_OCY (0xc6457d11UL)
+#define IIC_RX_FIFO_OCY_OCY_VAL (0xee6b4716UL)
+#define IIC_RX_FIFO_PIRQ (0x4201f0b4UL)
+#define IIC_RX_FIFO_PIRQ_CMP_VAL (0xc5121291UL)
+#define IIC_SOFTR (0xfb3f55bfUL)
+#define IIC_SOFTR_RKEY (0x8c9a6beeUL)
+#define IIC_SR (0x645b677fUL)
+#define IIC_SR_AAS (0x66a5d25dUL)
+#define IIC_SR_ABGC (0x4831e30UL)
+#define IIC_SR_BB (0x1ea7e5d6UL)
+#define IIC_SR_RXFIFO_EMPTY (0xe419563UL)
+#define IIC_SR_RXFIFO_FULL (0x60ecb95aUL)
+#define IIC_SR_SRW (0x1f8520c8UL)
+#define IIC_SR_TXFIFO_EMPTY (0xe17c3083UL)
+#define IIC_SR_TXFIFO_FULL (0x88597319UL)
+#define IIC_TBUF (0xe32a311bUL)
+#define IIC_TBUF_TBUF_VAL (0xd48a5ee6UL)
+#define IIC_TEN_ADR (0xb5d88814UL)
+#define IIC_TEN_ADR_MSB_SLV_ADR (0x1bf3647bUL)
+#define IIC_THDDAT (0x9dc42de9UL)
+#define IIC_THDDAT_THDDAT_VAL (0xa4fe6780UL)
+#define IIC_THDSTA (0xdec59ae3UL)
+#define IIC_THDSTA_THDSTA_VAL (0xc3705793UL)
+#define IIC_THIGH (0x43194ec3UL)
+#define IIC_THIGH_THIGH_VAL (0x320d9d1bUL)
+#define IIC_TLOW (0x3329c638UL)
+#define IIC_TLOW_TLOW_VAL (0x167c1ff3UL)
+#define IIC_TSUDAT (0x6251bb80UL)
+#define IIC_TSUDAT_TSUDAT_VAL (0x7b1fdb1dUL)
+#define IIC_TSUSTA (0x21500c8aUL)
+#define IIC_TSUSTA_TSUSTA_VAL (0x1c91eb0eUL)
+#define IIC_TSUSTO (0xc6e8218dUL)
+#define IIC_TSUSTO_TSUSTO_VAL (0x4a908671UL)
+#define IIC_TX_FIFO (0x25226095UL)
+#define IIC_TX_FIFO_START (0xc24fb6c4UL)
+#define IIC_TX_FIFO_STOP (0xe7ae5f6cUL)
+#define IIC_TX_FIFO_TXDATA (0xbe59e736UL)
+#define IIC_TX_FIFO_OCY (0x2ef0b752UL)
+#define IIC_TX_FIFO_OCY_OCY_VAL (0x73b74c05UL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_IIC_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_ins.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_ins.h
new file mode 100644
index 0000000000..a4fffb11ab
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_ins.h
@@ -0,0 +1,29 @@
+/*
+ * nthw_fpga_reg_defs_ins.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_INS_
+#define _NTHW_FPGA_REG_DEFS_INS_
+
+/* INS */
+#define NTHW_MOD_INS (0x24df4b78UL)
+#define INS_RCP_CTRL (0x93de4e05UL)
+#define INS_RCP_CTRL_ADR (0x3ae620a8UL)
+#define INS_RCP_CTRL_CNT (0x2aeeb979UL)
+#define INS_RCP_DATA (0x3c0fcc1cUL)
+#define INS_RCP_DATA_DYN (0xc6aa4fccUL)
+#define INS_RCP_DATA_LEN (0x2ece4329UL)
+#define INS_RCP_DATA_OFS (0x64a3c26aUL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_INS_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_ioa.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_ioa.h
new file mode 100644
index 0000000000..dec8fccdbb
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_ioa.h
@@ -0,0 +1,44 @@
+/*
+ * nthw_fpga_reg_defs_ioa.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_IOA_
+#define _NTHW_FPGA_REG_DEFS_IOA_
+
+/* IOA */
+#define NTHW_MOD_IOA (0xce7d0b71UL)
+#define IOA_RECIPE_CTRL (0x3fd57501UL)
+#define IOA_RECIPE_CTRL_ADR (0xa12e8b86UL)
+#define IOA_RECIPE_CTRL_CNT (0xb1261257UL)
+#define IOA_RECIPE_DATA (0x9004f718UL)
+#define IOA_RECIPE_DATA_QUEUE_ID (0x7b82dc9eUL)
+#define IOA_RECIPE_DATA_QUEUE_OVERRIDE_EN (0x65468a0bUL)
+#define IOA_RECIPE_DATA_TUNNEL_POP (0xaa73a3b3UL)
+#define IOA_RECIPE_DATA_VLAN_DEI (0xf27320c4UL)
+#define IOA_RECIPE_DATA_VLAN_PCP (0xdb6d242eUL)
+#define IOA_RECIPE_DATA_VLAN_POP (0x77d86b22UL)
+#define IOA_RECIPE_DATA_VLAN_PUSH (0x458ecac5UL)
+#define IOA_RECIPE_DATA_VLAN_TPID_SEL (0xe1660623UL)
+#define IOA_RECIPE_DATA_VLAN_VID (0x3fd5646bUL)
+#define IOA_ROA_EPP_CTRL (0xab29dcacUL)
+#define IOA_ROA_EPP_CTRL_ADR (0x87edd55dUL)
+#define IOA_ROA_EPP_CTRL_CNT (0x97e54c8cUL)
+#define IOA_ROA_EPP_DATA (0x4f85eb5UL)
+#define IOA_ROA_EPP_DATA_PUSH_TUNNEL (0xc5d915c6UL)
+#define IOA_ROA_EPP_DATA_TX_PORT (0xb127a8d0UL)
+#define IOA_VLAN_TPID_SPECIAL (0x7812827cUL)
+#define IOA_VLAN_TPID_SPECIAL_CUSTTPID0 (0x4333af30UL)
+#define IOA_VLAN_TPID_SPECIAL_CUSTTPID1 (0x34349fa6UL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_IOA_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_ipf.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_ipf.h
new file mode 100644
index 0000000000..8dc7f26d71
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_ipf.h
@@ -0,0 +1,84 @@
+/*
+ * nthw_fpga_reg_defs_ipf.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_IPF_
+#define _NTHW_FPGA_REG_DEFS_IPF_
+
+/* IPF */
+#define NTHW_MOD_IPF (0x9d43904cUL)
+#define IPF_CTRL (0x3b50b688UL)
+#define IPF_CTRL_ALL_UNM (0x8b16703UL)
+#define IPF_CTRL_ALL_UNM_INNER (0x16068451UL)
+#define IPF_CTRL_DEL_UNM (0x7d86196cUL)
+#define IPF_CTRL_ENABLE (0xd827d73eUL)
+#define IPF_CTRL_FST_UNM (0x6f063580UL)
+#define IPF_CTRL_PASSIVE (0x441c1633UL)
+#define IPF_CTRL_PERSIST (0xf52aa922UL)
+#define IPF_DEBUG (0x4418698UL)
+#define IPF_DEBUG_FTF_N (0x2cda6a1fUL)
+#define IPF_DEBUG_LIMIT_N (0x8588c40eUL)
+#define IPF_EXPIRE (0xa1d1a3e0UL)
+#define IPF_EXPIRE_PERSIST (0x8d985989UL)
+#define IPF_EXPIRE_T (0x37792e51UL)
+#define IPF_FTF_DEBUG (0x2e34232dUL)
+#define IPF_FTF_DEBUG_N (0x59f772edUL)
+#define IPF_RCP_CTRL (0xaed9eb64UL)
+#define IPF_RCP_CTRL_ADR (0x71e6f593UL)
+#define IPF_RCP_CTRL_CNT (0x61ee6c42UL)
+#define IPF_RCP_DATA (0x108697dUL)
+#define IPF_RCP_DATA_ALL_UNM (0xe9fd243cUL)
+#define IPF_RCP_DATA_COL_INH (0x9da0e920UL)
+#define IPF_RCP_DATA_DEL_UNM (0x9cca5a53UL)
+#define IPF_RCP_DATA_DISC_INH (0x8914e9a0UL)
+#define IPF_RCP_DATA_DUP_INH (0x5f5a8cd0UL)
+#define IPF_RCP_DATA_ENABLE (0x9afcf075UL)
+#define IPF_RCP_DATA_FST_UNM (0x8e4a76bfUL)
+#define IPF_RCP_DATA_GROUP_ID (0xffc993cdUL)
+#define IPF_RCP_DATA_HASH_CENC (0x812cf8c7UL)
+#define IPF_RCP_DATA_HSH_INH (0x1e33d9faUL)
+#define IPF_RCP_DATA_PORT_GROUP_ID (0xd786e10bUL)
+#define IPF_RCP_DATA_QUEUE_INH (0x6cafcc65UL)
+#define IPF_RCP_DATA_UNMQ_HI (0xb6bb8520UL)
+#define IPF_RCP_DATA_UNMQ_LO (0x3bb4e511UL)
+#define IPF_RCP_DATA_UNM_FLAG_CENC (0xbb06fcddUL)
+#define IPF_SIZE_DEBUG (0xa3c27df1UL)
+#define IPF_SIZE_DEBUG_N (0xf8a909fbUL)
+#define IPF_STAT_MAX1 (0xbb09703fUL)
+#define IPF_STAT_MAX1_N (0xd361974dUL)
+#define IPF_STAT_MAX2 (0x22002185UL)
+#define IPF_STAT_MAX2_N (0xd1272914UL)
+#define IPF_STAT_MAX3 (0x55071113UL)
+#define IPF_STAT_MAX3_N (0xd0e54323UL)
+#define IPF_STAT_MAX4 (0xcb6384b0UL)
+#define IPF_STAT_MAX4_N (0xd5aa55a6UL)
+#define IPF_TIMEOUT (0x9b16c106UL)
+#define IPF_TIMEOUT_T (0x9ce14088UL)
+#define IPF_UNMQ_CTRL (0x9c6c2c32UL)
+#define IPF_UNMQ_CTRL_ADR (0x5a052e55UL)
+#define IPF_UNMQ_CTRL_CNT (0x4a0db784UL)
+#define IPF_UNMQ_DATA (0x33bdae2bUL)
+#define IPF_UNMQ_DATA_CENC (0xe444d471UL)
+#define IPF_UNMQ_DATA_EN (0x60b4924bUL)
+#define IPF_UNMQ_DATA_ID (0x2cd43459UL)
+#define IPF_UNM_FEED (0x5be1a729UL)
+#define IPF_UNM_FEED_ADDR (0x109a9424UL)
+#define IPF_UNM_FEED_CNT (0xab58226eUL)
+#define IPF_UNM_FEED_FEED (0x614042baUL)
+#define IPF_UNM_FEED_FEED_VALID (0xba08d9c3UL)
+#define IPF_UNM_FEED_RES1 (0x82ccb216UL)
+#define IPF_UNM_FEED_RES2 (0x1bc5e3acUL)
+#define IPF_UNM_FEED_RES3 (0x6cc2d33aUL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_IPF_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_km.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_km.h
new file mode 100644
index 0000000000..ec9a928eda
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_km.h
@@ -0,0 +1,125 @@
+/*
+ * nthw_fpga_reg_defs_km.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_KM_
+#define _NTHW_FPGA_REG_DEFS_KM_
+
+/* KM */
+#define NTHW_MOD_KM (0xcfbd9dbeUL)
+#define KM_CAM_CTRL (0x601dcc08UL)
+#define KM_CAM_CTRL_ADR (0xee5e10b0UL)
+#define KM_CAM_CTRL_CNT (0xfe568961UL)
+#define KM_CAM_DATA (0xcfcc4e11UL)
+#define KM_CAM_DATA_FT0 (0x138589ccUL)
+#define KM_CAM_DATA_FT1 (0x6482b95aUL)
+#define KM_CAM_DATA_FT2 (0xfd8be8e0UL)
+#define KM_CAM_DATA_FT3 (0x8a8cd876UL)
+#define KM_CAM_DATA_FT4 (0x14e84dd5UL)
+#define KM_CAM_DATA_FT5 (0x63ef7d43UL)
+#define KM_CAM_DATA_W0 (0xff7d6c5fUL)
+#define KM_CAM_DATA_W1 (0x887a5cc9UL)
+#define KM_CAM_DATA_W2 (0x11730d73UL)
+#define KM_CAM_DATA_W3 (0x66743de5UL)
+#define KM_CAM_DATA_W4 (0xf810a846UL)
+#define KM_CAM_DATA_W5 (0x8f1798d0UL)
+#define KM_RCP_CTRL (0xf8dbfdd1UL)
+#define KM_RCP_CTRL_ADR (0xf3df02baUL)
+#define KM_RCP_CTRL_CNT (0xe3d79b6bUL)
+#define KM_RCP_DATA (0x570a7fc8UL)
+#define KM_RCP_DATA_BANK_A (0x7fd7bd1UL)
+#define KM_RCP_DATA_BANK_B (0x9ef42a6bUL)
+#define KM_RCP_DATA_DUAL (0x428e6b23UL)
+#define KM_RCP_DATA_DW0_B_DYN (0x342bde5aUL)
+#define KM_RCP_DATA_DW0_B_OFS (0x962253fcUL)
+#define KM_RCP_DATA_DW10_DYN (0x54eccf30UL)
+#define KM_RCP_DATA_DW10_OFS (0xf6e54296UL)
+#define KM_RCP_DATA_DW10_SEL_A (0x6237e887UL)
+#define KM_RCP_DATA_DW10_SEL_B (0xfb3eb93dUL)
+#define KM_RCP_DATA_DW2_B_DYN (0xa3b4cf73UL)
+#define KM_RCP_DATA_DW2_B_OFS (0x1bd42d5UL)
+#define KM_RCP_DATA_DW8_B_DYN (0x7c4903dUL)
+#define KM_RCP_DATA_DW8_B_OFS (0xa5cd1d9bUL)
+#define KM_RCP_DATA_DW8_DYN (0x3f6b49f0UL)
+#define KM_RCP_DATA_DW8_OFS (0x9d62c456UL)
+#define KM_RCP_DATA_DW8_SEL_A (0xad16725bUL)
+#define KM_RCP_DATA_DW8_SEL_B (0x341f23e1UL)
+#define KM_RCP_DATA_EL_A (0x4335d7dbUL)
+#define KM_RCP_DATA_EL_B (0xda3c8661UL)
+#define KM_RCP_DATA_FLOW_SET (0x6b56d647UL)
+#define KM_RCP_DATA_FTM_A (0xdb75ed61UL)
+#define KM_RCP_DATA_FTM_B (0x427cbcdbUL)
+#define KM_RCP_DATA_INFO_A (0x2dd79cf0UL)
+#define KM_RCP_DATA_INFO_B (0xb4decd4aUL)
+#define KM_RCP_DATA_KEYWAY_A (0xd0e5dc89UL)
+#define KM_RCP_DATA_KEYWAY_B (0x49ec8d33UL)
+#define KM_RCP_DATA_KL_A (0xa3eaa0e8UL)
+#define KM_RCP_DATA_KL_B (0x3ae3f152UL)
+#define KM_RCP_DATA_MASK_A (0x54d84646UL)
+#define KM_RCP_DATA_MASK_B (0xcdd117fcUL)
+#define KM_RCP_DATA_PAIRED (0x7847653UL)
+#define KM_RCP_DATA_QW0_B_DYN (0xd27cd964UL)
+#define KM_RCP_DATA_QW0_B_OFS (0x707554c2UL)
+#define KM_RCP_DATA_QW0_DYN (0x3afdb158UL)
+#define KM_RCP_DATA_QW0_OFS (0x98f43cfeUL)
+#define KM_RCP_DATA_QW0_SEL_A (0x78ae3b02UL)
+#define KM_RCP_DATA_QW0_SEL_B (0xe1a76ab8UL)
+#define KM_RCP_DATA_QW4_B_DYN (0x2633fd77UL)
+#define KM_RCP_DATA_QW4_B_OFS (0x843a70d1UL)
+#define KM_RCP_DATA_QW4_DYN (0xcf7d1798UL)
+#define KM_RCP_DATA_QW4_OFS (0x6d749a3eUL)
+#define KM_RCP_DATA_QW4_SEL_A (0x8ce11f11UL)
+#define KM_RCP_DATA_QW4_SEL_B (0x15e84eabUL)
+#define KM_RCP_DATA_SW4_B_DYN (0x8c5d5f1UL)
+#define KM_RCP_DATA_SW4_B_OFS (0xaacc5857UL)
+#define KM_RCP_DATA_SW5_B_DYN (0xaeb2de45UL)
+#define KM_RCP_DATA_SW5_B_OFS (0xcbb53e3UL)
+#define KM_RCP_DATA_SW8_B_DYN (0xcf65bf85UL)
+#define KM_RCP_DATA_SW8_B_OFS (0x6d6c3223UL)
+#define KM_RCP_DATA_SW8_DYN (0x9d12ebb0UL)
+#define KM_RCP_DATA_SW8_OFS (0x3f1b6616UL)
+#define KM_RCP_DATA_SW8_SEL_A (0x65b75de3UL)
+#define KM_RCP_DATA_SW8_SEL_B (0xfcbe0c59UL)
+#define KM_RCP_DATA_SW9_B_DYN (0x6912b431UL)
+#define KM_RCP_DATA_SW9_B_OFS (0xcb1b3997UL)
+#define KM_RCP_DATA_SW9_DYN (0xa072c200UL)
+#define KM_RCP_DATA_SW9_OFS (0x27b4fa6UL)
+#define KM_RCP_DATA_SW9_SEL_A (0xc3c05657UL)
+#define KM_RCP_DATA_SW9_SEL_B (0x5ac907edUL)
+#define KM_RCP_DATA_SWX_CCH (0x5821d596UL)
+#define KM_RCP_DATA_SWX_OVS_SB (0x808773bdUL)
+#define KM_RCP_DATA_SWX_SEL_A (0xee011106UL)
+#define KM_RCP_DATA_SWX_SEL_B (0x770840bcUL)
+#define KM_RCP_DATA_SYNERGY_MODE (0x35a76c4aUL)
+#define KM_STATUS (0x2f1f9d13UL)
+#define KM_STATUS_TCQ_RDY (0x653553c4UL)
+#define KM_TCAM_CTRL (0x18fbc021UL)
+#define KM_TCAM_CTRL_ADR (0x6c84a404UL)
+#define KM_TCAM_CTRL_CNT (0x7c8c3dd5UL)
+#define KM_TCAM_DATA (0xb72a4238UL)
+#define KM_TCAM_DATA_T (0xa995a553UL)
+#define KM_TCI_CTRL (0x1a6da705UL)
+#define KM_TCI_CTRL_ADR (0xc7590d78UL)
+#define KM_TCI_CTRL_CNT (0xd75194a9UL)
+#define KM_TCI_DATA (0xb5bc251cUL)
+#define KM_TCI_DATA_COLOR (0x324017ecUL)
+#define KM_TCI_DATA_FT (0x38afba77UL)
+#define KM_TCQ_CTRL (0xf5e827f3UL)
+#define KM_TCQ_CTRL_ADR (0xf320cc64UL)
+#define KM_TCQ_CTRL_CNT (0xe32855b5UL)
+#define KM_TCQ_DATA (0x5a39a5eaUL)
+#define KM_TCQ_DATA_BANK_MASK (0x97cf4b5aUL)
+#define KM_TCQ_DATA_QUAL (0x4422cc93UL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_KM_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac.h
new file mode 100644
index 0000000000..6c2014e468
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac.h
@@ -0,0 +1,177 @@
+/*
+ * nthw_fpga_reg_defs_mac.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_MAC_
+#define _NTHW_FPGA_REG_DEFS_MAC_
+
+/* MAC */
+#define NTHW_MOD_MAC (0xb9f9ef0fUL)
+#define MAC_CONF_SERDES_BITFRAG (0xb22a0224UL)
+#define MAC_CONF_SERDES_BITFRAG_BITFRAG (0x4980ae1bUL)
+#define MAC_CONF_SERDES_DELAY (0xb106e3baUL)
+#define MAC_CONF_SERDES_DELAY_DELAY (0x3a5a3634UL)
+#define MAC_CONF_SERDES_REORDER (0x7b67c6e7UL)
+#define MAC_CONF_SERDES_REORDER_REORDER (0x1b75028cUL)
+#define MAC_FAULTY_BLK (0x221eb456UL)
+#define MAC_FAULTY_BLK_DATA (0x96b88c4fUL)
+#define MAC_HOST_STAT_BYTE_FILL (0xbb1fc15cUL)
+#define MAC_HOST_STAT_BYTE_FILL_CNT (0x91d6eb19UL)
+#define MAC_INT (0x9100902fUL)
+#define MAC_INT_EN (0x93a8ee79UL)
+#define MAC_INT_MAX_PACE (0x65054b07UL)
+#define MAC_LINK_SUMMARY (0x7f2f60ceUL)
+#define MAC_LINK_SUMMARY_ABS (0x2c3fcbfaUL)
+#define MAC_LINK_SUMMARY_GBOX_INTERR (0x35d304b0UL)
+#define MAC_LINK_SUMMARY_GLB_ALARMN (0x8eac9ca9UL)
+#define MAC_LINK_SUMMARY_LH_ABS (0x24f77279UL)
+#define MAC_LINK_SUMMARY_LH_GLB_ALARMN (0x1646a58eUL)
+#define MAC_LINK_SUMMARY_LH_LOCAL_FAULT (0x36543c21UL)
+#define MAC_LINK_SUMMARY_LH_REMOTE_FAULT (0x97481576UL)
+#define MAC_LINK_SUMMARY_LH_RX_LOS (0x837691acUL)
+#define MAC_LINK_SUMMARY_LINK_DOWN_CNT (0x1879082dUL)
+#define MAC_LINK_SUMMARY_LL_PHY_LINK_STATE (0x64cc82a2UL)
+#define MAC_LINK_SUMMARY_LOCAL_FAULT (0x93c66373UL)
+#define MAC_LINK_SUMMARY_NT_PHY_LINK_STATE (0x25c4b3b4UL)
+#define MAC_LINK_SUMMARY_REMOTE_FAULT (0x1288b7f1UL)
+#define MAC_LINK_SUMMARY_RX_LOS (0xc0bd6b0eUL)
+#define MAC_MAC_STAT_BYTE (0x7c8bb288UL)
+#define MAC_MAC_STAT_BYTE_CNT (0x7e7a0bd3UL)
+#define MAC_MAC_STAT_CRC (0x39d27996UL)
+#define MAC_MAC_STAT_CRC_CNT (0x3e8901dcUL)
+#define MAC_MAC_STAT_CV (0xd9cde09fUL)
+#define MAC_MAC_STAT_CV_CNT (0xdc1321cfUL)
+#define MAC_MAC_STAT_FRAME (0xc71e1060UL)
+#define MAC_MAC_STAT_FRAME_CNT (0xe7c8ff51UL)
+#define MAC_MAC_STAT_MICRO_DROP (0xe4d098cbUL)
+#define MAC_MAC_STAT_MICRO_DROP_CNT (0x659aa0dfUL)
+#define MAC_MAC_STAT_RATE_DROP (0x403c4fbbUL)
+#define MAC_MAC_STAT_RATE_DROP_CNT (0xa513f8e7UL)
+#define MAC_MAC_STAT_TRUNC (0x45f29d8UL)
+#define MAC_MAC_STAT_TRUNC_CNT (0xffbbaa75UL)
+#define MAC_MDS_CEN_VAL (0xa9a494fdUL)
+#define MAC_MDS_CEN_VAL_VAL (0x74e79a1bUL)
+#define MAC_MDS_CONF (0xd4f79721UL)
+#define MAC_MDS_CONF_CENTER_REC_ENA (0x61ec9442UL)
+#define MAC_MDS_CONF_CLR_STAT (0xdc56da95UL)
+#define MAC_MDS_CONF_ENA_TS_MOD (0xf071678dUL)
+#define MAC_MDS_CONF_REC_ENA (0x9c1d77c5UL)
+#define MAC_MDS_CONF_TIME_MODE (0x4f2a4dcaUL)
+#define MAC_MDS_DATA (0x6df7edeaUL)
+#define MAC_MDS_DATA_DATA (0x24589197UL)
+#define MAC_MDS_FRAMES (0x40ca5335UL)
+#define MAC_MDS_FRAMES_CNT (0xff4f25c0UL)
+#define MAC_MDS_MAX (0x230406d6UL)
+#define MAC_MDS_MAX_MAX (0x54809081UL)
+#define MAC_MDS_MIN (0x1f09398fUL)
+#define MAC_MDS_MIN_MIN (0x6b7e4f97UL)
+#define MAC_MDS_STAT (0xe0bce1a8UL)
+#define MAC_MDS_STAT_CLR_BUSY (0x4a5ac60dUL)
+#define MAC_MDS_STAT_HIT_MAX (0xe5a34512UL)
+#define MAC_MDS_STAT_HIT_MIN (0xd9ae7a4bUL)
+#define MAC_MDS_VAL_REC (0x8ec946abUL)
+#define MAC_MDS_VAL_REC_VALUE (0xe4e373beUL)
+#define MAC_MDS_VAL_REC_FRAME (0x8c12c923UL)
+#define MAC_MDS_VAL_REC_FRAME_VALUE (0xd76728beUL)
+#define MAC_NT_PORT_CTRL (0x8cd09e7cUL)
+#define MAC_NT_PORT_CTRL_LED_MODE (0x8486e464UL)
+#define MAC_RAM_MDS_ADDR (0xad17b5f2UL)
+#define MAC_RAM_MDS_ADDR_ADR (0x439fe32bUL)
+#define MAC_RAM_MDS_ADDR_CLR_RAM (0x824a2a22UL)
+#define MAC_RAM_MDS_ADDR_RD_DONE (0x4d858fc4UL)
+#define MAC_RAM_MDS_ADDR_RD_ENA (0xb0e2aae4UL)
+#define MAC_RAW_ADDR (0xfeacc28aUL)
+#define MAC_RAW_ADDR_ADR (0x49f962b0UL)
+#define MAC_RAW_ADDR_RDENA (0x57a8bee0UL)
+#define MAC_RAW_ADDR_RD_DONE (0x1441bde9UL)
+#define MAC_RAW_CTRL (0xae1421c5UL)
+#define MAC_RAW_CTRL_OVERWR_LM (0x4b06da1cUL)
+#define MAC_RAW_CTRL_RESTART (0xc0d2b66fUL)
+#define MAC_RAW_CTRL_TG_ACT (0x40471be4UL)
+#define MAC_RAW_CTRL_TG_ENA (0x9f3d299eUL)
+#define MAC_RAW_CTRL_WRAP (0x11e8b136UL)
+#define MAC_RAW_DATA (0x1c5a3dcUL)
+#define MAC_RAW_DATA_RAW_DATA (0xcb2757bcUL)
+#define MAC_RAW_REPETITION (0xbbec07c6UL)
+#define MAC_RAW_REPETITION_CNT (0xe998b255UL)
+#define MAC_RX_CONFIG (0x69191a34UL)
+#define MAC_RX_CONFIG_DESCRAMB (0xcd5890eUL)
+#define MAC_RX_CONFIG_HOST_CLR_CNT (0xb1ea5438UL)
+#define MAC_RX_CONFIG_MAC_CLR_CNT (0x5181c6edUL)
+#define MAC_RX_CONFIG_MIN_RX_FRAME (0xcf749efeUL)
+#define MAC_RX_CONFIG_NT_DEBOUNCE_LATENCY (0x39a4b7f3UL)
+#define MAC_RX_CONFIG_NT_FORCE_LINK_DOWN (0x361dbc83UL)
+#define MAC_RX_CONFIG_NT_LINKUP_LATENCY (0xe25cf44aUL)
+#define MAC_RX_CONFIG_RST_BLK_ERR (0x476bf210UL)
+#define MAC_RX_CONFIG_RX_MAC_EN (0xbcb6ab91UL)
+#define MAC_RX_CONFIG_TS_EOP (0xc648dd62UL)
+#define MAC_RX_CONFIG_TXRX_LOOP (0x66156fdfUL)
+#define MAC_RX_CONFIG2 (0x3b0853a2UL)
+#define MAC_RX_CONFIG2_NT_MOD_ABS_MASK_INT (0x15c7f251UL)
+#define MAC_RX_CONFIG2_NT_MOD_ABS_MASK_LINK (0xadc9cd69UL)
+#define MAC_RX_CONFIG2_NT_MOD_ABS_MASK_RST (0xfad8d2dcUL)
+#define MAC_RX_CONFIG2_NT_RXLOS_MASK_INT (0x76a6fa30UL)
+#define MAC_RX_CONFIG2_NT_RXLOS_MASK_LINK (0x971ffdafUL)
+#define MAC_RX_CONFIG2_NT_RXLOS_MASK_RST (0x99b9dabdUL)
+#define MAC_RX_STATUS (0xc6935054UL)
+#define MAC_RX_STATUS_CORE_MODE (0xb8548429UL)
+#define MAC_RX_STATUS_LOCAL_FAULT (0x4d495f63UL)
+#define MAC_RX_STATUS_REMOTE_FAULT (0xfe128a9UL)
+#define MAC_RX_STATUS_RXTX_OVERFLOW (0xc63536a2UL)
+#define MAC_RX_STATUS_VERSION (0x9bf530b7UL)
+#define MAC_TFG_ADDR (0xfeb2f718UL)
+#define MAC_TFG_ADDR_ADR (0xa851533bUL)
+#define MAC_TFG_ADDR_RDENA (0xde011ef2UL)
+#define MAC_TFG_ADDR_RD_DONE (0xba63e77bUL)
+#define MAC_TFG_CTRL (0xae0a1457UL)
+#define MAC_TFG_CTRL_ID_ENA (0x94e59ae3UL)
+#define MAC_TFG_CTRL_ID_POS (0x64aabb71UL)
+#define MAC_TFG_CTRL_RESTART (0x6ef0ecfdUL)
+#define MAC_TFG_CTRL_TG_ACT (0xb377c30cUL)
+#define MAC_TFG_CTRL_TG_ENA (0x6c0df176UL)
+#define MAC_TFG_CTRL_TIME_MODE (0xc7d30a61UL)
+#define MAC_TFG_CTRL_WRAP (0x6b6343afUL)
+#define MAC_TFG_DATA (0x1db964eUL)
+#define MAC_TFG_DATA_GAP (0x1eb74eaUL)
+#define MAC_TFG_DATA_ID (0xd1864536UL)
+#define MAC_TFG_DATA_LENGTH (0xdb3bb77fUL)
+#define MAC_TFG_FRAME_HDR (0xd36f87edUL)
+#define MAC_TFG_FRAME_HDR_HDR (0x33800156UL)
+#define MAC_TFG_REPETITION (0x3245a7d4UL)
+#define MAC_TFG_REPETITION_CNT (0x21514c05UL)
+#define MAC_TX_CONFIG (0x1a0363beUL)
+#define MAC_TX_CONFIG_CLR_STICKY (0x170875aUL)
+#define MAC_TX_CONFIG_CRC_ERR_INS (0xf0ac9462UL)
+#define MAC_TX_CONFIG_HOST_TX_ENA (0x5593f749UL)
+#define MAC_TX_CONFIG_MAC_LOOP (0x34b86cc7UL)
+#define MAC_TX_CONFIG_PCS_BIP_ERR (0xed089516UL)
+#define MAC_TX_CONFIG_PCS_DIS_BIP_INS (0xce7f1bc7UL)
+#define MAC_TX_CONFIG_PCS_IDLE (0x3a34f374UL)
+#define MAC_TX_CONFIG_PCS_IDLE_DIS (0x3899c1f1UL)
+#define MAC_TX_CONFIG_PCS_LOCAL_FAULT (0xdfeb9ecdUL)
+#define MAC_TX_CONFIG_PCS_LOCAL_FAULT_DIS (0xce2c57b5UL)
+#define MAC_TX_CONFIG_PCS_REMOTE_FAULT (0x3e1d0487UL)
+#define MAC_TX_CONFIG_PCS_REMOTE_FAULT_DIS (0x5fea461fUL)
+#define MAC_TX_CONFIG_PCS_SCRAMB_ENA (0xaa28e162UL)
+#define MAC_TX_CONFIG_PCS_SCRAMB_ERR (0xc8e1fde1UL)
+#define MAC_TX_CONFIG_TIME_OFFSET_TX (0x78fff470UL)
+#define MAC_TX_CONFIG_TS_EOP (0x95d9b486UL)
+#define MAC_TX_STATUS (0xb58929deUL)
+#define MAC_TX_STATUS_PCS_ERR (0x1c890ea7UL)
+#define MAC_TX_STATUS_TX_MAC_ST (0x5ac922d9UL)
+#define MAC_TX_STATUS_UNDER_FLOW (0x49718623UL)
+#define MAC_UPD_RX_COUNTERS (0x82256265UL)
+#define MAC_UPD_RX_COUNTERS_TRIGGER (0x29f90550UL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_MAC_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_pcs.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_pcs.h
new file mode 100644
index 0000000000..3ad544798c
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_pcs.h
@@ -0,0 +1,298 @@
+/*
+ * nthw_fpga_reg_defs_mac_pcs.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_MAC_PCS_
+#define _NTHW_FPGA_REG_DEFS_MAC_PCS_
+
+/* MAC_PCS */
+#define NTHW_MOD_MAC_PCS (0x7abe24c7UL)
+#define MAC_PCS_BAD_CODE (0x10d9fce5UL)
+#define MAC_PCS_BAD_CODE_CODE_ERR (0xb08ecc3fUL)
+#define MAC_PCS_BIP_ERR (0x7aead929UL)
+#define MAC_PCS_BIP_ERR_BIP_ERR (0x7e06ff82UL)
+#define MAC_PCS_BLOCK_LOCK (0xa44a8a0bUL)
+#define MAC_PCS_BLOCK_LOCK_LOCK (0x6adfd96bUL)
+#define MAC_PCS_BLOCK_LOCK_CHG (0xf0603b66UL)
+#define MAC_PCS_BLOCK_LOCK_CHG_LOCK_CHG (0x9ef4519dUL)
+#define MAC_PCS_CLKRX_FRQ (0x999882b5UL)
+#define MAC_PCS_CLKRX_FRQ_RX_FREQ (0x8b935059UL)
+#define MAC_PCS_CLKTX_FRQ (0x4fc161a8UL)
+#define MAC_PCS_CLKTX_FRQ_TX_FREQ (0x10812ed5UL)
+#define MAC_PCS_DEBOUNCE_CTRL (0x37a3bb69UL)
+#define MAC_PCS_DEBOUNCE_CTRL_NT_DEBOUNCE_LATENCY (0xf5845748UL)
+#define MAC_PCS_DEBOUNCE_CTRL_NT_FORCE_LINK_DOWN (0x1a8a9237UL)
+#define MAC_PCS_DEBOUNCE_CTRL_NT_LINKUP_LATENCY (0xaceccbf4UL)
+#define MAC_PCS_DEBOUNCE_CTRL_NT_PORT_CTRL (0x7f66469eUL)
+#define MAC_PCS_DRP_CONFIG (0x1281f4d8UL)
+#define MAC_PCS_DRP_CONFIG_DRP_ADR (0x398caa76UL)
+#define MAC_PCS_DRP_CONFIG_DRP_DI (0x83b54c6fUL)
+#define MAC_PCS_DRP_CONFIG_DRP_EN (0x4cae88dUL)
+#define MAC_PCS_DRP_CONFIG_DRP_MOD_ADR (0xc24d1deaUL)
+#define MAC_PCS_DRP_CONFIG_DRP_WREN (0x926388aeUL)
+#define MAC_PCS_DRP_CTRL (0x6df0725eUL)
+#define MAC_PCS_DRP_CTRL_ADR (0x5a9962c8UL)
+#define MAC_PCS_DRP_CTRL_DATA (0x2173d834UL)
+#define MAC_PCS_DRP_CTRL_DBG_BUSY (0x26dd3668UL)
+#define MAC_PCS_DRP_CTRL_DONE (0x9cadcbfcUL)
+#define MAC_PCS_DRP_CTRL_MOD_ADR (0x4352354dUL)
+#define MAC_PCS_DRP_CTRL_WREN (0xbed903edUL)
+#define MAC_PCS_DRP_DATA (0xc221f047UL)
+#define MAC_PCS_DRP_DATA_DRP_DO (0xbeb48b96UL)
+#define MAC_PCS_DRP_DATA_DRP_RDY (0x2238822eUL)
+#define MAC_PCS_FEC_CTRL (0x8eea756UL)
+#define MAC_PCS_FEC_CTRL_RS_FEC_CTRL_IN (0xd0c0525eUL)
+#define MAC_PCS_FEC_CW_CNT (0x59e0c4deUL)
+#define MAC_PCS_FEC_CW_CNT_CW_CNT (0xd0b8ee0UL)
+#define MAC_PCS_FEC_ERR_CNT_0 (0xee88619cUL)
+#define MAC_PCS_FEC_ERR_CNT_0_ERR_CNT (0x4fdf126bUL)
+#define MAC_PCS_FEC_ERR_CNT_1 (0x998f510aUL)
+#define MAC_PCS_FEC_ERR_CNT_1_ERR_CNT (0x58a40628UL)
+#define MAC_PCS_FEC_ERR_CNT_2 (0x8600b0UL)
+#define MAC_PCS_FEC_ERR_CNT_2_ERR_CNT (0x61293aedUL)
+#define MAC_PCS_FEC_ERR_CNT_3 (0x77813026UL)
+#define MAC_PCS_FEC_ERR_CNT_3_ERR_CNT (0x76522eaeUL)
+#define MAC_PCS_FEC_LANE_DLY_0 (0xc18f945eUL)
+#define MAC_PCS_FEC_LANE_DLY_0_DLY (0xd9f1d54bUL)
+#define MAC_PCS_FEC_LANE_DLY_1 (0xb688a4c8UL)
+#define MAC_PCS_FEC_LANE_DLY_1_DLY (0xe491fcfbUL)
+#define MAC_PCS_FEC_LANE_DLY_2 (0x2f81f572UL)
+#define MAC_PCS_FEC_LANE_DLY_2_DLY (0xa331862bUL)
+#define MAC_PCS_FEC_LANE_DLY_3 (0x5886c5e4UL)
+#define MAC_PCS_FEC_LANE_DLY_3_DLY (0x9e51af9bUL)
+#define MAC_PCS_FEC_LANE_MAP (0x21d4bd54UL)
+#define MAC_PCS_FEC_LANE_MAP_MAPPING (0x87d12932UL)
+#define MAC_PCS_FEC_STAT (0x2a74290dUL)
+#define MAC_PCS_FEC_STAT_AM_LOCK (0x289b2822UL)
+#define MAC_PCS_FEC_STAT_AM_LOCK_0 (0xc824a589UL)
+#define MAC_PCS_FEC_STAT_AM_LOCK_1 (0xbf23951fUL)
+#define MAC_PCS_FEC_STAT_AM_LOCK_2 (0x262ac4a5UL)
+#define MAC_PCS_FEC_STAT_AM_LOCK_3 (0x512df433UL)
+#define MAC_PCS_FEC_STAT_BLOCK_LOCK (0x6a7d0f5fUL)
+#define MAC_PCS_FEC_STAT_BYPASS (0x2e754185UL)
+#define MAC_PCS_FEC_STAT_FEC_LANE_ALGN (0xfd302594UL)
+#define MAC_PCS_FEC_STAT_HI_SER (0xc3501768UL)
+#define MAC_PCS_FEC_STAT_PCS_LANE_ALGN (0xa8193db8UL)
+#define MAC_PCS_FEC_STAT_VALID (0x90dd6fe1UL)
+#define MAC_PCS_FEC_UCW_CNT (0xd1354660UL)
+#define MAC_PCS_FEC_UCW_CNT_UCW_CNT (0xf90f900UL)
+#define MAC_PCS_FRAMING_ERR (0x73b6341dUL)
+#define MAC_PCS_FRAMING_ERR_FRAMING_ERR (0xd4bfdbf4UL)
+#define MAC_PCS_GTY_CTL (0x325263edUL)
+#define MAC_PCS_GTY_CTL_CDR_HOLD_0 (0x423e0e64UL)
+#define MAC_PCS_GTY_CTL_CDR_HOLD_1 (0x35393ef2UL)
+#define MAC_PCS_GTY_CTL_CDR_HOLD_2 (0xac306f48UL)
+#define MAC_PCS_GTY_CTL_CDR_HOLD_3 (0xdb375fdeUL)
+#define MAC_PCS_GTY_CTL_RX (0x1f131df2UL)
+#define MAC_PCS_GTY_CTL_RX_CDR_HOLD_0 (0x3c2aeb81UL)
+#define MAC_PCS_GTY_CTL_RX_CDR_HOLD_1 (0x4b2ddb17UL)
+#define MAC_PCS_GTY_CTL_RX_CDR_HOLD_2 (0xd2248aadUL)
+#define MAC_PCS_GTY_CTL_RX_CDR_HOLD_3 (0xa523ba3bUL)
+#define MAC_PCS_GTY_CTL_RX_EQUA_RST_0 (0x78b8f7dbUL)
+#define MAC_PCS_GTY_CTL_RX_EQUA_RST_1 (0xfbfc74dUL)
+#define MAC_PCS_GTY_CTL_RX_EQUA_RST_2 (0x96b696f7UL)
+#define MAC_PCS_GTY_CTL_RX_EQUA_RST_3 (0xe1b1a661UL)
+#define MAC_PCS_GTY_CTL_RX_LPM_EN_0 (0xce64b22bUL)
+#define MAC_PCS_GTY_CTL_RX_LPM_EN_1 (0xb96382bdUL)
+#define MAC_PCS_GTY_CTL_RX_LPM_EN_2 (0x206ad307UL)
+#define MAC_PCS_GTY_CTL_RX_LPM_EN_3 (0x576de391UL)
+#define MAC_PCS_GTY_CTL_RX_POLARITY_0 (0x80681033UL)
+#define MAC_PCS_GTY_CTL_RX_POLARITY_1 (0xf76f20a5UL)
+#define MAC_PCS_GTY_CTL_RX_POLARITY_2 (0x6e66711fUL)
+#define MAC_PCS_GTY_CTL_RX_POLARITY_3 (0x19614189UL)
+#define MAC_PCS_GTY_CTL_RX_RATE_0 (0x6c6c737dUL)
+#define MAC_PCS_GTY_CTL_RX_RATE_1 (0x1b6b43ebUL)
+#define MAC_PCS_GTY_CTL_RX_RATE_2 (0x82621251UL)
+#define MAC_PCS_GTY_CTL_RX_RATE_3 (0xf56522c7UL)
+#define MAC_PCS_GTY_CTL_TX (0x4949ba74UL)
+#define MAC_PCS_GTY_CTL_TX_INHIBIT_0 (0xd2423364UL)
+#define MAC_PCS_GTY_CTL_TX_INHIBIT_1 (0xa54503f2UL)
+#define MAC_PCS_GTY_CTL_TX_INHIBIT_2 (0x3c4c5248UL)
+#define MAC_PCS_GTY_CTL_TX_INHIBIT_3 (0x4b4b62deUL)
+#define MAC_PCS_GTY_CTL_TX_POLARITY_0 (0x208dcfeeUL)
+#define MAC_PCS_GTY_CTL_TX_POLARITY_1 (0x578aff78UL)
+#define MAC_PCS_GTY_CTL_TX_POLARITY_2 (0xce83aec2UL)
+#define MAC_PCS_GTY_CTL_TX_POLARITY_3 (0xb9849e54UL)
+#define MAC_PCS_GTY_DIFF_CTL (0x8756c12fUL)
+#define MAC_PCS_GTY_DIFF_CTL_TX_DIFF_CTL_0 (0xf08ceefdUL)
+#define MAC_PCS_GTY_DIFF_CTL_TX_DIFF_CTL_1 (0x878bde6bUL)
+#define MAC_PCS_GTY_DIFF_CTL_TX_DIFF_CTL_2 (0x1e828fd1UL)
+#define MAC_PCS_GTY_DIFF_CTL_TX_DIFF_CTL_3 (0x6985bf47UL)
+#define MAC_PCS_GTY_LOOP (0x4dd7ddbUL)
+#define MAC_PCS_GTY_LOOP_GT_LOOP_0 (0xd55e5438UL)
+#define MAC_PCS_GTY_LOOP_GT_LOOP_1 (0xa25964aeUL)
+#define MAC_PCS_GTY_LOOP_GT_LOOP_2 (0x3b503514UL)
+#define MAC_PCS_GTY_LOOP_GT_LOOP_3 (0x4c570582UL)
+#define MAC_PCS_GTY_POST_CURSOR (0x4699c607UL)
+#define MAC_PCS_GTY_POST_CURSOR_TX_POST_CSR_0 (0x23ff66e9UL)
+#define MAC_PCS_GTY_POST_CURSOR_TX_POST_CSR_1 (0x54f8567fUL)
+#define MAC_PCS_GTY_POST_CURSOR_TX_POST_CSR_2 (0xcdf107c5UL)
+#define MAC_PCS_GTY_POST_CURSOR_TX_POST_CSR_3 (0xbaf63753UL)
+#define MAC_PCS_GTY_PRBS_SEL (0x6610ec4eUL)
+#define MAC_PCS_GTY_PRBS_SEL_RX_PRBS_SEL_0 (0xb535fd56UL)
+#define MAC_PCS_GTY_PRBS_SEL_RX_PRBS_SEL_1 (0xc232cdc0UL)
+#define MAC_PCS_GTY_PRBS_SEL_RX_PRBS_SEL_2 (0x5b3b9c7aUL)
+#define MAC_PCS_GTY_PRBS_SEL_RX_PRBS_SEL_3 (0x2c3cacecUL)
+#define MAC_PCS_GTY_PRBS_SEL_TX_PRBS_SEL_0 (0x15d0228bUL)
+#define MAC_PCS_GTY_PRBS_SEL_TX_PRBS_SEL_1 (0x62d7121dUL)
+#define MAC_PCS_GTY_PRBS_SEL_TX_PRBS_SEL_2 (0xfbde43a7UL)
+#define MAC_PCS_GTY_PRBS_SEL_TX_PRBS_SEL_3 (0x8cd97331UL)
+#define MAC_PCS_GTY_PRE_CURSOR (0x989e0463UL)
+#define MAC_PCS_GTY_PRE_CURSOR_TX_PRE_CSR_0 (0x264242bdUL)
+#define MAC_PCS_GTY_PRE_CURSOR_TX_PRE_CSR_1 (0x5145722bUL)
+#define MAC_PCS_GTY_PRE_CURSOR_TX_PRE_CSR_2 (0xc84c2391UL)
+#define MAC_PCS_GTY_PRE_CURSOR_TX_PRE_CSR_3 (0xbf4b1307UL)
+#define MAC_PCS_GTY_RX_BUF_STAT (0xf37901e8UL)
+#define MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_0 (0xab8b9404UL)
+#define MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_1 (0xdc8ca492UL)
+#define MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_2 (0x4585f528UL)
+#define MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_3 (0x3282c5beUL)
+#define MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_CHANGED_0 (0x476782c4UL)
+#define MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_CHANGED_1 (0x3060b252UL)
+#define MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_CHANGED_2 (0xa969e3e8UL)
+#define MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_CHANGED_3 (0xde6ed37eUL)
+#define MAC_PCS_GTY_SCAN_CTL (0x782ddd2aUL)
+#define MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_RST_0 (0xc2791c66UL)
+#define MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_RST_1 (0xb57e2cf0UL)
+#define MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_RST_2 (0x2c777d4aUL)
+#define MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_RST_3 (0x5b704ddcUL)
+#define MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_TRG_0 (0xebe5938aUL)
+#define MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_TRG_1 (0x9ce2a31cUL)
+#define MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_TRG_2 (0x5ebf2a6UL)
+#define MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_TRG_3 (0x72ecc230UL)
+#define MAC_PCS_GTY_SCAN_CTL_PRBS_ERR_INS_0 (0x3243ecaeUL)
+#define MAC_PCS_GTY_SCAN_CTL_PRBS_ERR_INS_1 (0x4544dc38UL)
+#define MAC_PCS_GTY_SCAN_CTL_PRBS_ERR_INS_2 (0xdc4d8d82UL)
+#define MAC_PCS_GTY_SCAN_CTL_PRBS_ERR_INS_3 (0xab4abd14UL)
+#define MAC_PCS_GTY_SCAN_CTL_PRBS_RST_0 (0xf77381daUL)
+#define MAC_PCS_GTY_SCAN_CTL_PRBS_RST_1 (0x8074b14cUL)
+#define MAC_PCS_GTY_SCAN_CTL_PRBS_RST_2 (0x197de0f6UL)
+#define MAC_PCS_GTY_SCAN_CTL_PRBS_RST_3 (0x6e7ad060UL)
+#define MAC_PCS_GTY_SCAN_STAT (0x8070b7b9UL)
+#define MAC_PCS_GTY_SCAN_STAT_EYE_SCAN_ERR_0 (0xe5ddd3f9UL)
+#define MAC_PCS_GTY_SCAN_STAT_EYE_SCAN_ERR_1 (0x92dae36fUL)
+#define MAC_PCS_GTY_SCAN_STAT_EYE_SCAN_ERR_2 (0xbd3b2d5UL)
+#define MAC_PCS_GTY_SCAN_STAT_EYE_SCAN_ERR_3 (0x7cd48243UL)
+#define MAC_PCS_GTY_SCAN_STAT_PRBS_ERR_0 (0xb0217badUL)
+#define MAC_PCS_GTY_SCAN_STAT_PRBS_ERR_1 (0xc7264b3bUL)
+#define MAC_PCS_GTY_SCAN_STAT_PRBS_ERR_2 (0x5e2f1a81UL)
+#define MAC_PCS_GTY_SCAN_STAT_PRBS_ERR_3 (0x29282a17UL)
+#define MAC_PCS_GTY_STAT (0x853a9f14UL)
+#define MAC_PCS_GTY_STAT_RX_RST_DONE_0 (0x71cda8d6UL)
+#define MAC_PCS_GTY_STAT_RX_RST_DONE_1 (0x6ca9840UL)
+#define MAC_PCS_GTY_STAT_RX_RST_DONE_2 (0x9fc3c9faUL)
+#define MAC_PCS_GTY_STAT_RX_RST_DONE_3 (0xe8c4f96cUL)
+#define MAC_PCS_GTY_STAT_TX_BUF_STAT_0 (0xf766f49eUL)
+#define MAC_PCS_GTY_STAT_TX_BUF_STAT_1 (0x8061c408UL)
+#define MAC_PCS_GTY_STAT_TX_BUF_STAT_2 (0x196895b2UL)
+#define MAC_PCS_GTY_STAT_TX_BUF_STAT_3 (0x6e6fa524UL)
+#define MAC_PCS_GTY_STAT_TX_RST_DONE_0 (0xd128770bUL)
+#define MAC_PCS_GTY_STAT_TX_RST_DONE_1 (0xa62f479dUL)
+#define MAC_PCS_GTY_STAT_TX_RST_DONE_2 (0x3f261627UL)
+#define MAC_PCS_GTY_STAT_TX_RST_DONE_3 (0x482126b1UL)
+#define MAC_PCS_LANE_ALIGNER_FILL (0x7f7c92b4UL)
+#define MAC_PCS_LANE_ALIGNER_FILL_FILL (0x5d03a992UL)
+#define MAC_PCS_LINK_SUMMARY (0x7506c2cfUL)
+#define MAC_PCS_LINK_SUMMARY_ABS (0xeaec5364UL)
+#define MAC_PCS_LINK_SUMMARY_LH_ABS (0x75386439UL)
+#define MAC_PCS_LINK_SUMMARY_LH_LOCAL_FAULT (0xfe0a1d22UL)
+#define MAC_PCS_LINK_SUMMARY_LH_REMOTE_FAULT (0xe891aedUL)
+#define MAC_PCS_LINK_SUMMARY_LINK_DOWN_CNT (0x91098b1fUL)
+#define MAC_PCS_LINK_SUMMARY_LL_PHY_LINK_STATE (0x66c65523UL)
+#define MAC_PCS_LINK_SUMMARY_LOCAL_FAULT (0x87148e11UL)
+#define MAC_PCS_LINK_SUMMARY_NIM_INTERR (0x3d95c18UL)
+#define MAC_PCS_LINK_SUMMARY_NT_PHY_LINK_STATE (0x27ce6435UL)
+#define MAC_PCS_LINK_SUMMARY_REMOTE_FAULT (0xb1206568UL)
+#define MAC_PCS_LINK_SUMMARY_RESERVED (0x254bc0e3UL)
+#define MAC_PCS_MAC_PCS_CONFIG (0x1534e5c0UL)
+#define MAC_PCS_MAC_PCS_CONFIG_RX_CORE_RST (0xe964d0f5UL)
+#define MAC_PCS_MAC_PCS_CONFIG_RX_ENABLE (0x3301c934UL)
+#define MAC_PCS_MAC_PCS_CONFIG_RX_FORCE_RESYNC (0xf01103aUL)
+#define MAC_PCS_MAC_PCS_CONFIG_RX_PATH_RST (0x65a6baccUL)
+#define MAC_PCS_MAC_PCS_CONFIG_RX_TEST_PATTERN (0xf932af1bUL)
+#define MAC_PCS_MAC_PCS_CONFIG_TX_CORE_RST (0x1d11ab6UL)
+#define MAC_PCS_MAC_PCS_CONFIG_TX_ENABLE (0x401bb0beUL)
+#define MAC_PCS_MAC_PCS_CONFIG_TX_FCS_REMOVE (0x25816398UL)
+#define MAC_PCS_MAC_PCS_CONFIG_TX_PATH_RST (0x8d13708fUL)
+#define MAC_PCS_MAC_PCS_CONFIG_TX_SEND_IDLE (0xbcff1ba5UL)
+#define MAC_PCS_MAC_PCS_CONFIG_TX_SEND_RFI (0xc4dd154eUL)
+#define MAC_PCS_MAC_PCS_CONFIG_TX_TEST_PATTERN (0xdbc87be9UL)
+#define MAC_PCS_MAX_PKT_LEN (0x396b0d64UL)
+#define MAC_PCS_MAX_PKT_LEN_MAX_LEN (0x6d95b01fUL)
+#define MAC_PCS_MF_ERR (0xb0be669dUL)
+#define MAC_PCS_MF_ERR_MF_ERR (0x6c7b7561UL)
+#define MAC_PCS_MF_LEN_ERR (0x559f33efUL)
+#define MAC_PCS_MF_LEN_ERR_MF_LEN_ERR (0x196e21f6UL)
+#define MAC_PCS_MF_REPEAT_ERR (0xc7dedbb3UL)
+#define MAC_PCS_MF_REPEAT_ERR_MF_REPEAT_ERR (0xb5be34c7UL)
+#define MAC_PCS_PHYMAC_MISC (0x4d213de4UL)
+#define MAC_PCS_PHYMAC_MISC_TS_EOP (0xc9232087UL)
+#define MAC_PCS_PHYMAC_MISC_TX_MUX_STATE (0x761f1c74UL)
+#define MAC_PCS_PHYMAC_MISC_TX_SEL_HOST (0xb50087a5UL)
+#define MAC_PCS_PHYMAC_MISC_TX_SEL_RX_LOOP (0xbe5ce3b1UL)
+#define MAC_PCS_PHYMAC_MISC_TX_SEL_TFG (0x106d1efUL)
+#define MAC_PCS_PHY_STAT (0x533a519cUL)
+#define MAC_PCS_PHY_STAT_ALARM (0x57360efaUL)
+#define MAC_PCS_PHY_STAT_MOD_PRS (0x5d9d2135UL)
+#define MAC_PCS_PHY_STAT_RX_LOS (0xf9354fecUL)
+#define MAC_PCS_STAT_PCS_RX (0xb11d1a0cUL)
+#define MAC_PCS_STAT_PCS_RX_ALIGNED (0xc04d3946UL)
+#define MAC_PCS_STAT_PCS_RX_ALIGNED_ERR (0x82e5aacbUL)
+#define MAC_PCS_STAT_PCS_RX_GOT_SIGNAL_OS (0xe2ebace5UL)
+#define MAC_PCS_STAT_PCS_RX_HI_BER (0x44ed301UL)
+#define MAC_PCS_STAT_PCS_RX_INTERNAL_LOCAL_FAULT (0xd302122UL)
+#define MAC_PCS_STAT_PCS_RX_LOCAL_FAULT (0x2fd7a554UL)
+#define MAC_PCS_STAT_PCS_RX_MISALIGNED (0x4f8958c8UL)
+#define MAC_PCS_STAT_PCS_RX_RECEIVED_LOCAL_FAULT (0xce46c6b2UL)
+#define MAC_PCS_STAT_PCS_RX_REMOTE_FAULT (0xb73e135cUL)
+#define MAC_PCS_STAT_PCS_RX_STATUS (0x6087afc3UL)
+#define MAC_PCS_STAT_PCS_RX_LATCH (0x12a96a4UL)
+#define MAC_PCS_STAT_PCS_RX_LATCH_ALIGNED (0xffeb7af8UL)
+#define MAC_PCS_STAT_PCS_RX_LATCH_ALIGNED_ERR (0x43af96a9UL)
+#define MAC_PCS_STAT_PCS_RX_LATCH_GOT_SIGNAL_OS (0x9a4f180dUL)
+#define MAC_PCS_STAT_PCS_RX_LATCH_HI_BER (0x170bb0a7UL)
+#define MAC_PCS_STAT_PCS_RX_LATCH_INTERNAL_LOCAL_FAULT (0x97082914UL)
+#define MAC_PCS_STAT_PCS_RX_LATCH_LOCAL_FAULT (0xee9d9936UL)
+#define MAC_PCS_STAT_PCS_RX_LATCH_MISALIGNED (0x64a891f6UL)
+#define MAC_PCS_STAT_PCS_RX_LATCH_RECEIVED_LOCAL_FAULT (0x547ece84UL)
+#define MAC_PCS_STAT_PCS_RX_LATCH_REMOTE_FAULT (0x14435914UL)
+#define MAC_PCS_STAT_PCS_RX_LATCH_STATUS (0x73c2cc65UL)
+#define MAC_PCS_STAT_PCS_TX (0xe747bd8aUL)
+#define MAC_PCS_STAT_PCS_TX_LOCAL_FAULT (0xd715eee2UL)
+#define MAC_PCS_STAT_PCS_TX_LOCAL_FAULT_CHANGED (0x125aedaaUL)
+#define MAC_PCS_STAT_PCS_TX_PTP_FIFO_READ_ERROR (0x892ad851UL)
+#define MAC_PCS_STAT_PCS_TX_PTP_FIFO_READ_ERROR_CHANGED (0xf39f6854UL)
+#define MAC_PCS_STAT_PCS_TX_PTP_FIFO_WRITE_ERROR (0x6075c4dfUL)
+#define MAC_PCS_STAT_PCS_TX_PTP_FIFO_WRITE_ERROR_CHANGED (0xcd4c168aUL)
+#define MAC_PCS_STAT_PCS_TX_TX_OVFOUT (0x4483a41fUL)
+#define MAC_PCS_STAT_PCS_TX_TX_OVFOUT_CHANGED (0xcbd66e98UL)
+#define MAC_PCS_STAT_PCS_TX_TX_UNFOUT (0xb65e59a1UL)
+#define MAC_PCS_STAT_PCS_TX_TX_UNFOUT_CHANGED (0x9157fdd8UL)
+#define MAC_PCS_SYNCED (0x76ad78aaUL)
+#define MAC_PCS_SYNCED_SYNC (0xbff0beadUL)
+#define MAC_PCS_SYNCED_ERR (0x136856e9UL)
+#define MAC_PCS_SYNCED_ERR_SYNC_ERROR (0x16c52dc7UL)
+#define MAC_PCS_TEST_ERR (0xbf52be89UL)
+#define MAC_PCS_TEST_ERR_CODE_ERR (0x33a662cUL)
+#define MAC_PCS_TIMESTAMP_COMP (0x3054d1fcUL)
+#define MAC_PCS_TIMESTAMP_COMP_RX_DLY (0xa6496d75UL)
+#define MAC_PCS_TIMESTAMP_COMP_TX_DLY (0x70108e68UL)
+#define MAC_PCS_VL_DEMUXED (0xe1a41659UL)
+#define MAC_PCS_VL_DEMUXED_LOCK (0xf1e85d36UL)
+#define MAC_PCS_VL_DEMUXED_CHG (0xa326d6a6UL)
+#define MAC_PCS_VL_DEMUXED_CHG_LOCK_CHG (0x9327587fUL)
+#define MAC_PCS_VL_NUMBER (0x149d9e3UL)
+#define MAC_PCS_VL_NUMBER_VL_NUMBER (0x3b87c706UL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_MAC_PCS_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_pcs_xxv.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_pcs_xxv.h
new file mode 100644
index 0000000000..92878fb01f
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_pcs_xxv.h
@@ -0,0 +1,1092 @@
+/*
+ * nthw_fpga_reg_defs_mac_pcs_xxv.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_MAC_PCS_XXV_
+#define _NTHW_FPGA_REG_DEFS_MAC_PCS_XXV_
+
+/* MAC_PCS_XXV */
+#define NTHW_MOD_MAC_PCS_XXV (0x3ea7bfeaUL)
+#define MAC_PCS_XXV_ANEG_1G_CONFIG_0 (0xe8535535UL)
+#define MAC_PCS_XXV_ANEG_1G_CONFIG_0_ASMDIR (0xc90a5f78UL)
+#define MAC_PCS_XXV_ANEG_1G_CONFIG_0_BYPASS (0x66bcb293UL)
+#define MAC_PCS_XXV_ANEG_1G_CONFIG_0_ENABLE (0x7a14fcd5UL)
+#define MAC_PCS_XXV_ANEG_1G_CONFIG_0_PAUSE (0xb0859554UL)
+#define MAC_PCS_XXV_ANEG_1G_CONFIG_0_RESTART (0xe270c120UL)
+#define MAC_PCS_XXV_ANEG_1G_CONFIG_1 (0x9f5465a3UL)
+#define MAC_PCS_XXV_ANEG_1G_CONFIG_1_ASMDIR (0x5a05fe6UL)
+#define MAC_PCS_XXV_ANEG_1G_CONFIG_1_BYPASS (0xaa16b20dUL)
+#define MAC_PCS_XXV_ANEG_1G_CONFIG_1_ENABLE (0xb6befc4bUL)
+#define MAC_PCS_XXV_ANEG_1G_CONFIG_1_PAUSE (0x16f29ee0UL)
+#define MAC_PCS_XXV_ANEG_1G_CONFIG_1_RESTART (0xf50bd563UL)
+#define MAC_PCS_XXV_ANEG_1G_STA_0 (0x577adc44UL)
+#define MAC_PCS_XXV_ANEG_1G_STA_0_COMPLETE (0xc61358ebUL)
+#define MAC_PCS_XXV_ANEG_1G_STA_0_LP_ANEG_ABLE (0x61fcc32aUL)
+#define MAC_PCS_XXV_ANEG_1G_STA_0_LP_ASM (0x9aa1191UL)
+#define MAC_PCS_XXV_ANEG_1G_STA_0_LP_PAUSE (0x61b6e89aUL)
+#define MAC_PCS_XXV_ANEG_1G_STA_0_LP_RF (0x1f056f1eUL)
+#define MAC_PCS_XXV_ANEG_1G_STA_1 (0x207decd2UL)
+#define MAC_PCS_XXV_ANEG_1G_STA_1_COMPLETE (0x29d133d5UL)
+#define MAC_PCS_XXV_ANEG_1G_STA_1_LP_ANEG_ABLE (0xfcf3225cUL)
+#define MAC_PCS_XXV_ANEG_1G_STA_1_LP_ASM (0xc500110fUL)
+#define MAC_PCS_XXV_ANEG_1G_STA_1_LP_PAUSE (0x8e7483a4UL)
+#define MAC_PCS_XXV_ANEG_1G_STA_1_LP_RF (0xb97264aaUL)
+#define MAC_PCS_XXV_ANEG_ABILITY_0 (0xd2af0b3bUL)
+#define MAC_PCS_XXV_ANEG_ABILITY_0_25GBASE_CR (0xe523e7bcUL)
+#define MAC_PCS_XXV_ANEG_ABILITY_0_25GBASE_CR1 (0x41ee33f7UL)
+#define MAC_PCS_XXV_ANEG_ABILITY_0_25GBASE_CR_S (0xf8862066UL)
+#define MAC_PCS_XXV_ANEG_ABILITY_0_BASE25G_CR (0xb2bec4abUL)
+#define MAC_PCS_XXV_ANEG_ABILITY_0_BASE25G_CR1 (0xc26a2b13UL)
+#define MAC_PCS_XXV_ANEG_ABILITY_0_BASE25G_CR_S (0x5f62821fUL)
+#define MAC_PCS_XXV_ANEG_ABILITY_1 (0xa5a83badUL)
+#define MAC_PCS_XXV_ANEG_ABILITY_1_BASE25G_CR (0x291b88c4UL)
+#define MAC_PCS_XXV_ANEG_ABILITY_1_BASE25G_CR1 (0x1ffcf296UL)
+#define MAC_PCS_XXV_ANEG_ABILITY_1_BASE25G_CR_S (0xc26d6369UL)
+#define MAC_PCS_XXV_ANEG_ABILITY_1_25GBASE_CR (0x412a26e0UL)
+#define MAC_PCS_XXV_ANEG_ABILITY_1_25GBASE_CR1 (0x239727e9UL)
+#define MAC_PCS_XXV_ANEG_ABILITY_1_25GBASE_CR_S (0x2eb6411UL)
+#define MAC_PCS_XXV_ANEG_ABILITY_2 (0x3ca16a17UL)
+#define MAC_PCS_XXV_ANEG_ABILITY_2_BASE25G_CR (0x5e855a34UL)
+#define MAC_PCS_XXV_ANEG_ABILITY_2_BASE25G_CR1 (0xa2369e58UL)
+#define MAC_PCS_XXV_ANEG_ABILITY_2_BASE25G_CR_S (0xbe0c46b2UL)
+#define MAC_PCS_XXV_ANEG_ABILITY_2_25GBASE_CR (0x36b4f410UL)
+#define MAC_PCS_XXV_ANEG_ABILITY_2_25GBASE_CR1 (0x9e5d4b27UL)
+#define MAC_PCS_XXV_ANEG_ABILITY_2_25GBASE_CR_S (0x7e8a41caUL)
+#define MAC_PCS_XXV_ANEG_ABILITY_3 (0x4ba65a81UL)
+#define MAC_PCS_XXV_ANEG_ABILITY_3_BASE25G_CR (0xc520165bUL)
+#define MAC_PCS_XXV_ANEG_ABILITY_3_BASE25G_CR1 (0x7fa047ddUL)
+#define MAC_PCS_XXV_ANEG_ABILITY_3_BASE25G_CR_S (0x2303a7c4UL)
+#define MAC_PCS_XXV_ANEG_ABILITY_3_25GBASE_CR (0xad11b87fUL)
+#define MAC_PCS_XXV_ANEG_ABILITY_3_25GBASE_CR1 (0x43cb92a2UL)
+#define MAC_PCS_XXV_ANEG_ABILITY_3_25GBASE_CR_S (0xe385a0bcUL)
+#define MAC_PCS_XXV_ANEG_CONFIG_0 (0x4c943ef2UL)
+#define MAC_PCS_XXV_ANEG_CONFIG_0_ASMDIR (0x3bbfbb7dUL)
+#define MAC_PCS_XXV_ANEG_CONFIG_0_BYPASS (0x94095696UL)
+#define MAC_PCS_XXV_ANEG_CONFIG_0_ENABLE (0x88a118d0UL)
+#define MAC_PCS_XXV_ANEG_CONFIG_0_FEC74_REQUEST (0x76aa937UL)
+#define MAC_PCS_XXV_ANEG_CONFIG_0_FEC74_REQUEST_10G (0x1a5e1df6UL)
+#define MAC_PCS_XXV_ANEG_CONFIG_0_FEC91_ABILITY (0x5d6cbd68UL)
+#define MAC_PCS_XXV_ANEG_CONFIG_0_FEC91_REQUEST (0x5334dccbUL)
+#define MAC_PCS_XXV_ANEG_CONFIG_0_HIDE_FEC74 (0xf0c50196UL)
+#define MAC_PCS_XXV_ANEG_CONFIG_0_NONCE_SEED (0x8f9feb1eUL)
+#define MAC_PCS_XXV_ANEG_CONFIG_0_PAUSE (0x6761de07UL)
+#define MAC_PCS_XXV_ANEG_CONFIG_0_PSEUDO (0xfdcd997fUL)
+#define MAC_PCS_XXV_ANEG_CONFIG_0_REMOTE_FAULT (0xa56faacbUL)
+#define MAC_PCS_XXV_ANEG_CONFIG_0_RESTART (0x92e8804bUL)
+#define MAC_PCS_XXV_ANEG_CONFIG_0_RS_FEC_REQUEST (0x5bcb427dUL)
+#define MAC_PCS_XXV_ANEG_CONFIG_0_SW_FEC_OVERWRITE (0x28a23fa1UL)
+#define MAC_PCS_XXV_ANEG_CONFIG_0_SW_SPEED_OVERWRITE (0x864c3454UL)
+#define MAC_PCS_XXV_ANEG_CONFIG_1 (0x3b930e64UL)
+#define MAC_PCS_XXV_ANEG_CONFIG_1_ASMDIR (0xf715bbe3UL)
+#define MAC_PCS_XXV_ANEG_CONFIG_1_BYPASS (0x58a35608UL)
+#define MAC_PCS_XXV_ANEG_CONFIG_1_ENABLE (0x440b184eUL)
+#define MAC_PCS_XXV_ANEG_CONFIG_1_FEC74_REQUEST (0xbe9172dfUL)
+#define MAC_PCS_XXV_ANEG_CONFIG_1_FEC74_REQUEST_10G (0xcdbc9daeUL)
+#define MAC_PCS_XXV_ANEG_CONFIG_1_FEC91_ABILITY (0xe4976680UL)
+#define MAC_PCS_XXV_ANEG_CONFIG_1_FEC91_REQUEST (0xeacf0723UL)
+#define MAC_PCS_XXV_ANEG_CONFIG_1_HIDE_FEC74 (0x6b604df9UL)
+#define MAC_PCS_XXV_ANEG_CONFIG_1_NONCE_SEED (0x143aa771UL)
+#define MAC_PCS_XXV_ANEG_CONFIG_1_PAUSE (0xc116d5b3UL)
+#define MAC_PCS_XXV_ANEG_CONFIG_1_PSEUDO (0x316799e1UL)
+#define MAC_PCS_XXV_ANEG_CONFIG_1_REMOTE_FAULT (0x38604bbdUL)
+#define MAC_PCS_XXV_ANEG_CONFIG_1_RESTART (0x85939408UL)
+#define MAC_PCS_XXV_ANEG_CONFIG_1_RS_FEC_REQUEST (0xf5a3d3ecUL)
+#define MAC_PCS_XXV_ANEG_CONFIG_1_SW_FEC_OVERWRITE (0xc7f08940UL)
+#define MAC_PCS_XXV_ANEG_CONFIG_1_SW_SPEED_OVERWRITE (0xe32b0f12UL)
+#define MAC_PCS_XXV_ANEG_CONFIG_2 (0xa29a5fdeUL)
+#define MAC_PCS_XXV_ANEG_CONFIG_2_ASMDIR (0x799abc00UL)
+#define MAC_PCS_XXV_ANEG_CONFIG_2_BYPASS (0xd62c51ebUL)
+#define MAC_PCS_XXV_ANEG_CONFIG_2_ENABLE (0xca841fadUL)
+#define MAC_PCS_XXV_ANEG_CONFIG_2_FEC74_REQUEST (0xafec18a6UL)
+#define MAC_PCS_XXV_ANEG_CONFIG_2_FEC74_REQUEST_10G (0x6eea1b07UL)
+#define MAC_PCS_XXV_ANEG_CONFIG_2_FEC91_ABILITY (0xf5ea0cf9UL)
+#define MAC_PCS_XXV_ANEG_CONFIG_2_FEC91_REQUEST (0xfbb26d5aUL)
+#define MAC_PCS_XXV_ANEG_CONFIG_2_HIDE_FEC74 (0x1cfe9f09UL)
+#define MAC_PCS_XXV_ANEG_CONFIG_2_NONCE_SEED (0x63a47581UL)
+#define MAC_PCS_XXV_ANEG_CONFIG_2_PAUSE (0xf0fecf2eUL)
+#define MAC_PCS_XXV_ANEG_CONFIG_2_PSEUDO (0xbfe89e02UL)
+#define MAC_PCS_XXV_ANEG_CONFIG_2_REMOTE_FAULT (0x44016e66UL)
+#define MAC_PCS_XXV_ANEG_CONFIG_2_RESTART (0xbc1ea8cdUL)
+#define MAC_PCS_XXV_ANEG_CONFIG_2_RS_FEC_REQUEST (0xdc6b671eUL)
+#define MAC_PCS_XXV_ANEG_CONFIG_2_SW_FEC_OVERWRITE (0x2d765422UL)
+#define MAC_PCS_XXV_ANEG_CONFIG_2_SW_SPEED_OVERWRITE (0x4c8242d8UL)
+#define MAC_PCS_XXV_ANEG_CONFIG_3 (0xd59d6f48UL)
+#define MAC_PCS_XXV_ANEG_CONFIG_3_ASMDIR (0xb530bc9eUL)
+#define MAC_PCS_XXV_ANEG_CONFIG_3_BYPASS (0x1a865175UL)
+#define MAC_PCS_XXV_ANEG_CONFIG_3_ENABLE (0x62e1f33UL)
+#define MAC_PCS_XXV_ANEG_CONFIG_3_FEC74_REQUEST (0x1617c34eUL)
+#define MAC_PCS_XXV_ANEG_CONFIG_3_FEC74_REQUEST_10G (0xb9089b5fUL)
+#define MAC_PCS_XXV_ANEG_CONFIG_3_FEC91_ABILITY (0x4c11d711UL)
+#define MAC_PCS_XXV_ANEG_CONFIG_3_FEC91_REQUEST (0x4249b6b2UL)
+#define MAC_PCS_XXV_ANEG_CONFIG_3_HIDE_FEC74 (0x875bd366UL)
+#define MAC_PCS_XXV_ANEG_CONFIG_3_NONCE_SEED (0xf80139eeUL)
+#define MAC_PCS_XXV_ANEG_CONFIG_3_PAUSE (0x5689c49aUL)
+#define MAC_PCS_XXV_ANEG_CONFIG_3_PSEUDO (0x73429e9cUL)
+#define MAC_PCS_XXV_ANEG_CONFIG_3_REMOTE_FAULT (0xd90e8f10UL)
+#define MAC_PCS_XXV_ANEG_CONFIG_3_RESTART (0xab65bc8eUL)
+#define MAC_PCS_XXV_ANEG_CONFIG_3_RS_FEC_REQUEST (0x7203f68fUL)
+#define MAC_PCS_XXV_ANEG_CONFIG_3_SW_FEC_OVERWRITE (0xc224e2c3UL)
+#define MAC_PCS_XXV_ANEG_CONFIG_3_SW_SPEED_OVERWRITE (0x29e5799eUL)
+#define MAC_PCS_XXV_ANEG_DEBUG_0 (0x44ac1d35UL)
+#define MAC_PCS_XXV_ANEG_DEBUG_0_ANEG_END (0x85d17994UL)
+#define MAC_PCS_XXV_ANEG_DEBUG_0_ANEG_STARTED (0xd51a0134UL)
+#define MAC_PCS_XXV_ANEG_DEBUG_0_CDR_HOLD (0xdfa847b5UL)
+#define MAC_PCS_XXV_ANEG_DEBUG_0_LT_END (0xa921af33UL)
+#define MAC_PCS_XXV_ANEG_DEBUG_0_LT_STARTED (0xaac6e454UL)
+#define MAC_PCS_XXV_ANEG_DEBUG_1 (0x33ab2da3UL)
+#define MAC_PCS_XXV_ANEG_DEBUG_1_ANEG_END (0x6a1312aaUL)
+#define MAC_PCS_XXV_ANEG_DEBUG_1_ANEG_STARTED (0x4815e042UL)
+#define MAC_PCS_XXV_ANEG_DEBUG_1_CDR_HOLD (0x306a2c8bUL)
+#define MAC_PCS_XXV_ANEG_DEBUG_1_LT_END (0x658bafadUL)
+#define MAC_PCS_XXV_ANEG_DEBUG_1_LT_STARTED (0x3163a83bUL)
+#define MAC_PCS_XXV_ANEG_DEBUG_2 (0xaaa27c19UL)
+#define MAC_PCS_XXV_ANEG_DEBUG_2_ANEG_END (0x8124a9a9UL)
+#define MAC_PCS_XXV_ANEG_DEBUG_2_ANEG_STARTED (0x3474c599UL)
+#define MAC_PCS_XXV_ANEG_DEBUG_2_CDR_HOLD (0xdb5d9788UL)
+#define MAC_PCS_XXV_ANEG_DEBUG_2_LT_END (0xeb04a84eUL)
+#define MAC_PCS_XXV_ANEG_DEBUG_2_LT_STARTED (0x46fd7acbUL)
+#define MAC_PCS_XXV_ANEG_DEBUG_3 (0xdda54c8fUL)
+#define MAC_PCS_XXV_ANEG_DEBUG_3_ANEG_END (0x6ee6c297UL)
+#define MAC_PCS_XXV_ANEG_DEBUG_3_ANEG_STARTED (0xa97b24efUL)
+#define MAC_PCS_XXV_ANEG_DEBUG_3_CDR_HOLD (0x349ffcb6UL)
+#define MAC_PCS_XXV_ANEG_DEBUG_3_LT_END (0x27aea8d0UL)
+#define MAC_PCS_XXV_ANEG_DEBUG_3_LT_STARTED (0xdd5836a4UL)
+#define MAC_PCS_XXV_ANEG_LINK_STA_0 (0x9cd3a7adUL)
+#define MAC_PCS_XXV_ANEG_LINK_STA_0_LINK_CR (0x833d2c0eUL)
+#define MAC_PCS_XXV_ANEG_LINK_STA_0_LINK_CR1 (0x64e7ff9cUL)
+#define MAC_PCS_XXV_ANEG_LINK_STA_0_LINK_CR_S (0x22c3917aUL)
+#define MAC_PCS_XXV_ANEG_LINK_STA_1 (0xebd4973bUL)
+#define MAC_PCS_XXV_ANEG_LINK_STA_1_LINK_CR (0x9446384dUL)
+#define MAC_PCS_XXV_ANEG_LINK_STA_1_LINK_CR1 (0x8b2594a2UL)
+#define MAC_PCS_XXV_ANEG_LINK_STA_1_LINK_CR_S (0xe34d4ebaUL)
+#define MAC_PCS_XXV_ANEG_LINK_STA_2 (0x72ddc681UL)
+#define MAC_PCS_XXV_ANEG_LINK_STA_2_LINK_CR (0xadcb0488UL)
+#define MAC_PCS_XXV_ANEG_LINK_STA_2_LINK_CR1 (0x60122fa1UL)
+#define MAC_PCS_XXV_ANEG_LINK_STA_2_LINK_CR_S (0x7aaf28bbUL)
+#define MAC_PCS_XXV_ANEG_LINK_STA_3 (0x5daf617UL)
+#define MAC_PCS_XXV_ANEG_LINK_STA_3_LINK_CR (0xbab010cbUL)
+#define MAC_PCS_XXV_ANEG_LINK_STA_3_LINK_CR1 (0x8fd0449fUL)
+#define MAC_PCS_XXV_ANEG_LINK_STA_3_LINK_CR_S (0xbb21f77bUL)
+#define MAC_PCS_XXV_ANEG_LP_ABILITIES_0 (0x679ed455UL)
+#define MAC_PCS_XXV_ANEG_LP_ABILITIES_0_LP_25GBASE_CR (0xc77ef9eaUL)
+#define MAC_PCS_XXV_ANEG_LP_ABILITIES_0_LP_25GBASE_CR_S (0xee68c58aUL)
+#define MAC_PCS_XXV_ANEG_LP_ABILITIES_1 (0x1099e4c3UL)
+#define MAC_PCS_XXV_ANEG_LP_ABILITIES_1_LP_25GBASE_CR (0x7e852202UL)
+#define MAC_PCS_XXV_ANEG_LP_ABILITIES_1_LP_25GBASE_CR_S (0x69ce0ec9UL)
+#define MAC_PCS_XXV_ANEG_LP_ABILITIES_2 (0x8990b579UL)
+#define MAC_PCS_XXV_ANEG_LP_ABILITIES_2_LP_25GBASE_CR (0x6ff8487bUL)
+#define MAC_PCS_XXV_ANEG_LP_ABILITIES_2_LP_25GBASE_CR_S (0x3a54554dUL)
+#define MAC_PCS_XXV_ANEG_LP_ABILITIES_3 (0xfe9785efUL)
+#define MAC_PCS_XXV_ANEG_LP_ABILITIES_3_LP_25GBASE_CR (0xd6039393UL)
+#define MAC_PCS_XXV_ANEG_LP_ABILITIES_3_LP_25GBASE_CR_S (0xbdf29e0eUL)
+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_0 (0x29fb18a1UL)
+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_0_C_FEC74_ABILITY (0x15810dbeUL)
+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_0_C_FEC74_REQUEST (0x1bd96c1dUL)
+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_0_C_FEC91_ABILITY (0x41df7842UL)
+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_0_C_FEC91_REQUEST (0x4f8719e1UL)
+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_0_LP_25GBASE_CR1 (0x23d251c1UL)
+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_0_LP_EX_ABILITY_VALID (0xc632a6a7UL)
+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_1 (0x5efc2837UL)
+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_1_C_FEC74_ABILITY (0x9227c6fdUL)
+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_1_C_FEC74_REQUEST (0x9c7fa75eUL)
+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_1_C_FEC91_ABILITY (0xc679b301UL)
+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_1_C_FEC91_REQUEST (0xc821d2a2UL)
+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_1_LP_25GBASE_CR1 (0x8dbac050UL)
+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_1_LP_EX_ABILITY_VALID (0x59e82539UL)
+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_2 (0xc7f5798dUL)
+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_2_C_FEC74_ABILITY (0xc1bd9d79UL)
+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_2_C_FEC74_REQUEST (0xcfe5fcdaUL)
+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_2_C_FEC91_ABILITY (0x95e3e885UL)
+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_2_C_FEC91_REQUEST (0x9bbb8926UL)
+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_2_LP_25GBASE_CR1 (0xa47274a2UL)
+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_2_LP_EX_ABILITY_VALID (0x22f6a7daUL)
+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_3 (0xb0f2491bUL)
+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_3_C_FEC74_ABILITY (0x461b563aUL)
+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_3_C_FEC74_REQUEST (0x48433799UL)
+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_3_C_FEC91_ABILITY (0x124523c6UL)
+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_3_C_FEC91_REQUEST (0x1c1d4265UL)
+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_3_LP_25GBASE_CR1 (0xa1ae533UL)
+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_3_LP_EX_ABILITY_VALID (0xbd2c2444UL)
+#define MAC_PCS_XXV_ANEG_LP_STA_0 (0xc256fa45UL)
+#define MAC_PCS_XXV_ANEG_LP_STA_0_LP_ABILITY_VALID (0x414cfb0cUL)
+#define MAC_PCS_XXV_ANEG_LP_STA_0_LP_ANEG_ABLE (0xe0623a0aUL)
+#define MAC_PCS_XXV_ANEG_LP_STA_0_LP_ASM (0xf0872f9dUL)
+#define MAC_PCS_XXV_ANEG_LP_STA_0_LP_FEC74_REQ (0x3881d9daUL)
+#define MAC_PCS_XXV_ANEG_LP_STA_0_LP_PAUSE (0xc624310UL)
+#define MAC_PCS_XXV_ANEG_LP_STA_0_LP_RF (0x8be40c82UL)
+#define MAC_PCS_XXV_ANEG_LP_STA_0_LP_RS_FEC_REQ (0x9807cff4UL)
+#define MAC_PCS_XXV_ANEG_LP_STA_1 (0xb551cad3UL)
+#define MAC_PCS_XXV_ANEG_LP_STA_1_LP_ABILITY_VALID (0xae1e4dedUL)
+#define MAC_PCS_XXV_ANEG_LP_STA_1_LP_ANEG_ABLE (0x7d6ddb7cUL)
+#define MAC_PCS_XXV_ANEG_LP_STA_1_LP_ASM (0x3c2d2f03UL)
+#define MAC_PCS_XXV_ANEG_LP_STA_1_LP_FEC74_REQ (0xa58e38acUL)
+#define MAC_PCS_XXV_ANEG_LP_STA_1_LP_PAUSE (0xe3a0282eUL)
+#define MAC_PCS_XXV_ANEG_LP_STA_1_LP_RF (0x2d930736UL)
+#define MAC_PCS_XXV_ANEG_LP_STA_1_LP_RS_FEC_REQ (0x21fc141cUL)
+#define MAC_PCS_XXV_ANEG_LP_STA_2 (0x2c589b69UL)
+#define MAC_PCS_XXV_ANEG_LP_STA_2_LP_ABILITY_VALID (0x4498908fUL)
+#define MAC_PCS_XXV_ANEG_LP_STA_2_LP_ANEG_ABLE (0x10cfea7UL)
+#define MAC_PCS_XXV_ANEG_LP_STA_2_LP_ASM (0xb2a228e0UL)
+#define MAC_PCS_XXV_ANEG_LP_STA_2_LP_FEC74_REQ (0xd9ef1d77UL)
+#define MAC_PCS_XXV_ANEG_LP_STA_2_LP_PAUSE (0x897932dUL)
+#define MAC_PCS_XXV_ANEG_LP_STA_2_LP_RF (0x1c7b1dabUL)
+#define MAC_PCS_XXV_ANEG_LP_STA_2_LP_RS_FEC_REQ (0x30817e65UL)
+#define MAC_PCS_XXV_ANEG_LP_STA_3 (0x5b5fabffUL)
+#define MAC_PCS_XXV_ANEG_LP_STA_3_LP_ABILITY_VALID (0xabca266eUL)
+#define MAC_PCS_XXV_ANEG_LP_STA_3_LP_ANEG_ABLE (0x9c031fd1UL)
+#define MAC_PCS_XXV_ANEG_LP_STA_3_LP_ASM (0x7e08287eUL)
+#define MAC_PCS_XXV_ANEG_LP_STA_3_LP_FEC74_REQ (0x44e0fc01UL)
+#define MAC_PCS_XXV_ANEG_LP_STA_3_LP_PAUSE (0xe755f813UL)
+#define MAC_PCS_XXV_ANEG_LP_STA_3_LP_RF (0xba0c161fUL)
+#define MAC_PCS_XXV_ANEG_LP_STA_3_LP_RS_FEC_REQ (0x897aa58dUL)
+#define MAC_PCS_XXV_ANEG_STA_0 (0x3ed7a2b9UL)
+#define MAC_PCS_XXV_ANEG_STA_0_COMPLETE (0x11f713b8UL)
+#define MAC_PCS_XXV_ANEG_STA_0_FEC74_EN (0x974edcf2UL)
+#define MAC_PCS_XXV_ANEG_STA_0_PAR_D_FAULT (0xabe31863UL)
+#define MAC_PCS_XXV_ANEG_STA_0_RS_FEC_EN (0x178283ccUL)
+#define MAC_PCS_XXV_ANEG_STA_0_RX_PAUSE_EN (0xf5adbafaUL)
+#define MAC_PCS_XXV_ANEG_STA_0_TX_PAUSE_EN (0x1d1870b9UL)
+#define MAC_PCS_XXV_ANEG_STA_1 (0x49d0922fUL)
+#define MAC_PCS_XXV_ANEG_STA_1_COMPLETE (0xfe357886UL)
+#define MAC_PCS_XXV_ANEG_STA_1_FEC74_EN (0x788cb7ccUL)
+#define MAC_PCS_XXV_ANEG_STA_1_PAR_D_FAULT (0x7675c1e6UL)
+#define MAC_PCS_XXV_ANEG_STA_1_RS_FEC_EN (0xd60c5c0cUL)
+#define MAC_PCS_XXV_ANEG_STA_1_RX_PAUSE_EN (0x283b637fUL)
+#define MAC_PCS_XXV_ANEG_STA_1_TX_PAUSE_EN (0xc08ea93cUL)
+#define MAC_PCS_XXV_ANEG_STA_2 (0xd0d9c395UL)
+#define MAC_PCS_XXV_ANEG_STA_2_COMPLETE (0x1502c385UL)
+#define MAC_PCS_XXV_ANEG_STA_2_FEC74_EN (0x93bb0ccfUL)
+#define MAC_PCS_XXV_ANEG_STA_2_PAR_D_FAULT (0xcbbfad28UL)
+#define MAC_PCS_XXV_ANEG_STA_2_RS_FEC_EN (0x4fee3a0dUL)
+#define MAC_PCS_XXV_ANEG_STA_2_RX_PAUSE_EN (0x95f10fb1UL)
+#define MAC_PCS_XXV_ANEG_STA_2_TX_PAUSE_EN (0x7d44c5f2UL)
+#define MAC_PCS_XXV_ANEG_STA_3 (0xa7def303UL)
+#define MAC_PCS_XXV_ANEG_STA_3_COMPLETE (0xfac0a8bbUL)
+#define MAC_PCS_XXV_ANEG_STA_3_FEC74_EN (0x7c7967f1UL)
+#define MAC_PCS_XXV_ANEG_STA_3_PAR_D_FAULT (0x162974adUL)
+#define MAC_PCS_XXV_ANEG_STA_3_RS_FEC_EN (0x8e60e5cdUL)
+#define MAC_PCS_XXV_ANEG_STA_3_RX_PAUSE_EN (0x4867d634UL)
+#define MAC_PCS_XXV_ANEG_STA_3_TX_PAUSE_EN (0xa0d21c77UL)
+#define MAC_PCS_XXV_CLK_REF_ACTIVITY (0xad9a1b80UL)
+#define MAC_PCS_XXV_CLK_REF_ACTIVITY_COUNT (0x3216c992UL)
+#define MAC_PCS_XXV_CORE_CONF_0 (0xc665a258UL)
+#define MAC_PCS_XXV_CORE_CONF_0_ENHANCED_TS (0x10792af0UL)
+#define MAC_PCS_XXV_CORE_CONF_0_INLINE_MODE (0xb75bd54aUL)
+#define MAC_PCS_XXV_CORE_CONF_0_LINE_LOOPBACK (0xe27b24f2UL)
+#define MAC_PCS_XXV_CORE_CONF_0_RX_ENABLE (0x58298567UL)
+#define MAC_PCS_XXV_CORE_CONF_0_RX_FORCE_RESYNC (0x391c7c3bUL)
+#define MAC_PCS_XXV_CORE_CONF_0_TS_AT_EOP (0x34e1ac8fUL)
+#define MAC_PCS_XXV_CORE_CONF_0_TX_ENABLE (0x2b33fcedUL)
+#define MAC_PCS_XXV_CORE_CONF_0_TX_IGN_FCS (0x65b14385UL)
+#define MAC_PCS_XXV_CORE_CONF_0_TX_INS_FCS (0xdace417eUL)
+#define MAC_PCS_XXV_CORE_CONF_0_TX_SEND_IDLE (0xbb7c23d4UL)
+#define MAC_PCS_XXV_CORE_CONF_0_TX_SEND_LFI (0x3c99f330UL)
+#define MAC_PCS_XXV_CORE_CONF_0_TX_SEND_RFI (0x2a217d4aUL)
+#define MAC_PCS_XXV_CORE_CONF_1 (0xb16292ceUL)
+#define MAC_PCS_XXV_CORE_CONF_1_ENHANCED_TS (0xcdeff375UL)
+#define MAC_PCS_XXV_CORE_CONF_1_INLINE_MODE (0x6acd0ccfUL)
+#define MAC_PCS_XXV_CORE_CONF_1_LINE_LOOPBACK (0x5b80ff1aUL)
+#define MAC_PCS_XXV_CORE_CONF_1_RX_ENABLE (0x99a75aa7UL)
+#define MAC_PCS_XXV_CORE_CONF_1_RX_FORCE_RESYNC (0xbebab778UL)
+#define MAC_PCS_XXV_CORE_CONF_1_TS_AT_EOP (0xf56f734fUL)
+#define MAC_PCS_XXV_CORE_CONF_1_TX_ENABLE (0xeabd232dUL)
+#define MAC_PCS_XXV_CORE_CONF_1_TX_IGN_FCS (0xfe140feaUL)
+#define MAC_PCS_XXV_CORE_CONF_1_TX_INS_FCS (0x416b0d11UL)
+#define MAC_PCS_XXV_CORE_CONF_1_TX_SEND_IDLE (0x2673c2a2UL)
+#define MAC_PCS_XXV_CORE_CONF_1_TX_SEND_LFI (0xe10f2ab5UL)
+#define MAC_PCS_XXV_CORE_CONF_1_TX_SEND_RFI (0xf7b7a4cfUL)
+#define MAC_PCS_XXV_CORE_CONF_2 (0x286bc374UL)
+#define MAC_PCS_XXV_CORE_CONF_2_ENHANCED_TS (0x70259fbbUL)
+#define MAC_PCS_XXV_CORE_CONF_2_INLINE_MODE (0xd7076001UL)
+#define MAC_PCS_XXV_CORE_CONF_2_LINE_LOOPBACK (0x4afd9563UL)
+#define MAC_PCS_XXV_CORE_CONF_2_RX_ENABLE (0x453ca6UL)
+#define MAC_PCS_XXV_CORE_CONF_2_RX_FORCE_RESYNC (0xed20ecfcUL)
+#define MAC_PCS_XXV_CORE_CONF_2_TS_AT_EOP (0x6c8d154eUL)
+#define MAC_PCS_XXV_CORE_CONF_2_TX_ENABLE (0x735f452cUL)
+#define MAC_PCS_XXV_CORE_CONF_2_TX_IGN_FCS (0x898add1aUL)
+#define MAC_PCS_XXV_CORE_CONF_2_TX_INS_FCS (0x36f5dfe1UL)
+#define MAC_PCS_XXV_CORE_CONF_2_TX_SEND_IDLE (0x5a12e779UL)
+#define MAC_PCS_XXV_CORE_CONF_2_TX_SEND_LFI (0x5cc5467bUL)
+#define MAC_PCS_XXV_CORE_CONF_2_TX_SEND_RFI (0x4a7dc801UL)
+#define MAC_PCS_XXV_CORE_CONF_3 (0x5f6cf3e2UL)
+#define MAC_PCS_XXV_CORE_CONF_3_ENHANCED_TS (0xadb3463eUL)
+#define MAC_PCS_XXV_CORE_CONF_3_INLINE_MODE (0xa91b984UL)
+#define MAC_PCS_XXV_CORE_CONF_3_LINE_LOOPBACK (0xf3064e8bUL)
+#define MAC_PCS_XXV_CORE_CONF_3_RX_ENABLE (0xc1cbe366UL)
+#define MAC_PCS_XXV_CORE_CONF_3_RX_FORCE_RESYNC (0x6a8627bfUL)
+#define MAC_PCS_XXV_CORE_CONF_3_TS_AT_EOP (0xad03ca8eUL)
+#define MAC_PCS_XXV_CORE_CONF_3_TX_ENABLE (0xb2d19aecUL)
+#define MAC_PCS_XXV_CORE_CONF_3_TX_IGN_FCS (0x122f9175UL)
+#define MAC_PCS_XXV_CORE_CONF_3_TX_INS_FCS (0xad50938eUL)
+#define MAC_PCS_XXV_CORE_CONF_3_TX_SEND_IDLE (0xc71d060fUL)
+#define MAC_PCS_XXV_CORE_CONF_3_TX_SEND_LFI (0x81539ffeUL)
+#define MAC_PCS_XXV_CORE_CONF_3_TX_SEND_RFI (0x97eb1184UL)
+#define MAC_PCS_XXV_DEBOUNCE_CTRL_0 (0xcd1b26beUL)
+#define MAC_PCS_XXV_DEBOUNCE_CTRL_0_NT_DEBOUNCE_LATENCY (0x32bcbfc6UL)
+#define MAC_PCS_XXV_DEBOUNCE_CTRL_0_NT_FORCE_LINK_DOWN (0xf5caa84cUL)
+#define MAC_PCS_XXV_DEBOUNCE_CTRL_0_NT_LINKUP_LATENCY (0x39c69ab7UL)
+#define MAC_PCS_XXV_DEBOUNCE_CTRL_0_NT_PORT_CTRL (0xbba352c4UL)
+#define MAC_PCS_XXV_DEBOUNCE_CTRL_1 (0xba1c1628UL)
+#define MAC_PCS_XXV_DEBOUNCE_CTRL_1_NT_DEBOUNCE_LATENCY (0xad663c58UL)
+#define MAC_PCS_XXV_DEBOUNCE_CTRL_1_NT_FORCE_LINK_DOWN (0x90ad930aUL)
+#define MAC_PCS_XXV_DEBOUNCE_CTRL_1_NT_LINKUP_LATENCY (0xee241aefUL)
+#define MAC_PCS_XXV_DEBOUNCE_CTRL_1_NT_PORT_CTRL (0x26acb3b2UL)
+#define MAC_PCS_XXV_DEBOUNCE_CTRL_2 (0x23154792UL)
+#define MAC_PCS_XXV_DEBOUNCE_CTRL_2_NT_DEBOUNCE_LATENCY (0xd678bebbUL)
+#define MAC_PCS_XXV_DEBOUNCE_CTRL_2_NT_FORCE_LINK_DOWN (0x3f04dec0UL)
+#define MAC_PCS_XXV_DEBOUNCE_CTRL_2_NT_LINKUP_LATENCY (0x4d729c46UL)
+#define MAC_PCS_XXV_DEBOUNCE_CTRL_2_NT_PORT_CTRL (0x5acd9669UL)
+#define MAC_PCS_XXV_DEBOUNCE_CTRL_3 (0x54127704UL)
+#define MAC_PCS_XXV_DEBOUNCE_CTRL_3_NT_DEBOUNCE_LATENCY (0x49a23d25UL)
+#define MAC_PCS_XXV_DEBOUNCE_CTRL_3_NT_FORCE_LINK_DOWN (0x5a63e586UL)
+#define MAC_PCS_XXV_DEBOUNCE_CTRL_3_NT_LINKUP_LATENCY (0x9a901c1eUL)
+#define MAC_PCS_XXV_DEBOUNCE_CTRL_3_NT_PORT_CTRL (0xc7c2771fUL)
+#define MAC_PCS_XXV_FEC74_CCW_CNT_0 (0x98d5cef3UL)
+#define MAC_PCS_XXV_FEC74_CCW_CNT_0_FEC74_CCW_CNT (0x98570079UL)
+#define MAC_PCS_XXV_FEC74_CCW_CNT_1 (0xefd2fe65UL)
+#define MAC_PCS_XXV_FEC74_CCW_CNT_1_FEC74_CCW_CNT (0x21acdb91UL)
+#define MAC_PCS_XXV_FEC74_CCW_CNT_2 (0x76dbafdfUL)
+#define MAC_PCS_XXV_FEC74_CCW_CNT_2_FEC74_CCW_CNT (0x30d1b1e8UL)
+#define MAC_PCS_XXV_FEC74_CCW_CNT_3 (0x1dc9f49UL)
+#define MAC_PCS_XXV_FEC74_CCW_CNT_3_FEC74_CCW_CNT (0x892a6a00UL)
+#define MAC_PCS_XXV_FEC74_CONFIG_0 (0xd8988d69UL)
+#define MAC_PCS_XXV_FEC74_CONFIG_0_FEC74_ERRORS_TO_PCS (0xbad20553UL)
+#define MAC_PCS_XXV_FEC74_CONFIG_0_RX_FEC74_ENABLE (0x95657559UL)
+#define MAC_PCS_XXV_FEC74_CONFIG_0_TX_FEC74_ENABLE (0xb79fa1abUL)
+#define MAC_PCS_XXV_FEC74_CONFIG_1 (0xaf9fbdffUL)
+#define MAC_PCS_XXV_FEC74_CONFIG_1_FEC74_ERRORS_TO_PCS (0x250886cdUL)
+#define MAC_PCS_XXV_FEC74_CONFIG_1_RX_FEC74_ENABLE (0x12c3be1aUL)
+#define MAC_PCS_XXV_FEC74_CONFIG_1_TX_FEC74_ENABLE (0x30396ae8UL)
+#define MAC_PCS_XXV_FEC74_CONFIG_2 (0x3696ec45UL)
+#define MAC_PCS_XXV_FEC74_CONFIG_2_FEC74_ERRORS_TO_PCS (0x5e16042eUL)
+#define MAC_PCS_XXV_FEC74_CONFIG_2_RX_FEC74_ENABLE (0x4159e59eUL)
+#define MAC_PCS_XXV_FEC74_CONFIG_2_TX_FEC74_ENABLE (0x63a3316cUL)
+#define MAC_PCS_XXV_FEC74_CONFIG_3 (0x4191dcd3UL)
+#define MAC_PCS_XXV_FEC74_CONFIG_3_FEC74_ERRORS_TO_PCS (0xc1cc87b0UL)
+#define MAC_PCS_XXV_FEC74_CONFIG_3_RX_FEC74_ENABLE (0xc6ff2eddUL)
+#define MAC_PCS_XXV_FEC74_CONFIG_3_TX_FEC74_ENABLE (0xe405fa2fUL)
+#define MAC_PCS_XXV_FEC74_UCW_CNT_0 (0x470ff508UL)
+#define MAC_PCS_XXV_FEC74_UCW_CNT_0_FEC74_UCW_CNT (0x70e15dbbUL)
+#define MAC_PCS_XXV_FEC74_UCW_CNT_1 (0x3008c59eUL)
+#define MAC_PCS_XXV_FEC74_UCW_CNT_1_FEC74_UCW_CNT (0xc91a8653UL)
+#define MAC_PCS_XXV_FEC74_UCW_CNT_2 (0xa9019424UL)
+#define MAC_PCS_XXV_FEC74_UCW_CNT_2_FEC74_UCW_CNT (0xd867ec2aUL)
+#define MAC_PCS_XXV_FEC74_UCW_CNT_3 (0xde06a4b2UL)
+#define MAC_PCS_XXV_FEC74_UCW_CNT_3_FEC74_UCW_CNT (0x619c37c2UL)
+#define MAC_PCS_XXV_GTY_CTL_RX_0 (0xb45ac330UL)
+#define MAC_PCS_XXV_GTY_CTL_RX_0_CDR_HOLD (0x9494702eUL)
+#define MAC_PCS_XXV_GTY_CTL_RX_0_EQUA_RST (0xac159264UL)
+#define MAC_PCS_XXV_GTY_CTL_RX_0_LPM_EN (0x8f3f6136UL)
+#define MAC_PCS_XXV_GTY_CTL_RX_0_POLARITY (0x589f67ddUL)
+#define MAC_PCS_XXV_GTY_CTL_RX_0_RATE (0x54b5525dUL)
+#define MAC_PCS_XXV_GTY_CTL_RX_1 (0xc35df3a6UL)
+#define MAC_PCS_XXV_GTY_CTL_RX_1_CDR_HOLD (0x7b561b10UL)
+#define MAC_PCS_XXV_GTY_CTL_RX_1_EQUA_RST (0x43d7f95aUL)
+#define MAC_PCS_XXV_GTY_CTL_RX_1_LPM_EN (0x439561a8UL)
+#define MAC_PCS_XXV_GTY_CTL_RX_1_POLARITY (0xb75d0ce3UL)
+#define MAC_PCS_XXV_GTY_CTL_RX_1_RATE (0x9fe981f8UL)
+#define MAC_PCS_XXV_GTY_CTL_RX_2 (0x5a54a21cUL)
+#define MAC_PCS_XXV_GTY_CTL_RX_2_CDR_HOLD (0x9061a013UL)
+#define MAC_PCS_XXV_GTY_CTL_RX_2_EQUA_RST (0xa8e04259UL)
+#define MAC_PCS_XXV_GTY_CTL_RX_2_LPM_EN (0xcd1a664bUL)
+#define MAC_PCS_XXV_GTY_CTL_RX_2_POLARITY (0x5c6ab7e0UL)
+#define MAC_PCS_XXV_GTY_CTL_RX_2_RATE (0x197df356UL)
+#define MAC_PCS_XXV_GTY_CTL_RX_3 (0x2d53928aUL)
+#define MAC_PCS_XXV_GTY_CTL_RX_3_CDR_HOLD (0x7fa3cb2dUL)
+#define MAC_PCS_XXV_GTY_CTL_RX_3_EQUA_RST (0x47222967UL)
+#define MAC_PCS_XXV_GTY_CTL_RX_3_LPM_EN (0x1b066d5UL)
+#define MAC_PCS_XXV_GTY_CTL_RX_3_POLARITY (0xb3a8dcdeUL)
+#define MAC_PCS_XXV_GTY_CTL_RX_3_RATE (0xd22120f3UL)
+#define MAC_PCS_XXV_GTY_CTL_TX_0 (0x91319cecUL)
+#define MAC_PCS_XXV_GTY_CTL_TX_0_INHIBIT (0x2743e45UL)
+#define MAC_PCS_XXV_GTY_CTL_TX_0_POLARITY (0xf87ab800UL)
+#define MAC_PCS_XXV_GTY_CTL_TX_1 (0xe636ac7aUL)
+#define MAC_PCS_XXV_GTY_CTL_TX_1_INHIBIT (0x150f2a06UL)
+#define MAC_PCS_XXV_GTY_CTL_TX_1_POLARITY (0x17b8d33eUL)
+#define MAC_PCS_XXV_GTY_CTL_TX_2 (0x7f3ffdc0UL)
+#define MAC_PCS_XXV_GTY_CTL_TX_2_INHIBIT (0x2c8216c3UL)
+#define MAC_PCS_XXV_GTY_CTL_TX_2_POLARITY (0xfc8f683dUL)
+#define MAC_PCS_XXV_GTY_CTL_TX_3 (0x838cd56UL)
+#define MAC_PCS_XXV_GTY_CTL_TX_3_INHIBIT (0x3bf90280UL)
+#define MAC_PCS_XXV_GTY_CTL_TX_3_POLARITY (0x134d0303UL)
+#define MAC_PCS_XXV_GTY_DIFF_CTL_0 (0x7a99aa99UL)
+#define MAC_PCS_XXV_GTY_DIFF_CTL_0_TX_DIFF_CTL (0xcdf499beUL)
+#define MAC_PCS_XXV_GTY_DIFF_CTL_0_TX_DIFF_CTL_ADJUSTED (0x833ddf3dUL)
+#define MAC_PCS_XXV_GTY_DIFF_CTL_1 (0xd9e9a0fUL)
+#define MAC_PCS_XXV_GTY_DIFF_CTL_1_TX_DIFF_CTL (0x1062403bUL)
+#define MAC_PCS_XXV_GTY_DIFF_CTL_1_TX_DIFF_CTL_ADJUSTED (0x9415bbfdUL)
+#define MAC_PCS_XXV_GTY_DIFF_CTL_2 (0x9497cbb5UL)
+#define MAC_PCS_XXV_GTY_DIFF_CTL_2_TX_DIFF_CTL (0xada82cf5UL)
+#define MAC_PCS_XXV_GTY_DIFF_CTL_2_TX_DIFF_CTL_ADJUSTED (0xad6d16bdUL)
+#define MAC_PCS_XXV_GTY_DIFF_CTL_3 (0xe390fb23UL)
+#define MAC_PCS_XXV_GTY_DIFF_CTL_3_TX_DIFF_CTL (0x703ef570UL)
+#define MAC_PCS_XXV_GTY_DIFF_CTL_3_TX_DIFF_CTL_ADJUSTED (0xba45727dUL)
+#define MAC_PCS_XXV_GTY_LOOP_0 (0xcfacffb3UL)
+#define MAC_PCS_XXV_GTY_LOOP_0_GT_LOOP (0x5c74ecacUL)
+#define MAC_PCS_XXV_GTY_LOOP_1 (0xb8abcf25UL)
+#define MAC_PCS_XXV_GTY_LOOP_1_GT_LOOP (0x4b0ff8efUL)
+#define MAC_PCS_XXV_GTY_LOOP_2 (0x21a29e9fUL)
+#define MAC_PCS_XXV_GTY_LOOP_2_GT_LOOP (0x7282c42aUL)
+#define MAC_PCS_XXV_GTY_LOOP_3 (0x56a5ae09UL)
+#define MAC_PCS_XXV_GTY_LOOP_3_GT_LOOP (0x65f9d069UL)
+#define MAC_PCS_XXV_GTY_MAIN_CTL_0 (0xd79b7f80UL)
+#define MAC_PCS_XXV_GTY_MAIN_CTL_0_TX_MAIN_CTL (0xded513f4UL)
+#define MAC_PCS_XXV_GTY_MAIN_CTL_1 (0xa09c4f16UL)
+#define MAC_PCS_XXV_GTY_MAIN_CTL_1_TX_MAIN_CTL (0x343ca71UL)
+#define MAC_PCS_XXV_GTY_MAIN_CTL_2 (0x39951eacUL)
+#define MAC_PCS_XXV_GTY_MAIN_CTL_2_TX_MAIN_CTL (0xbe89a6bfUL)
+#define MAC_PCS_XXV_GTY_MAIN_CTL_3 (0x4e922e3aUL)
+#define MAC_PCS_XXV_GTY_MAIN_CTL_3_TX_MAIN_CTL (0x631f7f3aUL)
+#define MAC_PCS_XXV_GTY_POST_CURSOR_0 (0xaa04cb19UL)
+#define MAC_PCS_XXV_GTY_POST_CURSOR_0_TX_POST_CSR (0x7b6f0b43UL)
+#define MAC_PCS_XXV_GTY_POST_CURSOR_0_TX_POST_CSR_ADJUSTED (0xa87d9ad2UL)
+#define MAC_PCS_XXV_GTY_POST_CURSOR_1 (0xdd03fb8fUL)
+#define MAC_PCS_XXV_GTY_POST_CURSOR_1_TX_POST_CSR (0xa6f9d2c6UL)
+#define MAC_PCS_XXV_GTY_POST_CURSOR_1_TX_POST_CSR_ADJUSTED (0xbf55fe12UL)
+#define MAC_PCS_XXV_GTY_POST_CURSOR_2 (0x440aaa35UL)
+#define MAC_PCS_XXV_GTY_POST_CURSOR_2_TX_POST_CSR (0x1b33be08UL)
+#define MAC_PCS_XXV_GTY_POST_CURSOR_2_TX_POST_CSR_ADJUSTED (0x862d5352UL)
+#define MAC_PCS_XXV_GTY_POST_CURSOR_3 (0x330d9aa3UL)
+#define MAC_PCS_XXV_GTY_POST_CURSOR_3_TX_POST_CSR (0xc6a5678dUL)
+#define MAC_PCS_XXV_GTY_POST_CURSOR_3_TX_POST_CSR_ADJUSTED (0x91053792UL)
+#define MAC_PCS_XXV_GTY_PRBS_0 (0xd3e408e4UL)
+#define MAC_PCS_XXV_GTY_PRBS_0_PRBS_ERR (0x4fd820bdUL)
+#define MAC_PCS_XXV_GTY_PRBS_0_PRBS_ERR_INS (0x292ed7d3UL)
+#define MAC_PCS_XXV_GTY_PRBS_0_PRBS_RST (0xa6c9013cUL)
+#define MAC_PCS_XXV_GTY_PRBS_0_RX_PRBS_SEL (0x9c43c790UL)
+#define MAC_PCS_XXV_GTY_PRBS_0_TX_PRBS_SEL (0x74f60dd3UL)
+#define MAC_PCS_XXV_GTY_PRBS_1 (0xa4e33872UL)
+#define MAC_PCS_XXV_GTY_PRBS_1_PRBS_ERR (0xa01a4b83UL)
+#define MAC_PCS_XXV_GTY_PRBS_1_PRBS_ERR_INS (0xb42136a5UL)
+#define MAC_PCS_XXV_GTY_PRBS_1_PRBS_RST (0x490b6a02UL)
+#define MAC_PCS_XXV_GTY_PRBS_1_RX_PRBS_SEL (0x41d51e15UL)
+#define MAC_PCS_XXV_GTY_PRBS_1_TX_PRBS_SEL (0xa960d456UL)
+#define MAC_PCS_XXV_GTY_PRBS_2 (0x3dea69c8UL)
+#define MAC_PCS_XXV_GTY_PRBS_2_PRBS_ERR (0x4b2df080UL)
+#define MAC_PCS_XXV_GTY_PRBS_2_PRBS_ERR_INS (0xc840137eUL)
+#define MAC_PCS_XXV_GTY_PRBS_2_PRBS_RST (0xa23cd101UL)
+#define MAC_PCS_XXV_GTY_PRBS_2_RX_PRBS_SEL (0xfc1f72dbUL)
+#define MAC_PCS_XXV_GTY_PRBS_2_TX_PRBS_SEL (0x14aab898UL)
+#define MAC_PCS_XXV_GTY_PRBS_3 (0x4aed595eUL)
+#define MAC_PCS_XXV_GTY_PRBS_3_PRBS_ERR (0xa4ef9bbeUL)
+#define MAC_PCS_XXV_GTY_PRBS_3_PRBS_ERR_INS (0x554ff208UL)
+#define MAC_PCS_XXV_GTY_PRBS_3_PRBS_RST (0x4dfeba3fUL)
+#define MAC_PCS_XXV_GTY_PRBS_3_RX_PRBS_SEL (0x2189ab5eUL)
+#define MAC_PCS_XXV_GTY_PRBS_3_TX_PRBS_SEL (0xc93c611dUL)
+#define MAC_PCS_XXV_GTY_PRBS_CNT_0 (0xe674af07UL)
+#define MAC_PCS_XXV_GTY_PRBS_CNT_0_COUNT (0x9e8b170cUL)
+#define MAC_PCS_XXV_GTY_PRBS_CNT_1 (0x91739f91UL)
+#define MAC_PCS_XXV_GTY_PRBS_CNT_1_COUNT (0x38fc1cb8UL)
+#define MAC_PCS_XXV_GTY_PRBS_CNT_2 (0x87ace2bUL)
+#define MAC_PCS_XXV_GTY_PRBS_CNT_2_COUNT (0x9140625UL)
+#define MAC_PCS_XXV_GTY_PRBS_CNT_3 (0x7f7dfebdUL)
+#define MAC_PCS_XXV_GTY_PRBS_CNT_3_COUNT (0xaf630d91UL)
+#define MAC_PCS_XXV_GTY_PRE_CURSOR_0 (0xa5879edeUL)
+#define MAC_PCS_XXV_GTY_PRE_CURSOR_0_TX_PRE_CSR (0x2f0d4bd2UL)
+#define MAC_PCS_XXV_GTY_PRE_CURSOR_0_TX_PRE_CSR_ADJUSTED (0xd738196fUL)
+#define MAC_PCS_XXV_GTY_PRE_CURSOR_1 (0xd280ae48UL)
+#define MAC_PCS_XXV_GTY_PRE_CURSOR_1_TX_PRE_CSR (0xb4a807bdUL)
+#define MAC_PCS_XXV_GTY_PRE_CURSOR_1_TX_PRE_CSR_ADJUSTED (0x48e29af1UL)
+#define MAC_PCS_XXV_GTY_PRE_CURSOR_2 (0x4b89fff2UL)
+#define MAC_PCS_XXV_GTY_PRE_CURSOR_2_TX_PRE_CSR (0xc336d54dUL)
+#define MAC_PCS_XXV_GTY_PRE_CURSOR_2_TX_PRE_CSR_ADJUSTED (0x33fc1812UL)
+#define MAC_PCS_XXV_GTY_PRE_CURSOR_3 (0x3c8ecf64UL)
+#define MAC_PCS_XXV_GTY_PRE_CURSOR_3_TX_PRE_CSR (0x58939922UL)
+#define MAC_PCS_XXV_GTY_PRE_CURSOR_3_TX_PRE_CSR_ADJUSTED (0xac269b8cUL)
+#define MAC_PCS_XXV_GTY_STATUS_0 (0x922d078cUL)
+#define MAC_PCS_XXV_GTY_STATUS_0_GT_POWERGOOD (0x46fffefcUL)
+#define MAC_PCS_XXV_GTY_STATUS_0_GT_RXBUFSTATUS (0x71961330UL)
+#define MAC_PCS_XXV_GTY_STATUS_0_GT_STARTOFSEQ (0x302abe66UL)
+#define MAC_PCS_XXV_GTY_STATUS_0_GT_TXBUFSTATUS (0x9923d973UL)
+#define MAC_PCS_XXV_GTY_STATUS_1 (0xe52a371aUL)
+#define MAC_PCS_XXV_GTY_STATUS_1_GT_POWERGOOD (0xdbf01f8aUL)
+#define MAC_PCS_XXV_GTY_STATUS_1_GT_RXBUFSTATUS (0xdffe82a1UL)
+#define MAC_PCS_XXV_GTY_STATUS_1_GT_STARTOFSEQ (0x89d1658eUL)
+#define MAC_PCS_XXV_GTY_STATUS_1_GT_TXBUFSTATUS (0x374b48e2UL)
+#define MAC_PCS_XXV_GTY_STATUS_2 (0x7c2366a0UL)
+#define MAC_PCS_XXV_GTY_STATUS_2_GT_POWERGOOD (0xa7913a51UL)
+#define MAC_PCS_XXV_GTY_STATUS_2_GT_RXBUFSTATUS (0xf6363653UL)
+#define MAC_PCS_XXV_GTY_STATUS_2_GT_STARTOFSEQ (0x98ac0ff7UL)
+#define MAC_PCS_XXV_GTY_STATUS_2_GT_TXBUFSTATUS (0x1e83fc10UL)
+#define MAC_PCS_XXV_GTY_STATUS_3 (0xb245636UL)
+#define MAC_PCS_XXV_GTY_STATUS_3_GT_POWERGOOD (0x3a9edb27UL)
+#define MAC_PCS_XXV_GTY_STATUS_3_GT_RXBUFSTATUS (0x585ea7c2UL)
+#define MAC_PCS_XXV_GTY_STATUS_3_GT_STARTOFSEQ (0x2157d41fUL)
+#define MAC_PCS_XXV_GTY_STATUS_3_GT_TXBUFSTATUS (0xb0eb6d81UL)
+#define MAC_PCS_XXV_LATENCY_0 (0x1ebce893UL)
+#define MAC_PCS_XXV_LATENCY_0_RX_LATENCY_MEAS (0x16e7962UL)
+#define MAC_PCS_XXV_LATENCY_1 (0x69bbd805UL)
+#define MAC_PCS_XXV_LATENCY_1_RX_LATENCY_MEAS (0x86c8b221UL)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_0 (0x64b5dd89UL)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_0_DEC_MAIN (0x3a6efcd0UL)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_0_DEC_POST (0xdfcc5d39UL)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_0_DEC_PRE (0xa8605393UL)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_0_INC_MAIN (0xa36cbdfbUL)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_0_INC_POST (0x46ce1c12UL)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_0_INC_PRE (0xa370c290UL)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_0_INIT (0xc3ba915bUL)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_0_PRESET (0xb0c65848UL)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_1 (0x13b2ed1fUL)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_1_DEC_MAIN (0xd5ac97eeUL)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_1_DEC_POST (0x300e3607UL)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_1_DEC_PRE (0xbf1b47d0UL)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_1_INC_MAIN (0x4caed6c5UL)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_1_INC_POST (0xa90c772cUL)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_1_INC_PRE (0xb40bd6d3UL)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_1_INIT (0x8e642feUL)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_1_PRESET (0x7c6c58d6UL)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_2 (0x8abbbca5UL)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_2_DEC_MAIN (0x3e9b2cedUL)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_2_DEC_POST (0xdb398d04UL)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_2_DEC_PRE (0x86967b15UL)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_2_INC_MAIN (0xa7996dc6UL)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_2_INC_POST (0x423bcc2fUL)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_2_INC_PRE (0x8d86ea16UL)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_2_INIT (0x8e723050UL)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_2_PRESET (0xf2e35f35UL)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_3 (0xfdbc8c33UL)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_3_DEC_MAIN (0xd15947d3UL)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_3_DEC_POST (0x34fbe63aUL)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_3_DEC_PRE (0x91ed6f56UL)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_3_INC_MAIN (0x485b06f8UL)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_3_INC_POST (0xadf9a711UL)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_3_INC_PRE (0x9afdfe55UL)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_3_INIT (0x452ee3f5UL)
+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_3_PRESET (0x3e495fabUL)
+#define MAC_PCS_XXV_LE_LT_STA_SEND_0 (0xf103387fUL)
+#define MAC_PCS_XXV_LE_LT_STA_SEND_0_MAIN_STA (0x87c6ab44UL)
+#define MAC_PCS_XXV_LE_LT_STA_SEND_0_POST_STA (0xb85a5a3dUL)
+#define MAC_PCS_XXV_LE_LT_STA_SEND_0_PRE_STA (0x44fa3d7eUL)
+#define MAC_PCS_XXV_LE_LT_STA_SEND_1 (0x860408e9UL)
+#define MAC_PCS_XXV_LE_LT_STA_SEND_1_MAIN_STA (0x6804c07aUL)
+#define MAC_PCS_XXV_LE_LT_STA_SEND_1_POST_STA (0x57983103UL)
+#define MAC_PCS_XXV_LE_LT_STA_SEND_1_PRE_STA (0x5381293dUL)
+#define MAC_PCS_XXV_LE_LT_STA_SEND_2 (0x1f0d5953UL)
+#define MAC_PCS_XXV_LE_LT_STA_SEND_2_MAIN_STA (0x83337b79UL)
+#define MAC_PCS_XXV_LE_LT_STA_SEND_2_POST_STA (0xbcaf8a00UL)
+#define MAC_PCS_XXV_LE_LT_STA_SEND_2_PRE_STA (0x6a0c15f8UL)
+#define MAC_PCS_XXV_LE_LT_STA_SEND_3 (0x680a69c5UL)
+#define MAC_PCS_XXV_LE_LT_STA_SEND_3_MAIN_STA (0x6cf11047UL)
+#define MAC_PCS_XXV_LE_LT_STA_SEND_3_POST_STA (0x536de13eUL)
+#define MAC_PCS_XXV_LE_LT_STA_SEND_3_PRE_STA (0x7d7701bbUL)
+#define MAC_PCS_XXV_LINK_SPEED_0 (0xfcf10505UL)
+#define MAC_PCS_XXV_LINK_SPEED_0_10G (0xfb473664UL)
+#define MAC_PCS_XXV_LINK_SPEED_0_SPEED (0xa81deb0bUL)
+#define MAC_PCS_XXV_LINK_SPEED_0_TOGGLE (0xdd2f38f7UL)
+#define MAC_PCS_XXV_LINK_SPEED_1 (0x8bf63593UL)
+#define MAC_PCS_XXV_LINK_SPEED_1_10G (0xc6271fd4UL)
+#define MAC_PCS_XXV_LINK_SPEED_1_SPEED (0xe6ae0bfUL)
+#define MAC_PCS_XXV_LINK_SPEED_1_TOGGLE (0x11853869UL)
+#define MAC_PCS_XXV_LINK_SPEED_2 (0x12ff6429UL)
+#define MAC_PCS_XXV_LINK_SPEED_2_10G (0x81876504UL)
+#define MAC_PCS_XXV_LINK_SPEED_2_SPEED (0x3f82fa22UL)
+#define MAC_PCS_XXV_LINK_SPEED_2_TOGGLE (0x9f0a3f8aUL)
+#define MAC_PCS_XXV_LINK_SPEED_3 (0x65f854bfUL)
+#define MAC_PCS_XXV_LINK_SPEED_3_10G (0xbce74cb4UL)
+#define MAC_PCS_XXV_LINK_SPEED_3_SPEED (0x99f5f196UL)
+#define MAC_PCS_XXV_LINK_SPEED_3_TOGGLE (0x53a03f14UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_0 (0xbdeefa9fUL)
+#define MAC_PCS_XXV_LINK_SUMMARY_0_ABS (0x881db88UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_0_ANEG_COMPLETE (0x5fc67735UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_0_ANEG_CONSORTIUM_MISMATCH (0x61d4136fUL)
+#define MAC_PCS_XXV_LINK_SUMMARY_0_INTERNAL_LOCAL_FAULT (0x16fc1a7aUL)
+#define MAC_PCS_XXV_LINK_SUMMARY_0_LH_ABS (0x159942b9UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_0_LH_INTERNAL_LOCAL_FAULT (0x95aab8f5UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_0_LH_LOCAL_FAULT (0x4a2e2158UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_0_LH_RECEIVED_LOCAL_FAULT (0x56dc5f65UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_0_LH_REMOTE_FAULT (0xbeeda6f3UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_0_LH_RX_FEC74_LOCK_ERROR (0xcf25e9b5UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_0_LH_RX_HIGH_BIT_ERROR_RATE (0x8d8fa991UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_0_LH_RX_PCS_VALID_CTRL_CODE (0x2846c322UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_0_LH_RX_RSFEC_HI_SER (0xbb5aafe6UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_0_LH_TX_LOCAL_FAULT (0x8f3e56b4UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_0_LH_TX_UNDERRUN (0xb1c337c4UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_0_LINK_DOWN_CNT (0xbe8bc6e3UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_0_LL_PHY_LINK_STATE (0x7050253fUL)
+#define MAC_PCS_XXV_LINK_SUMMARY_0_LL_RX_BLOCK_LOCK (0x639554a2UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_0_LL_RX_FEC74_LOCK (0x73211ce0UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_0_LL_RX_RSFEC_LANE_ALIGNMENT (0xd0bd97c6UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_0_LL_TX_RSFEC_LANE_ALIGNMENT (0x3d77e5bcUL)
+#define MAC_PCS_XXV_LINK_SUMMARY_0_LT_DONE (0xd2620565UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_0_NIM_INTERR (0x28ee3c81UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_0_NT_PHY_LINK_STATE (0x31581429UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_1 (0xcae9ca09UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_1_ABS (0x35e1f238UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_1_ANEG_COMPLETE (0xe63dacddUL)
+#define MAC_PCS_XXV_LINK_SUMMARY_1_ANEG_CONSORTIUM_MISMATCH (0x86c9b5f8UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_1_INTERNAL_LOCAL_FAULT (0x1d47ebaUL)
+#define MAC_PCS_XXV_LINK_SUMMARY_1_LH_ABS (0xd9334227UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_1_LH_INTERNAL_LOCAL_FAULT (0x302128fbUL)
+#define MAC_PCS_XXV_LINK_SUMMARY_1_LH_LOCAL_FAULT (0xe446b0c9UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_1_LH_RECEIVED_LOCAL_FAULT (0xf357cf6bUL)
+#define MAC_PCS_XXV_LINK_SUMMARY_1_LH_REMOTE_FAULT (0x394b6db0UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_1_LH_RX_FEC74_LOCK_ERROR (0x4e008c92UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_1_LH_RX_HIGH_BIT_ERROR_RATE (0xe303b2d0UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_1_LH_RX_PCS_VALID_CTRL_CODE (0x46cad863UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_1_LH_RX_RSFEC_HI_SER (0xde3d94a0UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_1_LH_TX_LOCAL_FAULT (0x58dcd6ecUL)
+#define MAC_PCS_XXV_LINK_SUMMARY_1_LH_TX_UNDERRUN (0x1faba655UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_1_LINK_DOWN_CNT (0x7701d0bUL)
+#define MAC_PCS_XXV_LINK_SUMMARY_1_LL_PHY_LINK_STATE (0xa7b2a567UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_1_LL_RX_BLOCK_LOCK (0x8cc7e243UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_1_LL_RX_FEC74_LOCK (0x9c73aa01UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_1_LL_RX_RSFEC_LANE_ALIGNMENT (0xd1086adbUL)
+#define MAC_PCS_XXV_LINK_SUMMARY_1_LL_TX_RSFEC_LANE_ALIGNMENT (0x3cc218a1UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_1_LT_DONE (0xc5191126UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_1_NIM_INTERR (0xb34b70eeUL)
+#define MAC_PCS_XXV_LINK_SUMMARY_1_NT_PHY_LINK_STATE (0xe6ba9471UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_2 (0x53e09bb3UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_2_ABS (0x724188e8UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_2_ANEG_COMPLETE (0xf740c6a4UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_2_ANEG_CONSORTIUM_MISMATCH (0x749e5800UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_2_INTERNAL_LOCAL_FAULT (0x38acd3faUL)
+#define MAC_PCS_XXV_LINK_SUMMARY_2_LH_ABS (0x57bc45c4UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_2_LH_INTERNAL_LOCAL_FAULT (0x5cc9ea8UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_2_LH_LOCAL_FAULT (0xcd8e043bUL)
+#define MAC_PCS_XXV_LINK_SUMMARY_2_LH_RECEIVED_LOCAL_FAULT (0xc6ba7938UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_2_LH_REMOTE_FAULT (0x6ad13634UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_2_LH_RX_FEC74_LOCK_ERROR (0x161e25baUL)
+#define MAC_PCS_XXV_LINK_SUMMARY_2_LH_RX_HIGH_BIT_ERROR_RATE (0x50979f13UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_2_LH_RX_PCS_VALID_CTRL_CODE (0xf55ef5a0UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_2_LH_RX_RSFEC_HI_SER (0x7194d96aUL)
+#define MAC_PCS_XXV_LINK_SUMMARY_2_LH_TX_LOCAL_FAULT (0xfb8a5045UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_2_LH_TX_UNDERRUN (0x366312a7UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_2_LINK_DOWN_CNT (0x160d7772UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_2_LL_PHY_LINK_STATE (0x4e423ceUL)
+#define MAC_PCS_XXV_LINK_SUMMARY_2_LL_RX_BLOCK_LOCK (0x66413f21UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_2_LL_RX_FEC74_LOCK (0x76f57763UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_2_LL_RX_RSFEC_LANE_ALIGNMENT (0xd3d66dfcUL)
+#define MAC_PCS_XXV_LINK_SUMMARY_2_LL_TX_RSFEC_LANE_ALIGNMENT (0x3e1c1f86UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_2_LT_DONE (0xfc942de3UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_2_NIM_INTERR (0xc4d5a21eUL)
+#define MAC_PCS_XXV_LINK_SUMMARY_2_NT_PHY_LINK_STATE (0x45ec12d8UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_3 (0x24e7ab25UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_3_ABS (0x4f21a158UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_3_ANEG_COMPLETE (0x4ebb1d4cUL)
+#define MAC_PCS_XXV_LINK_SUMMARY_3_ANEG_CONSORTIUM_MISMATCH (0x9383fe97UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_3_INTERNAL_LOCAL_FAULT (0x2f84b73aUL)
+#define MAC_PCS_XXV_LINK_SUMMARY_3_LH_ABS (0x9b16455aUL)
+#define MAC_PCS_XXV_LINK_SUMMARY_3_LH_INTERNAL_LOCAL_FAULT (0xa0470ea6UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_3_LH_LOCAL_FAULT (0x63e695aaUL)
+#define MAC_PCS_XXV_LINK_SUMMARY_3_LH_RECEIVED_LOCAL_FAULT (0x6331e936UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_3_LH_REMOTE_FAULT (0xed77fd77UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_3_LH_RX_FEC74_LOCK_ERROR (0x973b409dUL)
+#define MAC_PCS_XXV_LINK_SUMMARY_3_LH_RX_HIGH_BIT_ERROR_RATE (0x3e1b8452UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_3_LH_RX_PCS_VALID_CTRL_CODE (0x9bd2eee1UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_3_LH_RX_RSFEC_HI_SER (0x14f3e22cUL)
+#define MAC_PCS_XXV_LINK_SUMMARY_3_LH_TX_LOCAL_FAULT (0x2c68d01dUL)
+#define MAC_PCS_XXV_LINK_SUMMARY_3_LH_TX_UNDERRUN (0x980b8336UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_3_LINK_DOWN_CNT (0xaff6ac9aUL)
+#define MAC_PCS_XXV_LINK_SUMMARY_3_LL_PHY_LINK_STATE (0xd306a396UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_3_LL_RX_BLOCK_LOCK (0x891389c0UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_3_LL_RX_FEC74_LOCK (0x99a7c182UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_3_LL_RX_RSFEC_LANE_ALIGNMENT (0xd26390e1UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_3_LL_TX_RSFEC_LANE_ALIGNMENT (0x3fa9e29bUL)
+#define MAC_PCS_XXV_LINK_SUMMARY_3_LT_DONE (0xebef39a0UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_3_NIM_INTERR (0x5f70ee71UL)
+#define MAC_PCS_XXV_LINK_SUMMARY_3_NT_PHY_LINK_STATE (0x920e9280UL)
+#define MAC_PCS_XXV_LT_CONF_0 (0x26c9751bUL)
+#define MAC_PCS_XXV_LT_CONF_0_ENABLE (0xef1e1da6UL)
+#define MAC_PCS_XXV_LT_CONF_0_RESTART (0x2be9eb47UL)
+#define MAC_PCS_XXV_LT_CONF_0_SEED (0xfdf46f00UL)
+#define MAC_PCS_XXV_LT_CONF_1 (0x51ce458dUL)
+#define MAC_PCS_XXV_LT_CONF_1_ENABLE (0x23b41d38UL)
+#define MAC_PCS_XXV_LT_CONF_1_RESTART (0x3c92ff04UL)
+#define MAC_PCS_XXV_LT_CONF_1_SEED (0x36a8bca5UL)
+#define MAC_PCS_XXV_LT_CONF_2 (0xc8c71437UL)
+#define MAC_PCS_XXV_LT_CONF_2_ENABLE (0xad3b1adbUL)
+#define MAC_PCS_XXV_LT_CONF_2_RESTART (0x51fc3c1UL)
+#define MAC_PCS_XXV_LT_CONF_2_SEED (0xb03cce0bUL)
+#define MAC_PCS_XXV_LT_CONF_3 (0xbfc024a1UL)
+#define MAC_PCS_XXV_LT_CONF_3_ENABLE (0x61911a45UL)
+#define MAC_PCS_XXV_LT_CONF_3_RESTART (0x1264d782UL)
+#define MAC_PCS_XXV_LT_CONF_3_SEED (0x7b601daeUL)
+#define MAC_PCS_XXV_LT_STA_0 (0xb58612d6UL)
+#define MAC_PCS_XXV_LT_STA_0_DONE (0x3f809c59UL)
+#define MAC_PCS_XXV_LT_STA_0_FAIL (0xa98a57bbUL)
+#define MAC_PCS_XXV_LT_STA_0_LOCK (0xa822e7fcUL)
+#define MAC_PCS_XXV_LT_STA_0_TRAIN (0x3494fa27UL)
+#define MAC_PCS_XXV_LT_STA_1 (0xc2812240UL)
+#define MAC_PCS_XXV_LT_STA_1_DONE (0xf4dc4ffcUL)
+#define MAC_PCS_XXV_LT_STA_1_FAIL (0x62d6841eUL)
+#define MAC_PCS_XXV_LT_STA_1_LOCK (0x637e3459UL)
+#define MAC_PCS_XXV_LT_STA_1_TRAIN (0x92e3f193UL)
+#define MAC_PCS_XXV_LT_STA_2 (0x5b8873faUL)
+#define MAC_PCS_XXV_LT_STA_2_DONE (0x72483d52UL)
+#define MAC_PCS_XXV_LT_STA_2_FAIL (0xe442f6b0UL)
+#define MAC_PCS_XXV_LT_STA_2_LOCK (0xe5ea46f7UL)
+#define MAC_PCS_XXV_LT_STA_2_TRAIN (0xa30beb0eUL)
+#define MAC_PCS_XXV_LT_STA_3 (0x2c8f436cUL)
+#define MAC_PCS_XXV_LT_STA_3_DONE (0xb914eef7UL)
+#define MAC_PCS_XXV_LT_STA_3_FAIL (0x2f1e2515UL)
+#define MAC_PCS_XXV_LT_STA_3_LOCK (0x2eb69552UL)
+#define MAC_PCS_XXV_LT_STA_3_TRAIN (0x57ce0baUL)
+#define MAC_PCS_XXV_LT_TABLE_READBACK_0 (0x397037c0UL)
+#define MAC_PCS_XXV_LT_TABLE_READBACK_0_ATTRIB (0x38d464dcUL)
+#define MAC_PCS_XXV_LT_TABLE_READBACK_0_NEXT (0x75b189c5UL)
+#define MAC_PCS_XXV_LT_TABLE_READBACK_0_PREV (0xcd7c11acUL)
+#define MAC_PCS_XXV_LT_TABLE_READBACK_1 (0x4e770756UL)
+#define MAC_PCS_XXV_LT_TABLE_READBACK_1_ATTRIB (0xf47e6442UL)
+#define MAC_PCS_XXV_LT_TABLE_READBACK_1_NEXT (0xbeed5a60UL)
+#define MAC_PCS_XXV_LT_TABLE_READBACK_1_PREV (0x620c209UL)
+#define MAC_PCS_XXV_LT_TABLE_READBACK_2 (0xd77e56ecUL)
+#define MAC_PCS_XXV_LT_TABLE_READBACK_2_ATTRIB (0x7af163a1UL)
+#define MAC_PCS_XXV_LT_TABLE_READBACK_2_NEXT (0x387928ceUL)
+#define MAC_PCS_XXV_LT_TABLE_READBACK_2_PREV (0x80b4b0a7UL)
+#define MAC_PCS_XXV_LT_TABLE_READBACK_3 (0xa079667aUL)
+#define MAC_PCS_XXV_LT_TABLE_READBACK_3_ATTRIB (0xb65b633fUL)
+#define MAC_PCS_XXV_LT_TABLE_READBACK_3_NEXT (0xf325fb6bUL)
+#define MAC_PCS_XXV_LT_TABLE_READBACK_3_PREV (0x4be86302UL)
+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_0 (0xa935a75dUL)
+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_0_ATTRIB (0x86fe53feUL)
+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_0_NEXT (0xe6774ef1UL)
+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_0_PREV (0x5ebad698UL)
+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_0_SEL (0x155c6463UL)
+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_0_TABLE_ADDR (0xa7ff653fUL)
+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_0_UPDATE (0xc44806baUL)
+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_1 (0xde3297cbUL)
+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_1_ATTRIB (0x4a545360UL)
+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_1_NEXT (0x2d2b9d54UL)
+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_1_PREV (0x95e6053dUL)
+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_1_SEL (0x283c4dd3UL)
+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_1_TABLE_ADDR (0x3c5a2950UL)
+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_1_UPDATE (0x8e20624UL)
+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_2 (0x473bc671UL)
+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_2_ATTRIB (0xc4db5483UL)
+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_2_NEXT (0xabbfeffaUL)
+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_2_PREV (0x13727793UL)
+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_2_SEL (0x6f9c3703UL)
+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_2_TABLE_ADDR (0x4bc4fba0UL)
+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_2_UPDATE (0x866d01c7UL)
+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_3 (0x303cf6e7UL)
+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_3_ATTRIB (0x871541dUL)
+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_3_NEXT (0x60e33c5fUL)
+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_3_PREV (0xd82ea436UL)
+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_3_SEL (0x52fc1eb3UL)
+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_3_TABLE_ADDR (0xd061b7cfUL)
+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_3_UPDATE (0x4ac70159UL)
+#define MAC_PCS_XXV_MAC_RX_MAX_LENGTH_0 (0xca36b2f7UL)
+#define MAC_PCS_XXV_MAC_RX_MAX_LENGTH_0_RX_MAX_LENGTH (0xad9bad5fUL)
+#define MAC_PCS_XXV_MAC_RX_MAX_LENGTH_1 (0xbd318261UL)
+#define MAC_PCS_XXV_MAC_RX_MAX_LENGTH_1_RX_MAX_LENGTH (0x146076b7UL)
+#define MAC_PCS_XXV_MAC_RX_MAX_LENGTH_2 (0x2438d3dbUL)
+#define MAC_PCS_XXV_MAC_RX_MAX_LENGTH_2_RX_MAX_LENGTH (0x51d1cceUL)
+#define MAC_PCS_XXV_MAC_RX_MAX_LENGTH_3 (0x533fe34dUL)
+#define MAC_PCS_XXV_MAC_RX_MAX_LENGTH_3_RX_MAX_LENGTH (0xbce6c726UL)
+#define MAC_PCS_XXV_MAC_RX_MIN_LENGTH_0 (0x5a45a21dUL)
+#define MAC_PCS_XXV_MAC_RX_MIN_LENGTH_0_MIN_RX_FRAME (0x781d8621UL)
+#define MAC_PCS_XXV_MAC_RX_MIN_LENGTH_0_RX_MIN_LENGTH (0x4fca8931UL)
+#define MAC_PCS_XXV_MAC_RX_MIN_LENGTH_1 (0x2d42928bUL)
+#define MAC_PCS_XXV_MAC_RX_MIN_LENGTH_1_MIN_RX_FRAME (0xe5126757UL)
+#define MAC_PCS_XXV_MAC_RX_MIN_LENGTH_1_RX_MIN_LENGTH (0xf63152d9UL)
+#define MAC_PCS_XXV_MAC_RX_MIN_LENGTH_2 (0xb44bc331UL)
+#define MAC_PCS_XXV_MAC_RX_MIN_LENGTH_2_MIN_RX_FRAME (0x9973428cUL)
+#define MAC_PCS_XXV_MAC_RX_MIN_LENGTH_2_RX_MIN_LENGTH (0xe74c38a0UL)
+#define MAC_PCS_XXV_MAC_RX_MIN_LENGTH_3 (0xc34cf3a7UL)
+#define MAC_PCS_XXV_MAC_RX_MIN_LENGTH_3_MIN_RX_FRAME (0x47ca3faUL)
+#define MAC_PCS_XXV_MAC_RX_MIN_LENGTH_3_RX_MIN_LENGTH (0x5eb7e348UL)
+#define MAC_PCS_XXV_MAX_PKT_LEN_0 (0x5b190150UL)
+#define MAC_PCS_XXV_MAX_PKT_LEN_0_MAX_LEN (0xeaa0f0bUL)
+#define MAC_PCS_XXV_MAX_PKT_LEN_1 (0x2c1e31c6UL)
+#define MAC_PCS_XXV_MAX_PKT_LEN_1_MAX_LEN (0x19d11b48UL)
+#define MAC_PCS_XXV_MAX_PKT_LEN_2 (0xb517607cUL)
+#define MAC_PCS_XXV_MAX_PKT_LEN_2_MAX_LEN (0x205c278dUL)
+#define MAC_PCS_XXV_MAX_PKT_LEN_3 (0xc21050eaUL)
+#define MAC_PCS_XXV_MAX_PKT_LEN_3_MAX_LEN (0x372733ceUL)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_0 (0xbee01144UL)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_0_ADJ_MAIN (0x553fe7f6UL)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_0_ADJ_POST (0xb09d461fUL)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_0_ADJ_PRE (0x490c9445UL)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_0_ENABLE (0x1dc34d8aUL)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_0_INIT (0xff042d41UL)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_0_PRESET (0xc23c618aUL)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_0_RX_READY (0x5f37a378UL)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_1 (0xc9e721d2UL)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_1_ADJ_MAIN (0xbafd8cc8UL)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_1_ADJ_POST (0x5f5f2d21UL)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_1_ADJ_PRE (0x5e778006UL)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_1_ENABLE (0xd1694d14UL)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_1_INIT (0x3458fee4UL)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_1_PRESET (0xe966114UL)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_1_RX_READY (0xb0f5c846UL)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_2 (0x50ee7068UL)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_2_ADJ_MAIN (0x51ca37cbUL)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_2_ADJ_POST (0xb4689622UL)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_2_ADJ_PRE (0x67fabcc3UL)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_2_ENABLE (0x5fe64af7UL)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_2_INIT (0xb2cc8c4aUL)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_2_PRESET (0x801966f7UL)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_2_RX_READY (0x5bc27345UL)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_3 (0x27e940feUL)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_3_ADJ_MAIN (0xbe085cf5UL)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_3_ADJ_POST (0x5baafd1cUL)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_3_ADJ_PRE (0x7081a880UL)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_3_ENABLE (0x934c4a69UL)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_3_INIT (0x79905fefUL)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_3_PRESET (0x4cb36669UL)
+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_3_RX_READY (0xb400187bUL)
+#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_0 (0xf12740e1UL)
+#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_0_MAIN_STA (0xc1d6a542UL)
+#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_0_POST_STA (0xfe4a543bUL)
+#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_0_PRE_STA (0x3d4a42d1UL)
+#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_1 (0x86207077UL)
+#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_1_MAIN_STA (0x2e14ce7cUL)
+#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_1_POST_STA (0x11883f05UL)
+#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_1_PRE_STA (0x2a315692UL)
+#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_2 (0x1f2921cdUL)
+#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_2_MAIN_STA (0xc523757fUL)
+#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_2_POST_STA (0xfabf8406UL)
+#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_2_PRE_STA (0x13bc6a57UL)
+#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_3 (0x682e115bUL)
+#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_3_MAIN_STA (0x2ae11e41UL)
+#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_3_POST_STA (0x157def38UL)
+#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_3_PRE_STA (0x4c77e14UL)
+#define MAC_PCS_XXV_RST_0 (0xbc41405eUL)
+#define MAC_PCS_XXV_RST_0_MAC_PCS (0xb425c579UL)
+#define MAC_PCS_XXV_RST_1 (0xcb4670c8UL)
+#define MAC_PCS_XXV_RST_1_MAC_PCS (0xa35ed13aUL)
+#define MAC_PCS_XXV_RST_2 (0x524f2172UL)
+#define MAC_PCS_XXV_RST_2_MAC_PCS (0x9ad3edffUL)
+#define MAC_PCS_XXV_RST_3 (0x254811e4UL)
+#define MAC_PCS_XXV_RST_3_MAC_PCS (0x8da8f9bcUL)
+#define MAC_PCS_XXV_RS_FEC_CCW_CNT_0 (0x1fc33ac9UL)
+#define MAC_PCS_XXV_RS_FEC_CCW_CNT_0_RS_FEC_CCW_CNT (0x63c40291UL)
+#define MAC_PCS_XXV_RS_FEC_CCW_CNT_1 (0x68c40a5fUL)
+#define MAC_PCS_XXV_RS_FEC_CCW_CNT_1_RS_FEC_CCW_CNT (0xcdac9300UL)
+#define MAC_PCS_XXV_RS_FEC_CCW_CNT_2 (0xf1cd5be5UL)
+#define MAC_PCS_XXV_RS_FEC_CCW_CNT_2_RS_FEC_CCW_CNT (0xe46427f2UL)
+#define MAC_PCS_XXV_RS_FEC_CCW_CNT_3 (0x86ca6b73UL)
+#define MAC_PCS_XXV_RS_FEC_CCW_CNT_3_RS_FEC_CCW_CNT (0x4a0cb663UL)
+#define MAC_PCS_XXV_RS_FEC_CONF_0 (0x7de9885UL)
+#define MAC_PCS_XXV_RS_FEC_CONF_0_CONSORTIUM (0xaf731a5bUL)
+#define MAC_PCS_XXV_RS_FEC_CONF_0_RS_FEC_CORRECTION (0x574a1223UL)
+#define MAC_PCS_XXV_RS_FEC_CONF_0_RS_FEC_ENABLE (0xc8d960dUL)
+#define MAC_PCS_XXV_RS_FEC_CONF_0_RS_FEC_IEEE_ERROR_INDICATION (0xe5a25113UL)
+#define MAC_PCS_XXV_RS_FEC_CONF_0_RS_FEC_INDICATION (0x2487d64cUL)
+#define MAC_PCS_XXV_RS_FEC_CONF_1 (0x70d9a813UL)
+#define MAC_PCS_XXV_RS_FEC_CONF_1_CONSORTIUM (0x34d65634UL)
+#define MAC_PCS_XXV_RS_FEC_CONF_1_RS_FEC_CORRECTION (0x80a8927bUL)
+#define MAC_PCS_XXV_RS_FEC_CONF_1_RS_FEC_ENABLE (0xb5764de5UL)
+#define MAC_PCS_XXV_RS_FEC_CONF_1_RS_FEC_IEEE_ERROR_INDICATION (0xd9c2b21bUL)
+#define MAC_PCS_XXV_RS_FEC_CONF_1_RS_FEC_INDICATION (0xf3655614UL)
+#define MAC_PCS_XXV_RS_FEC_CONF_2 (0xe9d0f9a9UL)
+#define MAC_PCS_XXV_RS_FEC_CONF_2_CONSORTIUM (0x434884c4UL)
+#define MAC_PCS_XXV_RS_FEC_CONF_2_RS_FEC_CORRECTION (0x23fe14d2UL)
+#define MAC_PCS_XXV_RS_FEC_CONF_2_RS_FEC_ENABLE (0xa40b279cUL)
+#define MAC_PCS_XXV_RS_FEC_CONF_2_RS_FEC_IEEE_ERROR_INDICATION (0x9d639703UL)
+#define MAC_PCS_XXV_RS_FEC_CONF_2_RS_FEC_INDICATION (0x5033d0bdUL)
+#define MAC_PCS_XXV_RS_FEC_CONF_3 (0x9ed7c93fUL)
+#define MAC_PCS_XXV_RS_FEC_CONF_3_CONSORTIUM (0xd8edc8abUL)
+#define MAC_PCS_XXV_RS_FEC_CONF_3_RS_FEC_CORRECTION (0xf41c948aUL)
+#define MAC_PCS_XXV_RS_FEC_CONF_3_RS_FEC_ENABLE (0x1df0fc74UL)
+#define MAC_PCS_XXV_RS_FEC_CONF_3_RS_FEC_IEEE_ERROR_INDICATION (0xa103740bUL)
+#define MAC_PCS_XXV_RS_FEC_CONF_3_RS_FEC_INDICATION (0x87d150e5UL)
+#define MAC_PCS_XXV_RS_FEC_ERR_CNT_0 (0x8ef05d51UL)
+#define MAC_PCS_XXV_RS_FEC_ERR_CNT_0_RS_FEC_ERR_CNT (0x61cba0edUL)
+#define MAC_PCS_XXV_RS_FEC_ERR_CNT_1 (0xf9f76dc7UL)
+#define MAC_PCS_XXV_RS_FEC_ERR_CNT_1_RS_FEC_ERR_CNT (0xcfa3317cUL)
+#define MAC_PCS_XXV_RS_FEC_ERR_CNT_2 (0x60fe3c7dUL)
+#define MAC_PCS_XXV_RS_FEC_ERR_CNT_2_RS_FEC_ERR_CNT (0xe66b858eUL)
+#define MAC_PCS_XXV_RS_FEC_ERR_CNT_3 (0x17f90cebUL)
+#define MAC_PCS_XXV_RS_FEC_ERR_CNT_3_RS_FEC_ERR_CNT (0x4803141fUL)
+#define MAC_PCS_XXV_RS_FEC_UCW_CNT_0 (0xc0190132UL)
+#define MAC_PCS_XXV_RS_FEC_UCW_CNT_0_RS_FEC_UCW_CNT (0xa89c8608UL)
+#define MAC_PCS_XXV_RS_FEC_UCW_CNT_1 (0xb71e31a4UL)
+#define MAC_PCS_XXV_RS_FEC_UCW_CNT_1_RS_FEC_UCW_CNT (0x6f41799UL)
+#define MAC_PCS_XXV_RS_FEC_UCW_CNT_2 (0x2e17601eUL)
+#define MAC_PCS_XXV_RS_FEC_UCW_CNT_2_RS_FEC_UCW_CNT (0x2f3ca36bUL)
+#define MAC_PCS_XXV_RS_FEC_UCW_CNT_3 (0x59105088UL)
+#define MAC_PCS_XXV_RS_FEC_UCW_CNT_3_RS_FEC_UCW_CNT (0x815432faUL)
+#define MAC_PCS_XXV_RX_BAD_FCS_0 (0x53d3df14UL)
+#define MAC_PCS_XXV_RX_BAD_FCS_0_COUNT (0xf1329ab1UL)
+#define MAC_PCS_XXV_RX_BAD_FCS_1 (0x24d4ef82UL)
+#define MAC_PCS_XXV_RX_BAD_FCS_1_COUNT (0x57459105UL)
+#define MAC_PCS_XXV_RX_BAD_FCS_2 (0xbdddbe38UL)
+#define MAC_PCS_XXV_RX_BAD_FCS_2_COUNT (0x66ad8b98UL)
+#define MAC_PCS_XXV_RX_BAD_FCS_3 (0xcada8eaeUL)
+#define MAC_PCS_XXV_RX_BAD_FCS_3_COUNT (0xc0da802cUL)
+#define MAC_PCS_XXV_RX_FRAMING_ERROR_0 (0x88c256ceUL)
+#define MAC_PCS_XXV_RX_FRAMING_ERROR_0_COUNT (0x97189d30UL)
+#define MAC_PCS_XXV_RX_FRAMING_ERROR_1 (0xffc56658UL)
+#define MAC_PCS_XXV_RX_FRAMING_ERROR_1_COUNT (0x316f9684UL)
+#define MAC_PCS_XXV_RX_FRAMING_ERROR_2 (0x66cc37e2UL)
+#define MAC_PCS_XXV_RX_FRAMING_ERROR_2_COUNT (0x878c19UL)
+#define MAC_PCS_XXV_RX_FRAMING_ERROR_3 (0x11cb0774UL)
+#define MAC_PCS_XXV_RX_FRAMING_ERROR_3_COUNT (0xa6f087adUL)
+#define MAC_PCS_XXV_RX_GOOD_BYTES_0 (0xdb9d71adUL)
+#define MAC_PCS_XXV_RX_GOOD_BYTES_0_COUNT (0x970d9ccdUL)
+#define MAC_PCS_XXV_RX_GOOD_BYTES_1 (0xac9a413bUL)
+#define MAC_PCS_XXV_RX_GOOD_BYTES_1_COUNT (0x317a9779UL)
+#define MAC_PCS_XXV_RX_GOOD_BYTES_2 (0x35931081UL)
+#define MAC_PCS_XXV_RX_GOOD_BYTES_2_COUNT (0x928de4UL)
+#define MAC_PCS_XXV_RX_GOOD_BYTES_3 (0x42942017UL)
+#define MAC_PCS_XXV_RX_GOOD_BYTES_3_COUNT (0xa6e58650UL)
+#define MAC_PCS_XXV_RX_GOOD_PACKETS_0 (0xa1a32858UL)
+#define MAC_PCS_XXV_RX_GOOD_PACKETS_0_COUNT (0xaec3dbc9UL)
+#define MAC_PCS_XXV_RX_GOOD_PACKETS_1 (0xd6a418ceUL)
+#define MAC_PCS_XXV_RX_GOOD_PACKETS_1_COUNT (0x8b4d07dUL)
+#define MAC_PCS_XXV_RX_GOOD_PACKETS_2 (0x4fad4974UL)
+#define MAC_PCS_XXV_RX_GOOD_PACKETS_2_COUNT (0x395ccae0UL)
+#define MAC_PCS_XXV_RX_GOOD_PACKETS_3 (0x38aa79e2UL)
+#define MAC_PCS_XXV_RX_GOOD_PACKETS_3_COUNT (0x9f2bc154UL)
+#define MAC_PCS_XXV_RX_LATENCY_0 (0x636577a2UL)
+#define MAC_PCS_XXV_RX_LATENCY_0_LATENCY (0x5bc360b1UL)
+#define MAC_PCS_XXV_RX_LATENCY_1 (0x14624734UL)
+#define MAC_PCS_XXV_RX_LATENCY_1_LATENCY (0x4cb874f2UL)
+#define MAC_PCS_XXV_RX_TOTAL_BYTES_0 (0x566d6603UL)
+#define MAC_PCS_XXV_RX_TOTAL_BYTES_0_COUNT (0x95039b5UL)
+#define MAC_PCS_XXV_RX_TOTAL_BYTES_1 (0x216a5695UL)
+#define MAC_PCS_XXV_RX_TOTAL_BYTES_1_COUNT (0xaf273201UL)
+#define MAC_PCS_XXV_RX_TOTAL_BYTES_2 (0xb863072fUL)
+#define MAC_PCS_XXV_RX_TOTAL_BYTES_2_COUNT (0x9ecf289cUL)
+#define MAC_PCS_XXV_RX_TOTAL_BYTES_3 (0xcf6437b9UL)
+#define MAC_PCS_XXV_RX_TOTAL_BYTES_3_COUNT (0x38b82328UL)
+#define MAC_PCS_XXV_RX_TOTAL_PACKETS_0 (0x12f4b108UL)
+#define MAC_PCS_XXV_RX_TOTAL_PACKETS_0_COUNT (0xef99e10dUL)
+#define MAC_PCS_XXV_RX_TOTAL_PACKETS_1 (0x65f3819eUL)
+#define MAC_PCS_XXV_RX_TOTAL_PACKETS_1_COUNT (0x49eeeab9UL)
+#define MAC_PCS_XXV_RX_TOTAL_PACKETS_2 (0xfcfad024UL)
+#define MAC_PCS_XXV_RX_TOTAL_PACKETS_2_COUNT (0x7806f024UL)
+#define MAC_PCS_XXV_RX_TOTAL_PACKETS_3 (0x8bfde0b2UL)
+#define MAC_PCS_XXV_RX_TOTAL_PACKETS_3_COUNT (0xde71fb90UL)
+#define MAC_PCS_XXV_SUB_RST_0 (0xcea66ca4UL)
+#define MAC_PCS_XXV_SUB_RST_0_AN_LT (0xe868535cUL)
+#define MAC_PCS_XXV_SUB_RST_0_QPLL (0xf8a38742UL)
+#define MAC_PCS_XXV_SUB_RST_0_RX_BUF (0x56ef70f8UL)
+#define MAC_PCS_XXV_SUB_RST_0_RX_GT_DATA (0x233f5adcUL)
+#define MAC_PCS_XXV_SUB_RST_0_RX_MAC_PCS (0x1d82003eUL)
+#define MAC_PCS_XXV_SUB_RST_0_RX_PCS (0x380856daUL)
+#define MAC_PCS_XXV_SUB_RST_0_RX_PMA (0x55320a1cUL)
+#define MAC_PCS_XXV_SUB_RST_0_SPEED_CTRL (0xa1c62fb2UL)
+#define MAC_PCS_XXV_SUB_RST_0_TX_GT_DATA (0x2e212a9bUL)
+#define MAC_PCS_XXV_SUB_RST_0_TX_MAC_PCS (0x109c7079UL)
+#define MAC_PCS_XXV_SUB_RST_0_TX_PCS (0xee51b5c7UL)
+#define MAC_PCS_XXV_SUB_RST_0_TX_PMA (0x836be901UL)
+#define MAC_PCS_XXV_SUB_RST_1 (0xb9a15c32UL)
+#define MAC_PCS_XXV_SUB_RST_1_AN_LT (0x4e1f58e8UL)
+#define MAC_PCS_XXV_SUB_RST_1_QPLL (0x33ff54e7UL)
+#define MAC_PCS_XXV_SUB_RST_1_RX_BUF (0x9a457066UL)
+#define MAC_PCS_XXV_SUB_RST_1_RX_GT_DATA (0xb89a16b3UL)
+#define MAC_PCS_XXV_SUB_RST_1_RX_MAC_PCS (0x86274c51UL)
+#define MAC_PCS_XXV_SUB_RST_1_RX_PCS (0xf4a25644UL)
+#define MAC_PCS_XXV_SUB_RST_1_RX_PMA (0x99980a82UL)
+#define MAC_PCS_XXV_SUB_RST_1_SPEED_CTRL (0x3a6363ddUL)
+#define MAC_PCS_XXV_SUB_RST_1_TX_GT_DATA (0xb58466f4UL)
+#define MAC_PCS_XXV_SUB_RST_1_TX_MAC_PCS (0x8b393c16UL)
+#define MAC_PCS_XXV_SUB_RST_1_TX_PCS (0x22fbb559UL)
+#define MAC_PCS_XXV_SUB_RST_1_TX_PMA (0x4fc1e99fUL)
+#define MAC_PCS_XXV_SUB_RST_2 (0x20a80d88UL)
+#define MAC_PCS_XXV_SUB_RST_2_AN_LT (0x7ff74275UL)
+#define MAC_PCS_XXV_SUB_RST_2_QPLL (0xb56b2649UL)
+#define MAC_PCS_XXV_SUB_RST_2_RX_BUF (0x14ca7785UL)
+#define MAC_PCS_XXV_SUB_RST_2_RX_GT_DATA (0xcf04c443UL)
+#define MAC_PCS_XXV_SUB_RST_2_RX_MAC_PCS (0xf1b99ea1UL)
+#define MAC_PCS_XXV_SUB_RST_2_RX_PCS (0x7a2d51a7UL)
+#define MAC_PCS_XXV_SUB_RST_2_RX_PMA (0x17170d61UL)
+#define MAC_PCS_XXV_SUB_RST_2_SPEED_CTRL (0x4dfdb12dUL)
+#define MAC_PCS_XXV_SUB_RST_2_TX_GT_DATA (0xc21ab404UL)
+#define MAC_PCS_XXV_SUB_RST_2_TX_MAC_PCS (0xfca7eee6UL)
+#define MAC_PCS_XXV_SUB_RST_2_TX_PCS (0xac74b2baUL)
+#define MAC_PCS_XXV_SUB_RST_2_TX_PMA (0xc14eee7cUL)
+#define MAC_PCS_XXV_SUB_RST_3 (0x57af3d1eUL)
+#define MAC_PCS_XXV_SUB_RST_3_AN_LT (0xd98049c1UL)
+#define MAC_PCS_XXV_SUB_RST_3_QPLL (0x7e37f5ecUL)
+#define MAC_PCS_XXV_SUB_RST_3_RX_BUF (0xd860771bUL)
+#define MAC_PCS_XXV_SUB_RST_3_RX_GT_DATA (0x54a1882cUL)
+#define MAC_PCS_XXV_SUB_RST_3_RX_MAC_PCS (0x6a1cd2ceUL)
+#define MAC_PCS_XXV_SUB_RST_3_RX_PCS (0xb6875139UL)
+#define MAC_PCS_XXV_SUB_RST_3_RX_PMA (0xdbbd0dffUL)
+#define MAC_PCS_XXV_SUB_RST_3_SPEED_CTRL (0xd658fd42UL)
+#define MAC_PCS_XXV_SUB_RST_3_TX_GT_DATA (0x59bff86bUL)
+#define MAC_PCS_XXV_SUB_RST_3_TX_MAC_PCS (0x6702a289UL)
+#define MAC_PCS_XXV_SUB_RST_3_TX_PCS (0x60deb224UL)
+#define MAC_PCS_XXV_SUB_RST_3_TX_PMA (0xde4eee2UL)
+#define MAC_PCS_XXV_SUB_RST_STATUS_0 (0x31f1d051UL)
+#define MAC_PCS_XXV_SUB_RST_STATUS_0_QPLL_LOCK (0x2c39cf3dUL)
+#define MAC_PCS_XXV_SUB_RST_STATUS_0_USER_RX_RST (0xa1223741UL)
+#define MAC_PCS_XXV_SUB_RST_STATUS_0_USER_TX_RST (0x777bd45cUL)
+#define MAC_PCS_XXV_SUB_RST_STATUS_1 (0x46f6e0c7UL)
+#define MAC_PCS_XXV_SUB_RST_STATUS_1_QPLL_LOCK (0xedb710fdUL)
+#define MAC_PCS_XXV_SUB_RST_STATUS_1_USER_RX_RST (0x7cb4eec4UL)
+#define MAC_PCS_XXV_SUB_RST_STATUS_1_USER_TX_RST (0xaaed0dd9UL)
+#define MAC_PCS_XXV_SUB_RST_STATUS_2 (0xdfffb17dUL)
+#define MAC_PCS_XXV_SUB_RST_STATUS_2_QPLL_LOCK (0x745576fcUL)
+#define MAC_PCS_XXV_SUB_RST_STATUS_2_USER_RX_RST (0xc17e820aUL)
+#define MAC_PCS_XXV_SUB_RST_STATUS_2_USER_TX_RST (0x17276117UL)
+#define MAC_PCS_XXV_SUB_RST_STATUS_3 (0xa8f881ebUL)
+#define MAC_PCS_XXV_SUB_RST_STATUS_3_QPLL_LOCK (0xb5dba93cUL)
+#define MAC_PCS_XXV_SUB_RST_STATUS_3_USER_RX_RST (0x1ce85b8fUL)
+#define MAC_PCS_XXV_SUB_RST_STATUS_3_USER_TX_RST (0xcab1b892UL)
+#define MAC_PCS_XXV_TIMESTAMP_COMP_0 (0xa5e7869aUL)
+#define MAC_PCS_XXV_TIMESTAMP_COMP_0_RX_DLY (0x825d4fb7UL)
+#define MAC_PCS_XXV_TIMESTAMP_COMP_0_TX_DLY (0x5404acaaUL)
+#define MAC_PCS_XXV_TIMESTAMP_COMP_1 (0xd2e0b60cUL)
+#define MAC_PCS_XXV_TIMESTAMP_COMP_1_RX_DLY (0x4ef74f29UL)
+#define MAC_PCS_XXV_TIMESTAMP_COMP_1_TX_DLY (0x98aeac34UL)
+#define MAC_PCS_XXV_TIMESTAMP_COMP_2 (0x4be9e7b6UL)
+#define MAC_PCS_XXV_TIMESTAMP_COMP_2_RX_DLY (0xc07848caUL)
+#define MAC_PCS_XXV_TIMESTAMP_COMP_2_TX_DLY (0x1621abd7UL)
+#define MAC_PCS_XXV_TIMESTAMP_COMP_3 (0x3ceed720UL)
+#define MAC_PCS_XXV_TIMESTAMP_COMP_3_RX_DLY (0xcd24854UL)
+#define MAC_PCS_XXV_TIMESTAMP_COMP_3_TX_DLY (0xda8bab49UL)
+#define MAC_PCS_XXV_TX_BAD_FCS_0 (0xbcee7af4UL)
+#define MAC_PCS_XXV_TX_BAD_FCS_0_COUNT (0xff4e2634UL)
+#define MAC_PCS_XXV_TX_BAD_FCS_1 (0xcbe94a62UL)
+#define MAC_PCS_XXV_TX_BAD_FCS_1_COUNT (0x59392d80UL)
+#define MAC_PCS_XXV_TX_BAD_FCS_2 (0x52e01bd8UL)
+#define MAC_PCS_XXV_TX_BAD_FCS_2_COUNT (0x68d1371dUL)
+#define MAC_PCS_XXV_TX_BAD_FCS_3 (0x25e72b4eUL)
+#define MAC_PCS_XXV_TX_BAD_FCS_3_COUNT (0xcea63ca9UL)
+#define MAC_PCS_XXV_TX_FRAME_ERROR_0 (0x64717f86UL)
+#define MAC_PCS_XXV_TX_FRAME_ERROR_0_COUNT (0x17fd90f4UL)
+#define MAC_PCS_XXV_TX_FRAME_ERROR_1 (0x13764f10UL)
+#define MAC_PCS_XXV_TX_FRAME_ERROR_1_COUNT (0xb18a9b40UL)
+#define MAC_PCS_XXV_TX_FRAME_ERROR_2 (0x8a7f1eaaUL)
+#define MAC_PCS_XXV_TX_FRAME_ERROR_2_COUNT (0x806281ddUL)
+#define MAC_PCS_XXV_TX_FRAME_ERROR_3 (0xfd782e3cUL)
+#define MAC_PCS_XXV_TX_FRAME_ERROR_3_COUNT (0x26158a69UL)
+#define MAC_PCS_XXV_TX_GOOD_BYTES_0 (0xf967a55fUL)
+#define MAC_PCS_XXV_TX_GOOD_BYTES_0_COUNT (0x6130990bUL)
+#define MAC_PCS_XXV_TX_GOOD_BYTES_1 (0x8e6095c9UL)
+#define MAC_PCS_XXV_TX_GOOD_BYTES_1_COUNT (0xc74792bfUL)
+#define MAC_PCS_XXV_TX_GOOD_BYTES_2 (0x1769c473UL)
+#define MAC_PCS_XXV_TX_GOOD_BYTES_2_COUNT (0xf6af8822UL)
+#define MAC_PCS_XXV_TX_GOOD_BYTES_3 (0x606ef4e5UL)
+#define MAC_PCS_XXV_TX_GOOD_BYTES_3_COUNT (0x50d88396UL)
+#define MAC_PCS_XXV_TX_GOOD_PACKETS_0 (0x6979f50UL)
+#define MAC_PCS_XXV_TX_GOOD_PACKETS_0_COUNT (0x4309a9b3UL)
+#define MAC_PCS_XXV_TX_GOOD_PACKETS_1 (0x7190afc6UL)
+#define MAC_PCS_XXV_TX_GOOD_PACKETS_1_COUNT (0xe57ea207UL)
+#define MAC_PCS_XXV_TX_GOOD_PACKETS_2 (0xe899fe7cUL)
+#define MAC_PCS_XXV_TX_GOOD_PACKETS_2_COUNT (0xd496b89aUL)
+#define MAC_PCS_XXV_TX_GOOD_PACKETS_3 (0x9f9eceeaUL)
+#define MAC_PCS_XXV_TX_GOOD_PACKETS_3_COUNT (0x72e1b32eUL)
+#define MAC_PCS_XXV_TX_TOTAL_BYTES_0 (0x5fc0fe7UL)
+#define MAC_PCS_XXV_TX_TOTAL_BYTES_0_COUNT (0x7ba16335UL)
+#define MAC_PCS_XXV_TX_TOTAL_BYTES_1 (0x72fb3f71UL)
+#define MAC_PCS_XXV_TX_TOTAL_BYTES_1_COUNT (0xddd66881UL)
+#define MAC_PCS_XXV_TX_TOTAL_BYTES_2 (0xebf26ecbUL)
+#define MAC_PCS_XXV_TX_TOTAL_BYTES_2_COUNT (0xec3e721cUL)
+#define MAC_PCS_XXV_TX_TOTAL_BYTES_3 (0x9cf55e5dUL)
+#define MAC_PCS_XXV_TX_TOTAL_BYTES_3_COUNT (0x4a4979a8UL)
+#define MAC_PCS_XXV_TX_TOTAL_PACKETS_0 (0x1c880d8dUL)
+#define MAC_PCS_XXV_TX_TOTAL_PACKETS_0_COUNT (0x5fa4b35dUL)
+#define MAC_PCS_XXV_TX_TOTAL_PACKETS_1 (0x6b8f3d1bUL)
+#define MAC_PCS_XXV_TX_TOTAL_PACKETS_1_COUNT (0xf9d3b8e9UL)
+#define MAC_PCS_XXV_TX_TOTAL_PACKETS_2 (0xf2866ca1UL)
+#define MAC_PCS_XXV_TX_TOTAL_PACKETS_2_COUNT (0xc83ba274UL)
+#define MAC_PCS_XXV_TX_TOTAL_PACKETS_3 (0x85815c37UL)
+#define MAC_PCS_XXV_TX_TOTAL_PACKETS_3_COUNT (0x6e4ca9c0UL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_MAC_PCS_XXV_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_rx.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_rx.h
new file mode 100644
index 0000000000..e8dcf06144
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_rx.h
@@ -0,0 +1,90 @@
+/*
+ * nthw_fpga_reg_defs_mac_rx.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_MAC_RX_
+#define _NTHW_FPGA_REG_DEFS_MAC_RX_
+
+/* MAC_RX */
+#define NTHW_MOD_MAC_RX (0x6347b490UL)
+#define MAC_RX_BAD_FCS (0xca07f618UL)
+#define MAC_RX_BAD_FCS_COUNT (0x11d5ba0eUL)
+#define MAC_RX_BAD_PREAMBLE (0x8a9e1895UL)
+#define MAC_RX_BAD_PREAMBLE_COUNT (0x94cde758UL)
+#define MAC_RX_BAD_SFD (0x2e4ee601UL)
+#define MAC_RX_BAD_SFD_COUNT (0x1d1b1114UL)
+#define MAC_RX_BROADCAST (0xc601a955UL)
+#define MAC_RX_BROADCAST_COUNT (0x34215d1eUL)
+#define MAC_RX_FRAGMENT (0x5363b736UL)
+#define MAC_RX_FRAGMENT_COUNT (0xf664c9aUL)
+#define MAC_RX_INRANGEERR (0x8c827f5aUL)
+#define MAC_RX_INRANGEERR_COUNT (0x412374f1UL)
+#define MAC_RX_JABBER (0x2e057c27UL)
+#define MAC_RX_JABBER_COUNT (0x1b4d17b2UL)
+#define MAC_RX_MULTICAST (0x891e2299UL)
+#define MAC_RX_MULTICAST_COUNT (0xe7818f66UL)
+#define MAC_RX_OVERSIZE (0x7630fc85UL)
+#define MAC_RX_OVERSIZE_COUNT (0x5b25605eUL)
+#define MAC_RX_PACKET_1024_1518_BYTES (0xe525d34dUL)
+#define MAC_RX_PACKET_1024_1518_BYTES_COUNT (0x7d9de556UL)
+#define MAC_RX_PACKET_128_255_BYTES (0xcd8a378bUL)
+#define MAC_RX_PACKET_128_255_BYTES_COUNT (0x442e67ebUL)
+#define MAC_RX_PACKET_1519_1522_BYTES (0x681c88adUL)
+#define MAC_RX_PACKET_1519_1522_BYTES_COUNT (0x40d43ff6UL)
+#define MAC_RX_PACKET_1523_1548_BYTES (0x5dfe5acbUL)
+#define MAC_RX_PACKET_1523_1548_BYTES_COUNT (0x339a5140UL)
+#define MAC_RX_PACKET_1549_2047_BYTES (0x40c4e3d2UL)
+#define MAC_RX_PACKET_1549_2047_BYTES_COUNT (0x81fc4090UL)
+#define MAC_RX_PACKET_2048_4095_BYTES (0x4f3bdf16UL)
+#define MAC_RX_PACKET_2048_4095_BYTES_COUNT (0xba0d0879UL)
+#define MAC_RX_PACKET_256_511_BYTES (0x42cadeecUL)
+#define MAC_RX_PACKET_256_511_BYTES_COUNT (0x566f927UL)
+#define MAC_RX_PACKET_4096_8191_BYTES (0x3ad4685aUL)
+#define MAC_RX_PACKET_4096_8191_BYTES_COUNT (0xbc56edbfUL)
+#define MAC_RX_PACKET_512_1023_BYTES (0xa88bf6b7UL)
+#define MAC_RX_PACKET_512_1023_BYTES_COUNT (0x15430ff8UL)
+#define MAC_RX_PACKET_64_BYTES (0x35e6dcadUL)
+#define MAC_RX_PACKET_64_BYTES_COUNT (0xf81dddUL)
+#define MAC_RX_PACKET_65_127_BYTES (0x262f6a19UL)
+#define MAC_RX_PACKET_65_127_BYTES_COUNT (0xb010dafUL)
+#define MAC_RX_PACKET_8192_9215_BYTES (0x10cd73eaUL)
+#define MAC_RX_PACKET_8192_9215_BYTES_COUNT (0xa967837aUL)
+#define MAC_RX_PACKET_BAD_FCS (0x4cb8b34cUL)
+#define MAC_RX_PACKET_BAD_FCS_COUNT (0xb6701e28UL)
+#define MAC_RX_PACKET_LARGE (0xc11f49c8UL)
+#define MAC_RX_PACKET_LARGE_COUNT (0x884a975UL)
+#define MAC_RX_PACKET_SMALL (0xed318a65UL)
+#define MAC_RX_PACKET_SMALL_COUNT (0x72095ec7UL)
+#define MAC_RX_STOMPED_FCS (0xedbc183eUL)
+#define MAC_RX_STOMPED_FCS_COUNT (0xa0b5bc65UL)
+#define MAC_RX_TOOLONG (0x61da6643UL)
+#define MAC_RX_TOOLONG_COUNT (0xa789b6efUL)
+#define MAC_RX_TOTAL_BYTES (0x831313e2UL)
+#define MAC_RX_TOTAL_BYTES_COUNT (0xe5d8be59UL)
+#define MAC_RX_TOTAL_GOOD_BYTES (0x912c2d1cUL)
+#define MAC_RX_TOTAL_GOOD_BYTES_COUNT (0x63bb5f3eUL)
+#define MAC_RX_TOTAL_GOOD_PACKETS (0xfbb4f497UL)
+#define MAC_RX_TOTAL_GOOD_PACKETS_COUNT (0xae9d21b0UL)
+#define MAC_RX_TOTAL_PACKETS (0xb0ea3730UL)
+#define MAC_RX_TOTAL_PACKETS_COUNT (0x532c885dUL)
+#define MAC_RX_TRUNCATED (0x28c83348UL)
+#define MAC_RX_TRUNCATED_COUNT (0xb8e62fccUL)
+#define MAC_RX_UNDERSIZE (0xb6fa4bdbUL)
+#define MAC_RX_UNDERSIZE_COUNT (0x471945ffUL)
+#define MAC_RX_UNICAST (0xaa9e5b6cUL)
+#define MAC_RX_UNICAST_COUNT (0x814ecbf0UL)
+#define MAC_RX_VLAN (0x2f200d8dUL)
+#define MAC_RX_VLAN_COUNT (0xf156d97eUL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_MAC_RX_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_tfg.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_tfg.h
new file mode 100644
index 0000000000..0b36ffbea1
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_tfg.h
@@ -0,0 +1,42 @@
+/*
+ * nthw_fpga_reg_defs_mac_tfg.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_MAC_TFG_
+#define _NTHW_FPGA_REG_DEFS_MAC_TFG_
+
+/* MAC_TFG */
+#define NTHW_MOD_MAC_TFG (0x1a1aac23UL)
+#define MAC_TFG_TFG_ADDR (0x90a59c6bUL)
+#define MAC_TFG_TFG_ADDR_ADR (0x3ad0b041UL)
+#define MAC_TFG_TFG_ADDR_RDENA (0x32d2aecdUL)
+#define MAC_TFG_TFG_ADDR_RD_DONE (0x29dc9218UL)
+#define MAC_TFG_TFG_CTRL (0xc01d7f24UL)
+#define MAC_TFG_TFG_CTRL_ID_ENA (0x226f646eUL)
+#define MAC_TFG_TFG_CTRL_ID_POS (0xd22045fcUL)
+#define MAC_TFG_TFG_CTRL_RESTART (0xfd4f999eUL)
+#define MAC_TFG_TFG_CTRL_TG_ACT (0x5fd3d81UL)
+#define MAC_TFG_TFG_CTRL_TG_ENA (0xda870ffbUL)
+#define MAC_TFG_TFG_CTRL_TIME_MODE (0xa96c2409UL)
+#define MAC_TFG_TFG_CTRL_WRAP (0xdb215a6eUL)
+#define MAC_TFG_TFG_DATA (0x6fccfd3dUL)
+#define MAC_TFG_TFG_DATA_GAP (0x936a9790UL)
+#define MAC_TFG_TFG_DATA_ID (0x82eba4faUL)
+#define MAC_TFG_TFG_DATA_LENGTH (0x6db149f2UL)
+#define MAC_TFG_TFG_FRAME_HDR (0x632d9e2cUL)
+#define MAC_TFG_TFG_FRAME_HDR_HDR (0xe7a88ec1UL)
+#define MAC_TFG_TFG_REPETITION (0xde9617ebUL)
+#define MAC_TFG_TFG_REPETITION_CNT (0x4fee626dUL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_MAC_TFG_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_tx.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_tx.h
new file mode 100644
index 0000000000..d05556bce4
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_tx.h
@@ -0,0 +1,70 @@
+/*
+ * nthw_fpga_reg_defs_mac_tx.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_MAC_TX_
+#define _NTHW_FPGA_REG_DEFS_MAC_TX_
+
+/* MAC_TX */
+#define NTHW_MOD_MAC_TX (0x351d1316UL)
+#define MAC_TX_BAD_FCS (0xc719865fUL)
+#define MAC_TX_BAD_FCS_COUNT (0x4244d3eaUL)
+#define MAC_TX_BROADCAST (0x293c0cb5UL)
+#define MAC_TX_BROADCAST_COUNT (0x3a5de19bUL)
+#define MAC_TX_FRAME_ERRORS (0xaa9219a8UL)
+#define MAC_TX_FRAME_ERRORS_COUNT (0x63d223c3UL)
+#define MAC_TX_MULTICAST (0x66238779UL)
+#define MAC_TX_MULTICAST_COUNT (0xe9fd33e3UL)
+#define MAC_TX_PACKET_1024_1518_BYTES (0x8efebfebUL)
+#define MAC_TX_PACKET_1024_1518_BYTES_COUNT (0x5bcd97b0UL)
+#define MAC_TX_PACKET_128_255_BYTES (0x204045f1UL)
+#define MAC_TX_PACKET_128_255_BYTES_COUNT (0xd54fb772UL)
+#define MAC_TX_PACKET_1519_1522_BYTES (0x3c7e40bUL)
+#define MAC_TX_PACKET_1519_1522_BYTES_COUNT (0x66844d10UL)
+#define MAC_TX_PACKET_1523_1548_BYTES (0x3625366dUL)
+#define MAC_TX_PACKET_1523_1548_BYTES_COUNT (0x15ca23a6UL)
+#define MAC_TX_PACKET_1549_2047_BYTES (0x2b1f8f74UL)
+#define MAC_TX_PACKET_1549_2047_BYTES_COUNT (0xa7ac3276UL)
+#define MAC_TX_PACKET_2048_4095_BYTES (0x24e0b3b0UL)
+#define MAC_TX_PACKET_2048_4095_BYTES_COUNT (0x9c5d7a9fUL)
+#define MAC_TX_PACKET_256_511_BYTES (0xaf00ac96UL)
+#define MAC_TX_PACKET_256_511_BYTES_COUNT (0x940729beUL)
+#define MAC_TX_PACKET_4096_8191_BYTES (0x510f04fcUL)
+#define MAC_TX_PACKET_4096_8191_BYTES_COUNT (0x9a069f59UL)
+#define MAC_TX_PACKET_512_1023_BYTES (0x18b6a4e7UL)
+#define MAC_TX_PACKET_512_1023_BYTES_COUNT (0x9c0145c8UL)
+#define MAC_TX_PACKET_64_BYTES (0x3b9a6028UL)
+#define MAC_TX_PACKET_64_BYTES_COUNT (0xb0c54f8dUL)
+#define MAC_TX_PACKET_65_127_BYTES (0x54de3099UL)
+#define MAC_TX_PACKET_65_127_BYTES_COUNT (0xebd03e1UL)
+#define MAC_TX_PACKET_8192_9215_BYTES (0x7b161f4cUL)
+#define MAC_TX_PACKET_8192_9215_BYTES_COUNT (0x8f37f19cUL)
+#define MAC_TX_PACKET_LARGE (0xe3e59d3aUL)
+#define MAC_TX_PACKET_LARGE_COUNT (0xfeb9acb3UL)
+#define MAC_TX_PACKET_SMALL (0xcfcb5e97UL)
+#define MAC_TX_PACKET_SMALL_COUNT (0x84345b01UL)
+#define MAC_TX_TOTAL_BYTES (0x7bd15854UL)
+#define MAC_TX_TOTAL_BYTES_COUNT (0x61fb238cUL)
+#define MAC_TX_TOTAL_GOOD_BYTES (0xcf0260fUL)
+#define MAC_TX_TOTAL_GOOD_BYTES_COUNT (0x8603398UL)
+#define MAC_TX_TOTAL_GOOD_PACKETS (0xd89f151UL)
+#define MAC_TX_TOTAL_GOOD_PACKETS_COUNT (0x12c47c77UL)
+#define MAC_TX_TOTAL_PACKETS (0xe37b5ed4UL)
+#define MAC_TX_TOTAL_PACKETS_COUNT (0x21ddd2ddUL)
+#define MAC_TX_UNICAST (0xa7802b2bUL)
+#define MAC_TX_UNICAST_COUNT (0xd2dfa214UL)
+#define MAC_TX_VLAN (0x4cf038b7UL)
+#define MAC_TX_VLAN_COUNT (0x51b306a3UL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_MAC_TX_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_msk.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_msk.h
new file mode 100644
index 0000000000..fdc74e56bd
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_msk.h
@@ -0,0 +1,42 @@
+/*
+ * nthw_fpga_reg_defs_msk.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_MSK_
+#define _NTHW_FPGA_REG_DEFS_MSK_
+
+/* MSK */
+#define NTHW_MOD_MSK (0xcfd617eeUL)
+#define MSK_RCP_CTRL (0xc1c33daaUL)
+#define MSK_RCP_CTRL_ADR (0x350a336UL)
+#define MSK_RCP_CTRL_CNT (0x13583ae7UL)
+#define MSK_RCP_DATA (0x6e12bfb3UL)
+#define MSK_RCP_DATA_MASK_DYN0 (0x9d269a43UL)
+#define MSK_RCP_DATA_MASK_DYN1 (0xea21aad5UL)
+#define MSK_RCP_DATA_MASK_DYN2 (0x7328fb6fUL)
+#define MSK_RCP_DATA_MASK_DYN3 (0x42fcbf9UL)
+#define MSK_RCP_DATA_MASK_EN0 (0x487b2e09UL)
+#define MSK_RCP_DATA_MASK_EN1 (0x3f7c1e9fUL)
+#define MSK_RCP_DATA_MASK_EN2 (0xa6754f25UL)
+#define MSK_RCP_DATA_MASK_EN3 (0xd1727fb3UL)
+#define MSK_RCP_DATA_MASK_LEN0 (0x4daee8b8UL)
+#define MSK_RCP_DATA_MASK_LEN1 (0x3aa9d82eUL)
+#define MSK_RCP_DATA_MASK_LEN2 (0xa3a08994UL)
+#define MSK_RCP_DATA_MASK_LEN3 (0xd4a7b902UL)
+#define MSK_RCP_DATA_MASK_OFS0 (0xa2319513UL)
+#define MSK_RCP_DATA_MASK_OFS1 (0xd536a585UL)
+#define MSK_RCP_DATA_MASK_OFS2 (0x4c3ff43fUL)
+#define MSK_RCP_DATA_MASK_OFS3 (0x3b38c4a9UL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_MSK_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pci_rd_tg.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pci_rd_tg.h
new file mode 100644
index 0000000000..c21a1b20c3
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pci_rd_tg.h
@@ -0,0 +1,37 @@
+/*
+ * nthw_fpga_reg_defs_pci_rd_tg.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_PCI_RD_TG_
+#define _NTHW_FPGA_REG_DEFS_PCI_RD_TG_
+
+/* PCI_RD_TG */
+#define NTHW_MOD_PCI_RD_TG (0x9ad9eed2UL)
+#define PCI_RD_TG_TG_CTRL (0x5a899dc8UL)
+#define PCI_RD_TG_TG_CTRL_TG_RD_RDY (0x66c70bffUL)
+#define PCI_RD_TG_TG_RDADDR (0x39e1af65UL)
+#define PCI_RD_TG_TG_RDADDR_RAM_ADDR (0xf6b0ecd1UL)
+#define PCI_RD_TG_TG_RDDATA0 (0x4bcd36f9UL)
+#define PCI_RD_TG_TG_RDDATA0_PHYS_ADDR_LOW (0xa4479fe8UL)
+#define PCI_RD_TG_TG_RDDATA1 (0x3cca066fUL)
+#define PCI_RD_TG_TG_RDDATA1_PHYS_ADDR_HIGH (0x6b3563dfUL)
+#define PCI_RD_TG_TG_RDDATA2 (0xa5c357d5UL)
+#define PCI_RD_TG_TG_RDDATA2_REQ_HID (0x5dab4bc3UL)
+#define PCI_RD_TG_TG_RDDATA2_REQ_SIZE (0x85dd8d92UL)
+#define PCI_RD_TG_TG_RDDATA2_WAIT (0x85ba70b2UL)
+#define PCI_RD_TG_TG_RDDATA2_WRAP (0x546e238aUL)
+#define PCI_RD_TG_TG_RD_RUN (0xd6542f54UL)
+#define PCI_RD_TG_TG_RD_RUN_RD_ITERATION (0xcdc6e166UL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_PCI_RD_TG_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pci_ta.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pci_ta.h
new file mode 100644
index 0000000000..43dacda70a
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pci_ta.h
@@ -0,0 +1,32 @@
+/*
+ * nthw_fpga_reg_defs_pci_ta.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_PCI_TA_
+#define _NTHW_FPGA_REG_DEFS_PCI_TA_
+
+/* PCI_TA */
+#define NTHW_MOD_PCI_TA (0xfb431997UL)
+#define PCI_TA_CONTROL (0xa707df59UL)
+#define PCI_TA_CONTROL_ENABLE (0x87cdcc9aUL)
+#define PCI_TA_LENGTH_ERROR (0x8648b862UL)
+#define PCI_TA_LENGTH_ERROR_AMOUNT (0x8774bd63UL)
+#define PCI_TA_PACKET_BAD (0xaaa256d4UL)
+#define PCI_TA_PACKET_BAD_AMOUNT (0x601f72f3UL)
+#define PCI_TA_PACKET_GOOD (0xfc13da6cUL)
+#define PCI_TA_PACKET_GOOD_AMOUNT (0xd936d64dUL)
+#define PCI_TA_PAYLOAD_ERROR (0x69d7a09bUL)
+#define PCI_TA_PAYLOAD_ERROR_AMOUNT (0x445da330UL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_PCI_TA_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pci_wr_tg.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pci_wr_tg.h
new file mode 100644
index 0000000000..491152bb97
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pci_wr_tg.h
@@ -0,0 +1,40 @@
+/*
+ * nthw_fpga_reg_defs_pci_wr_tg.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_PCI_WR_TG_
+#define _NTHW_FPGA_REG_DEFS_PCI_WR_TG_
+
+/* PCI_WR_TG */
+#define NTHW_MOD_PCI_WR_TG (0x274b69e1UL)
+#define PCI_WR_TG_TG_CTRL (0xa48366c7UL)
+#define PCI_WR_TG_TG_CTRL_TG_WR_RDY (0x9983a3e8UL)
+#define PCI_WR_TG_TG_SEQ (0x8b3e0bd6UL)
+#define PCI_WR_TG_TG_SEQ_SEQUENCE (0xebf1c760UL)
+#define PCI_WR_TG_TG_WRADDR (0x2b7b95a5UL)
+#define PCI_WR_TG_TG_WRADDR_RAM_ADDR (0x5fdc2aceUL)
+#define PCI_WR_TG_TG_WRDATA0 (0xd0bb6e73UL)
+#define PCI_WR_TG_TG_WRDATA0_PHYS_ADDR_LOW (0x97cb1c89UL)
+#define PCI_WR_TG_TG_WRDATA1 (0xa7bc5ee5UL)
+#define PCI_WR_TG_TG_WRDATA1_PHYS_ADDR_HIGH (0x51b3be92UL)
+#define PCI_WR_TG_TG_WRDATA2 (0x3eb50f5fUL)
+#define PCI_WR_TG_TG_WRDATA2_INC_MODE (0x5be5577UL)
+#define PCI_WR_TG_TG_WRDATA2_REQ_HID (0xf4c78ddcUL)
+#define PCI_WR_TG_TG_WRDATA2_REQ_SIZE (0x87ceca1UL)
+#define PCI_WR_TG_TG_WRDATA2_WAIT (0xb29cb8ffUL)
+#define PCI_WR_TG_TG_WRDATA2_WRAP (0x6348ebc7UL)
+#define PCI_WR_TG_TG_WR_RUN (0xc4ce1594UL)
+#define PCI_WR_TG_TG_WR_RUN_WR_ITERATION (0xe83c0a22UL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_PCI_WR_TG_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcie3.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcie3.h
new file mode 100644
index 0000000000..4b8bf53cd9
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcie3.h
@@ -0,0 +1,281 @@
+/*
+ * nthw_fpga_reg_defs_pcie3.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_PCIE3_
+#define _NTHW_FPGA_REG_DEFS_PCIE3_
+
+/* PCIE3 */
+#define NTHW_MOD_PCIE3 (0xfbc48c18UL)
+#define PCIE3_BUILD_SEED (0x7a6457c5UL)
+#define PCIE3_BUILD_SEED_BUILD_SEED (0x626b816fUL)
+#define PCIE3_BUILD_TIME (0x51772c86UL)
+#define PCIE3_BUILD_TIME_TIME (0xe6ca8be1UL)
+#define PCIE3_CONFIG (0xe7ef0d51UL)
+#define PCIE3_CONFIG_EXT_TAG (0xce1f05adUL)
+#define PCIE3_CONFIG_MAX_READ (0x2943f801UL)
+#define PCIE3_CONFIG_MAX_TLP (0x2aa40e12UL)
+#define PCIE3_CONTROL (0x935935d4UL)
+#define PCIE3_CONTROL_RD_ATTR (0xc59aa0a3UL)
+#define PCIE3_CONTROL_WRAW (0x1fdd0c42UL)
+#define PCIE3_CONTROL_WR_ATTR (0x422d6e82UL)
+#define PCIE3_CORESPEED (0x5cbe0925UL)
+#define PCIE3_CORESPEED_CORESPEED (0x52ed2515UL)
+#define PCIE3_CORESPEED_DDR3SPEED (0xb69dba56UL)
+#define PCIE3_DRP_COMMON (0xffd331a2UL)
+#define PCIE3_DRP_COMMON_DRP_ADDR (0xbbfbc2fbUL)
+#define PCIE3_DRP_COMMON_DRP_RDY (0x8289f931UL)
+#define PCIE3_DRP_COMMON_GTH_SEL (0x40ac636fUL)
+#define PCIE3_DRP_COMMON_WR (0xbe76449eUL)
+#define PCIE3_DRP_DATE (0xeaae0e97UL)
+#define PCIE3_DRP_DATE_DRP_DATA (0xa27d4522UL)
+#define PCIE3_EP_TO_RP_ERR (0x3784de0fUL)
+#define PCIE3_EP_TO_RP_ERR_ERR_COR (0x3bb2d717UL)
+#define PCIE3_EP_TO_RP_ERR_ERR_FATAL (0xe6571da2UL)
+#define PCIE3_EP_TO_RP_ERR_ERR_NONFATAL (0xb3be48faUL)
+#define PCIE3_INT_CLR (0xcde216faUL)
+#define PCIE3_INT_CLR_AVR (0x1982c8eUL)
+#define PCIE3_INT_CLR_FHM (0x5d9e0821UL)
+#define PCIE3_INT_CLR_INT_0 (0x6cabf375UL)
+#define PCIE3_INT_CLR_INT_1 (0x1bacc3e3UL)
+#define PCIE3_INT_CLR_INT_10 (0xcdc3c020UL)
+#define PCIE3_INT_CLR_INT_11 (0xbac4f0b6UL)
+#define PCIE3_INT_CLR_INT_12 (0x23cda10cUL)
+#define PCIE3_INT_CLR_INT_13 (0x54ca919aUL)
+#define PCIE3_INT_CLR_INT_14 (0xcaae0439UL)
+#define PCIE3_INT_CLR_INT_15 (0xbda934afUL)
+#define PCIE3_INT_CLR_INT_16 (0x24a06515UL)
+#define PCIE3_INT_CLR_INT_17 (0x53a75583UL)
+#define PCIE3_INT_CLR_INT_18 (0xc3184812UL)
+#define PCIE3_INT_CLR_INT_19 (0xb41f7884UL)
+#define PCIE3_INT_CLR_INT_2 (0x82a59259UL)
+#define PCIE3_INT_CLR_INT_20 (0xe6ee93e3UL)
+#define PCIE3_INT_CLR_INT_21 (0x91e9a375UL)
+#define PCIE3_INT_CLR_INT_22 (0x8e0f2cfUL)
+#define PCIE3_INT_CLR_INT_23 (0x7fe7c259UL)
+#define PCIE3_INT_CLR_INT_24 (0xe18357faUL)
+#define PCIE3_INT_CLR_INT_25 (0x9684676cUL)
+#define PCIE3_INT_CLR_INT_26 (0xf8d36d6UL)
+#define PCIE3_INT_CLR_INT_27 (0x788a0640UL)
+#define PCIE3_INT_CLR_INT_28 (0xe8351bd1UL)
+#define PCIE3_INT_CLR_INT_29 (0x9f322b47UL)
+#define PCIE3_INT_CLR_INT_3 (0xf5a2a2cfUL)
+#define PCIE3_INT_CLR_INT_30 (0xfff5a2a2UL)
+#define PCIE3_INT_CLR_INT_31 (0x88f29234UL)
+#define PCIE3_INT_CLR_INT_4 (0x6bc6376cUL)
+#define PCIE3_INT_CLR_INT_5 (0x1cc107faUL)
+#define PCIE3_INT_CLR_INT_6 (0x85c85640UL)
+#define PCIE3_INT_CLR_INT_7 (0xf2cf66d6UL)
+#define PCIE3_INT_CLR_INT_8 (0x62707b47UL)
+#define PCIE3_INT_CLR_INT_9 (0x15774bd1UL)
+#define PCIE3_INT_CLR_PORT (0x4f57e46eUL)
+#define PCIE3_INT_CLR_PPS (0x3d2172d9UL)
+#define PCIE3_INT_CLR_QSPI (0xb3e7d744UL)
+#define PCIE3_INT_CLR_SPIM (0x87c5cc97UL)
+#define PCIE3_INT_CLR_SPIS (0x7dcaf1f4UL)
+#define PCIE3_INT_CLR_STA (0xa8b278ccUL)
+#define PCIE3_INT_CLR_TIMER (0x696afaafUL)
+#define PCIE3_INT_FORC (0x55ea48d8UL)
+#define PCIE3_INT_FORC_AVR (0x5b8cd9ffUL)
+#define PCIE3_INT_FORC_FHM (0x78afd50UL)
+#define PCIE3_INT_FORC_INT_0 (0x9758e745UL)
+#define PCIE3_INT_FORC_INT_1 (0xe05fd7d3UL)
+#define PCIE3_INT_FORC_INT_10 (0xebe10398UL)
+#define PCIE3_INT_FORC_INT_11 (0x9ce6330eUL)
+#define PCIE3_INT_FORC_INT_12 (0x5ef62b4UL)
+#define PCIE3_INT_FORC_INT_13 (0x72e85222UL)
+#define PCIE3_INT_FORC_INT_14 (0xec8cc781UL)
+#define PCIE3_INT_FORC_INT_15 (0x9b8bf717UL)
+#define PCIE3_INT_FORC_INT_16 (0x282a6adUL)
+#define PCIE3_INT_FORC_INT_17 (0x7585963bUL)
+#define PCIE3_INT_FORC_INT_18 (0xe53a8baaUL)
+#define PCIE3_INT_FORC_INT_19 (0x923dbb3cUL)
+#define PCIE3_INT_FORC_INT_2 (0x79568669UL)
+#define PCIE3_INT_FORC_INT_20 (0xc0cc505bUL)
+#define PCIE3_INT_FORC_INT_21 (0xb7cb60cdUL)
+#define PCIE3_INT_FORC_INT_22 (0x2ec23177UL)
+#define PCIE3_INT_FORC_INT_23 (0x59c501e1UL)
+#define PCIE3_INT_FORC_INT_24 (0xc7a19442UL)
+#define PCIE3_INT_FORC_INT_25 (0xb0a6a4d4UL)
+#define PCIE3_INT_FORC_INT_26 (0x29aff56eUL)
+#define PCIE3_INT_FORC_INT_27 (0x5ea8c5f8UL)
+#define PCIE3_INT_FORC_INT_28 (0xce17d869UL)
+#define PCIE3_INT_FORC_INT_29 (0xb910e8ffUL)
+#define PCIE3_INT_FORC_INT_3 (0xe51b6ffUL)
+#define PCIE3_INT_FORC_INT_30 (0xd9d7611aUL)
+#define PCIE3_INT_FORC_INT_31 (0xaed0518cUL)
+#define PCIE3_INT_FORC_INT_4 (0x9035235cUL)
+#define PCIE3_INT_FORC_INT_5 (0xe73213caUL)
+#define PCIE3_INT_FORC_INT_6 (0x7e3b4270UL)
+#define PCIE3_INT_FORC_INT_7 (0x93c72e6UL)
+#define PCIE3_INT_FORC_INT_8 (0x99836f77UL)
+#define PCIE3_INT_FORC_INT_9 (0xee845fe1UL)
+#define PCIE3_INT_FORC_PORT (0x680fb131UL)
+#define PCIE3_INT_FORC_PPS (0x673587a8UL)
+#define PCIE3_INT_FORC_QSPI (0x94bf821bUL)
+#define PCIE3_INT_FORC_SPIM (0xa09d99c8UL)
+#define PCIE3_INT_FORC_SPIS (0x5a92a4abUL)
+#define PCIE3_INT_FORC_STA (0xf2a68dbdUL)
+#define PCIE3_INT_FORC_TIMER (0x9299ee9fUL)
+#define PCIE3_INT_MASK (0x9fb55ba0UL)
+#define PCIE3_INT_MASK_AVR (0xadf52690UL)
+#define PCIE3_INT_MASK_FHM (0xf1f3023fUL)
+#define PCIE3_INT_MASK_IIC0 (0x856e56f1UL)
+#define PCIE3_INT_MASK_IIC1 (0xf2696667UL)
+#define PCIE3_INT_MASK_IIC2 (0x6b6037ddUL)
+#define PCIE3_INT_MASK_IIC3 (0x1c67074bUL)
+#define PCIE3_INT_MASK_IIC4 (0x820392e8UL)
+#define PCIE3_INT_MASK_IIC5 (0xf504a27eUL)
+#define PCIE3_INT_MASK_INT_0 (0x583f89d9UL)
+#define PCIE3_INT_MASK_INT_1 (0x2f38b94fUL)
+#define PCIE3_INT_MASK_INT_10 (0x1297bb99UL)
+#define PCIE3_INT_MASK_INT_11 (0x65908b0fUL)
+#define PCIE3_INT_MASK_INT_12 (0xfc99dab5UL)
+#define PCIE3_INT_MASK_INT_13 (0x8b9eea23UL)
+#define PCIE3_INT_MASK_INT_14 (0x15fa7f80UL)
+#define PCIE3_INT_MASK_INT_15 (0x62fd4f16UL)
+#define PCIE3_INT_MASK_INT_16 (0xfbf41eacUL)
+#define PCIE3_INT_MASK_INT_17 (0x8cf32e3aUL)
+#define PCIE3_INT_MASK_INT_18 (0x1c4c33abUL)
+#define PCIE3_INT_MASK_INT_19 (0x6b4b033dUL)
+#define PCIE3_INT_MASK_INT_2 (0xb631e8f5UL)
+#define PCIE3_INT_MASK_INT_20 (0x39bae85aUL)
+#define PCIE3_INT_MASK_INT_21 (0x4ebdd8ccUL)
+#define PCIE3_INT_MASK_INT_22 (0xd7b48976UL)
+#define PCIE3_INT_MASK_INT_23 (0xa0b3b9e0UL)
+#define PCIE3_INT_MASK_INT_24 (0x3ed72c43UL)
+#define PCIE3_INT_MASK_INT_25 (0x49d01cd5UL)
+#define PCIE3_INT_MASK_INT_26 (0xd0d94d6fUL)
+#define PCIE3_INT_MASK_INT_27 (0xa7de7df9UL)
+#define PCIE3_INT_MASK_INT_28 (0x37616068UL)
+#define PCIE3_INT_MASK_INT_29 (0x406650feUL)
+#define PCIE3_INT_MASK_INT_3 (0xc136d863UL)
+#define PCIE3_INT_MASK_INT_30 (0x20a1d91bUL)
+#define PCIE3_INT_MASK_INT_31 (0x57a6e98dUL)
+#define PCIE3_INT_MASK_INT_4 (0x5f524dc0UL)
+#define PCIE3_INT_MASK_INT_5 (0x28557d56UL)
+#define PCIE3_INT_MASK_INT_6 (0xb15c2cecUL)
+#define PCIE3_INT_MASK_INT_7 (0xc65b1c7aUL)
+#define PCIE3_INT_MASK_INT_8 (0x56e401ebUL)
+#define PCIE3_INT_MASK_INT_9 (0x21e3317dUL)
+#define PCIE3_INT_MASK_PORT (0xb5f4b407UL)
+#define PCIE3_INT_MASK_PPS (0x914c78c7UL)
+#define PCIE3_INT_MASK_QSPI (0x4944872dUL)
+#define PCIE3_INT_MASK_SPIM (0x7d669cfeUL)
+#define PCIE3_INT_MASK_SPIS (0x8769a19dUL)
+#define PCIE3_INT_MASK_STA (0x4df72d2UL)
+#define PCIE3_INT_MASK_TIMER (0x5dfe8003UL)
+#define PCIE3_LAT_CTRL (0x5c509767UL)
+#define PCIE3_LAT_CTRL_CLEAR_RAM (0x8a124a71UL)
+#define PCIE3_LAT_CTRL_ENABLE (0x47ce18e9UL)
+#define PCIE3_LAT_CTRL_PRESCAL (0x471e1378UL)
+#define PCIE3_LAT_CTRL_RAM_VLD (0x8efd11f9UL)
+#define PCIE3_LAT_CTRL_READ_RAM (0x9cfa1247UL)
+#define PCIE3_LAT_CTRL_STATUS (0xcf6eb5c7UL)
+#define PCIE3_LAT_MAX (0x316931d1UL)
+#define PCIE3_LAT_MAX_MAX (0xcb993f8fUL)
+#define PCIE3_LAT_RAMADR (0x745612a7UL)
+#define PCIE3_LAT_RAMADR_ADR (0x7516436aUL)
+#define PCIE3_LAT_RAMDATA (0xfc506b8dUL)
+#define PCIE3_LAT_RAMDATA_DATA (0x73152393UL)
+#define PCIE3_LINK_STATUS (0xab303a44UL)
+#define PCIE3_LINK_STATUS_CLEAR (0x2fda333UL)
+#define PCIE3_LINK_STATUS_RETRAIN_CNT (0xd32d9b1dUL)
+#define PCIE3_MARKADR_LSB (0xbf66115UL)
+#define PCIE3_MARKADR_LSB_ADR (0xfa67c336UL)
+#define PCIE3_MARKADR_MSB (0xa340b22UL)
+#define PCIE3_MARKADR_MSB_ADR (0x5c10c882UL)
+#define PCIE3_PB_INTERVAL (0x6d0029bfUL)
+#define PCIE3_PB_INTERVAL_INTERVAL (0xd3638bc4UL)
+#define PCIE3_PB_MAX_RD (0x14d4cfd0UL)
+#define PCIE3_PB_MAX_RD_PB (0xafae2778UL)
+#define PCIE3_PB_MAX_WR (0x9d778ec4UL)
+#define PCIE3_PB_MAX_WR_PB (0x123ca04bUL)
+#define PCIE3_PCIE_CTRL (0x6a657a79UL)
+#define PCIE3_PCIE_CTRL_EXT_TAG_ENA (0xc0feaf2UL)
+#define PCIE3_PCI_ENDPOINT (0xef3fb5fcUL)
+#define PCIE3_PCI_ENDPOINT_DMA_EP0_ALLOW_MASK (0x96497384UL)
+#define PCIE3_PCI_ENDPOINT_DMA_EP1_ALLOW_MASK (0xdec3febUL)
+#define PCIE3_PCI_ENDPOINT_GET_MSG (0x8d574999UL)
+#define PCIE3_PCI_ENDPOINT_IF_ID (0xe093c118UL)
+#define PCIE3_PCI_ENDPOINT_SEND_MSG (0x3c6e3993UL)
+#define PCIE3_PCI_TEST0 (0x9035b95dUL)
+#define PCIE3_PCI_TEST0_DATA (0xf1e900b8UL)
+#define PCIE3_PCI_TEST1 (0xe73289cbUL)
+#define PCIE3_PCI_TEST1_DATA (0x3ab5d31dUL)
+#define PCIE3_PCI_TEST2 (0x7e3bd871UL)
+#define PCIE3_PCI_TEST2_DATA (0xbc21a1b3UL)
+#define PCIE3_PCI_TEST3 (0x93ce8e7UL)
+#define PCIE3_PCI_TEST3_DATA (0x777d7216UL)
+#define PCIE3_PROD_ID_EX (0x8611a98cUL)
+#define PCIE3_PROD_ID_EX_LAYOUT (0x9df9070dUL)
+#define PCIE3_PROD_ID_EX_LAYOUT_VERSION (0xb1b84c8bUL)
+#define PCIE3_PROD_ID_EX_RESERVED (0x7eaa8a3bUL)
+#define PCIE3_PROD_ID_LSB (0x427df3d7UL)
+#define PCIE3_PROD_ID_LSB_GROUP_ID (0x79fb4c8UL)
+#define PCIE3_PROD_ID_LSB_REV_ID (0xc70a49f8UL)
+#define PCIE3_PROD_ID_LSB_VER_ID (0xd3f99cb9UL)
+#define PCIE3_PROD_ID_MSB (0x43bf99e0UL)
+#define PCIE3_PROD_ID_MSB_BUILD_NO (0xad3c5124UL)
+#define PCIE3_PROD_ID_MSB_PATCH_NO (0x77fde683UL)
+#define PCIE3_PROD_ID_MSB_TYPE_ID (0xdbb9d1adUL)
+#define PCIE3_RESET_CTRL (0xcc9a6c8bUL)
+#define PCIE3_RESET_CTRL_MASK (0xf060fbbcUL)
+#define PCIE3_RP_TO_EP_ERR (0x51d7e85fUL)
+#define PCIE3_RP_TO_EP_ERR_ERR_COR (0x394f4c0dUL)
+#define PCIE3_RP_TO_EP_ERR_ERR_FATAL (0x31a7af48UL)
+#define PCIE3_RP_TO_EP_ERR_ERR_NONFATAL (0x7c85237dUL)
+#define PCIE3_SAMPLE_TIME (0x6c2ab747UL)
+#define PCIE3_SAMPLE_TIME_SAMPLE_TIME (0xae51ac57UL)
+#define PCIE3_STATUS (0x48654731UL)
+#define PCIE3_STATUS_RD_ERR (0x153789c6UL)
+#define PCIE3_STATUS_TAGS_IN_USE (0x4dbe283UL)
+#define PCIE3_STATUS_WR_ERR (0xaa5a7a57UL)
+#define PCIE3_STATUS0 (0xa54dba5cUL)
+#define PCIE3_STATUS0_TAGS_IN_USE (0x67828096UL)
+#define PCIE3_STATUS0_UR_ADDR (0xcbf0c755UL)
+#define PCIE3_STATUS0_UR_DWORD (0x3e60a758UL)
+#define PCIE3_STATUS0_UR_FBE (0xba0c2851UL)
+#define PCIE3_STATUS0_UR_FMT (0x5724146cUL)
+#define PCIE3_STATUS0_UR_LBE (0xb79bad87UL)
+#define PCIE3_STATUS0_UR_REG (0x6cd416UL)
+#define PCIE3_STAT_CTRL (0xdef3e1d7UL)
+#define PCIE3_STAT_CTRL_STAT_ENA (0x613ed39aUL)
+#define PCIE3_STAT_CTRL_STAT_REQ (0x8614afc0UL)
+#define PCIE3_STAT_REFCLK (0xa4423dd2UL)
+#define PCIE3_STAT_REFCLK_REFCLK250 (0xf072561UL)
+#define PCIE3_STAT_RQ_RDY (0x3ab72682UL)
+#define PCIE3_STAT_RQ_RDY_COUNTER (0xbbf817faUL)
+#define PCIE3_STAT_RQ_VLD (0x9661688fUL)
+#define PCIE3_STAT_RQ_VLD_COUNTER (0x457981aaUL)
+#define PCIE3_STAT_RX (0xf2a8e7a1UL)
+#define PCIE3_STAT_RX_COUNTER (0x8d8ef524UL)
+#define PCIE3_STAT_TX (0xa4f24027UL)
+#define PCIE3_STAT_TX_COUNTER (0x80908563UL)
+#define PCIE3_TEST0 (0xa0e404f1UL)
+#define PCIE3_TEST0_DATA (0xf82b8d9cUL)
+#define PCIE3_TEST1 (0xd7e33467UL)
+#define PCIE3_TEST1_DATA (0x33775e39UL)
+#define PCIE3_TEST2_DATA (0x7151e5e8UL)
+#define PCIE3_TEST3_DATA (0xba0d364dUL)
+#define PCIE3_UUID0 (0x96ee4e29UL)
+#define PCIE3_UUID0_UUID0 (0x459d36b3UL)
+#define PCIE3_UUID1 (0xe1e97ebfUL)
+#define PCIE3_UUID1_UUID1 (0x94ed0d91UL)
+#define PCIE3_UUID2 (0x78e02f05UL)
+#define PCIE3_UUID2_UUID2 (0x3c0c46b6UL)
+#define PCIE3_UUID3 (0xfe71f93UL)
+#define PCIE3_UUID3_UUID3 (0xed7c7d94UL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_PCIE3_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcm_nt400dxx.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcm_nt400dxx.h
new file mode 100644
index 0000000000..34c10c3bea
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcm_nt400dxx.h
@@ -0,0 +1,19 @@
+/*
+ * nthw_fpga_reg_defs_pcm_nt400dxx.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_PCM_NT400DXX_
+#define _NTHW_FPGA_REG_DEFS_PCM_NT400DXX_
+
+#endif	/* _NTHW_FPGA_REG_DEFS_PCM_NT400DXX_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcm_nt50b01_01.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcm_nt50b01_01.h
new file mode 100644
index 0000000000..a3447de224
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcm_nt50b01_01.h
@@ -0,0 +1,19 @@
+/*
+ * nthw_fpga_reg_defs_pcm_nt50b01_01.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_PCM_NT50B01_01_
+#define _NTHW_FPGA_REG_DEFS_PCM_NT50B01_01_
+
+#endif	/* _NTHW_FPGA_REG_DEFS_PCM_NT50B01_01_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcs.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcs.h
new file mode 100644
index 0000000000..61efcee4e8
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcs.h
@@ -0,0 +1,92 @@
+/*
+ * nthw_fpga_reg_defs_pcs.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_PCS_
+#define _NTHW_FPGA_REG_DEFS_PCS_
+
+/* PCS */
+#define NTHW_MOD_PCS (0x8286adcaUL)
+#define PCS_BER_COUNT (0x2e91033bUL)
+#define PCS_BER_COUNT_CNT (0x8069b483UL)
+#define PCS_BIP_COUNT (0xeea1075dUL)
+#define PCS_BIP_COUNT_CNT (0xdd0f40c3UL)
+#define PCS_BLOCK_LOCK (0xcca988f2UL)
+#define PCS_BLOCK_LOCK_LOCK (0x8372ac9aUL)
+#define PCS_BLOCK_LOCK_LATCH (0x4b4db873UL)
+#define PCS_BLOCK_LOCK_LATCH_LATCH_LOCK (0x3e50cbe6UL)
+#define PCS_BLOCK_LOCK_ST (0x8f218598UL)
+#define PCS_BLOCK_LOCK_ST_LATCH_STATE (0xc29c506eUL)
+#define PCS_DDR3_STATUS (0xe0963286UL)
+#define PCS_DDR3_STATUS_CALIB_DONE (0x9a8acba0UL)
+#define PCS_DRP_CONFIG (0x7a62f621UL)
+#define PCS_DRP_CONFIG_DRP_ADR (0x77a5e19eUL)
+#define PCS_DRP_CONFIG_DRP_DI (0xae7df08dUL)
+#define PCS_DRP_CONFIG_DRP_EN (0x2902546fUL)
+#define PCS_DRP_CONFIG_DRP_WREN (0x3cfccbafUL)
+#define PCS_DRP_DATA (0x1d57f9a0UL)
+#define PCS_DRP_DATA_DRP_DO (0x5719fe67UL)
+#define PCS_DRP_DATA_DRP_RDY (0xe86bedd1UL)
+#define PCS_FSM_DONE (0xfb93f7e4UL)
+#define PCS_FSM_DONE_RX_RST_DONE (0x57e501cbUL)
+#define PCS_FSM_DONE_TX_RST_DONE (0xbf50cb88UL)
+#define PCS_GTH_CONFIG (0x4d111e36UL)
+#define PCS_GTH_CONFIG_EYE_SCAN_RST (0xf26521beUL)
+#define PCS_GTH_CONFIG_EYE_SCAN_TRIG (0xcd5499e3UL)
+#define PCS_GTH_CONFIG_GT_LOOP (0x8f0a29e8UL)
+#define PCS_GTH_CONFIG_GT_LPM_EN (0xca43244fUL)
+#define PCS_GTH_CONFIG_GT_MRST (0xc252e7eaUL)
+#define PCS_GTH_CONFIG_GT_RX_RST (0xd0dd4c8fUL)
+#define PCS_GTH_CONFIG_GT_SOFT_RST (0xf4291740UL)
+#define PCS_GTH_CONFIG_GT_TX_RST (0x684af92UL)
+#define PCS_GTH_CONFIG_RX_MONITOR_SEL (0xdb170715UL)
+#define PCS_GTH_CONFIG_RX_PCS_RST (0x63f7aa78UL)
+#define PCS_GTH_CONFIG_RX_USER_RDY (0x25431f5fUL)
+#define PCS_GTH_CONFIG_TX_PCS_RST (0x6ee9da3fUL)
+#define PCS_GTH_CONFIG_TX_USER_RDYU (0xddcfe06cUL)
+#define PCS_GTH_CONTROL (0x40253f3cUL)
+#define PCS_GTH_CONTROL_CPLL_LOCK (0xa7d1c749UL)
+#define PCS_GTH_CONTROL_CPLL_REFCLK_LOST (0x5d089cc9UL)
+#define PCS_GTH_CONTROL_RX_BUF_RST (0x44d16a8eUL)
+#define PCS_GTH_TX_TUNING (0x712f49ceUL)
+#define PCS_GTH_TX_TUNING_DIFF_CTRL (0x28d64209UL)
+#define PCS_GTH_TX_TUNING_POST_CURSOR (0x1baff955UL)
+#define PCS_GTH_TX_TUNING_PRE_CURSOR (0xc6ba5499UL)
+#define PCS_LANE_LOCK (0xfe988167UL)
+#define PCS_LANE_LOCK_LOCK (0x2f4590a6UL)
+#define PCS_LANE_LOCK_LATCH (0x648ef3c8UL)
+#define PCS_LANE_LOCK_LATCH_LATCH_LOCK (0x85bc8101UL)
+#define PCS_LANE_LOCK_ST (0xf4e544c2UL)
+#define PCS_LANE_LOCK_ST_LATCH_STATE (0x7755e260UL)
+#define PCS_LANE_MAPPING (0xabb9e1caUL)
+#define PCS_LANE_MAPPING_LANE (0x3a1fc704UL)
+#define PCS_LANE_OFFSET (0xbebd9e39UL)
+#define PCS_LANE_OFFSET_DIFF (0xac1cb16eUL)
+#define PCS_PCS_CONFIG (0x61138662UL)
+#define PCS_PCS_CONFIG_BER_RST (0x1ed2e4bfUL)
+#define PCS_PCS_CONFIG_BIP_RST (0x13d077a4UL)
+#define PCS_PCS_CONFIG_LANE_ADDR (0xc48ed818UL)
+#define PCS_PCS_CONFIG_LANE_BLOCK_CLR (0x6b249b8UL)
+#define PCS_PCS_CONFIG_TIME_OFFSET_RX (0xc19c631dUL)
+#define PCS_PCS_CONFIG_TXRX_LOOP (0x5c917a55UL)
+#define PCS_PCS_STATUS (0xce99cc02UL)
+#define PCS_PCS_STATUS_ALIGN (0x5376e136UL)
+#define PCS_PCS_STATUS_DELAY_ERR (0x3c8d9a55UL)
+#define PCS_PCS_STATUS_FIFO_DELAY (0x4e88e0e6UL)
+#define PCS_PCS_STATUS_HI_BER (0xe72cf1f6UL)
+#define PCS_POLARITY (0x206611d1UL)
+#define PCS_POLARITY_RX_POL (0xcfec2b60UL)
+#define PCS_POLARITY_TX_POL (0x19b5c87dUL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_PCS_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcs100.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcs100.h
new file mode 100644
index 0000000000..7c5b076eff
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcs100.h
@@ -0,0 +1,90 @@
+/*
+ * nthw_fpga_reg_defs_pcs100.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_PCS100_
+#define _NTHW_FPGA_REG_DEFS_PCS100_
+
+/* PCS100 */
+#define NTHW_MOD_PCS100 (0xa03da74fUL)
+#define PCS100_BER_COUNT (0x682da9a4UL)
+#define PCS100_BER_COUNT_CNT (0x666a98d6UL)
+#define PCS100_BIP_COUNT (0xa81dadc2UL)
+#define PCS100_BIP_COUNT_CNT (0x3b0c6c96UL)
+#define PCS100_BLOCK_LOCK (0xac5fba8dUL)
+#define PCS100_BLOCK_LOCK_LOCK (0x76668f6bUL)
+#define PCS100_BLOCK_LOCK_LATCH (0x81026edaUL)
+#define PCS100_BLOCK_LOCK_LATCH_LATCH_LOCK (0xc22270cUL)
+#define PCS100_BLOCK_LOCK_ST (0x6922a9cdUL)
+#define PCS100_BLOCK_LOCK_ST_LATCH_STATE (0x48d92300UL)
+#define PCS100_DDR3_STATUS (0x204ca819UL)
+#define PCS100_DDR3_STATUS_CALIB_DONE (0xfd635a82UL)
+#define PCS100_DRP_CONFIG (0x1a94c45eUL)
+#define PCS100_DRP_CONFIG_DRP_ADR (0x67d05b90UL)
+#define PCS100_DRP_CONFIG_DRP_DI (0x1bda417UL)
+#define PCS100_DRP_CONFIG_DRP_EN (0x86c200f5UL)
+#define PCS100_DRP_CONFIG_DRP_WREN (0xdb549312UL)
+#define PCS100_DRP_DATA (0xc8431f0fUL)
+#define PCS100_DRP_DATA_DRP_DO (0xa20ddd96UL)
+#define PCS100_DRP_DATA_DRP_RDY (0x22243b78UL)
+#define PCS100_FSM_DONE (0x2e87114bUL)
+#define PCS100_FSM_DONE_RX_RST_DONE (0xe2d266a2UL)
+#define PCS100_FSM_DONE_TX_RST_DONE (0xa67ace1UL)
+#define PCS100_GTH_CONFIG (0x2de72c49UL)
+#define PCS100_GTH_CONFIG_EYE_SCAN_RST (0x276289cbUL)
+#define PCS100_GTH_CONFIG_EYE_SCAN_TRIG (0xedee1bf8UL)
+#define PCS100_GTH_CONFIG_GT_LOOP (0x9f7f93e6UL)
+#define PCS100_GTH_CONFIG_GT_MRST (0xd2275de4UL)
+#define PCS100_GTH_CONFIG_GT_RX_RST (0x65ea2be6UL)
+#define PCS100_GTH_CONFIG_GT_SOFT_RST (0x93c08662UL)
+#define PCS100_GTH_CONFIG_GT_TX_RST (0xb3b3c8fbUL)
+#define PCS100_GTH_CONFIG_RX_MONITOR_SEL (0x5152747bUL)
+#define PCS100_GTH_CONFIG_RX_PCS_RST (0x572c44e3UL)
+#define PCS100_GTH_CONFIG_RX_USER_RDY (0x42aa8e7dUL)
+#define PCS100_GTH_CONFIG_TX_PCS_RST (0x5a3234a4UL)
+#define PCS100_GTH_CONFIG_TX_USER_RDYU (0x8c84819UL)
+#define PCS100_GTH_CONTROL (0x80ffa5a3UL)
+#define PCS100_GTH_CONTROL_CPLL_LOCK (0x930a29d2UL)
+#define PCS100_GTH_CONTROL_CPLL_REFCLK_LOST (0x1de5e543UL)
+#define PCS100_GTH_CONTROL_QPLL_LOCK (0x113c4325UL)
+#define PCS100_GTH_CONTROL_QPLL_REFCLK_LOST (0x7c62febeUL)
+#define PCS100_GTH_CONTROL_RX_BUF_RST (0x2338fbacUL)
+#define PCS100_GTH_TX_TUNING (0x972c659bUL)
+#define PCS100_GTH_TX_TUNING_DIFF_CTRL (0xfdd1ea7cUL)
+#define PCS100_GTH_TX_TUNING_POST_CURSOR (0x91ea8a3bUL)
+#define PCS100_GTH_TX_TUNING_PRE_CURSOR (0xe600d682UL)
+#define PCS100_LANE_LOCK (0xb8242bf8UL)
+#define PCS100_LANE_LOCK_LOCK (0x34a236f1UL)
+#define PCS100_LANE_LOCK_LATCH (0x919ad039UL)
+#define PCS100_LANE_LOCK_LATCH_LATCH_LOCK (0x2f3c882dUL)
+#define PCS100_LANE_LOCK_ST (0x9495108dUL)
+#define PCS100_LANE_LOCK_ST_LATCH_STATE (0x57ef607bUL)
+#define PCS100_LANE_MAPPING (0xcbc9b585UL)
+#define PCS100_LANE_MAPPING_LANE (0x95df939eUL)
+#define PCS100_LANE_OFFSET (0x7e6704a6UL)
+#define PCS100_LANE_OFFSET_DIFF (0x665367c7UL)
+#define PCS100_PCS_CONFIG (0x1e5b41dUL)
+#define PCS100_PCS_CONFIG_BER_RST (0xea75eb1UL)
+#define PCS100_PCS_CONFIG_BIP_RST (0x3a5cdaaUL)
+#define PCS100_PCS_CONFIG_LANE_ADDR (0x71b9bf71UL)
+#define PCS100_PCS_CONFIG_LANE_BLOCK_CLR (0x8cf73ad6UL)
+#define PCS100_PCS_CONFIG_TIME_OFFSET_RX (0x4bd91073UL)
+#define PCS100_PCS_CONFIG_TXRX_LOOP (0xe9a61d3cUL)
+#define PCS100_PCS_STATUS (0xae6ffe7dUL)
+#define PCS100_PCS_STATUS_ALIGN (0x9939379fUL)
+#define PCS100_PCS_STATUS_DELAY_ERR (0x89bafd3cUL)
+#define PCS100_PCS_STATUS_FIFO_DELAY (0x7a530e7dUL)
+#define PCS100_PCS_STATUS_HI_BER (0x48eca56cUL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_PCS100_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pdb.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pdb.h
new file mode 100644
index 0000000000..03d7c89dda
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pdb.h
@@ -0,0 +1,47 @@
+/*
+ * nthw_fpga_reg_defs_pdb.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_PDB_
+#define _NTHW_FPGA_REG_DEFS_PDB_
+
+/* PDB */
+#define NTHW_MOD_PDB (0xa7771bffUL)
+#define PDB_CONFIG (0xf73771edUL)
+#define PDB_CONFIG_PORT_OFS (0xb5b30335UL)
+#define PDB_CONFIG_TS_FORMAT (0x7013d8aUL)
+#define PDB_RCP_CTRL (0x28ac2b3aUL)
+#define PDB_RCP_CTRL_ADR (0x9d08b0e4UL)
+#define PDB_RCP_CTRL_CNT (0x8d002935UL)
+#define PDB_RCP_DATA (0x877da923UL)
+#define PDB_RCP_DATA_ALIGN (0xe802afb8UL)
+#define PDB_RCP_DATA_CRC_OVERWRITE (0x4847dc0aUL)
+#define PDB_RCP_DATA_DESCRIPTOR (0x46cb76faUL)
+#define PDB_RCP_DATA_DESC_LEN (0xf467e85bUL)
+#define PDB_RCP_DATA_DUPLICATE_BIT (0xaeb59507UL)
+#define PDB_RCP_DATA_DUPLICATE_EN (0xbab03efeUL)
+#define PDB_RCP_DATA_IP_PROT_TNL (0xec892325UL)
+#define PDB_RCP_DATA_OFS0_DYN (0xcef3786aUL)
+#define PDB_RCP_DATA_OFS0_REL (0xde219bd9UL)
+#define PDB_RCP_DATA_OFS1_DYN (0xf39351daUL)
+#define PDB_RCP_DATA_OFS1_REL (0xe341b269UL)
+#define PDB_RCP_DATA_OFS2_DYN (0xb4332b0aUL)
+#define PDB_RCP_DATA_OFS2_REL (0xa4e1c8b9UL)
+#define PDB_RCP_DATA_PCAP_KEEP_FCS (0x90bc735eUL)
+#define PDB_RCP_DATA_PPC_HSH (0xac10e9f8UL)
+#define PDB_RCP_DATA_TX_IGNORE (0x14c556dcUL)
+#define PDB_RCP_DATA_TX_NOW (0x479cb22cUL)
+#define PDB_RCP_DATA_TX_PORT (0x412a5ed8UL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_PDB_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pdi.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pdi.h
new file mode 100644
index 0000000000..8c48d5c2e5
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pdi.h
@@ -0,0 +1,48 @@
+/*
+ * nthw_fpga_reg_defs_pdi.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_PDI_
+#define _NTHW_FPGA_REG_DEFS_PDI_
+
+/* PDI */
+#define NTHW_MOD_PDI (0x30a5c277UL)
+#define PDI_CR (0x9d6d02a8UL)
+#define PDI_CR_EN (0x7a6160dUL)
+#define PDI_CR_PARITY (0xaed85250UL)
+#define PDI_CR_RST (0x26b77922UL)
+#define PDI_CR_RXRST (0xe1aedb39UL)
+#define PDI_CR_STOP (0x78eaf29eUL)
+#define PDI_CR_TXRST (0x6eee2e99UL)
+#define PDI_DRR (0x8ab88f08UL)
+#define PDI_DRR_DRR (0x157e17dfUL)
+#define PDI_DTR (0xdce2288eUL)
+#define PDI_DTR_DTR (0x957d5344UL)
+#define PDI_PRE (0x12440163UL)
+#define PDI_PRE_PRE (0xccd36afbUL)
+#define PDI_SR (0xd7af10f9UL)
+#define PDI_SR_DISABLE_BUSY (0xd8936666UL)
+#define PDI_SR_DONE (0xb64f984dUL)
+#define PDI_SR_ENABLE_BUSY (0xee39b4e3UL)
+#define PDI_SR_FRAME_ERR (0x7c7b177dUL)
+#define PDI_SR_OVERRUN_ERR (0x4093d29dUL)
+#define PDI_SR_PARITY_ERR (0xa12e1293UL)
+#define PDI_SR_RXLVL (0xe5b6087bUL)
+#define PDI_SR_RX_BUSY (0xeb248de4UL)
+#define PDI_SR_TXLVL (0x6af6fddbUL)
+#define PDI_SR_TX_BUSY (0x88f4b8deUL)
+#define PDI_SRR (0x93d13afdUL)
+#define PDI_SRR_RST (0x5fd4fe29UL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_PDI_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_phy_tile.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_phy_tile.h
new file mode 100644
index 0000000000..a2fbb01da8
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_phy_tile.h
@@ -0,0 +1,196 @@
+/*
+ * nthw_fpga_reg_defs_phy_tile.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_PHY_TILE_
+#define _NTHW_FPGA_REG_DEFS_PHY_TILE_
+
+/* PHY_TILE */
+#define NTHW_MOD_PHY_TILE (0x4e0aef6eUL)
+#define PHY_TILE_DR_CFG_STATUS (0x252aff33UL)
+#define PHY_TILE_DR_CFG_STATUS_CURR_PROFILE_ID (0x98db7e13UL)
+#define PHY_TILE_DR_CFG_STATUS_ERROR (0x594c35e7UL)
+#define PHY_TILE_DR_CFG_STATUS_IN_PROGRESS (0x62cdc29fUL)
+#define PHY_TILE_DYN_RECONFIG_BASE (0xda7abd93UL)
+#define PHY_TILE_DYN_RECONFIG_BASE_BUSY (0x3b97f6c6UL)
+#define PHY_TILE_DYN_RECONFIG_BASE_CMD (0xf6b609f6UL)
+#define PHY_TILE_DYN_RECONFIG_BASE_PTR (0x87020896UL)
+#define PHY_TILE_DYN_RECONFIG_DATA (0xb73db091UL)
+#define PHY_TILE_DYN_RECONFIG_DATA_DATA (0x74d2a935UL)
+#define PHY_TILE_LINK_SUMMARY_0 (0x2e6c2bb2UL)
+#define PHY_TILE_LINK_SUMMARY_0_LH_RECEIVED_LOCAL_FAULT (0x658fa4f2UL)
+#define PHY_TILE_LINK_SUMMARY_0_LH_REMOTE_FAULT (0x12c794faUL)
+#define PHY_TILE_LINK_SUMMARY_0_LH_RX_HIGH_BIT_ERROR_RATE (0x99e0ad8bUL)
+#define PHY_TILE_LINK_SUMMARY_0_LINK_DOWN_CNT (0x7c6a63a9UL)
+#define PHY_TILE_LINK_SUMMARY_0_LL_PHY_LINK_STATE (0x694563dcUL)
+#define PHY_TILE_LINK_SUMMARY_0_LL_RX_AM_LOCK (0xc958731bUL)
+#define PHY_TILE_LINK_SUMMARY_0_LL_RX_BLOCK_LOCK (0x1ae5c634UL)
+#define PHY_TILE_LINK_SUMMARY_0_NT_PHY_LINK_STATE (0x284d52caUL)
+#define PHY_TILE_LINK_SUMMARY_1 (0x596b1b24UL)
+#define PHY_TILE_LINK_SUMMARY_1_LH_RECEIVED_LOCAL_FAULT (0xc00434fcUL)
+#define PHY_TILE_LINK_SUMMARY_1_LH_REMOTE_FAULT (0x95615fb9UL)
+#define PHY_TILE_LINK_SUMMARY_1_LH_RX_HIGH_BIT_ERROR_RATE (0xf76cb6caUL)
+#define PHY_TILE_LINK_SUMMARY_1_LINK_DOWN_CNT (0xc591b841UL)
+#define PHY_TILE_LINK_SUMMARY_1_LL_PHY_LINK_STATE (0xbea7e384UL)
+#define PHY_TILE_LINK_SUMMARY_1_LL_RX_AM_LOCK (0x70a3a8f3UL)
+#define PHY_TILE_LINK_SUMMARY_1_LL_RX_BLOCK_LOCK (0xf5b770d5UL)
+#define PHY_TILE_LINK_SUMMARY_1_NT_PHY_LINK_STATE (0xffafd292UL)
+#define PHY_TILE_PORT_0_ETH_0_BASE (0x337c4712UL)
+#define PHY_TILE_PORT_0_ETH_0_BASE_BUSY (0xd5fbad30UL)
+#define PHY_TILE_PORT_0_ETH_0_BASE_CMD (0x948cd3f4UL)
+#define PHY_TILE_PORT_0_ETH_0_BASE_PTR (0xe538d294UL)
+#define PHY_TILE_PORT_0_ETH_0_DATA (0x5e3b4a10UL)
+#define PHY_TILE_PORT_0_ETH_0_DATA_DATA (0x9abef2c3UL)
+#define PHY_TILE_PORT_0_ETH_1_BASE (0xf82094b7UL)
+#define PHY_TILE_PORT_0_ETH_1_BASE_BUSY (0x147572f0UL)
+#define PHY_TILE_PORT_0_ETH_1_BASE_CMD (0x7b4eb8caUL)
+#define PHY_TILE_PORT_0_ETH_1_BASE_PTR (0xafab9aaUL)
+#define PHY_TILE_PORT_0_ETH_1_DATA (0x956799b5UL)
+#define PHY_TILE_PORT_0_ETH_1_DATA_DATA (0x5b302d03UL)
+#define PHY_TILE_PORT_0_ETH_2_BASE (0x7eb4e619UL)
+#define PHY_TILE_PORT_0_ETH_2_BASE_BUSY (0x8d9714f1UL)
+#define PHY_TILE_PORT_0_ETH_2_BASE_CMD (0x907903c9UL)
+#define PHY_TILE_PORT_0_ETH_2_BASE_PTR (0xe1cd02a9UL)
+#define PHY_TILE_PORT_0_ETH_2_DATA (0x13f3eb1bUL)
+#define PHY_TILE_PORT_0_ETH_2_DATA_DATA (0xc2d24b02UL)
+#define PHY_TILE_PORT_0_ETH_3_BASE (0xb5e835bcUL)
+#define PHY_TILE_PORT_0_ETH_3_BASE_BUSY (0x4c19cb31UL)
+#define PHY_TILE_PORT_0_ETH_3_BASE_CMD (0x7fbb68f7UL)
+#define PHY_TILE_PORT_0_ETH_3_BASE_PTR (0xe0f6997UL)
+#define PHY_TILE_PORT_0_ETH_3_DATA (0xd8af38beUL)
+#define PHY_TILE_PORT_0_ETH_3_DATA_DATA (0x35c94c2UL)
+#define PHY_TILE_PORT_0_XCVR_0_BASE (0x758a7765UL)
+#define PHY_TILE_PORT_0_XCVR_0_BASE_BUSY (0x79488eafUL)
+#define PHY_TILE_PORT_0_XCVR_0_BASE_CMD (0x9b560cdfUL)
+#define PHY_TILE_PORT_0_XCVR_0_BASE_PTR (0xeae20dbfUL)
+#define PHY_TILE_PORT_0_XCVR_0_DATA (0x18cd7a67UL)
+#define PHY_TILE_PORT_0_XCVR_0_DATA_DATA (0x360dd15cUL)
+#define PHY_TILE_PORT_0_XCVR_1_BASE (0xbed6a4c0UL)
+#define PHY_TILE_PORT_0_XCVR_1_BASE_BUSY (0xb8c6516fUL)
+#define PHY_TILE_PORT_0_XCVR_1_BASE_CMD (0x749467e1UL)
+#define PHY_TILE_PORT_0_XCVR_1_BASE_PTR (0x5206681UL)
+#define PHY_TILE_PORT_0_XCVR_1_DATA (0xd391a9c2UL)
+#define PHY_TILE_PORT_0_XCVR_1_DATA_DATA (0xf7830e9cUL)
+#define PHY_TILE_PORT_0_XCVR_2_BASE (0x3842d66eUL)
+#define PHY_TILE_PORT_0_XCVR_2_BASE_BUSY (0x2124376eUL)
+#define PHY_TILE_PORT_0_XCVR_2_BASE_CMD (0x9fa3dce2UL)
+#define PHY_TILE_PORT_0_XCVR_2_BASE_PTR (0xee17dd82UL)
+#define PHY_TILE_PORT_0_XCVR_2_DATA (0x5505db6cUL)
+#define PHY_TILE_PORT_0_XCVR_2_DATA_DATA (0x6e61689dUL)
+#define PHY_TILE_PORT_0_XCVR_3_BASE (0xf31e05cbUL)
+#define PHY_TILE_PORT_0_XCVR_3_BASE_BUSY (0xe0aae8aeUL)
+#define PHY_TILE_PORT_0_XCVR_3_BASE_CMD (0x7061b7dcUL)
+#define PHY_TILE_PORT_0_XCVR_3_BASE_PTR (0x1d5b6bcUL)
+#define PHY_TILE_PORT_0_XCVR_3_DATA (0x9e5908c9UL)
+#define PHY_TILE_PORT_0_XCVR_3_DATA_DATA (0xafefb75dUL)
+#define PHY_TILE_PORT_1_ETH_0_BASE (0xa8d90b7dUL)
+#define PHY_TILE_PORT_1_ETH_0_BASE_BUSY (0x525d6673UL)
+#define PHY_TILE_PORT_1_ETH_0_BASE_CMD (0x3ae44265UL)
+#define PHY_TILE_PORT_1_ETH_0_BASE_PTR (0x4b504305UL)
+#define PHY_TILE_PORT_1_ETH_0_DATA (0xc59e067fUL)
+#define PHY_TILE_PORT_1_ETH_0_DATA_DATA (0x1d183980UL)
+#define PHY_TILE_PORT_1_ETH_1_BASE (0x6385d8d8UL)
+#define PHY_TILE_PORT_1_ETH_1_BASE_BUSY (0x93d3b9b3UL)
+#define PHY_TILE_PORT_1_ETH_1_BASE_CMD (0xd526295bUL)
+#define PHY_TILE_PORT_1_ETH_1_BASE_PTR (0xa492283bUL)
+#define PHY_TILE_PORT_1_ETH_1_DATA (0xec2d5daUL)
+#define PHY_TILE_PORT_1_ETH_1_DATA_DATA (0xdc96e640UL)
+#define PHY_TILE_PORT_1_ETH_2_BASE (0xe511aa76UL)
+#define PHY_TILE_PORT_1_ETH_2_BASE_BUSY (0xa31dfb2UL)
+#define PHY_TILE_PORT_1_ETH_2_BASE_CMD (0x3e119258UL)
+#define PHY_TILE_PORT_1_ETH_2_BASE_PTR (0x4fa59338UL)
+#define PHY_TILE_PORT_1_ETH_2_DATA (0x8856a774UL)
+#define PHY_TILE_PORT_1_ETH_2_DATA_DATA (0x45748041UL)
+#define PHY_TILE_PORT_1_ETH_3_BASE (0x2e4d79d3UL)
+#define PHY_TILE_PORT_1_ETH_3_BASE_BUSY (0xcbbf0072UL)
+#define PHY_TILE_PORT_1_ETH_3_BASE_CMD (0xd1d3f966UL)
+#define PHY_TILE_PORT_1_ETH_3_BASE_PTR (0xa067f806UL)
+#define PHY_TILE_PORT_1_ETH_3_DATA (0x430a74d1UL)
+#define PHY_TILE_PORT_1_ETH_3_DATA_DATA (0x84fa5f81UL)
+#define PHY_TILE_PORT_1_XCVR_0_BASE (0xa81caee0UL)
+#define PHY_TILE_PORT_1_XCVR_0_BASE_BUSY (0x961a384eUL)
+#define PHY_TILE_PORT_1_XCVR_0_BASE_CMD (0x1cf0c79cUL)
+#define PHY_TILE_PORT_1_XCVR_0_BASE_PTR (0x6d44c6fcUL)
+#define PHY_TILE_PORT_1_XCVR_0_DATA (0xc55ba3e2UL)
+#define PHY_TILE_PORT_1_XCVR_0_DATA_DATA (0xd95f67bdUL)
+#define PHY_TILE_PORT_1_XCVR_1_BASE (0x63407d45UL)
+#define PHY_TILE_PORT_1_XCVR_1_BASE_BUSY (0x5794e78eUL)
+#define PHY_TILE_PORT_1_XCVR_1_BASE_CMD (0xf332aca2UL)
+#define PHY_TILE_PORT_1_XCVR_1_BASE_PTR (0x8286adc2UL)
+#define PHY_TILE_PORT_1_XCVR_1_DATA (0xe077047UL)
+#define PHY_TILE_PORT_1_XCVR_1_DATA_DATA (0x18d1b87dUL)
+#define PHY_TILE_PORT_1_XCVR_2_BASE (0xe5d40febUL)
+#define PHY_TILE_PORT_1_XCVR_2_BASE_BUSY (0xce76818fUL)
+#define PHY_TILE_PORT_1_XCVR_2_BASE_CMD (0x180517a1UL)
+#define PHY_TILE_PORT_1_XCVR_2_BASE_PTR (0x69b116c1UL)
+#define PHY_TILE_PORT_1_XCVR_2_DATA (0x889302e9UL)
+#define PHY_TILE_PORT_1_XCVR_2_DATA_DATA (0x8133de7cUL)
+#define PHY_TILE_PORT_1_XCVR_3_BASE (0x2e88dc4eUL)
+#define PHY_TILE_PORT_1_XCVR_3_BASE_BUSY (0xff85e4fUL)
+#define PHY_TILE_PORT_1_XCVR_3_BASE_CMD (0xf7c77c9fUL)
+#define PHY_TILE_PORT_1_XCVR_3_BASE_PTR (0x86737dffUL)
+#define PHY_TILE_PORT_1_XCVR_3_DATA (0x43cfd14cUL)
+#define PHY_TILE_PORT_1_XCVR_3_DATA_DATA (0x40bd01bcUL)
+#define PHY_TILE_PORT_COMP_0 (0xfc048a04UL)
+#define PHY_TILE_PORT_COMP_0_RX_COMPENSATION (0xffba9733UL)
+#define PHY_TILE_PORT_COMP_0_TX_COMPENSATION (0xdd4043c1UL)
+#define PHY_TILE_PORT_COMP_1 (0x8b03ba92UL)
+#define PHY_TILE_PORT_COMP_1_RX_COMPENSATION (0x781c5c70UL)
+#define PHY_TILE_PORT_COMP_1_TX_COMPENSATION (0x5ae68882UL)
+#define PHY_TILE_PORT_CONFIG (0x24e3ab60UL)
+#define PHY_TILE_PORT_CONFIG_DYN_RESET (0x72b5f859UL)
+#define PHY_TILE_PORT_CONFIG_NT_FORCE_LINK_DOWN_0 (0x7e66781UL)
+#define PHY_TILE_PORT_CONFIG_NT_FORCE_LINK_DOWN_1 (0x70e15717UL)
+#define PHY_TILE_PORT_CONFIG_NT_LINKUP_LATENCY_0 (0x33fd94c2UL)
+#define PHY_TILE_PORT_CONFIG_NT_LINKUP_LATENCY_1 (0x44faa454UL)
+#define PHY_TILE_PORT_CONFIG_RESET_0 (0xf0e1e1c4UL)
+#define PHY_TILE_PORT_CONFIG_RESET_1 (0x87e6d152UL)
+#define PHY_TILE_PORT_CONFIG_RX_RESET_0 (0x70027edeUL)
+#define PHY_TILE_PORT_CONFIG_RX_RESET_1 (0x7054e48UL)
+#define PHY_TILE_PORT_CONFIG_TX_RESET_0 (0x7d1c0e99UL)
+#define PHY_TILE_PORT_CONFIG_TX_RESET_1 (0xa1b3e0fUL)
+#define PHY_TILE_PORT_STATUS (0x8b69e100UL)
+#define PHY_TILE_PORT_STATUS_RESET_ACK_N_0 (0x812f344UL)
+#define PHY_TILE_PORT_STATUS_RESET_ACK_N_1 (0x7f15c3d2UL)
+#define PHY_TILE_PORT_STATUS_RX_AM_LOCK_0 (0x18c38950UL)
+#define PHY_TILE_PORT_STATUS_RX_AM_LOCK_1 (0x6fc4b9c6UL)
+#define PHY_TILE_PORT_STATUS_RX_BLOCK_LOCK_0 (0x72b847a5UL)
+#define PHY_TILE_PORT_STATUS_RX_BLOCK_LOCK_1 (0x5bf7733UL)
+#define PHY_TILE_PORT_STATUS_RX_CDR_LOCK_0 (0x8557733cUL)
+#define PHY_TILE_PORT_STATUS_RX_CDR_LOCK_1 (0xf25043aaUL)
+#define PHY_TILE_PORT_STATUS_RX_HI_BER_0 (0xae6e5427UL)
+#define PHY_TILE_PORT_STATUS_RX_HI_BER_1 (0xd96964b1UL)
+#define PHY_TILE_PORT_STATUS_RX_LOCAL_FAULT_0 (0xb7de3d5eUL)
+#define PHY_TILE_PORT_STATUS_RX_LOCAL_FAULT_1 (0xc0d90dc8UL)
+#define PHY_TILE_PORT_STATUS_RX_PCS_FULLY_ALIGNED_0 (0x690e7dbcUL)
+#define PHY_TILE_PORT_STATUS_RX_PCS_FULLY_ALIGNED_1 (0x1e094d2aUL)
+#define PHY_TILE_PORT_STATUS_RX_PCS_READY_0 (0x4bb3d53cUL)
+#define PHY_TILE_PORT_STATUS_RX_PCS_READY_1 (0x3cb4e5aaUL)
+#define PHY_TILE_PORT_STATUS_RX_PTP_OFFSET_DATA_VALID_0 (0x4a8305e7UL)
+#define PHY_TILE_PORT_STATUS_RX_PTP_OFFSET_DATA_VALID_1 (0x3d843571UL)
+#define PHY_TILE_PORT_STATUS_RX_PTP_READY_0 (0xb74c7368UL)
+#define PHY_TILE_PORT_STATUS_RX_PTP_READY_1 (0xc04b43feUL)
+#define PHY_TILE_PORT_STATUS_RX_REMOTE_FAULT_0 (0x7160c5c7UL)
+#define PHY_TILE_PORT_STATUS_RX_REMOTE_FAULT_1 (0x667f551UL)
+#define PHY_TILE_PORT_STATUS_SYSTEMPLL_LOCK (0x3d44b5b8UL)
+#define PHY_TILE_PORT_STATUS_SYS_PLL_LOCKED_0 (0x9a284858UL)
+#define PHY_TILE_PORT_STATUS_SYS_PLL_LOCKED_1 (0xed2f78ceUL)
+#define PHY_TILE_PORT_STATUS_TX_LANES_STABLE_0 (0x9d0d322aUL)
+#define PHY_TILE_PORT_STATUS_TX_LANES_STABLE_1 (0xea0a02bcUL)
+#define PHY_TILE_PORT_STATUS_TX_PLL_LOCKED_0 (0x56587371UL)
+#define PHY_TILE_PORT_STATUS_TX_PLL_LOCKED_1 (0x215f43e7UL)
+#define PHY_TILE_SCRATCH (0xcd637527UL)
+#define PHY_TILE_SCRATCH_DATA (0x1934d873UL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_PHY_TILE_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_prm_nt400dxx.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_prm_nt400dxx.h
new file mode 100644
index 0000000000..87f255bfea
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_prm_nt400dxx.h
@@ -0,0 +1,19 @@
+/*
+ * nthw_fpga_reg_defs_prm_nt400dxx.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_PRM_NT400DXX_
+#define _NTHW_FPGA_REG_DEFS_PRM_NT400DXX_
+
+#endif	/* _NTHW_FPGA_REG_DEFS_PRM_NT400DXX_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_prm_nt50b01_01.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_prm_nt50b01_01.h
new file mode 100644
index 0000000000..193598092d
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_prm_nt50b01_01.h
@@ -0,0 +1,19 @@
+/*
+ * nthw_fpga_reg_defs_prm_nt50b01_01.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_PRM_NT50B01_01_
+#define _NTHW_FPGA_REG_DEFS_PRM_NT50B01_01_
+
+#endif	/* _NTHW_FPGA_REG_DEFS_PRM_NT50B01_01_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_qsl.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_qsl.h
new file mode 100644
index 0000000000..c768109866
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_qsl.h
@@ -0,0 +1,65 @@
+/*
+ * nthw_fpga_reg_defs_qsl.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_QSL_
+#define _NTHW_FPGA_REG_DEFS_QSL_
+
+/* QSL */
+#define NTHW_MOD_QSL (0x448ed859UL)
+#define QSL_LTX_CTRL (0xd16859aUL)
+#define QSL_LTX_CTRL_ADR (0x56ab4bfeUL)
+#define QSL_LTX_CTRL_CNT (0x46a3d22fUL)
+#define QSL_LTX_DATA (0xa2c70783UL)
+#define QSL_LTX_DATA_LR (0xbd09e686UL)
+#define QSL_LTX_DATA_TSA (0xdc9172f1UL)
+#define QSL_LTX_DATA_TX_PORT (0x4e838100UL)
+#define QSL_QEN_CTRL (0xfe8ed79cUL)
+#define QSL_QEN_CTRL_ADR (0x81d44d48UL)
+#define QSL_QEN_CTRL_CNT (0x91dcd499UL)
+#define QSL_QEN_DATA (0x515f5585UL)
+#define QSL_QEN_DATA_EN (0xa1e5961UL)
+#define QSL_QST_CTRL (0x58cd5f95UL)
+#define QSL_QST_CTRL_ADR (0xf71b52e1UL)
+#define QSL_QST_CTRL_CNT (0xe713cb30UL)
+#define QSL_QST_DATA (0xf71cdd8cUL)
+#define QSL_QST_DATA_EN (0x19406021UL)
+#define QSL_QST_DATA_LRE (0x71626c7eUL)
+#define QSL_QST_DATA_QEN (0xf7cd0143UL)
+#define QSL_QST_DATA_QUEUE (0x70bc6d12UL)
+#define QSL_QST_DATA_TCI (0x3938f18dUL)
+#define QSL_QST_DATA_TX_PORT (0x101a63f0UL)
+#define QSL_QST_DATA_VEN (0xf28217c6UL)
+#define QSL_RCP_CTRL (0x2a0d86aeUL)
+#define QSL_RCP_CTRL_ADR (0x2798e4a0UL)
+#define QSL_RCP_CTRL_CNT (0x37907d71UL)
+#define QSL_RCP_DATA (0x85dc04b7UL)
+#define QSL_RCP_DATA_CAO (0x2b87358eUL)
+#define QSL_RCP_DATA_DISCARD (0x5b3da2b8UL)
+#define QSL_RCP_DATA_DROP (0x30f5b2fbUL)
+#define QSL_RCP_DATA_LR (0x3f2331c2UL)
+#define QSL_RCP_DATA_TBL_HI (0xde81892fUL)
+#define QSL_RCP_DATA_TBL_IDX (0xa8d19ee1UL)
+#define QSL_RCP_DATA_TBL_LO (0x538ee91eUL)
+#define QSL_RCP_DATA_TBL_MSK (0x2ee5f375UL)
+#define QSL_RCP_DATA_TSA (0xada2ddafUL)
+#define QSL_RCP_DATA_VLI (0x6da78f6dUL)
+#define QSL_UNMQ_CTRL (0xe759d3f1UL)
+#define QSL_UNMQ_CTRL_ADR (0xe5833152UL)
+#define QSL_UNMQ_CTRL_CNT (0xf58ba883UL)
+#define QSL_UNMQ_DATA (0x488851e8UL)
+#define QSL_UNMQ_DATA_DEST_QUEUE (0xef8ce959UL)
+#define QSL_UNMQ_DATA_EN (0x36ca8378UL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_QSL_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_qspi.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_qspi.h
new file mode 100644
index 0000000000..a34df75c14
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_qspi.h
@@ -0,0 +1,89 @@
+/*
+ * nthw_fpga_reg_defs_qspi.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_QSPI_
+#define _NTHW_FPGA_REG_DEFS_QSPI_
+
+/* QSPI */
+#define NTHW_MOD_QSPI (0x29862c6cUL)
+#define QSPI_CR (0xef84e130UL)
+#define QSPI_CR_CPHA (0x948dc9b4UL)
+#define QSPI_CR_CPOL (0xa57d23ceUL)
+#define QSPI_CR_LOOP (0xfe658b9aUL)
+#define QSPI_CR_LSBF (0xaa231a92UL)
+#define QSPI_CR_MSSAE (0xa5dafdd0UL)
+#define QSPI_CR_MST (0xd32a6268UL)
+#define QSPI_CR_MTI (0xff6d9876UL)
+#define QSPI_CR_RXFIFO_RST (0x66004882UL)
+#define QSPI_CR_SPE (0x840f9f23UL)
+#define QSPI_CR_TXFIFO_RST (0x6b1e38c5UL)
+#define QSPI_DGIE (0xe9a50117UL)
+#define QSPI_DGIE_GIE (0xf5dbca66UL)
+#define QSPI_DRR (0x741e7d9dUL)
+#define QSPI_DRR_DATA_VAL (0xd7977338UL)
+#define QSPI_DTR (0x2244da1bUL)
+#define QSPI_DTR_DATA_VAL (0x3f22b97bUL)
+#define QSPI_IER (0x79456a58UL)
+#define QSPI_IER_CMD_ERR (0x80d9abaUL)
+#define QSPI_IER_CPOL_CPHA_ERR (0x607c3883UL)
+#define QSPI_IER_DRR_FULL (0xbb33732UL)
+#define QSPI_IER_DRR_NEMPTY (0xf947b1acUL)
+#define QSPI_IER_DRR_OR (0x1fe5371bUL)
+#define QSPI_IER_DTR_EMPTY (0x8b2c2a00UL)
+#define QSPI_IER_DTR_UR (0x20883860UL)
+#define QSPI_IER_LOOP_ERR (0xfc3eeec4UL)
+#define QSPI_IER_MODF (0x75955c38UL)
+#define QSPI_IER_MSB_ERR (0xeeae77acUL)
+#define QSPI_IER_SLV_ERR (0xbeaf1133UL)
+#define QSPI_IER_SLV_MODF (0x3f016834UL)
+#define QSPI_IER_SLV_MS (0x14b5e998UL)
+#define QSPI_IER_TXFIFO_HEMPTY (0x4711acf3UL)
+#define QSPI_ISR (0x65dddf8fUL)
+#define QSPI_ISR_CMD_ERR (0x22bd6b15UL)
+#define QSPI_ISR_CPOL_CPHA_ERR (0xd5ca6ff9UL)
+#define QSPI_ISR_DRR_FULL (0x4df039baUL)
+#define QSPI_ISR_DRR_NEMPTY (0xeda5c8abUL)
+#define QSPI_ISR_DRR_OR (0xc03f0ce0UL)
+#define QSPI_ISR_DTR_EMPTY (0x6809621cUL)
+#define QSPI_ISR_DTR_UR (0xff52039bUL)
+#define QSPI_ISR_LOOP_ERR (0xba7de04cUL)
+#define QSPI_ISR_MODF (0x719bf5ccUL)
+#define QSPI_ISR_MSB_ERR (0xc41e8603UL)
+#define QSPI_ISR_SLV_ERR (0x941fe09cUL)
+#define QSPI_ISR_SLV_MODF (0x794266bcUL)
+#define QSPI_ISR_SLV_MS (0xcb6fd263UL)
+#define QSPI_ISR_TXFIFO_HEMPTY (0xf2a7fb89UL)
+#define QSPI_RX_FIFO_OCY (0xd5306ee6UL)
+#define QSPI_RX_FIFO_OCY_OCY_VAL (0x315cad36UL)
+#define QSPI_SR (0xa546f361UL)
+#define QSPI_SR_CMD_ERR (0x224e01f5UL)
+#define QSPI_SR_CPOL_CPHA_ERR (0x84dfa2deUL)
+#define QSPI_SR_LOOP_ERR (0x1a77f15eUL)
+#define QSPI_SR_MODF (0x36271cabUL)
+#define QSPI_SR_MSB_ERR (0xc4edece3UL)
+#define QSPI_SR_RXEMPTY (0xace9ac96UL)
+#define QSPI_SR_RXFULL (0xafa43e79UL)
+#define QSPI_SR_SLVMS (0x50619a67UL)
+#define QSPI_SR_SLV_ERR (0x94ec8a7cUL)
+#define QSPI_SR_TXEMPTY (0xcf3999acUL)
+#define QSPI_SR_TXFULL (0x79fddd64UL)
+#define QSPI_SRR (0x6d77c868UL)
+#define QSPI_SRR_RST (0xc1528c75UL)
+#define QSPI_SSR (0x746cf929UL)
+#define QSPI_SSR_SEL_SLV (0x1e9e863cUL)
+#define QSPI_TX_FIFO_OCY (0x3d85a4a5UL)
+#define QSPI_TX_FIFO_OCY_OCY_VAL (0xac80a625UL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_QSPI_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_r2drp.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_r2drp.h
new file mode 100644
index 0000000000..ffff2552fe
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_r2drp.h
@@ -0,0 +1,29 @@
+/*
+ * nthw_fpga_reg_defs_r2drp.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_R2DRP_
+#define _NTHW_FPGA_REG_DEFS_R2DRP_
+
+/* R2DRP */
+#define NTHW_MOD_R2DRP (0x8b673fa6UL)
+#define R2DRP_CTRL (0x6fe03b4eUL)
+#define R2DRP_CTRL_ADR (0xd107f065UL)
+#define R2DRP_CTRL_DATA (0x899f99f3UL)
+#define R2DRP_CTRL_DBG_BUSY (0x96d9901aUL)
+#define R2DRP_CTRL_DONE (0x34418a3bUL)
+#define R2DRP_CTRL_RES (0xa17bec9bUL)
+#define R2DRP_CTRL_WREN (0x1635422aUL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_R2DRP_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rac.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rac.h
new file mode 100644
index 0000000000..b4af411b47
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rac.h
@@ -0,0 +1,72 @@
+/*
+ * nthw_fpga_reg_defs_rac.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_RAC_
+#define _NTHW_FPGA_REG_DEFS_RAC_
+
+/* RAC */
+#define NTHW_MOD_RAC (0xae830b42UL)
+#define RAC_DBG_CTRL (0x587273e2UL)
+#define RAC_DBG_CTRL_C (0x4fe263UL)
+#define RAC_DBG_DATA (0xf7a3f1fbUL)
+#define RAC_DBG_DATA_D (0x69d9305UL)
+#define RAC_DUMMY0 (0xd8e9ed5bUL)
+#define RAC_DUMMY1 (0xafeeddcdUL)
+#define RAC_DUMMY2 (0x36e78c77UL)
+#define RAC_NDM_REGISTER (0x36b9e7d0UL)
+#define RAC_NDM_REGISTER_NDM (0xf791ef23UL)
+#define RAC_NMB_DATA (0xc0e60c69UL)
+#define RAC_NMB_DATA_NMB_DATA (0x21f71466UL)
+#define RAC_NMB_RD_ADR (0x274e1df2UL)
+#define RAC_NMB_RD_ADR_ADR (0xf2e063d0UL)
+#define RAC_NMB_RD_ADR_RES (0x829c7f2eUL)
+#define RAC_NMB_STATUS (0x2070b64UL)
+#define RAC_NMB_STATUS_BUS_TIMEOUT (0x7b220848UL)
+#define RAC_NMB_STATUS_NMB_READY (0xe67a182bUL)
+#define RAC_NMB_WR_ADR (0x9823ee63UL)
+#define RAC_NMB_WR_ADR_ADR (0xcb13936fUL)
+#define RAC_NMB_WR_ADR_RES (0xbb6f8f91UL)
+#define RAC_RAB_BUF_FREE (0x60f7f2d8UL)
+#define RAC_RAB_BUF_FREE_IB_FREE (0x4ddd870fUL)
+#define RAC_RAB_BUF_FREE_IB_OVF (0x92388832UL)
+#define RAC_RAB_BUF_FREE_OB_FREE (0x2e0db235UL)
+#define RAC_RAB_BUF_FREE_OB_OVF (0x44616b2fUL)
+#define RAC_RAB_BUF_FREE_TIMEOUT (0x1d0ae34eUL)
+#define RAC_RAB_BUF_USED (0x549e5008UL)
+#define RAC_RAB_BUF_USED_FLUSH (0xeb99f9baUL)
+#define RAC_RAB_BUF_USED_IB_USED (0xd4c7d150UL)
+#define RAC_RAB_BUF_USED_OB_USED (0xb717e46aUL)
+#define RAC_RAB_DMA_IB_HI (0x3adf4e92UL)
+#define RAC_RAB_DMA_IB_HI_PHYADDR (0x482070e9UL)
+#define RAC_RAB_DMA_IB_LO (0xb7d02ea3UL)
+#define RAC_RAB_DMA_IB_LO_PHYADDR (0x32d1a919UL)
+#define RAC_RAB_DMA_IB_RD (0xf443c8f4UL)
+#define RAC_RAB_DMA_IB_RD_PTR (0xa19bede2UL)
+#define RAC_RAB_DMA_IB_WR (0x7de089e0UL)
+#define RAC_RAB_DMA_IB_WR_PTR (0x1ef61e73UL)
+#define RAC_RAB_DMA_OB_HI (0xb59fbb32UL)
+#define RAC_RAB_DMA_OB_HI_PHYADDR (0xe8c5af34UL)
+#define RAC_RAB_DMA_OB_LO (0x3890db03UL)
+#define RAC_RAB_DMA_OB_LO_PHYADDR (0x923476c4UL)
+#define RAC_RAB_DMA_OB_WR (0xf2a07c40UL)
+#define RAC_RAB_DMA_OB_WR_PTR (0x6dec67f9UL)
+#define RAC_RAB_IB_DATA (0xea524b52UL)
+#define RAC_RAB_IB_DATA_D (0x52ecd3c6UL)
+#define RAC_RAB_INIT (0x47d5556eUL)
+#define RAC_RAB_INIT_RAB (0xda582a35UL)
+#define RAC_RAB_OB_DATA (0x89827e68UL)
+#define RAC_RAB_OB_DATA_D (0x21f6aa4cUL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_RAC_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rfd.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rfd.h
new file mode 100644
index 0000000000..5e5a7e96d1
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rfd.h
@@ -0,0 +1,37 @@
+/*
+ * nthw_fpga_reg_defs_rfd.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_RFD_
+#define _NTHW_FPGA_REG_DEFS_RFD_
+
+/* RFD */
+#define NTHW_MOD_RFD (0x7fa60826UL)
+#define RFD_CTRL (0x5347930aUL)
+#define RFD_CTRL_CFP (0x38fb2beUL)
+#define RFD_CTRL_ISL (0x2dac8d33UL)
+#define RFD_CTRL_PWMCW (0xebb075fcUL)
+#define RFD_MAX_FRAME_SIZE (0x8369a9a2UL)
+#define RFD_MAX_FRAME_SIZE_MAX (0x647c0b15UL)
+#define RFD_TNL_VLAN (0xb85aa35fUL)
+#define RFD_TNL_VLAN_TPID0 (0xe2dfb0a4UL)
+#define RFD_TNL_VLAN_TPID1 (0x95d88032UL)
+#define RFD_VLAN (0xa954e6d1UL)
+#define RFD_VLAN_TPID0 (0xab4dac41UL)
+#define RFD_VLAN_TPID1 (0xdc4a9cd7UL)
+#define RFD_VXLAN (0xe2207aeaUL)
+#define RFD_VXLAN_DP0 (0xb17ca4d9UL)
+#define RFD_VXLAN_DP1 (0xc67b944fUL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_RFD_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rmc.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rmc.h
new file mode 100644
index 0000000000..7857314251
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rmc.h
@@ -0,0 +1,35 @@
+/*
+ * nthw_fpga_reg_defs_rmc.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_RMC_
+#define _NTHW_FPGA_REG_DEFS_RMC_
+
+/* RMC */
+#define NTHW_MOD_RMC (0x236444eUL)
+#define RMC_CTRL (0x4c45f748UL)
+#define RMC_CTRL_BLOCK_KEEPA (0x5e036c8UL)
+#define RMC_CTRL_BLOCK_MAC_PORT (0x582a6486UL)
+#define RMC_CTRL_BLOCK_RPP_SLICE (0x58c719cUL)
+#define RMC_CTRL_BLOCK_STATT (0xb36d5342UL)
+#define RMC_CTRL_LAG_PHY_ODD_EVEN (0xf4613c9UL)
+#define RMC_DBG (0x578721f2UL)
+#define RMC_DBG_MERGE (0xebfd6f00UL)
+#define RMC_MAC_IF (0x806bb8b0UL)
+#define RMC_MAC_IF_ERR (0xa79e974aUL)
+#define RMC_STATUS (0x3c415d75UL)
+#define RMC_STATUS_DESCR_FIFO_OF (0x7be968baUL)
+#define RMC_STATUS_SF_RAM_OF (0x1832173dUL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_RMC_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_roa.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_roa.h
new file mode 100644
index 0000000000..a776ac1dfb
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_roa.h
@@ -0,0 +1,67 @@
+/*
+ * nthw_fpga_reg_defs_roa.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_ROA_
+#define _NTHW_FPGA_REG_DEFS_ROA_
+
+/* ROA */
+#define NTHW_MOD_ROA (0xde0e47e0UL)
+#define ROA_CONFIG (0xff1838eeUL)
+#define ROA_CONFIG_FWD_CELLBUILDER_PCKS (0xd6e1416dUL)
+#define ROA_CONFIG_FWD_NON_NORMAL_PCKS (0xc5d32d2eUL)
+#define ROA_CONFIG_FWD_NORMAL_PCKS (0x1127f510UL)
+#define ROA_CONFIG_FWD_RECIRCULATE (0x500dc0bcUL)
+#define ROA_CONFIG_FWD_TXPORT0 (0xf5b61631UL)
+#define ROA_CONFIG_FWD_TXPORT1 (0x82b126a7UL)
+#define ROA_IGS (0xffa60f2UL)
+#define ROA_IGS_BYTE (0x4dbd049UL)
+#define ROA_IGS_BYTE_DROP (0x8da204f9UL)
+#define ROA_IGS_PKT (0x68ca2b28UL)
+#define ROA_IGS_PKT_DROP (0xac3b264eUL)
+#define ROA_LAGCFG_CTRL (0xd5c2463cUL)
+#define ROA_LAGCFG_CTRL_ADR (0xc01e7fc3UL)
+#define ROA_LAGCFG_CTRL_CNT (0xd016e612UL)
+#define ROA_LAGCFG_DATA (0x7a13c425UL)
+#define ROA_LAGCFG_DATA_TXPHY_PORT (0xf1a085aUL)
+#define ROA_RCC (0x6652f903UL)
+#define ROA_RCC_BYTE (0xd293dbbcUL)
+#define ROA_RCC_BYTE_DROP (0x739ce234UL)
+#define ROA_RCC_PKT (0xf6623688UL)
+#define ROA_RCC_PKT_DROP (0x46c69dd6UL)
+#define ROA_TUNCFG_CTRL (0x4311f47bUL)
+#define ROA_TUNCFG_CTRL_ADR (0xb37e9594UL)
+#define ROA_TUNCFG_CTRL_CNT (0xa3760c45UL)
+#define ROA_TUNCFG_DATA (0xecc07662UL)
+#define ROA_TUNCFG_DATA_PUSH_TUNNEL (0x2b684608UL)
+#define ROA_TUNCFG_DATA_RECIRCULATE (0xc0947b2fUL)
+#define ROA_TUNCFG_DATA_RECIRC_BYPASS (0xb167919dUL)
+#define ROA_TUNCFG_DATA_RECIRC_PORT (0xa69f21d7UL)
+#define ROA_TUNCFG_DATA_TUN_IPCS_PRECALC (0xf78f25e0UL)
+#define ROA_TUNCFG_DATA_TUN_IPCS_UPD (0xa524f432UL)
+#define ROA_TUNCFG_DATA_TUN_IPTL_PRECALC (0x418432d1UL)
+#define ROA_TUNCFG_DATA_TUN_IPTL_UPD (0x5947c642UL)
+#define ROA_TUNCFG_DATA_TUN_IP_TYPE (0xdcb0763UL)
+#define ROA_TUNCFG_DATA_TUN_LEN (0xf2fad7ffUL)
+#define ROA_TUNCFG_DATA_TUN_TYPE (0xad945573UL)
+#define ROA_TUNCFG_DATA_TUN_VLAN (0xd97b06fbUL)
+#define ROA_TUNCFG_DATA_TUN_VXLAN_UDP_LEN_UPD (0x9b13a7cbUL)
+#define ROA_TUNCFG_DATA_TX_LAG_IX (0x1ed24069UL)
+#define ROA_TUNHDR_CTRL (0xdaff6a2cUL)
+#define ROA_TUNHDR_CTRL_ADR (0x5b07c2f7UL)
+#define ROA_TUNHDR_CTRL_CNT (0x4b0f5b26UL)
+#define ROA_TUNHDR_DATA (0x752ee835UL)
+#define ROA_TUNHDR_DATA_TUNNEL_HDR (0xf2fed211UL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_ROA_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rpf.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rpf.h
new file mode 100644
index 0000000000..90afca44c7
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rpf.h
@@ -0,0 +1,30 @@
+/*
+ * nthw_fpga_reg_defs_rpf.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_RPF_
+#define _NTHW_FPGA_REG_DEFS_RPF_
+
+/* RPF */
+#define NTHW_MOD_RPF (0x8d30dcddUL)
+#define RPF_CONTROL (0x7a5bdb50UL)
+#define RPF_CONTROL_KEEP_ALIVE_EN (0x80be3ffcUL)
+#define RPF_CONTROL_PEN (0xb23137b8UL)
+#define RPF_CONTROL_RPP_EN (0xdb51f109UL)
+#define RPF_CONTROL_ST_TGL_EN (0x45a6ecfaUL)
+#define RPF_TS_SORT_PRG (0xff1d137eUL)
+#define RPF_TS_SORT_PRG_MATURING_DELAY (0x2a38e127UL)
+#define RPF_TS_SORT_PRG_TS_AT_EOF (0x9f27d433UL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_RPF_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rpl.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rpl.h
new file mode 100644
index 0000000000..5346bc673d
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rpl.h
@@ -0,0 +1,42 @@
+/*
+ * nthw_fpga_reg_defs_rpl.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_RPL_
+#define _NTHW_FPGA_REG_DEFS_RPL_
+
+/* RPL */
+#define NTHW_MOD_RPL (0x6de535c3UL)
+#define RPL_EXT_CTRL (0x4c47804fUL)
+#define RPL_EXT_CTRL_ADR (0xe391ddadUL)
+#define RPL_EXT_CTRL_CNT (0xf399447cUL)
+#define RPL_EXT_DATA (0xe3960256UL)
+#define RPL_EXT_DATA_RPL_PTR (0xa8e4d0d9UL)
+#define RPL_RCP_CTRL (0xc471325fUL)
+#define RPL_RCP_CTRL_ADR (0x1f2d3a2bUL)
+#define RPL_RCP_CTRL_CNT (0xf25a3faUL)
+#define RPL_RCP_DATA (0x6ba0b046UL)
+#define RPL_RCP_DATA_DYN (0xe361554fUL)
+#define RPL_RCP_DATA_ETH_TYPE_WR (0xfc7f05c1UL)
+#define RPL_RCP_DATA_EXT_PRIO (0xcd2ae9d1UL)
+#define RPL_RCP_DATA_LEN (0xb0559aaUL)
+#define RPL_RCP_DATA_OFS (0x4168d8e9UL)
+#define RPL_RCP_DATA_RPL_PTR (0x3000a098UL)
+#define RPL_RPL_CTRL (0xe65376ecUL)
+#define RPL_RPL_CTRL_ADR (0x15abf987UL)
+#define RPL_RPL_CTRL_CNT (0x5a36056UL)
+#define RPL_RPL_DATA (0x4982f4f5UL)
+#define RPL_RPL_DATA_VALUE (0x60951eb4UL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_RPL_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rpp_lr.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rpp_lr.h
new file mode 100644
index 0000000000..c8a6efb2b6
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rpp_lr.h
@@ -0,0 +1,36 @@
+/*
+ * nthw_fpga_reg_defs_rpp_lr.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_RPP_LR_
+#define _NTHW_FPGA_REG_DEFS_RPP_LR_
+
+/* RPP_LR */
+#define NTHW_MOD_RPP_LR (0xba7f945cUL)
+#define RPP_LR_IFR_RCP_CTRL (0xce88594UL)
+#define RPP_LR_IFR_RCP_CTRL_ADR (0x4b4cc068UL)
+#define RPP_LR_IFR_RCP_CTRL_CNT (0x5b4459b9UL)
+#define RPP_LR_IFR_RCP_DATA (0xa339078dUL)
+#define RPP_LR_IFR_RCP_DATA_IPV4_DF_DROP (0xee1d681fUL)
+#define RPP_LR_IFR_RCP_DATA_IPV4_EN (0xfe386131UL)
+#define RPP_LR_IFR_RCP_DATA_IPV6_DROP (0x41f324ffUL)
+#define RPP_LR_IFR_RCP_DATA_IPV6_EN (0x5431a9baUL)
+#define RPP_LR_IFR_RCP_DATA_MTU (0x871a2322UL)
+#define RPP_LR_RCP_CTRL (0xf3395d47UL)
+#define RPP_LR_RCP_CTRL_ADR (0x4916a944UL)
+#define RPP_LR_RCP_CTRL_CNT (0x591e3095UL)
+#define RPP_LR_RCP_DATA (0x5ce8df5eUL)
+#define RPP_LR_RCP_DATA_EXP (0x578ca035UL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_RPP_LR_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rst9563.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rst9563.h
new file mode 100644
index 0000000000..0a1fecd649
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rst9563.h
@@ -0,0 +1,59 @@
+/*
+ * nthw_fpga_reg_defs_rst9563.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_RST9563_
+#define _NTHW_FPGA_REG_DEFS_RST9563_
+
+/* RST9563 */
+#define NTHW_MOD_RST9563 (0x385d6d1dUL)
+#define RST9563_CTRL (0x8fe7585fUL)
+#define RST9563_CTRL_PTP_MMCM_CLKSEL (0xf441b405UL)
+#define RST9563_CTRL_TS_CLKSEL (0x210e9a78UL)
+#define RST9563_CTRL_TS_CLKSEL_OVERRIDE (0x304bbf3UL)
+#define RST9563_POWER (0xdb6d3006UL)
+#define RST9563_POWER_PU_NSEB (0x68a55de6UL)
+#define RST9563_POWER_PU_PHY (0xdc0b7719UL)
+#define RST9563_RST (0x366a2a03UL)
+#define RST9563_RST_CORE_MMCM (0x4055af70UL)
+#define RST9563_RST_DDR4 (0x367cad64UL)
+#define RST9563_RST_MAC_RX (0x46da79e6UL)
+#define RST9563_RST_PERIPH (0xd39d53bdUL)
+#define RST9563_RST_PHY (0x50c57f90UL)
+#define RST9563_RST_PTP (0xcf6e9a69UL)
+#define RST9563_RST_PTP_MMCM (0xf69029c8UL)
+#define RST9563_RST_RPP (0xa8868b03UL)
+#define RST9563_RST_SDC (0x35477bfUL)
+#define RST9563_RST_SYS (0xe18f0bc7UL)
+#define RST9563_RST_SYS_MMCM (0x9f5c3d45UL)
+#define RST9563_RST_TMC (0xd7d9da73UL)
+#define RST9563_RST_TS (0x216dd0e7UL)
+#define RST9563_RST_TSM_REF_MMCM (0x664f1a24UL)
+#define RST9563_RST_TS_MMCM (0xce54ff59UL)
+#define RST9563_STAT (0xad7dd604UL)
+#define RST9563_STAT_CORE_MMCM_LOCKED (0xfd6d0a5aUL)
+#define RST9563_STAT_DDR4_MMCM_LOCKED (0xb902f1d0UL)
+#define RST9563_STAT_DDR4_PLL_LOCKED (0xe8a6d1b9UL)
+#define RST9563_STAT_PTP_MMCM_LOCKED (0x4e4fd2a9UL)
+#define RST9563_STAT_SYS_MMCM_LOCKED (0x5502a445UL)
+#define RST9563_STAT_TS_MMCM_LOCKED (0xe6405b02UL)
+#define RST9563_STICKY (0x97e2efe3UL)
+#define RST9563_STICKY_CORE_MMCM_UNLOCKED (0xac340bb6UL)
+#define RST9563_STICKY_DDR4_MMCM_UNLOCKED (0x4737148cUL)
+#define RST9563_STICKY_DDR4_PLL_UNLOCKED (0xf9857d1bUL)
+#define RST9563_STICKY_PTP_MMCM_UNLOCKED (0x2a4e9819UL)
+#define RST9563_STICKY_SYS_MMCM_UNLOCKED (0x61e3ebbdUL)
+#define RST9563_STICKY_TS_MMCM_UNLOCKED (0x7e9f941eUL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_RST9563_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_sdc.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_sdc.h
new file mode 100644
index 0000000000..ed3a25ebfa
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_sdc.h
@@ -0,0 +1,44 @@
+/*
+ * nthw_fpga_reg_defs_sdc.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_SDC_
+#define _NTHW_FPGA_REG_DEFS_SDC_
+
+/* SDC */
+#define NTHW_MOD_SDC (0xd2369530UL)
+#define SDC_CELL_CNT (0xc6d82110UL)
+#define SDC_CELL_CNT_CELL_CNT (0xdd4de629UL)
+#define SDC_CELL_CNT_PERIOD (0x8dfef1d4UL)
+#define SDC_CELL_CNT_PERIOD_CELL_CNT_PERIOD (0x2b5819c1UL)
+#define SDC_CTRL (0x1577b205UL)
+#define SDC_CTRL_INIT (0x70e62104UL)
+#define SDC_CTRL_RESET_POINTERS (0xec1c0f9cUL)
+#define SDC_CTRL_RUN_TEST (0x2efbe98eUL)
+#define SDC_CTRL_STOP_CLIENT (0xb11ebe2dUL)
+#define SDC_CTRL_TEST_EN (0xaa1fa4UL)
+#define SDC_FILL_LVL (0xd3b30232UL)
+#define SDC_FILL_LVL_FILL_LVL (0xc97281acUL)
+#define SDC_MAX_FILL_LVL (0x326de743UL)
+#define SDC_MAX_FILL_LVL_MAX_FILL_LVL (0x915fbf73UL)
+#define SDC_STAT (0x37ed3c5eUL)
+#define SDC_STAT_CALIB (0x27122e80UL)
+#define SDC_STAT_CELL_CNT_STOPPED (0x517d5cafUL)
+#define SDC_STAT_ERR_FOUND (0x3bb6bd0UL)
+#define SDC_STAT_INIT_DONE (0x1dc2e095UL)
+#define SDC_STAT_MMCM_LOCK (0xd9aac1c2UL)
+#define SDC_STAT_PLL_LOCK (0x3bcab6ebUL)
+#define SDC_STAT_RESETTING (0xa85349c1UL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_SDC_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_slc.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_slc.h
new file mode 100644
index 0000000000..da257a9425
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_slc.h
@@ -0,0 +1,33 @@
+/*
+ * nthw_fpga_reg_defs_slc.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_SLC_
+#define _NTHW_FPGA_REG_DEFS_SLC_
+
+/* SLC */
+#define NTHW_MOD_SLC (0x1aef1f38UL)
+#define SLC_RCP_CTRL (0xa3373b1UL)
+#define SLC_RCP_CTRL_ADR (0xe64629e7UL)
+#define SLC_RCP_CTRL_CNT (0xf64eb036UL)
+#define SLC_RCP_DATA (0xa5e2f1a8UL)
+#define SLC_RCP_DATA_HEAD_DYN (0x86b55a78UL)
+#define SLC_RCP_DATA_HEAD_OFS (0x24bcd7deUL)
+#define SLC_RCP_DATA_HEAD_SLC_EN (0x61cf5ef7UL)
+#define SLC_RCP_DATA_PCAP (0x84909c04UL)
+#define SLC_RCP_DATA_TAIL_DYN (0x85cd93a3UL)
+#define SLC_RCP_DATA_TAIL_OFS (0x27c41e05UL)
+#define SLC_RCP_DATA_TAIL_SLC_EN (0xa4f5112cUL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_SLC_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_slc_lr.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_slc_lr.h
new file mode 100644
index 0000000000..6d1cf03bd8
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_slc_lr.h
@@ -0,0 +1,22 @@
+/*
+ * nthw_fpga_reg_defs_slc_lr.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_SLC_LR_
+#define _NTHW_FPGA_REG_DEFS_SLC_LR_
+
+/* SLC_LR */
+#define NTHW_MOD_SLC_LR (0x969fc50bUL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_SLC_LR_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_spim.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_spim.h
new file mode 100644
index 0000000000..1e9eebd59a
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_spim.h
@@ -0,0 +1,75 @@
+/*
+ * nthw_fpga_reg_defs_spim.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_SPIM_
+#define _NTHW_FPGA_REG_DEFS_SPIM_
+
+/* SPIM */
+#define NTHW_MOD_SPIM (0x1da437bfUL)
+#define SPIM_CFG (0x90b6b0d5UL)
+#define SPIM_CFG_PRE (0x156a8ea9UL)
+#define SPIM_CFG_CLK (0xeb7046a1UL)
+#define SPIM_CFG_CLK_MODE (0x228be0cbUL)
+#define SPIM_CMD (0xea4b38a4UL)
+#define SPIM_CMD_ADDR (0x95fe56baUL)
+#define SPIM_CMD_CMD (0x9c30279bUL)
+#define SPIM_CMD_DATA (0x6a9737ecUL)
+#define SPIM_CONF0 (0x84d4acb5UL)
+#define SPIM_CONF0_BYTE_PACE (0xc9a95016UL)
+#define SPIM_CONF0_MIRROR_EN (0xa710688UL)
+#define SPIM_CONF0_MSB_FIRST (0x5f60c96aUL)
+#define SPIM_CONF0_PRESCAL_CLK (0xadb38a7UL)
+#define SPIM_CONF0_RESTART (0x1fda85dcUL)
+#define SPIM_CONF0_RST (0x64e3b3bUL)
+#define SPIM_CONF0_SYNC_MON_EN (0x591a639eUL)
+#define SPIM_CONF1 (0xf3d39c23UL)
+#define SPIM_CONF1_MIRROR_PACE (0x370f3f34UL)
+#define SPIM_CONF1_MIRROR_SCAN (0x83daffbeUL)
+#define SPIM_CONF1_SYNCTIMEOUT (0x1b5d30cdUL)
+#define SPIM_CONF2 (0x6adacd99UL)
+#define SPIM_CONF2_MIRROR_PRESC (0x3a8c10e2UL)
+#define SPIM_CONF2_OPCODE_RD (0x3eb6084fUL)
+#define SPIM_CONF2_OPCODE_WR (0xb715495bUL)
+#define SPIM_CONF3 (0x1dddfd0fUL)
+#define SPIM_CONF3_MIRROR_RDADR (0xc00ba60fUL)
+#define SPIM_CONF3_MIRROR_WRADR (0x7d99213cUL)
+#define SPIM_CR (0x1c1de013UL)
+#define SPIM_CR_EN (0xf2e0e72fUL)
+#define SPIM_CR_LOOP (0xdeb882aUL)
+#define SPIM_CR_RXRST (0x487f7d1bUL)
+#define SPIM_CR_TXRST (0xc73f88bbUL)
+#define SPIM_DRR (0xd68a95eeUL)
+#define SPIM_DRR_DRR (0x78766633UL)
+#define SPIM_DTR (0x80d03268UL)
+#define SPIM_DTR_DTR (0xf87522a8UL)
+#define SPIM_REPLY (0x6ed04defUL)
+#define SPIM_REPLY_RDDATA (0x40db3b24UL)
+#define SPIM_SR (0x56dff242UL)
+#define SPIM_SR_DONE (0xdb47e9a1UL)
+#define SPIM_SR_RXEMPTY (0x489aaf91UL)
+#define SPIM_SR_RXFULL (0xd26832f5UL)
+#define SPIM_SR_RXLVL (0x4c67ae59UL)
+#define SPIM_SR_TXEMPTY (0x2b4a9aabUL)
+#define SPIM_SR_TXFULL (0x431d1e8UL)
+#define SPIM_SR_TXLVL (0xc3275bf9UL)
+#define SPIM_SRR (0xcfe3201bUL)
+#define SPIM_SRR_RST (0x32dc8fc5UL)
+#define SPIM_STATUS (0xd04220ceUL)
+#define SPIM_STATUS_CMDPENDING (0x74ed833fUL)
+#define SPIM_STATUS_RESERVED (0xa50278bUL)
+#define SPIM_STATUS_RESYNCDETECT (0x5b268881UL)
+#define SPIM_STATUS_RESYNCING (0x5ec3f11UL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_SPIM_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_spis.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_spis.h
new file mode 100644
index 0000000000..30ff3a624e
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_spis.h
@@ -0,0 +1,50 @@
+/*
+ * nthw_fpga_reg_defs_spis.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_SPIS_
+#define _NTHW_FPGA_REG_DEFS_SPIS_
+
+/* SPIS */
+#define NTHW_MOD_SPIS (0xe7ab0adcUL)
+#define SPIS_CR (0xacdbc0bfUL)
+#define SPIS_CR_DEBUG (0xf2096408UL)
+#define SPIS_CR_EN (0xc50100bcUL)
+#define SPIS_CR_LOOP (0x69e911c9UL)
+#define SPIS_CR_RXRST (0x7118cc40UL)
+#define SPIS_CR_TXRST (0xfe5839e0UL)
+#define SPIS_DRR (0x95abc0dUL)
+#define SPIS_DRR_DRR (0x1c74ffd0UL)
+#define SPIS_DTR (0x5f001b8bUL)
+#define SPIS_DTR_DTR (0x9c77bb4bUL)
+#define SPIS_RAM_CTRL (0x682dc7d8UL)
+#define SPIS_RAM_CTRL_ADR (0x15c2f809UL)
+#define SPIS_RAM_CTRL_CNT (0x5ca61d8UL)
+#define SPIS_RAM_DATA (0xc7fc45c1UL)
+#define SPIS_RAM_DATA_DATA (0x422b05eaUL)
+#define SPIS_SR (0xe619d2eeUL)
+#define SPIS_SR_DONE (0xbf457042UL)
+#define SPIS_SR_FRAME_ERR (0x31b5d7e4UL)
+#define SPIS_SR_READ_ERR (0xa83d91f1UL)
+#define SPIS_SR_RXEMPTY (0xadb39173UL)
+#define SPIS_SR_RXFULL (0x2ee8dd38UL)
+#define SPIS_SR_RXLVL (0x75001f02UL)
+#define SPIS_SR_TXEMPTY (0xce63a449UL)
+#define SPIS_SR_TXFULL (0xf8b13e25UL)
+#define SPIS_SR_TXLVL (0xfa40eaa2UL)
+#define SPIS_SR_WRITE_ERR (0x9d389ce2UL)
+#define SPIS_SRR (0x103309f8UL)
+#define SPIS_SRR_RST (0x56de1626UL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_SPIS_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_sta.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_sta.h
new file mode 100644
index 0000000000..a028ece8d8
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_sta.h
@@ -0,0 +1,59 @@
+/*
+ * nthw_fpga_reg_defs_sta.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_STA_
+#define _NTHW_FPGA_REG_DEFS_STA_
+
+/* STA */
+#define NTHW_MOD_STA (0x76fae64dUL)
+#define STA_BYTE (0xa08364d4UL)
+#define STA_BYTE_CNT (0x3119e6bcUL)
+#define STA_CFG (0xcecaf9f4UL)
+#define STA_CFG_CNT_CLEAR (0xc325e12eUL)
+#define STA_CFG_CNT_FRZ (0x8c27a596UL)
+#define STA_CFG_DMA_ENA (0x940dbacUL)
+#define STA_CFG_TX_DISABLE (0x30f43250UL)
+#define STA_CV_ERR (0x7db7db5dUL)
+#define STA_CV_ERR_CNT (0x2c02fbbeUL)
+#define STA_FCS_ERR (0xa0de1647UL)
+#define STA_FCS_ERR_CNT (0xc68c37d1UL)
+#define STA_HOST_ADR_LSB (0xde569336UL)
+#define STA_HOST_ADR_LSB_LSB (0xb6f2f94bUL)
+#define STA_HOST_ADR_MSB (0xdf94f901UL)
+#define STA_HOST_ADR_MSB_MSB (0x114798c8UL)
+#define STA_LOAD_BIN (0x2e842591UL)
+#define STA_LOAD_BIN_BIN (0x1a2b942eUL)
+#define STA_LOAD_BPS_RX_0 (0xbf8f4595UL)
+#define STA_LOAD_BPS_RX_0_BPS (0x41647781UL)
+#define STA_LOAD_BPS_RX_1 (0xc8887503UL)
+#define STA_LOAD_BPS_RX_1_BPS (0x7c045e31UL)
+#define STA_LOAD_BPS_TX_0 (0x9ae41a49UL)
+#define STA_LOAD_BPS_TX_0_BPS (0x870b7e06UL)
+#define STA_LOAD_BPS_TX_1 (0xede32adfUL)
+#define STA_LOAD_BPS_TX_1_BPS (0xba6b57b6UL)
+#define STA_LOAD_PPS_RX_0 (0x811173c3UL)
+#define STA_LOAD_PPS_RX_0_PPS (0xbee573fcUL)
+#define STA_LOAD_PPS_RX_1 (0xf6164355UL)
+#define STA_LOAD_PPS_RX_1_PPS (0x83855a4cUL)
+#define STA_LOAD_PPS_TX_0 (0xa47a2c1fUL)
+#define STA_LOAD_PPS_TX_0_PPS (0x788a7a7bUL)
+#define STA_LOAD_PPS_TX_1 (0xd37d1c89UL)
+#define STA_LOAD_PPS_TX_1_PPS (0x45ea53cbUL)
+#define STA_PCKT (0xecc8f30aUL)
+#define STA_PCKT_CNT (0x63291d16UL)
+#define STA_STATUS (0x91c5c51cUL)
+#define STA_STATUS_STAT_TOGGLE_MISSED (0xf7242b11UL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_STA_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tempmon.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tempmon.h
new file mode 100644
index 0000000000..5c5190bb4f
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tempmon.h
@@ -0,0 +1,29 @@
+/*
+ * nthw_fpga_reg_defs_tempmon.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_TEMPMON_
+#define _NTHW_FPGA_REG_DEFS_TEMPMON_
+
+/* TEMPMON */
+#define NTHW_MOD_TEMPMON (0x2f77020dUL)
+#define TEMPMON_ALARMS (0x3f7046c2UL)
+#define TEMPMON_ALARMS_OT (0xb278af71UL)
+#define TEMPMON_ALARMS_OT_OVERWR (0x6e4d38d3UL)
+#define TEMPMON_ALARMS_OT_OVERWRVAL (0x9145f23eUL)
+#define TEMPMON_ALARMS_TEMP (0x85d42f2cUL)
+#define TEMPMON_STAT (0x9e81e173UL)
+#define TEMPMON_STAT_TEMP (0x7bd5bb7bUL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_TEMPMON_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tint.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tint.h
new file mode 100644
index 0000000000..9ffcec3bf6
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tint.h
@@ -0,0 +1,27 @@
+/*
+ * nthw_fpga_reg_defs_tint.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_TINT_
+#define _NTHW_FPGA_REG_DEFS_TINT_
+
+/* TINT */
+#define NTHW_MOD_TINT (0xb8aea9feUL)
+#define TINT_CTRL (0x95bdc9c3UL)
+#define TINT_CTRL_INTERVAL (0xfe472b70UL)
+#define TINT_STATUS (0x2557d8a6UL)
+#define TINT_STATUS_DELAYED (0xabd2ff4cUL)
+#define TINT_STATUS_SKIPPED (0x1c35b879UL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_TINT_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tsm.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tsm.h
new file mode 100644
index 0000000000..1eb7939d3a
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tsm.h
@@ -0,0 +1,294 @@
+/*
+ * nthw_fpga_reg_defs_tsm.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_TSM_
+#define _NTHW_FPGA_REG_DEFS_TSM_
+
+/* TSM */
+#define NTHW_MOD_TSM (0x35422a24UL)
+#define TSM_ADJ_FINE_N (0x5ee7eb67UL)
+#define TSM_ADJ_FINE_N_2DY (0x5e4ebc9dUL)
+#define TSM_ADJ_FINE_N_2DY2DX (0x5d41df5UL)
+#define TSM_ADJ_FINE_P (0xa4e8d604UL)
+#define TSM_ADJ_FINE_P_2DY (0x819e957eUL)
+#define TSM_ADJ_FINE_P_2DY2DX (0x6ce53eecUL)
+#define TSM_ADJ_LIMIT_HI (0x735c7b90UL)
+#define TSM_ADJ_LIMIT_HI_LIMIT (0x868cb9a6UL)
+#define TSM_ADJ_LIMIT_LO (0xfe531ba1UL)
+#define TSM_ADJ_LIMIT_LO_LIMIT (0x61168266UL)
+#define TSM_BASIC_2DY (0x70dd9159UL)
+#define TSM_BASIC_2DY_2DY (0xeea30d3fUL)
+#define TSM_BASIC_2DY2DX (0xda5ebb56UL)
+#define TSM_BASIC_2DY2DX_2DY2DX (0x78a2f0edUL)
+#define TSM_CON0_CONFIG (0xf893d371UL)
+#define TSM_CON0_CONFIG_BLIND (0x59ccfcbUL)
+#define TSM_CON0_CONFIG_DC_SRC (0x1879812bUL)
+#define TSM_CON0_CONFIG_PORT (0x3ff0bb08UL)
+#define TSM_CON0_CONFIG_PPSIN_2_5V (0xb8e78227UL)
+#define TSM_CON0_CONFIG_SAMPLE_EDGE (0x4a4022ebUL)
+#define TSM_CON0_INTERFACE (0x76e93b59UL)
+#define TSM_CON0_INTERFACE_EX_TERM (0xd079b416UL)
+#define TSM_CON0_INTERFACE_IN_REF_PWM (0x16f73c33UL)
+#define TSM_CON0_INTERFACE_PWM_ENA (0x3629e73fUL)
+#define TSM_CON0_INTERFACE_RESERVED (0xf9c5066UL)
+#define TSM_CON0_INTERFACE_VTERM_PWM (0x6d2b1e23UL)
+#define TSM_CON0_SAMPLE_HI (0x6e536b8UL)
+#define TSM_CON0_SAMPLE_HI_SEC (0x5fc26159UL)
+#define TSM_CON0_SAMPLE_LO (0x8bea5689UL)
+#define TSM_CON0_SAMPLE_LO_NS (0x13d0010dUL)
+#define TSM_CON1_CONFIG (0x3439d3efUL)
+#define TSM_CON1_CONFIG_BLIND (0x98932ebdUL)
+#define TSM_CON1_CONFIG_DC_SRC (0xa1825ac3UL)
+#define TSM_CON1_CONFIG_PORT (0xe266628dUL)
+#define TSM_CON1_CONFIG_PPSIN_2_5V (0x6f05027fUL)
+#define TSM_CON1_CONFIG_SAMPLE_EDGE (0x2f2719adUL)
+#define TSM_CON1_SAMPLE_HI (0xc76be978UL)
+#define TSM_CON1_SAMPLE_HI_SEC (0xe639bab1UL)
+#define TSM_CON1_SAMPLE_LO (0x4a648949UL)
+#define TSM_CON1_SAMPLE_LO_NS (0x8edfe07bUL)
+#define TSM_CON2_CONFIG (0xbab6d40cUL)
+#define TSM_CON2_CONFIG_BLIND (0xe4f20b66UL)
+#define TSM_CON2_CONFIG_DC_SRC (0xb0ff30baUL)
+#define TSM_CON2_CONFIG_PORT (0x5fac0e43UL)
+#define TSM_CON2_CONFIG_PPSIN_2_5V (0xcc5384d6UL)
+#define TSM_CON2_CONFIG_SAMPLE_EDGE (0x808e5467UL)
+#define TSM_CON2_SAMPLE_HI (0x5e898f79UL)
+#define TSM_CON2_SAMPLE_HI_SEC (0xf744d0c8UL)
+#define TSM_CON2_SAMPLE_LO (0xd386ef48UL)
+#define TSM_CON2_SAMPLE_LO_NS (0xf2bec5a0UL)
+#define TSM_CON3_CONFIG (0x761cd492UL)
+#define TSM_CON3_CONFIG_BLIND (0x79fdea10UL)
+#define TSM_CON3_CONFIG_PORT (0x823ad7c6UL)
+#define TSM_CON3_CONFIG_SAMPLE_EDGE (0xe5e96f21UL)
+#define TSM_CON3_SAMPLE_HI (0x9f0750b9UL)
+#define TSM_CON3_SAMPLE_HI_SEC (0x4ebf0b20UL)
+#define TSM_CON3_SAMPLE_LO (0x12083088UL)
+#define TSM_CON3_SAMPLE_LO_NS (0x6fb124d6UL)
+#define TSM_CON4_CONFIG (0x7cd9dd8bUL)
+#define TSM_CON4_CONFIG_BLIND (0x1c3040d0UL)
+#define TSM_CON4_CONFIG_PORT (0xff49d19eUL)
+#define TSM_CON4_CONFIG_SAMPLE_EDGE (0x4adc9b2UL)
+#define TSM_CON4_SAMPLE_HI (0xb63c453aUL)
+#define TSM_CON4_SAMPLE_HI_SEC (0xd5be043aUL)
+#define TSM_CON4_SAMPLE_LO (0x3b33250bUL)
+#define TSM_CON4_SAMPLE_LO_NS (0xa7c8e16UL)
+#define TSM_CON5_CONFIG (0xb073dd15UL)
+#define TSM_CON5_CONFIG_BLIND (0x813fa1a6UL)
+#define TSM_CON5_CONFIG_PORT (0x22df081bUL)
+#define TSM_CON5_CONFIG_SAMPLE_EDGE (0x61caf2f4UL)
+#define TSM_CON5_SAMPLE_HI (0x77b29afaUL)
+#define TSM_CON5_SAMPLE_HI_SEC (0x6c45dfd2UL)
+#define TSM_CON5_SAMPLE_LO (0xfabdfacbUL)
+#define TSM_CON5_SAMPLE_LO_TIME (0x945d87e8UL)
+#define TSM_CON6_CONFIG (0x3efcdaf6UL)
+#define TSM_CON6_CONFIG_BLIND (0xfd5e847dUL)
+#define TSM_CON6_CONFIG_PORT (0x9f1564d5UL)
+#define TSM_CON6_CONFIG_SAMPLE_EDGE (0xce63bf3eUL)
+#define TSM_CON6_SAMPLE_HI (0xee50fcfbUL)
+#define TSM_CON6_SAMPLE_HI_SEC (0x7d38b5abUL)
+#define TSM_CON6_SAMPLE_LO (0x635f9ccaUL)
+#define TSM_CON6_SAMPLE_LO_NS (0xeb124abbUL)
+#define TSM_CON7_HOST_SAMPLE_HI (0xdcd90e52UL)
+#define TSM_CON7_HOST_SAMPLE_HI_SEC (0xd98d3618UL)
+#define TSM_CON7_HOST_SAMPLE_LO (0x51d66e63UL)
+#define TSM_CON7_HOST_SAMPLE_LO_NS (0x8f5594ddUL)
+#define TSM_CONFIG (0xef5dec83UL)
+#define TSM_CONFIG_NTTS_SRC (0x1b60227bUL)
+#define TSM_CONFIG_NTTS_SYNC (0x43e0a69dUL)
+#define TSM_CONFIG_TIMESET_EDGE (0x8c381127UL)
+#define TSM_CONFIG_TIMESET_SRC (0xe7590a31UL)
+#define TSM_CONFIG_TIMESET_UP (0x561980c1UL)
+#define TSM_CONFIG_TS_FORMAT (0xe6efc2faUL)
+#define TSM_CTRL (0x87c1782cUL)
+#define TSM_CTRL_DCEN_CON0 (0x50b3db87UL)
+#define TSM_CTRL_DCEN_CON1 (0x27b4eb11UL)
+#define TSM_CTRL_DCEN_CON2 (0xbebdbaabUL)
+#define TSM_CTRL_FORMAT (0xd6f91ae8UL)
+#define TSM_CTRL_HIGH_SAMPLE (0x6d4509b1UL)
+#define TSM_CTRL_LED_CON0 (0x225af447UL)
+#define TSM_CTRL_LED_CON1 (0x555dc4d1UL)
+#define TSM_CTRL_LED_CON2 (0xcc54956bUL)
+#define TSM_CTRL_MASTER_STAT (0x6a0e3d17UL)
+#define TSM_CTRL_OEN_CON0 (0xd4ed0c2UL)
+#define TSM_CTRL_OEN_CON1 (0x7a49e054UL)
+#define TSM_CTRL_OEN_CON2 (0xe340b1eeUL)
+#define TSM_CTRL_PPSEN (0x9eada897UL)
+#define TSM_CTRL_PPS_NEGEDGE (0x8390d486UL)
+#define TSM_CTRL_PPS_TIME_UP (0x78161775UL)
+#define TSM_CTRL_PTP_TIME_UP (0x48708bcaUL)
+#define TSM_CTRL_RESERVED (0x3026aeb5UL)
+#define TSM_CTRL_SEL_EXTSRC (0x57855b43UL)
+#define TSM_CTRL_SYNEN (0xb0fbadeeUL)
+#define TSM_CTRL_TS_CON0 (0x7c756725UL)
+#define TSM_CTRL_TS_CON1 (0xb7257b3UL)
+#define TSM_CTRL_TS_CON2 (0x927b0609UL)
+#define TSM_EXT_STAT (0xf7c0a6cbUL)
+#define TSM_EXT_STAT_STAT (0xb32dd5d8UL)
+#define TSM_EXT_TIME_HI (0x678de1fUL)
+#define TSM_EXT_TIME_HI_TIME (0xe8159c02UL)
+#define TSM_EXT_TIME_LO (0x8b77be2eUL)
+#define TSM_EXT_TIME_LO_TIME (0xca035b0cUL)
+#define TSM_INTERFACE (0xe4ab597bUL)
+#define TSM_INTERFACE_EX_TERM (0x9e5553e6UL)
+#define TSM_INTERFACE_IN_REF_PWM (0x80d44665UL)
+#define TSM_INTERFACE_PWM_ENA (0x780500cfUL)
+#define TSM_INTERFACE_RESERVED (0xb26f8e9dUL)
+#define TSM_INTERFACE_VTERM_PWM (0x47f9c669UL)
+#define TSM_INT_CONFIG (0x9a0d52dUL)
+#define TSM_INT_CONFIG_AUTO_DISABLE (0x9581470UL)
+#define TSM_INT_CONFIG_MASK (0xf00cd3d7UL)
+#define TSM_INT_STAT (0xa4611a70UL)
+#define TSM_INT_STAT_CAUSE (0x315168cfUL)
+#define TSM_INT_STAT_ENABLE (0x980a12d1UL)
+#define TSM_INT_TIME_HI (0x26d2bd77UL)
+#define TSM_INT_TIME_HI_TIME (0x29af0477UL)
+#define TSM_INT_TIME_LO (0xabdddd46UL)
+#define TSM_INT_TIME_LO_TIME (0xbb9c379UL)
+#define TSM_LED (0x6ae05f87UL)
+#define TSM_LED_LED0_BG_COLOR (0x897cf9eeUL)
+#define TSM_LED_LED0_COLOR (0x6d7ada39UL)
+#define TSM_LED_LED0_MODE (0x6087b644UL)
+#define TSM_LED_LED0_SRC (0x4fe29639UL)
+#define TSM_LED_LED1_BG_COLOR (0x66be92d0UL)
+#define TSM_LED_LED1_COLOR (0xcb0dd18dUL)
+#define TSM_LED_LED1_MODE (0xabdb65e1UL)
+#define TSM_LED_LED1_SRC (0x7282bf89UL)
+#define TSM_LED_LED2_BG_COLOR (0x8d8929d3UL)
+#define TSM_LED_LED2_COLOR (0xfae5cb10UL)
+#define TSM_LED_LED2_MODE (0x2d4f174fUL)
+#define TSM_LED_LED2_SRC (0x3522c559UL)
+#define TSM_NTTS_CONFIG (0x8bc38bdeUL)
+#define TSM_NTTS_CONFIG_AUTO_HARDSET (0xd75be25dUL)
+#define TSM_NTTS_CONFIG_EXT_CLK_ADJ (0x700425b6UL)
+#define TSM_NTTS_CONFIG_HIGH_SAMPLE (0x37135b7eUL)
+#define TSM_NTTS_CONFIG_TS_SRC_FORMAT (0x6e6e707UL)
+#define TSM_NTTS_CTRL (0x4798367bUL)
+#define TSM_NTTS_CTRL_NTTS_CMD (0x85e132cfUL)
+#define TSM_NTTS_DATA_HI (0x6bfb0188UL)
+#define TSM_NTTS_DATA_HI_DATA (0x44315d8UL)
+#define TSM_NTTS_DATA_LO (0xe6f461b9UL)
+#define TSM_NTTS_DATA_LO_DATA (0x2655d2d6UL)
+#define TSM_NTTS_EXT_STAT (0x2b0315b7UL)
+#define TSM_NTTS_EXT_STAT_MASTER_ID (0xf263315eUL)
+#define TSM_NTTS_EXT_STAT_MASTER_REV (0xd543795eUL)
+#define TSM_NTTS_EXT_STAT_MASTER_STAT (0x92d96f5eUL)
+#define TSM_NTTS_LIMIT_HI (0x1ddaa85fUL)
+#define TSM_NTTS_LIMIT_HI_SEC (0x315c6ef2UL)
+#define TSM_NTTS_LIMIT_LO (0x90d5c86eUL)
+#define TSM_NTTS_LIMIT_LO_NS (0xe6d94d9aUL)
+#define TSM_NTTS_OFFSET (0x6436e72UL)
+#define TSM_NTTS_OFFSET_NS (0x12d43a06UL)
+#define TSM_NTTS_SAMPLE_HI (0xcdc8aa3eUL)
+#define TSM_NTTS_SAMPLE_HI_SEC (0x4f6588fdUL)
+#define TSM_NTTS_SAMPLE_LO (0x40c7ca0fUL)
+#define TSM_NTTS_SAMPLE_LO_NS (0x6e43ff97UL)
+#define TSM_NTTS_STAT (0x6502b820UL)
+#define TSM_NTTS_STAT_NTTS_VALID (0x3e184471UL)
+#define TSM_NTTS_STAT_SIGNAL_LOST (0x178bedfdUL)
+#define TSM_NTTS_STAT_SYNC_LOST (0xe4cd53dfUL)
+#define TSM_NTTS_TS_T0_HI (0x1300d1b6UL)
+#define TSM_NTTS_TS_T0_HI_TIME (0xa016ae4fUL)
+#define TSM_NTTS_TS_T0_LO (0x9e0fb187UL)
+#define TSM_NTTS_TS_T0_LO_TIME (0x82006941UL)
+#define TSM_NTTS_TS_T0_OFFSET (0xbf70ce4fUL)
+#define TSM_NTTS_TS_T0_OFFSET_COUNT (0x35dd4398UL)
+#define TSM_OFFSET_HI (0xb5b09839UL)
+#define TSM_OFFSET_HI_OFFSET (0xec7bf359UL)
+#define TSM_OFFSET_LO (0x38bff808UL)
+#define TSM_OFFSET_LO_OFFSET (0x77f8abd2UL)
+#define TSM_PB_CTRL (0x7a8b60faUL)
+#define TSM_PB_CTRL_INSTMEM_WR (0xf96e2cbcUL)
+#define TSM_PB_CTRL_RESET (0xa38ade8bUL)
+#define TSM_PB_CTRL_RST (0x3aaa82f4UL)
+#define TSM_PB_INSTMEM (0xb54aeecUL)
+#define TSM_PB_INSTMEM_ADDR (0x3549ddaaUL)
+#define TSM_PB_INSTMEM_DATA (0xca20bcfcUL)
+#define TSM_PB_INSTMEM_MEM_ADDR (0x9ac79b6eUL)
+#define TSM_PB_INSTMEM_MEM_DATA (0x65aefa38UL)
+#define TSM_PI_CTRL_I (0x8d71a4e2UL)
+#define TSM_PI_CTRL_I_VAL (0x98baedc9UL)
+#define TSM_PI_CTRL_KI (0xa1bd86cbUL)
+#define TSM_PI_CTRL_KI_GAIN (0x53faa916UL)
+#define TSM_PI_CTRL_KP (0xc5d62e0bUL)
+#define TSM_PI_CTRL_KP_GAIN (0x7723fa45UL)
+#define TSM_PI_CTRL_SHL (0xaa518701UL)
+#define TSM_PI_CTRL_SHL_VAL (0x56f56a6fUL)
+#define TSM_RSYNC_COUNT (0xa7bb7108UL)
+#define TSM_RSYNC_COUNT_COUNT (0x66e7d46UL)
+#define TSM_STAT (0xa55bf677UL)
+#define TSM_STAT_EXT_SRC_OK (0x62036046UL)
+#define TSM_STAT_HARD_SYNC (0x7fff20fdUL)
+#define TSM_STAT_INSYNC (0x29f2e4adUL)
+#define TSM_STAT_LINK_ACTIVE (0x575513d4UL)
+#define TSM_STAT_LINK_CON0 (0x216086f0UL)
+#define TSM_STAT_LINK_CON1 (0x5667b666UL)
+#define TSM_STAT_LINK_CON2 (0xcf6ee7dcUL)
+#define TSM_STAT_LINK_CON3 (0xb869d74aUL)
+#define TSM_STAT_LINK_CON4 (0x260d42e9UL)
+#define TSM_STAT_LINK_CON5 (0x510a727fUL)
+#define TSM_STAT_NTTS_INSYNC (0xb593a245UL)
+#define TSM_STAT_PTP_MI_PRESENT (0x43131eb0UL)
+#define TSM_TIMER_CTRL (0x648da051UL)
+#define TSM_TIMER_CTRL_TIMER_EN_T0 (0x17cee154UL)
+#define TSM_TIMER_CTRL_TIMER_EN_T1 (0x60c9d1c2UL)
+#define TSM_TIMER_CTRL_TRIGGER_SEL (0x79f7c3a5UL)
+#define TSM_TIMER_D_T0 (0xfae6ed98UL)
+#define TSM_TIMER_D_T0_MAX_COUNT (0xbd0df6dbUL)
+#define TSM_TIMER_T0 (0x417217a5UL)
+#define TSM_TIMER_T0_MAX_COUNT (0xaa601706UL)
+#define TSM_TIMER_T1 (0x36752733UL)
+#define TSM_TIMER_T1_MAX_COUNT (0x6beec8c6UL)
+#define TSM_TIMESTAMP_HI (0x59f35088UL)
+#define TSM_TIMESTAMP_HI_TIME (0x56f613f0UL)
+#define TSM_TIMESTAMP_LO (0xd4fc30b9UL)
+#define TSM_TIMESTAMP_LO_TIME (0x74e0d4feUL)
+#define TSM_TIME_HARDSET_HI (0xf28bdb46UL)
+#define TSM_TIME_HARDSET_HI_TIME (0x2d9a28baUL)
+#define TSM_TIME_HARDSET_LO (0x7f84bb77UL)
+#define TSM_TIME_HARDSET_LO_TIME (0xf8cefb4UL)
+#define TSM_TIME_HI (0x175acea1UL)
+#define TSM_TIME_HI_SEC (0xc0e9c9a1UL)
+#define TSM_TIME_HI_TIME (0x7febcc76UL)
+#define TSM_TIME_LO (0x9a55ae90UL)
+#define TSM_TIME_LO_NS (0x879c5c4bUL)
+#define TSM_TIME_RATE_ADJ (0xb1cc4bb1UL)
+#define TSM_TIME_RATE_ADJ_FRACTION (0xb7ab96UL)
+#define TSM_TS_HI (0xccfe9e5eUL)
+#define TSM_TS_HI_TIME (0xc23fed30UL)
+#define TSM_TS_LO (0x41f1fe6fUL)
+#define TSM_TS_LO_TIME (0xe0292a3eUL)
+#define TSM_TS_OFFSET (0x4b2e6e13UL)
+#define TSM_TS_OFFSET_NS (0x68c286b9UL)
+#define TSM_TS_STAT (0x64d41b8cUL)
+#define TSM_TS_STAT_OVERRUN (0xad9db92aUL)
+#define TSM_TS_STAT_SAMPLES (0xb6350e0bUL)
+#define TSM_TS_STAT_HI_OFFSET (0x1aa2ddf2UL)
+#define TSM_TS_STAT_HI_OFFSET_NS (0xeb040e0fUL)
+#define TSM_TS_STAT_LO_OFFSET (0x81218579UL)
+#define TSM_TS_STAT_LO_OFFSET_NS (0xb7ff33UL)
+#define TSM_TS_STAT_TAR_HI (0x65af24b6UL)
+#define TSM_TS_STAT_TAR_HI_SEC (0x7e92f619UL)
+#define TSM_TS_STAT_TAR_LO (0xe8a04487UL)
+#define TSM_TS_STAT_TAR_LO_NS (0xf7b3f439UL)
+#define TSM_TS_STAT_X (0x419f0ddUL)
+#define TSM_TS_STAT_X_NS (0xa48c3f27UL)
+#define TSM_TS_STAT_X2_HI (0xd6b1c517UL)
+#define TSM_TS_STAT_X2_HI_NS (0x4288c50fUL)
+#define TSM_TS_STAT_X2_LO (0x5bbea526UL)
+#define TSM_TS_STAT_X2_LO_NS (0x92633c13UL)
+#define TSM_UTC_OFFSET (0xf622a13aUL)
+#define TSM_UTC_OFFSET_SEC (0xd9c80209UL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_TSM_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_cpy.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_cpy.h
new file mode 100644
index 0000000000..2b156f9de9
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_cpy.h
@@ -0,0 +1,22 @@
+/*
+ * nthw_fpga_reg_defs_tx_cpy.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_TX_CPY_
+#define _NTHW_FPGA_REG_DEFS_TX_CPY_
+
+/* TX_CPY */
+#define NTHW_MOD_TX_CPY (0x60acf217UL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_TX_CPY_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_csi.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_csi.h
new file mode 100644
index 0000000000..98d9bbc452
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_csi.h
@@ -0,0 +1,22 @@
+/*
+ * nthw_fpga_reg_defs_tx_csi.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_TX_CSI_
+#define _NTHW_FPGA_REG_DEFS_TX_CSI_
+
+/* TX_CSI */
+#define NTHW_MOD_TX_CSI (0x5636b1b0UL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_TX_CSI_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_cso.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_cso.h
new file mode 100644
index 0000000000..8b2d77878b
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_cso.h
@@ -0,0 +1,22 @@
+/*
+ * nthw_fpga_reg_defs_tx_cso.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_TX_CSO_
+#define _NTHW_FPGA_REG_DEFS_TX_CSO_
+
+/* TX_CSO */
+#define NTHW_MOD_TX_CSO (0xbf551485UL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_TX_CSO_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_ins.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_ins.h
new file mode 100644
index 0000000000..48add8d788
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_ins.h
@@ -0,0 +1,22 @@
+/*
+ * nthw_fpga_reg_defs_tx_ins.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_TX_INS_
+#define _NTHW_FPGA_REG_DEFS_TX_INS_
+
+/* TX_INS */
+#define NTHW_MOD_TX_INS (0x59afa100UL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_TX_INS_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_rpl.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_rpl.h
new file mode 100644
index 0000000000..2ddeadaf53
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_tx_rpl.h
@@ -0,0 +1,22 @@
+/*
+ * nthw_fpga_reg_defs_tx_rpl.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_TX_RPL_
+#define _NTHW_FPGA_REG_DEFS_TX_RPL_
+
+/* TX_RPL */
+#define NTHW_MOD_TX_RPL (0x1095dfbbUL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_TX_RPL_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
-- 
2.44.0


^ permalink raw reply	[flat|nested] 238+ messages in thread

* [PATCH v1 02/17] net/ntnic: add core platform functionality
  2024-05-30 14:48 [PATCH v1 01/17] net/ntnic: Add registers for NapaTech SmartNiC Serhii Iliushyk
@ 2024-05-30 14:48 ` Serhii Iliushyk
  2024-05-30 14:49 ` [PATCH v1 03/17] net/ntnic: add interfaces for " Serhii Iliushyk
                   ` (23 subsequent siblings)
  24 siblings, 0 replies; 238+ messages in thread
From: Serhii Iliushyk @ 2024-05-30 14:48 UTC (permalink / raw)
  To: dev; +Cc: mko-plv, ckm, andrew.rybchenko, ferruh.yigit

Add ntnic platform interfaces for FPGA registers

Signed-off-by: Serhii Iliushyk <sil-plv@napatech.com>
---
 drivers/net/ntnic/nthw/nthw_drv.h          |  94 +++
 drivers/net/ntnic/nthw/nthw_epp.c          | 226 ++++++
 drivers/net/ntnic/nthw/nthw_epp.h          |  92 +++
 drivers/net/ntnic/nthw/nthw_helper.h       |  30 +
 drivers/net/ntnic/nthw/nthw_platform.c     |  52 ++
 drivers/net/ntnic/nthw/nthw_platform_drv.h |  49 ++
 drivers/net/ntnic/nthw/nthw_profile.h      |  16 +
 drivers/net/ntnic/nthw/nthw_rac.c          | 801 +++++++++++++++++++++
 drivers/net/ntnic/nthw/nthw_rac.h          | 154 ++++
 drivers/net/ntnic/nthw/nthw_register.h     |  22 +
 drivers/net/ntnic/nthw/nthw_utils.c        |  53 ++
 drivers/net/ntnic/nthw/nthw_utils.h        |  11 +
 12 files changed, 1600 insertions(+)
 create mode 100644 drivers/net/ntnic/nthw/nthw_drv.h
 create mode 100644 drivers/net/ntnic/nthw/nthw_epp.c
 create mode 100644 drivers/net/ntnic/nthw/nthw_epp.h
 create mode 100644 drivers/net/ntnic/nthw/nthw_helper.h
 create mode 100644 drivers/net/ntnic/nthw/nthw_platform.c
 create mode 100644 drivers/net/ntnic/nthw/nthw_platform_drv.h
 create mode 100644 drivers/net/ntnic/nthw/nthw_profile.h
 create mode 100644 drivers/net/ntnic/nthw/nthw_rac.c
 create mode 100644 drivers/net/ntnic/nthw/nthw_rac.h
 create mode 100644 drivers/net/ntnic/nthw/nthw_register.h
 create mode 100644 drivers/net/ntnic/nthw/nthw_utils.c
 create mode 100644 drivers/net/ntnic/nthw/nthw_utils.h

diff --git a/drivers/net/ntnic/nthw/nthw_drv.h b/drivers/net/ntnic/nthw/nthw_drv.h
new file mode 100644
index 0000000000..e9e25bbc29
--- /dev/null
+++ b/drivers/net/ntnic/nthw/nthw_drv.h
@@ -0,0 +1,94 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef __NTHW_DRV_H__
+#define __NTHW_DRV_H__
+
+#include "nthw_profile.h"
+
+typedef enum nt_meta_port_type_e {
+	PORT_TYPE_PHYSICAL,
+	PORT_TYPE_VIRTUAL,
+	PORT_TYPE_OVERRIDE,
+} nt_meta_port_type_t;
+
+#include "nthw_helper.h"
+#include "nthw_utils.h"
+#include "nthw_platform_drv.h"
+#include "nthw_fpga_model.h"
+#include "ntnic_stat.h"
+#include "ntnic_dbs.h"
+#include "nthw_epp.h"
+#include "nthw_core.h"
+
+typedef struct mcu_info_s {
+	bool mb_has_mcu;
+	int mn_mcu_type;
+	int mn_mcu_dram_size;
+} mcu_info_t;
+
+typedef struct nthw_hw_info_s {
+	/* From FW */
+	int hw_id;
+	int hw_id_emulated;
+	char hw_plat_id_str[32];
+
+	struct vpd_info_s {
+		int mn_mac_addr_count;
+		uint64_t mn_mac_addr_value;
+		uint8_t ma_mac_addr_octets[6];
+	} vpd_info;
+} nthw_hw_info_t;
+
+typedef struct fpga_info_s {
+	uint64_t n_fpga_ident;
+
+	int n_fpga_type_id;
+	int n_fpga_prod_id;
+	int n_fpga_ver_id;
+	int n_fpga_rev_id;
+
+	int n_fpga_build_time;
+
+	int n_fpga_debug_mode;
+
+	int n_nims;
+	int n_phy_ports;
+	int n_phy_quads;
+	int n_rx_ports;
+	int n_tx_ports;
+	int n_vf_offset;
+
+	enum fpga_info_profile profile;
+
+	struct nthw_fpga_s *mp_fpga;
+
+	struct nthw_rac *mp_nthw_rac;
+	struct nthw_hif *mp_nthw_hif;
+	struct nthw_pcie3 *mp_nthw_pcie3;
+	struct nthw_tsm *mp_nthw_tsm;
+
+	nthw_dbs_t *mp_nthw_dbs;
+	nthw_epp_t *mp_nthw_epp;
+
+	uint8_t *bar0_addr;	/* Needed for register read/write */
+	size_t bar0_size;
+
+	int adapter_no;	/* Needed for nthw_rac DMA array indexing */
+	uint32_t pciident;	/* Needed for nthw_rac DMA memzone_reserve */
+	int numa_node;	/* Needed for nthw_rac DMA memzone_reserve */
+
+	char *mp_adapter_id_str;/* Pointer to string literal used in nthw log messages */
+
+	struct mcu_info_s mcu_info;
+
+	struct nthw_hw_info_s nthw_hw_info;
+
+	nthw_adapter_id_t n_nthw_adapter_id;
+
+} fpga_info_t;
+
+
+#endif	/* __NTHW_DRV_H__ */
diff --git a/drivers/net/ntnic/nthw/nthw_epp.c b/drivers/net/ntnic/nthw/nthw_epp.c
new file mode 100644
index 0000000000..fe1c562394
--- /dev/null
+++ b/drivers/net/ntnic/nthw/nthw_epp.c
@@ -0,0 +1,226 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#include "ntlog.h"
+
+#include "nthw_drv.h"
+#include "nthw_register.h"
+
+#include "nthw_epp.h"
+
+#include <errno.h>	/* ENOTSUP */
+
+nthw_epp_t *nthw_epp_new(void)
+{
+	nthw_epp_t *p = malloc(sizeof(nthw_epp_t));
+
+	if (p)
+		memset(p, 0, sizeof(nthw_epp_t));
+
+	return p;
+}
+
+int nthw_epp_present(nthw_fpga_t *p_fpga, int n_instance)
+{
+	return nthw_epp_init(NULL, p_fpga, n_instance) == 0;
+}
+
+int nthw_epp_init(nthw_epp_t *p, nthw_fpga_t *p_fpga, int n_instance)
+{
+	nthw_module_t *mod = nthw_fpga_query_module(p_fpga, MOD_EPP, n_instance);
+
+	if (p == NULL)
+		return mod == NULL ? -1 : 0;
+
+	if (mod == NULL) {
+		NT_LOG(ERR, NTHW, "%s: EPP %d: no such instance\n",
+			p_fpga->p_fpga_info->mp_adapter_id_str, n_instance);
+		return -1;
+	}
+
+	p->mp_fpga = p_fpga;
+	p->mn_instance = n_instance;
+	p->mp_mod_epp = mod;
+
+	p->mn_epp_categories = nthw_fpga_get_product_param(p_fpga, NT_EPP_CATEGORIES, 0);
+
+	p->mp_reg_reciepe_memory_control = nthw_module_get_register(p->mp_mod_epp, EPP_RCP_CTRL);
+	p->mp_fld_reciepe_memory_control_adr =
+		nthw_register_get_field(p->mp_reg_reciepe_memory_control, EPP_RCP_CTRL_ADR);
+	p->mp_fld_reciepe_memory_control_cnt =
+		nthw_register_get_field(p->mp_reg_reciepe_memory_control, EPP_RCP_CTRL_CNT);
+
+	p->mp_reg_reciepe_memory_data = nthw_module_get_register(p->mp_mod_epp, EPP_RCP_DATA);
+	p->mp_fld_reciepe_memory_data_tx_mtu_epp_enable =
+		nthw_register_get_field(p->mp_reg_reciepe_memory_data, EPP_RCP_DATA_TX_MTU_EPP_EN);
+	p->mp_fld_reciepe_memory_data_queue_mtu_epp_enable =
+		nthw_register_get_field(p->mp_reg_reciepe_memory_data,
+			EPP_RCP_DATA_QUEUE_MTU_EPP_EN);
+	p->mp_fld_reciepe_memory_data_size_adjust_tx_port =
+		nthw_register_get_field(p->mp_reg_reciepe_memory_data,
+			EPP_RCP_DATA_SIZE_ADJUST_TXP);
+	p->mp_fld_reciepe_memory_data_size_adjust_virtual_port =
+		nthw_register_get_field(p->mp_reg_reciepe_memory_data,
+			EPP_RCP_DATA_SIZE_ADJUST_VPORT);
+	p->mp_fld_reciepe_memory_data_fixed18b_l2_mtu =
+		nthw_register_get_field(p->mp_reg_reciepe_memory_data,
+			EPP_RCP_DATA_FIXED_18B_L2_MTU);
+	p->mp_fld_reciepe_memory_data_txp_qos_epp_enable =
+		nthw_register_get_field(p->mp_reg_reciepe_memory_data, EPP_RCP_DATA_TX_QOS_EPP_EN);
+	p->mp_fld_reciepe_memory_data_queue_qos_epp_enable =
+		nthw_register_get_field(p->mp_reg_reciepe_memory_data,
+			EPP_RCP_DATA_QUEUE_QOS_EPP_EN);
+
+	p->mp_reg_txp_port_mtu_control = nthw_module_get_register(p->mp_mod_epp, EPP_TXP_MTU_CTRL);
+	p->mp_fld_txp_port_mtu_control_adr =
+		nthw_register_get_field(p->mp_reg_txp_port_mtu_control, EPP_TXP_MTU_CTRL_ADR);
+	p->mp_fld_txp_port_mtu_control_cnt =
+		nthw_register_get_field(p->mp_reg_txp_port_mtu_control, EPP_TXP_MTU_CTRL_CNT);
+
+	p->mp_reg_txp_port_mtu_data = nthw_module_get_register(p->mp_mod_epp, EPP_TXP_MTU_DATA);
+	p->mp_fld_txp_port_mtu_data_max_mtu =
+		nthw_register_get_field(p->mp_reg_txp_port_mtu_data, EPP_TXP_MTU_DATA_MAX_MTU);
+
+	p->mp_reg_queue_mtu_control = nthw_module_get_register(p->mp_mod_epp, EPP_QUEUE_MTU_CTRL);
+	p->mp_fld_queue_mtu_control_adr =
+		nthw_register_get_field(p->mp_reg_queue_mtu_control, EPP_QUEUE_MTU_CTRL_ADR);
+	p->mp_fld_queue_mtu_control_cnt =
+		nthw_register_get_field(p->mp_reg_queue_mtu_control, EPP_QUEUE_MTU_CTRL_CNT);
+
+	p->mp_reg_queue_mtu_data = nthw_module_get_register(p->mp_mod_epp, EPP_QUEUE_MTU_DATA);
+	p->mp_fld_queue_mtu_data_max_mtu =
+		nthw_register_get_field(p->mp_reg_queue_mtu_data, EPP_QUEUE_MTU_DATA_MAX_MTU);
+
+	p->mp_reg_txp_qos_control = nthw_module_get_register(p->mp_mod_epp, EPP_TXP_QOS_CTRL);
+	p->mp_fld_txp_qos_control_adr =
+		nthw_register_get_field(p->mp_reg_txp_qos_control, EPP_TXP_QOS_CTRL_ADR);
+	p->mp_fld_txp_qos_control_cnt =
+		nthw_register_get_field(p->mp_reg_txp_qos_control, EPP_TXP_QOS_CTRL_CNT);
+
+	p->mp_reg_txp_qos_data = nthw_module_get_register(p->mp_mod_epp, EPP_TXP_QOS_DATA);
+	p->mp_fld_txp_qos_data_enable =
+		nthw_register_get_field(p->mp_reg_txp_qos_data, EPP_TXP_QOS_DATA_EN);
+	p->mp_fld_txp_qos_data_information_rate =
+		nthw_register_get_field(p->mp_reg_txp_qos_data, EPP_TXP_QOS_DATA_IR);
+	p->mp_fld_txp_qos_data_information_rate_fractional =
+		nthw_register_get_field(p->mp_reg_txp_qos_data, EPP_TXP_QOS_DATA_IR_FRACTION);
+	p->mp_fld_txp_qos_data_burst_size =
+		nthw_register_get_field(p->mp_reg_txp_qos_data, EPP_TXP_QOS_DATA_BS);
+
+	p->mp_reg_vport_qos_control = nthw_module_get_register(p->mp_mod_epp, EPP_VPORT_QOS_CTRL);
+	p->mp_fld_vport_qos_control_adr =
+		nthw_register_get_field(p->mp_reg_vport_qos_control, EPP_VPORT_QOS_CTRL_ADR);
+	p->mp_fld_vport_qos_control_cnt =
+		nthw_register_get_field(p->mp_reg_vport_qos_control, EPP_VPORT_QOS_CTRL_CNT);
+
+	p->mp_reg_vport_qos_data = nthw_module_get_register(p->mp_mod_epp, EPP_VPORT_QOS_DATA);
+	p->mp_fld_vport_qos_data_enable =
+		nthw_register_get_field(p->mp_reg_vport_qos_data, EPP_VPORT_QOS_DATA_EN);
+	p->mp_fld_vport_qos_data_information_rate =
+		nthw_register_get_field(p->mp_reg_vport_qos_data, EPP_VPORT_QOS_DATA_IR);
+	p->mp_fld_vport_qos_data_information_rate_fractional =
+		nthw_register_get_field(p->mp_reg_vport_qos_data, EPP_VPORT_QOS_DATA_IR_FRACTION);
+	p->mp_fld_vport_qos_data_burst_size =
+		nthw_register_get_field(p->mp_reg_vport_qos_data, EPP_VPORT_QOS_DATA_BS);
+
+	p->mp_reg_queue_vport_control =
+		nthw_module_get_register(p->mp_mod_epp, EPP_QUEUE_VPORT_CTRL);
+	p->mp_fld_queue_vport_control_adr =
+		nthw_register_get_field(p->mp_reg_queue_vport_control, EPP_QUEUE_VPORT_CTRL_ADR);
+	p->mp_fld_queue_vport_control_cnt =
+		nthw_register_get_field(p->mp_reg_queue_vport_control, EPP_QUEUE_VPORT_CTRL_CNT);
+
+	p->mp_reg_queue_vport_data = nthw_module_get_register(p->mp_mod_epp, EPP_QUEUE_VPORT_DATA);
+	p->mp_fld_queue_vport_data_vport =
+		nthw_register_get_field(p->mp_reg_queue_vport_data, EPP_QUEUE_VPORT_DATA_VPORT);
+
+	return 0;
+}
+
+int nthw_epp_setup(nthw_epp_t *p)
+{
+	if (p == NULL)
+		return 0;
+
+	/* Set recieps for 2 first records */
+	nthw_field_set_val32(p->mp_fld_reciepe_memory_control_cnt, 1);
+
+	/* Zero all categories */
+	for (int i = 0; i < p->mn_epp_categories; ++i) {
+		nthw_field_set_val32(p->mp_fld_reciepe_memory_control_adr, i);
+		nthw_register_flush(p->mp_reg_reciepe_memory_control, 1);
+
+		nthw_field_set_val32(p->mp_fld_reciepe_memory_data_tx_mtu_epp_enable, 0);
+		nthw_field_set_val32(p->mp_fld_reciepe_memory_data_queue_mtu_epp_enable, 0);
+		nthw_field_set_val32(p->mp_fld_reciepe_memory_data_size_adjust_tx_port, 0);
+		nthw_field_set_val32(p->mp_fld_reciepe_memory_data_size_adjust_virtual_port, 0);
+		nthw_field_set_val32(p->mp_fld_reciepe_memory_data_fixed18b_l2_mtu, 0);
+		nthw_field_set_val32(p->mp_fld_reciepe_memory_data_txp_qos_epp_enable, 0);
+		nthw_field_set_val32(p->mp_fld_reciepe_memory_data_queue_qos_epp_enable, 0);
+		nthw_register_flush(p->mp_reg_reciepe_memory_data, 1);
+	}
+
+	for (int i = 0; i < NRECIPE; ++i) {
+		nthw_field_set_val32(p->mp_fld_reciepe_memory_control_adr, i);
+		nthw_register_flush(p->mp_reg_reciepe_memory_control, 1);
+
+		nthw_field_set_val32(p->mp_fld_reciepe_memory_data_tx_mtu_epp_enable, 1);
+		nthw_field_set_val32(p->mp_fld_reciepe_memory_data_queue_mtu_epp_enable, 1);
+		nthw_field_set_val32(p->mp_fld_reciepe_memory_data_size_adjust_tx_port,
+			rcp_data_size_adjust_txp[i]);
+		nthw_field_set_val32(p->mp_fld_reciepe_memory_data_size_adjust_virtual_port,
+			rcp_data_size_adjust_vport[i]);
+		nthw_field_set_val32(p->mp_fld_reciepe_memory_data_fixed18b_l2_mtu, 1);
+		nthw_field_set_val32(p->mp_fld_reciepe_memory_data_txp_qos_epp_enable, 1);
+		nthw_field_set_val32(p->mp_fld_reciepe_memory_data_queue_qos_epp_enable, 1);
+		nthw_register_flush(p->mp_reg_reciepe_memory_data, 1);
+	}
+
+	/* phy mtu setup */
+	nthw_field_set_val32(p->mp_fld_txp_port_mtu_control_cnt, 1);
+
+	for (int i = 0; i < 2; ++i) {
+		nthw_field_set_val32(p->mp_fld_txp_port_mtu_control_adr, i);
+		nthw_register_flush(p->mp_reg_txp_port_mtu_control, 1);
+
+		nthw_field_set_val32(p->mp_fld_txp_port_mtu_data_max_mtu, MTUINITVAL);
+		nthw_register_flush(p->mp_reg_txp_port_mtu_data, 1);
+	}
+
+	/* phy QoS setup */
+	nthw_field_set_val32(p->mp_fld_txp_qos_control_cnt, 1);
+
+	for (int i = 0; i < 2; ++i) {
+		nthw_field_set_val32(p->mp_fld_txp_qos_control_adr, i);
+		nthw_register_flush(p->mp_reg_txp_qos_control, 1);
+
+		nthw_field_set_val32(p->mp_fld_txp_qos_data_enable, 0);
+		nthw_register_flush(p->mp_reg_txp_qos_data, 1);
+	}
+
+	/* virt mtu setup */
+	nthw_field_set_val32(p->mp_fld_queue_mtu_control_cnt, 1);
+
+	for (int i = 0; i < 128; ++i) {
+		nthw_field_set_val32(p->mp_fld_queue_mtu_control_adr, i);
+		nthw_register_flush(p->mp_reg_queue_mtu_control, 1);
+
+		nthw_field_set_val32(p->mp_fld_queue_mtu_data_max_mtu, MTUINITVAL);
+		nthw_register_flush(p->mp_reg_queue_mtu_data, 1);
+	}
+
+	/* virt QoS setup */
+	nthw_field_set_val32(p->mp_fld_vport_qos_control_cnt, 1);
+
+	for (int i = 0; i < 128; ++i) {
+		nthw_field_set_val32(p->mp_fld_vport_qos_control_adr, i);
+		nthw_register_flush(p->mp_reg_vport_qos_control, 1);
+
+		nthw_field_set_val32(p->mp_fld_vport_qos_data_enable, 0);
+		nthw_register_flush(p->mp_reg_vport_qos_data, 1);
+	}
+
+	return 0;
+}
diff --git a/drivers/net/ntnic/nthw/nthw_epp.h b/drivers/net/ntnic/nthw/nthw_epp.h
new file mode 100644
index 0000000000..413a812273
--- /dev/null
+++ b/drivers/net/ntnic/nthw/nthw_epp.h
@@ -0,0 +1,92 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef NTHW_EPP_HPP_
+#define NTHW_EPP_HPP_
+
+/* VXLAN adds extra 50 bytes */
+#define VXLANDATASIZEADJUST 50
+#define VXLANDATASIZEADJUSTIPV6 70
+#define MTUINITVAL 1500
+#define NRECIPE 3
+
+/* List of size adjust values to put in the recipe memory data register at startup */
+static const int rcp_data_size_adjust_txp[NRECIPE] = { 0, VXLANDATASIZEADJUST,
+		VXLANDATASIZEADJUSTIPV6
+	};
+static const int rcp_data_size_adjust_vport[NRECIPE] = { 0, VXLANDATASIZEADJUST,
+		VXLANDATASIZEADJUSTIPV6
+	};
+
+struct nthw_epp_s {
+	nthw_fpga_t *mp_fpga;
+	nthw_module_t *mp_mod_epp;
+	int mn_instance;
+	int mn_epp_categories;
+
+	nthw_register_t *mp_reg_reciepe_memory_control;
+	nthw_field_t *mp_fld_reciepe_memory_control_adr;
+	nthw_field_t *mp_fld_reciepe_memory_control_cnt;
+
+	nthw_register_t *mp_reg_reciepe_memory_data;
+	nthw_field_t *mp_fld_reciepe_memory_data_tx_mtu_epp_enable;
+	nthw_field_t *mp_fld_reciepe_memory_data_queue_mtu_epp_enable;
+	nthw_field_t *mp_fld_reciepe_memory_data_size_adjust_tx_port;
+	nthw_field_t *mp_fld_reciepe_memory_data_size_adjust_virtual_port;
+	nthw_field_t *mp_fld_reciepe_memory_data_fixed18b_l2_mtu;
+	nthw_field_t *mp_fld_reciepe_memory_data_txp_qos_epp_enable;
+	nthw_field_t *mp_fld_reciepe_memory_data_queue_qos_epp_enable;
+
+	nthw_register_t *mp_reg_txp_port_mtu_control;
+	nthw_field_t *mp_fld_txp_port_mtu_control_adr;
+	nthw_field_t *mp_fld_txp_port_mtu_control_cnt;
+
+	nthw_register_t *mp_reg_txp_port_mtu_data;
+	nthw_field_t *mp_fld_txp_port_mtu_data_max_mtu;
+
+	nthw_register_t *mp_reg_queue_mtu_control;
+	nthw_field_t *mp_fld_queue_mtu_control_adr;
+	nthw_field_t *mp_fld_queue_mtu_control_cnt;
+
+	nthw_register_t *mp_reg_queue_mtu_data;
+	nthw_field_t *mp_fld_queue_mtu_data_max_mtu;
+
+	nthw_register_t *mp_reg_txp_qos_control;
+	nthw_field_t *mp_fld_txp_qos_control_adr;
+	nthw_field_t *mp_fld_txp_qos_control_cnt;
+
+	nthw_register_t *mp_reg_txp_qos_data;
+	nthw_field_t *mp_fld_txp_qos_data_enable;
+	nthw_field_t *mp_fld_txp_qos_data_information_rate;
+	nthw_field_t *mp_fld_txp_qos_data_information_rate_fractional;
+	nthw_field_t *mp_fld_txp_qos_data_burst_size;
+
+	nthw_register_t *mp_reg_vport_qos_control;
+	nthw_field_t *mp_fld_vport_qos_control_adr;
+	nthw_field_t *mp_fld_vport_qos_control_cnt;
+
+	nthw_register_t *mp_reg_vport_qos_data;
+	nthw_field_t *mp_fld_vport_qos_data_enable;
+	nthw_field_t *mp_fld_vport_qos_data_information_rate;
+	nthw_field_t *mp_fld_vport_qos_data_information_rate_fractional;
+	nthw_field_t *mp_fld_vport_qos_data_burst_size;
+
+	nthw_register_t *mp_reg_queue_vport_control;
+	nthw_field_t *mp_fld_queue_vport_control_adr;
+	nthw_field_t *mp_fld_queue_vport_control_cnt;
+
+	nthw_register_t *mp_reg_queue_vport_data;
+	nthw_field_t *mp_fld_queue_vport_data_vport;
+};
+
+typedef struct nthw_epp_s nthw_epp_t;
+
+nthw_epp_t *nthw_epp_new(void);
+
+int nthw_epp_present(nthw_fpga_t *p_fpga, int n_instance);
+int nthw_epp_init(nthw_epp_t *p, nthw_fpga_t *p_fpga, int n_instance);
+int nthw_epp_setup(nthw_epp_t *p);
+
+#endif	/* NTHW_EPP_HPP_ */
diff --git a/drivers/net/ntnic/nthw/nthw_helper.h b/drivers/net/ntnic/nthw/nthw_helper.h
new file mode 100644
index 0000000000..d1bd5cec79
--- /dev/null
+++ b/drivers/net/ntnic/nthw/nthw_helper.h
@@ -0,0 +1,30 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef __NTHW_HELPER_H__
+#define __NTHW_HELPER_H__
+
+#include <unistd.h>
+#include <stdint.h>
+#include <inttypes.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <stdbool.h>
+#include <string.h>
+#include <assert.h>
+
+#ifndef PRIXPTR
+#define PRIXPTR "llX"
+#endif
+
+#ifndef UINT8_MAX
+#define UINT8_MAX (U8_MAX)
+#endif
+
+#ifndef ARRAY_SIZE
+#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
+#endif
+
+#endif	/* __NTHW_HELPER_H__ */
diff --git a/drivers/net/ntnic/nthw/nthw_platform.c b/drivers/net/ntnic/nthw/nthw_platform.c
new file mode 100644
index 0000000000..510841f2af
--- /dev/null
+++ b/drivers/net/ntnic/nthw/nthw_platform.c
@@ -0,0 +1,52 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#include "nthw_platform_drv.h"
+
+nthw_adapter_id_t nthw_platform_get_nthw_adapter_id(const uint16_t n_pci_device_id)
+{
+	switch (n_pci_device_id) {
+	case NT_HW_PCI_DEVICE_ID_NT40E3:
+		return NT_HW_ADAPTER_ID_NT40E3;
+
+	case NT_HW_PCI_DEVICE_ID_NT100E3:
+		return NT_HW_ADAPTER_ID_NT100E3;
+
+	case NT_HW_PCI_DEVICE_ID_NT80E3:
+		return NT_HW_ADAPTER_ID_NT80E3;
+
+	case NT_HW_PCI_DEVICE_ID_NT40A00:
+		return NT_HW_ADAPTER_ID_NT40E3;
+
+	case NT_HW_PCI_DEVICE_ID_NT40A01:
+		return NT_HW_ADAPTER_ID_NT40E3;
+
+	case NT_HW_PCI_DEVICE_ID_NT200E3:
+		return NT_HW_ADAPTER_ID_NT200E3;
+
+	case NT_HW_PCI_DEVICE_ID_NT200A01:
+		return NT_HW_ADAPTER_ID_NT200A01;
+
+	case NT_HW_PCI_DEVICE_ID_NT200D01:
+		return NT_HW_ADAPTER_ID_NT200D01;
+
+	case NT_HW_PCI_DEVICE_ID_NT200A02_LENOVO:
+	case NT_HW_PCI_DEVICE_ID_NT200A02:
+		return NT_HW_ADAPTER_ID_NT200A02;
+
+	case NT_HW_PCI_DEVICE_ID_NT50B01_LENOVO:
+	case NT_HW_PCI_DEVICE_ID_NT50B01:
+		return NT_HW_ADAPTER_ID_NT50B01;
+
+	case NT_HW_PCI_DEVICE_ID_NT100A01:
+		return NT_HW_ADAPTER_ID_NT100A01;
+
+	case NT_HW_PCI_DEVICE_ID_NT400D11:
+		return NT_HW_ADAPTER_ID_NT400D11;
+
+	default:
+		return NT_HW_ADAPTER_ID_UNKNOWN;
+	}
+}
diff --git a/drivers/net/ntnic/nthw/nthw_platform_drv.h b/drivers/net/ntnic/nthw/nthw_platform_drv.h
new file mode 100644
index 0000000000..96245ffb3e
--- /dev/null
+++ b/drivers/net/ntnic/nthw/nthw_platform_drv.h
@@ -0,0 +1,49 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef __NTHW_PLATFORM_DRV_H__
+#define __NTHW_PLATFORM_DRV_H__
+
+#include "nthw_helper.h"
+
+#define NT_HW_PCI_VENDOR_ID (0x18f4)
+#define NT_HW_PCI_VENDOR_ID_LENOVO (0x17aa)
+
+#define NT_HW_PCI_DEVICE_ID_NT40E3 (0x145)
+#define NT_HW_PCI_DEVICE_ID_NT100E3 (0x155)
+#define NT_HW_PCI_DEVICE_ID_NT80E3 (0x165)
+#define NT_HW_PCI_DEVICE_ID_NT40A00 (0x175)	/* ehrmmm bummer */
+#define NT_HW_PCI_DEVICE_ID_NT40A01 (0x185)
+#define NT_HW_PCI_DEVICE_ID_NT200E3 (0x195)
+#define NT_HW_PCI_DEVICE_ID_NT200A01 (0x1A5)
+#define NT_HW_PCI_DEVICE_ID_NT200D01 (0x1B5)
+#define NT_HW_PCI_DEVICE_ID_NT200A02 (0x1C5)
+#define NT_HW_PCI_DEVICE_ID_NT50B01 (0x1D5)
+#define NT_HW_PCI_DEVICE_ID_NT100A01 (0x1E5)
+#define NT_HW_PCI_DEVICE_ID_NT400D11 (0x215)
+
+#define NT_HW_PCI_DEVICE_ID_NT200A02_LENOVO (0x05a1)
+#define NT_HW_PCI_DEVICE_ID_NT50B01_LENOVO (0x05b1)
+
+enum nthw_adapter_id_e {
+	NT_HW_ADAPTER_ID_UNKNOWN = 0,
+	NT_HW_ADAPTER_ID_NT40E3,
+	NT_HW_ADAPTER_ID_NT40A01 = NT_HW_ADAPTER_ID_NT40E3,
+	NT_HW_ADAPTER_ID_NT50B01,
+	NT_HW_ADAPTER_ID_NT80E3,
+	NT_HW_ADAPTER_ID_NT100E3,
+	NT_HW_ADAPTER_ID_NT100A01,
+	NT_HW_ADAPTER_ID_NT200E3,
+	NT_HW_ADAPTER_ID_NT200A01,
+	NT_HW_ADAPTER_ID_NT200D01,
+	NT_HW_ADAPTER_ID_NT200A02,
+	NT_HW_ADAPTER_ID_NT400D11,
+};
+
+typedef enum nthw_adapter_id_e nthw_adapter_id_t;
+
+nthw_adapter_id_t nthw_platform_get_nthw_adapter_id(const uint16_t n_pci_device_id);
+
+#endif	/* __NTHW_PLATFORM_DRV_H__ */
diff --git a/drivers/net/ntnic/nthw/nthw_profile.h b/drivers/net/ntnic/nthw/nthw_profile.h
new file mode 100644
index 0000000000..d7ac30b20d
--- /dev/null
+++ b/drivers/net/ntnic/nthw/nthw_profile.h
@@ -0,0 +1,16 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef __NTHW_PROFILE_H__
+#define __NTHW_PROFILE_H__
+
+enum fpga_info_profile {
+	FPGA_INFO_PROFILE_UNKNOWN = 0,
+	FPGA_INFO_PROFILE_VSWITCH = 1,
+	FPGA_INFO_PROFILE_INLINE = 2,
+	FPGA_INFO_PROFILE_CAPTURE = 3,
+};
+
+#endif	/* __NTHW_PROFILE_H__ */
diff --git a/drivers/net/ntnic/nthw/nthw_rac.c b/drivers/net/ntnic/nthw/nthw_rac.c
new file mode 100644
index 0000000000..e0a8847d08
--- /dev/null
+++ b/drivers/net/ntnic/nthw/nthw_rac.c
@@ -0,0 +1,801 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#include "nt_util.h"
+#include "ntlog.h"
+
+#include "nthw_drv.h"
+#include "nthw_register.h"
+#include "nthw_rac.h"
+
+#include <pthread.h>
+
+/*
+ * Prevent that RAB echo debug trace ever gets into a release build
+ */
+#if defined(DEBUG)
+#undef RAB_DEBUG_ECHO
+#else
+#undef RAB_DEBUG_ECHO
+#endif	/* DEBUG */
+
+#define RAB_DMA_WAIT (1000000)
+
+#define RAB_READ (0x01)
+#define RAB_WRITE (0x02)
+#define RAB_ECHO (0x08)
+#define RAB_COMPLETION (0x0F)
+
+#define RAB_OPR_LO (28)
+#define RAB_OPR_HI (31)
+#define RAB_OPR_BW (4)
+
+#define RAB_CNT_LO (20)
+#define RAB_CNT_HI (27)
+#define RAB_CNT_BW (8)
+
+#define RAB_BUSID_LO (16)
+#define RAB_BUSID_HI (19)
+#define RAB_BUSID_BW (4)
+
+#define RAB_ADDR_LO (0)
+#define RAB_ADDR_HI (15)
+#define RAB_ADDR_BW (16)
+
+nthw_rac_t *nthw_rac_new(void)
+{
+	nthw_rac_t *p = malloc(sizeof(nthw_rac_t));
+	memset(p, 0, sizeof(nthw_rac_t));
+	return p;
+}
+
+int nthw_rac_init(nthw_rac_t *p, nthw_fpga_t *p_fpga, struct fpga_info_s *p_fpga_info)
+{
+	assert(p_fpga_info);
+
+	const char *const p_adapter_id_str = p_fpga_info->mp_adapter_id_str;
+	nthw_module_t *p_mod = nthw_fpga_query_module(p_fpga, MOD_RAC, 0);
+
+	if (p == NULL)
+		return p_mod == NULL ? -1 : 0;
+
+	if (p_mod == NULL) {
+		NT_LOG(ERR, NTHW, "%s: RAC %d: no such instance\n", p_adapter_id_str, 0);
+		return -1;
+	}
+
+	p->mp_fpga = p_fpga;
+	p->mp_mod_rac = p_mod;
+
+	/* Params */
+	p->mn_param_rac_rab_interfaces =
+		nthw_fpga_get_product_param(p->mp_fpga, NT_RAC_RAB_INTERFACES, 3);
+	NT_LOG(DBG, NTHW, "%s: NT_RAC_RAB_INTERFACES=%d\n", p_adapter_id_str,
+		p->mn_param_rac_rab_interfaces);
+
+	p->mn_param_rac_rab_ob_update =
+		nthw_fpga_get_product_param(p->mp_fpga, NT_RAC_RAB_OB_UPDATE, 0);
+	NT_LOG(DBG, NTHW, "%s: NT_RAC_RAB_OB_UPDATE=%d\n", p_adapter_id_str,
+		p->mn_param_rac_rab_ob_update);
+
+	/* Optional dummy test registers */
+	p->mp_reg_dummy0 = nthw_module_query_register(p->mp_mod_rac, RAC_DUMMY0);
+	p->mp_reg_dummy1 = nthw_module_query_register(p->mp_mod_rac, RAC_DUMMY1);
+	p->mp_reg_dummy2 = nthw_module_query_register(p->mp_mod_rac, RAC_DUMMY2);
+
+	p->mp_reg_rab_init = nthw_module_get_register(p->mp_mod_rac, RAC_RAB_INIT);
+	p->mp_fld_rab_init = nthw_register_get_field(p->mp_reg_rab_init, RAC_RAB_INIT_RAB);
+	p->mn_fld_rab_init_bw = nthw_field_get_bit_width(p->mp_fld_rab_init);
+	p->mn_fld_rab_init_mask = nthw_field_get_mask(p->mp_fld_rab_init);
+
+	/* RAC_RAB_INIT_RAB reg/field sanity checks: */
+	assert(p->mn_fld_rab_init_mask == ((1UL << p->mn_fld_rab_init_bw) - 1));
+	assert(p->mn_fld_rab_init_bw == p->mn_param_rac_rab_interfaces);
+
+	p->mp_reg_dbg_ctrl = nthw_module_query_register(p->mp_mod_rac, RAC_DBG_CTRL);
+
+	if (p->mp_reg_dbg_ctrl)
+		p->mp_fld_dbg_ctrl = nthw_register_query_field(p->mp_reg_dbg_ctrl, RAC_DBG_CTRL_C);
+
+	else
+		p->mp_fld_dbg_ctrl = NULL;
+
+	p->mp_reg_dbg_data = nthw_module_query_register(p->mp_mod_rac, RAC_DBG_DATA);
+
+	if (p->mp_reg_dbg_data)
+		p->mp_fld_dbg_data = nthw_register_query_field(p->mp_reg_dbg_data, RAC_DBG_DATA_D);
+
+	else
+		p->mp_reg_dbg_data = NULL;
+
+	p->mp_reg_rab_ib_data = nthw_module_get_register(p->mp_mod_rac, RAC_RAB_IB_DATA);
+	p->mp_fld_rab_ib_data = nthw_register_get_field(p->mp_reg_rab_ib_data, RAC_RAB_IB_DATA_D);
+
+	p->mp_reg_rab_ob_data = nthw_module_get_register(p->mp_mod_rac, RAC_RAB_OB_DATA);
+	p->mp_fld_rab_ob_data = nthw_register_get_field(p->mp_reg_rab_ob_data, RAC_RAB_OB_DATA_D);
+
+	p->mp_reg_rab_buf_free = nthw_module_get_register(p->mp_mod_rac, RAC_RAB_BUF_FREE);
+	p->mp_fld_rab_buf_free_ib_free =
+		nthw_register_get_field(p->mp_reg_rab_buf_free, RAC_RAB_BUF_FREE_IB_FREE);
+	p->mp_fld_rab_buf_free_ib_ovf =
+		nthw_register_get_field(p->mp_reg_rab_buf_free, RAC_RAB_BUF_FREE_IB_OVF);
+	p->mp_fld_rab_buf_free_ob_free =
+		nthw_register_get_field(p->mp_reg_rab_buf_free, RAC_RAB_BUF_FREE_OB_FREE);
+	p->mp_fld_rab_buf_free_ob_ovf =
+		nthw_register_get_field(p->mp_reg_rab_buf_free, RAC_RAB_BUF_FREE_OB_OVF);
+	p->mp_fld_rab_buf_free_timeout =
+		nthw_register_get_field(p->mp_reg_rab_buf_free, RAC_RAB_BUF_FREE_TIMEOUT);
+
+	p->mp_reg_rab_buf_used = nthw_module_get_register(p->mp_mod_rac, RAC_RAB_BUF_USED);
+	p->mp_fld_rab_buf_used_ib_used =
+		nthw_register_get_field(p->mp_reg_rab_buf_used, RAC_RAB_BUF_USED_IB_USED);
+	p->mp_fld_rab_buf_used_ob_used =
+		nthw_register_get_field(p->mp_reg_rab_buf_used, RAC_RAB_BUF_USED_OB_USED);
+	p->mp_fld_rab_buf_used_flush =
+		nthw_register_get_field(p->mp_reg_rab_buf_used, RAC_RAB_BUF_USED_FLUSH);
+
+	/*
+	 * RAC_RAB_DMA regs are optional - only found in real
+	 * NT4GA - not found in 9231/9232 and earlier
+	 */
+	p->mp_reg_rab_dma_ib_lo = nthw_module_get_register(p->mp_mod_rac, RAC_RAB_DMA_IB_LO);
+	p->mp_fld_rab_dma_ib_lo_phy_addr =
+		nthw_register_get_field(p->mp_reg_rab_dma_ib_lo, RAC_RAB_DMA_IB_LO_PHYADDR);
+
+	p->mp_reg_rab_dma_ib_hi = nthw_module_get_register(p->mp_mod_rac, RAC_RAB_DMA_IB_HI);
+	p->mp_fld_rab_dma_ib_hi_phy_addr =
+		nthw_register_get_field(p->mp_reg_rab_dma_ib_hi, RAC_RAB_DMA_IB_HI_PHYADDR);
+
+	p->mp_reg_rab_dma_ob_lo = nthw_module_get_register(p->mp_mod_rac, RAC_RAB_DMA_OB_LO);
+	p->mp_fld_rab_dma_ob_lo_phy_addr =
+		nthw_register_get_field(p->mp_reg_rab_dma_ob_lo, RAC_RAB_DMA_OB_LO_PHYADDR);
+
+	p->mp_reg_rab_dma_ob_hi = nthw_module_get_register(p->mp_mod_rac, RAC_RAB_DMA_OB_HI);
+	p->mp_fld_rab_dma_ob_hi_phy_addr =
+		nthw_register_get_field(p->mp_reg_rab_dma_ob_hi, RAC_RAB_DMA_OB_HI_PHYADDR);
+
+	p->mp_reg_rab_dma_ib_wr = nthw_module_get_register(p->mp_mod_rac, RAC_RAB_DMA_IB_WR);
+	p->mp_fld_rab_dma_ib_wr_ptr =
+		nthw_register_get_field(p->mp_reg_rab_dma_ib_wr, RAC_RAB_DMA_IB_WR_PTR);
+
+	p->mp_reg_rab_dma_ib_rd = nthw_module_get_register(p->mp_mod_rac, RAC_RAB_DMA_IB_RD);
+	p->mp_fld_rab_dma_ib_rd_ptr =
+		nthw_register_get_field(p->mp_reg_rab_dma_ib_rd, RAC_RAB_DMA_IB_RD_PTR);
+
+	p->mp_reg_rab_dma_ob_wr = nthw_module_get_register(p->mp_mod_rac, RAC_RAB_DMA_OB_WR);
+	p->mp_fld_rab_dma_ob_wr_ptr =
+		nthw_register_get_field(p->mp_reg_rab_dma_ob_wr, RAC_RAB_DMA_OB_WR_PTR);
+
+	p->RAC_RAB_INIT_ADDR = nthw_register_get_address(p->mp_reg_rab_init);
+	p->RAC_RAB_IB_DATA_ADDR = nthw_register_get_address(p->mp_reg_rab_ib_data);
+	p->RAC_RAB_OB_DATA_ADDR = nthw_register_get_address(p->mp_reg_rab_ob_data);
+	p->RAC_RAB_BUF_FREE_ADDR = nthw_register_get_address(p->mp_reg_rab_buf_free);
+	p->RAC_RAB_BUF_USED_ADDR = nthw_register_get_address(p->mp_reg_rab_buf_used);
+
+	/*
+	 * RAC_RAB_DMA regs are optional - only found in real NT4GA - not found in 9231/9232 and
+	 * earlier
+	 */
+
+	p->RAC_RAB_DMA_IB_LO_ADDR = nthw_register_get_address(p->mp_reg_rab_dma_ib_lo);
+	p->RAC_RAB_DMA_IB_HI_ADDR = nthw_register_get_address(p->mp_reg_rab_dma_ib_hi);
+	p->RAC_RAB_DMA_OB_LO_ADDR = nthw_register_get_address(p->mp_reg_rab_dma_ob_lo);
+	p->RAC_RAB_DMA_OB_HI_ADDR = nthw_register_get_address(p->mp_reg_rab_dma_ob_hi);
+	p->RAC_RAB_DMA_IB_RD_ADDR = nthw_register_get_address(p->mp_reg_rab_dma_ib_rd);
+	p->RAC_RAB_DMA_OB_WR_ADDR = nthw_register_get_address(p->mp_reg_rab_dma_ob_wr);
+	p->RAC_RAB_DMA_IB_WR_ADDR = nthw_register_get_address(p->mp_reg_rab_dma_ib_wr);
+
+	p->RAC_RAB_BUF_FREE_IB_FREE_MASK = nthw_field_get_mask(p->mp_fld_rab_buf_free_ib_free);
+	p->RAC_RAB_BUF_FREE_OB_FREE_MASK = nthw_field_get_mask(p->mp_fld_rab_buf_free_ob_free);
+	p->RAC_RAB_BUF_USED_IB_USED_MASK = nthw_field_get_mask(p->mp_fld_rab_buf_used_ib_used);
+	p->RAC_RAB_BUF_USED_OB_USED_MASK = nthw_field_get_mask(p->mp_fld_rab_buf_used_ob_used);
+
+	p->RAC_RAB_BUF_USED_FLUSH_MASK = nthw_field_get_mask(p->mp_fld_rab_buf_used_flush);
+
+	p->RAC_RAB_BUF_USED_OB_USED_LOW =
+		nthw_field_get_bit_pos_low(p->mp_fld_rab_buf_used_ob_used);
+
+	p->mp_reg_rab_nmb_rd = nthw_module_query_register(p->mp_mod_rac, RAC_NMB_RD_ADR);
+
+	if (p->mp_reg_rab_nmb_rd)
+		p->RAC_NMB_RD_ADR_ADDR = nthw_register_get_address(p->mp_reg_rab_nmb_rd);
+
+	p->mp_reg_rab_nmb_data = nthw_module_query_register(p->mp_mod_rac, RAC_NMB_DATA);
+
+	if (p->mp_reg_rab_nmb_data)
+		p->RAC_NMB_DATA_ADDR = nthw_register_get_address(p->mp_reg_rab_nmb_data);
+
+	p->mp_reg_rab_nmb_wr = nthw_module_query_register(p->mp_mod_rac, RAC_NMB_WR_ADR);
+
+	if (p->mp_reg_rab_nmb_wr)
+		p->RAC_NMB_WR_ADR_ADDR = nthw_register_get_address(p->mp_reg_rab_nmb_wr);
+
+	p->mp_reg_rab_nmb_status = nthw_module_query_register(p->mp_mod_rac, RAC_NMB_STATUS);
+
+	if (p->mp_reg_rab_nmb_status)
+		p->RAC_NMB_STATUS_ADDR = nthw_register_get_address(p->mp_reg_rab_nmb_status);
+
+	p->m_dma = NULL;
+
+	{
+		/*
+		 * RAC is a primary communication channel - debug will be messy
+		 * turn off debug by default - except for rac_rab_init
+		 * NOTE: currently debug will not work - due to optimizations
+		 */
+		const int n_debug_mode = nthw_module_get_debug_mode(p->mp_mod_rac);
+
+		if (n_debug_mode && n_debug_mode <= 0xff) {
+			nthw_module_set_debug_mode(p->mp_mod_rac, 0);
+			nthw_register_set_debug_mode(p->mp_reg_rab_init, n_debug_mode);
+		}
+	}
+
+	pthread_mutex_init(&p->m_mutex, NULL);
+
+	return 0;
+}
+
+int nthw_rac_get_rab_interface_count(const nthw_rac_t *p)
+{
+	return p->mn_param_rac_rab_interfaces;
+}
+
+/* private function for internal RAC operations -
+ * improves log flexibility and prevents log flooding
+ */
+static void nthw_rac_reg_read32(const struct fpga_info_s *p_fpga_info, uint32_t reg_addr,
+	uint32_t *p_data)
+{
+	*p_data = *(volatile uint32_t *)((uint8_t *)p_fpga_info->bar0_addr + reg_addr);
+}
+
+/* private function for internal RAC operations -
+ * improves log flexibility and prevents log flooding
+ */
+static void nthw_rac_reg_write32(const struct fpga_info_s *p_fpga_info, uint32_t reg_addr,
+	uint32_t n_data)
+{
+	*(volatile uint32_t *)((uint8_t *)p_fpga_info->bar0_addr + reg_addr) = n_data;
+}
+
+static inline int _nthw_rac_wait_for_rab_done(const nthw_rac_t *p, uint32_t address,
+	uint32_t word_cnt)
+{
+	const struct fpga_info_s *const p_fpga_info = p->mp_fpga->p_fpga_info;
+	const char *const p_adapter_id_str = p_fpga_info->mp_adapter_id_str;
+	uint32_t used = 0;
+	uint32_t retry;
+
+	for (retry = 0; retry < 100000; retry++) {
+		nthw_rac_reg_read32(p_fpga_info, p->RAC_RAB_BUF_USED_ADDR, &used);
+		used = (used & p->RAC_RAB_BUF_USED_OB_USED_MASK) >>
+			p->RAC_RAB_BUF_USED_OB_USED_LOW;
+
+		if (used >= word_cnt)
+			break;
+	}
+
+	if (used < word_cnt) {
+		NT_LOG(ERR, NTHW, "%s: Fail rab bus r/w addr=0x%08X used=%x wordcount=%d\n",
+			p_adapter_id_str, address, used, word_cnt);
+		return -1;
+	}
+
+	return 0;
+}
+
+/*
+ * NT_PCI_REG_P9xyz_RAC_RAB_INIT
+ *
+ * Initializes (resets) the programmable registers on the Register Access Busses (RAB).
+ * This initialization must be performed by software as part of the driver load procedure.
+ *
+ * Bit n of this field initializes the programmable registers on RAB interface n.
+ * Software must write one to the bit and then clear the bit again.
+ *
+ * All RAB module registers will be reset to their defaults.
+ * This includes the product specific RESET module (eg RST9xyz)
+ * As a consequence of this behavior the official reset sequence
+ * must be excersised - as all RAB modules will be held in reset.
+ */
+int nthw_rac_rab_init(nthw_rac_t *p, uint32_t n_rab_intf_mask)
+{
+	/*
+	 * Write rac_rab_init
+	 * Perform operation twice - first to get trace of operation -
+	 * second to get things done...
+	 */
+	const struct fpga_info_s *const p_fpga_info = p->mp_fpga->p_fpga_info;
+	nthw_field_set_val_flush32(p->mp_fld_rab_init, n_rab_intf_mask);
+	nthw_rac_reg_write32(p_fpga_info, p->RAC_RAB_INIT_ADDR, n_rab_intf_mask);
+	return 0;
+}
+
+int nthw_rac_rab_reset(nthw_rac_t *p)
+{
+	const struct fpga_info_s *const p_fpga_info = p->mp_fpga->p_fpga_info;
+	const char *const p_adapter_id_str = p_fpga_info->mp_adapter_id_str;
+	(void)p_adapter_id_str;
+
+	/* RAC RAB bus "flip/flip" reset */
+	const int n_rac_rab_bus_count = nthw_rac_get_rab_interface_count(p);
+	const int n_rac_rab_bus_mask = (1 << n_rac_rab_bus_count) - 1;
+
+	NT_LOG(DBG, NTHW, "%s: NT_RAC_RAB_INTERFACES=%d (0x%02X)\n", p_adapter_id_str,
+		n_rac_rab_bus_count, n_rac_rab_bus_mask);
+	assert(n_rac_rab_bus_count);
+	assert(n_rac_rab_bus_mask);
+
+	/* RAC RAB bus "flip/flip" reset first stage - new impl (ref RMT#37020) */
+	nthw_rac_rab_init(p, 0);
+	nthw_rac_rab_init(p, n_rac_rab_bus_mask);
+	nthw_rac_rab_init(p, n_rac_rab_bus_mask & ~0x01);
+
+	return 0;
+}
+
+int nthw_rac_rab_setup(nthw_rac_t *p)
+{
+	int rc = 0;
+
+	const struct fpga_info_s *const p_fpga_info = p->mp_fpga->p_fpga_info;
+	uint32_t n_dma_buf_size = 2L * RAB_DMA_BUF_CNT * sizeof(uint32_t);
+	const size_t align_size = nt_util_align_size(n_dma_buf_size);
+	int numa_node = p_fpga_info->numa_node;
+	uint64_t dma_addr;
+	uint32_t buf;
+
+	if (!p->m_dma) {
+		struct nt_dma_s *vfio_dma;
+		/* FPGA needs Page alignment (4K) */
+		vfio_dma = nt_dma_alloc(align_size, 0x1000, numa_node);
+
+		if (vfio_dma == NULL) {
+			NT_LOG(ERR, ETHDEV, "%s: nt_dma_alloc failed\n", __func__);
+			return -1;
+		}
+
+		p->m_dma_in_buf = (uint32_t *)vfio_dma->addr;
+		p->m_dma_out_buf = p->m_dma_in_buf + RAB_DMA_BUF_CNT;
+		p->m_dma = vfio_dma;
+	}
+
+	/* Setup DMA on the adapter */
+	dma_addr = p->m_dma->iova;
+	nthw_rac_reg_write32(p_fpga_info, p->RAC_RAB_DMA_IB_LO_ADDR, dma_addr & 0xffffffff);
+	nthw_rac_reg_write32(p_fpga_info, p->RAC_RAB_DMA_IB_HI_ADDR,
+		(uint32_t)(dma_addr >> 32) & 0xffffffff);
+	dma_addr += RAB_DMA_BUF_CNT * sizeof(uint32_t);
+	nthw_rac_reg_write32(p_fpga_info, p->RAC_RAB_DMA_OB_LO_ADDR, dma_addr & 0xffffffff);
+	nthw_rac_reg_write32(p_fpga_info, p->RAC_RAB_DMA_OB_HI_ADDR,
+		(uint32_t)(dma_addr >> 32) & 0xffffffff);
+
+	/* Set initial value of internal pointers */
+	nthw_rac_reg_read32(p_fpga_info, p->RAC_RAB_DMA_IB_RD_ADDR, &buf);
+	p->m_dma_in_ptr_wr = (uint16_t)(buf / sizeof(uint32_t));
+	nthw_rac_reg_read32(p_fpga_info, p->RAC_RAB_DMA_OB_WR_ADDR, &buf);
+	p->m_dma_out_ptr_rd = (uint16_t)(buf / sizeof(uint32_t));
+	p->m_in_free = RAB_DMA_BUF_CNT;
+
+	return rc;
+}
+
+void nthw_rac_bar0_read32(const struct fpga_info_s *p_fpga_info, uint32_t reg_addr,
+	uint32_t word_cnt, uint32_t *p_data)
+{
+	volatile const uint32_t *const src_addr =
+		(uint32_t *)((uint8_t *)p_fpga_info->bar0_addr + reg_addr);
+
+	for (uint32_t i = 0; i < word_cnt; i++)
+		p_data[i] = src_addr[i];
+}
+
+void nthw_rac_bar0_write32(const struct fpga_info_s *p_fpga_info, uint32_t reg_addr,
+	uint32_t word_cnt, const uint32_t *p_data)
+{
+	volatile uint32_t *const dst_addr =
+		(uint32_t *)((uint8_t *)p_fpga_info->bar0_addr + reg_addr);
+
+	for (uint32_t i = 0; i < word_cnt; i++)
+		dst_addr[i] = p_data[i];
+}
+
+int nthw_rac_rab_write32(nthw_rac_t *p, bool trc, nthw_rab_bus_id_t bus_id, uint32_t address,
+	uint32_t word_cnt, const uint32_t *p_data)
+{
+	const struct fpga_info_s *const p_fpga_info = p->mp_fpga->p_fpga_info;
+	const char *const p_adapter_id_str = p_fpga_info->mp_adapter_id_str;
+	uint32_t buf_used;
+	uint32_t buf_free;
+	uint32_t in_buf_free;
+	uint32_t out_buf_free;
+	int res = 0;
+
+	if (address > (1 << RAB_ADDR_BW)) {
+		NT_LOG(ERR, NTHW, "%s: RAB: Illegal address: value too large %d - max %d\n",
+			p_adapter_id_str, address, (1 << RAB_ADDR_BW));
+		return -1;
+	}
+
+	if (bus_id > (1 << RAB_BUSID_BW)) {
+		NT_LOG(ERR, NTHW, "%s: RAB: Illegal bus id: value too large %d - max %d\n",
+			p_adapter_id_str, bus_id, (1 << RAB_BUSID_BW));
+		return -1;
+	}
+
+	if (word_cnt == 0) {
+		NT_LOG(ERR, NTHW, "%s: RAB: Illegal word count: value is zero (%d)\n",
+			p_adapter_id_str, word_cnt);
+		return -1;
+	}
+
+	if (word_cnt > (1 << RAB_CNT_BW)) {
+		NT_LOG(ERR, NTHW, "%s: RAB: Illegal word count: value too large %d - max %d\n",
+			p_adapter_id_str, word_cnt, (1 << RAB_CNT_BW));
+		return -1;
+	}
+
+	pthread_mutex_lock(&p->m_mutex);
+
+	if (p->m_dma_active) {
+		NT_LOG(ERR, NTHW, "%s: RAB: Illegal operation: DMA enabled\n", p_adapter_id_str);
+		res = -1;
+		goto exit_unlock_res;
+	}
+
+	/* Read buffer free register */
+	nthw_rac_reg_read32(p_fpga_info, p->RAC_RAB_BUF_FREE_ADDR, &buf_free);
+
+	in_buf_free = buf_free & p->RAC_RAB_BUF_FREE_IB_FREE_MASK;
+	out_buf_free = (buf_free & p->RAC_RAB_BUF_FREE_OB_FREE_MASK) >> 16;
+
+	/* Read buffer used register */
+	nthw_rac_reg_read32(p_fpga_info, p->RAC_RAB_BUF_USED_ADDR, &buf_used);
+
+	buf_used =
+		buf_used & (p->RAC_RAB_BUF_USED_IB_USED_MASK | p->RAC_RAB_BUF_USED_OB_USED_MASK);
+
+	/*
+	 * Verify that output buffer can hold one completion word,
+	 * input buffer can hold the number of words to be written +
+	 * one write and one completion command
+	 * and that the input and output "used" buffer is 0
+	 */
+	if (out_buf_free >= 1 && in_buf_free >= word_cnt + 2 && buf_used == 0) {
+		const uint32_t rab_oper_cmpl = (RAB_COMPLETION << RAB_OPR_LO);
+		uint32_t rab_echo_oper_cmpl;
+		uint32_t word_cnt_expected = 1;
+		uint32_t rab_oper_wr;
+		uint32_t i;
+
+		rab_oper_wr = (RAB_WRITE << RAB_OPR_LO) |
+			((word_cnt & ((1 << RAB_CNT_BW) - 1)) << RAB_CNT_LO) |
+			(bus_id << RAB_BUSID_LO) | address;
+
+		if (trc) {
+			rab_oper_wr |= (RAB_ECHO << RAB_OPR_LO);
+			word_cnt_expected += word_cnt + 1;
+		}
+
+		/* Write command */
+		nthw_rac_reg_write32(p_fpga_info, p->RAC_RAB_IB_DATA_ADDR, rab_oper_wr);
+
+		/* Write data to input buffer */
+		for (i = 0; i < word_cnt; i++)
+			nthw_rac_reg_write32(p_fpga_info, p->RAC_RAB_IB_DATA_ADDR, p_data[i]);
+
+		/* Write completion command */
+		nthw_rac_reg_write32(p_fpga_info, p->RAC_RAB_IB_DATA_ADDR, rab_oper_cmpl);
+
+		/* Wait until done */
+		if (_nthw_rac_wait_for_rab_done(p, address, word_cnt_expected)) {
+			res = -1;
+			goto exit_unlock_res;
+		}
+
+		if (trc) {
+			uint32_t rab_echo_oper_wr;
+			nthw_rac_reg_read32(p_fpga_info, p->RAC_RAB_OB_DATA_ADDR,
+				&rab_echo_oper_wr);
+
+			if (p->mn_param_rac_rab_ob_update)
+				nthw_rac_reg_write32(p_fpga_info, p->RAC_RAB_OB_DATA_ADDR, 0);
+
+			if (rab_oper_wr != rab_echo_oper_wr) {
+				NT_LOG(ERR, NTHW,
+					"%s: expected rab read echo oper (0x%08X) - read (0x%08X)\n",
+					p_adapter_id_str, rab_oper_wr, rab_echo_oper_wr);
+			}
+		}
+
+		{
+			/* Read data from output buffer */
+			uint32_t data;
+			char *tmp_string;
+
+			if (trc) {
+				tmp_string = ntlog_helper_str_alloc("Register::write");
+				ntlog_helper_str_add(tmp_string,
+					"(Dev: NA, Bus: RAB%u, Addr: 0x%08X, Cnt: %d, Data:",
+					bus_id, address, word_cnt);
+			}
+
+			for (i = 0; i < word_cnt; i++) {
+				nthw_rac_reg_read32(p_fpga_info, p->RAC_RAB_OB_DATA_ADDR, &data);
+
+				if (p->mn_param_rac_rab_ob_update) {
+					nthw_rac_reg_write32(p_fpga_info, p->RAC_RAB_OB_DATA_ADDR,
+						0);
+				}
+
+				if (trc)
+					ntlog_helper_str_add(tmp_string, " 0x%08X", data);
+			}
+
+			if (trc) {
+				ntlog_helper_str_add(tmp_string, ")");
+				NT_LOG(DBG, NTHW, "%s", tmp_string);
+				ntlog_helper_str_free(tmp_string);
+			}
+		}
+
+		/* Read completion from out buffer */
+		nthw_rac_reg_read32(p_fpga_info, p->RAC_RAB_OB_DATA_ADDR, &rab_echo_oper_cmpl);
+
+		if (p->mn_param_rac_rab_ob_update)
+			nthw_rac_reg_write32(p_fpga_info, p->RAC_RAB_OB_DATA_ADDR, 0);
+
+		if (rab_echo_oper_cmpl != rab_oper_cmpl) {
+			NT_LOG(ERR, NTHW,
+				"%s: RAB: Unexpected value of completion (0x%08X)- inBufFree: 0x%08X, outBufFree: 0x%08X, bufUsed: 0x%08X\n",
+				p_adapter_id_str, rab_echo_oper_cmpl, in_buf_free, out_buf_free,
+				buf_used);
+			res = -1;
+			goto exit_unlock_res;
+		}
+
+		/* Read buffer free register */
+		nthw_rac_reg_read32(p_fpga_info, p->RAC_RAB_BUF_FREE_ADDR, &buf_free);
+
+		if (buf_free & 0x80000000) {
+			/* Clear Timeout and overflow bits */
+			nthw_rac_reg_write32(p_fpga_info, p->RAC_RAB_BUF_FREE_ADDR, 0x0);
+			NT_LOG(ERR, NTHW,
+				"%s: RAB: timeout - Access outside register - bus: %d addr: 0x%08X - inBufFree: 0x%08X, outBufFree: 0x%08X, bufUsed: 0x%08X\n",
+				p_adapter_id_str, bus_id, address, in_buf_free, out_buf_free,
+				buf_used);
+			res = -1;
+			goto exit_unlock_res;
+		}
+
+		res = 0;
+		goto exit_unlock_res;
+
+	} else {
+		NT_LOG(ERR, NTHW,
+			"%s: RAB: Fail rab bus buffer check - bus: %d addr: 0x%08X wordcount: %d - inBufFree: 0x%08X, outBufFree: 0x%08X, bufUsed: 0x%08X\n",
+			p_adapter_id_str, bus_id, address, word_cnt, in_buf_free, out_buf_free,
+			buf_used);
+		res = -1;
+		goto exit_unlock_res;
+	}
+
+exit_unlock_res:
+	pthread_mutex_unlock(&p->m_mutex);
+	return res;
+}
+
+int nthw_rac_rab_read32(nthw_rac_t *p, bool trc, nthw_rab_bus_id_t bus_id, uint32_t address,
+	uint32_t word_cnt, uint32_t *p_data)
+{
+	const struct fpga_info_s *const p_fpga_info = p->mp_fpga->p_fpga_info;
+	const char *const p_adapter_id_str = p_fpga_info->mp_adapter_id_str;
+	uint32_t buf_used;
+	uint32_t buf_free;
+	uint32_t in_buf_free;
+	uint32_t out_buf_free;
+	int res = 0;
+
+	pthread_mutex_lock(&p->m_mutex);
+
+	if (address > (1 << RAB_ADDR_BW)) {
+		NT_LOG(ERR, NTHW, "%s: RAB: Illegal address: value too large %d - max %d\n",
+			p_adapter_id_str, address, (1 << RAB_ADDR_BW));
+		res = -1;
+		goto exit_unlock_res;
+	}
+
+	if (bus_id > (1 << RAB_BUSID_BW)) {
+		NT_LOG(ERR, NTHW, "%s: RAB: Illegal bus id: value too large %d - max %d\n",
+			p_adapter_id_str, bus_id, (1 << RAB_BUSID_BW));
+		res = -1;
+		goto exit_unlock_res;
+	}
+
+	if (word_cnt == 0) {
+		NT_LOG(ERR, NTHW, "%s: RAB: Illegal word count: value is zero (%d)\n",
+			p_adapter_id_str, word_cnt);
+		res = -1;
+		goto exit_unlock_res;
+	}
+
+	if (word_cnt > (1 << RAB_CNT_BW)) {
+		NT_LOG(ERR, NTHW, "%s: RAB: Illegal word count: value too large %d - max %d\n",
+			p_adapter_id_str, word_cnt, (1 << RAB_CNT_BW));
+		res = -1;
+		goto exit_unlock_res;
+	}
+
+	/* Read buffer free register */
+	nthw_rac_reg_read32(p_fpga_info, p->RAC_RAB_BUF_FREE_ADDR, &buf_free);
+
+	in_buf_free = buf_free & p->RAC_RAB_BUF_FREE_IB_FREE_MASK;
+	out_buf_free = (buf_free & p->RAC_RAB_BUF_FREE_OB_FREE_MASK) >> 16;
+
+	/* Read buffer used register */
+	nthw_rac_reg_read32(p_fpga_info, p->RAC_RAB_BUF_USED_ADDR, &buf_used);
+
+	buf_used =
+		buf_used & (p->RAC_RAB_BUF_USED_IB_USED_MASK | p->RAC_RAB_BUF_USED_OB_USED_MASK);
+
+	/*
+	 * Verify that output buffer can hold the number of words to be read,
+	 * input buffer can hold one read command
+	 * and that the input and output "used" buffer is 0
+	 */
+	if (out_buf_free >= word_cnt && in_buf_free >= 1 && buf_used == 0) {
+		const uint32_t rab_oper_cmpl = (RAB_COMPLETION << RAB_OPR_LO);
+		uint32_t rab_read_oper_cmpl;
+		uint32_t word_cnt_expected = word_cnt + 1;
+		uint32_t rab_oper_rd;
+
+		rab_oper_rd = (RAB_READ << RAB_OPR_LO) |
+			((word_cnt & ((1 << RAB_CNT_BW) - 1)) << RAB_CNT_LO) |
+			(bus_id << RAB_BUSID_LO) | address;
+
+		if (trc) {
+			rab_oper_rd |= (RAB_ECHO << RAB_OPR_LO);
+			word_cnt_expected++;
+		}
+
+		/* Write command */
+		nthw_rac_reg_write32(p_fpga_info, p->RAC_RAB_IB_DATA_ADDR, rab_oper_rd);
+
+		/* Write completion command */
+		nthw_rac_reg_write32(p_fpga_info, p->RAC_RAB_IB_DATA_ADDR, rab_oper_cmpl);
+
+		/* Wait until done */
+		if (_nthw_rac_wait_for_rab_done(p, address, word_cnt_expected)) {
+			res = -1;
+			goto exit_unlock_res;
+		}
+
+		if (trc) {
+			uint32_t rab_echo_oper_rd;
+			nthw_rac_reg_read32(p_fpga_info, p->RAC_RAB_OB_DATA_ADDR,
+				&rab_echo_oper_rd);
+
+			if (p->mn_param_rac_rab_ob_update)
+				nthw_rac_reg_write32(p_fpga_info, p->RAC_RAB_OB_DATA_ADDR, 0);
+
+			if (rab_oper_rd != rab_echo_oper_rd) {
+				NT_LOG(ERR, NTHW,
+					"%s: RAB: expected rab read echo oper (0x%08X) - read (0x%08X)\n",
+					p_adapter_id_str, rab_oper_rd, rab_echo_oper_rd);
+			}
+		}
+
+		{
+			/* Read data from output buffer */
+			uint32_t i;
+
+			for (i = 0; i < word_cnt; i++) {
+				nthw_rac_reg_read32(p_fpga_info, p->RAC_RAB_OB_DATA_ADDR,
+					&p_data[i]);
+
+				if (p->mn_param_rac_rab_ob_update) {
+					nthw_rac_reg_write32(p_fpga_info, p->RAC_RAB_OB_DATA_ADDR,
+						0);
+				}
+			}
+
+			if (trc) {
+				char *tmp_string = ntlog_helper_str_alloc("Register::read");
+				ntlog_helper_str_add(tmp_string,
+					"(Dev: NA, Bus: RAB%u, Addr: 0x%08X, Cnt: %d, Data:",
+					bus_id, address, word_cnt);
+
+				for (i = 0; i < word_cnt; i++)
+					ntlog_helper_str_add(tmp_string, " 0x%08X", p_data[i]);
+
+				ntlog_helper_str_add(tmp_string, ")");
+				NT_LOG(DBG, NTHW, "%s", tmp_string);
+				ntlog_helper_str_free(tmp_string);
+			}
+		}
+
+		/* Read completion from out buffer */
+		nthw_rac_reg_read32(p_fpga_info, p->RAC_RAB_OB_DATA_ADDR, &rab_read_oper_cmpl);
+
+		if (p->mn_param_rac_rab_ob_update)
+			nthw_rac_reg_write32(p_fpga_info, p->RAC_RAB_OB_DATA_ADDR, 0);
+
+		if (rab_read_oper_cmpl != rab_oper_cmpl) {
+			NT_LOG(ERR, NTHW,
+				"%s: RAB: Unexpected value of completion (0x%08X)- inBufFree: 0x%08X, outBufFree: 0x%08X, bufUsed: 0x%08X\n",
+				p_adapter_id_str, rab_read_oper_cmpl, in_buf_free, out_buf_free,
+				buf_used);
+			res = -1;
+			goto exit_unlock_res;
+		}
+
+		/* Read buffer free register */
+		nthw_rac_reg_read32(p_fpga_info, p->RAC_RAB_BUF_FREE_ADDR, &buf_free);
+
+		if (buf_free & 0x80000000) {
+			/* Clear Timeout and overflow bits */
+			nthw_rac_reg_write32(p_fpga_info, p->RAC_RAB_BUF_FREE_ADDR, 0x0);
+			NT_LOG(ERR, NTHW,
+				"%s: RAB: timeout - Access outside register - bus: %d addr: 0x%08X - inBufFree: 0x%08X, outBufFree: 0x%08X, bufUsed: 0x%08X\n",
+				p_adapter_id_str, bus_id, address, in_buf_free, out_buf_free,
+				buf_used);
+			res = -1;
+			goto exit_unlock_res;
+		}
+
+		res = 0;
+		goto exit_unlock_res;
+
+	} else {
+		NT_LOG(ERR, NTHW,
+			"%s: RAB: Fail rab bus buffer check - bus: %d addr: 0x%08X wordcount: %d - inBufFree: 0x%08X, outBufFree: 0x%08X, bufUsed: 0x%08X\n",
+			p_adapter_id_str, bus_id, address, word_cnt, in_buf_free, out_buf_free,
+			buf_used);
+		res = -1;
+		goto exit_unlock_res;
+	}
+
+exit_unlock_res:
+	pthread_mutex_unlock(&p->m_mutex);
+	return res;
+}
+
+int nthw_rac_rab_flush(nthw_rac_t *p)
+{
+	const struct fpga_info_s *const p_fpga_info = p->mp_fpga->p_fpga_info;
+	const char *const p_adapter_id_str = p_fpga_info->mp_adapter_id_str;
+	uint32_t data = 0;
+	uint32_t retry;
+	int res = 0;
+
+	pthread_mutex_lock(&p->m_mutex);
+
+	/* Set the flush bit */
+	nthw_rac_reg_write32(p_fpga_info, p->RAC_RAB_BUF_USED_ADDR,
+		p->RAC_RAB_BUF_USED_FLUSH_MASK);
+
+	/* Reset BUF FREE register */
+	nthw_rac_reg_write32(p_fpga_info, p->RAC_RAB_BUF_FREE_ADDR, 0x0);
+
+	/* Wait until OB_USED and IB_USED are 0 */
+	for (retry = 0; retry < 100000; retry++) {
+		nthw_rac_reg_read32(p_fpga_info, p->RAC_RAB_BUF_USED_ADDR, &data);
+
+		if ((data & 0xFFFFFFFF) == p->RAC_RAB_BUF_USED_FLUSH_MASK)
+			break;
+	}
+
+	if (data != p->RAC_RAB_BUF_USED_FLUSH_MASK) {
+		NT_LOG(ERR, NTHW, "%s: RAB: Rab bus flush error.\n", p_adapter_id_str);
+		res = -1;
+	}
+
+	/* Clear flush bit when done */
+	nthw_rac_reg_write32(p_fpga_info, p->RAC_RAB_BUF_USED_ADDR, 0x0);
+
+	pthread_mutex_unlock(&p->m_mutex);
+	return res;
+}
diff --git a/drivers/net/ntnic/nthw/nthw_rac.h b/drivers/net/ntnic/nthw/nthw_rac.h
new file mode 100644
index 0000000000..44426cb608
--- /dev/null
+++ b/drivers/net/ntnic/nthw/nthw_rac.h
@@ -0,0 +1,154 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef __NTHW_RAC_H__
+#define __NTHW_RAC_H__
+
+#include "nt_util.h"
+#include "nthw_bus.h"
+
+#define RAB_DMA_BUF_CNT (0x4000)
+
+struct nthw_rac {
+	nthw_fpga_t *mp_fpga;
+	nthw_module_t *mp_mod_rac;
+
+	pthread_mutex_t m_mutex;
+
+	int mn_param_rac_rab_interfaces;
+	int mn_param_rac_rab_ob_update;
+
+	nthw_register_t *mp_reg_dummy0;
+	nthw_register_t *mp_reg_dummy1;
+	nthw_register_t *mp_reg_dummy2;
+
+	nthw_register_t *mp_reg_rab_init;
+	nthw_field_t *mp_fld_rab_init;
+
+	int mn_fld_rab_init_bw;
+	uint32_t mn_fld_rab_init_mask;
+
+	nthw_register_t *mp_reg_dbg_ctrl;
+	nthw_field_t *mp_fld_dbg_ctrl;
+
+	nthw_register_t *mp_reg_dbg_data;
+	nthw_field_t *mp_fld_dbg_data;
+
+	nthw_register_t *mp_reg_rab_ib_data;
+	nthw_field_t *mp_fld_rab_ib_data;
+
+	nthw_register_t *mp_reg_rab_ob_data;
+	nthw_field_t *mp_fld_rab_ob_data;
+
+	nthw_register_t *mp_reg_rab_buf_free;
+	nthw_field_t *mp_fld_rab_buf_free_ib_free;
+	nthw_field_t *mp_fld_rab_buf_free_ib_ovf;
+	nthw_field_t *mp_fld_rab_buf_free_ob_free;
+	nthw_field_t *mp_fld_rab_buf_free_ob_ovf;
+	nthw_field_t *mp_fld_rab_buf_free_timeout;
+
+	nthw_register_t *mp_reg_rab_buf_used;
+	nthw_field_t *mp_fld_rab_buf_used_ib_used;
+	nthw_field_t *mp_fld_rab_buf_used_ob_used;
+	nthw_field_t *mp_fld_rab_buf_used_flush;
+
+	nthw_register_t *mp_reg_rab_dma_ib_lo;
+	nthw_field_t *mp_fld_rab_dma_ib_lo_phy_addr;
+
+	nthw_register_t *mp_reg_rab_dma_ib_hi;
+	nthw_field_t *mp_fld_rab_dma_ib_hi_phy_addr;
+
+	nthw_register_t *mp_reg_rab_dma_ob_hi;
+	nthw_field_t *mp_fld_rab_dma_ob_hi_phy_addr;
+
+	nthw_register_t *mp_reg_rab_dma_ob_lo;
+	nthw_field_t *mp_fld_rab_dma_ob_lo_phy_addr;
+
+	nthw_register_t *mp_reg_rab_dma_ib_wr;
+	nthw_field_t *mp_fld_rab_dma_ib_wr_ptr;
+
+	nthw_register_t *mp_reg_rab_dma_ib_rd;
+	nthw_field_t *mp_fld_rab_dma_ib_rd_ptr;
+
+	nthw_register_t *mp_reg_rab_dma_ob_wr;
+	nthw_field_t *mp_fld_rab_dma_ob_wr_ptr;
+
+	nthw_register_t *mp_reg_rab_nmb_rd;
+	nthw_register_t *mp_reg_rab_nmb_data;
+	nthw_register_t *mp_reg_rab_nmb_wr;
+	nthw_register_t *mp_reg_rab_nmb_status;
+
+	uint32_t RAC_RAB_INIT_ADDR;
+	uint32_t RAC_RAB_IB_DATA_ADDR;
+	uint32_t RAC_RAB_OB_DATA_ADDR;
+	uint32_t RAC_RAB_BUF_FREE_ADDR;
+	uint32_t RAC_RAB_BUF_USED_ADDR;
+
+	uint32_t RAC_RAB_DMA_IB_LO_ADDR;
+	uint32_t RAC_RAB_DMA_IB_HI_ADDR;
+	uint32_t RAC_RAB_DMA_OB_LO_ADDR;
+	uint32_t RAC_RAB_DMA_OB_HI_ADDR;
+	uint32_t RAC_RAB_DMA_IB_RD_ADDR;
+	uint32_t RAC_RAB_DMA_OB_WR_ADDR;
+	uint32_t RAC_RAB_DMA_IB_WR_ADDR;
+
+	uint32_t RAC_RAB_BUF_FREE_IB_FREE_MASK;
+	uint32_t RAC_RAB_BUF_FREE_OB_FREE_MASK;
+	uint32_t RAC_RAB_BUF_USED_IB_USED_MASK;
+	uint32_t RAC_RAB_BUF_USED_OB_USED_MASK;
+	uint32_t RAC_RAB_BUF_USED_FLUSH_MASK;
+
+	uint32_t RAC_RAB_BUF_USED_OB_USED_LOW;
+
+	uint32_t RAC_NMB_RD_ADR_ADDR;
+	uint32_t RAC_NMB_DATA_ADDR;
+	uint32_t RAC_NMB_WR_ADR_ADDR;
+	uint32_t RAC_NMB_STATUS_ADDR;
+
+	bool m_dma_active;
+
+	struct nt_dma_s *m_dma;
+
+	volatile uint32_t *m_dma_in_buf;
+	volatile uint32_t *m_dma_out_buf;
+
+	uint16_t m_dma_out_ptr_rd;
+	uint16_t m_dma_in_ptr_wr;
+	uint32_t m_in_free;
+};
+
+typedef struct nthw_rac nthw_rac_t;
+typedef struct nthw_rac nthw_rac;
+
+struct dma_buf_ptr {
+	uint32_t size;
+	uint32_t index;
+	volatile uint32_t *base;
+};
+
+nthw_rac_t *nthw_rac_new(void);
+int nthw_rac_init(nthw_rac_t *p, nthw_fpga_t *p_fpga, struct fpga_info_s *p_fpga_info);
+
+int nthw_rac_get_rab_interface_count(const nthw_rac_t *p);
+
+int nthw_rac_rab_init(nthw_rac_t *p, uint32_t n_rab_intf_mask);
+
+int nthw_rac_rab_setup(nthw_rac_t *p);
+
+int nthw_rac_rab_reset(nthw_rac_t *p);
+
+int nthw_rac_rab_write32(nthw_rac_t *p, bool trc, nthw_rab_bus_id_t bus_id, uint32_t address,
+	uint32_t word_cnt, const uint32_t *p_data);
+int nthw_rac_rab_read32(nthw_rac_t *p, bool trc, nthw_rab_bus_id_t bus_id, uint32_t address,
+	uint32_t word_cnt, uint32_t *p_data);
+
+int nthw_rac_rab_flush(nthw_rac_t *p);
+
+void nthw_rac_bar0_read32(const struct fpga_info_s *p_fpga_info, uint32_t reg_addr,
+	uint32_t word_cnt, uint32_t *p_data);
+void nthw_rac_bar0_write32(const struct fpga_info_s *p_fpga_info, uint32_t reg_addr,
+	uint32_t word_cnt, const uint32_t *p_data);
+
+#endif	/* __NTHW_RAC_H__ */
diff --git a/drivers/net/ntnic/nthw/nthw_register.h b/drivers/net/ntnic/nthw/nthw_register.h
new file mode 100644
index 0000000000..ecc661a656
--- /dev/null
+++ b/drivers/net/ntnic/nthw/nthw_register.h
@@ -0,0 +1,22 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef NTHW_REGISTER_H_
+#define NTHW_REGISTER_H_
+
+#include <unistd.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <inttypes.h>
+
+#include "nthw_fpga_model.h"
+
+#include "fpga_model.h"
+
+#include "nthw_fpga_mod_defs.h"
+#include "nthw_fpga_param_defs.h"
+#include "nthw_fpga_reg_defs.h"
+
+#endif	/* NTHW_REGISTER_H_ */
diff --git a/drivers/net/ntnic/nthw/nthw_utils.c b/drivers/net/ntnic/nthw/nthw_utils.c
new file mode 100644
index 0000000000..d06460b67c
--- /dev/null
+++ b/drivers/net/ntnic/nthw/nthw_utils.c
@@ -0,0 +1,53 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#include "ntlog.h"
+
+#include <stdint.h>
+#include <inttypes.h>
+#include <ctype.h>	/* isprint */
+#include <sys/socket.h>
+#include <netinet/in.h>
+#include <arpa/inet.h>	/* inet_addr */
+#include <string.h>	/* memset */
+
+#include "nthw_utils.h"
+#include "nthw_helper.h"
+
+int socket_loopback_setup(uint16_t port)
+{
+	int res = 0;
+	struct sockaddr_in serv_addr;
+	int sockfd;
+	int sockval;
+
+	/* socket create and verification */
+	sockfd = socket(AF_INET, SOCK_STREAM, 0);
+
+	if (sockfd == -1) {
+		NT_LOG(ERR, NTHW, "socket creation failed...\n");
+		res = -1;
+	}
+
+	setsockopt(sockfd, SOL_SOCKET, SO_REUSEPORT, &sockval, sizeof(sockval));
+
+	memset(&serv_addr, 0, sizeof(serv_addr));
+	serv_addr.sin_family = AF_INET;
+	serv_addr.sin_addr.s_addr = htonl(INADDR_LOOPBACK);
+	serv_addr.sin_port = htons(port);
+
+	if ((bind(sockfd, (struct sockaddr *)&serv_addr, sizeof(serv_addr))) != 0) {
+		NT_LOG(ERR, NTHW, "socket bind failed...\n");
+		res = -1;
+	}
+
+	/* Now server is ready to listen and verification */
+	if ((listen(sockfd, 5)) != 0) {
+		NT_LOG(ERR, NTHW, "Listen failed...\n");
+		res = -1;
+	}
+
+	return res == 0 ? sockfd : res;
+}
diff --git a/drivers/net/ntnic/nthw/nthw_utils.h b/drivers/net/ntnic/nthw/nthw_utils.h
new file mode 100644
index 0000000000..b1ac4977b3
--- /dev/null
+++ b/drivers/net/ntnic/nthw/nthw_utils.h
@@ -0,0 +1,11 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef __NTHW_UTILS_H__
+#define __NTHW_UTILS_H__
+
+int socket_loopback_setup(uint16_t port);
+
+#endif	/* __NTHW_UTILS_H__ */
-- 
2.44.0


^ permalink raw reply	[flat|nested] 238+ messages in thread

* [PATCH v1 03/17] net/ntnic: add interfaces for platform functionality
  2024-05-30 14:48 [PATCH v1 01/17] net/ntnic: Add registers for NapaTech SmartNiC Serhii Iliushyk
  2024-05-30 14:48 ` [PATCH v1 02/17] net/ntnic: add core platform functionality Serhii Iliushyk
@ 2024-05-30 14:49 ` Serhii Iliushyk
  2024-05-30 14:49 ` [PATCH v1 04/17] net/ntnic: add FPGA model implementation Serhii Iliushyk
                   ` (22 subsequent siblings)
  24 siblings, 0 replies; 238+ messages in thread
From: Serhii Iliushyk @ 2024-05-30 14:49 UTC (permalink / raw)
  To: dev; +Cc: mko-plv, ckm, andrew.rybchenko, ferruh.yigit

Add ntnic structures and prototypes for platform interfaces.

Signed-off-by: Serhii Iliushyk <sil-plv@napatech.com>
---
 .../nthw/core/include/nthw_clock_profiles.h   |  20 ++
 .../net/ntnic/nthw/core/include/nthw_core.h   |  32 +++
 .../net/ntnic/nthw/core/include/nthw_fpga.h   |  54 +++++
 .../ntnic/nthw/core/include/nthw_fpga_rst.h   |  18 ++
 .../net/ntnic/nthw/core/include/nthw_hif.h    | 152 +++++++++++++
 .../net/ntnic/nthw/core/include/nthw_igam.h   |  36 +++
 .../net/ntnic/nthw/core/include/nthw_iic.h    | 101 +++++++++
 .../nthw/core/include/nthw_mac_pcs_xxv.h      | 208 ++++++++++++++++++
 .../ntnic/nthw/core/include/nthw_mac_tfg.h    |  58 +++++
 .../net/ntnic/nthw/core/include/nthw_pcie3.h  |  99 +++++++++
 .../ntnic/nthw/core/include/nthw_phy_tile.h   | 123 +++++++++++
 .../net/ntnic/nthw/core/include/nthw_sdc.h    |  43 ++++
 .../net/ntnic/nthw/core/include/nthw_si5340.h |  33 +++
 .../net/ntnic/nthw/core/include/nthw_spi_v3.h | 105 +++++++++
 .../net/ntnic/nthw/core/include/nthw_spim.h   |  57 +++++
 .../net/ntnic/nthw/core/include/nthw_spis.h   |  62 ++++++
 .../net/ntnic/nthw/core/include/nthw_tsm.h    |  52 +++++
 17 files changed, 1253 insertions(+)
 create mode 100644 drivers/net/ntnic/nthw/core/include/nthw_clock_profiles.h
 create mode 100644 drivers/net/ntnic/nthw/core/include/nthw_core.h
 create mode 100644 drivers/net/ntnic/nthw/core/include/nthw_fpga.h
 create mode 100644 drivers/net/ntnic/nthw/core/include/nthw_fpga_rst.h
 create mode 100644 drivers/net/ntnic/nthw/core/include/nthw_hif.h
 create mode 100644 drivers/net/ntnic/nthw/core/include/nthw_igam.h
 create mode 100644 drivers/net/ntnic/nthw/core/include/nthw_iic.h
 create mode 100644 drivers/net/ntnic/nthw/core/include/nthw_mac_pcs_xxv.h
 create mode 100644 drivers/net/ntnic/nthw/core/include/nthw_mac_tfg.h
 create mode 100644 drivers/net/ntnic/nthw/core/include/nthw_pcie3.h
 create mode 100644 drivers/net/ntnic/nthw/core/include/nthw_phy_tile.h
 create mode 100644 drivers/net/ntnic/nthw/core/include/nthw_sdc.h
 create mode 100644 drivers/net/ntnic/nthw/core/include/nthw_si5340.h
 create mode 100644 drivers/net/ntnic/nthw/core/include/nthw_spi_v3.h
 create mode 100644 drivers/net/ntnic/nthw/core/include/nthw_spim.h
 create mode 100644 drivers/net/ntnic/nthw/core/include/nthw_spis.h
 create mode 100644 drivers/net/ntnic/nthw/core/include/nthw_tsm.h

diff --git a/drivers/net/ntnic/nthw/core/include/nthw_clock_profiles.h b/drivers/net/ntnic/nthw/core/include/nthw_clock_profiles.h
new file mode 100644
index 0000000000..bf8911bca2
--- /dev/null
+++ b/drivers/net/ntnic/nthw/core/include/nthw_clock_profiles.h
@@ -0,0 +1,20 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef _NTHW_CLOCK_PROFILES_H_
+#define _NTHW_CLOCK_PROFILES_H_
+
+/* TODO: figure out why static_assert(sizeof(x)...) does not work in plain C */
+#ifndef __cplusplus
+#ifndef __KERNEL__
+#include <assert.h>	/* static_assert */
+#endif	/* __KERNEL__ */
+#endif	/* __cplusplus */
+
+#include "nthw_helper.h"
+
+#include "clock_profiles_structs.h"
+
+#endif	/* _NTHW_CLOCK_PROFILES_H_ */
diff --git a/drivers/net/ntnic/nthw/core/include/nthw_core.h b/drivers/net/ntnic/nthw/core/include/nthw_core.h
new file mode 100644
index 0000000000..f2d56a41f9
--- /dev/null
+++ b/drivers/net/ntnic/nthw/core/include/nthw_core.h
@@ -0,0 +1,32 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef __NTHW_CORE_H__
+#define __NTHW_CORE_H__
+
+#include "nthw_helper.h"
+#include "nthw_utils.h"
+
+#include "nthw_platform_drv.h"
+#include "nthw_fpga_model.h"
+#include "nthw_hif.h"
+#include "nthw_pcie3.h"
+#include "nthw_iic.h"
+
+#include "nthw_mac_pcs_xxv.h"
+#include "nthw_mac_tfg.h"
+#include "nthw_sdc.h"
+
+#include "nthw_spim.h"
+#include "nthw_spis.h"
+
+#include "nthw_tsm.h"
+
+#include "nthw_si5340.h"
+
+#include "nthw_phy_tile.h"
+#include "nthw_igam.h"
+
+#endif	/* __NTHW_CORE_H__ */
diff --git a/drivers/net/ntnic/nthw/core/include/nthw_fpga.h b/drivers/net/ntnic/nthw/core/include/nthw_fpga.h
new file mode 100644
index 0000000000..ee92b674a2
--- /dev/null
+++ b/drivers/net/ntnic/nthw/core/include/nthw_fpga.h
@@ -0,0 +1,54 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef __NTHW_FPGA_H__
+#define __NTHW_FPGA_H__
+
+#include "nthw_drv.h"
+
+#include "nthw_fpga_model.h"
+
+#include "nthw_rac.h"
+#include "nthw_iic.h"
+
+#include "nthw_fpga_rst.h"
+
+int nthw_fpga_init(struct fpga_info_s *p_fpga_info);
+int nthw_fpga_shutdown(struct fpga_info_s *p_fpga_info);
+
+int nthw_fpga_get_param_info(struct fpga_info_s *p_fpga_info, nthw_fpga_t *p_fpga);
+
+int nthw_fpga_avr_probe(nthw_fpga_t *p_fpga, const int n_instance_no);
+
+int nthw_fpga_iic_scan(nthw_fpga_t *p_fpga, const int n_instance_no_begin,
+	const int n_instance_no_end);
+
+int nthw_fpga_silabs_detect(nthw_fpga_t *p_fpga, const int n_instance_no, const int n_dev_addr,
+	const int n_page_reg_addr);
+
+int nthw_fpga_si5340_clock_synth_init_fmt2(nthw_fpga_t *p_fpga, const uint8_t n_iic_addr,
+	const clk_profile_data_fmt2_t *p_clk_profile,
+	const int n_clk_profile_rec_cnt);
+
+struct nt50b0x_ops {
+	int (*nthw_fpga_nt50b0x_init)(struct fpga_info_s *p_fpga_info);
+};
+
+struct nt50b0x_ops *get_nt50b0x_ops(void);
+
+struct nt400dxx_ops {
+	int (*nthw_fpga_nt400dxx_init)(struct fpga_info_s *p_fpga_info);
+};
+
+struct nt400dxx_ops *get_nt400dxx_ops(void);
+
+struct nt200a0x_ops {
+	int (*nthw_fpga_nt200a0x_init)(struct fpga_info_s *p_fpga_info);
+};
+
+void register_nt200a0x_ops(struct nt200a0x_ops *ops);
+struct nt200a0x_ops *get_nt200a0x_ops(void);
+
+#endif	/* __NTHW_FPGA_H__ */
diff --git a/drivers/net/ntnic/nthw/core/include/nthw_fpga_rst.h b/drivers/net/ntnic/nthw/core/include/nthw_fpga_rst.h
new file mode 100644
index 0000000000..206120fa37
--- /dev/null
+++ b/drivers/net/ntnic/nthw/core/include/nthw_fpga_rst.h
@@ -0,0 +1,18 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef __NTHW_FPGA_RST_H__
+#define __NTHW_FPGA_RST_H__
+
+#include "nthw_drv.h"
+
+#include "nthw_fpga_model.h"
+
+#include "nthw_rac.h"
+#include "nthw_iic.h"
+
+#include "ntnic_nthw_fpga_rst_nt200a0x.h"
+
+#endif	/* __NTHW_FPGA_RST_H__ */
diff --git a/drivers/net/ntnic/nthw/core/include/nthw_hif.h b/drivers/net/ntnic/nthw/core/include/nthw_hif.h
new file mode 100644
index 0000000000..1e18ddfaf0
--- /dev/null
+++ b/drivers/net/ntnic/nthw/core/include/nthw_hif.h
@@ -0,0 +1,152 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef __NTHW_HIF_H__
+#define __NTHW_HIF_H__
+
+#define NTHW_TG_CNT_SIZE (4ULL)
+
+struct nthw_hif {
+	nthw_fpga_t *mp_fpga;
+	nthw_module_t *mp_mod_hif;
+	int mn_instance;
+
+	nthw_register_t *mp_reg_ctrl;
+	nthw_field_t *mp_fld_ctrl_fsr;
+
+	nthw_register_t *mp_reg_prod_id_lsb;
+	nthw_field_t *mp_fld_prod_id_lsb_rev_id;
+	nthw_field_t *mp_fld_prod_id_lsb_ver_id;
+	nthw_field_t *mp_fld_prod_id_lsb_group_id;
+
+	nthw_register_t *mp_reg_prod_id_msb;
+	nthw_field_t *mp_fld_prod_id_msb_type_id;
+	nthw_field_t *mp_fld_prod_id_msb_build_no;
+
+	nthw_register_t *mp_reg_build_time;
+	nthw_field_t *mp_fld_build_time;
+
+	nthw_register_t *mp_reg_build_seed;
+	nthw_field_t *mp_fld_build_seed;
+
+	nthw_register_t *mp_reg_core_speed;
+	nthw_field_t *mp_fld_core_speed;
+	nthw_field_t *mp_fld_ddr3_speed;
+
+	nthw_register_t *mp_reg_int_mask;
+	nthw_field_t *mp_fld_int_mask_timer;
+	nthw_field_t *mp_fld_int_mask_port;
+	nthw_field_t *mp_fld_int_mask_pps;
+
+	nthw_register_t *mp_reg_int_clr;
+	nthw_field_t *mp_fld_int_clr_timer;
+	nthw_field_t *mp_fld_int_clr_port;
+	nthw_field_t *mp_fld_int_clr_pps;
+
+	nthw_register_t *mp_reg_int_force;
+	nthw_field_t *mp_fld_int_force_timer;
+	nthw_field_t *mp_fld_int_force_port;
+	nthw_field_t *mp_fld_int_force_pps;
+
+	nthw_register_t *mp_reg_sample_time;
+	nthw_field_t *mp_fld_sample_time;
+
+	nthw_register_t *mp_reg_status;
+	nthw_field_t *mp_fld_status_tags_in_use;
+	nthw_field_t *mp_fld_status_wr_err;
+	nthw_field_t *mp_fld_status_rd_err;
+
+	nthw_register_t *mp_reg_stat_ctrl;
+	nthw_field_t *mp_fld_stat_ctrl_ena;
+	nthw_field_t *mp_fld_stat_ctrl_req;
+
+	nthw_register_t *mp_reg_stat_rx;
+	nthw_field_t *mp_fld_stat_rx_counter;
+
+	nthw_register_t *mp_reg_stat_tx;
+	nthw_field_t *mp_fld_stat_tx_counter;
+
+	nthw_register_t *mp_reg_stat_ref_clk;
+	nthw_field_t *mp_fld_stat_ref_clk_ref_clk;
+
+	nthw_register_t *mp_reg_pci_test0;
+	nthw_field_t *mp_fld_pci_test0;
+
+	nthw_register_t *mp_reg_pci_test1;
+	nthw_field_t *mp_fld_pci_test1;
+
+	nthw_register_t *mp_reg_pci_test2;
+	nthw_field_t *mp_fld_pci_test2;
+
+	nthw_register_t *mp_reg_pci_test3;
+	nthw_field_t *mp_fld_pci_test3;
+
+	nthw_register_t *mp_reg_config;
+	nthw_field_t *mp_fld_max_tlp;
+	nthw_field_t *mp_fld_max_read;
+	nthw_field_t *mp_fld_ext_tag;
+
+	int mn_fpga_id_item;
+	int mn_fpga_id_prod;
+	int mn_fpga_id_ver;
+	int mn_fpga_id_rev;
+	int mn_fpga_id_build_no;
+
+	int mn_fpga_param_hif_per_ps;
+	uint32_t mn_fpga_hif_ref_clk_freq;
+};
+
+typedef struct nthw_hif nthw_hif_t;
+typedef struct nthw_hif nthw_hif;
+
+struct nthw_hif_end_point_err_counters {
+	uint32_t n_err_correctable, n_err_non_fatal, n_err_fatal;
+};
+
+struct nthw_hif_end_point_counters {
+	int n_numa_node;
+
+	int n_tg_direction;
+	int n_tg_pkt_size;
+	int n_tg_num_pkts;
+	int n_tg_delay;
+
+	uint64_t cur_rx, cur_tx;
+	uint64_t cur_pci_nt_util, cur_pci_xil_util;
+	uint64_t n_ref_clk_cnt;
+
+	uint64_t n_tags_in_use;
+	uint64_t n_rd_err;
+	uint64_t n_wr_err;
+
+	struct nthw_hif_end_point_err_counters s_rc_ep_pre, s_rc_ep_post, s_rc_ep_delta;
+	struct nthw_hif_end_point_err_counters s_ep_rc_pre, s_ep_rc_post, s_ep_rc_delta;
+
+	int bo_error;
+};
+
+struct nthw_hif_end_points {
+	struct nthw_hif_end_point_counters pri, sla;
+};
+
+nthw_hif_t *nthw_hif_new(void);
+void nthw_hif_delete(nthw_hif_t *p);
+int nthw_hif_init(nthw_hif_t *p, nthw_fpga_t *p_fpga, int n_instance);
+
+int nthw_hif_trigger_sample_time(nthw_hif_t *p);
+
+int nthw_hif_stat_req_enable(nthw_hif_t *p);
+int nthw_hif_stat_req_disable(nthw_hif_t *p);
+
+int nthw_hif_get_stat(nthw_hif_t *p, uint32_t *p_rx_cnt, uint32_t *p_tx_cnt,
+	uint32_t *p_ref_clk_cnt, uint32_t *p_tg_unit_size, uint32_t *p_tg_ref_freq,
+	uint64_t *p_tags_in_use, uint64_t *p_rd_err, uint64_t *p_wr_err);
+int nthw_hif_get_stat_rate(nthw_hif_t *p, uint64_t *p_pci_rx_rate, uint64_t *p_pci_tx_rate,
+	uint64_t *p_ref_clk_cnt, uint64_t *p_tags_in_use,
+	uint64_t *p_rd_err_cnt, uint64_t *p_wr_err_cnt);
+
+int nthw_hif_end_point_counters_sample(nthw_hif_t *p, struct nthw_hif_end_point_counters *epc);
+
+#endif	/* __NTHW_HIF_H__ */
diff --git a/drivers/net/ntnic/nthw/core/include/nthw_igam.h b/drivers/net/ntnic/nthw/core/include/nthw_igam.h
new file mode 100644
index 0000000000..05c09cc89a
--- /dev/null
+++ b/drivers/net/ntnic/nthw/core/include/nthw_igam.h
@@ -0,0 +1,36 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef __NTHW_IGAM_H__
+#define __NTHW_IGAM_H__
+
+#include "nthw_fpga_model.h"
+
+struct nt_igam {
+	nthw_fpga_t *mp_fpga;
+
+	nthw_module_t *mp_mod_igam;
+
+	int mn_igam_instance;
+
+	nthw_register_t *mp_reg_base;
+	nthw_field_t *mp_fld_base_ptr;
+	nthw_field_t *mp_fld_base_busy;
+	nthw_field_t *mp_fld_base_cmd;
+
+	nthw_register_t *mp_reg_data;
+	nthw_field_t *mp_fld_data_data;
+};
+
+typedef struct nt_igam nthw_igam_t;
+typedef struct nt_igam nthw_igam;
+
+nthw_igam_t *nthw_igam_new(void);
+void nthw_igam_delete(nthw_igam_t *p);
+int nthw_igam_init(nthw_igam_t *p, nthw_fpga_t *p_fpga, int mn_igam_instance);
+uint32_t nthw_igam_read(nthw_igam_t *p, uint32_t address);
+void nthw_igam_write(nthw_igam_t *p, uint32_t address, uint32_t data);
+
+#endif	/*  __NTHW_IGAM_H__ */
diff --git a/drivers/net/ntnic/nthw/core/include/nthw_iic.h b/drivers/net/ntnic/nthw/core/include/nthw_iic.h
new file mode 100644
index 0000000000..5193696455
--- /dev/null
+++ b/drivers/net/ntnic/nthw/core/include/nthw_iic.h
@@ -0,0 +1,101 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef __NTHW_IIC_H__
+#define __NTHW_IIC_H__
+
+#include "nthw_fpga_model.h"
+
+struct nthw_iic {
+	nthw_fpga_t *mp_fpga;
+	nthw_module_t *mp_mod_iic;
+	int mn_iic_instance;
+
+	uint32_t mn_iic_cycle_time;
+	int mn_poll_delay;
+	int mn_bus_ready_retry;
+	int mn_data_ready_retry;
+	int mn_read_data_retry;
+	int mn_write_data_retry;
+
+	nthw_register_t *mp_reg_tsusta;
+	nthw_field_t *mp_fld_tsusta;
+
+	nthw_register_t *mp_reg_tsusto;
+	nthw_field_t *mp_fld_tsusto;
+
+	nthw_register_t *mp_reg_thdsta;
+	nthw_field_t *mp_fld_thdsta;
+
+	nthw_register_t *mp_reg_tsudat;
+	nthw_field_t *mp_fld_tsudat;
+
+	nthw_register_t *mp_reg_tbuf;
+	nthw_field_t *mp_fld_tbuf;
+
+	nthw_register_t *mp_reg_thigh;
+	nthw_field_t *mp_fld_thigh;
+
+	nthw_register_t *mp_reg_tlow;
+	nthw_field_t *mp_fld_tlow;
+
+	nthw_register_t *mp_reg_thddat;
+	nthw_field_t *mp_fld_thddat;
+
+	nthw_register_t *mp_reg_cr;
+	nthw_field_t *mp_fld_cr_en;
+	nthw_field_t *mp_fld_cr_msms;
+	nthw_field_t *mp_fld_cr_txfifo_reset;
+	nthw_field_t *mp_fld_cr_txak;
+
+	nthw_register_t *mp_reg_sr;
+	nthw_field_t *mp_fld_sr_bb;
+	nthw_field_t *mp_fld_sr_rxfifo_full;
+	nthw_field_t *mp_fld_sr_rxfifo_empty;
+	nthw_field_t *mp_fld_sr_txfifo_full;
+	nthw_field_t *mp_fld_sr_txfifo_empty;
+
+	nthw_register_t *mp_reg_tx_fifo;
+	nthw_field_t *mp_fld_tx_fifo_txdata;
+	nthw_field_t *mp_fld_tx_fifo_start;
+	nthw_field_t *mp_fld_tx_fifo_stop;
+
+	nthw_register_t *mp_reg_rx_fifo_pirq;
+	nthw_field_t *mp_fld_rx_fifo_pirq_cmp_val;
+
+	nthw_register_t *mp_reg_rx_fifo;
+	nthw_field_t *mp_fld_rx_fifo_rxdata;
+
+	nthw_register_t *mp_reg_softr;
+	nthw_field_t *mp_fld_softr_rkey;
+};
+
+typedef struct nthw_iic nthw_iic_t;
+typedef struct nthw_iic nthw_iic;
+
+nthw_iic_t *nthw_iic_new(void);
+int nthw_iic_init(nthw_iic_t *p, nthw_fpga_t *p_fpga, int n_iic_instance,
+	uint32_t n_iic_cycle_time);
+void nthw_iic_delete(nthw_iic_t *p);
+
+int nthw_iic_set_retry_params(nthw_iic_t *p, const int n_poll_delay, const int n_bus_ready_retry,
+	const int n_data_ready_retry, const int n_read_data_retry,
+	const int n_write_data_retry);
+
+int nthw_iic_read_data(nthw_iic_t *p, uint8_t dev_addr, uint8_t a_reg_addr, uint8_t data_len,
+	void *p_void);
+int nthw_iic_readbyte(nthw_iic_t *p, uint8_t dev_addr, uint8_t a_reg_addr, uint8_t data_len,
+	uint8_t *p_byte);
+int nthw_iic_write_data(nthw_iic_t *p, uint8_t dev_addr, uint8_t a_reg_addr, uint8_t data_len,
+	void *p_void);
+int nthw_iic_writebyte(nthw_iic_t *p, uint8_t dev_addr, uint8_t a_reg_addr, uint8_t data_len,
+	uint8_t *p_byte);
+bool nthw_iic_bus_ready(nthw_iic_t *p);
+bool nthw_iic_data_ready(nthw_iic_t *p);
+
+int nthw_iic_scan(nthw_iic_t *p);
+int nthw_iic_scan_dev_addr(nthw_iic_t *p, int n_dev_addr, int n_reg_addr);
+
+#endif	/* __NTHW_IIC_H__ */
diff --git a/drivers/net/ntnic/nthw/core/include/nthw_mac_pcs_xxv.h b/drivers/net/ntnic/nthw/core/include/nthw_mac_pcs_xxv.h
new file mode 100644
index 0000000000..4537decf12
--- /dev/null
+++ b/drivers/net/ntnic/nthw/core/include/nthw_mac_pcs_xxv.h
@@ -0,0 +1,208 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef NTHW_MAC_PCS_XXV_H_
+#define NTHW_MAC_PCS_XXV_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "nthw_fpga_model.h"
+
+enum nthw_mac_pcs_xxv_led_mode_e {
+	NTHW_MAC_PCS_XXV_LED_AUTO = 0x00,
+	NTHW_MAC_PCS_XXV_LED_ON = 0x01,
+	NTHW_MAC_PCS_XXV_LED_OFF = 0x02,
+	NTHW_MAC_PCS_XXV_LED_PORTID = 0x03,
+};
+
+enum nthw_mac_pcs_xxv_dac_mode_e {
+	NTHW_MAC_PCS_XXV_DAC_OFF = 0x00,
+	NTHW_MAC_PCS_XXV_DAC_CA_25G_N = 0x01,
+	NTHW_MAC_PCS_XXV_DAC_CA_25G_S = 0x02,
+	NTHW_MAC_PCS_XXV_DAC_CA_25G_L = 0x03,
+};
+
+struct nthw_mac_pcs_xxv {
+	nthw_fpga_t *mp_fpga;
+	nthw_module_t *mp_mod_mac_pcs_xxv;
+	int mn_instance;
+
+	uint8_t m_port_no;
+	bool m_mac_8x10G;
+
+#define NTHW_MAC_PCS_XXV_NUM_ELEMS 4
+	struct nthw_mac_pcs_xxv_registers_fields {
+		/* CORE_CONF */
+		nthw_register_t *mp_reg_core_conf;
+		nthw_field_t *mp_fld_core_conf_rx_enable;
+		nthw_field_t *mp_fld_core_conf_rx_force_resync;
+		nthw_field_t *mp_fld_core_conf_tx_enable;
+		nthw_field_t *mp_fld_core_conf_tx_ins_fcs;
+		nthw_field_t *mp_fld_core_conf_tx_ign_fcs;
+		nthw_field_t *mp_fld_core_conf_tx_send_lfi;
+		nthw_field_t *mp_fld_core_conf_tx_send_rfi;
+		nthw_field_t *mp_fld_core_conf_tx_send_idle;
+		nthw_field_t *mp_fld_core_conf_inline_mode;
+		nthw_field_t *mp_fld_core_conf_line_loopback;
+		nthw_field_t *mp_fld_core_conf_ts_at_eop;
+
+		/* ANEG_CONFIG */
+		nthw_register_t *mp_reg_aneg_config;
+		nthw_field_t *mp_fld_aneg_config_enable;
+		nthw_field_t *mp_fld_aneg_config_bypass;
+		nthw_field_t *mp_fld_aneg_config_restart;
+		nthw_field_t *mp_fld_aneg_config_pseudo;
+		nthw_field_t *mp_fld_aneg_config_nonce_seed;
+		nthw_field_t *mp_fld_aneg_config_remote_fault;
+		nthw_field_t *mp_fld_aneg_config_pause;
+		nthw_field_t *mp_fld_aneg_config_asmdir;
+		nthw_field_t *mp_fld_aneg_config_fec74_request10g;
+		nthw_field_t *mp_fld_aneg_config_hide_fec74;
+		nthw_field_t *mp_fld_aneg_config_fec74_request;
+		nthw_field_t *mp_fld_aneg_config_fec91_request;
+		nthw_field_t *mp_fld_aneg_config_fec91_ability;
+		nthw_field_t *mp_fld_aneg_config_rs_fec_request;
+		nthw_field_t *mp_fld_aneg_config_sw_fec_overwrite;
+		nthw_field_t *mp_fld_aneg_config_sw_speed_overwrite;
+
+		/* ANEG_ABILITY */
+		nthw_register_t *mp_reg_aneg_ability;
+		nthw_field_t *mp_fld_aneg_ability_25g_base_cr;
+		nthw_field_t *mp_fld_aneg_ability_25g_base_crs;
+		nthw_field_t *mp_fld_aneg_ability_25g_base_cr1;
+
+		/* LT_CONF */
+		nthw_register_t *mp_reg_lt_conf;
+		nthw_field_t *mp_fld_lt_conf_enable;
+		nthw_field_t *mp_fld_lt_conf_restart;
+		nthw_field_t *mp_fld_lt_conf_seed;
+
+		/* SUB_RST */
+		nthw_register_t *mp_reg_sub_rst;
+		nthw_field_t *mp_fld_sub_rst_rx_mac_pcs;
+		nthw_field_t *mp_fld_sub_rst_tx_mac_pcs;
+		nthw_field_t *mp_fld_sub_rst_rx_gt_data;
+		nthw_field_t *mp_fld_sub_rst_tx_gt_data;
+		nthw_field_t *mp_fld_sub_rst_rx_buf;
+		nthw_field_t *mp_fld_sub_rst_rx_pma;
+		nthw_field_t *mp_fld_sub_rst_tx_pma;
+		nthw_field_t *mp_fld_sub_rst_rx_pcs;
+		nthw_field_t *mp_fld_sub_rst_tx_pcs;
+		nthw_field_t *mp_fld_sub_rst_an_lt;
+		nthw_field_t *mp_fld_sub_rst_speed_ctrl;
+
+		/* SUB_RST_STATUS */
+		nthw_register_t *mp_reg_sub_rst_status;
+		nthw_field_t *mp_fld_sub_rst_status_user_rx_rst;
+		nthw_field_t *mp_fld_sub_rst_status_user_tx_rst;
+		nthw_field_t *mp_fld_sub_rst_status_qpll_lock;
+
+		/* LINK_SUMMARY */
+		nthw_register_t *mp_reg_link_summary;
+		nthw_field_t *mp_fld_link_summary_nt_phy_link_state;
+		nthw_field_t *mp_fld_link_summary_ll_nt_phy_link_state;
+		nthw_field_t *mp_fld_link_summary_abs;
+		nthw_field_t *mp_fld_link_summary_lh_abs;
+		nthw_field_t *mp_fld_link_summary_link_down_cnt;
+		/* Begin 2 x 10/25 Gbps only fields: */
+		nthw_field_t *mp_fld_link_summary_ll_rx_fec74_lock;
+		nthw_field_t *mp_fld_link_summary_lh_rx_rsfec_hi_ser;
+		nthw_field_t *mp_fld_link_summary_ll_rx_rsfec_lane_alignment;
+		nthw_field_t *mp_fld_link_summary_ll_tx_rsfec_lane_alignment;
+		nthw_field_t *mp_fld_link_summary_lh_rx_pcs_valid_ctrl_code;
+		/* End 2 x 10/25 Gbps only fields. */
+		nthw_field_t *mp_fld_link_summary_ll_rx_block_lock;
+		nthw_field_t *mp_fld_link_summary_lh_rx_high_bit_error_rate;
+		nthw_field_t *mp_fld_link_summary_lh_internal_local_fault;
+		nthw_field_t *mp_fld_link_summary_lh_received_local_fault;
+		nthw_field_t *mp_fld_link_summary_lh_local_fault;
+		nthw_field_t *mp_fld_link_summary_lh_remote_fault;
+		nthw_field_t *mp_fld_link_summary_lh_tx_local_fault;
+		nthw_field_t *mp_fld_link_summary_nim_interr;
+
+		/* GTY_LOOP */
+		nthw_register_t *mp_reg_gty_loop;
+		nthw_field_t *mp_fld_gty_loop_gt_loop;
+
+		/* GTY_CTL_RX */
+		nthw_register_t *mp_reg_gty_ctl_rx;
+		nthw_field_t *mp_fld_gty_ctl_rx_polarity;
+		nthw_field_t *mp_fld_gty_ctl_rx_lpm_en;
+		nthw_field_t *mp_fld_gty_ctl_rx_equa_rst;
+
+		/* GTY_CTL_TX */
+		nthw_register_t *mp_reg_gty_ctl_tx;
+		nthw_field_t *mp_fld_gty_ctl_tx_polarity;
+		nthw_field_t *mp_fld_gty_ctl_tx_inhibit;
+
+		/* LINK_SPEED */
+		nthw_register_t *mp_reg_link_speed;
+		nthw_field_t *mp_fld_link_speed_10g;
+		nthw_field_t *mp_fld_link_speed_toggle;
+
+		/* RS_FEC_CONF */
+		nthw_register_t *mp_reg_rs_fec_conf;
+		nthw_field_t *mp_fld_rs_fec_conf_rs_fec_enable;
+
+		/* DEBOUNCE_CTRL */
+		nthw_register_t *mp_reg_debounce_ctrl;
+		nthw_field_t *mp_field_debounce_ctrl_nt_port_ctrl;
+
+		/* FEC_CCW_CNT */
+		nthw_register_t *mp_reg_rs_fec_ccw;
+		nthw_field_t *mp_field_reg_rs_fec_ccw_reg_rs_fec_ccw_cnt;
+
+		/* FEC_UCW_CNT */
+		nthw_register_t *mp_reg_rs_fec_ucw;
+		nthw_field_t *mp_field_reg_rs_fec_ucw_reg_rs_fec_ucw_cnt;
+
+		/* TIMESTAMP_COMP */
+		nthw_register_t *mp_reg_timestamp_comp;
+		nthw_field_t *mp_field_timestamp_comp_rx_dly;
+		nthw_field_t *mp_field_timestamp_comp_tx_dly;
+
+		/* GTY_PRE_CURSOR */
+		nthw_register_t *mp_reg_gty_pre_cursor;
+		nthw_field_t *mp_field_gty_pre_cursor_tx_pre_csr;
+
+		/* GTY_DIFF_CTL */
+		nthw_register_t *mp_reg_gty_diff_ctl;
+		nthw_field_t *mp_field_gty_gty_diff_ctl_tx_diff_ctl;
+
+		/* GTY_POST_CURSOR */
+		nthw_register_t *mp_reg_gty_post_cursor;
+		nthw_field_t *mp_field_gty_post_cursor_tx_post_csr;
+	} regs[NTHW_MAC_PCS_XXV_NUM_ELEMS];
+};
+
+typedef struct nthw_mac_pcs_xxv nthw_mac_pcs_xxv_t;
+typedef struct nthw_mac_pcs_xxv nthw_mac_pcs_xxv;
+
+nthw_mac_pcs_xxv_t *nthw_mac_pcs_xxv_new(void);
+void nthw_mac_pcs_xxv_delete(nthw_mac_pcs_xxv_t *p);
+int nthw_mac_pcs_xxv_init(nthw_mac_pcs_xxv_t *p,
+	nthw_fpga_t *p_fpga,
+	int n_instance,
+	int n_channels,
+	bool mac_8x10G);
+
+void nthw_mac_pcs_xxv_get_link_summary(nthw_mac_pcs_xxv_t *p,
+	uint32_t *p_abs,
+	uint32_t *p_nt_phy_link_state,
+	uint32_t *p_lh_abs,
+	uint32_t *p_ll_nt_phy_link_state,
+	uint32_t *p_link_down_cnt,
+	uint32_t *p_nim_interr,
+	uint32_t *p_lh_local_fault,
+	uint32_t *p_lh_remote_fault,
+	uint32_t *p_lh_internal_local_fault,
+	uint32_t *p_lh_received_local_fault,
+	uint8_t index);
+
+void nthw_mac_pcs_xxv_reset_rx_gt_data(nthw_mac_pcs_xxv_t *p, bool enable, uint8_t index);
+
+void nthw_mac_pcs_xxv_set_rx_mac_pcs_rst(nthw_mac_pcs_xxv_t *p, bool enable, uint8_t index);
+
+#endif	/* NTHW_MAC_PCS_XXV_H_ */
diff --git a/drivers/net/ntnic/nthw/core/include/nthw_mac_tfg.h b/drivers/net/ntnic/nthw/core/include/nthw_mac_tfg.h
new file mode 100644
index 0000000000..6caf47b378
--- /dev/null
+++ b/drivers/net/ntnic/nthw/core/include/nthw_mac_tfg.h
@@ -0,0 +1,58 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef NTHW_MAC_TFG_H_
+#define NTHW_MAC_TFG_H_
+
+struct nthw_mac_tfg {
+	nthw_fpga_t *mp_fpga;
+	nthw_module_t *mp_mod_mac_tfg;
+	int mn_instance;
+
+	/* Params */
+	int mn_ifg_speed_mul;
+	int mn_ifg_speed_div;
+
+	/* TFG */
+	nthw_register_t *mp_reg_tfg_data;
+	nthw_register_t *mp_reg_tfg_addr;
+	nthw_register_t *mp_reg_tfg_ctrl;
+	nthw_register_t *mp_reg_tfg_repetition;
+
+	/* TFG ADDR */
+	nthw_field_t *mp_fld_tfg_addr_write_ram_adr;
+	nthw_field_t *mp_fld_tfg_addr_read_enable;
+	nthw_field_t *mp_fld_tfg_addr_read_done;
+
+	/* TFG DATA */
+	nthw_field_t *mp_fld_tfg_data_length;
+	nthw_field_t *mp_fld_tfg_data_gap;
+	nthw_field_t *mp_fld_tfg_data_id;
+
+	/* TFG CTRL */
+	nthw_field_t *mp_fld_tfg_wrap;
+	nthw_field_t *mp_fld_tfg_restart;
+	nthw_field_t *mp_fld_tfg_enable;
+	nthw_field_t *mp_fld_tfg_time_mode;
+	nthw_field_t *mp_fld_tfg_id_pos;
+	nthw_field_t *mp_fld_tfg_id_ena;
+	nthw_field_t *mp_fld_tfg_tx_active;
+
+	/* TFG REPETITION */
+	nthw_field_t *mp_fld_tfg_repetition_count;
+};
+
+typedef struct nthw_mac_tfg nthw_mac_tfg_t;
+typedef struct nthw_mac_tfg nthw_mac_tfg;
+
+nthw_mac_tfg_t *nthw_mac_tfg_new(void);
+void nthw_mac_tfg_delete(nthw_mac_tfg_t *p);
+int nthw_mac_tfg_init(nthw_mac_tfg_t *p, nthw_fpga_t *p_fpga, int n_instance);
+
+void nthw_mac_tfg_tfg_tx_start(nthw_mac_tfg_t *p, uint32_t repetition, uint32_t size,
+	uint32_t pkt_gap);
+void nthw_mac_tfg_tfg_tx_stop(nthw_mac_tfg_t *p);
+
+#endif	/* NTHW_MAC_TFG_H_ */
diff --git a/drivers/net/ntnic/nthw/core/include/nthw_pcie3.h b/drivers/net/ntnic/nthw/core/include/nthw_pcie3.h
new file mode 100644
index 0000000000..32a18793bc
--- /dev/null
+++ b/drivers/net/ntnic/nthw/core/include/nthw_pcie3.h
@@ -0,0 +1,99 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef __NTHW_PCIE3_H__
+#define __NTHW_PCIE3_H__
+
+struct nthw_pcie3 {
+	nthw_fpga_t *mp_fpga;
+	nthw_module_t *mp_mod_pcie3;
+	int mn_instance;
+
+	nthw_register_t *mp_reg_stat_ctrl;
+	nthw_field_t *mp_fld_stat_ctrl_req;
+	nthw_field_t *mp_fld_stat_ctrl_ena;
+
+	nthw_register_t *mp_reg_stat_rx;
+	nthw_field_t *mp_fld_stat_rx_counter;
+
+	nthw_register_t *mp_reg_stat_tx;
+	nthw_field_t *mp_fld_stat_tx_counter;
+
+	nthw_register_t *mp_reg_stat_rq_rdy;
+	nthw_field_t *mp_fld_stat_rq_rdy_counter;
+
+	nthw_register_t *mp_reg_stat_rq_vld;
+	nthw_field_t *mp_fld_stat_rq_vld_counter;
+
+	nthw_register_t *mp_reg_status0;
+	nthw_field_t *mp_fld_status0_tags_in_use;
+
+	nthw_register_t *mp_reg_stat_ref_clk;
+	nthw_field_t *mp_fld_stat_ref_clk_ref_clk;
+
+	nthw_register_t *mp_reg_rp_to_ep_err;
+	nthw_field_t *mp_fld_rp_to_ep_err_cor;
+	nthw_field_t *mp_fld_rp_to_ep_err_non_fatal;
+	nthw_field_t *mp_fld_rp_to_ep_err_fatal;
+
+	nthw_register_t *mp_reg_ep_to_rp_err;
+	nthw_field_t *mp_fld_ep_to_rp_err_cor;
+	nthw_field_t *mp_fld_ep_to_rp_err_non_fatal;
+	nthw_field_t *mp_fld_ep_to_rp_err_fatal;
+
+	nthw_register_t *mp_reg_sample_time;
+	nthw_field_t *mp_fld_sample_time;
+
+	nthw_register_t *mp_reg_pci_end_point;
+	nthw_field_t *mp_fld_pci_end_point_if_id;
+	nthw_field_t *mp_fld_pci_end_point_send_msg;
+	nthw_field_t *mp_fld_pci_end_point_get_msg;
+	nthw_field_t *mp_fld_pci_end_point_dmaep0_allow_mask;
+	nthw_field_t *mp_fld_pci_end_point_dmaep1_allow_mask;
+
+	nthw_register_t *mp_reg_pci_e3_mark_adr_lsb;
+	nthw_field_t *mp_fld_pci_e3_mark_adr_lsb_adr;
+
+	nthw_register_t *mp_reg_pci_e3_mark_adr_msb;
+	nthw_field_t *mp_fld_pci_e3_mark_adr_msb_adr;
+
+	nthw_register_t *mp_reg_pci_test0;
+	nthw_field_t *mp_fld_pci_test0;
+
+	nthw_register_t *mp_reg_pci_test1;
+	nthw_field_t *mp_fld_pci_test1;
+
+	nthw_register_t *mp_reg_pci_test2;
+	nthw_field_t *mp_fld_pci_test2;
+
+	nthw_register_t *mp_reg_pci_test3;
+	nthw_field_t *mp_fld_pci_test3;
+};
+
+typedef struct nthw_pcie3 nthw_pcie3_t;
+typedef struct nthw_pcie3 nthw_pcie3;
+
+nthw_pcie3_t *nthw_pcie3_new(void);
+void nthw_pcie3_delete(nthw_pcie3_t *p);
+int nthw_pcie3_init(nthw_pcie3_t *p, nthw_fpga_t *p_fpga, int n_instance);
+
+int nthw_pcie3_trigger_sample_time(nthw_pcie3_t *p);
+
+int nthw_pcie3_stat_req_enable(nthw_pcie3_t *p);
+int nthw_pcie3_stat_req_disable(nthw_pcie3_t *p);
+
+int nthw_pcie3_get_stat(nthw_pcie3_t *p, uint32_t *p_rx_cnt, uint32_t *p_tx_cnt,
+	uint32_t *p_ref_clk_cnt, uint32_t *p_tg_unit_size, uint32_t *p_tg_ref_freq,
+	uint32_t *p_tag_use_cnt, uint32_t *p_rq_rdy_cnt, uint32_t *p_rq_vld_cnt);
+int nthw_pcie3_get_stat_rate(nthw_pcie3_t *p, uint64_t *p_pci_rx_rate, uint64_t *p_pci_tx_rate,
+	uint64_t *p_ref_clk_cnt, uint64_t *p_tag_use_cnt,
+	uint64_t *p_pci_nt_bus_util, uint64_t *p_pci_xil_bus_util);
+
+int nthw_pcie3_end_point_counters_sample_pre(nthw_pcie3_t *p,
+	struct nthw_hif_end_point_counters *epc);
+int nthw_pcie3_end_point_counters_sample_post(nthw_pcie3_t *p,
+	struct nthw_hif_end_point_counters *epc);
+
+#endif	/* __NTHW_PCIE3_H__ */
diff --git a/drivers/net/ntnic/nthw/core/include/nthw_phy_tile.h b/drivers/net/ntnic/nthw/core/include/nthw_phy_tile.h
new file mode 100644
index 0000000000..86cacda85f
--- /dev/null
+++ b/drivers/net/ntnic/nthw/core/include/nthw_phy_tile.h
@@ -0,0 +1,123 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef __NTHW_PHY_TILE_H__
+#define __NTHW_PHY_TILE_H__
+
+#include "nthw_fpga_model.h"
+
+struct nt_phy_tile {
+	nthw_fpga_t *mp_fpga;
+
+	nthw_module_t *m_mod_phy_tile;
+
+	int mn_phy_tile_instance;
+
+	nthw_register_t *mp_reg_port_xcvr_base[2][4];
+	nthw_field_t *mp_fld_port_xcvr_base_ptr[2][4];
+	nthw_field_t *mp_fld_port_xcvr_base_busy[2][4];
+	nthw_field_t *mp_fld_port_xcvr_base_cmd[2][4];
+
+	nthw_register_t *mp_reg_port_xcvr_data[2][4];
+	nthw_field_t *mp_fld_port_xcvr_data_data[2][4];
+
+	nthw_register_t *mp_reg_port_eth_base[2][4];
+	nthw_field_t *mp_fld_port_eth_base_ptr[2][4];
+	nthw_field_t *mp_fld_port_eth_base_busy[2][4];
+	nthw_field_t *mp_fld_port_eth_base_cmd[2][4];
+
+	nthw_register_t *mp_reg_port_eth_data[2][4];
+	nthw_field_t *mp_fld_port_eth_data_data[2][4];
+
+	nthw_register_t *mp_reg_link_summary[2];
+	nthw_field_t *mp_fld_link_summary_nt_phy_link_state[2];
+	nthw_field_t *mp_fld_link_summary_ll_nt_phy_link_state[2];
+	nthw_field_t *mp_fld_link_summary_link_down_cnt[2];
+	nthw_field_t *mp_fld_link_summary_ll_rx_block_lock[2];
+	nthw_field_t *mp_fld_link_summary_ll_rx_am_lock[2];
+	nthw_field_t *mp_fld_link_summary_lh_rx_high_bit_error_rate[2];
+	nthw_field_t *mp_fld_link_summary_lh_received_local_fault[2];
+	nthw_field_t *mp_fld_link_summary_lh_remote_fault[2];
+
+	nthw_register_t *mp_reg_port_status;
+	nthw_field_t *mp_fld_port_status_rx_pcs_fully_aligned[2];
+	nthw_field_t *mp_fld_port_status_rx_hi_ber[2];
+	nthw_field_t *mp_fld_port_status_rx_remote_fault[2];
+	nthw_field_t *mp_fld_port_status_rx_local_fault[2];
+	nthw_field_t *mp_fld_port_status_rx_am_lock[2];
+
+	nthw_register_t *mp_reg_port_config;
+	nthw_field_t *mp_fld_port_config_dyn_reset;
+	nthw_field_t *mp_fld_port_config_reset[2];
+	nthw_field_t *mp_fld_port_config_rx_reset[2];
+	nthw_field_t *mp_fld_port_config_tx_reset[2];
+
+	nthw_register_t *mp_reg_port_comp[2];
+	nthw_field_t *mp_fld_port_comp_rx_compensation[2];
+	nthw_field_t *mp_fld_port_comp_tx_compensation[2];
+
+	nthw_register_t *mp_reg_dyn_reconfig_base;
+	nthw_field_t *mp_fld_dyn_reconfig_base_ptr;
+	nthw_field_t *mp_fld_dyn_reconfig_base_busy;
+	nthw_field_t *mp_fld_dyn_reconfig_base_cmd;
+
+	nthw_register_t *mp_reg_dyn_reconfig_data;
+	nthw_field_t *mp_fld_dyn_reconfig_data_data;
+
+	nthw_register_t *mp_reg_scratch;
+	nthw_field_t *mp_fld_scratch_data;
+
+	nthw_register_t *mp_reg_dr_cfg_status;
+	nthw_field_t *mp_fld_dr_cfg_status_curr_profile_id;
+	nthw_field_t *mp_fld_dr_cfg_status_in_progress;
+	nthw_field_t *mp_fld_dr_cfg_status_error;
+};
+
+typedef struct nt_phy_tile nthw_phy_tile_t;
+typedef struct nt_phy_tile nt_phy_tile;
+
+nthw_phy_tile_t *nthw_phy_tile_new(void);
+void nthw_phy_tile_delete(nthw_phy_tile_t *p);
+int nthw_phy_tile_init(nthw_phy_tile_t *p, nthw_fpga_t *p_fpga, int mn_phy_tile_instance);
+uint32_t nthw_phy_tile_get_tx_pol_inv(nthw_phy_tile_t *p, uint8_t intf_no, uint8_t lane);
+uint32_t nthw_phy_tile_get_rx_pol_inv(nthw_phy_tile_t *p, uint8_t intf_no, uint8_t lane);
+void nthw_phy_tile_set_tx_pol_inv(nthw_phy_tile_t *p, uint8_t intf_no, uint8_t lane, bool invert);
+void nthw_phy_tile_set_rx_pol_inv(nthw_phy_tile_t *p, uint8_t intf_no, uint8_t lane, bool invert);
+void nthw_phy_tile_set_host_loopback(nthw_phy_tile_t *p, uint8_t intf_no, uint8_t lane,
+	bool enable);
+uint32_t nthw_phy_tile_get_host_loopback(nthw_phy_tile_t *p, uint8_t intf_no, uint8_t lane);
+void nthw_phy_tile_set_tx_equalization(nthw_phy_tile_t *p, uint8_t intf_no, uint8_t lane,
+	uint32_t pre_tap2, uint32_t main_tap, uint32_t pre_tap1,
+	uint32_t post_tap1);
+void nthw_phy_tile_get_tx_equalization(nthw_phy_tile_t *p, uint8_t intf_no, uint8_t lane);
+void nthw_phy_tile_get_link_summary(nthw_phy_tile_t *p, uint32_t *p_nt_phy_link_state,
+	uint32_t *p_ll_nt_phy_link_state, uint32_t *p_lh_local_fault,
+	uint32_t *p_lh_remote_fault, uint8_t index);
+void nthw_phy_tile_set_tx_reset(nthw_phy_tile_t *p, uint8_t intf_no, bool reset);
+void nthw_phy_tile_set_rx_reset(nthw_phy_tile_t *p, uint8_t intf_no, bool reset);
+bool nthw_phy_tile_read_fec_enabled_by_scratch(nthw_phy_tile_t *p, uint8_t intf_no);
+void nthw_phy_tile_write_fec_enabled_by_scratch(nthw_phy_tile_t *p, uint8_t intf_no,
+	bool fec_enabled);
+void nthw_phy_tile_set_dyn_reset(nthw_phy_tile_t *p, uint8_t reset);
+bool nthw_phy_tile_get_rx_hi_ber(nthw_phy_tile_t *p, uint8_t intf_no);
+bool nthw_phy_tile_get_rx_am_lock(nthw_phy_tile_t *p, uint8_t intf_no);
+void nthw_phy_tile_set_timestamp_comp_rx(nthw_phy_tile_t *p, uint8_t intf_no, uint32_t value);
+uint32_t nthw_phy_tile_get_timestamp_comp_rx(nthw_phy_tile_t *p, uint8_t intf_no);
+void nthw_phy_tile_set_timestamp_comp_tx(nthw_phy_tile_t *p, uint8_t intf_no, uint32_t value);
+void nthw_phy_tile_write_dr_ctrl_mc_cfgcsr_reg(nthw_phy_tile_t *p, uint32_t offset,
+	uint32_t wdata);
+uint32_t nthw_phy_tile_polling_for_bit_dr_ctrl(nthw_phy_tile_t *p, uint32_t channel,
+	uint32_t offset, uint32_t bit_offset);
+uint32_t nthw_phy_tile_read_eth(nthw_phy_tile_t *p, uint8_t intf_no, uint8_t lane,
+	uint32_t address);
+void nthw_phy_tile_write_eth(nthw_phy_tile_t *p, uint8_t intf_no, uint8_t lane, uint32_t address,
+	uint32_t data);
+bool nthw_phy_tile_configure_fec(nthw_phy_tile_t *p, uint8_t intf_no, bool enable);
+uint32_t nthw_phy_tile_read_xcvr(nthw_phy_tile_t *p, uint8_t intf_no, uint8_t lane,
+	uint32_t address);
+void nthw_phy_tile_write_xcvr(nthw_phy_tile_t *p, uint8_t intf_no, uint8_t lane, uint32_t address,
+	uint32_t data);
+
+#endif	/* __NTHW_PHY_TILE_H__ */
diff --git a/drivers/net/ntnic/nthw/core/include/nthw_sdc.h b/drivers/net/ntnic/nthw/core/include/nthw_sdc.h
new file mode 100644
index 0000000000..53df9c7520
--- /dev/null
+++ b/drivers/net/ntnic/nthw/core/include/nthw_sdc.h
@@ -0,0 +1,43 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef __NTHW_SDC_H__
+#define __NTHW_SDC_H__
+
+struct nthw_sdc {
+	nthw_fpga_t *mp_fpga;
+	nthw_module_t *mp_mod_sdc;
+	int mn_instance;
+
+	nthw_field_t *mp_fld_ctrl_init;
+	nthw_field_t *mp_fld_ctrl_run_test;
+	nthw_field_t *mp_fld_ctrl_stop_client;
+	nthw_field_t *mp_fld_ctrl_test_enable;
+
+	nthw_field_t *mp_fld_stat_calib;
+	nthw_field_t *mp_fld_stat_cell_cnt_stopped;
+	nthw_field_t *mp_fld_stat_err_found;
+	nthw_field_t *mp_fld_stat_init_done;
+	nthw_field_t *mp_fld_stat_mmcm_lock;
+	nthw_field_t *mp_fld_stat_pll_lock;
+	nthw_field_t *mp_fld_stat_resetting;
+
+	nthw_field_t *mp_fld_cell_cnt;
+	nthw_field_t *mp_fld_cell_cnt_period;
+	nthw_field_t *mp_fld_fill_level;
+	nthw_field_t *mp_fld_max_fill_level;
+};
+
+typedef struct nthw_sdc nthw_sdc_t;
+typedef struct nthw_sdc nthw_sdc;
+
+nthw_sdc_t *nthw_sdc_new(void);
+int nthw_sdc_init(nthw_sdc_t *p, nthw_fpga_t *p_fpga, int n_instance);
+void nthw_sdc_delete(nthw_sdc_t *p);
+
+int nthw_sdc_wait_states(nthw_sdc_t *p, const int n_poll_iterations, const int n_poll_interval);
+int nthw_sdc_get_states(nthw_sdc_t *p, uint64_t *pn_result_mask);
+
+#endif	/* __NTHW_SDC_H__ */
diff --git a/drivers/net/ntnic/nthw/core/include/nthw_si5340.h b/drivers/net/ntnic/nthw/core/include/nthw_si5340.h
new file mode 100644
index 0000000000..62e6c2d443
--- /dev/null
+++ b/drivers/net/ntnic/nthw/core/include/nthw_si5340.h
@@ -0,0 +1,33 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef __NTHW_SI5340_H__
+#define __NTHW_SI5340_H__
+
+#include "nthw_clock_profiles.h"
+
+#define SI5340_SUCCESS (0)
+#define SI5340_FAILED (999)
+#define SI5340_TIMEOUT (666)
+
+struct nthw_si5340 {
+	uint8_t mn_iic_addr;
+	nthw_iic_t *mp_nthw_iic;
+	int mn_clk_cfg;
+	uint8_t m_si5340_page;
+};
+
+typedef struct nthw_si5340 nthw_si5340_t;
+
+nthw_si5340_t *nthw_si5340_new(void);
+int nthw_si5340_init(nthw_si5340_t *p, nthw_iic_t *p_nthw_iic, uint8_t n_iic_addr);
+void nthw_si5340_delete(nthw_si5340_t *p);
+
+int nthw_si5340_config(nthw_si5340_t *p, const void *p_data, int data_cnt,
+	clk_profile_data_fmt_t data_format);
+int nthw_si5340_config_fmt2(nthw_si5340_t *p, const clk_profile_data_fmt2_t *p_data,
+	const int data_cnt);
+
+#endif	/* __NTHW_SI5338_H__ */
diff --git a/drivers/net/ntnic/nthw/core/include/nthw_spi_v3.h b/drivers/net/ntnic/nthw/core/include/nthw_spi_v3.h
new file mode 100644
index 0000000000..b051a0a9fc
--- /dev/null
+++ b/drivers/net/ntnic/nthw/core/include/nthw_spi_v3.h
@@ -0,0 +1,105 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef __NT4GA_SPI_V3__
+#define __NT4GA_SPI_V3__
+
+/* Must include v1.x series. The first v1.0a only had 248 bytes of storage. v2.0x have 255 */
+#define MAX_AVR_CONTAINER_SIZE (248)
+
+enum avr_opcodes {
+	__AVR_OP_NOP = 0,	/* v2 NOP command */
+	/* version handlers */
+	AVR_OP_VERSION = 1,
+	AVR_OP_SPI_VERSION = 2,	/* v2.0+ command Get protocol version */
+	AVR_OP_SYSINFO = 3,
+	/* Ping handlers */
+	AVR_OP_PING = 4,
+	AVR_OP_PING_DELAY = 5,
+	/* i2c handlers */
+	AVR_OP_I2C_READ = 9,
+	AVR_OP_I2C_WRITE = 10,
+	AVR_OP_I2C_RANDOM_READ = 11,
+	/* VPD handlers */
+	AVR_OP_VPD_READ = 19,
+	AVR_OP_VPD_WRITE = 20,
+	/* SENSOR handlers */
+	AVR_OP_SENSOR_FETCH = 28,
+	/* The following command are only relevant to V3 */
+	AVR_OP_SENSOR_MON_CONTROL = 42,
+	AVR_OP_SENSOR_MON_SETUP = 43,
+	/* special version handler */
+	AVR_OP_SYSINFO_2 = 62,
+};
+
+#define GEN2_AVR_IDENT_SIZE (20)
+#define GEN2_AVR_VERSION_SIZE (50)
+
+#define GEN2_PN_SIZE (13)
+#define GEN2_PBA_SIZE (16)
+#define GEN2_SN_SIZE (10)
+#define GEN2_BNAME_SIZE (14)
+#define GEN2_PLATFORM_SIZE (72)
+#define GEN2_VPD_SIZE_TOTAL                                                                       \
+	(1 + GEN2_PN_SIZE + GEN2_PBA_SIZE + GEN2_SN_SIZE + GEN2_BNAME_SIZE + GEN2_PLATFORM_SIZE + \
+	 2)
+
+typedef struct vpd_eeprom_s {
+	uint8_t psu_hw_version;	/* Hw revision - MUST NEVER ne overwritten. */
+	/* Vital Product Data: P/N   (13bytes ascii 0-9) */
+	uint8_t vpd_pn[GEN2_PN_SIZE];
+	/* Vital Product Data: PBA   (16bytes ascii 0-9) */
+	uint8_t vpd_pba[GEN2_PBA_SIZE];
+	/* Vital Product Data: S/N   (10bytes ascii 0-9) */
+	uint8_t vpd_sn[GEN2_SN_SIZE];
+	/* Vital Product Data: Board Name (10bytes ascii) (e.g. "ntmainb1e2" or "ntfront20b1") */
+	uint8_t vpd_board_name[GEN2_BNAME_SIZE];
+	/*
+	 * Vital Product Data: Other (72bytes of MAC addresses or other stuff.. (gives up to 12 mac
+	 * addresses)
+	 */
+	uint8_t vpd_platform_section[GEN2_PLATFORM_SIZE];
+	/* CRC16 checksum of all of above. This field is not included in the checksum */
+	uint16_t crc16;
+} vpd_eeprom_t;
+
+typedef struct {
+	uint8_t psu_hw_revision;
+	char board_type[GEN2_BNAME_SIZE + 1];
+	char product_id[GEN2_PN_SIZE + 1];
+	char pba_id[GEN2_PBA_SIZE + 1];
+	char serial_number[GEN2_SN_SIZE + 1];
+	uint8_t product_family;
+	uint32_t feature_mask;
+	uint32_t invfeature_mask;
+	uint8_t no_of_macs;
+	uint8_t mac_address[6];
+	uint16_t custom_id;
+	uint8_t user_id[8];
+} board_info_t;
+
+struct tx_rx_buf {
+	uint16_t size;
+	void *p_buf;
+};
+
+struct nthw_spi_v3 {
+	int m_time_out;
+	int mn_instance_no;
+	nthw_spim_t *mp_spim_mod;
+	nthw_spis_t *mp_spis_mod;
+};
+
+typedef struct nthw_spi_v3 nthw_spi_v3_t;
+typedef struct nthw_spi_v3 nthw_spi_v3;
+
+nthw_spi_v3_t *nthw_spi_v3_new(void);
+int nthw_spi_v3_init(nthw_spi_v3_t *p, nthw_fpga_t *p_fpga, int n_instance_no);
+
+int nthw_spi_v3_set_timeout(nthw_spi_v3_t *p, int time_out);
+int nthw_spi_v3_transfer(nthw_spi_v3_t *p, uint16_t opcode, struct tx_rx_buf *tx_buf,
+	struct tx_rx_buf *rx_buf);
+
+#endif	/* __NT4GA_SPI_V3__ */
diff --git a/drivers/net/ntnic/nthw/core/include/nthw_spim.h b/drivers/net/ntnic/nthw/core/include/nthw_spim.h
new file mode 100644
index 0000000000..473ceb86d6
--- /dev/null
+++ b/drivers/net/ntnic/nthw/core/include/nthw_spim.h
@@ -0,0 +1,57 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef __NTHW_SPIM_H__
+#define __NTHW_SPIM_H__
+
+struct nthw_spim {
+	nthw_fpga_t *mp_fpga;
+	nthw_module_t *mp_mod_spim;
+	int mn_instance;
+
+	nthw_register_t *mp_reg_srr;
+	nthw_field_t *mp_fld_srr_rst;
+
+	nthw_register_t *mp_reg_cr;
+	nthw_field_t *mp_fld_cr_loop;
+	nthw_field_t *mp_fld_cr_en;
+	nthw_field_t *mp_fld_cr_txrst;
+	nthw_field_t *mp_fld_cr_rxrst;
+
+	nthw_register_t *mp_reg_sr;
+	nthw_field_t *mp_fld_sr_done;
+	nthw_field_t *mp_fld_sr_txempty;
+	nthw_field_t *mp_fld_sr_rxempty;
+	nthw_field_t *mp_fld_sr_txfull;
+	nthw_field_t *mp_fld_sr_rxfull;
+	nthw_field_t *mp_fld_sr_txlvl;
+	nthw_field_t *mp_fld_sr_rxlvl;
+
+	nthw_register_t *mp_reg_dtr;
+	nthw_field_t *mp_fld_dtr_dtr;
+
+	nthw_register_t *mp_reg_drr;
+	nthw_field_t *mp_fld_drr_drr;
+
+	nthw_register_t *mp_reg_cfg;
+	nthw_field_t *mp_fld_cfg_pre;
+
+	nthw_register_t *mp_reg_cfg_clk;
+	nthw_field_t *mp_fld_cfg_clk_mode;
+};
+
+typedef struct nthw_spim nthw_spim_t;
+typedef struct nthw_spim nthw_spim;
+
+nthw_spim_t *nthw_spim_new(void);
+int nthw_spim_init(nthw_spim_t *p, nthw_fpga_t *p_fpga, int n_instance);
+void nthw_spim_delete(nthw_spim_t *p);
+
+uint32_t nthw_spim_reset(nthw_spim_t *p);
+uint32_t nthw_spim_enable(nthw_spim_t *p, bool b_enable);
+uint32_t nthw_spim_get_tx_fifo_empty(nthw_spim_t *p, bool *pb_empty);
+uint32_t nthw_spim_write_tx_fifo(nthw_spim_t *p, uint32_t n_data);
+
+#endif	/* __NTHW_SPIM_H__ */
diff --git a/drivers/net/ntnic/nthw/core/include/nthw_spis.h b/drivers/net/ntnic/nthw/core/include/nthw_spis.h
new file mode 100644
index 0000000000..b9a7b6b49d
--- /dev/null
+++ b/drivers/net/ntnic/nthw/core/include/nthw_spis.h
@@ -0,0 +1,62 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef __NTHW_SPIS_H__
+#define __NTHW_SPIS_H__
+
+struct nthw_spis {
+	nthw_fpga_t *mp_fpga;
+	nthw_module_t *mp_mod_spis;
+	int mn_instance;
+
+	nthw_register_t *mp_reg_srr;
+	nthw_field_t *mp_fld_srr_rst;
+
+	nthw_register_t *mp_reg_cr;
+	nthw_field_t *mp_fld_cr_loop;
+	nthw_field_t *mp_fld_cr_en;
+	nthw_field_t *mp_fld_cr_txrst;
+	nthw_field_t *mp_fld_cr_rxrst;
+	nthw_field_t *mp_fld_cr_debug;
+
+	nthw_register_t *mp_reg_sr;
+	nthw_field_t *mp_fld_sr_done;
+	nthw_field_t *mp_fld_sr_txempty;
+	nthw_field_t *mp_fld_sr_rxempty;
+	nthw_field_t *mp_fld_sr_txfull;
+	nthw_field_t *mp_fld_sr_rxfull;
+	nthw_field_t *mp_fld_sr_txlvl;
+	nthw_field_t *mp_fld_sr_rxlvl;
+	nthw_field_t *mp_fld_sr_frame_err;
+	nthw_field_t *mp_fld_sr_read_err;
+	nthw_field_t *mp_fld_sr_write_err;
+
+	nthw_register_t *mp_reg_dtr;
+	nthw_field_t *mp_fld_dtr_dtr;
+
+	nthw_register_t *mp_reg_drr;
+	nthw_field_t *mp_fld_drr_drr;
+
+	nthw_register_t *mp_reg_ram_ctrl;
+	nthw_field_t *mp_fld_ram_ctrl_adr;
+	nthw_field_t *mp_fld_ram_ctrl_cnt;
+
+	nthw_register_t *mp_reg_ram_data;
+	nthw_field_t *mp_fld_ram_data_data;
+};
+
+typedef struct nthw_spis nthw_spis_t;
+typedef struct nthw_spis nthw_spis;
+
+nthw_spis_t *nthw_spis_new(void);
+int nthw_spis_init(nthw_spis_t *p, nthw_fpga_t *p_fpga, int n_instance);
+void nthw_spis_delete(nthw_spis_t *p);
+
+uint32_t nthw_spis_reset(nthw_spis_t *p);
+uint32_t nthw_spis_enable(nthw_spis_t *p, bool b_enable);
+uint32_t nthw_spis_get_rx_fifo_empty(nthw_spis_t *p, bool *pb_empty);
+uint32_t nthw_spis_read_rx_fifo(nthw_spis_t *p, uint32_t *p_data);
+
+#endif	/* __NTHW_SPIS_H__ */
diff --git a/drivers/net/ntnic/nthw/core/include/nthw_tsm.h b/drivers/net/ntnic/nthw/core/include/nthw_tsm.h
new file mode 100644
index 0000000000..3c766370b4
--- /dev/null
+++ b/drivers/net/ntnic/nthw/core/include/nthw_tsm.h
@@ -0,0 +1,52 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef __NTHW_TSM_H__
+#define __NTHW_TSM_H__
+
+struct nthw_tsm {
+	nthw_fpga_t *mp_fpga;
+	nthw_module_t *mp_mod_tsm;
+	int mn_instance;
+
+	nthw_field_t *mp_fld_config_ts_format;
+
+	nthw_field_t *mp_fld_timer_ctrl_timer_en_t0;
+	nthw_field_t *mp_fld_timer_ctrl_timer_en_t1;
+
+	nthw_field_t *mp_fld_timer_timer_t0_max_count;
+
+	nthw_field_t *mp_fld_timer_timer_t1_max_count;
+
+	nthw_register_t *mp_reg_ts_lo;
+	nthw_field_t *mp_fld_ts_lo;
+
+	nthw_register_t *mp_reg_ts_hi;
+	nthw_field_t *mp_fld_ts_hi;
+
+	nthw_register_t *mp_reg_time_lo;
+	nthw_field_t *mp_fld_time_lo;
+
+	nthw_register_t *mp_reg_time_hi;
+	nthw_field_t *mp_fld_time_hi;
+};
+
+typedef struct nthw_tsm nthw_tsm_t;
+typedef struct nthw_tsm nthw_tsm;
+
+nthw_tsm_t *nthw_tsm_new(void);
+int nthw_tsm_init(nthw_tsm_t *p, nthw_fpga_t *p_fpga, int n_instance);
+
+int nthw_tsm_get_ts(nthw_tsm_t *p, uint64_t *p_ts);
+int nthw_tsm_get_time(nthw_tsm_t *p, uint64_t *p_time);
+
+int nthw_tsm_set_timer_t0_enable(nthw_tsm_t *p, bool b_enable);
+int nthw_tsm_set_timer_t0_max_count(nthw_tsm_t *p, uint32_t n_timer_val);
+int nthw_tsm_set_timer_t1_enable(nthw_tsm_t *p, bool b_enable);
+int nthw_tsm_set_timer_t1_max_count(nthw_tsm_t *p, uint32_t n_timer_val);
+
+int nthw_tsm_set_config_ts_format(nthw_tsm_t *p, uint32_t n_val);
+
+#endif	/* __NTHW_TSM_H__ */
-- 
2.44.0


^ permalink raw reply	[flat|nested] 238+ messages in thread

* [PATCH v1 04/17] net/ntnic: add FPGA model implementation
  2024-05-30 14:48 [PATCH v1 01/17] net/ntnic: Add registers for NapaTech SmartNiC Serhii Iliushyk
  2024-05-30 14:48 ` [PATCH v1 02/17] net/ntnic: add core platform functionality Serhii Iliushyk
  2024-05-30 14:49 ` [PATCH v1 03/17] net/ntnic: add interfaces for " Serhii Iliushyk
@ 2024-05-30 14:49 ` Serhii Iliushyk
  2024-05-30 14:49 ` [PATCH v1 05/17] net/ntnic: add NTNIC adapter interfaces Serhii Iliushyk
                   ` (21 subsequent siblings)
  24 siblings, 0 replies; 238+ messages in thread
From: Serhii Iliushyk @ 2024-05-30 14:49 UTC (permalink / raw)
  To: dev; +Cc: mko-plv, ckm, andrew.rybchenko, ferruh.yigit

Add ntnic query FPGA functionality.

Signed-off-by: Serhii Iliushyk <sil-plv@napatech.com>
---
 .../net/ntnic/nthw/model/nthw_fpga_model.c    | 1218 +++++++++++++++++
 .../net/ntnic/nthw/model/nthw_fpga_model.h    |  247 ++++
 2 files changed, 1465 insertions(+)
 create mode 100644 drivers/net/ntnic/nthw/model/nthw_fpga_model.c
 create mode 100644 drivers/net/ntnic/nthw/model/nthw_fpga_model.h

diff --git a/drivers/net/ntnic/nthw/model/nthw_fpga_model.c b/drivers/net/ntnic/nthw/model/nthw_fpga_model.c
new file mode 100644
index 0000000000..36a7dfcf7a
--- /dev/null
+++ b/drivers/net/ntnic/nthw/model/nthw_fpga_model.c
@@ -0,0 +1,1218 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#include <time.h>	/* ctime */
+
+#include "nthw_drv.h"	/* fpga_info_s */
+#include "nthw_register.h"
+#include "nthw_fpga_model.h"
+#include "nthw_rac.h"
+#include "ntlog.h"
+
+/*
+ * NOTE: this needs to be (manually) synced with enum nthw_fpga_bus_type
+ */
+static const char *const sa_nthw_fpga_bus_type_str[] = {
+	"ERR",	/* NTHW_FPGA_BUS_TYPE_UNKNOWN, */
+	"BAR",	/* NTHW_FPGA_BUS_TYPE_BAR, */
+	"PCI",	/* NTHW_FPGA_BUS_TYPE_PCI, */
+	"CCIP",	/* NTHW_FPGA_BUS_TYPE_CCIP, */
+	"RAB0",	/* NTHW_FPGA_BUS_TYPE_RAB0, */
+	"RAB1",	/* NTHW_FPGA_BUS_TYPE_RAB1, */
+	"RAB2",	/* NTHW_FPGA_BUS_TYPE_RAB2, */
+	"NMB",	/* NTHW_FPGA_BUS_TYPE_NMB, */
+	"NDM",	/* NTHW_FPGA_BUS_TYPE_NDM, */
+};
+
+static const char *get_bus_name(int n_bus_type_id)
+{
+	if (n_bus_type_id >= 1 && n_bus_type_id <= (int)ARRAY_SIZE(sa_nthw_fpga_bus_type_str))
+		return sa_nthw_fpga_bus_type_str[n_bus_type_id];
+
+	else
+		return "ERR";
+}
+
+/*
+ * module name lookup by id from array
+ * Uses naive linear search as performance is not an issue here...
+ */
+
+static const struct {
+	const nthw_id_t a;
+	const char *b;
+} *sa_nthw_fpga_mod_str_map;
+
+static const char *nthw_fpga_mod_id_to_str(nthw_id_t n_fpga_mod_id)
+{
+	int i;
+
+	if (sa_nthw_fpga_mod_str_map) {
+		for (i = 0; sa_nthw_fpga_mod_str_map[i].a && sa_nthw_fpga_mod_str_map[i].b; i++)
+			if ((nthw_id_t)sa_nthw_fpga_mod_str_map[i].a == n_fpga_mod_id)
+				return sa_nthw_fpga_mod_str_map[i].b;
+	}
+
+	return "unknown";
+}
+
+static int nthw_read_data(struct fpga_info_s *p_fpga_info, bool trc, int n_bus_type_id,
+	uint32_t addr, uint32_t len, uint32_t *p_data)
+{
+	int rc = -1;
+
+	assert(p_fpga_info);
+	assert(p_data);
+	assert(len >= 1);
+
+	switch (n_bus_type_id) {
+	case NTHW_FPGA_BUS_TYPE_BAR:
+	case NTHW_FPGA_BUS_TYPE_PCI:
+		nthw_rac_bar0_read32(p_fpga_info, addr, len, p_data);
+		rc = 0;
+		break;
+
+	case NTHW_FPGA_BUS_TYPE_RAB0:
+		assert(p_fpga_info->mp_nthw_rac);
+		rc = nthw_rac_rab_read32(p_fpga_info->mp_nthw_rac, trc, 0, addr, len, p_data);
+		break;
+
+	case NTHW_FPGA_BUS_TYPE_RAB1:
+		assert(p_fpga_info->mp_nthw_rac);
+		rc = nthw_rac_rab_read32(p_fpga_info->mp_nthw_rac, trc, 1, addr, len, p_data);
+		break;
+
+	case NTHW_FPGA_BUS_TYPE_RAB2:
+		assert(p_fpga_info->mp_nthw_rac);
+		rc = nthw_rac_rab_read32(p_fpga_info->mp_nthw_rac, trc, 2, addr, len, p_data);
+		break;
+
+	default:
+		assert(false);
+		return -1;
+	}
+
+	return rc;
+}
+
+static int nthw_write_data(struct fpga_info_s *p_fpga_info, bool trc, int n_bus_type_id,
+	uint32_t addr, uint32_t len, const uint32_t *p_data)
+{
+	int rc = -1;
+
+	assert(p_fpga_info);
+	assert(p_data);
+	assert(len >= 1);
+
+	switch (n_bus_type_id) {
+	case NTHW_FPGA_BUS_TYPE_BAR:
+	case NTHW_FPGA_BUS_TYPE_PCI:
+		nthw_rac_bar0_write32(p_fpga_info, addr, len, p_data);
+		rc = 0;
+		break;
+
+	case NTHW_FPGA_BUS_TYPE_RAB0:
+		assert(p_fpga_info->mp_nthw_rac);
+		rc = nthw_rac_rab_write32(p_fpga_info->mp_nthw_rac, trc, 0, addr, len, p_data);
+		break;
+
+	case NTHW_FPGA_BUS_TYPE_RAB1:
+		assert(p_fpga_info->mp_nthw_rac);
+		rc = nthw_rac_rab_write32(p_fpga_info->mp_nthw_rac, trc, 1, addr, len, p_data);
+		break;
+
+	case NTHW_FPGA_BUS_TYPE_RAB2:
+		assert(p_fpga_info->mp_nthw_rac);
+		rc = nthw_rac_rab_write32(p_fpga_info->mp_nthw_rac, trc, 2, addr, len, p_data);
+		break;
+
+	default:
+		assert(false);
+		return -1;
+	}
+
+	return rc;
+}
+
+uint64_t nthw_fpga_read_ident(struct fpga_info_s *p_fpga_info)
+{
+	uint64_t n_fpga_ident;
+	uint32_t n_fpga_ident_lo, n_fpga_ident_hi;
+	nthw_rac_bar0_read32(p_fpga_info, 0x0, 1, &n_fpga_ident_lo);
+	nthw_rac_bar0_read32(p_fpga_info, 0x8, 1, &n_fpga_ident_hi);
+	n_fpga_ident = (((uint64_t)n_fpga_ident_hi << 32) | n_fpga_ident_lo);
+	return n_fpga_ident;
+}
+
+uint32_t nthw_fpga_read_buildtime(struct fpga_info_s *p_fpga_info)
+{
+	uint32_t n_fpga_build_time;
+	nthw_rac_bar0_read32(p_fpga_info, 0x10, 1, &n_fpga_build_time);
+	return n_fpga_build_time;
+}
+
+int nthw_fpga_extract_type_id(const uint64_t n_fpga_ident)
+{
+	return (uint16_t)(n_fpga_ident >> 32) & 0xFF;
+}
+
+int nthw_fpga_extract_prod_id(const uint64_t n_fpga_ident)
+{
+	return (uint16_t)(n_fpga_ident >> 16) & 0xFFFF;
+}
+
+int nthw_fpga_extract_ver_id(const uint64_t n_fpga_ident)
+{
+	return (uint16_t)((n_fpga_ident >> 8) & 0xFF);
+}
+
+int nthw_fpga_extract_rev_id(const uint64_t n_fpga_ident)
+{
+	return (uint16_t)(n_fpga_ident & 0xFF);
+}
+
+/*
+ * FpgaMgr
+ */
+nthw_fpga_mgr_t *nthw_fpga_mgr_new(void)
+{
+	nthw_fpga_mgr_t *p = malloc(sizeof(nthw_fpga_mgr_t));
+	return p;
+}
+
+void nthw_fpga_mgr_delete(nthw_fpga_mgr_t *p)
+{
+	memset(p, 0, sizeof(nthw_fpga_mgr_t));
+	free(p);
+}
+
+void nthw_fpga_mgr_init(nthw_fpga_mgr_t *p, struct nthw_fpga_prod_init **pa_nthw_fpga_instances,
+	const void *pa_mod_str_map)
+{
+	size_t i = 0;
+
+	p->mpa_fpga_prod_init = pa_nthw_fpga_instances;
+	sa_nthw_fpga_mod_str_map = pa_mod_str_map;
+
+	/* Count fpga instance in array */
+	if (pa_nthw_fpga_instances) {
+		for (i = 0;; i++)
+			if (p->mpa_fpga_prod_init[i] == NULL)
+				break;
+	}
+
+	p->mn_fpgas = (int)i;
+}
+
+static nthw_fpga_t *nthw_fpga_mgr_lookup_fpga(nthw_fpga_mgr_t *p, uint64_t n_fpga_id,
+	struct fpga_info_s *p_fpga_info)
+{
+	const int n_fpga_prod_id = nthw_fpga_extract_prod_id(n_fpga_id);
+	const int n_fpga_ver = nthw_fpga_extract_ver_id(n_fpga_id);
+	const int n_fpga_rev = nthw_fpga_extract_rev_id(n_fpga_id);
+	int i;
+
+	for (i = 0; i < p->mn_fpgas; i++) {
+		nthw_fpga_prod_init_s *p_init = p->mpa_fpga_prod_init[i];
+
+		if (p_init->fpga_product_id == n_fpga_prod_id &&
+			p_init->fpga_version == n_fpga_ver && p_init->fpga_revision == n_fpga_rev) {
+			nthw_fpga_t *p_fpga = nthw_fpga_model_new();
+			nthw_fpga_model_init(p_fpga, p_init, p_fpga_info);
+			return p_fpga;
+		}
+	}
+
+	return NULL;
+}
+
+nthw_fpga_t *nthw_fpga_mgr_query_fpga(nthw_fpga_mgr_t *p_fpga_mgr, uint64_t n_fpga_id,
+	struct fpga_info_s *p_fpga_info)
+{
+	const int n_fpga_prod_id = nthw_fpga_extract_prod_id(n_fpga_id);
+	const int n_fpga_ver = nthw_fpga_extract_ver_id(n_fpga_id);
+	const int n_fpga_rev = nthw_fpga_extract_rev_id(n_fpga_id);
+
+	nthw_fpga_t *p_fpga = nthw_fpga_mgr_lookup_fpga(p_fpga_mgr, n_fpga_id, p_fpga_info);
+
+	if (p_fpga) {
+	} else {
+		NT_LOG(ERR, NTHW, "FPGA Id 0x%" PRIX64 ": %04d: %d.%d: no match found\n",
+			n_fpga_id, n_fpga_prod_id, n_fpga_ver, n_fpga_rev);
+	}
+
+	return p_fpga;
+}
+
+void nthw_fpga_mgr_show(nthw_fpga_mgr_t *p, FILE *fh_out, int detail_level)
+{
+	int i;
+
+	fprintf(fh_out, "\n");	/* start of records */
+
+	for (i = 0; i < p->mn_fpgas; i++) {
+		nthw_fpga_prod_init_s *p_init = p->mpa_fpga_prod_init[i];
+
+		if (detail_level == 0) {
+			fprintf(fh_out, "%04d-%02d-%02d\n", p_init->fpga_product_id,
+				p_init->fpga_version, p_init->fpga_revision);
+
+		} else {
+			time_t fpga_build_time = p_init->fpga_build_time;
+			fprintf(fh_out, "%04d-%02d-%02d: 0x%08lX: %s\n", p_init->fpga_product_id,
+				p_init->fpga_version, p_init->fpga_revision, fpga_build_time,
+				(fpga_build_time ? ctime(&fpga_build_time) : "NA\n"));
+		}
+	}
+
+	fprintf(fh_out, "\n");	/* end of records */
+	fflush(fh_out);
+}
+
+void nthw_fpga_mgr_log_dump(nthw_fpga_mgr_t *p)
+{
+	int i;
+
+	NT_LOG(DBG, NTHW, "%s: fpgas=%d\n", __func__, p->mn_fpgas);
+
+	for (i = 0; i < p->mn_fpgas; i++) {
+		nthw_fpga_prod_init_s *p_init = p->mpa_fpga_prod_init[i];
+		(void)p_init;
+		NT_LOG(DBG, NTHW, "%s: fpga=%d/%d: %04d-%02d-%02d\n", __func__, i, p->mn_fpgas,
+			p_init->fpga_product_id, p_init->fpga_version, p_init->fpga_revision);
+	}
+}
+
+/*
+ * Fpga
+ */
+nthw_fpga_t *nthw_fpga_model_new(void)
+{
+	nthw_fpga_t *p = malloc(sizeof(nthw_fpga_t));
+
+	if (p)
+		memset(p, 0, sizeof(nthw_fpga_t));
+
+	return p;
+}
+
+void nthw_fpga_model_init(nthw_fpga_t *p, nthw_fpga_prod_init_s *p_init,
+	struct fpga_info_s *p_fpga_info)
+{
+	int i;
+
+	p->p_fpga_info = p_fpga_info;
+	p->mp_init = p_init;
+
+	p->mn_item_id = p_init->fpga_item_id;
+	p->mn_product_id = p_init->fpga_product_id;
+	p->mn_fpga_version = p_init->fpga_version;
+	p->mn_fpga_revision = p_init->fpga_revision;
+	p->mn_fpga_patch_no = p_init->fpga_patch_no;
+	p->mn_fpga_build_no = p_init->fpga_build_no;
+	p->mn_fpga_build_time = p_init->fpga_build_time;
+
+	p->mn_params = p_init->nb_prod_params;
+
+	if (p->mn_params) {
+		p->mpa_params = malloc(p->mn_params * sizeof(nthw_param_t *));
+
+		if (p->mpa_params) {
+			memset(p->mpa_params, 0, (p->mn_params * sizeof(nthw_param_t *)));
+
+			for (i = 0; i < p->mn_params; i++) {
+				nthw_param_t *p_param = nthw_param_new();
+
+				nthw_param_init(p_param, p, &p_init->product_params[i]);
+				p->mpa_params[i] = p_param;
+			}
+		}
+	}
+
+	p->mn_modules = p_init->nb_modules;
+
+	if (p->mn_modules) {
+		p->mpa_modules = malloc(p_init->nb_modules * sizeof(nthw_module_t *));
+
+		if (p->mpa_modules) {
+			memset(p->mpa_modules, 0, (p->mn_modules * sizeof(nthw_module_t *)));
+
+			for (i = 0; i < p->mn_modules; i++) {
+				nthw_module_t *p_mod = nthw_module_new();
+
+				nthw_module_init(p_mod, p, &p_init->modules[i]);
+				p->mpa_modules[i] = p_mod;
+			}
+		}
+	}
+}
+
+void nthw_fpga_set_debug_mode(nthw_fpga_t *p, int debug_mode)
+{
+	int i;
+
+	p->m_debug_mode = debug_mode;
+
+	for (i = 0; i < p->mn_modules; i++) {
+		nthw_module_t *p_mod = p->mpa_modules[i];
+
+		if (p_mod)
+			nthw_module_set_debug_mode(p_mod, debug_mode);
+	}
+}
+
+static nthw_module_t *nthw_fpga_lookup_module(const nthw_fpga_t *p, nthw_id_t id, int instance)
+{
+	int i;
+
+	for (i = 0; i < p->mn_modules; i++) {
+		nthw_module_t *p_mod = p->mpa_modules[i];
+
+		if (p_mod->mn_mod_id == id && p_mod->mn_instance == instance)
+			return p_mod;
+	}
+
+	return NULL;
+}
+
+nthw_module_t *nthw_fpga_query_module(const nthw_fpga_t *p, nthw_id_t id, int instance)
+{
+	return nthw_fpga_lookup_module(p, id, instance);
+}
+
+int nthw_fpga_get_product_param(const nthw_fpga_t *p, const nthw_id_t n_param_id,
+	const int n_default_value)
+{
+	int i;
+
+	for (i = 0; i < p->mn_params; i++) {
+		nthw_param_t *p_param = p->mpa_params[i];
+
+		if (p_param->mn_param_id == n_param_id)
+			return p_param->mn_param_value;
+	}
+
+	return n_default_value;
+}
+
+int nthw_fpga_get_product_id(const nthw_fpga_t *p)
+{
+	return p->mn_product_id;
+}
+
+/*
+ * Param
+ */
+nthw_param_t *nthw_param_new(void)
+{
+	nthw_param_t *p = malloc(sizeof(nthw_param_t));
+
+	return p;
+}
+
+void nthw_param_init(nthw_param_t *p, nthw_fpga_t *p_fpga, nthw_fpga_prod_param_s *p_init)
+{
+	p->mp_owner = p_fpga;
+	p->mp_init = p_init;
+
+	p->mn_param_id = p_init->id;
+	p->mn_param_value = p_init->value;
+}
+
+/*
+ * Module
+ */
+nthw_module_t *nthw_module_new(void)
+{
+	nthw_module_t *p = malloc(sizeof(nthw_module_t));
+
+	return p;
+}
+
+void nthw_module_init(nthw_module_t *p, nthw_fpga_t *p_fpga, nthw_fpga_module_init_s *p_init)
+{
+	int i;
+
+	p->mp_owner = p_fpga;
+	p->mp_init = p_init;
+
+	p->mn_mod_id = p_init->id;
+	p->mn_instance = p_init->instance;
+
+	/* Copy debug mode from owner */
+	if (p->mp_owner)
+		p->mn_debug_mode = p->mp_owner->m_debug_mode;
+
+	else
+		p->mn_debug_mode = 0;
+
+	p->mn_mod_def_id = p_init->def_id;
+	p->mn_major_version = p_init->major_version;
+	p->mn_minor_version = p_init->minor_version;
+	p->mn_bus = p_init->bus_id;
+	p->mn_addr_base = p_init->addr_base;
+
+	p->mn_registers = p_init->nb_registers;
+
+	if (p->mn_registers) {
+		p->mpa_registers = malloc(p->mn_registers * sizeof(nthw_register_t *));
+
+		if (p->mpa_registers) {
+			memset(p->mpa_registers, 0, (p->mn_registers * sizeof(nthw_register_t *)));
+
+			for (i = 0; i < p->mn_registers; i++) {
+				nthw_register_t *p_reg = nthw_register_new();
+
+				nthw_register_init(p_reg, p, &p_init->registers[i]);
+				p->mpa_registers[i] = p_reg;
+			}
+		}
+	}
+}
+
+int nthw_module_get_major_version(const nthw_module_t *p)
+{
+	return p->mn_major_version;
+}
+
+int nthw_module_get_minor_version(const nthw_module_t *p)
+{
+	return p->mn_minor_version;
+}
+
+uint64_t nthw_module_get_version_packed64(const nthw_module_t *p)
+{
+	return (((uint64_t)p->mn_major_version & 0xFFFFFFFF) << 32) |
+		(p->mn_minor_version & 0xFFFFFFFF);
+}
+
+bool nthw_module_is_version_newer(const nthw_module_t *p, int major_version, int minor_version)
+{
+	if (major_version == p->mn_major_version)
+		return p->mn_minor_version >= minor_version;
+
+	return p->mn_major_version >= major_version;
+}
+
+static nthw_register_t *nthw_module_lookup_register(nthw_module_t *p, nthw_id_t id)
+{
+	int i;
+	nthw_register_t *p_register = NULL;
+
+	for (i = 0; i < p->mn_registers; i++) {
+		if (p->mpa_registers[i]->mn_id == id) {
+			p_register = p->mpa_registers[i];
+			break;
+		}
+	}
+
+	return p_register;
+}
+
+nthw_register_t *nthw_module_query_register(nthw_module_t *p, nthw_id_t id)
+{
+	return nthw_module_lookup_register(p, id);
+}
+
+nthw_register_t *nthw_module_get_register(nthw_module_t *p, nthw_id_t id)
+{
+	nthw_register_t *p_register;
+
+	if (p == NULL) {
+		NT_LOG(ERR, NTHW, "Illegal module context for register %u\n", id);
+		return NULL;
+	}
+
+	p_register = nthw_module_lookup_register(p, id);
+
+	if (!p_register) {
+		NT_LOG(ERR, NTHW, "Register %u not found in module: %s (%u)\n", id,
+			nthw_fpga_mod_id_to_str(p->mn_mod_id), p->mn_mod_id);
+	}
+
+	return p_register;
+}
+
+int nthw_module_get_debug_mode(const nthw_module_t *p)
+{
+	return p->mn_debug_mode;
+}
+
+void nthw_module_set_debug_mode(nthw_module_t *p, unsigned int debug_mode)
+{
+	int i;
+
+	p->mn_debug_mode = debug_mode;
+
+	for (i = 0; i < p->mn_registers; i++) {
+		nthw_register_t *p_register = p->mpa_registers[i];
+
+		if (p_register)
+			nthw_register_set_debug_mode(p_register, debug_mode);
+	}
+}
+
+int nthw_module_get_bus(const nthw_module_t *p)
+{
+	return p->mn_bus;
+}
+
+/*
+ * Register
+ */
+nthw_register_t *nthw_register_new(void)
+{
+	nthw_register_t *p = malloc(sizeof(nthw_register_t));
+
+	return p;
+}
+
+void nthw_register_init(nthw_register_t *p, nthw_module_t *p_module,
+	nthw_fpga_register_init_s *p_init)
+{
+	int i;
+
+	p->mp_owner = p_module;
+
+	p->mn_id = p_init->id;
+	p->mn_bit_width = p_init->bw;
+	p->mn_addr_rel = p_init->addr_rel;
+	p->mn_addr = p_module->mn_addr_base + p_init->addr_rel;
+	p->mn_type = p_init->type;
+	/* Old P200 registers have no bw at register level - default to BW=-1 */
+	p->mn_len = ((p_init->bw != (uint16_t)-1) ? ((p_init->bw + 31) >> 5) : 1);
+	p->mn_debug_mode = p_module->mn_debug_mode;
+
+	p->mn_fields = p_init->nb_fields;
+
+	if (p->mn_fields) {
+		p->mpa_fields = malloc(p->mn_fields * sizeof(nthw_field_t *));
+
+		if (p->mpa_fields) {
+			memset(p->mpa_fields, 0, (p->mn_fields * sizeof(nthw_field_t *)));
+
+			for (i = 0; i < p->mn_fields; i++) {
+				nthw_field_t *p_field = nthw_field_new();
+
+				nthw_field_init(p_field, p, &p_init->fields[i]);
+				p->mpa_fields[i] = p_field;
+			}
+
+			p->mp_shadow = malloc(p->mn_len * sizeof(uint32_t));
+
+			if (p->mp_shadow)
+				memset(p->mp_shadow, 0x00, (p->mn_len * sizeof(uint32_t)));
+
+			p->mp_dirty = malloc(p->mn_len * sizeof(bool));
+
+			if (p->mp_dirty)
+				memset(p->mp_dirty, 0x00, (p->mn_len * sizeof(bool)));
+		}
+	}
+}
+
+uint32_t nthw_register_get_address(const nthw_register_t *p)
+{
+	return p->mn_addr;
+}
+
+void nthw_register_reset(const nthw_register_t *p)
+{
+	int i;
+	nthw_field_t *p_field = NULL;
+
+	for (i = 0; i < p->mn_fields; i++) {
+		p_field = p->mpa_fields[i];
+
+		if (p_field)
+			nthw_field_reset(p_field);
+	}
+}
+
+static nthw_field_t *nthw_register_lookup_field(const nthw_register_t *p, nthw_id_t id)
+{
+	int i;
+	nthw_field_t *p_field = NULL;
+
+	if (!p)
+		return NULL;
+
+	for (i = 0; i < p->mn_fields; i++) {
+		if (p->mpa_fields[i]->mn_id == id) {
+			p_field = p->mpa_fields[i];
+			break;
+		}
+	}
+
+	return p_field;
+}
+
+nthw_field_t *nthw_register_query_field(const nthw_register_t *p, nthw_id_t id)
+{
+	return nthw_register_lookup_field(p, id);
+}
+
+nthw_field_t *nthw_register_get_field(const nthw_register_t *p, nthw_id_t id)
+{
+	nthw_field_t *p_field;
+
+	if (p == NULL) {
+		NT_LOG(ERR, NTHW, "Illegal register context for field %u\n", id);
+		return NULL;
+	}
+
+	p_field = nthw_register_lookup_field(p, id);
+
+	if (!p_field) {
+		NT_LOG(ERR, NTHW, "Field %u not found in module: %s (%u)\n", id,
+			nthw_fpga_mod_id_to_str(p->mp_owner->mn_mod_id), p->mp_owner->mn_mod_id);
+	}
+
+	return p_field;
+}
+
+int nthw_register_get_bit_width(const nthw_register_t *p)
+{
+	return p->mn_bit_width;
+}
+
+int nthw_register_get_debug_mode(const nthw_register_t *p)
+{
+	return p->mn_debug_mode;
+}
+
+/*
+ * NOTE: do not set debug on fields - as register operation dumps typically are enough
+ */
+void nthw_register_set_debug_mode(nthw_register_t *p, unsigned int debug_mode)
+{
+	int i;
+
+	p->mn_debug_mode = debug_mode;
+
+	for (i = 0; i < p->mn_fields; i++) {
+		nthw_field_t *p_field = p->mpa_fields[i];
+
+		if (p_field)
+			nthw_field_set_debug_mode(p_field, debug_mode);
+	}
+}
+
+static int nthw_register_read_data(const nthw_register_t *p)
+{
+	int rc = -1;
+
+	const int n_bus_type_id = nthw_module_get_bus(p->mp_owner);
+	const uint32_t addr = p->mn_addr;
+	const uint32_t len = p->mn_len;
+	uint32_t *const p_data = p->mp_shadow;
+	const bool trc = (p->mn_debug_mode & NTHW_REG_TRACE_ON_READ);
+
+	struct fpga_info_s *p_fpga_info = NULL;
+
+	if (p && p->mp_owner && p->mp_owner->mp_owner)
+		p_fpga_info = p->mp_owner->mp_owner->p_fpga_info;
+
+	assert(p_fpga_info);
+	assert(p_data);
+
+	rc = nthw_read_data(p_fpga_info, trc, n_bus_type_id, addr, len, p_data);
+	return rc;
+}
+
+static int nthw_register_write_data(const nthw_register_t *p, uint32_t cnt)
+{
+	int rc = -1;
+
+	const int n_bus_type_id = nthw_module_get_bus(p->mp_owner);
+	const uint32_t addr = p->mn_addr;
+	const uint32_t len = p->mn_len;
+	uint32_t *const p_data = p->mp_shadow;
+	const bool trc = (p->mn_debug_mode & NTHW_REG_TRACE_ON_WRITE);
+
+	struct fpga_info_s *p_fpga_info = NULL;
+
+	if (p && p->mp_owner && p->mp_owner->mp_owner)
+		p_fpga_info = p->mp_owner->mp_owner->p_fpga_info;
+
+	assert(p_fpga_info);
+	assert(p_data);
+
+	rc = nthw_write_data(p_fpga_info, trc, n_bus_type_id, addr, (len * cnt), p_data);
+
+	return rc;
+}
+
+void nthw_register_get_val(const nthw_register_t *p, uint32_t *p_data, uint32_t len)
+{
+	uint32_t i;
+
+	if (len == (uint32_t)-1 || len > p->mn_len)
+		len = p->mn_len;
+
+	assert(len <= p->mn_len);
+	assert(p_data);
+
+	for (i = 0; i < len; i++)
+		p_data[i] = p->mp_shadow[i];
+}
+
+uint32_t nthw_register_get_val32(const nthw_register_t *p)
+{
+	uint32_t val = 0;
+
+	nthw_register_get_val(p, &val, 1);
+	return val;
+}
+
+void nthw_register_update(const nthw_register_t *p)
+{
+	if (p && p->mn_type != NTHW_FPGA_REG_TYPE_WO) {
+		const char *const p_dev_name = "NA";
+		(void)p_dev_name;
+		const int n_bus_type_id = nthw_module_get_bus(p->mp_owner);
+		const char *const p_bus_name = get_bus_name(n_bus_type_id);
+		(void)p_bus_name;
+		const uint32_t addr = p->mn_addr;
+		(void)addr;
+		const uint32_t len = p->mn_len;
+		uint32_t *const p_data = p->mp_shadow;
+
+		nthw_register_read_data(p);
+
+		if (p->mn_debug_mode & NTHW_REG_DEBUG_ON_READ) {
+			uint32_t i = len;
+			uint32_t *ptr = p_data;
+			(void)ptr;
+			char *tmp_string = ntlog_helper_str_alloc("Register::read");
+			ntlog_helper_str_add(tmp_string,
+				"(Dev: %s, Bus: %s, Addr: 0x%08X, Cnt: %d, Data:",
+				p_dev_name, p_bus_name, addr, len);
+
+			while (i--)
+				ntlog_helper_str_add(tmp_string, " 0x%08X", *ptr++);
+
+			ntlog_helper_str_add(tmp_string, ")");
+			NT_LOG(DBG, NTHW, "%s", tmp_string);
+			ntlog_helper_str_free(tmp_string);
+		}
+	}
+}
+
+uint32_t nthw_register_get_val_updated32(const nthw_register_t *p)
+{
+	uint32_t val = 0;
+
+	nthw_register_update(p);
+	nthw_register_get_val(p, &val, 1);
+	return val;
+}
+
+void nthw_register_make_dirty(nthw_register_t *p)
+{
+	uint32_t i;
+
+	for (i = 0; i < p->mn_len; i++)
+		p->mp_dirty[i] = true;
+}
+
+void nthw_register_set_val(nthw_register_t *p, const uint32_t *p_data, uint32_t len)
+{
+	assert(len <= p->mn_len);
+	assert(p_data);
+
+	if (len == (uint32_t)-1 || len > p->mn_len)
+		len = p->mn_len;
+
+	if (p->mp_shadow != p_data)
+		memcpy(p->mp_shadow, p_data, (len * sizeof(uint32_t)));
+}
+
+void nthw_register_flush(const nthw_register_t *p, uint32_t cnt)
+{
+	int rc;
+
+	if (p->mn_type != NTHW_FPGA_REG_TYPE_RO) {
+		const char *const p_dev_name = "NA";
+		const int n_bus_type_id = nthw_module_get_bus(p->mp_owner);
+		const char *p_bus_name = get_bus_name(n_bus_type_id);
+		const uint32_t addr = p->mn_addr;
+		const uint32_t len = p->mn_len;
+		uint32_t *const p_data = p->mp_shadow;
+		uint32_t i;
+
+		assert(len * cnt <= 256);
+
+		if (p->mn_debug_mode & NTHW_REG_DEBUG_ON_WRITE) {
+			uint32_t i = len * cnt;
+			uint32_t *ptr = p_data;
+			char *tmp_string = ntlog_helper_str_alloc("Register::write");
+
+			ntlog_helper_str_add(tmp_string,
+				"(Dev: %s, Bus: %s, Addr: 0x%08X, Cnt: %d, Data:",
+				p_dev_name, p_bus_name, addr, i);
+
+			while (i--)
+				ntlog_helper_str_add(tmp_string, " 0x%08X", *ptr++);
+
+			ntlog_helper_str_add(tmp_string, ")");
+			NT_LOG(DBG, NTHW, "%s", tmp_string);
+			ntlog_helper_str_free(tmp_string);
+		}
+
+		rc = nthw_register_write_data(p, cnt);
+
+		if (rc)
+			NT_LOG(ERR, NTHW, "Register write error %d\n", rc);
+
+		for (i = 0; i < cnt; i++)
+			p->mp_dirty[i] = false;
+	}
+}
+
+void nthw_register_clr(nthw_register_t *p)
+{
+	memset(p->mp_shadow, 0, p->mn_len * sizeof(uint32_t));
+	nthw_register_make_dirty(p);
+}
+
+/*
+ * Field
+ */
+nthw_field_t *nthw_field_new(void)
+{
+	nthw_field_t *p = malloc(sizeof(nthw_field_t));
+
+	return p;
+}
+
+void nthw_field_init(nthw_field_t *p, nthw_register_t *p_reg, const nthw_fpga_field_init_s *p_init)
+{
+	p->mp_owner = p_reg;
+
+	p->mn_debug_mode = p_reg->mn_debug_mode;
+
+	p->mn_id = p_init->id;
+	p->mn_bit_width = p_init->bw;
+	p->mn_bit_pos_low = p_init->low;
+	p->mn_reset_val = (uint32_t)p_init->reset_val;
+	p->mn_first_word = p_init->low / 32;
+	p->mn_first_bit = p_init->low % 32;
+	p->mn_front_mask = 0;
+	p->mn_body_length = 0;
+	p->mn_words = (p_init->bw + 0x1f) / 0x20;
+	p->mn_tail_mask = 0;
+
+	{
+		int bits_remaining = p_init->bw;
+		int front_mask_length = 32 - p->mn_first_bit;
+
+		if (front_mask_length > bits_remaining)
+			front_mask_length = bits_remaining;
+
+		bits_remaining -= front_mask_length;
+
+		p->mn_front_mask =
+			(uint32_t)(((1ULL << front_mask_length) - 1) << p->mn_first_bit);
+
+		p->mn_body_length = bits_remaining / 32;
+		bits_remaining -= p->mn_body_length * 32;
+		p->mn_tail_mask = (1 << bits_remaining) - 1;
+
+		if (p->mn_debug_mode >= 0x100) {
+			NT_LOG(DBG, NTHW,
+				"%s: fldid=%08d: [%08d:%08d] %08d/%08d: (%08d,%08d) (0x%08X,%08d,0x%08X)\n",
+				__func__, p_init->id, p_init->low, (p_init->low + p_init->bw),
+				p_init->bw, ((p_init->bw + 31) / 32), p->mn_first_word,
+				p->mn_first_bit, p->mn_front_mask, p->mn_body_length,
+				p->mn_tail_mask);
+		}
+	}
+}
+
+int nthw_field_get_debug_mode(const nthw_field_t *p)
+{
+	return p->mn_debug_mode;
+}
+
+void nthw_field_set_debug_mode(nthw_field_t *p, unsigned int debug_mode)
+{
+	p->mn_debug_mode = debug_mode;
+}
+
+int nthw_field_get_bit_width(const nthw_field_t *p)
+{
+	return p->mn_bit_width;
+}
+
+int nthw_field_get_bit_pos_low(const nthw_field_t *p)
+{
+	return p->mn_bit_pos_low;
+}
+
+int nthw_field_get_bit_pos_high(const nthw_field_t *p)
+{
+	return p->mn_bit_pos_low + p->mn_bit_width - 1;
+}
+
+uint32_t nthw_field_get_mask(const nthw_field_t *p)
+{
+	return p->mn_front_mask;
+}
+
+void nthw_field_reset(const nthw_field_t *p)
+{
+	nthw_field_set_val32(p, (uint32_t)p->mn_reset_val);
+}
+
+void nthw_field_get_val(const nthw_field_t *p, uint32_t *p_data, uint32_t len)
+{
+	uint32_t i;
+	uint32_t data_index = 0;
+	uint32_t shadow_index = p->mn_first_word;
+
+	union {
+		uint32_t w32[2];
+		uint64_t w64;
+	} buf;
+
+	(void)len;
+	assert(len <= p->mn_words);
+
+	/* handle front */
+	buf.w32[0] = p->mp_owner->mp_shadow[shadow_index++] & p->mn_front_mask;
+
+	/* handle body */
+	for (i = 0; i < p->mn_body_length; i++) {
+		buf.w32[1] = p->mp_owner->mp_shadow[shadow_index++];
+		buf.w64 = buf.w64 >> (p->mn_first_bit);
+		assert(data_index < len);
+		p_data[data_index++] = buf.w32[0];
+		buf.w64 = buf.w64 >> (32 - p->mn_first_bit);
+	}
+
+	/* handle tail */
+	if (p->mn_tail_mask)
+		buf.w32[1] = p->mp_owner->mp_shadow[shadow_index++] & p->mn_tail_mask;
+
+	else
+		buf.w32[1] = 0;
+
+	buf.w64 = buf.w64 >> (p->mn_first_bit);
+	p_data[data_index++] = buf.w32[0];
+
+	if (data_index < p->mn_words)
+		p_data[data_index++] = buf.w32[1];
+}
+
+void nthw_field_set_val(const nthw_field_t *p, const uint32_t *p_data, uint32_t len)
+{
+	uint32_t i;
+	uint32_t data_index = 0;
+	uint32_t shadow_index = p->mn_first_word;
+
+	union {
+		uint32_t w32[2];
+		uint64_t w64;
+	} buf;
+
+	(void)len;
+	assert(len == p->mn_words);
+
+	/* handle front */
+	buf.w32[0] = 0;
+	buf.w32[1] = p_data[data_index++];
+	buf.w64 = buf.w64 >> (32 - p->mn_first_bit);
+	p->mp_owner->mp_shadow[shadow_index] =
+		(p->mp_owner->mp_shadow[shadow_index] & ~p->mn_front_mask) |
+		(buf.w32[0] & p->mn_front_mask);
+	shadow_index++;
+
+	/* handle body */
+	for (i = 0; i < p->mn_body_length; i++) {
+		buf.w64 = buf.w64 >> (p->mn_first_bit);
+		assert(data_index < len);
+		buf.w32[1] = p_data[data_index++];
+		buf.w64 = buf.w64 >> (32 - p->mn_first_bit);
+		p->mp_owner->mp_shadow[shadow_index++] = buf.w32[0];
+	}
+
+	/* handle tail */
+	if (p->mn_tail_mask) {
+		buf.w64 = buf.w64 >> (p->mn_first_bit);
+
+		if (data_index < len)
+			buf.w32[1] = p_data[data_index];
+
+		buf.w64 = buf.w64 >> (32 - p->mn_first_bit);
+		p->mp_owner->mp_shadow[shadow_index] =
+			(p->mp_owner->mp_shadow[shadow_index] & ~p->mn_tail_mask) |
+			(buf.w32[0] & p->mn_tail_mask);
+	}
+
+	nthw_register_make_dirty(p->mp_owner);
+}
+
+void nthw_field_set_val_flush(const nthw_field_t *p, const uint32_t *p_data, uint32_t len)
+{
+	nthw_field_set_val(p, p_data, len);
+	nthw_field_flush_register(p);
+}
+
+uint32_t nthw_field_get_val32(const nthw_field_t *p)
+{
+	uint32_t val;
+
+	nthw_field_get_val(p, &val, 1);
+	return val;
+}
+
+uint32_t nthw_field_get_updated(const nthw_field_t *p)
+{
+	uint32_t val;
+
+	nthw_register_update(p->mp_owner);
+	nthw_field_get_val(p, &val, 1);
+
+	return val;
+}
+
+void nthw_field_update_register(const nthw_field_t *p)
+{
+	nthw_register_update(p->mp_owner);
+}
+
+void nthw_field_flush_register(const nthw_field_t *p)
+{
+	nthw_register_flush(p->mp_owner, 1);
+}
+
+void nthw_field_set_val32(const nthw_field_t *p, uint32_t val)
+{
+	nthw_field_set_val(p, &val, 1);
+}
+
+void nthw_field_set_val_flush32(const nthw_field_t *p, uint32_t val)
+{
+	nthw_field_set_val(p, &val, 1);
+	nthw_register_flush(p->mp_owner, 1);
+}
+
+void nthw_field_clr_all(const nthw_field_t *p)
+{
+	assert(p->mn_body_length == 0);
+	nthw_field_set_val32(p, 0);
+}
+
+void nthw_field_clr_flush(const nthw_field_t *p)
+{
+	nthw_field_clr_all(p);
+	nthw_register_flush(p->mp_owner, 1);
+}
+
+void nthw_field_set_all(const nthw_field_t *p)
+{
+	assert(p->mn_body_length == 0);
+	nthw_field_set_val32(p, ~0);
+}
+
+void nthw_field_set_flush(const nthw_field_t *p)
+{
+	nthw_field_set_all(p);
+	nthw_register_flush(p->mp_owner, 1);
+}
+
+enum nthw_field_match {
+	NTHW_FIELD_MATCH_CLR_ALL,
+	NTHW_FIELD_MATCH_SET_ALL,
+	NTHW_FIELD_MATCH_CLR_ANY,
+	NTHW_FIELD_MATCH_SET_ANY,
+};
+
+static int nthw_field_wait_cond32(const nthw_field_t *p, enum nthw_field_match e_match,
+	int n_poll_iterations, int n_poll_interval)
+{
+	const uint32_t n_mask = (1 << p->mn_bit_width) - 1;
+
+	if (n_poll_iterations == -1)
+		n_poll_iterations = 10000;
+
+	if (n_poll_interval == -1)
+		n_poll_interval = 100;	/* usec */
+
+	if (p->mn_debug_mode) {
+		const char *const p_cond_name =
+			((e_match == NTHW_FIELD_MATCH_SET_ALL)
+				? "SetAll"
+				: ((e_match == NTHW_FIELD_MATCH_CLR_ALL)
+					? "ClrAll"
+					: ((e_match == NTHW_FIELD_MATCH_CLR_ANY) ? "ClrAny"
+						: "SetAny")));
+		(void)p_cond_name;
+		const char *const p_dev_name = "NA";
+		(void)p_dev_name;
+		const char *const p_bus_name =
+			get_bus_name(nthw_module_get_bus(p->mp_owner->mp_owner));
+		(void)p_bus_name;
+		uint32_t n_reg_addr = nthw_register_get_address(p->mp_owner);
+		(void)n_reg_addr;
+		uint32_t n_reg_mask = (((1 << p->mn_bit_width) - 1) << p->mn_bit_pos_low);
+		(void)n_reg_mask;
+
+		NT_LOG(DBG, NTHW,
+			"Register::Field::wait%s32(Dev: %s, Bus: %s, Addr: 0x%08X, Mask: 0x%08X, Iterations: %d, Interval: %d)\n",
+			p_cond_name, p_dev_name, p_bus_name, n_reg_addr, n_reg_mask,
+			n_poll_iterations, n_poll_interval);
+	}
+
+	while (true) {
+		uint32_t val = nthw_field_get_updated(p);
+
+		if (e_match == NTHW_FIELD_MATCH_SET_ANY && val != 0) {
+			return 0;
+
+		} else if (e_match == NTHW_FIELD_MATCH_SET_ALL && val == n_mask) {
+			return 0;
+
+		} else if (e_match == NTHW_FIELD_MATCH_CLR_ALL && val == 0) {
+			return 0;
+
+		} else if (e_match == NTHW_FIELD_MATCH_CLR_ANY) {
+			uint32_t mask = nthw_field_get_mask(p);
+
+			if (val != mask)
+				return 0;
+		}
+
+		n_poll_iterations--;
+
+		if (n_poll_iterations <= 0)
+			return -1;
+
+		nt_os_wait_usec(n_poll_interval);
+	}
+
+	return 0;
+}
+
+int nthw_field_wait_set_all32(const nthw_field_t *p, int n_poll_iterations, int n_poll_interval)
+{
+	return nthw_field_wait_cond32(p, NTHW_FIELD_MATCH_SET_ALL, n_poll_iterations,
+			n_poll_interval);
+}
+
+int nthw_field_wait_clr_all32(const nthw_field_t *p, int n_poll_iterations, int n_poll_interval)
+{
+	return nthw_field_wait_cond32(p, NTHW_FIELD_MATCH_CLR_ALL, n_poll_iterations,
+			n_poll_interval);
+}
+
+int nthw_field_wait_set_any32(const nthw_field_t *p, int n_poll_iterations, int n_poll_interval)
+{
+	return nthw_field_wait_cond32(p, NTHW_FIELD_MATCH_SET_ANY, n_poll_iterations,
+			n_poll_interval);
+}
+
+/* EOF */
diff --git a/drivers/net/ntnic/nthw/model/nthw_fpga_model.h b/drivers/net/ntnic/nthw/model/nthw_fpga_model.h
new file mode 100644
index 0000000000..f9968362b7
--- /dev/null
+++ b/drivers/net/ntnic/nthw/model/nthw_fpga_model.h
@@ -0,0 +1,247 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef _NTHW_FPGA_MODEL_H_
+#define _NTHW_FPGA_MODEL_H_
+
+#include <stdbool.h>
+#include <stdio.h>
+#include "fpga_model.h"
+
+#define VERSION_PACKED64(_major_, _minor_)                                                        \
+	((((uint64_t)(_major_) & (0xFFFFFFFF)) << 32) | ((_minor_) & (0xFFFFFFFF)))
+
+enum nthw_reg_debug_mode {
+	NTHW_REG_DEBUG_NONE = 0,
+	NTHW_REG_DEBUG_ON_READ = 1,
+	NTHW_REG_DEBUG_ON_WRITE = 2,
+	NTHW_REG_TRACE_ON_READ = 4,
+	NTHW_REG_TRACE_ON_WRITE = 8,
+};
+
+struct nthw_fpga_s;
+
+struct nthw_param_s;
+
+struct nthw_module_s;
+
+struct nthw_register_s;
+
+struct nthw_field_s;
+
+struct nthw_fpga_mgr_s {
+	int mn_fpgas;
+	struct nthw_fpga_prod_init **mpa_fpga_prod_init;
+};
+
+typedef struct nthw_fpga_mgr_s nthw_fpga_mgr_t;
+
+struct nthw_fpga_s {
+	struct fpga_info_s *p_fpga_info;
+
+	int mn_item_id;
+	int mn_product_id;
+	int mn_fpga_version;
+	int mn_fpga_revision;
+	int mn_fpga_patch_no;
+	int mn_fpga_build_no;
+	uint32_t mn_fpga_build_time;
+
+	int mn_params;
+	struct nthw_param_s **mpa_params;
+
+	int mn_modules;
+	struct nthw_module_s **mpa_modules;
+
+	nthw_fpga_prod_init_s *mp_init;
+
+	int m_debug_mode;
+};
+
+typedef struct nthw_fpga_s nthw_fpga_t;
+
+struct nthw_param_s {
+	nthw_fpga_t *mp_owner;
+
+	nthw_id_t mn_param_id;
+	int mn_param_value;
+
+	nthw_fpga_prod_param_s *mp_init;
+};
+
+typedef struct nthw_param_s nthw_param_t;
+
+struct nthw_module_s {
+	nthw_fpga_t *mp_owner;
+
+	nthw_id_t mn_mod_id;
+
+	int mn_instance;
+
+	int mn_mod_def_id;
+	int mn_major_version;
+	int mn_minor_version;
+
+	int mn_bus;
+	uint32_t mn_addr_base;
+
+	int mn_debug_mode;
+
+	int mn_registers;
+	struct nthw_register_s **mpa_registers;
+
+	nthw_fpga_module_init_s *mp_init;
+};
+
+typedef struct nthw_module_s nthw_module_t;
+
+struct nthw_register_s {
+	nthw_module_t *mp_owner;
+
+	nthw_id_t mn_id;
+
+	uint32_t mn_bit_width;
+	uint32_t mn_addr_rel;
+	uint32_t mn_addr;
+	uint32_t mn_type;
+	uint32_t mn_len;
+
+	int mn_debug_mode;
+
+	int mn_fields;
+	struct nthw_field_s **mpa_fields;
+
+	uint32_t *mp_shadow;
+	bool *mp_dirty;
+
+	nthw_fpga_register_init_s *mp_init;
+};
+
+typedef struct nthw_register_s nthw_register_t;
+
+struct nthw_field_s {
+	nthw_register_t *mp_owner;
+
+	nthw_id_t mn_id;
+
+	uint32_t mn_bit_width;
+	uint32_t mn_bit_pos_low;
+	uint32_t mn_reset_val;
+	uint32_t mn_first_word;
+	uint32_t mn_first_bit;
+	uint32_t mn_front_mask;
+	uint32_t mn_body_length;
+	uint32_t mn_words;
+	uint32_t mn_tail_mask;
+
+	int mn_debug_mode;
+
+	nthw_fpga_field_init_s *mp_init;
+};
+
+typedef struct nthw_field_s nthw_field_t;
+
+int nthw_fpga_extract_type_id(const uint64_t n_fpga_ident);
+int nthw_fpga_extract_prod_id(const uint64_t n_fpga_ident);
+int nthw_fpga_extract_ver_id(const uint64_t n_fpga_ident);
+int nthw_fpga_extract_rev_id(const uint64_t n_fpga_ident);
+
+uint64_t nthw_fpga_read_ident(struct fpga_info_s *p_fpga_info);
+uint32_t nthw_fpga_read_buildtime(struct fpga_info_s *p_fpga_info);
+
+nthw_fpga_mgr_t *nthw_fpga_mgr_new(void);
+void nthw_fpga_mgr_init(nthw_fpga_mgr_t *p, struct nthw_fpga_prod_init **pa_nthw_fpga_instances,
+	const void *pa_mod_str_map);
+void nthw_fpga_mgr_delete(nthw_fpga_mgr_t *p);
+nthw_fpga_t *nthw_fpga_mgr_query_fpga(nthw_fpga_mgr_t *p, uint64_t n_fpga_id,
+	struct fpga_info_s *p_fpga_info);
+void nthw_fpga_mgr_log_dump(nthw_fpga_mgr_t *p);
+void nthw_fpga_mgr_show(nthw_fpga_mgr_t *p, FILE *out, int detail_level);
+
+nthw_fpga_t *nthw_fpga_model_new(void);
+void nthw_fpga_model_init(nthw_fpga_t *p, nthw_fpga_prod_init_s *p_init,
+	struct fpga_info_s *p_fpga_info);
+
+int nthw_fpga_get_product_param(const nthw_fpga_t *p, const nthw_id_t n_param_id,
+	const int default_value);
+int nthw_fpga_get_product_id(const nthw_fpga_t *p);
+
+nthw_module_t *nthw_fpga_query_module(const nthw_fpga_t *p, nthw_id_t id, int instance);
+void nthw_fpga_set_debug_mode(nthw_fpga_t *p, int n_debug_mode);
+
+nthw_param_t *nthw_param_new(void);
+void nthw_param_init(nthw_param_t *p, nthw_fpga_t *p_fpga, nthw_fpga_prod_param_s *p_init);
+
+nthw_module_t *nthw_module_new(void);
+void nthw_module_init(nthw_module_t *p, nthw_fpga_t *p_fpga, nthw_fpga_module_init_s *p_init);
+void nthw_module_init2(nthw_module_t *p, nthw_fpga_t *p_fpga, nthw_id_t mod_id, int instance,
+	int debug_mode);
+
+int nthw_module_get_major_version(const nthw_module_t *p);
+int nthw_module_get_minor_version(const nthw_module_t *p);
+uint64_t nthw_module_get_version_packed64(const nthw_module_t *p);
+bool nthw_module_is_version_newer(const nthw_module_t *p, int major_version, int minor_version);
+
+int nthw_module_get_bus(const nthw_module_t *p);
+nthw_register_t *nthw_module_query_register(nthw_module_t *p, nthw_id_t id);
+nthw_register_t *nthw_module_get_register(nthw_module_t *p, nthw_id_t id);
+int nthw_module_get_debug_mode(const nthw_module_t *p);
+void nthw_module_set_debug_mode(nthw_module_t *p, unsigned int debug_mode);
+
+nthw_register_t *nthw_register_new(void);
+void nthw_register_init(nthw_register_t *p, nthw_module_t *p_module,
+	nthw_fpga_register_init_s *p_init);
+
+nthw_field_t *nthw_register_query_field(const nthw_register_t *p, nthw_id_t id);
+nthw_field_t *nthw_register_get_field(const nthw_register_t *p, nthw_id_t id);
+
+uint32_t nthw_register_get_address(const nthw_register_t *p);
+int nthw_register_get_bit_width(const nthw_register_t *p);
+int nthw_register_get_debug_mode(const nthw_register_t *p);
+void nthw_register_set_debug_mode(nthw_register_t *p, unsigned int debug_mode);
+
+void nthw_register_get_val(const nthw_register_t *p, uint32_t *p_data, uint32_t len);
+uint32_t nthw_register_get_val32(const nthw_register_t *p);
+uint32_t nthw_register_get_val_updated32(const nthw_register_t *p);
+
+void nthw_register_set_val(nthw_register_t *p, const uint32_t *p_data, uint32_t len);
+
+void nthw_register_make_dirty(nthw_register_t *p);
+void nthw_register_update(const nthw_register_t *p);
+void nthw_register_reset(const nthw_register_t *p);
+void nthw_register_flush(const nthw_register_t *p, uint32_t cnt);
+void nthw_register_clr(nthw_register_t *p);
+
+nthw_field_t *nthw_field_new(void);
+void nthw_field_init(nthw_field_t *p, nthw_register_t *p_reg,
+	const nthw_fpga_field_init_s *p_init);
+
+int nthw_field_get_debug_mode(const nthw_field_t *p);
+void nthw_field_set_debug_mode(nthw_field_t *p, unsigned int n_debug_mode);
+int nthw_field_get_bit_width(const nthw_field_t *p);
+int nthw_field_get_bit_pos_low(const nthw_field_t *p);
+int nthw_field_get_bit_pos_high(const nthw_field_t *p);
+uint32_t nthw_field_get_mask(const nthw_field_t *p);
+void nthw_field_reset(const nthw_field_t *p);
+void nthw_field_get_val(const nthw_field_t *p, uint32_t *p_data, uint32_t len);
+void nthw_field_set_val(const nthw_field_t *p, const uint32_t *p_data, uint32_t len);
+void nthw_field_set_val_flush(const nthw_field_t *p, const uint32_t *p_data, uint32_t len);
+uint32_t nthw_field_get_val32(const nthw_field_t *p);
+uint32_t nthw_field_get_updated(const nthw_field_t *p);
+void nthw_field_update_register(const nthw_field_t *p);
+void nthw_field_flush_register(const nthw_field_t *p);
+void nthw_field_set_val32(const nthw_field_t *p, uint32_t val);
+void nthw_field_set_val_flush32(const nthw_field_t *p, uint32_t val);
+void nthw_field_clr_all(const nthw_field_t *p);
+void nthw_field_clr_flush(const nthw_field_t *p);
+void nthw_field_set_all(const nthw_field_t *p);
+void nthw_field_set_flush(const nthw_field_t *p);
+
+int nthw_field_wait_clr_all32(const nthw_field_t *p, int n_poll_iterations, int n_poll_interval);
+int nthw_field_wait_set_all32(const nthw_field_t *p, int n_poll_iterations, int n_poll_interval);
+
+int nthw_field_wait_set_any32(const nthw_field_t *p, int n_poll_iterations, int n_poll_interval);
+
+#endif	/* _NTHW_FPGA_MODEL_H_ */
-- 
2.44.0


^ permalink raw reply	[flat|nested] 238+ messages in thread

* [PATCH v1 05/17] net/ntnic: add NTNIC adapter interfaces
  2024-05-30 14:48 [PATCH v1 01/17] net/ntnic: Add registers for NapaTech SmartNiC Serhii Iliushyk
                   ` (2 preceding siblings ...)
  2024-05-30 14:49 ` [PATCH v1 04/17] net/ntnic: add FPGA model implementation Serhii Iliushyk
@ 2024-05-30 14:49 ` Serhii Iliushyk
  2024-05-30 14:49 ` [PATCH v1 06/17] net/ntnic: add interfaces for PMD driver modules Serhii Iliushyk
                   ` (20 subsequent siblings)
  24 siblings, 0 replies; 238+ messages in thread
From: Serhii Iliushyk @ 2024-05-30 14:49 UTC (permalink / raw)
  To: dev; +Cc: mko-plv, ckm, andrew.rybchenko, ferruh.yigit

Add ntnic adapter interfaces structures.

Signed-off-by: Serhii Iliushyk <sil-plv@napatech.com>
---
 .../ntnic/include/clock_profiles_structs.h    |  69 +++++++
 .../net/ntnic/include/common_adapter_defs.h   |  15 ++
 drivers/net/ntnic/include/fpga_model.h        | 153 +++++++++++++++
 drivers/net/ntnic/include/nt4ga_adapter.h     | 105 ++++++++++
 drivers/net/ntnic/include/nt4ga_pci_ta_tg.h   |  42 ++++
 drivers/net/ntnic/include/nt4ga_tfg.h         |  18 ++
 drivers/net/ntnic/include/ntdrv_4ga.h         |  33 ++++
 drivers/net/ntnic/include/nthw_bus.h          |  20 ++
 drivers/net/ntnic/include/ntos_drv.h          | 180 ++++++++++++++++++
 drivers/net/ntnic/include/ntos_system.h       |  25 +++
 drivers/net/ntnic/include/ntoss_virt_queue.h  | 163 ++++++++++++++++
 11 files changed, 823 insertions(+)
 create mode 100644 drivers/net/ntnic/include/clock_profiles_structs.h
 create mode 100644 drivers/net/ntnic/include/common_adapter_defs.h
 create mode 100644 drivers/net/ntnic/include/fpga_model.h
 create mode 100644 drivers/net/ntnic/include/nt4ga_adapter.h
 create mode 100644 drivers/net/ntnic/include/nt4ga_pci_ta_tg.h
 create mode 100644 drivers/net/ntnic/include/nt4ga_tfg.h
 create mode 100644 drivers/net/ntnic/include/ntdrv_4ga.h
 create mode 100644 drivers/net/ntnic/include/nthw_bus.h
 create mode 100644 drivers/net/ntnic/include/ntos_drv.h
 create mode 100644 drivers/net/ntnic/include/ntos_system.h
 create mode 100644 drivers/net/ntnic/include/ntoss_virt_queue.h

diff --git a/drivers/net/ntnic/include/clock_profiles_structs.h b/drivers/net/ntnic/include/clock_profiles_structs.h
new file mode 100644
index 0000000000..0f967453aa
--- /dev/null
+++ b/drivers/net/ntnic/include/clock_profiles_structs.h
@@ -0,0 +1,69 @@
+/* */
+/* clock_profiles_structs.h */
+/* */
+
+/*
+ * %NT_SOFTWARE_LICENSE%
+ */
+
+#ifndef _NT_CLOCK_PROFILES_STRUCTS_H_
+#define _NT_CLOCK_PROFILES_STRUCTS_H_
+
+/* */
+/* */
+/* */
+#include <stdint.h>
+
+/* */
+/* */
+/* */
+#define GET_VAR_NAME(var) #var
+
+#define clk_profile_size_error_msg "Size test failed"
+
+/* */
+/* */
+/* */
+struct clk_profile_data_fmt0_s {
+	unsigned char reg_addr;
+	unsigned char reg_val;
+	unsigned char reg_mask;
+};
+
+struct clk_profile_data_fmt1_s {
+	uint16_t reg_addr;
+	uint8_t reg_val;
+};
+
+struct clk_profile_data_fmt2_s {
+	unsigned int reg_addr;
+	unsigned char reg_val;
+};
+
+struct clk_profile_data_fmt3_s {
+	unsigned int address;
+	unsigned int data;
+};
+
+typedef struct clk_profile_data_fmt0_s clk_profile_data_fmt0_t;
+typedef struct clk_profile_data_fmt1_s clk_profile_data_fmt1_t;
+typedef struct clk_profile_data_fmt2_s clk_profile_data_fmt2_t;
+typedef struct clk_profile_data_fmt3_s clk_profile_data_fmt3_t;
+
+enum clk_profile_data_fmt_e {
+	clk_profile_data_fmt_0,
+	clk_profile_data_fmt_1,
+	clk_profile_data_fmt_2,
+	clk_profile_data_fmt_3,
+};
+
+typedef enum clk_profile_data_fmt_e clk_profile_data_fmt_t;
+
+/* */
+/* */
+/* */
+#endif	/* _NT_CLOCK_PROFILES_STRUCTS_H_ */
+
+/* */
+/* EOF */
+/* */
diff --git a/drivers/net/ntnic/include/common_adapter_defs.h b/drivers/net/ntnic/include/common_adapter_defs.h
new file mode 100644
index 0000000000..6ed9121f0f
--- /dev/null
+++ b/drivers/net/ntnic/include/common_adapter_defs.h
@@ -0,0 +1,15 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef _COMMON_ADAPTER_DEFS_H_
+#define _COMMON_ADAPTER_DEFS_H_
+
+/*
+ * Declarations shared by NT adapter types.
+ */
+#define NUM_ADAPTER_MAX (8)
+#define NUM_ADAPTER_PORTS_MAX (128)
+
+#endif	/* _COMMON_ADAPTER_DEFS_H_ */
diff --git a/drivers/net/ntnic/include/fpga_model.h b/drivers/net/ntnic/include/fpga_model.h
new file mode 100644
index 0000000000..3d6610a41b
--- /dev/null
+++ b/drivers/net/ntnic/include/fpga_model.h
@@ -0,0 +1,153 @@
+/* */
+/* fpga_model.h */
+/* */
+
+#ifndef _FPGA_MODEL_H_
+#define _FPGA_MODEL_H_
+
+/* */
+/* */
+/* */
+#ifdef __cplusplus
+#include <cstdint>
+#else
+#ifndef __KERNEL__
+#include <unistd.h>
+#include <stdint.h>
+#include <inttypes.h>
+#else
+#include <linux/types.h>
+#endif	/* __KERNEL__ */
+#endif	/* __cplusplus */
+
+/* */
+/* */
+/* */
+
+typedef uint32_t nthw_id_t;
+
+/* */
+/* */
+/* */
+enum nthw_fpga_bus_type {
+	NTHW_FPGA_BUS_TYPE_UNKNOWN =
+		0,	/* Unknown/uninitialized - keep this as the first enum element */
+	NTHW_FPGA_BUS_TYPE_BAR,
+	NTHW_FPGA_BUS_TYPE_PCI,
+	NTHW_FPGA_BUS_TYPE_CCIP,
+	NTHW_FPGA_BUS_TYPE_RAB0,
+	NTHW_FPGA_BUS_TYPE_RAB1,
+	NTHW_FPGA_BUS_TYPE_RAB2,
+	NTHW_FPGA_BUS_TYPE_NMB,
+	NTHW_FPGA_BUS_TYPE_NDM,
+	NTHW_FPGA_BUS_TYPE_SPI0,
+	NTHW_FPGA_BUS_TYPE_SPI = NTHW_FPGA_BUS_TYPE_SPI0,
+};
+
+typedef enum nthw_fpga_bus_type nthw_fpga_bus_type_e;
+
+/* */
+/* */
+/* */
+enum nthw_fpga_register_type {
+	NTHW_FPGA_REG_TYPE_UNKNOWN =
+		0,	/* Unknown/uninitialized - keep this as the first enum element */
+	NTHW_FPGA_REG_TYPE_RW,
+	NTHW_FPGA_REG_TYPE_RO,
+	NTHW_FPGA_REG_TYPE_WO,
+	NTHW_FPGA_REG_TYPE_RC1,
+	NTHW_FPGA_REG_TYPE_MIXED,
+};
+
+typedef enum nthw_fpga_register_type nthw_fpga_register_type_e;
+
+/* */
+/* */
+/* */
+struct nthw_fpga_field_init {
+	nthw_id_t id;
+	/* */
+	uint16_t bw;
+	uint16_t low;
+	uint64_t reset_val;
+};
+
+typedef struct nthw_fpga_field_init nthw_fpga_field_init_s;
+
+/* */
+/* */
+/* */
+struct nthw_fpga_register_init {
+	nthw_id_t id;
+	/* */
+	uint32_t addr_rel;
+	uint16_t bw;
+	nthw_fpga_register_type_e type;
+	uint64_t reset_val;
+	/* */
+	int nb_fields;
+	struct nthw_fpga_field_init *fields;
+};
+
+typedef struct nthw_fpga_register_init nthw_fpga_register_init_s;
+
+/* */
+/* */
+/* */
+struct nthw_fpga_module_init {
+	nthw_id_t id;
+	int instance;
+	/* */
+	nthw_id_t def_id;
+	int major_version;
+	int minor_version;
+	/* */
+	nthw_fpga_bus_type_e bus_id;
+	uint32_t addr_base;
+	/* */
+	int nb_registers;
+	struct nthw_fpga_register_init *registers;
+};
+
+typedef struct nthw_fpga_module_init nthw_fpga_module_init_s;
+
+/* */
+/* */
+/* */
+struct nthw_fpga_prod_param {
+	const nthw_id_t id;
+	const int value;
+};
+
+typedef struct nthw_fpga_prod_param nthw_fpga_prod_param_s;
+
+/* */
+/* */
+/* */
+struct nthw_fpga_prod_init {
+	int fpga_item_id;
+	int fpga_product_id;
+	int fpga_version;
+	int fpga_revision;
+	int fpga_patch_no;
+	int fpga_build_no;
+	uint32_t fpga_build_time;
+	/* */
+	int nb_prod_params;
+	struct nthw_fpga_prod_param *product_params;
+	/* */
+	int nb_modules;
+	struct nthw_fpga_module_init *modules;
+};
+
+typedef struct nthw_fpga_prod_init nthw_fpga_prod_init_s;
+
+/* */
+/* */
+/* */
+
+#endif	/* _FPGA_MODEL_H_ */
+
+/* */
+/* EOF */
+/* */
diff --git a/drivers/net/ntnic/include/nt4ga_adapter.h b/drivers/net/ntnic/include/nt4ga_adapter.h
new file mode 100644
index 0000000000..0722829529
--- /dev/null
+++ b/drivers/net/ntnic/include/nt4ga_adapter.h
@@ -0,0 +1,105 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef _NT4GA_ADAPTER_H_
+#define _NT4GA_ADAPTER_H_
+
+#include "common_adapter_defs.h"
+
+struct adapter_info_s;
+
+/*
+ * DN-0060 section 9
+ */
+typedef struct hw_info_s {
+	/* pciids */
+	uint16_t pci_vendor_id;
+	uint16_t pci_device_id;
+	uint16_t pci_sub_vendor_id;
+	uint16_t pci_sub_device_id;
+	uint16_t pci_class_id;
+
+	/* Derived from pciid */
+	nthw_adapter_id_t n_nthw_adapter_id;
+	int hw_platform_id;
+	int hw_product_type;
+	int hw_reserved1;
+} hw_info_t;
+
+/*
+ * Services provided by the adapter module
+ */
+#include "nt4ga_pci_ta_tg.h"
+#include "nt4ga_filter.h"
+#include "ntnic_stat.h"
+#include "nt4ga_tfg.h"
+#include "nt4ga_link.h"
+
+#include "nthw_spi_v3.h"
+#include "ntnic_nim.h"
+
+#include "ntnic_sensor.h"
+
+typedef struct adapter_info_s {
+	struct nt4ga_pci_ta_tg_s nt4ga_pci_ta_tg;
+	struct nt4ga_stat_s nt4ga_stat;
+	struct nt4ga_filter_s nt4ga_filter;
+	struct nt4ga_tfg_s nt4ga_tfg;
+	struct nt4ga_link_s nt4ga_link;
+
+	struct nthw_mcu *mp_nthw_mcu;
+
+	struct hw_info_s hw_info;
+	struct fpga_info_s fpga_info;
+
+	uint16_t adapter_sensors_cnt;
+	uint16_t nim_sensors_cnt[NUM_ADAPTER_PORTS_MAX];
+	struct nt_sensor_group *adapter_sensors;
+	struct nim_sensor_group *nim_sensors[NUM_ADAPTER_PORTS_MAX];
+
+	char *mp_port_id_str[NUM_ADAPTER_PORTS_MAX];
+	char *mp_adapter_id_str;
+	char *p_dev_name;
+	volatile bool *pb_shutdown;
+
+	int adapter_no;
+	int n_rx_host_buffers;
+	int n_tx_host_buffers;
+} adapter_info_t;
+
+/*
+ * Monitor task operations.  This structure defines the management hooks for
+ * Napatech network devices.  The following hooks can be defined; unless noted
+ * otherwise, they are optional and can be filled with a null pointer.
+ *
+ * int (*mto_open)(int adapter, int port);
+ *     The function to call when a network device transitions to the up state,
+ *     e.g., `ip link set <interface> up`.
+ *
+ * int (*mto_stop)(int adapter, int port);
+ *     The function to call when a network device transitions to the down state,
+ *     e.g., `ip link set <interface> down`.
+ */
+struct monitor_task_ops {
+	int (*mto_open)(int adapter, int port);
+	int (*mto_stop)(int adapter, int port);
+};
+
+#include <pthread.h>
+#include <signal.h>
+
+/* The file nt4ga_adapter.c defines the next four variables. */
+extern pthread_t monitor_tasks[NUM_ADAPTER_MAX];
+extern volatile int monitor_task_is_running[NUM_ADAPTER_MAX];
+
+/*
+ * Function that sets up signal handler(s) that stop the monitoring tasks.
+ */
+int set_up_signal_handlers_to_stop_monitoring_tasks(void);
+
+/* SPI for sensors reading */
+nthw_spis_t *new_sensors_t_spi(struct nthw_fpga_s *p_fpga);
+
+#endif	/* _NT4GA_ADAPTER_H_ */
diff --git a/drivers/net/ntnic/include/nt4ga_pci_ta_tg.h b/drivers/net/ntnic/include/nt4ga_pci_ta_tg.h
new file mode 100644
index 0000000000..b445a22930
--- /dev/null
+++ b/drivers/net/ntnic/include/nt4ga_pci_ta_tg.h
@@ -0,0 +1,42 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef _NT4GA_PCI_TA_TG_H_
+#define _NT4GA_PCI_TA_TG_H_
+
+#include <stdint.h>
+
+#define TA_TG_DBG_SHOW_SUMMARY (1)
+
+#define TG_NUM_PACKETS (8)
+#define TG_PKT_SIZE (2048 * 1)
+#define TG_AREA_SIZE (TG_NUM_PACKETS * TG_PKT_SIZE)
+
+#define TG_DELAY (200000)	/* usec */
+
+/* Struct predefinitions */
+struct adapter_info_s;
+struct nthw_hif_end_point_counters;
+
+struct nt4ga_pci_ta_tg_s {
+	struct nthw_pci_rd_tg *mp_nthw_pci_rd_tg;
+	struct nthw_pci_wr_tg *mp_nthw_pci_wr_tg;
+	struct nthw_pci_ta *mp_nthw_pci_ta;
+};
+
+typedef struct nt4ga_pci_ta_tg_s nt4ga_pci_ta_tg_t;
+typedef struct nt4ga_pci_ta_tg_s nt4ga_pci_ta_tg;
+
+int nt4ga_pci_ta_tg_init(struct adapter_info_s *p_adapter_info);
+
+int nt4ga_pci_ta_tg_measure_throughput_run(struct adapter_info_s *p_adapter_info,
+	struct nthw_hif_end_point_counters *pri,
+	struct nthw_hif_end_point_counters *sla);
+int nt4ga_pci_ta_tg_measure_throughput_main(struct adapter_info_s *p_adapter_info,
+	const uint8_t numa_node, const int direction,
+	const int n_pkt_size, const int n_batch_count,
+	const int n_delay);
+
+#endif	/* _NT4GA_PCI_TA_TG_H_ */
diff --git a/drivers/net/ntnic/include/nt4ga_tfg.h b/drivers/net/ntnic/include/nt4ga_tfg.h
new file mode 100644
index 0000000000..9797403dec
--- /dev/null
+++ b/drivers/net/ntnic/include/nt4ga_tfg.h
@@ -0,0 +1,18 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef NT4GA_TFG_H_
+#define NT4GA_TFG_H_
+
+typedef struct nt4ga_tfg_s {
+	nthw_mac_tfg_t *mp_nthw_mac_tfg;
+} nt4ga_tfg_t;
+
+int nt4ga_tfg_init(struct adapter_info_s *p_adapter_info);
+int nt4ga_tfg_setup(struct adapter_info_s *p_adapter_info, const int n_intf_no,
+	const int n_cmd_start_stop, const int n_frame_count, const int n_frame_size,
+	const int n_frame_fill_mode, const int n_frame_stream_id);
+
+#endif	/* NT4GA_TFG_H_ */
diff --git a/drivers/net/ntnic/include/ntdrv_4ga.h b/drivers/net/ntnic/include/ntdrv_4ga.h
new file mode 100644
index 0000000000..cae25ecfa6
--- /dev/null
+++ b/drivers/net/ntnic/include/ntdrv_4ga.h
@@ -0,0 +1,33 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef __NTDRV_4GA_H__
+#define __NTDRV_4GA_H__
+
+#include <rte_version.h>
+#include <rte_thread.h>
+#include "nthw_drv.h"
+#include "nt4ga_adapter.h"
+#include "nthw_platform_drv.h"
+
+typedef struct ntdrv_4ga_s {
+	uint32_t pciident;
+	struct adapter_info_s adapter_info;
+	char *p_drv_name;
+
+	volatile bool b_shutdown;
+	pthread_mutex_t stat_lck;
+#if RTE_VERSION_NUM(23, 11, 0, 0) < RTE_VERSION
+	rte_thread_t stat_thread;
+	rte_thread_t flm_thread;
+	rte_thread_t port_event_thread;
+#else
+	pthread_t stat_thread;
+	pthread_t flm_thread;
+	pthread_t port_event_thread;
+#endif
+} ntdrv_4ga_t;
+
+#endif	/* __NTDRV_4GA_H__ */
diff --git a/drivers/net/ntnic/include/nthw_bus.h b/drivers/net/ntnic/include/nthw_bus.h
new file mode 100644
index 0000000000..9d1532335b
--- /dev/null
+++ b/drivers/net/ntnic/include/nthw_bus.h
@@ -0,0 +1,20 @@
+/* */
+/* nthw_bus.h */
+/* */
+
+/* */
+/* */
+/* */
+#ifndef __NTHW_BUS_H__
+#define __NTHW_BUS_H__
+
+/* */
+/* */
+/* */
+typedef uint8_t nthw_rab_bus_id_t;
+
+#endif	/* __NTHW_BUS_H__ */
+
+/* */
+/* EOF */
+/* */
diff --git a/drivers/net/ntnic/include/ntos_drv.h b/drivers/net/ntnic/include/ntos_drv.h
new file mode 100644
index 0000000000..a181676593
--- /dev/null
+++ b/drivers/net/ntnic/include/ntos_drv.h
@@ -0,0 +1,180 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef __NTOS_DRV_H__
+#define __NTOS_DRV_H__
+
+#include <unistd.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <stdint.h>
+#include <inttypes.h>
+
+#include <rte_version.h>/* RTE_VERSION, RTE_VERSION_NUM */
+#include <rte_mtr_driver.h>
+
+#include "stream_binary_flow_api.h"
+#include "nthw_drv.h"
+#include "nthw_profile.h"
+
+#define NUM_MAC_ADDRS_PER_PORT (16U)
+#define NUM_MULTICAST_ADDRS_PER_PORT (16U)
+
+/* Max RSS queues */
+#define MAX_QUEUES 125
+
+/* Structs: */
+#define SG_HDR_SIZE 12
+
+struct _pkt_hdr_rx {
+	uint32_t cap_len : 14;
+	uint32_t fid : 10;
+	uint32_t ofs1 : 8;
+	uint32_t ip_prot : 8;
+	uint32_t port : 13;
+	uint32_t descr : 8;
+	uint32_t descr_12b : 1;
+	uint32_t color_type : 2;
+	uint32_t color : 32;
+};
+
+struct _pkt_hdr_tx {
+	uint32_t cap_len : 14;
+	uint32_t lso_cso0 : 9;
+	uint32_t lso_cso1 : 9;
+	uint32_t lso_cso2 : 8;
+	/* all 1's : use implicit in-port. 0-127 queue index. 0x80 + phy-port to phy */
+	uint32_t bypass_port : 13;
+	uint32_t descr : 8;
+	uint32_t descr_12b : 1;
+	uint32_t color_type : 2;
+	uint32_t color : 32;
+};
+
+/* Total max ports per NT NFV NIC */
+#define MAX_NTNIC_PORTS 2
+
+/* Total max VDPA ports */
+#define MAX_VDPA_PORTS 128UL
+
+struct nthw_memory_descriptor {
+	void *phys_addr;
+	void *virt_addr;
+	uint32_t len;
+};
+
+struct hwq_s {
+	int vf_num;
+	struct nthw_memory_descriptor virt_queues_ctrl;
+	struct nthw_memory_descriptor *pkt_buffers;
+};
+
+struct ntnic_rx_queue {
+	struct flow_queue_id_s queue;	/* queue info - user id and hw queue index */
+
+	struct rte_mempool *mb_pool;	/* mbuf memory pool */
+	uint16_t buf_size;	/* Size of data area in mbuf */
+	unsigned long rx_pkts;	/* Rx packet statistics */
+	unsigned long rx_bytes;	/* Rx bytes statistics */
+	unsigned long err_pkts;	/* Rx error packet statistics */
+	int enabled;	/* Enabling/disabling of this queue */
+
+	struct hwq_s hwq;
+	struct nthw_virt_queue *vq;
+	int nb_hw_rx_descr;
+	nt_meta_port_type_t type;
+	uint32_t port;	/* Rx port for this queue */
+	enum fpga_info_profile profile;	/* Vswitch / Inline / Capture */
+
+} __rte_cache_aligned;
+
+struct ntnic_tx_queue {
+	struct flow_queue_id_s queue;	/* queue info - user id and hw queue index */
+	struct hwq_s hwq;
+	struct nthw_virt_queue *vq;
+	int nb_hw_tx_descr;
+	/* Used for bypass in NTDVIO0 header on  Tx - pre calculated */
+	int target_id;
+	nt_meta_port_type_t type;
+	/* only used for exception tx queue from OVS SW switching */
+	int rss_target_id;
+
+	uint32_t port;	/* Tx port for this queue */
+	unsigned long tx_pkts;	/* Tx packet statistics */
+	unsigned long tx_bytes;	/* Tx bytes statistics */
+	unsigned long err_pkts;	/* Tx error packet stat */
+	int enabled;	/* Enabling/disabling of this queue */
+	enum fpga_info_profile profile;	/* Vswitch / Inline / Capture */
+} __rte_cache_aligned;
+
+struct nt_mtr_profile {
+	LIST_ENTRY(nt_mtr_profile) next;
+	uint32_t profile_id;
+	struct rte_mtr_meter_profile profile;
+};
+
+struct nt_mtr {
+	LIST_ENTRY(nt_mtr) next;
+	uint32_t mtr_id;
+	int shared;
+	struct nt_mtr_profile *profile;
+};
+
+enum virt_port_comm {
+	VIRT_PORT_NEGOTIATED_NONE,
+	VIRT_PORT_NEGOTIATED_SPLIT,
+	VIRT_PORT_NEGOTIATED_PACKED,
+	VIRT_PORT_USE_RELAY
+};
+
+struct pmd_internals {
+	const struct rte_pci_device *pci_dev;
+
+	struct flow_eth_dev *flw_dev;
+
+	char name[20];
+	char vhost_path[MAX_PATH_LEN];
+
+	int n_intf_no;
+	int if_index;
+
+	int lpbk_mode;
+
+	uint8_t ts_multiplier;
+	uint16_t min_tx_pkt_size;
+	uint16_t max_tx_pkt_size;
+
+	unsigned int nb_rx_queues;	/* Number of Rx queues configured */
+	unsigned int nb_tx_queues;	/* Number of Tx queues configured */
+	uint32_t port;
+	uint32_t port_id;
+	uint8_t vf_offset;	/* Offset of the VF from the PF */
+
+	nt_meta_port_type_t type;
+	struct flow_queue_id_s vpq[MAX_QUEUES];
+	unsigned int vpq_nb_vq;
+	int vhid;	/* if a virtual port type - the vhid */
+	enum virt_port_comm vport_comm;	/* link and how split,packed,relay */
+	uint32_t vlan;
+
+	struct ntnic_rx_queue rxq_scg[MAX_QUEUES];	/* Array of Rx queues */
+	struct ntnic_tx_queue txq_scg[MAX_QUEUES];	/* Array of Tx queues */
+
+	struct drv_s *p_drv;
+	/* Ethernet (MAC) addresses. Element number zero denotes default address. */
+	struct rte_ether_addr eth_addrs[NUM_MAC_ADDRS_PER_PORT];
+	/* Multicast ethernet (MAC) addresses. */
+	struct rte_ether_addr mc_addrs[NUM_MULTICAST_ADDRS_PER_PORT];
+
+	LIST_HEAD(_profiles, nt_mtr_profile) mtr_profiles;
+	LIST_HEAD(_mtrs, nt_mtr) mtrs;
+
+	uint64_t last_stat_rtc;
+	uint64_t rx_missed;
+
+	struct pmd_internals *next;
+};
+
+#endif	/* __NTOS_DRV_H__ */
diff --git a/drivers/net/ntnic/include/ntos_system.h b/drivers/net/ntnic/include/ntos_system.h
new file mode 100644
index 0000000000..cf4768799d
--- /dev/null
+++ b/drivers/net/ntnic/include/ntos_system.h
@@ -0,0 +1,25 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef __NTOS_SYSTEM_H__
+#define __NTOS_SYSTEM_H__
+
+#include "include/ntdrv_4ga.h"
+
+/*
+ * struct drv_s for DPDK (clone of kernel struct)
+ * keep it as close as possible to original kernel struct
+ */
+struct drv_s {
+	int adapter_no;
+	struct rte_pci_device *p_dev;
+	struct ntdrv_4ga_s ntdrv;
+
+	int n_eth_dev_init_count;
+	int probe_finished;
+	int setup_finished;
+};
+
+#endif	/* __NTOS_SYSTEM_H__ */
diff --git a/drivers/net/ntnic/include/ntoss_virt_queue.h b/drivers/net/ntnic/include/ntoss_virt_queue.h
new file mode 100644
index 0000000000..03d652066a
--- /dev/null
+++ b/drivers/net/ntnic/include/ntoss_virt_queue.h
@@ -0,0 +1,163 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef __NTOSS_VIRT_QUEUE_H__
+#define __NTOSS_VIRT_QUEUE_H__
+
+#include <stdint.h>
+#include <stdalign.h>
+
+#include "ntos_drv.h"
+struct nthw_virt_queue;
+
+#define ule64 uint64_t
+#define ule32 uint32_t
+#define ule16 uint16_t
+
+#define MAX_MSIX_VECTORS_PR_VF 8
+
+#define SPLIT_RING 0
+#define PACKED_RING 1
+#define IN_ORDER 1
+#define NO_ORDER_REQUIRED 0
+
+/*
+ * SPLIT : This marks a buffer as continuing via the next field.
+ * PACKED: This marks a buffer as continuing. (packed does not have a next field, so must be
+ * contiguous) In Used descriptors it must be ignored
+ */
+#define VIRTQ_DESC_F_NEXT 1
+/*
+ * SPLIT : This marks a buffer as device write-only (otherwise device read-only).
+ * PACKED: This marks a descriptor as device write-only (otherwise device read-only).
+ * PACKED: In a used descriptor, this bit is used to specify whether any data has been written by
+ * the device into any parts of the buffer.
+ */
+#define VIRTQ_DESC_F_WRITE 2
+/*
+ * SPLIT : This means the buffer contains a list of buffer descriptors.
+ * PACKED: This means the element contains a table of descriptors.
+ */
+#define VIRTQ_DESC_F_INDIRECT 4
+
+/*
+ * Split Ring virtq Descriptor
+ */
+#pragma pack(1)
+struct virtq_desc {
+	/* Address (guest-physical). */
+	ule64 addr;
+	/* Length. */
+	ule32 len;
+	/* The flags as indicated above. */
+	ule16 flags;
+	/* Next field if flags & NEXT */
+	ule16 next;
+};
+#pragma pack()
+
+/*
+ * Packed Ring special structures and defines
+ */
+
+#define MAX_PACKED_RING_ELEMENTS (1 << 15)	/* 32768 */
+
+/* additional packed ring flags */
+#define VIRTQ_DESC_F_AVAIL (1 << 7)
+#define VIRTQ_DESC_F_USED (1 << 15)
+
+/* descr phys address must be 16 byte aligned */
+#pragma pack(push, 16)
+struct pvirtq_desc {
+	/* Buffer Address. */
+	ule64 addr;
+	/* Buffer Length. */
+	ule32 len;
+	/* Buffer ID. */
+	ule16 id;
+	/* The flags depending on descriptor type. */
+	ule16 flags;
+};
+#pragma pack(pop)
+
+/* Enable events */
+#define RING_EVENT_FLAGS_ENABLE 0x0
+/* Disable events */
+#define RING_EVENT_FLAGS_DISABLE 0x1
+/*
+ * Enable events for a specific descriptor
+ * (as specified by Descriptor Ring Change Event Offset/Wrap Counter).
+ * Only valid if VIRTIO_F_RING_EVENT_IDX has been negotiated.
+ */
+#define RING_EVENT_FLAGS_DESC 0x2
+/* The value 0x3 is reserved */
+
+struct pvirtq_event_suppress {
+	union {
+		struct {
+			/* Descriptor Ring Change Event Offset */
+			ule16 desc_event_off : 15;
+			/* Descriptor Ring Change Event Wrap Counter */
+			ule16 desc_event_wrap : 1;
+		};
+		/* If desc_event_flags set to RING_EVENT_FLAGS_DESC */
+		ule16 desc;
+	};
+
+	/* phys address must be 4 byte aligned */
+#pragma pack(push, 16)
+	union {
+		struct {
+			ule16 desc_event_flags : 2;	/* Descriptor Ring Change Event Flags */
+			ule16 reserved : 14;	/* Reserved, set to 0 */
+		};
+		ule16 flags;
+	};
+};
+#pragma pack(pop)
+
+/*
+ * Common virtq descr
+ */
+#define vq_set_next(vq, index, nxt)                                                               \
+	do {                                                                                      \
+		struct nthw_cvirtq_desc *temp_vq = (vq);                                          \
+		if (temp_vq->vq_type == SPLIT_RING)                                               \
+			temp_vq->s[index].next = nxt;                                             \
+	} while (0)
+
+#define vq_set_flags(vq, index, flgs)                                                             \
+	do {                                                                                      \
+		struct nthw_cvirtq_desc *temp_vq = (vq);                                          \
+		uint32_t temp_flags = (flgs);                                                     \
+		uint32_t temp_index = (index);                                                    \
+		if ((temp_vq)->vq_type == SPLIT_RING)                                             \
+			(temp_vq)->s[temp_index].flags = temp_flags;                              \
+		else if ((temp_vq)->vq_type == PACKED_RING)                                       \
+			(temp_vq)->p[temp_index].flags = temp_flags;                              \
+	} while (0)
+
+struct nthw_virtq_desc_buf {
+	/* Address (guest-physical). */
+	alignas(16) ule64 addr;
+	/* Length. */
+	ule32 len;
+};
+
+struct nthw_cvirtq_desc {
+	union {
+		struct nthw_virtq_desc_buf *b;	/* buffer part as is common */
+		struct virtq_desc *s;	/* SPLIT */
+		struct pvirtq_desc *p;	/* PACKED */
+	};
+	uint16_t vq_type;
+};
+
+struct nthw_received_packets {
+	void *addr;
+	uint32_t len;
+};
+
+#endif	/* __NTOSS_VIRT_QUEUE_H__ */
-- 
2.44.0


^ permalink raw reply	[flat|nested] 238+ messages in thread

* [PATCH v1 06/17] net/ntnic: add interfaces for PMD driver modules
  2024-05-30 14:48 [PATCH v1 01/17] net/ntnic: Add registers for NapaTech SmartNiC Serhii Iliushyk
                   ` (3 preceding siblings ...)
  2024-05-30 14:49 ` [PATCH v1 05/17] net/ntnic: add NTNIC adapter interfaces Serhii Iliushyk
@ 2024-05-30 14:49 ` Serhii Iliushyk
  2024-05-30 14:49 ` [PATCH v1 07/17] net/ntnic: add API " Serhii Iliushyk
                   ` (19 subsequent siblings)
  24 siblings, 0 replies; 238+ messages in thread
From: Serhii Iliushyk @ 2024-05-30 14:49 UTC (permalink / raw)
  To: dev; +Cc: mko-plv, ckm, andrew.rybchenko, ferruh.yigit

Add ntnic base interfaces for: link, NIM, sensors, statistics.

Signed-off-by: Serhii Iliushyk <sil-plv@napatech.com>
---
 drivers/net/ntnic/include/nt4ga_link.h        | 132 +++++
 drivers/net/ntnic/include/ntnic_dbs.h         | 356 ++++++++++++
 drivers/net/ntnic/include/ntnic_nim.h         | 160 ++++++
 .../include/ntnic_nthw_fpga_rst_nt200a0x.h    |  82 +++
 drivers/net/ntnic/include/ntnic_sensor.h      | 515 ++++++++++++++++++
 drivers/net/ntnic/include/ntnic_stat.h        | 291 ++++++++++
 6 files changed, 1536 insertions(+)
 create mode 100644 drivers/net/ntnic/include/nt4ga_link.h
 create mode 100644 drivers/net/ntnic/include/ntnic_dbs.h
 create mode 100644 drivers/net/ntnic/include/ntnic_nim.h
 create mode 100644 drivers/net/ntnic/include/ntnic_nthw_fpga_rst_nt200a0x.h
 create mode 100644 drivers/net/ntnic/include/ntnic_sensor.h
 create mode 100644 drivers/net/ntnic/include/ntnic_stat.h

diff --git a/drivers/net/ntnic/include/nt4ga_link.h b/drivers/net/ntnic/include/nt4ga_link.h
new file mode 100644
index 0000000000..49e1c5d672
--- /dev/null
+++ b/drivers/net/ntnic/include/nt4ga_link.h
@@ -0,0 +1,132 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef NT4GA_LINK_H_
+#define NT4GA_LINK_H_
+
+#include "common_adapter_defs.h"
+#include "nthw_drv.h"
+#include "ntnic_nim.h"
+#include "ntnic_nthw_fpga_rst_nt200a0x.h"
+
+/*
+ * Link state.\n
+ * Just after start of ntservice the link state might be unknown since the
+ * monitoring routine is busy reading NIM state and NIM data. This might also
+ * be the case after a NIM is plugged into an interface.
+ * The error state indicates a HW reading error.
+ */
+enum nt_link_state_e {
+	NT_LINK_STATE_UNKNOWN = 0,	/* The link state has not been read yet */
+	NT_LINK_STATE_DOWN = 1,	/* The link state is DOWN */
+	NT_LINK_STATE_UP = 2,	/* The link state is UP */
+	NT_LINK_STATE_ERROR = 3	/* The link state could not be read */
+};
+
+typedef enum nt_link_state_e nt_link_state_t, *nt_link_state_p;
+
+/*
+ * Link duplex mode
+ */
+enum nt_link_duplex_e {
+	NT_LINK_DUPLEX_UNKNOWN = 0,
+	NT_LINK_DUPLEX_HALF = 0x01,	/* Half duplex */
+	NT_LINK_DUPLEX_FULL = 0x02,	/* Full duplex */
+};
+
+typedef enum nt_link_duplex_e nt_link_duplex_t;
+
+/*
+ * Link loopback mode
+ */
+enum nt_link_loopback_e {
+	NT_LINK_LOOPBACK_OFF = 0,
+	NT_LINK_LOOPBACK_HOST = 0x01,	/* Host loopback mode */
+	NT_LINK_LOOPBACK_LINE = 0x02,	/* Line loopback mode */
+};
+
+/*
+ * Link MDI mode
+ */
+enum nt_link_mdi_e {
+	NT_LINK_MDI_NA = 0,
+	NT_LINK_MDI_AUTO = 0x01,/* MDI auto */
+	NT_LINK_MDI_MDI = 0x02,	/* MDI mode */
+	NT_LINK_MDI_MDIX = 0x04,/* MDIX mode */
+};
+
+typedef enum nt_link_mdi_e nt_link_mdi_t;
+
+/*
+ * Link Auto/Manual mode
+ */
+enum nt_link_auto_neg_e {
+	NT_LINK_AUTONEG_NA = 0,
+	NT_LINK_AUTONEG_MANUAL = 0x01,
+	NT_LINK_AUTONEG_OFF = NT_LINK_AUTONEG_MANUAL,	/* Auto negotiation OFF */
+	NT_LINK_AUTONEG_AUTO = 0x02,
+	NT_LINK_AUTONEG_ON = NT_LINK_AUTONEG_AUTO,	/* Auto negotiation ON */
+};
+
+typedef enum nt_link_auto_neg_e nt_link_auto_neg_t;
+
+/*
+ * Callback functions to setup mac, pcs and phy
+ */
+typedef struct link_state_s {
+	bool link_disabled;
+	bool nim_present;
+	bool lh_nim_absent;
+	bool link_up;
+	enum nt_link_state_e link_state;
+	enum nt_link_state_e link_state_latched;
+} link_state_t;
+
+/*
+ * Link speed.
+ * Note this is a bitmask.
+ */
+enum nt_link_speed_e {
+	NT_LINK_SPEED_UNKNOWN = 0,
+	NT_LINK_SPEED_10M = 0x01,	/* 10 Mbps */
+	NT_LINK_SPEED_100M = 0x02,	/* 100 Mbps */
+	NT_LINK_SPEED_1G = 0x04,/* 1 Gbps  (Autoneg only) */
+	NT_LINK_SPEED_10G = 0x08,	/* 10 Gbps (Autoneg only) */
+	NT_LINK_SPEED_40G = 0x10,	/* 40 Gbps (Autoneg only) */
+	NT_LINK_SPEED_100G = 0x20,	/* 100 Gbps (Autoneg only) */
+	NT_LINK_SPEED_50G = 0x40,	/* 50 Gbps (Autoneg only) */
+	NT_LINK_SPEED_25G = 0x80,	/* 25 Gbps (Autoneg only) */
+	NT_LINK_SPEED_END	/* always keep this entry as the last in enum */
+};
+typedef enum nt_link_speed_e nt_link_speed_t;
+
+typedef struct link_info_s {
+	enum nt_link_speed_e link_speed;
+	enum nt_link_duplex_e link_duplex;
+	enum nt_link_auto_neg_e link_auto_neg;
+} link_info_t;
+
+typedef struct port_action_s {
+	bool port_disable;
+	enum nt_link_speed_e port_speed;
+	enum nt_link_duplex_e port_duplex;
+	uint32_t port_lpbk_mode;
+} port_action_t;
+
+typedef union adapter_var_s {
+	nim_i2c_ctx_t nim_ctx[NUM_ADAPTER_PORTS_MAX];	/* First field in all the adaptors type */
+} adapter_var_u;
+
+typedef struct nt4ga_link_s {
+	link_state_t link_state[NUM_ADAPTER_PORTS_MAX];
+	link_info_t link_info[NUM_ADAPTER_PORTS_MAX];
+	port_action_t port_action[NUM_ADAPTER_PORTS_MAX];
+	uint32_t speed_capa;
+	/* */
+	bool variables_initialized;
+	adapter_var_u u;
+} nt4ga_link_t;
+
+#endif	/* NT4GA_LINK_H_ */
diff --git a/drivers/net/ntnic/include/ntnic_dbs.h b/drivers/net/ntnic/include/ntnic_dbs.h
new file mode 100644
index 0000000000..cf3cc46024
--- /dev/null
+++ b/drivers/net/ntnic/include/ntnic_dbs.h
@@ -0,0 +1,356 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef _NTNIC_DBS_H_
+#define _NTNIC_DBS_H_
+
+#include "nthw_fpga_model.h"
+
+#define NT_DBS_RX_QUEUES_MAX (128)
+#define NT_DBS_TX_QUEUES_MAX (128)
+
+/*
+ * Struct for implementation of memory bank shadows
+ */
+
+/* DBS_RX_AM_DATA */
+struct nthw_dbs_rx_am_data_s {
+	uint64_t guest_physical_address;
+	uint32_t enable;
+	uint32_t host_id;
+	uint32_t packed;
+	uint32_t int_enable;
+};
+
+/* DBS_TX_AM_DATA */
+struct nthw_dbs_tx_am_data_s {
+	uint64_t guest_physical_address;
+	uint32_t enable;
+	uint32_t host_id;
+	uint32_t packed;
+	uint32_t int_enable;
+};
+
+/* DBS_RX_UW_DATA */
+struct nthw_dbs_rx_uw_data_s {
+	uint64_t guest_physical_address;
+	uint32_t host_id;
+	uint32_t queue_size;
+	uint32_t packed;
+	uint32_t int_enable;
+	uint32_t vec;
+	uint32_t istk;
+};
+
+/* DBS_TX_UW_DATA */
+struct nthw_dbs_tx_uw_data_s {
+	uint64_t guest_physical_address;
+	uint32_t host_id;
+	uint32_t queue_size;
+	uint32_t packed;
+	uint32_t int_enable;
+	uint32_t vec;
+	uint32_t istk;
+	uint32_t in_order;
+};
+
+/* DBS_RX_DR_DATA */
+struct nthw_dbs_rx_dr_data_s {
+	uint64_t guest_physical_address;
+	uint32_t host_id;
+	uint32_t queue_size;
+	uint32_t header;
+	uint32_t packed;
+};
+
+/* DBS_TX_DR_DATA */
+struct nthw_dbs_tx_dr_data_s {
+	uint64_t guest_physical_address;
+	uint32_t host_id;
+	uint32_t queue_size;
+	uint32_t header;
+	uint32_t port;
+	uint32_t packed;
+};
+
+/* DBS_TX_QP_DATA */
+struct nthw_dbs_tx_qp_data_s {
+	uint32_t virtual_port;
+};
+
+struct nthw_dbs_tx_qos_data_s {
+	uint32_t enable;
+	uint32_t ir;
+	uint32_t bs;
+};
+
+struct nthw_dbs_s {
+	nthw_fpga_t *mp_fpga;
+	nthw_module_t *mp_mod_dbs;
+	int mn_instance;
+
+	int mn_param_dbs_present;
+
+	nthw_register_t *mp_reg_rx_control;
+	nthw_field_t *mp_fld_rx_control_last_queue;
+	nthw_field_t *mp_fld_rx_control_avail_monitor_enable;
+	nthw_field_t *mp_fld_rx_control_avail_monitor_scan_speed;
+	nthw_field_t *mp_fld_rx_control_used_write_enable;
+	nthw_field_t *mp_fld_rx_control_used_writer_update_speed;
+	nthw_field_t *mp_fld_rx_control_rx_queues_enable;
+
+	nthw_register_t *mp_reg_tx_control;
+	nthw_field_t *mp_fld_tx_control_last_queue;
+	nthw_field_t *mp_fld_tx_control_avail_monitor_enable;
+	nthw_field_t *mp_fld_tx_control_avail_monitor_scan_speed;
+	nthw_field_t *mp_fld_tx_control_used_write_enable;
+	nthw_field_t *mp_fld_tx_control_used_writer_update_speed;
+	nthw_field_t *mp_fld_tx_control_tx_queues_enable;
+
+	nthw_register_t *mp_reg_rx_init;
+	nthw_field_t *mp_fld_rx_init_init;
+	nthw_field_t *mp_fld_rx_init_queue;
+	nthw_field_t *mp_fld_rx_init_busy;
+
+	nthw_register_t *mp_reg_rx_init_val;
+	nthw_field_t *mp_fld_rx_init_val_idx;
+	nthw_field_t *mp_fld_rx_init_val_ptr;
+
+	nthw_register_t *mp_reg_rx_ptr;
+	nthw_field_t *mp_fld_rx_ptr_ptr;
+	nthw_field_t *mp_fld_rx_ptr_queue;
+	nthw_field_t *mp_fld_rx_ptr_valid;
+
+	nthw_register_t *mp_reg_tx_init;
+	nthw_field_t *mp_fld_tx_init_init;
+	nthw_field_t *mp_fld_tx_init_queue;
+	nthw_field_t *mp_fld_tx_init_busy;
+
+	nthw_register_t *mp_reg_tx_init_val;
+	nthw_field_t *mp_fld_tx_init_val_idx;
+	nthw_field_t *mp_fld_tx_init_val_ptr;
+
+	nthw_register_t *mp_reg_tx_ptr;
+	nthw_field_t *mp_fld_tx_ptr_ptr;
+	nthw_field_t *mp_fld_tx_ptr_queue;
+	nthw_field_t *mp_fld_tx_ptr_valid;
+
+	nthw_register_t *mp_reg_rx_idle;
+	nthw_field_t *mp_fld_rx_idle_idle;
+	nthw_field_t *mp_fld_rx_idle_queue;
+	nthw_field_t *mp_fld_rx_idle_busy;
+
+	nthw_register_t *mp_reg_tx_idle;
+	nthw_field_t *mp_fld_tx_idle_idle;
+	nthw_field_t *mp_fld_tx_idle_queue;
+	nthw_field_t *mp_fld_tx_idle_busy;
+
+	nthw_register_t *mp_reg_rx_avail_monitor_control;
+	nthw_field_t *mp_fld_rx_avail_monitor_control_adr;
+	nthw_field_t *mp_fld_rx_avail_monitor_control_cnt;
+
+	nthw_register_t *mp_reg_rx_avail_monitor_data;
+	nthw_field_t *mp_fld_rx_avail_monitor_data_guest_physical_address;
+	nthw_field_t *mp_fld_rx_avail_monitor_data_enable;
+	nthw_field_t *mp_fld_rx_avail_monitor_data_host_id;
+	nthw_field_t *mp_fld_rx_avail_monitor_data_packed;
+	nthw_field_t *mp_fld_rx_avail_monitor_data_int;
+
+	nthw_register_t *mp_reg_tx_avail_monitor_control;
+	nthw_field_t *mp_fld_tx_avail_monitor_control_adr;
+	nthw_field_t *mp_fld_tx_avail_monitor_control_cnt;
+
+	nthw_register_t *mp_reg_tx_avail_monitor_data;
+	nthw_field_t *mp_fld_tx_avail_monitor_data_guest_physical_address;
+	nthw_field_t *mp_fld_tx_avail_monitor_data_enable;
+	nthw_field_t *mp_fld_tx_avail_monitor_data_host_id;
+	nthw_field_t *mp_fld_tx_avail_monitor_data_packed;
+	nthw_field_t *mp_fld_tx_avail_monitor_data_int;
+
+	nthw_register_t *mp_reg_rx_used_writer_control;
+	nthw_field_t *mp_fld_rx_used_writer_control_adr;
+	nthw_field_t *mp_fld_rx_used_writer_control_cnt;
+
+	nthw_register_t *mp_reg_rx_used_writer_data;
+	nthw_field_t *mp_fld_rx_used_writer_data_guest_physical_address;
+	nthw_field_t *mp_fld_rx_used_writer_data_host_id;
+	nthw_field_t *mp_fld_rx_used_writer_data_queue_size;
+	nthw_field_t *mp_fld_rx_used_writer_data_packed;
+	nthw_field_t *mp_fld_rx_used_writer_data_int;
+	nthw_field_t *mp_fld_rx_used_writer_data_vec;
+	nthw_field_t *mp_fld_rx_used_writer_data_istk;
+
+	nthw_register_t *mp_reg_tx_used_writer_control;
+	nthw_field_t *mp_fld_tx_used_writer_control_adr;
+	nthw_field_t *mp_fld_tx_used_writer_control_cnt;
+
+	nthw_register_t *mp_reg_tx_used_writer_data;
+	nthw_field_t *mp_fld_tx_used_writer_data_guest_physical_address;
+	nthw_field_t *mp_fld_tx_used_writer_data_host_id;
+	nthw_field_t *mp_fld_tx_used_writer_data_queue_size;
+	nthw_field_t *mp_fld_tx_used_writer_data_packed;
+	nthw_field_t *mp_fld_tx_used_writer_data_int;
+	nthw_field_t *mp_fld_tx_used_writer_data_vec;
+	nthw_field_t *mp_fld_tx_used_writer_data_istk;
+	nthw_field_t *mp_fld_tx_used_writer_data_in_order;
+
+	nthw_register_t *mp_reg_rx_descriptor_reader_control;
+	nthw_field_t *mp_fld_rx_descriptor_reader_control_adr;
+	nthw_field_t *mp_fld_rx_descriptor_reader_control_cnt;
+
+	nthw_register_t *mp_reg_rx_descriptor_reader_data;
+	nthw_field_t *mp_fld_rx_descriptor_reader_data_guest_physical_address;
+	nthw_field_t *mp_fld_rx_descriptor_reader_data_host_id;
+	nthw_field_t *mp_fld_rx_descriptor_reader_data_queue_size;
+	nthw_field_t *mp_fld_rx_descriptor_reader_data_header;
+	nthw_field_t *mp_fld_rx_descriptor_reader_data_packed;
+
+	nthw_register_t *mp_reg_tx_descriptor_reader_control;
+	nthw_field_t *mp_fld_tx_descriptor_reader_control_adr;
+	nthw_field_t *mp_fld_tx_descriptor_reader_control_cnt;
+
+	nthw_register_t *mp_reg_tx_descriptor_reader_data;
+	nthw_field_t *mp_fld_tx_descriptor_reader_data_guest_physical_address;
+	nthw_field_t *mp_fld_tx_descriptor_reader_data_host_id;
+	nthw_field_t *mp_fld_tx_descriptor_reader_data_queue_size;
+	nthw_field_t *mp_fld_tx_descriptor_reader_data_port;
+	nthw_field_t *mp_fld_tx_descriptor_reader_data_header;
+	nthw_field_t *mp_fld_tx_descriptor_reader_data_packed;
+
+	nthw_register_t *mp_reg_tx_queue_property_control;
+	nthw_field_t *mp_fld_tx_queue_property_control_adr;
+	nthw_field_t *mp_fld_tx_queue_property_control_cnt;
+
+	nthw_register_t *mp_reg_tx_queue_property_data;
+	nthw_field_t *mp_fld_tx_queue_property_data_v_port;
+
+	nthw_register_t *mp_reg_tx_queue_qos_control;
+	nthw_field_t *mp_reg_tx_queue_qos_control_adr;
+	nthw_field_t *mp_reg_tx_queue_qos_control_cnt;
+
+	nthw_register_t *mp_reg_tx_queue_qos_data;
+	nthw_field_t *mp_reg_tx_queue_qos_data_en;
+	nthw_field_t *mp_reg_tx_queue_qos_data_ir;
+	nthw_field_t *mp_reg_tx_queue_qos_data_bs;
+
+	nthw_register_t *mp_reg_tx_queue_qos_rate;
+	nthw_field_t *mp_reg_tx_queue_qos_rate_mul;
+	nthw_field_t *mp_reg_tx_queue_qos_rate_div;
+
+	struct nthw_dbs_rx_am_data_s m_rx_am_shadow[NT_DBS_RX_QUEUES_MAX];
+	struct nthw_dbs_rx_uw_data_s m_rx_uw_shadow[NT_DBS_RX_QUEUES_MAX];
+	struct nthw_dbs_rx_dr_data_s m_rx_dr_shadow[NT_DBS_RX_QUEUES_MAX];
+
+	struct nthw_dbs_tx_am_data_s m_tx_am_shadow[NT_DBS_TX_QUEUES_MAX];
+	struct nthw_dbs_tx_uw_data_s m_tx_uw_shadow[NT_DBS_TX_QUEUES_MAX];
+	struct nthw_dbs_tx_dr_data_s m_tx_dr_shadow[NT_DBS_TX_QUEUES_MAX];
+	struct nthw_dbs_tx_qp_data_s m_tx_qp_shadow[NT_DBS_TX_QUEUES_MAX];
+	struct nthw_dbs_tx_qos_data_s m_tx_qos_shadow[NT_DBS_TX_QUEUES_MAX];
+};
+
+typedef struct nthw_dbs_s nthw_dbs_t;
+
+nthw_dbs_t *nthw_dbs_new(void);
+void nthw_dbs_delete(nthw_dbs_t *p);
+int dbs_init(nthw_dbs_t *p, nthw_fpga_t *p_fpga, int n_instance);
+void dbs_reset(nthw_dbs_t *p);
+
+int dbs_reset_rx_control(nthw_dbs_t *p);
+int dbs_reset_tx_control(nthw_dbs_t *p);
+int set_rx_control(nthw_dbs_t *p,
+	uint32_t last_queue,
+	uint32_t avail_monitor_enable,
+	uint32_t avail_monitor_speed,
+	uint32_t used_write_enable,
+	uint32_t used_write_speed,
+	uint32_t rx_queue_enable);
+int nthw_dbs_get_rx_control(nthw_dbs_t *p,
+	uint32_t *last_queue,
+	uint32_t *avail_monitor_enable,
+	uint32_t *avail_monitor_speed,
+	uint32_t *used_write_enable,
+	uint32_t *used_write_speed,
+	uint32_t *rx_queue_enable);
+int set_tx_control(nthw_dbs_t *p,
+	uint32_t last_queue,
+	uint32_t avail_monitor_enable,
+	uint32_t avail_monitor_speed,
+	uint32_t used_write_enable,
+	uint32_t used_write_speed,
+	uint32_t tx_queue_enable);
+int nthw_dbs_get_tx_control(nthw_dbs_t *p,
+	uint32_t *last_queue,
+	uint32_t *avail_monitor_enable,
+	uint32_t *avail_monitor_speed,
+	uint32_t *used_write_enable,
+	uint32_t *used_write_speed,
+	uint32_t *tx_queue_enable);
+int set_rx_init(nthw_dbs_t *p, uint32_t start_idx, uint32_t start_ptr, uint32_t init,
+	uint32_t queue);
+int get_rx_init(nthw_dbs_t *p, uint32_t *init, uint32_t *queue, uint32_t *busy);
+int set_tx_init(nthw_dbs_t *p, uint32_t start_idx, uint32_t start_ptr, uint32_t init,
+	uint32_t queue);
+int get_tx_init(nthw_dbs_t *p, uint32_t *init, uint32_t *queue, uint32_t *busy);
+int set_rx_idle(nthw_dbs_t *p, uint32_t idle, uint32_t queue);
+int get_rx_idle(nthw_dbs_t *p, uint32_t *idle, uint32_t *queue, uint32_t *busy);
+int set_tx_idle(nthw_dbs_t *p, uint32_t idle, uint32_t queue);
+int get_tx_idle(nthw_dbs_t *p, uint32_t *idle, uint32_t *queue, uint32_t *busy);
+int set_rx_ptr_queue(nthw_dbs_t *p, uint32_t queue);
+int get_rx_ptr(nthw_dbs_t *p, uint32_t *ptr, uint32_t *queue, uint32_t *valid);
+int set_tx_ptr_queue(nthw_dbs_t *p, uint32_t queue);
+int get_tx_ptr(nthw_dbs_t *p, uint32_t *ptr, uint32_t *queue, uint32_t *valid);
+int set_rx_am_data(nthw_dbs_t *p,
+	uint32_t index,
+	uint64_t guest_physical_address,
+	uint32_t enable,
+	uint32_t host_id,
+	uint32_t packed,
+	uint32_t int_enable);
+int set_tx_am_data(nthw_dbs_t *p,
+	uint32_t index,
+	uint64_t guest_physical_address,
+	uint32_t enable,
+	uint32_t host_id,
+	uint32_t packed,
+	uint32_t int_enable);
+int set_rx_uw_data(nthw_dbs_t *p,
+	uint32_t index,
+	uint64_t guest_physical_address,
+	uint32_t host_id,
+	uint32_t queue_size,
+	uint32_t packed,
+	uint32_t int_enable,
+	uint32_t vec,
+	uint32_t istk);
+int set_tx_uw_data(nthw_dbs_t *p,
+	uint32_t index,
+	uint64_t guest_physical_address,
+	uint32_t host_id,
+	uint32_t queue_size,
+	uint32_t packed,
+	uint32_t int_enable,
+	uint32_t vec,
+	uint32_t istk,
+	uint32_t in_order);
+int set_rx_dr_data(nthw_dbs_t *p,
+	uint32_t index,
+	uint64_t guest_physical_address,
+	uint32_t host_id,
+	uint32_t queue_size,
+	uint32_t header,
+	uint32_t packed);
+int set_tx_dr_data(nthw_dbs_t *p,
+	uint32_t index,
+	uint64_t guest_physical_address,
+	uint32_t host_id,
+	uint32_t queue_size,
+	uint32_t port,
+	uint32_t header,
+	uint32_t packed);
+int nthw_dbs_set_tx_qp_data(nthw_dbs_t *p, uint32_t index, uint32_t virtual_port);
+int set_tx_qos_data(nthw_dbs_t *p, uint32_t index, uint32_t enable, uint32_t ir, uint32_t bs);
+int set_tx_qos_rate(nthw_dbs_t *p, uint32_t mul, uint32_t div);
+
+#endif	/* _NTNIC_DBS_H_ */
diff --git a/drivers/net/ntnic/include/ntnic_nim.h b/drivers/net/ntnic/include/ntnic_nim.h
new file mode 100644
index 0000000000..41457b7a07
--- /dev/null
+++ b/drivers/net/ntnic/include/ntnic_nim.h
@@ -0,0 +1,160 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2024 Napatech A/S
+ */
+
+#ifndef _NTNIC_NIM_H_
+#define _NTNIC_NIM_H_
+
+#include <stdint.h>
+
+typedef enum i2c_type {
+	I2C_HWIIC,
+	I2C_HWAGX
+} i2c_type_e;
+
+/*
+ * Port types
+ * The use of all non-generic XX_NOT_PRESENT is deprecated - use
+ * NT_PORT_TYPE_NIM_NOT_PRESENT instead
+ */
+enum nt_port_type_e {
+	NT_PORT_TYPE_NOT_AVAILABLE = 0,	/* The NIM/port type is not available (unknown) */
+	NT_PORT_TYPE_NOT_RECOGNISED,	/* The NIM/port type not recognized */
+	NT_PORT_TYPE_RJ45,	/* RJ45 type */
+	NT_PORT_TYPE_SFP_NOT_PRESENT,	/* SFP type but slot is empty */
+	NT_PORT_TYPE_SFP_SX,	/* SFP SX */
+	NT_PORT_TYPE_SFP_SX_DD,	/* SFP SX digital diagnostic */
+	NT_PORT_TYPE_SFP_LX,	/* SFP LX */
+	NT_PORT_TYPE_SFP_LX_DD,	/* SFP LX digital diagnostic */
+	NT_PORT_TYPE_SFP_ZX,	/* SFP ZX */
+	NT_PORT_TYPE_SFP_ZX_DD,	/* SFP ZX digital diagnostic */
+	NT_PORT_TYPE_SFP_CU,	/* SFP copper */
+	NT_PORT_TYPE_SFP_CU_DD,	/* SFP copper digital diagnostic */
+	NT_PORT_TYPE_SFP_NOT_RECOGNISED,/* SFP unknown */
+	NT_PORT_TYPE_XFP,	/* XFP */
+	NT_PORT_TYPE_XPAK,	/* XPAK */
+	NT_PORT_TYPE_SFP_CU_TRI_SPEED,	/* SFP copper tri-speed */
+	NT_PORT_TYPE_SFP_CU_TRI_SPEED_DD,	/* SFP copper tri-speed digital diagnostic */
+	NT_PORT_TYPE_SFP_PLUS,	/* SFP+ type */
+	NT_PORT_TYPE_SFP_PLUS_NOT_PRESENT,	/* SFP+ type but slot is empty */
+	NT_PORT_TYPE_XFP_NOT_PRESENT,	/* XFP type but slot is empty */
+	NT_PORT_TYPE_QSFP_PLUS_NOT_PRESENT,	/* QSFP type but slot is empty */
+	NT_PORT_TYPE_QSFP_PLUS,	/* QSFP type */
+	NT_PORT_TYPE_SFP_PLUS_PASSIVE_DAC,	/* SFP+ Passive DAC */
+	NT_PORT_TYPE_SFP_PLUS_ACTIVE_DAC,	/* SFP+ Active DAC */
+	NT_PORT_TYPE_CFP4,	/* CFP4 type */
+	NT_PORT_TYPE_CFP4_LR4 = NT_PORT_TYPE_CFP4,	/* CFP4 100G, LR4 type */
+	NT_PORT_TYPE_CFP4_NOT_PRESENT,	/* CFP4 type but slot is empty */
+	NT_PORT_TYPE_INITIALIZE,/* The port type is not fully established yet */
+	NT_PORT_TYPE_NIM_NOT_PRESENT,	/* Generic "Not present" */
+	NT_PORT_TYPE_HCB,	/* Test mode: Host Compliance Board */
+	NT_PORT_TYPE_NOT_SUPPORTED,	/* The NIM type is not supported in this context */
+	NT_PORT_TYPE_SFP_PLUS_DUAL_RATE,/* SFP+ supports 1G/10G */
+	NT_PORT_TYPE_CFP4_SR4,	/* CFP4 100G, SR4 type */
+	NT_PORT_TYPE_QSFP28_NOT_PRESENT,/* QSFP28 type but slot is empty */
+	NT_PORT_TYPE_QSFP28,	/* QSFP28 type */
+	NT_PORT_TYPE_QSFP28_SR4,/* QSFP28-SR4 type */
+	NT_PORT_TYPE_QSFP28_LR4,/* QSFP28-LR4 type */
+	/* Deprecated. The port type should not mention speed eg 4x10 or 1x40 */
+	NT_PORT_TYPE_QSFP_PLUS_4X10,
+	/* Deprecated. The port type should not mention speed eg 4x10 or 1x40 */
+	NT_PORT_TYPE_QSFP_PASSIVE_DAC_4X10,
+	/* QSFP passive DAC type */
+	NT_PORT_TYPE_QSFP_PASSIVE_DAC = NT_PORT_TYPE_QSFP_PASSIVE_DAC_4X10,
+	/* Deprecated. The port type should not mention speed eg 4x10 or 1x40 */
+	NT_PORT_TYPE_QSFP_ACTIVE_DAC_4X10,
+	/* QSFP active DAC type */
+	NT_PORT_TYPE_QSFP_ACTIVE_DAC = NT_PORT_TYPE_QSFP_ACTIVE_DAC_4X10,
+	NT_PORT_TYPE_SFP_28,	/* SFP28 type */
+	NT_PORT_TYPE_SFP_28_SR,	/* SFP28-SR type */
+	NT_PORT_TYPE_SFP_28_LR,	/* SFP28-LR type */
+	NT_PORT_TYPE_SFP_28_CR_CA_L,	/* SFP28-CR-CA-L type */
+	NT_PORT_TYPE_SFP_28_CR_CA_S,	/* SFP28-CR-CA-S type */
+	NT_PORT_TYPE_SFP_28_CR_CA_N,	/* SFP28-CR-CA-N type */
+	NT_PORT_TYPE_QSFP28_CR_CA_L,	/* QSFP28-CR-CA-L type */
+	NT_PORT_TYPE_QSFP28_CR_CA_S,	/* QSFP28-CR-CA-S type */
+	NT_PORT_TYPE_QSFP28_CR_CA_N,	/* QSFP28-CR-CA-N type */
+	NT_PORT_TYPE_SFP_28_SR_DR,	/* SFP28-SR-DR type */
+	NT_PORT_TYPE_SFP_28_LR_DR,	/* SFP28-LR-DR type */
+	NT_PORT_TYPE_SFP_FX,	/* SFP FX */
+	NT_PORT_TYPE_SFP_PLUS_CU,	/* SFP+ CU type */
+	/* QSFP28-FR type. Uses PAM4 modulation on one lane only */
+	NT_PORT_TYPE_QSFP28_FR,
+	/* QSFP28-DR type. Uses PAM4 modulation on one lane only */
+	NT_PORT_TYPE_QSFP28_DR,
+	/* QSFP28-LR type. Uses PAM4 modulation on one lane only */
+	NT_PORT_TYPE_QSFP28_LR,
+};
+
+typedef enum nt_port_type_e nt_port_type_t, *nt_port_type_p;
+
+typedef struct nim_i2c_ctx {
+	union {
+		nthw_iic_t hwiic;	/* depends on *Fpga_t, instance number, and cycle time */
+		struct {
+			int mux_channel;
+		} hwagx;
+	};
+	i2c_type_e type;/* 0 = hwiic (xilinx) - 1 =  hwagx (agilex) */
+	uint8_t instance;
+	uint8_t devaddr;
+	uint8_t regaddr;
+	uint8_t nim_id;
+	nt_port_type_t port_type;
+
+	char vendor_name[17];
+	char prod_no[17];
+	char serial_no[17];
+	char date[9];
+	char rev[5];
+	bool avg_pwr;
+	bool content_valid;
+	uint8_t pwr_level_req;
+	uint8_t pwr_level_cur;
+	uint16_t len_info[5];
+	uint32_t speed_mask;	/* Speeds supported by the NIM */
+	int8_t lane_idx;/* Is this associated with a single lane or all lanes (-1) */
+	uint8_t lane_count;
+	uint32_t options;
+	bool tx_disable;
+	bool dmi_supp;
+
+	union {
+		struct {
+			bool sfp28;
+			bool sfpplus;
+			bool dual_rate;
+			bool hw_rate_sel;
+			bool sw_rate_sel;
+			bool cu_type;
+			bool tri_speed;
+			bool ext_cal;
+			bool addr_chg;
+		} sfp;
+
+		struct {
+			bool rx_only;
+			bool qsfp28;
+			union {
+				struct {
+					uint8_t rev_compliance;
+					bool media_side_fec_ctrl;
+					bool host_side_fec_ctrl;
+					bool media_side_fec_ena;
+					bool host_side_fec_ena;
+				} qsfp28;
+			} specific_u;
+		} qsfp;
+
+	} specific_u;
+} nim_i2c_ctx_t, *nim_i2c_ctx_p;
+
+struct nim_sensor_group {
+	struct nt_adapter_sensor *sensor;
+	void (*read)(struct nim_sensor_group *sg, nthw_spis_t *t_spi);
+	struct nim_i2c_ctx *ctx;
+	struct nim_sensor_group *next;
+};
+
+#endif	/* _NTNIC_NIM_H_ */
diff --git a/drivers/net/ntnic/include/ntnic_nthw_fpga_rst_nt200a0x.h b/drivers/net/ntnic/include/ntnic_nthw_fpga_rst_nt200a0x.h
new file mode 100644
index 0000000000..8b7ebdf1fd
--- /dev/null
+++ b/drivers/net/ntnic/include/ntnic_nthw_fpga_rst_nt200a0x.h
@@ -0,0 +1,82 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2024 Napatech A/S
+ */
+
+#ifndef __NTNIC_NTHW_FPGA_RST_NT200A0X_H__
+#define __NTNIC_NTHW_FPGA_RST_NT200A0X_H__
+
+#include "nthw_drv.h"
+#include "nthw_fpga_model.h"
+
+struct nthw_fpga_rst_nt200a0x {
+	int mn_fpga_product_id;
+	int mn_fpga_version;
+	int mn_fpga_revision;
+
+	int mn_hw_id;
+
+	int mn_si_labs_clock_synth_model;
+	uint8_t mn_si_labs_clock_synth_i2c_addr;
+
+	nthw_field_t *mp_fld_rst_sys;
+	nthw_field_t *mp_fld_rst_sys_mmcm;
+	nthw_field_t *mp_fld_rst_core_mmcm;
+	nthw_field_t *mp_fld_rst_rpp;
+	nthw_field_t *mp_fld_rst_ddr4;
+	nthw_field_t *mp_fld_rst_sdc;
+	nthw_field_t *mp_fld_rst_phy;
+	nthw_field_t *mp_fld_rst_serdes_rx;
+	nthw_field_t *mp_fld_rst_serdes_tx;
+	nthw_field_t *mp_fld_rst_serdes_rx_datapath;
+	nthw_field_t *mp_fld_rst_pcs_rx;
+	nthw_field_t *mp_fld_rst_mac_rx;
+	nthw_field_t *mp_fld_rst_mac_tx;
+	nthw_field_t *mp_fld_rst_ptp;
+	nthw_field_t *mp_fld_rst_ts;
+	nthw_field_t *mp_fld_rst_ptp_mmcm;
+	nthw_field_t *mp_fld_rst_ts_mmcm;
+	nthw_field_t *mp_fld_rst_periph;
+	nthw_field_t *mp_fld_rst_tsm_ref_mmcm;
+	nthw_field_t *mp_fld_rst_tmc;
+
+	/* CTRL register field pointers */
+	nthw_field_t *mp_fld_ctrl_ts_clk_sel_override;
+	nthw_field_t *mp_fld_ctrl_ts_clk_sel;
+	nthw_field_t *mp_fld_ctrl_ts_clk_sel_ref;
+	nthw_field_t *mp_fld_ctrl_ptp_mmcm_clk_sel;
+
+	/* STAT register field pointers */
+	nthw_field_t *mp_fld_stat_ddr4_mmcm_locked;
+	nthw_field_t *mp_fld_stat_sys_mmcm_locked;
+	nthw_field_t *mp_fld_stat_core_mmcm_locked;
+	nthw_field_t *mp_fld_stat_ddr4_pll_locked;
+	nthw_field_t *mp_fld_stat_ptp_mmcm_locked;
+	nthw_field_t *mp_fld_stat_ts_mmcm_locked;
+	nthw_field_t *mp_fld_stat_tsm_ref_mmcm_locked;
+
+	/* STICKY register field pointers */
+	nthw_field_t *mp_fld_sticky_ptp_mmcm_unlocked;
+	nthw_field_t *mp_fld_sticky_ts_mmcm_unlocked;
+	nthw_field_t *mp_fld_sticky_ddr4_mmcm_unlocked;
+	nthw_field_t *mp_fld_sticky_ddr4_pll_unlocked;
+	nthw_field_t *mp_fld_sticky_core_mmcm_unlocked;
+	nthw_field_t *mp_fld_sticky_pci_sys_mmcm_unlocked;
+	nthw_field_t *mp_fld_sticky_tsm_ref_mmcm_unlocked;
+
+	/* POWER register field pointers */
+	nthw_field_t *mp_fld_power_pu_phy;
+	nthw_field_t *mp_fld_power_pu_nseb;
+
+	void (*reset_serdes_rx)(struct nthw_fpga_rst_nt200a0x *p, uint32_t intf_no, uint32_t rst);
+	void (*pcs_rx_rst)(struct nthw_fpga_rst_nt200a0x *p, uint32_t intf_no, uint32_t rst);
+	void (*get_serdes_rx_rst)(struct nthw_fpga_rst_nt200a0x *p, uint32_t intf_no,
+		uint32_t *p_set);
+	void (*get_pcs_rx_rst)(struct nthw_fpga_rst_nt200a0x *p, uint32_t intf_no,
+		uint32_t *p_set);
+	bool (*is_rst_serdes_rx_datapath_implemented)(struct nthw_fpga_rst_nt200a0x *p);
+};
+
+typedef struct nthw_fpga_rst_nt200a0x nthw_fpga_rst_nt200a0x_t;
+
+#endif	/* __NTHW_FPGA_RST_NT200A0X_H__ */
diff --git a/drivers/net/ntnic/include/ntnic_sensor.h b/drivers/net/ntnic/include/ntnic_sensor.h
new file mode 100644
index 0000000000..55ac519f42
--- /dev/null
+++ b/drivers/net/ntnic/include/ntnic_sensor.h
@@ -0,0 +1,515 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef _NTNIC_SENSOR_H_
+#define _NTNIC_SENSOR_H_
+
+#include "nthw_fpga_model.h"
+#include "nthw_spis.h"
+
+#define SENSOR_MON_UINT16_NAN 0xFFFF	/* Most positive number used as NaN */
+#define SENSOR_MON_INT16_NAN ((int16_t)0x8000)	/* Most negative number used as NaN */
+
+/*
+ * Sensor types
+ */
+
+#pragma pack(1)
+struct sensor_mon_setup_data16 {
+	uint8_t fpga_idx;	/* Destination of results */
+	uint8_t device;	/* Device to monitor */
+	uint8_t device_register;/* Sensor within device */
+	uint16_t mask;	/* Indicates active bits */
+	uint8_t pos;	/* Position of first active bit */
+	uint16_t format;/* b0,1:sensor_mon_endian_t endian */
+	/* b2,3:sensor_mon_sign_t   sign */
+	union {
+		struct {
+			int16_t limit_low;	/* Signed alarm limit low */
+			int16_t limit_high;	/* Signed alarm limit high */
+		} int16;
+
+		struct {
+			uint16_t limit_low;	/* Unsigned alarm limit low */
+			uint16_t limit_high;	/* Unsigned alarm limit high */
+		} uint16;
+	};
+};
+#pragma pack()
+struct sensor_mon_setup16 {
+	uint8_t setup_cnt;	/* Number of entries in setup_data */
+	struct sensor_mon_setup_data16 setup_data[40];
+};
+
+enum nt_sensor_type_e {
+	NT_SENSOR_TYPE_UNKNOWN = 0,
+	NT_SENSOR_TYPE_TEMPERATURE = 1,	/* Unit: 0.1 degree Celsius */
+	NT_SENSOR_TYPE_VOLTAGE = 2,	/* Unit: 1 mV */
+	NT_SENSOR_TYPE_CURRENT = 3,	/* Unit: 1 uA */
+	NT_SENSOR_TYPE_POWER = 4,	/* Unit: 0.1 uW */
+	NT_SENSOR_TYPE_FAN = 5,	/* Unit: 1 RPM (Revolutions Per Minute) */
+	NT_SENSOR_TYPE_HIGH_POWER = 6,	/* Unit: 1 mW */
+	NT_SENSOR_TYPE_NUMBER = 7,
+};
+
+typedef enum nt_sensor_type_e nt_sensor_type_t;
+
+/*
+ * Generic SFP/SFP+/SFP28 sensors
+ *
+ * These sensors should be used instead of all adapter specific SFP sensors
+ * that have been deprecated..
+ */
+enum nt_sensors_sfp {
+	NT_SENSOR_SFP_TEMP,
+	NT_SENSOR_SFP_SUPPLY,
+	NT_SENSOR_SFP_TX_BIAS,
+	NT_SENSOR_SFP_TX_POWER,
+	NT_SENSOR_SFP_RX_POWER,
+};
+
+/*
+ * Generic QSFP/QSFP+/QSFP28 sensors
+ *
+ * These sensors should be used instead of all adapter specific QSFP sensors
+ * that have been deprecated..
+ */
+enum nt_sensors_qsfp {
+	NT_SENSOR_QSFP_TEMP,
+	NT_SENSOR_QSFP_SUPPLY,
+	NT_SENSOR_QSFP_TX_BIAS1,
+	NT_SENSOR_QSFP_TX_BIAS2,
+	NT_SENSOR_QSFP_TX_BIAS3,
+	NT_SENSOR_QSFP_TX_BIAS4,
+	NT_SENSOR_QSFP_TX_POWER1,
+	NT_SENSOR_QSFP_TX_POWER2,
+	NT_SENSOR_QSFP_TX_POWER3,
+	NT_SENSOR_QSFP_TX_POWER4,
+	NT_SENSOR_QSFP_RX_POWER1,
+	NT_SENSOR_QSFP_RX_POWER2,
+	NT_SENSOR_QSFP_RX_POWER3,
+	NT_SENSOR_QSFP_RX_POWER4,
+};
+
+/*
+ * Sensor subtypes
+ */
+enum nt_sensor_sub_type_e {
+	NT_SENSOR_SUBTYPE_NA = 0,
+	/*
+	 * Subtype for NT_SENSOR_TYPE_POWER type on optical modules
+	 * (optical modulation amplitude measured)
+	 */
+	NT_SENSOR_SUBTYPE_POWER_OMA,
+	/* Subtype for NT_SENSOR_TYPE_POWER type on optical modules (average power measured) */
+	NT_SENSOR_SUBTYPE_POWER_AVERAGE,
+	/* Subtype for NT_SENSOR_TYPE_HIGH_POWER type on adapters (total power consumption) */
+	NT_SENSOR_SUBTYPE_POWER_TOTAL
+};
+
+typedef enum nt_sensor_sub_type_e nt_sensor_sub_type_t;
+
+/*
+ * Sensor source
+ */
+enum nt_sensor_source_e {
+	NT_SENSOR_SOURCE_UNKNOWN = 0x00,/* Unknown source */
+	/* Sensors located in a port. These are primary sensors - usually NIM temperature.
+	 * Presence depends on adapter and NIM type.
+	 */
+	NT_SENSOR_SOURCE_PORT = 0x01,
+	/*
+	 * Level 1 sensors located in a port.
+	 * These are secondary sensors - usually NIM supply voltage,
+	 * Tx bias and Rx/Tx optical power. Presence depends on adapter and NIM type.
+	 */
+	NT_SENSOR_SOURCE_LEVEL1_PORT = 0x02,
+#ifndef DOXYGEN_INTERNAL_ONLY
+	NT_SENSOR_SOURCE_LEVEL2_PORT = 0x04,	/* Level 2 sensors located in a port */
+#endif
+	NT_SENSOR_SOURCE_ADAPTER = 0x08,/* Sensors mounted on the adapter */
+	NT_SENSOR_SOURCE_LEVEL1_ADAPTER = 0x10,	/* Level 1 sensors mounted on the adapter */
+#ifndef DOXYGEN_INTERNAL_ONLY
+	NT_SENSOR_SOURCE_LEVEL2_ADAPTER = 0x20,	/* Level 2 sensors mounted on the adapter */
+#endif
+};
+
+/*
+ * Sensor state
+ */
+enum nt_sensor_state_e {
+	NT_SENSOR_STATE_UNKNOWN = 0,	/* Unknown state */
+	NT_SENSOR_STATE_INITIALIZING = 1,	/* The sensor is initializing */
+	NT_SENSOR_STATE_NORMAL = 2,	/* Sensor values are within range */
+	NT_SENSOR_STATE_ALARM = 3,	/* Sensor values are out of range */
+	/* The sensor is not present, for example, SFP without diagnostics */
+	NT_SENSOR_STATE_NOT_PRESENT = 4
+};
+
+typedef enum nt_sensor_state_e nt_sensor_state_t;
+
+/*
+ * Sensor value
+ */
+
+/* Indicates that sensor value or sensor limit is not valid (Not a Number) */
+#define NT_SENSOR_NAN 0x80000000
+
+enum nt_sensors_e {
+	/* Public sensors (Level 0) */
+	NT_SENSOR_FPGA_TEMP,	/* FPGA temperature sensor */
+};
+
+/*
+ * Adapter types
+ */
+enum nt_adapter_type_e {
+	NT_ADAPTER_TYPE_UNKNOWN = 0,	/* Unknown adapter type */
+	NT_ADAPTER_TYPE_NT4E,	/* NT4E network adapter */
+	NT_ADAPTER_TYPE_NT20E,	/* NT20E network adapter */
+	NT_ADAPTER_TYPE_NT4E_STD,	/* NT4E-STD network adapter */
+	NT_ADAPTER_TYPE_NT4E_PORT,	/* NTPORT4E expansion adapter */
+	NT_ADAPTER_TYPE_NTBPE,	/* NTBPE bypass adapter */
+	NT_ADAPTER_TYPE_NT20E2,	/* NT20E2 network adapter */
+	NT_ADAPTER_TYPE_RESERVED1,	/* Reserved */
+	NT_ADAPTER_TYPE_RESERVED2,	/* Reserved */
+	NT_ADAPTER_TYPE_NT40E2_1,	/* NT40E2-1 network adapter */
+	NT_ADAPTER_TYPE_NT40E2_4,	/* NT40E2-4 network adapter */
+	NT_ADAPTER_TYPE_NT4E2_4T_BP,	/* NT4E2-4T-BP bypass network adapter */
+	NT_ADAPTER_TYPE_NT4E2_4_PTP,	/* NT4E2-4 PTP network adapter with IEEE1588 */
+	NT_ADAPTER_TYPE_NT20E2_PTP,	/* NT20E2 PTP network adapter with IEEE1588 */
+	NT_ADAPTER_TYPE_NT40E3_4_PTP,	/* NT40E3 network adapter with IEEE1588 */
+	NT_ADAPTER_TYPE_NT100E3_1_PTP,	/* NT100E3 network adapter with IEEE1588 */
+	NT_ADAPTER_TYPE_NT20E3_2_PTP,	/* NT20E3 network adapter with IEEE1588 */
+	NT_ADAPTER_TYPE_NT80E3_2_PTP,	/* NT80E3 network adapter with IEEE1588 */
+	NT_ADAPTER_TYPE_NT200E3_2,	/* NT200E3 network adapter */
+	NT_ADAPTER_TYPE_NT200A01,	/* NT200A01 network adapter */
+	/* NT200A01 2 x 100 Gbps network adapter */
+	NT_ADAPTER_TYPE_NT200A01_2X100 = NT_ADAPTER_TYPE_NT200A01,
+	NT_ADAPTER_TYPE_NT40A01_4X1,	/* NT40A01_4X1 network adapter with IEEE1588 */
+	NT_ADAPTER_TYPE_NT200A01_2X40,	/* NT200A01 2 x 40 Gbps network adapter */
+	/* NT80E3 8 x 10 Gbps network adapter with IEEE1588 */
+	NT_ADAPTER_TYPE_NT80E3_2_PTP_8X10,
+	/*  */
+	NT_ADAPTER_TYPE_INTEL_A10_4X10,	/* Intel PAC A10 GX 4 x 10 Gbps network adapter */
+	NT_ADAPTER_TYPE_INTEL_A10_1X40,	/* Intel PAC A10 GX 1 x 40 Gbps network adapter */
+	/*  */
+	NT_ADAPTER_TYPE_NT200A01_8X10,	/* NT200A01 8 x 10 Gbps network adapter */
+	NT_ADAPTER_TYPE_NT200A02_2X100,	/* NT200A02 2 x 100 Gbps network adapter */
+	NT_ADAPTER_TYPE_NT200A02_2X40,	/* NT200A02 2 x 40 Gbps network adapter */
+	NT_ADAPTER_TYPE_NT200A01_2X25,	/* Deprecated */
+	/* NT200A01 2 x 10/25 Gbps network adapter */
+	NT_ADAPTER_TYPE_NT200A01_2X10_25 = NT_ADAPTER_TYPE_NT200A01_2X25,
+	NT_ADAPTER_TYPE_NT200A02_2X25,	/* Deprecated */
+	/* NT200A02 2 x 10/25 Gbps network adapter */
+	NT_ADAPTER_TYPE_NT200A02_2X10_25 = NT_ADAPTER_TYPE_NT200A02_2X25,
+	NT_ADAPTER_TYPE_NT200A02_4X25,	/* Deprecated */
+	/* NT200A02 4 x 10/25 Gbps network adapter */
+	NT_ADAPTER_TYPE_NT200A02_4X10_25 = NT_ADAPTER_TYPE_NT200A02_4X25,
+	NT_ADAPTER_TYPE_NT200A02_8X10,	/* NT200A02 8 x 10 Gbps network adapter */
+	NT_ADAPTER_TYPE_NT50B01_2X25,	/* Deprecated */
+	/* NT50B01 2 x 10/25 Gbps network adapter */
+	NT_ADAPTER_TYPE_NT50B01_2X10_25 = NT_ADAPTER_TYPE_NT50B01_2X25,
+	NT_ADAPTER_TYPE_NT200A02_2X1_10,/* NT200A02 2 x 1/10 Gbps network adapter */
+	NT_ADAPTER_TYPE_NT100A01_4X1_10,/* NT100A01 4 x 1/10 Gbps network adapter */
+	NT_ADAPTER_TYPE_NT100A01_4X10_25,	/* NT100A01 4 x 10/25 Gbps network adapter */
+	NT_ADAPTER_TYPE_NT50B01_2X1_10,	/* NT50B01 2 x 1/10 Gbps network adapter */
+	NT_ADAPTER_TYPE_NT40A11_4X1_10,	/* NT40A11 4 x 1/10 Gbps network adapter */
+	NT_ADAPTER_TYPE_NT400D11_2X100,	/*!< NT400D11 2 x 100 Gbps network adapter */
+#ifndef DOXYGEN_INTERNAL_ONLY
+	NT_ADAPTER_TYPE_ML605 = 10000,	/* NT20E2 eval board */
+#endif
+	NT_ADAPTER_TYPE_4GARCH_HAMOA =
+		(1U << 29),	/* Bit to mark to adapters as a 4GArch Hamoa adapter */
+	NT_ADAPTER_TYPE_4GARCH = (1U << 30),	/* Bit to mark to adapters as a 4GArch adapter */
+	/* NOTE: do *NOT* add normal adapters after the group bit mark enums */
+};
+
+/* The NT200E3 adapter sensor id's */
+typedef enum nt_sensors_adapter_nt200_e3_e {
+	/* Public sensors (Level 0) */
+	NT_SENSOR_NT200E3_FPGA_TEMP,	/* FPGA temperature sensor */
+	NT_SENSOR_NT200E3_FAN_SPEED,	/* FAN speed sensor */
+	/* MCU (Micro Controller Unit) temperature sensor located inside enclosure below FAN */
+	NT_SENSOR_NT200E3_MCU_TEMP,
+	NT_SENSOR_NT200E3_PSU0_TEMP,	/* Power supply 0 temperature sensor */
+	NT_SENSOR_NT200E3_PSU1_TEMP,	/* Power supply 1 temperature sensor */
+	NT_SENSOR_NT200E3_PCB_TEMP,	/* PCB temperature sensor */
+
+	/* Diagnostic sensors (Level 1) */
+	/* Total power consumption (calculated value) - does not generate alarms */
+	NT_SENSOR_NT200E3_NT200E3_POWER,
+	/* FPGA power consumption (calculated value) - does not generate alarms */
+	NT_SENSOR_NT200E3_FPGA_POWER,
+	/* DDR4 RAM power consumption (calculated value) - does not generate alarms */
+	NT_SENSOR_NT200E3_DDR4_POWER,
+	/* NIM power consumption (calculated value) - does not generate alarms */
+	NT_SENSOR_NT200E3_NIM_POWER,
+
+	NT_SENSOR_NT200E3_L1_MAX,	/* Number of NT200E3 level 0,1 board sensors */
+} nt_sensors_adapter_nt200_e3_t;
+
+/* The following sensors are deprecated - generic types should be used instead */
+/* The NIM temperature sensor must be the one with the lowest sensor_index */
+/* (enum value) in order to be shown by the monitoring tool in port mode */
+enum nt_sensors_port_nt200_e3_2_e {
+	/* Public sensors */
+	NT_SENSOR_NT200E3_NIM,	/* QSFP28 temperature sensor */
+
+	/* Diagnostic sensors (Level 1) */
+	NT_SENSOR_NT200E3_SUPPLY,	/* QSFP28 supply voltage sensor */
+	NT_SENSOR_NT200E3_TX_BIAS1,	/* QSFP28 TX bias line 0 current sensor */
+	NT_SENSOR_NT200E3_TX_BIAS2,	/* QSFP28 TX bias line 1 current sensor */
+	NT_SENSOR_NT200E3_TX_BIAS3,	/* QSFP28 TX bias line 2 current sensor */
+	NT_SENSOR_NT200E3_TX_BIAS4,	/* QSFP28 TX bias line 3 current sensor */
+	NT_SENSOR_NT200E3_RX1,	/* QSFP28 RX line 0 power sensor */
+	NT_SENSOR_NT200E3_RX2,	/* QSFP28 RX line 1 power sensor */
+	NT_SENSOR_NT200E3_RX3,	/* QSFP28 RX line 2 power sensor */
+	NT_SENSOR_NT200E3_RX4,	/* QSFP28 RX line 3 power sensor */
+	NT_SENSOR_NT200E3_TX1,	/* QSFP28 TX line 0 power sensor */
+	NT_SENSOR_NT200E3_TX2,	/* QSFP28 TX line 1 power sensor */
+	NT_SENSOR_NT200E3_TX3,	/* QSFP28 TX line 2 power sensor */
+	NT_SENSOR_NT200E3_TX4,	/* QSFP28 TX line 3 power sensor */
+	NT_SENSOR_NT200E3_PORT_MAX,	/* Number of NT200E3 port sensors */
+};
+
+typedef enum nt_sensors_adapter_nt400d11_e {
+	/*
+	 * Public sensors (Level 0)
+	 * NT_SENSOR_NT400D11_FPGA_TEMP,               //!< FPGA temperature sensor
+	 */
+	/* !< FPGA temperature sensor 2 = NT_SENSOR_NT400D11_FPGA_TEMP */
+	NT_SENSOR_NT400D11_TEMP2_TEMP_CORE_FABRIC,
+	NT_SENSOR_NT400D11_FAN_SPEED,	/* !< FAN speed sensor */
+	/* !< MCU (Micro Controller Unit) temperature sensor located inside enclosure below FAN */
+	NT_SENSOR_NT400D11_MCU_TEMP,
+	NT_SENSOR_NT400D11_PSU1_TEMP,	/* !< Power supply 1 temperature sensor */
+	NT_SENSOR_NT400D11_PSU2_TEMP,	/* !< Power supply 2 temperature sensor */
+	NT_SENSOR_NT400D11_PSU3_TEMP,	/* !< Power supply 3 temperature sensor */
+	NT_SENSOR_NT400D11_PSU5_TEMP,	/* !< Power supply 5 temperature sensor */
+	NT_SENSOR_NT400D11_L1_MAX,	/* !< Number of NT400D11 level 0,1 board sensors */
+} nt_sensors_adapter_nt400_d11_t;
+
+typedef enum nt_sensors_adapter_nt400_d11_level2_t {
+	/* Supportinfo sensors (Level 2) */
+	/* !< FPGA temperature sensor 1 */
+	NT_SENSOR_NT400D11_TEMP3_TEMP_INLET = NT_SENSOR_NT400D11_L1_MAX,
+	NT_SENSOR_NT400D11_L2_MAX
+} nt_sensors_adapter_nt400_d11_level2_t;
+
+enum nt_sensor_event_alarm_e {
+	NT_SENSOR_ENABLE_ALARM,
+	NT_SENSOR_LOG_ALARM,
+	NT_SENSOR_DISABLE_ALARM,
+};
+
+/*
+ * Specify the nature of the raw data. AVR and ntservice must use this
+ * information when comparing or converting to native format which is little endian
+ */
+enum sensor_mon_endian {
+	SENSOR_MON_LITTLE_ENDIAN,
+	SENSOR_MON_BIG_ENDIAN
+};
+
+enum sensor_mon_sign {
+	SENSOR_MON_UNSIGNED,
+	SENSOR_MON_SIGNED,	/* 2's complement */
+};
+
+/* Define sensor devices */
+enum sensor_mon_device {
+	SENSOR_MON_PSU_EXAR_7724_0 = 0,	/* NT40E3, NT100E3 */
+	SENSOR_MON_PSU_EXAR_7724_1,	/* NT40E3, NT100E3 */
+	SENSOR_MON_PSU_LTM_4676_0,	/* na      NT100E3, page-0 */
+	SENSOR_MON_PSU_LTM_4676_1,	/* na      NT100E3, page-0 */
+	SENSOR_MON_INA219_1,	/* NT40E3, NT100E3 */
+	SENSOR_MON_INA219_2,	/* NT40E3, NT100E3 */
+	SENSOR_MON_MAX6642,	/* NT40E3, NT100E3 */
+	SENSOR_MON_DS1775,	/* NT40E3, NT100E3 */
+	SENSOR_MON_FAN,	/* NT40E3, NT100E3 */
+	SENSOR_MON_AVR,	/* NT40E3, NT100E3 */
+	SENSOR_MON_PEX8734,	/* na      NT100E3 */
+	SENSOR_MON_RATE_COUNT,	/* NT40E3, NT100E3 */
+	SENSOR_MON_PSU_LTM_4676_0_1,	/* na      NT100E3, page-1 */
+	SENSOR_MON_PSU_LTM_4676_1_1,	/* na      NT100E3, page-1 */
+	SENSOR_MON_MP2886A,	/* na,     na,      NT200A02, */
+	SENSOR_MON_PSU_EM2260_1,/*     na,      na,      na,       na, NT200D01^M */
+	SENSOR_MON_PSU_EM2120_2,/*     na,      na,      na,       na, NT200D01^M */
+	/*     na,      na,      na, NT200A02,        na,   NT50B01, */
+	SENSOR_MON_MP2886A_PSU_1,
+	/*     na,      na,      na, NT200A02,        na,   NT50B01, */
+	SENSOR_MON_MP8869S_PSU_2,
+	/*     na,      na,      na, NT200A02,        na,   NT50B01, */
+	SENSOR_MON_MP8645PGVT_PSU_3,
+	/*     na,      na,      na, NT200A02,        na,   NT50B01, */
+	SENSOR_MON_MP8645PGVT_PSU_4,
+	/*     na,      na,      na, NT200A02,        na,   NT50B01, */
+	SENSOR_MON_MP8869S_PSU_5,
+	/*     na,      na,      na, NT200A02,        na,   NT50B01, */
+	SENSOR_MON_MP8869S_PSU_6,
+	/* NT40E3,      na,      na,      na,         na,        na,       na */
+	SENSOR_MON_NT40E3_MP8869S_PSU_1,
+	/* NT40E3,      na,      na,      na,         na,        na,       na */
+	SENSOR_MON_NT40E3_MP8645PGVT_PSU_2,
+	/* NT40E3,      na,      na,      na,         na,        na,       na */
+	SENSOR_MON_NT40E3_MP8869S_PSU_4,
+	/* NT40E3,      na,      na,      na,         na,        na,       na */
+	SENSOR_MON_NT40E3_MP8869S_PSU_6,
+	/* NT40E3,      na,      na,      na,         na,        na,       na */
+	SENSOR_MON_NT40E3_MP8869S_PSU_7,
+	/* NT40E3,      na,      na,      na,         na,        na,       na */
+	SENSOR_MON_NT40E3_MP8869S_PSU_8,
+	/*     na,      na,      na,      na,         na,        na,       na,  NT400D11 */
+	SENSOR_MON_MPS_PSU_1,
+	/*     na,      na,      na,      na,         na,        na,       na,  NT400D11 */
+	SENSOR_MON_MPS_PSU_2_PAGE_0,
+	/*     na,      na,      na,      na,         na,        na,       na,  NT400D11 */
+	SENSOR_MON_MPS_PSU_3,
+	/*     na,      na,      na,      na,         na,        na,       na,  NT400D11 */
+	SENSOR_MON_MPS_PSU_4,
+	/*     na,      na,      na,      na,         na,        na,       na,  NT400D11 */
+	SENSOR_MON_MPS_PSU_5,
+	/*     na,      na,      na,      na,         na,        na,       na,  NT400D11 */
+	SENSOR_MON_MPS_PSU_6,
+	/*     na,      na,      na,      na,         na,        na,       na,  NT400D11 */
+	SENSOR_MON_TMP464_1,
+	/*     na,      na,      na,      na,         na,        na,       na,  NT400D11 */
+	SENSOR_MON_TMP464_2,
+	/*     na,      na,      na,      na,         na,        na,       na,  NT400D11 */
+	SENSOR_MON_INA3221,
+	/*     na,      na,      na,      na,         na,        na,       na,  NT400D11 */
+	SENSOR_MON_MPS_PSU_2_PAGE_1,
+	/*     na,      na,      na,      na,         na,        na,       na,  NT400D11 */
+	SENSOR_MON_DEVICE_COUNT
+};
+
+/* Define sensor monitoring control */
+enum sensor_mon_control {
+	SENSOR_MON_CTRL_STOP = 0,	/* Stop sensor monitoring */
+	SENSOR_MON_CTRL_RUN = 1,/* Start sensor monitoring */
+	SENSOR_MON_CTRL_REM_ALL_SENSORS = 2,	/* Stop and remove all sensor monitoring setup */
+};
+
+/*
+ * This structure will return the sensor specific information
+ *
+ * The units used for the fields: value, value_lowest, value_highest, limit_low and
+ * limit_high depend on the type field. See @ref NtSensorType_e.
+ *
+ * For the limit_low and limit_high fields the following applies:\n
+ * If the sensor is located in a NIM (Network Interface Module), the limits are read
+ * from the NIM module via the DMI (Diagnostic Monitoring Interface) from the alarm
+ * and warning thresholds section, and the units are changed to internal representation.
+ * Only the alarm thresholds are used and are read only once during initialization.
+ * The limits cannot be changed.
+ *
+ * The value field is updated internally on a regular basis and is also based on a
+ * value read from the NIM which is also changed to internal representation.
+ *
+ * Not all NIM types support DMI data, and its presence must be determined by reading an
+ * option flag. In general, a NIM can read out: temperature, supply voltage,
+ * TX bias, TX optical power and RX optical power but not all NIM types support all
+ * 5 values.
+ *
+ * If external calibration is used (most NIM use internal calibration), both the
+ * current value and the threshold values are subjected to the specified calibration
+ * along with the change to internal calibration.
+ */
+#define NT_INFO_SENSOR_NAME 50
+struct nt_info_sensor_s {
+	/* The source of the sensor (port or adapter on which the sensor resides) */
+	enum nt_sensor_source_e source;
+	/*
+	 * The source index - the adapter number for
+	 * adapter sensors and port number for port sensors
+	 */
+	uint32_t source_index;
+	/*
+	 * The sensor index within the source index
+	 * (sensor number on the adapter or sensor number on the port)
+	 */
+	uint32_t sensor_index;
+	enum nt_sensor_type_e type;	/* The sensor type */
+	enum nt_sensor_sub_type_e subtype;	/* The sensor subtype (if applicable) */
+	enum nt_sensor_state_e state;	/* The current state (normal or alarm) */
+	int32_t value;	/* The current value */
+	int32_t value_lowest;	/* The lowest value registered */
+	int32_t value_highest;	/* The highest value registered */
+	char name[NT_INFO_SENSOR_NAME + 1];	/* The sensor name */
+	enum nt_adapter_type_e adaptertype;	/* The adapter type where the sensor resides */
+};
+
+/*
+ * Port of the sensor class
+ */
+struct nt_adapter_sensor {
+	uint8_t m_adapter_no;
+	uint8_t m_intf_no;
+	uint8_t fpga_idx;	/* for AVR sensors */
+	enum sensor_mon_sign si;
+	struct nt_info_sensor_s info;
+	enum nt_sensor_event_alarm_e alarm;
+	bool m_enable_alarm;
+};
+
+struct nt_fpga_sensor_monitor {
+	nthw_fpga_t *FPGA;
+	nthw_module_t *mod;
+
+	nthw_register_t *reg;
+	nthw_field_t **fields;
+	uint8_t fields_num;
+};
+
+/*
+ * Sensor description.
+ * Describe the static behavior of the sensor.
+ */
+struct nt_adapter_sensor_description {
+	enum nt_sensor_type_e type;	/* Sensor type. */
+	enum nt_sensor_sub_type_e subtype;	/* Sensor subtype (if any applicable) */
+	unsigned int index;	/* Sensor group index. */
+	enum nt_sensor_event_alarm_e event_alarm;	/* Enable/Disable event alarm */
+	char name[20];	/* Sensor name. */
+};
+
+struct nt_sensor_group {
+	struct nt_adapter_sensor *sensor;
+	struct nt_fpga_sensor_monitor *monitor;
+	void (*read)(struct nt_sensor_group *sg, nthw_spis_t *t_spi);
+
+	/* conv params are needed to call current conversion functions */
+	int (*conv_func)(uint32_t p_sensor_result);
+	/* i2c interface for NIM sensors */
+
+	struct nt_sensor_group *next;
+};
+
+/* The NT200A02 adapter sensor id's */
+enum nt_sensors_adapter_nt200a02_e {
+	/* Public sensors (Level 0) */
+	NT_SENSOR_NT200A02_FPGA_TEMP,	/* FPGA temperature sensor */
+	NT_SENSOR_NT200A02_FAN_SPEED,	/* FAN speed sensor */
+	/* MCU (Micro Controller Unit) temperature sensor located inside enclosure below FAN */
+	NT_SENSOR_NT200A02_MCU_TEMP,
+	NT_SENSOR_NT200A02_PSU0_TEMP,	/* Power supply 0 temperature sensor */
+	NT_SENSOR_NT200A02_PSU1_TEMP,	/* Power supply 1 temperature sensor */
+	NT_SENSOR_NT200A02_PCB_TEMP,	/* PCB temperature sensor */
+
+	/* Diagnostic sensors (Level 1) */
+	/* Total power consumption (calculated value) - does not generate alarms */
+	NT_SENSOR_NT200A02_NT200A02_POWER,
+	/* FPGA power consumption (calculated value) - does not generate alarms */
+	NT_SENSOR_NT200A02_FPGA_POWER,
+	/* DDR4 RAM power consumption (calculated value) - does not generate alarms */
+	NT_SENSOR_NT200A02_DDR4_POWER,
+	/* NIM power consumption (calculated value) - does not generate alarms */
+	NT_SENSOR_NT200A02_NIM_POWER,
+	/* Number of NT200A01 level 0,1 board sensors */
+	NT_SENSOR_NT200A02_L1_MAX,
+};
+
+#endif	/* _NTNIC_SENSOR_H_ */
diff --git a/drivers/net/ntnic/include/ntnic_stat.h b/drivers/net/ntnic/include/ntnic_stat.h
new file mode 100644
index 0000000000..3ef5980cf5
--- /dev/null
+++ b/drivers/net/ntnic/include/ntnic_stat.h
@@ -0,0 +1,291 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef NTNIC_STAT_H_
+#define NTNIC_STAT_H_
+
+#include "common_adapter_defs.h"
+#include "nthw_fpga_model.h"
+
+#define NT_MAX_COLOR_FLOW_STATS 0x400
+
+struct nthw_stat {
+	nthw_fpga_t *mp_fpga;
+	nthw_module_t *mp_mod_stat;
+	int mn_instance;
+
+	int mn_stat_layout_version;
+
+	bool mb_is_vswitch;
+	bool mb_has_tx_stats;
+
+	int m_nb_phy_ports;
+	int m_nb_nim_ports;
+
+	int m_nb_rx_ports;
+	int m_nb_tx_ports;
+
+	int m_nb_rx_host_buffers;
+	int m_nb_tx_host_buffers;
+
+	int m_dbs_present;
+
+	int m_rx_port_replicate;
+
+	int m_nb_color_counters;
+
+	int m_nb_rx_hb_counters;
+	int m_nb_tx_hb_counters;
+
+	int m_nb_rx_port_counters;
+	int m_nb_tx_port_counters;
+
+	int m_nb_counters;
+
+	int m_nb_rpp_per_ps;
+
+	nthw_field_t *mp_fld_dma_ena;
+	nthw_field_t *mp_fld_cnt_clear;
+
+	nthw_field_t *mp_fld_tx_disable;
+
+	nthw_field_t *mp_fld_cnt_freeze;
+
+	nthw_field_t *mp_fld_stat_toggle_missed;
+
+	nthw_field_t *mp_fld_dma_lsb;
+	nthw_field_t *mp_fld_dma_msb;
+
+	nthw_field_t *mp_fld_load_bin;
+	nthw_field_t *mp_fld_load_bps_rx0;
+	nthw_field_t *mp_fld_load_bps_rx1;
+	nthw_field_t *mp_fld_load_bps_tx0;
+	nthw_field_t *mp_fld_load_bps_tx1;
+	nthw_field_t *mp_fld_load_pps_rx0;
+	nthw_field_t *mp_fld_load_pps_rx1;
+	nthw_field_t *mp_fld_load_pps_tx0;
+	nthw_field_t *mp_fld_load_pps_tx1;
+
+	uint64_t m_stat_dma_physical;
+	uint32_t *mp_stat_dma_virtual;
+
+	uint64_t last_ts;
+
+	uint64_t *mp_timestamp;
+};
+
+typedef struct nthw_stat nthw_stat_t;
+typedef struct nthw_stat nthw_stat;
+
+struct color_counters {
+	uint64_t color_packets;
+	uint64_t color_bytes;
+	uint8_t tcp_flags;
+};
+
+struct host_buffer_counters {
+	uint64_t flush_packets;
+	uint64_t drop_packets;
+	uint64_t fwd_packets;
+	uint64_t dbs_drop_packets;
+	uint64_t flush_bytes;
+	uint64_t drop_bytes;
+	uint64_t fwd_bytes;
+	uint64_t dbs_drop_bytes;
+};
+
+struct port_load_counters {
+	uint64_t rx_pps;
+	uint64_t rx_pps_max;
+	uint64_t tx_pps;
+	uint64_t tx_pps_max;
+	uint64_t rx_bps;
+	uint64_t rx_bps_max;
+	uint64_t tx_bps;
+	uint64_t tx_bps_max;
+};
+
+struct port_counters_v2 {
+	/* Rx/Tx common port counters */
+	uint64_t drop_events;
+	uint64_t pkts;
+	/* FPGA counters */
+	uint64_t octets;
+	uint64_t broadcast_pkts;
+	uint64_t multicast_pkts;
+	uint64_t unicast_pkts;
+	uint64_t pkts_alignment;
+	uint64_t pkts_code_violation;
+	uint64_t pkts_crc;
+	uint64_t undersize_pkts;
+	uint64_t oversize_pkts;
+	uint64_t fragments;
+	uint64_t jabbers_not_truncated;
+	uint64_t jabbers_truncated;
+	uint64_t pkts_64_octets;
+	uint64_t pkts_65_to_127_octets;
+	uint64_t pkts_128_to_255_octets;
+	uint64_t pkts_256_to_511_octets;
+	uint64_t pkts_512_to_1023_octets;
+	uint64_t pkts_1024_to_1518_octets;
+	uint64_t pkts_1519_to_2047_octets;
+	uint64_t pkts_2048_to_4095_octets;
+	uint64_t pkts_4096_to_8191_octets;
+	uint64_t pkts_8192_to_max_octets;
+	uint64_t mac_drop_events;
+	uint64_t pkts_lr;
+	/* Rx only port counters */
+	uint64_t duplicate;
+	uint64_t pkts_ip_chksum_error;
+	uint64_t pkts_udp_chksum_error;
+	uint64_t pkts_tcp_chksum_error;
+	uint64_t pkts_giant_undersize;
+	uint64_t pkts_baby_giant;
+	uint64_t pkts_not_isl_vlan_mpls;
+	uint64_t pkts_isl;
+	uint64_t pkts_vlan;
+	uint64_t pkts_isl_vlan;
+	uint64_t pkts_mpls;
+	uint64_t pkts_isl_mpls;
+	uint64_t pkts_vlan_mpls;
+	uint64_t pkts_isl_vlan_mpls;
+	uint64_t pkts_no_filter;
+	uint64_t pkts_dedup_drop;
+	uint64_t pkts_filter_drop;
+	uint64_t pkts_overflow;
+	uint64_t pkts_dbs_drop;
+	uint64_t octets_no_filter;
+	uint64_t octets_dedup_drop;
+	uint64_t octets_filter_drop;
+	uint64_t octets_overflow;
+	uint64_t octets_dbs_drop;
+	uint64_t ipft_first_hit;
+	uint64_t ipft_first_not_hit;
+	uint64_t ipft_mid_hit;
+	uint64_t ipft_mid_not_hit;
+	uint64_t ipft_last_hit;
+	uint64_t ipft_last_not_hit;
+};
+
+struct port_counters_vswitch_v1 {
+	/* Rx/Tx common port counters */
+	uint64_t octets;
+	uint64_t pkts;
+	uint64_t drop_events;
+	uint64_t qos_drop_octets;
+	uint64_t qos_drop_pkts;
+};
+
+struct flm_counters_v1 {
+	/* FLM 0.17 */
+	uint64_t current;
+	uint64_t learn_done;
+	uint64_t learn_ignore;
+	uint64_t learn_fail;
+	uint64_t unlearn_done;
+	uint64_t unlearn_ignore;
+	uint64_t auto_unlearn_done;
+	uint64_t auto_unlearn_ignore;
+	uint64_t auto_unlearn_fail;
+	uint64_t timeout_unlearn_done;
+	uint64_t rel_done;
+	uint64_t rel_ignore;
+	/* FLM 0.20 */
+	uint64_t prb_done;
+	uint64_t prb_ignore;
+	uint64_t sta_done;
+	uint64_t inf_done;
+	uint64_t inf_skip;
+	uint64_t pck_hit;
+	uint64_t pck_miss;
+	uint64_t pck_unh;
+	uint64_t pck_dis;
+	uint64_t csh_hit;
+	uint64_t csh_miss;
+	uint64_t csh_unh;
+	uint64_t cuc_start;
+	uint64_t cuc_move;
+	/* FLM 0.17 Load */
+	uint64_t load_lps;
+	uint64_t load_aps;
+	uint64_t max_lps;
+	uint64_t max_aps;
+};
+
+struct nt4ga_stat_s {
+	nthw_stat_t *mp_nthw_stat;
+	struct nt_dma_s *p_stat_dma;
+	uint32_t *p_stat_dma_virtual;
+	uint32_t n_stat_size;
+
+	uint64_t last_timestamp;
+
+	int mn_rx_host_buffers;
+	int mn_tx_host_buffers;
+
+	int mn_rx_ports;
+	int mn_tx_ports;
+
+	struct color_counters *mp_stat_structs_color;
+	/* For calculating increments between stats polls */
+	struct color_counters a_stat_structs_color_base[NT_MAX_COLOR_FLOW_STATS];
+
+	union {
+		/* Port counters for VSWITCH/inline */
+		struct {
+			struct port_counters_vswitch_v1 *mp_stat_structs_port_rx;
+			struct port_counters_vswitch_v1 *mp_stat_structs_port_tx;
+		} virt;
+		struct {
+			struct port_counters_v2 *mp_stat_structs_port_rx;
+			struct port_counters_v2 *mp_stat_structs_port_tx;
+		} cap;
+	};
+
+	struct host_buffer_counters *mp_stat_structs_hb;
+	struct port_load_counters *mp_port_load;
+
+	int flm_stat_ver;
+	struct flm_counters_v1 *mp_stat_structs_flm;
+
+	/* Rx/Tx totals: */
+	uint64_t n_totals_reset_timestamp;	/* timestamp for last totals reset */
+
+	uint64_t a_port_rx_octets_total[NUM_ADAPTER_PORTS_MAX];
+	/* Base is for calculating increments between statistics reads */
+	uint64_t a_port_rx_octets_base[NUM_ADAPTER_PORTS_MAX];
+
+	uint64_t a_port_rx_packets_total[NUM_ADAPTER_PORTS_MAX];
+	uint64_t a_port_rx_packets_base[NUM_ADAPTER_PORTS_MAX];
+
+	uint64_t a_port_rx_drops_total[NUM_ADAPTER_PORTS_MAX];
+	uint64_t a_port_rx_drops_base[NUM_ADAPTER_PORTS_MAX];
+
+	uint64_t a_port_tx_octets_total[NUM_ADAPTER_PORTS_MAX];
+	uint64_t a_port_tx_octets_base[NUM_ADAPTER_PORTS_MAX];
+
+	uint64_t a_port_tx_packets_base[NUM_ADAPTER_PORTS_MAX];
+	uint64_t a_port_tx_packets_total[NUM_ADAPTER_PORTS_MAX];
+
+	uint64_t a_port_tx_drops_base[NUM_ADAPTER_PORTS_MAX];
+	uint64_t a_port_tx_drops_total[NUM_ADAPTER_PORTS_MAX];
+};
+
+typedef struct nt4ga_stat_s nt4ga_stat_t;
+
+nthw_stat_t *nthw_stat_new(void);
+int nthw_stat_init(nthw_stat_t *p, nthw_fpga_t *p_fpga, int n_instance);
+void nthw_stat_delete(nthw_stat_t *p);
+
+int nthw_stat_set_dma_address(nthw_stat_t *p, uint64_t stat_dma_physical,
+	uint32_t *p_stat_dma_virtual);
+int nthw_stat_trigger(nthw_stat_t *p);
+
+int nthw_stat_get_load_bps_rx(nthw_stat_t *p, uint8_t port, uint32_t *val);
+int nthw_stat_get_load_bps_tx(nthw_stat_t *p, uint8_t port, uint32_t *val);
+int nthw_stat_get_load_pps_rx(nthw_stat_t *p, uint8_t port, uint32_t *val);
+int nthw_stat_get_load_pps_tx(nthw_stat_t *p, uint8_t port, uint32_t *val);
+
+#endif	/* NTNIC_STAT_H_ */
-- 
2.44.0


^ permalink raw reply	[flat|nested] 238+ messages in thread

* [PATCH v1 07/17] net/ntnic: add API for PMD driver modules
  2024-05-30 14:48 [PATCH v1 01/17] net/ntnic: Add registers for NapaTech SmartNiC Serhii Iliushyk
                   ` (4 preceding siblings ...)
  2024-05-30 14:49 ` [PATCH v1 06/17] net/ntnic: add interfaces for PMD driver modules Serhii Iliushyk
@ 2024-05-30 14:49 ` Serhii Iliushyk
  2024-05-30 14:49 ` [PATCH v1 08/17] net/ntnic: add interfaces for flow API engine Serhii Iliushyk
                   ` (18 subsequent siblings)
  24 siblings, 0 replies; 238+ messages in thread
From: Serhii Iliushyk @ 2024-05-30 14:49 UTC (permalink / raw)
  To: dev; +Cc: mko-plv, ckm, andrew.rybchenko, ferruh.yigit

Add API for ntnic PMD driver modules,
thus allow modules to be enabled/disabled.

Signed-off-by: Serhii Iliushyk <sil-plv@napatech.com>
---
 drivers/net/ntnic/dpdk_mod_reg.c  |  64 ++++
 drivers/net/ntnic/dpdk_mod_reg.h  | 167 ++++++++++
 drivers/net/ntnic/ntnic_mod_reg.c | 382 ++++++++++++++++++++++
 drivers/net/ntnic/ntnic_mod_reg.h | 512 ++++++++++++++++++++++++++++++
 4 files changed, 1125 insertions(+)
 create mode 100644 drivers/net/ntnic/dpdk_mod_reg.c
 create mode 100644 drivers/net/ntnic/dpdk_mod_reg.h
 create mode 100644 drivers/net/ntnic/ntnic_mod_reg.c
 create mode 100644 drivers/net/ntnic/ntnic_mod_reg.h

diff --git a/drivers/net/ntnic/dpdk_mod_reg.c b/drivers/net/ntnic/dpdk_mod_reg.c
new file mode 100644
index 0000000000..dec3e54dc0
--- /dev/null
+++ b/drivers/net/ntnic/dpdk_mod_reg.c
@@ -0,0 +1,64 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#include <rte_flow_driver.h>
+#include "dpdk_mod_reg.h"
+
+static struct sg_ops_s *sg_ops;
+
+void register_sg_ops(struct sg_ops_s *ops)
+{
+	sg_ops = ops;
+}
+
+const struct sg_ops_s *get_sg_ops(void)
+{
+	return sg_ops;
+}
+
+/*
+ *
+ */
+static struct meter_ops_s *meter_ops;
+
+void register_meter_ops(struct meter_ops_s *ops)
+{
+	meter_ops = ops;
+}
+
+const struct meter_ops_s *get_meter_ops(void)
+{
+	return meter_ops;
+}
+
+/*
+ *
+ */
+static const struct ntnic_filter_ops *ntnic_filter_ops;
+
+void register_ntnic_filter_ops(const struct ntnic_filter_ops *ops)
+{
+	ntnic_filter_ops = ops;
+}
+
+const struct ntnic_filter_ops *get_ntnic_filter_ops(void)
+{
+	return ntnic_filter_ops;
+}
+
+/*
+ *
+ */
+static struct ntnic_xstats_ops *ntnic_xstats_ops;
+
+void register_ntnic_xstats_ops(struct ntnic_xstats_ops *ops)
+{
+	ntnic_xstats_ops = ops;
+}
+
+struct ntnic_xstats_ops *get_ntnic_xstats_ops(void)
+{
+	return ntnic_xstats_ops;
+}
diff --git a/drivers/net/ntnic/dpdk_mod_reg.h b/drivers/net/ntnic/dpdk_mod_reg.h
new file mode 100644
index 0000000000..5cc866f98c
--- /dev/null
+++ b/drivers/net/ntnic/dpdk_mod_reg.h
@@ -0,0 +1,167 @@
+#ifndef __DPDK_MOD_REG_H__
+#define __DPDK_MOD_REG_H__
+
+#include <rte_ethdev.h>
+#include "ntnic_ethdev.h"
+#include "ntoss_virt_queue.h"
+#include "ntnic_stat.h"
+
+/* sg ops section */
+struct sg_ops_s {
+	/* Setup a virtQueue for a VM */
+	struct nthw_virt_queue *(*nthw_setup_rx_virt_queue)(nthw_dbs_t *p_nthw_dbs,
+		uint32_t index,
+		uint16_t start_idx,
+		uint16_t start_ptr,
+		void *avail_struct_phys_addr,
+		void *used_struct_phys_addr,
+		void *desc_struct_phys_addr,
+		uint16_t queue_size,
+		uint32_t host_id,
+		uint32_t header,
+		uint32_t vq_type,
+		int irq_vector);
+	int (*nthw_enable_rx_virt_queue)(struct nthw_virt_queue *rx_vq);
+	int (*nthw_disable_rx_virt_queue)(struct nthw_virt_queue *rx_vq);
+	int (*nthw_release_rx_virt_queue)(struct nthw_virt_queue *rxvq);
+	struct nthw_virt_queue *(*nthw_setup_tx_virt_queue)(nthw_dbs_t *p_nthw_dbs,
+		uint32_t index,
+		uint16_t start_idx,
+		uint16_t start_ptr,
+		void *avail_struct_phys_addr,
+		void *used_struct_phys_addr,
+		void *desc_struct_phys_addr,
+		uint16_t queue_size,
+		uint32_t host_id,
+		uint32_t port,
+		uint32_t virtual_port,
+		uint32_t header,
+		uint32_t vq_type,
+		int irq_vector,
+		uint32_t in_order);
+	int (*nthw_enable_tx_virt_queue)(struct nthw_virt_queue *tx_vq);
+	int (*nthw_disable_tx_virt_queue)(struct nthw_virt_queue *tx_vq);
+	int (*nthw_release_tx_virt_queue)(struct nthw_virt_queue *txvq);
+	int (*nthw_enable_and_change_port_tx_virt_queue)(struct nthw_virt_queue *tx_vq,
+		uint32_t outport);
+	struct nthw_virt_queue *(*nthw_setup_managed_rx_virt_queue)(nthw_dbs_t *p_nthw_dbs,
+		uint32_t index,
+		uint32_t queue_size,
+		uint32_t host_id,
+		uint32_t header,
+		/*
+		 * Memory that can be used
+		 * for virtQueue structs
+		 */
+		struct nthw_memory_descriptor *p_virt_struct_area,
+		/*
+		 * Memory that can be used for packet
+		 * buffers - Array must have queue_size
+		 * entries
+		 */
+		struct nthw_memory_descriptor *p_packet_buffers,
+		uint32_t vq_type,
+		int irq_vector);
+	int (*nthw_release_managed_rx_virt_queue)(struct nthw_virt_queue *rxvq);
+	struct nthw_virt_queue *(*nthw_setup_managed_tx_virt_queue)(nthw_dbs_t *p_nthw_dbs,
+		uint32_t index,
+		uint32_t queue_size,
+		uint32_t host_id,
+		uint32_t port,
+		uint32_t virtual_port,
+		uint32_t header,
+		/*
+		 * Memory that can be used
+		 * for virtQueue structs
+		 */
+		struct nthw_memory_descriptor *p_virt_struct_area,
+		/*
+		 * Memory that can be used for packet
+		 * buffers - Array must have queue_size
+		 * entries
+		 */
+		struct nthw_memory_descriptor *p_packet_buffers,
+		uint32_t vq_type,
+		int irq_vector,
+		uint32_t in_order);
+	int (*nthw_release_managed_tx_virt_queue)(struct nthw_virt_queue *txvq);
+	int (*nthw_set_tx_qos_config)(nthw_dbs_t *p_nthw_dbs, uint32_t port, uint32_t enable,
+		uint32_t ir, uint32_t bs);
+	int (*nthw_set_tx_qos_rate_global)(nthw_dbs_t *p_nthw_dbs,
+		uint32_t multiplier,
+		uint32_t divider);
+	/*
+	 * These functions handles both Split and Packed including merged buffers (jumbo)
+	 */
+	uint16_t (*nthw_get_rx_packets)(struct nthw_virt_queue *rxvq,
+		uint16_t n,
+		struct nthw_received_packets *rp,
+		uint16_t *nb_pkts);
+	void (*nthw_release_rx_packets)(struct nthw_virt_queue *rxvq, uint16_t n);
+	uint16_t (*nthw_get_tx_buffers)(struct nthw_virt_queue *txvq,
+		uint16_t n,
+		uint16_t *first_idx,
+		struct nthw_cvirtq_desc *cvq,
+		struct nthw_memory_descriptor **p_virt_addr);
+	void (*nthw_release_tx_buffers)(struct nthw_virt_queue *txvq,
+		uint16_t n,
+		uint16_t n_segs[]);
+	int (*nthw_get_rx_queue_ptr)(struct nthw_virt_queue *rxvq, uint16_t *index);
+	int (*nthw_get_tx_queue_ptr)(struct nthw_virt_queue *txvq, uint16_t *index);
+	int (*nthw_virt_queue_init)(struct fpga_info_s *p_fpga_info);
+};
+
+void register_sg_ops(struct sg_ops_s *ops);
+const struct sg_ops_s *get_sg_ops(void);
+
+/* Meter ops section */
+struct meter_ops_s {
+	int (*eth_mtr_ops_get)(struct rte_eth_dev *eth_dev, void *ops);
+};
+
+void register_meter_ops(struct meter_ops_s *ops);
+const struct meter_ops_s *get_meter_ops(void);
+
+/*
+ *
+ */
+#ifdef __NTNIC_ETHDEV_H__
+struct ntnic_filter_ops {
+	int (*poll_statistics)(struct pmd_internals *internals);
+};
+
+void register_ntnic_filter_ops(const struct ntnic_filter_ops *ops);
+const struct ntnic_filter_ops *get_ntnic_filter_ops(void);
+#endif
+
+/*
+ *
+ */
+struct ntnic_xstats_ops {
+	int (*nthw_xstats_get_names)(nt4ga_stat_t *p_nt4ga_stat,
+		struct rte_eth_xstat_name *xstats_names,
+		unsigned int size,
+		bool is_vswitch);
+	int (*nthw_xstats_get)(nt4ga_stat_t *p_nt4ga_stat,
+		struct rte_eth_xstat *stats,
+		unsigned int n,
+		bool is_vswitch,
+		uint8_t port);
+	void (*nthw_xstats_reset)(nt4ga_stat_t *p_nt4ga_stat, bool is_vswitch, uint8_t port);
+	int (*nthw_xstats_get_names_by_id)(nt4ga_stat_t *p_nt4ga_stat,
+		struct rte_eth_xstat_name *xstats_names,
+		const uint64_t *ids,
+		unsigned int size,
+		bool is_vswitch);
+	int (*nthw_xstats_get_by_id)(nt4ga_stat_t *p_nt4ga_stat,
+		const uint64_t *ids,
+		uint64_t *values,
+		unsigned int n,
+		bool is_vswitch,
+		uint8_t port);
+};
+
+void register_ntnic_xstats_ops(struct ntnic_xstats_ops *ops);
+struct ntnic_xstats_ops *get_ntnic_xstats_ops(void);
+
+#endif	/* __DPDK_MOD_REG_H__ */
diff --git a/drivers/net/ntnic/ntnic_mod_reg.c b/drivers/net/ntnic/ntnic_mod_reg.c
new file mode 100644
index 0000000000..acd8da40d5
--- /dev/null
+++ b/drivers/net/ntnic/ntnic_mod_reg.c
@@ -0,0 +1,382 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#include <rte_flow_driver.h>
+#include "ntnic_mod_reg.h"
+
+/*
+ *
+ */
+static struct link_ops_s *link_100g_ops;
+
+void register_100g_link_ops(struct link_ops_s *ops)
+{
+	link_100g_ops = ops;
+}
+
+const struct link_ops_s *get_100g_link_ops(void)
+{
+	return link_100g_ops;
+}
+
+/*
+ *
+ */
+static struct link_ops_s *link_agx_100g_ops;
+
+void register_agx_100g_link_ops(struct link_ops_s *ops)
+{
+	link_agx_100g_ops = ops;
+}
+
+const struct link_ops_s *get_agx_100g_link_ops(void)
+{
+	return link_agx_100g_ops;
+}
+
+/*
+ *
+ */
+static struct link_ops_s *link_25g_ops;
+
+void register_25g_link_ops(struct link_ops_s *ops)
+{
+	link_25g_ops = ops;
+}
+
+const struct link_ops_s *get_25g_link_ops(void)
+{
+	return link_25g_ops;
+}
+
+/*
+ *
+ */
+static struct link_ops_s *link_40g_ops;
+
+void register_40g_link_ops(struct link_ops_s *ops)
+{
+	link_40g_ops = ops;
+}
+
+const struct link_ops_s *get_40g_link_ops(void)
+{
+	return link_40g_ops;
+}
+
+/*
+ *
+ */
+static struct link_ops_s *link_8x10g_ops;
+
+void register_8x10g_link_ops(struct link_ops_s *ops)
+{
+	link_8x10g_ops = ops;
+}
+
+const struct link_ops_s *get_8x10g_link_ops(void)
+{
+	return link_8x10g_ops;
+}
+
+/*
+ *
+ */
+static struct avr_sensors_ops *avr_sensors_ops;
+
+void register_avr_sensors_ops(struct avr_sensors_ops *ops)
+{
+	avr_sensors_ops = ops;
+}
+
+struct avr_sensors_ops *get_avr_sensors_ops(void)
+{
+	return avr_sensors_ops;
+}
+
+/*
+ *
+ */
+static struct board_sensors_ops *board_sensors_ops;
+
+void register_board_sensors_ops(struct board_sensors_ops *ops)
+{
+	board_sensors_ops = ops;
+}
+
+struct board_sensors_ops *get_board_sensors_ops(void)
+{
+	return board_sensors_ops;
+}
+
+/*
+ *
+ */
+static struct ntavr_ops *ntavr_ops;
+
+void register_ntavr_ops(struct ntavr_ops *ops)
+{
+	ntavr_ops = ops;
+}
+
+struct ntavr_ops *get_ntavr_ops(void)
+{
+	return ntavr_ops;
+}
+
+/*
+ *
+ */
+static struct sensor_convertion_fun_ops *sensor_convertion_fun_ops;
+
+void register_sensor_convertion_fun_ops(struct sensor_convertion_fun_ops *ops)
+{
+	sensor_convertion_fun_ops = ops;
+}
+
+struct sensor_convertion_fun_ops *get_sensor_convertion_fun_ops(void)
+{
+	return sensor_convertion_fun_ops;
+}
+
+/*
+ *
+ */
+static struct sensor_ops *sensor_ops;
+
+void register_sensor_ops(struct sensor_ops *ops)
+{
+	sensor_ops = ops;
+}
+
+struct sensor_ops *get_sensor_ops(void)
+{
+	return sensor_ops;
+}
+
+/*
+ *
+ */
+static struct nim_sensors_ops *nim_sensors_ops;
+
+void register_nim_sensors_ops(struct nim_sensors_ops *ops)
+{
+	nim_sensors_ops = ops;
+}
+
+struct nim_sensors_ops *get_nim_sensors_ops(void)
+{
+	return nim_sensors_ops;
+}
+
+/*
+ *
+ */
+static const struct port_ops *port_ops;
+
+void register_port_ops(const struct port_ops *ops)
+{
+	port_ops = ops;
+}
+
+const struct port_ops *get_port_ops(void)
+{
+	return port_ops;
+}
+
+/*
+ *
+ */
+static const struct nt4ga_stat_ops *nt4ga_stat_ops;
+
+void register_nt4ga_stat_ops(const struct nt4ga_stat_ops *ops)
+{
+	nt4ga_stat_ops = ops;
+}
+
+const struct nt4ga_stat_ops *get_nt4ga_stat_ops(void)
+{
+	return nt4ga_stat_ops;
+}
+
+/*
+ *
+ */
+static const struct adapter_ops *adapter_ops;
+
+void register_adapter_ops(const struct adapter_ops *ops)
+{
+	adapter_ops = ops;
+}
+
+const struct adapter_ops *get_adapter_ops(void)
+{
+	return adapter_ops;
+}
+
+static struct clk9530_ops *clk9530_ops;
+
+void register_clk9530_ops(struct clk9530_ops *ops)
+{
+	clk9530_ops = ops;
+}
+
+struct clk9530_ops *get_clk9530_ops(void)
+{
+	return clk9530_ops;
+}
+
+static struct clk9544_ops *clk9544_ops;
+
+void register_clk9544_ops(struct clk9544_ops *ops)
+{
+	clk9544_ops = ops;
+}
+
+struct clk9544_ops *get_clk9544_ops(void)
+{
+	return clk9544_ops;
+}
+
+static struct clk9563_ops *clk9563_ops;
+
+void register_clk9563_ops(struct clk9563_ops *ops)
+{
+	clk9563_ops = ops;
+}
+
+struct clk9563_ops *get_clk9563_ops(void)
+{
+	return clk9563_ops;
+}
+
+static struct clk9572_ops *clk9572_ops;
+
+void register_clk9572_ops(struct clk9572_ops *ops)
+{
+	clk9572_ops = ops;
+}
+
+struct clk9572_ops *get_clk9572_ops(void)
+{
+	return clk9572_ops;
+}
+
+static struct rst_nt200a0x_ops *rst_nt200a0x_ops;
+
+void register_rst_nt200a0x_ops(struct rst_nt200a0x_ops *ops)
+{
+	rst_nt200a0x_ops = ops;
+}
+
+struct rst_nt200a0x_ops *get_rst_nt200a0x_ops(void)
+{
+	return rst_nt200a0x_ops;
+}
+
+static struct rst9530_ops *rst9530_ops;
+
+void register_rst9530_ops(struct rst9530_ops *ops)
+{
+	rst9530_ops = ops;
+}
+
+struct rst9530_ops *get_rst9530_ops(void)
+{
+	return rst9530_ops;
+}
+
+static struct rst9544_ops *rst9544_ops;
+
+void register_rst9544_ops(struct rst9544_ops *ops)
+{
+	rst9544_ops = ops;
+}
+
+struct rst9544_ops *get_rst9544_ops(void)
+{
+	return rst9544_ops;
+}
+
+static struct rst9563_ops *rst9563_ops;
+
+void register_rst9563_ops(struct rst9563_ops *ops)
+{
+	rst9563_ops = ops;
+}
+
+struct rst9563_ops *get_rst9563_ops(void)
+{
+	return rst9563_ops;
+}
+
+static struct rst9572_ops *rst9572_ops;
+
+void register_rst9572_ops(struct rst9572_ops *ops)
+{
+	rst9572_ops = ops;
+}
+
+struct rst9572_ops *get_rst9572_ops(void)
+{
+	return rst9572_ops;
+}
+
+static struct rst_nt400dxx_ops *rst_nt400dxx_ops;
+
+void register_rst_nt400dxx_ops(struct rst_nt400dxx_ops *ops)
+{
+	rst_nt400dxx_ops = ops;
+}
+
+struct rst_nt400dxx_ops *get_rst_nt400dxx_ops(void)
+{
+	return rst_nt400dxx_ops;
+}
+
+/*
+ *
+ */
+static const struct profile_inline_ops *profile_inline_ops;
+
+void register_profile_inline_ops(const struct profile_inline_ops *ops)
+{
+	profile_inline_ops = ops;
+}
+
+const struct profile_inline_ops *get_profile_inline_ops(void)
+{
+	return profile_inline_ops;
+}
+
+/*
+ *
+ */
+static const struct flow_filter_ops *flow_filter_ops;
+
+void register_flow_filter_ops(const struct flow_filter_ops *ops)
+{
+	flow_filter_ops = ops;
+}
+
+const struct flow_filter_ops *get_flow_filter_ops(void)
+{
+	return flow_filter_ops;
+}
+
+/*
+ *
+ */
+static const struct rte_flow_ops *dev_flow_ops;
+
+void register_dev_flow_ops(const struct rte_flow_ops *ops)
+{
+	dev_flow_ops = ops;
+}
+
+const struct rte_flow_ops *get_dev_flow_ops(void)
+{
+	return dev_flow_ops;
+}
diff --git a/drivers/net/ntnic/ntnic_mod_reg.h b/drivers/net/ntnic/ntnic_mod_reg.h
new file mode 100644
index 0000000000..718f3245c0
--- /dev/null
+++ b/drivers/net/ntnic/ntnic_mod_reg.h
@@ -0,0 +1,512 @@
+#ifndef __NTNIC_MOD_REG_H__
+#define __NTNIC_MOD_REG_H__
+
+#include <stdint.h>
+#include "flow_api.h"
+#include "stream_binary_flow_api.h"
+#include "nthw_fpga_model.h"
+#include "nthw_platform_drv.h"
+#include "ntnic_stat.h"
+#include "nthw_drv.h"
+#include "nt4ga_adapter.h"
+
+/*
+ *
+ */
+struct link_ops_s {
+	int (*link_init)(struct adapter_info_s *p_adapter_info, nthw_fpga_t *p_fpga);
+};
+
+void register_100g_link_ops(struct link_ops_s *ops);
+const struct link_ops_s *get_100g_link_ops(void);
+
+void register_agx_100g_link_ops(struct link_ops_s *ops);
+const struct link_ops_s *get_agx_100g_link_ops(void);
+
+void register_25g_link_ops(struct link_ops_s *ops);
+const struct link_ops_s *get_25g_link_ops(void);
+
+void register_40g_link_ops(struct link_ops_s *ops);
+const struct link_ops_s *get_40g_link_ops(void);
+
+void register_8x10g_link_ops(struct link_ops_s *ops);
+const struct link_ops_s *get_8x10g_link_ops(void);
+
+/*
+ *
+ */
+struct avr_sensors_ops {
+	struct nt_sensor_group *(*avr_sensor_init)(nthw_spi_v3_t *s_spi, uint8_t m_adapter_no,
+		const char *p_name,
+		enum nt_sensor_source_e ssrc, enum nt_sensor_type_e type, unsigned int index,
+		enum sensor_mon_device avr_dev, uint8_t avr_dev_reg, enum sensor_mon_endian end,
+		enum sensor_mon_sign si, int (*conv_func)(uint32_t), uint16_t mask);
+};
+
+void register_avr_sensors_ops(struct avr_sensors_ops *ops);
+struct avr_sensors_ops *get_avr_sensors_ops(void);
+
+/*
+ *
+ */
+struct board_sensors_ops {
+	struct nt_sensor_group *(*fpga_temperature_sensor_init)(uint8_t adapter_no,
+		unsigned int sensor_idx,
+		nthw_fpga_t *p_fpga);
+};
+
+void register_board_sensors_ops(struct board_sensors_ops *ops);
+struct board_sensors_ops *get_board_sensors_ops(void);
+
+/*
+ *
+ */
+struct ntavr_ops {
+	int (*nt_avr_sensor_mon_ctrl)(nthw_spi_v3_t *s_spi, enum sensor_mon_control ctrl);
+	int (*nt_avr_sensor_mon_setup)(struct sensor_mon_setup16 *p_setup, nthw_spi_v3_t *s_spi);
+	uint32_t (*sensor_read)(nthw_spis_t *t_spi, uint8_t fpga_idx, uint32_t *p_sensor_result);
+};
+
+void register_ntavr_ops(struct ntavr_ops *ops);
+struct ntavr_ops *get_ntavr_ops(void);
+
+/*
+ *
+ */
+struct sensor_convertion_fun_ops {
+	int (*null_signed)(uint32_t p_sensor_result);
+	int (*exar7724_tj)(uint32_t p_sensor_result);
+	int (*ds1775_t)(uint32_t p_sensor_result);
+	int (*mp2886a_tj)(uint32_t p_sensor_result);
+	int (*fan)(uint32_t p_sensor_result);
+	int (*null_sign)(uint32_t sensor_result);
+	int (*tmp464p_t)(uint32_t p_sensor_result);
+	int (*fan_nt400)(uint32_t sensor_result);
+	int (*mp8645p_tj)(uint32_t sensor_result);
+	int (*mp2978_t)(uint32_t sensor_result);
+	int (*max6642_t)(uint32_t p_sensor_result);
+	int (*ltm4676_tj)(uint32_t p_sensor_result);
+	int (*exar7724_vin)(uint32_t p_sensor_result);
+	int (*exar7724_vch)(uint32_t p_sensor_result);
+	int (*null_unsigned)(uint32_t p_sensor_result);
+};
+
+void register_sensor_convertion_fun_ops(struct sensor_convertion_fun_ops *ops);
+struct sensor_convertion_fun_ops *get_sensor_convertion_fun_ops(void);
+
+/*
+ *
+ */
+struct sensor_ops {
+	void (*update_sensor_value)(struct nt_adapter_sensor *sensor, int32_t value);
+	void (*sensor_deinit)(struct nt_sensor_group *sg);
+	struct nt_adapter_sensor *(*allocate_sensor_by_description)(uint8_t adapter_or_port_index,
+		enum nt_sensor_source_e ssrc,
+		struct nt_adapter_sensor_description *descr);
+	void (*dump_sensor)(struct nt_adapter_sensor *sensor);
+	struct nt_adapter_sensor *(*allocate_sensor)(uint8_t adapter_or_port_index,
+		const char *p_name,
+		enum nt_sensor_source_e ssrc,
+		enum nt_sensor_type_e type,
+		unsigned int index,
+		enum nt_sensor_event_alarm_e event_alarm,
+		enum sensor_mon_sign si);
+	void (*init_sensor_group)(struct nt_sensor_group *sg);
+	int32_t (*get_value)(struct nt_sensor_group *sg);
+	int32_t (*get_lowest)(struct nt_sensor_group *sg);
+	int32_t (*get_highest)(struct nt_sensor_group *sg);
+	char *(*get_name)(struct nt_sensor_group *sg);
+};
+
+void register_sensor_ops(struct sensor_ops *ops);
+struct sensor_ops *get_sensor_ops(void);
+
+/*
+ *
+ */
+struct nim_sensors_ops {
+	struct nt_adapter_sensor_description *(*get_sfp_sensors_level0)(void);
+	struct nt_adapter_sensor_description *(*get_sfp_sensors_level1)(void);
+	struct nt_adapter_sensor_description *(*get_qsfp_sensor_level0)(void);
+	struct nt_adapter_sensor_description *(*get_qsfp_sensor_level1)(void);
+	struct nt_adapter_sensor *(*allocate_sensor_by_description)(uint8_t adapter_or_port_index,
+		enum nt_sensor_source_e src,
+		struct nt_adapter_sensor_description *descr);
+	void (*update_sensor_value)(struct nt_adapter_sensor *sensor, int32_t value);
+};
+
+void register_nim_sensors_ops(struct nim_sensors_ops *ops);
+struct nim_sensors_ops *get_nim_sensors_ops(void);
+
+/*
+ *
+ */
+struct port_ops {
+	bool (*get_nim_present)(struct adapter_info_s *p, int port);
+
+	/*
+	 * port:s link mode
+	 */
+	void (*set_adm_state)(struct adapter_info_s *p, int port, bool adm_state);
+	bool (*get_adm_state)(struct adapter_info_s *p, int port);
+
+	/*
+	 * port:s link status
+	 */
+	void (*set_link_status)(struct adapter_info_s *p, int port, bool status);
+	bool (*get_link_status)(struct adapter_info_s *p, int port);
+
+	/*
+	 * port: link autoneg
+	 */
+	void (*set_link_autoneg)(struct adapter_info_s *p, int port, bool autoneg);
+	bool (*get_link_autoneg)(struct adapter_info_s *p, int port);
+
+	/*
+	 * port: link speed
+	 */
+	void (*set_link_speed)(struct adapter_info_s *p, int port, nt_link_speed_t speed);
+	nt_link_speed_t (*get_link_speed)(struct adapter_info_s *p, int port);
+
+	/*
+	 * port: link duplex
+	 */
+	void (*set_link_duplex)(struct adapter_info_s *p, int port, nt_link_duplex_t duplex);
+	nt_link_duplex_t (*get_link_duplex)(struct adapter_info_s *p, int port);
+
+	/*
+	 * port: loopback mode
+	 */
+	void (*set_loopback_mode)(struct adapter_info_s *p, int port, uint32_t mode);
+	uint32_t (*get_loopback_mode)(struct adapter_info_s *p, int port);
+
+	uint32_t (*get_link_speed_capabilities)(struct adapter_info_s *p, int port);
+
+	/*
+	 * port: nim capabilities
+	 */
+	nim_i2c_ctx_t (*get_nim_capabilities)(struct adapter_info_s *p, int port);
+
+	/*
+	 * port: tx power
+	 */
+	int (*tx_power)(struct adapter_info_s *p, int port, bool disable);
+};
+
+void register_port_ops(const struct port_ops *ops);
+const struct port_ops *get_port_ops(void);
+
+/*
+ *
+ */
+struct nt4ga_stat_ops {
+	int (*nt4ga_stat_init)(struct adapter_info_s *p_adapter_info);
+	int (*nt4ga_stat_setup)(struct adapter_info_s *p_adapter_info);
+	int (*nt4ga_stat_stop)(struct adapter_info_s *p_adapter_info);
+	int (*nt4ga_stat_dump)(struct adapter_info_s *p_adapter_info, FILE *pfh);
+	int (*nt4ga_stat_collect)(struct adapter_info_s *p_adapter_info,
+		nt4ga_stat_t *p_nt4ga_stat);
+};
+
+void register_nt4ga_stat_ops(const struct nt4ga_stat_ops *ops);
+const struct nt4ga_stat_ops *get_nt4ga_stat_ops(void);
+
+/*
+ *
+ */
+struct adapter_ops {
+	int (*init)(struct adapter_info_s *p_adapter_info);
+	int (*deinit)(struct adapter_info_s *p_adapter_info);
+
+	int (*show_info)(struct adapter_info_s *p_adapter_info, FILE *pfh);
+};
+
+void register_adapter_ops(const struct adapter_ops *ops);
+const struct adapter_ops *get_adapter_ops(void);
+
+struct clk9530_ops {
+	const int *(*get_n_data_9530_si5340_nt200a02_u23_v6)(void);
+	const clk_profile_data_fmt2_t *(*get_p_data_9530_si5340_nt200a02_u23_v6)(void);
+};
+
+void register_clk9530_ops(struct clk9530_ops *ops);
+struct clk9530_ops *get_clk9530_ops(void);
+
+struct clk9544_ops {
+	const int *(*get_n_data_9544_si5340_nt200a02_u23_v6)(void);
+	const clk_profile_data_fmt2_t *(*get_p_data_9544_si5340_nt200a02_u23_v6)(void);
+};
+
+void register_clk9544_ops(struct clk9544_ops *ops);
+struct clk9544_ops *get_clk9544_ops(void);
+
+struct clk9563_ops {
+	const int *(*get_n_data_9563_si5340_nt200a02_u23_v5)(void);
+	const clk_profile_data_fmt2_t *(*get_p_data_9563_si5340_nt200a02_u23_v5)(void);
+};
+
+void register_clk9563_ops(struct clk9563_ops *ops);
+struct clk9563_ops *get_clk9563_ops(void);
+
+struct clk9572_ops {
+	const int *(*get_n_data_9572_si5340_nt200a02_u23_v12)(void);
+	const clk_profile_data_fmt2_t *(*get_p_data_9572_si5340_nt200a02_u23_v12)(void);
+};
+
+void register_clk9572_ops(struct clk9572_ops *ops);
+struct clk9572_ops *get_clk9572_ops(void);
+
+struct rst_nt200a0x_ops {
+	int (*nthw_fpga_rst_nt200a0x_init)(struct fpga_info_s *p_fpga_info,
+		struct nthw_fpga_rst_nt200a0x *p_rst);
+	int (*nthw_fpga_rst_nt200a0x_reset)(nthw_fpga_t *p_fpga,
+		const struct nthw_fpga_rst_nt200a0x *p);
+};
+
+void register_rst_nt200a0x_ops(struct rst_nt200a0x_ops *ops);
+struct rst_nt200a0x_ops *get_rst_nt200a0x_ops(void);
+
+struct rst9530_ops {
+	int (*nthw_fpga_rst9530_init)(struct fpga_info_s *p_fpga_info,
+		struct nthw_fpga_rst_nt200a0x *const p);
+};
+
+void register_rst9530_ops(struct rst9530_ops *ops);
+struct rst9530_ops *get_rst9530_ops(void);
+
+struct rst9544_ops {
+	int (*nthw_fpga_rst9544_init)(struct fpga_info_s *p_fpga_info,
+		struct nthw_fpga_rst_nt200a0x *const p);
+};
+
+void register_rst9544_ops(struct rst9544_ops *ops);
+struct rst9544_ops *get_rst9544_ops(void);
+
+struct rst9563_ops {
+	int (*nthw_fpga_rst9563_init)(struct fpga_info_s *p_fpga_info,
+		struct nthw_fpga_rst_nt200a0x *const p);
+};
+
+void register_rst9563_ops(struct rst9563_ops *ops);
+struct rst9563_ops *get_rst9563_ops(void);
+
+struct rst9572_ops {
+	int (*nthw_fpga_rst9572_init)(struct fpga_info_s *p_fpga_info,
+		struct nthw_fpga_rst_nt200a0x *const p);
+};
+
+void register_rst9572_ops(struct rst9572_ops *ops);
+struct rst9572_ops *get_rst9572_ops(void);
+
+struct rst_nt400dxx_ops {
+	int (*nthw_fpga_rst_nt400dxx_init)(struct fpga_info_s *p_fpga_info);
+	int (*nthw_fpga_rst_nt400dxx_reset)(struct fpga_info_s *p_fpga_info);
+};
+
+void register_rst_nt400dxx_ops(struct rst_nt400dxx_ops *ops);
+struct rst_nt400dxx_ops *get_rst_nt400dxx_ops(void);
+
+/*
+ *
+ */
+struct profile_inline_ops {
+	/*
+	 * NT Flow FLM Meter API
+	 */
+	int (*flow_mtr_supported)(struct flow_eth_dev *dev);
+
+	uint64_t (*flow_mtr_meter_policy_n_max)(void);
+
+	int (*flow_mtr_set_profile)(struct flow_eth_dev *dev, uint32_t profile_id,
+		uint64_t bucket_rate_a, uint64_t bucket_size_a,
+		uint64_t bucket_rate_b, uint64_t bucket_size_b);
+
+	int (*flow_mtr_set_policy)(struct flow_eth_dev *dev, uint32_t policy_id, int drop);
+
+	int (*flow_mtr_create_meter)(struct flow_eth_dev *dev, uint8_t caller_id, uint32_t mtr_id,
+		uint32_t profile_id, uint32_t policy_id, uint64_t stats_mask);
+
+	int (*flow_mtr_probe_meter)(struct flow_eth_dev *dev, uint8_t caller_id, uint32_t mtr_id);
+
+	int (*flow_mtr_destroy_meter)(struct flow_eth_dev *dev, uint8_t caller_id,
+		uint32_t mtr_id);
+
+	int (*flm_mtr_adjust_stats)(struct flow_eth_dev *dev, uint8_t caller_id, uint32_t mtr_id,
+		uint32_t adjust_value);
+
+	uint32_t (*flow_mtr_meters_supported)(struct flow_eth_dev *dev, uint8_t caller_id);
+
+	void (*flm_setup_queues)(void);
+	void (*flm_free_queues)(void);
+	uint32_t (*flm_lrn_update)(struct flow_eth_dev *dev, uint32_t *inf_cnt);
+
+	uint32_t (*flm_mtr_update_stats)(struct flow_eth_dev *dev, uint32_t *inf_cnt);
+	void (*flm_mtr_read_stats)(struct flow_eth_dev *dev,
+		uint8_t caller_id,
+		uint32_t id,
+		uint64_t *stats_mask,
+		uint64_t *green_pkt,
+		uint64_t *green_bytes,
+		int clear);
+
+	uint32_t (*flm_update)(struct flow_eth_dev *dev);
+
+	/*
+	 * Config API
+	 */
+	int (*flow_set_mtu_inline)(struct flow_eth_dev *dev, uint32_t port, uint16_t mtu);
+};
+
+void register_profile_inline_ops(const struct profile_inline_ops *ops);
+const struct profile_inline_ops *get_profile_inline_ops(void);
+
+/*
+ *
+ */
+struct flow_filter_ops {
+	int (*flow_filter_init)(nthw_fpga_t *p_fpga, struct flow_nic_dev **p_flow_device,
+		int adapter_no);
+	int (*flow_filter_done)(struct flow_nic_dev *dev);
+
+	/*
+	 * Device Management API
+	 */
+	int (*flow_reset_nic_dev)(uint8_t adapter_no);
+
+	struct flow_eth_dev *(*flow_get_eth_dev)(uint8_t adapter_no,
+		uint8_t hw_port_no,
+		uint32_t port_id,
+		int alloc_rx_queues,
+		struct flow_queue_id_s queue_ids[],
+		int *rss_target_id,
+		enum flow_eth_dev_profile flow_profile,
+		uint32_t exception_path);
+
+	int (*flow_eth_dev_add_queue)(struct flow_eth_dev *eth_dev,
+		struct flow_queue_id_s *queue_id);
+
+	int (*flow_delete_eth_dev)(struct flow_eth_dev *eth_dev);
+
+	int (*flow_get_tunnel_definition)(struct tunnel_cfg_s *tun, uint32_t flow_stat_id,
+		uint8_t vport);
+
+	/*
+	 * NT Flow API
+	 */
+	int (*flow_validate)(struct flow_eth_dev *dev,
+		const struct flow_elem item[],
+		const struct flow_action action[],
+		struct flow_error *error);
+
+	struct flow_handle *(*flow_create)(struct flow_eth_dev *dev,
+		const struct flow_attr *attr,
+		const struct flow_elem item[],
+		const struct flow_action action[],
+		struct flow_error *error);
+
+	int (*flow_destroy)(struct flow_eth_dev *dev,
+		struct flow_handle *flow,
+		struct flow_error *error);
+
+	int (*flow_flush)(struct flow_eth_dev *dev, uint16_t caller_id, struct flow_error *error);
+
+	int (*flow_actions_update)(struct flow_eth_dev *dev,
+		struct flow_handle *flow,
+		const struct flow_action action[],
+		struct flow_error *error);
+
+	int (*flow_query)(struct flow_eth_dev *dev,
+		struct flow_handle *flow,
+		const struct flow_action *action,
+		void **data,
+		uint32_t *length,
+		struct flow_error *error);
+
+	int (*flow_dev_dump)(struct flow_eth_dev *dev,
+		struct flow_handle *flow,
+		uint16_t caller_id,
+		FILE *file,
+		struct flow_error *error);
+
+	/*
+	 * NT Flow asynchronous operations API
+	 */
+	int (*flow_info_get)(struct flow_eth_dev *dev, struct flow_port_info *port_info,
+		struct flow_queue_info *queue_info, struct flow_error *error);
+
+	int (*flow_configure)(struct flow_eth_dev *dev, uint8_t caller_id,
+		const struct flow_port_attr *port_attr, uint16_t nb_queue,
+		const struct flow_queue_attr *queue_attr[],
+		struct flow_error *error);
+
+	struct flow_pattern_template *(*flow_pattern_template_create)(struct flow_eth_dev *dev,
+		const struct flow_pattern_template_attr *template_attr,
+		const struct flow_elem pattern[], struct flow_error *error);
+
+	int (*flow_pattern_template_destroy)(struct flow_eth_dev *dev,
+		struct flow_pattern_template *pattern_template,
+		struct flow_error *error);
+
+	struct flow_actions_template *(*flow_actions_template_create)(struct flow_eth_dev *dev,
+		const struct flow_actions_template_attr *template_attr,
+		const struct flow_action actions[], const struct flow_action masks[],
+		struct flow_error *error);
+
+	int (*flow_actions_template_destroy)(struct flow_eth_dev *dev,
+		struct flow_actions_template *actions_template,
+		struct flow_error *error);
+
+	struct flow_template_table *(*flow_template_table_create)(struct flow_eth_dev *dev,
+		const struct flow_template_table_attr *table_attr,
+		struct flow_pattern_template *pattern_templates[], uint8_t nb_pattern_templates,
+		struct flow_actions_template *actions_templates[], uint8_t nb_actions_templates,
+		struct flow_error *error);
+
+	int (*flow_template_table_destroy)(struct flow_eth_dev *dev,
+		struct flow_template_table *template_table,
+		struct flow_error *error);
+
+	struct flow_handle *(*flow_async_create)(struct flow_eth_dev *dev, uint32_t queue_id,
+		const struct flow_op_attr *op_attr,
+		struct flow_template_table *template_table, const struct flow_elem pattern[],
+		uint8_t pattern_template_index, const struct flow_action actions[],
+		uint8_t actions_template_index, void *user_data, struct flow_error *error);
+
+	int (*flow_async_destroy)(struct flow_eth_dev *dev, uint32_t queue_id,
+		const struct flow_op_attr *op_attr, struct flow_handle *flow,
+		void *user_data, struct flow_error *error);
+
+	int (*flow_push)(struct flow_eth_dev *dev, uint32_t queue_id, struct flow_error *error);
+
+	int (*flow_pull)(struct flow_eth_dev *dev, uint32_t queue_id, struct flow_op_result res[],
+		uint16_t n_res, struct flow_error *error);
+
+	/*
+	 * Other
+	 */
+	struct flow_eth_dev *(*nic_and_port_to_eth_dev)(uint8_t adapter_no, uint8_t port);
+	struct flow_nic_dev *(*get_nic_dev_from_adapter_no)(uint8_t adapter_no);
+
+	int (*flow_nic_set_hasher)(struct flow_nic_dev *ndev, int hsh_idx,
+		enum flow_nic_hash_e algorithm);
+
+	int (*flow_get_num_queues)(uint8_t adapter_no, uint8_t port_no);
+	int (*flow_get_hw_id)(uint8_t adapter_no, uint8_t port_no, uint8_t queue_no);
+
+	int (*flow_get_flm_stats)(struct flow_nic_dev *ndev, uint64_t *data, uint64_t size);
+
+	int (*hw_mod_hsh_rcp_flush)(struct flow_api_backend_s *be, int start_idx, int count);
+};
+
+void register_flow_filter_ops(const struct flow_filter_ops *ops);
+const struct flow_filter_ops *get_flow_filter_ops(void);
+
+/*
+ *
+ */
+#ifdef RTE_FLOW_DRIVER_H_
+void register_dev_flow_ops(const struct rte_flow_ops *ops);
+const struct rte_flow_ops *get_dev_flow_ops(void);
+#endif
+
+#endif	/* __NTNIC_MOD_REG_H__ */
-- 
2.44.0


^ permalink raw reply	[flat|nested] 238+ messages in thread

* [PATCH v1 08/17] net/ntnic: add interfaces for flow API engine
  2024-05-30 14:48 [PATCH v1 01/17] net/ntnic: Add registers for NapaTech SmartNiC Serhii Iliushyk
                   ` (5 preceding siblings ...)
  2024-05-30 14:49 ` [PATCH v1 07/17] net/ntnic: add API " Serhii Iliushyk
@ 2024-05-30 14:49 ` Serhii Iliushyk
  2024-05-30 14:49 ` [PATCH v1 09/17] net/ntnic: add VFIO module Serhii Iliushyk
                   ` (17 subsequent siblings)
  24 siblings, 0 replies; 238+ messages in thread
From: Serhii Iliushyk @ 2024-05-30 14:49 UTC (permalink / raw)
  To: dev; +Cc: mko-plv, ckm, andrew.rybchenko, ferruh.yigit

Add ntnic basic flow filter functionality.

Signed-off-by: Serhii Iliushyk <sil-plv@napatech.com>
---
 drivers/net/ntnic/include/flow_api.h          |  89 ++
 drivers/net/ntnic/include/flow_api_actions.h  |  13 +
 drivers/net/ntnic/include/flow_api_engine.h   |  46 +
 drivers/net/ntnic/include/flow_filter.h       |  15 +
 drivers/net/ntnic/include/hw_mod_backend.h    |  70 ++
 drivers/net/ntnic/include/nt4ga_filter.h      |  16 +
 .../ntnic/include/stream_binary_flow_api.h    | 946 ++++++++++++++++++
 7 files changed, 1195 insertions(+)
 create mode 100644 drivers/net/ntnic/include/flow_api.h
 create mode 100644 drivers/net/ntnic/include/flow_api_actions.h
 create mode 100644 drivers/net/ntnic/include/flow_api_engine.h
 create mode 100644 drivers/net/ntnic/include/flow_filter.h
 create mode 100644 drivers/net/ntnic/include/hw_mod_backend.h
 create mode 100644 drivers/net/ntnic/include/nt4ga_filter.h
 create mode 100644 drivers/net/ntnic/include/stream_binary_flow_api.h

diff --git a/drivers/net/ntnic/include/flow_api.h b/drivers/net/ntnic/include/flow_api.h
new file mode 100644
index 0000000000..4ccdbcde14
--- /dev/null
+++ b/drivers/net/ntnic/include/flow_api.h
@@ -0,0 +1,89 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef _FLOW_API_H_
+#define _FLOW_API_H_
+
+#include <pthread.h>
+#include <stdint.h>
+#include <assert.h>
+
+#include "ntlog.h"
+
+#include "flow_api_actions.h"
+#include "flow_api_engine.h"
+#include "hw_mod_backend.h"
+#include "stream_binary_flow_api.h"
+
+/*
+ * Flow NIC and Eth port device management
+ */
+
+struct hw_mod_resource_s {
+	uint8_t *alloc_bm;	/* allocation bitmap */
+	uint32_t *ref;	/* reference counter for each resource element */
+	uint32_t resource_count;/* number of total available entries */
+};
+
+struct flow_eth_dev {
+	struct flow_nic_dev *ndev;	/* NIC that owns this port device */
+	uint8_t port;	/* NIC port id */
+	uint32_t port_id;	/* App assigned port_id - may be DPDK port_id */
+
+	struct flow_queue_id_s rx_queue[FLOW_MAX_QUEUES + 1];	/* 0th for exception */
+	int num_queues;	/* VSWITCH has exceptions sent on queue 0 per design */
+
+	int rss_target_id;	/* QSL_HSH index if RSS needed QSL v6+ */
+	struct flow_eth_dev *next;
+};
+
+enum flow_nic_hash_e {
+	HASH_ALGO_ROUND_ROBIN = 0,
+	HASH_ALGO_5TUPLE,
+};
+
+/* registered NIC backends */
+struct flow_nic_dev {
+	uint8_t adapter_no;	/* physical adapter no in the host system */
+	uint16_t ports;	/* number of in-ports addressable on this NIC */
+	enum flow_eth_dev_profile
+	flow_profile;	/* flow profile this NIC is initially prepared for */
+	int flow_mgnt_prepared;
+
+	struct hw_mod_resource_s res[RES_COUNT];/* raw NIC resource allocation table */
+	void *km_res_handle;
+	void *kcc_res_handle;
+
+	void *flm_mtr_handle;
+	void *group_handle;
+	void *hw_db_handle;
+	void *id_table_handle;
+
+	/* statistics */
+	uint32_t flow_stat_id_map[MAX_COLOR_FLOW_STATS];
+
+	uint32_t flow_unique_id_counter;
+	/* linked list of all flows created on this NIC */
+	struct flow_handle *flow_base;
+	/* linked list of all FLM flows created on this NIC */
+	struct flow_handle *flow_base_flm;
+	pthread_mutex_t flow_mtx;
+
+	/* NIC backend API */
+	struct flow_api_backend_s be;
+	/* linked list of created eth-port devices on this NIC */
+	struct flow_eth_dev *eth_base;
+	pthread_mutex_t mtx;
+
+	/* pre allocated default QSL Drop */
+	int default_qsl_drop_index;
+	/* pre allocated default QSL Discard */
+	int default_qsl_discard_index;
+
+	/* next NIC linked list */
+	struct flow_nic_dev *next;
+};
+
+#endif
diff --git a/drivers/net/ntnic/include/flow_api_actions.h b/drivers/net/ntnic/include/flow_api_actions.h
new file mode 100644
index 0000000000..f62cda5dc5
--- /dev/null
+++ b/drivers/net/ntnic/include/flow_api_actions.h
@@ -0,0 +1,13 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef _FLOW_ACTIONS_H_
+#define _FLOW_ACTIONS_H_
+
+#include <stdint.h>
+
+#define MAX_COLOR_FLOW_STATS 0x400
+
+#endif	/* _FLOW_ACTIONS_H_ */
diff --git a/drivers/net/ntnic/include/flow_api_engine.h b/drivers/net/ntnic/include/flow_api_engine.h
new file mode 100644
index 0000000000..2fb43beac0
--- /dev/null
+++ b/drivers/net/ntnic/include/flow_api_engine.h
@@ -0,0 +1,46 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef _FLOW_API_ENGINE_H_
+#define _FLOW_API_ENGINE_H_
+
+#include <stdatomic.h>
+#include <stdint.h>
+
+#include "hw_mod_backend.h"
+#include "stream_binary_flow_api.h"
+
+/*
+ * Resource management
+ * These are free resources in FPGA
+ * Other FPGA memory lists are linked to one of these
+ * and will implicitly follow them
+ */
+enum res_type_e {
+	RES_QUEUE,
+	RES_CAT_CFN,
+	RES_CAT_COT,
+	RES_CAT_EXO,
+	RES_CAT_LEN,
+	RES_KM_FLOW_TYPE,
+	RES_KM_CATEGORY,
+	RES_HSH_RCP,
+	RES_PDB_RCP,
+	RES_QSL_RCP,
+	RES_QSL_QST,
+	RES_SLC_RCP,
+	RES_SLC_LR_RCP,
+	RES_IOA_RCP,
+	RES_ROA_RCP,
+	RES_FLM_FLOW_TYPE,
+	RES_FLM_RCP,
+	RES_TPE_RCP,
+	RES_TPE_EXT,
+	RES_TPE_RPL,
+	RES_COUNT,
+	RES_INVALID
+};
+
+#endif	/* _FLOW_API_ENGINE_H_ */
diff --git a/drivers/net/ntnic/include/flow_filter.h b/drivers/net/ntnic/include/flow_filter.h
new file mode 100644
index 0000000000..53f77a9b60
--- /dev/null
+++ b/drivers/net/ntnic/include/flow_filter.h
@@ -0,0 +1,15 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef __FLOW_FILTER_HPP__
+#define __FLOW_FILTER_HPP__
+
+#include "flow_api.h"
+#include "nthw_fpga_model.h"
+
+int flow_filter_init(nthw_fpga_t *p_fpga, struct flow_nic_dev **p_flow_device, int adapter_no);
+int flow_filter_done(struct flow_nic_dev *dev);
+
+#endif	/* __FLOW_FILTER_HPP__ */
diff --git a/drivers/net/ntnic/include/hw_mod_backend.h b/drivers/net/ntnic/include/hw_mod_backend.h
new file mode 100644
index 0000000000..ab3ce1f469
--- /dev/null
+++ b/drivers/net/ntnic/include/hw_mod_backend.h
@@ -0,0 +1,70 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef _HW_MOD_BACKEND_H_
+#define _HW_MOD_BACKEND_H_
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <string.h>
+
+#include "ntlog.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define COMMON_FUNC_INFO_S                                                                        \
+	int ver;                                                                                  \
+	void *base;                                                                               \
+	unsigned int alloced_size;                                                                \
+	int debug
+
+struct common_func_s {
+	COMMON_FUNC_INFO_S;
+};
+
+struct flm_func_s {
+	COMMON_FUNC_INFO_S;
+	uint32_t nb_categories;
+	uint32_t nb_size_mb;
+	uint32_t nb_entry_size;
+	uint32_t nb_variant;
+	uint32_t nb_prios;
+	uint32_t nb_pst_profiles;
+	uint32_t nb_scrub_profiles;
+	uint32_t nb_rpp_clock_in_ps;
+	uint32_t nb_load_aps_max;
+};
+
+struct tpe_func_s {
+	COMMON_FUNC_INFO_S;
+	uint32_t nb_rcp_categories;
+	uint32_t nb_ifr_categories;
+	uint32_t nb_cpy_writers;
+	uint32_t nb_rpl_depth;
+	uint32_t nb_rpl_ext_categories;
+};
+
+struct flow_api_backend_s {
+	void *be_dev;
+	/* flow filter FPGA modules */
+	struct flm_func_s flm;
+	struct tpe_func_s tpe;
+
+	/* NIC attributes */
+	unsigned int num_phy_ports;
+	unsigned int num_rx_ports;
+
+	/* flow filter resource capacities */
+	unsigned int max_categories;
+	unsigned int max_queues;
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* _HW_MOD_BACKEND_H_ */
diff --git a/drivers/net/ntnic/include/nt4ga_filter.h b/drivers/net/ntnic/include/nt4ga_filter.h
new file mode 100644
index 0000000000..8d1abbd2ee
--- /dev/null
+++ b/drivers/net/ntnic/include/nt4ga_filter.h
@@ -0,0 +1,16 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef NT4GA_FILTER_H_
+#define NT4GA_FILTER_H_
+
+typedef struct nt4ga_filter_s {
+	int n_intf_cnt;
+	int n_queues_per_intf_cnt;
+
+	struct flow_nic_dev *mp_flow_device;
+} nt4ga_filter_t;
+
+#endif	/* NT4GA_FILTER_H_ */
diff --git a/drivers/net/ntnic/include/stream_binary_flow_api.h b/drivers/net/ntnic/include/stream_binary_flow_api.h
new file mode 100644
index 0000000000..096a349cc0
--- /dev/null
+++ b/drivers/net/ntnic/include/stream_binary_flow_api.h
@@ -0,0 +1,946 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef _STREAM_BINARY_FLOW_API_H_
+#define _STREAM_BINARY_FLOW_API_H_
+
+#include <stdint.h>	/* uint16_t, uint32_t, uint64_t */
+#include <stdio.h>	/* snprintf */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef uint16_t be16_t;/* 16-bit big-endian */
+typedef uint32_t be32_t;/* 32-bit big-endian */
+typedef uint64_t be64_t;/* 64-bit big-endian */
+
+/* Max length for socket name, interface name, etc. */
+#define MAX_PATH_LEN 128
+
+/* Max RSS hash key length in bytes */
+#define MAX_RSS_KEY_LEN 40
+
+/** NT specific MASKs for RSS configuration **/
+#define NT_ETH_RSS_IPV4_MASK                                                                      \
+	(RTE_ETH_RSS_IPV4 | RTE_ETH_RSS_FRAG_IPV4 | RTE_ETH_RSS_NONFRAG_IPV4_OTHER |              \
+	 RTE_ETH_RSS_NONFRAG_IPV4_SCTP | RTE_ETH_RSS_NONFRAG_IPV4_TCP |                           \
+	 RTE_ETH_RSS_NONFRAG_IPV4_UDP)
+
+#define NT_ETH_RSS_IPV6_MASK                                                                      \
+	(RTE_ETH_RSS_IPV6 | RTE_ETH_RSS_FRAG_IPV6 | RTE_ETH_RSS_IPV6_EX |                         \
+	 RTE_ETH_RSS_IPV6_TCP_EX | RTE_ETH_RSS_IPV6_UDP_EX | RTE_ETH_RSS_NONFRAG_IPV6_OTHER |     \
+	 RTE_ETH_RSS_NONFRAG_IPV6_SCTP | RTE_ETH_RSS_NONFRAG_IPV6_TCP |                           \
+	 RTE_ETH_RSS_NONFRAG_IPV6_UDP)
+
+#define NT_ETH_RSS_IP_MASK                                                                        \
+	(NT_ETH_RSS_IPV4_MASK | NT_ETH_RSS_IPV6_MASK | RTE_ETH_RSS_L3_SRC_ONLY |                  \
+	 RTE_ETH_RSS_L3_DST_ONLY)
+
+/* List of all RSS flags supported for RSS calculation offload */
+#define NT_ETH_RSS_OFFLOAD_MASK                                                                   \
+	(RTE_ETH_RSS_ETH | RTE_ETH_RSS_L2_PAYLOAD | RTE_ETH_RSS_IP | RTE_ETH_RSS_TCP |            \
+	 RTE_ETH_RSS_UDP | RTE_ETH_RSS_SCTP | RTE_ETH_RSS_L2_SRC_ONLY | RTE_ETH_RSS_L2_DST_ONLY | \
+	 RTE_ETH_RSS_L4_SRC_ONLY | RTE_ETH_RSS_L4_DST_ONLY | RTE_ETH_RSS_L3_SRC_ONLY |            \
+	 RTE_ETH_RSS_L3_DST_ONLY | RTE_ETH_RSS_VLAN | RTE_ETH_RSS_LEVEL_MASK |                    \
+	 RTE_ETH_RSS_IPV4_CHKSUM | RTE_ETH_RSS_L4_CHKSUM | RTE_ETH_RSS_PORT | RTE_ETH_RSS_GTPU)
+
+/*
+ * Flow frontend for binary programming interface
+ */
+
+#define FLOW_MAX_QUEUES 128
+
+#define RAW_ENCAP_DECAP_ELEMS_MAX 16
+
+/*
+ * Partial flow mark and special flow marks
+ */
+#define FLOW_MARK_LACP 0x7fffffff
+#define FLOW_MARK_MAX 0x7ffffffe
+/*
+ * Flow eth dev profile determines how the FPGA module resources are
+ * managed and what features are available
+ */
+enum flow_eth_dev_profile {
+	FLOW_ETH_DEV_PROFILE_VSWITCH = 0,
+	FLOW_ETH_DEV_PROFILE_INLINE = 1,
+};
+
+/*
+ * Flow rule attributes
+ */
+struct flow_attr {
+	uint32_t group;	/* Priority group. */
+	uint32_t priority;	/* Rule priority level within group. */
+	uint16_t forced_vlan_vid;	/* Forced VLAN VID that filter must match. Ignored if 0. */
+	uint16_t caller_id;	/* Unique ID of caller application. */
+};
+
+struct flow_queue_id_s {
+	int id;
+	int hw_id;
+};
+
+/* NT Private rte flow items. */
+
+/* NT Private rte flow actions. */
+
+enum flow_elem_type {
+	FLOW_ELEM_TYPE_END,
+	FLOW_ELEM_TYPE_ANY,
+	FLOW_ELEM_TYPE_ETH,
+	FLOW_ELEM_TYPE_VLAN,
+	FLOW_ELEM_TYPE_IPV4,
+	FLOW_ELEM_TYPE_IPV6,
+	FLOW_ELEM_TYPE_SCTP,
+	FLOW_ELEM_TYPE_TCP,
+	FLOW_ELEM_TYPE_UDP,
+	FLOW_ELEM_TYPE_ICMP,
+	FLOW_ELEM_TYPE_ICMP6,
+	FLOW_ELEM_TYPE_VXLAN,
+	FLOW_ELEM_TYPE_GTP,
+	FLOW_ELEM_TYPE_GTP_PSC,
+	FLOW_ELEM_TYPE_PORT_ID,
+	FLOW_ELEM_TYPE_TAG,
+	FLOW_ELEM_TYPE_VOID,
+
+	/*
+	 * not associated with a RTE_ITEM..., but rather
+	 * an restoration API device specific extension
+	 */
+	FLOW_ELEM_TYPE_TUNNEL
+};
+
+enum flow_action_type {	/* conf structure */
+	FLOW_ACTION_TYPE_END,	/* -none- : End tag for action list */
+	FLOW_ACTION_TYPE_POP_VLAN,	/* -none- : Pops outer vlan tag */
+	FLOW_ACTION_TYPE_PUSH_VLAN,	/* struct flow_action_push_vlan : Push VLAN TAG */
+	FLOW_ACTION_TYPE_SET_VLAN_VID,	/* struct flow_action_set_vlan_vid : Set VLAN VID */
+	FLOW_ACTION_TYPE_SET_VLAN_PCP,	/* struct flow_action_set_vlan_pcp : Set VLAN PCP */
+	/* -none- : Decapsulate outer most VXLAN tunnel from matched flow */
+	FLOW_ACTION_TYPE_VXLAN_DECAP,
+	FLOW_ACTION_TYPE_VXLAN_ENCAP,	/* struct flow_action_vxlan_encap */
+	FLOW_ACTION_TYPE_DROP,	/* -none- : Drop packets of this flow */
+	FLOW_ACTION_TYPE_COUNT,	/* struct flow_action_count : Used for "query" flow function */
+	/* struct flow_action_mark : Used to tag a flow in HW with a MARK */
+	FLOW_ACTION_TYPE_MARK,
+	/* struct flow_action_tag : Used to tag a flow in HW with a TAG */
+	FLOW_ACTION_TYPE_SET_TAG,
+	/* struct flow_action_port_id : Destination port ID - HW port ID */
+	FLOW_ACTION_TYPE_PORT_ID,
+	FLOW_ACTION_TYPE_RSS,	/* struct flow_action_rss : */
+	FLOW_ACTION_TYPE_QUEUE,	/* struct flow_action_queue : */
+	FLOW_ACTION_TYPE_JUMP,	/* struct flow_action_jump : */
+	/* struct flow_action_meter : Used to set MBR record ids in FLM learn records */
+	FLOW_ACTION_TYPE_METER,
+	FLOW_ACTION_TYPE_RAW_ENCAP,	/* struct flow_action_raw_encap : */
+	FLOW_ACTION_TYPE_RAW_DECAP,	/* struct flow_action_raw_decap : */
+	FLOW_ACTION_TYPE_MODIFY_FIELD,	/* struct flow_action_modify_field : */
+
+	/*
+	 * -none- : not associated with a RTE_ACTION...,
+	 * but rather an restoration API device specific extension
+	 */
+	FLOW_ACTION_TYPE_TUNNEL_SET
+};
+
+#pragma pack(1)
+struct ether_addr_s {
+	uint8_t addr_b[6];
+};
+#pragma pack()
+
+static inline void flow_ether_format_addr(char *buf, uint16_t size,
+	const struct ether_addr_s *eth_addr)
+{
+	snprintf(buf, size, "%02X:%02X:%02X:%02X:%02X:%02X", eth_addr
+		->addr_b[0],
+		eth_addr
+		->addr_b[1], eth_addr
+		->addr_b[2], eth_addr
+		->addr_b[3],
+		eth_addr
+		->addr_b[4], eth_addr
+		->addr_b[5]);
+}
+
+/*
+ * IPv4 Header
+ */
+#pragma pack(1)
+struct ipv4_hdr_s {
+	uint8_t version_ihl;
+	uint8_t tos;
+	be16_t length;
+	be16_t id;
+	be16_t frag_offset;
+	uint8_t ttl;
+	uint8_t next_proto_id;
+	be16_t hdr_csum;
+	be32_t src_ip;
+	be32_t dst_ip;
+};
+#pragma pack()
+/*
+ * IPv6 Header
+ */
+#pragma pack(1)
+struct ipv6_hdr_s {
+	be32_t vtc_flow;/* IP version, traffic class & flow label */
+	be16_t payload_len;	/* IP packet length - includes ip header */
+	uint8_t proto;
+	uint8_t hop_limits;
+	uint8_t src_addr[16];
+	uint8_t dst_addr[16];
+};
+#pragma pack()
+
+/*
+ * SCTP Header
+ */
+#pragma pack(1)
+struct sctp_hdr_s {
+	be16_t src_port;
+	be16_t dst_port;
+	be32_t tag;	/* Validation tag */
+	be32_t cksum;
+};
+#pragma pack()
+
+/*
+ * TCP Header
+ */
+#pragma pack(1)
+struct tcp_hdr_s {
+	be16_t src_port;
+	be16_t dst_port;
+	be32_t sent_seq;
+	be32_t recv_ack;
+	uint8_t data_off;
+	uint8_t tcp_flags;
+	be16_t rx_win;
+	be16_t cksum;
+	be16_t tcp_urp;
+};
+#pragma pack()
+
+/*
+ * UDP Header
+ */
+#pragma pack(1)
+struct udp_hdr_s {
+	be16_t src_port;
+	be16_t dst_port;
+	be16_t len;
+	be16_t cksum;
+};
+#pragma pack()
+
+/*
+ * ICMP Header
+ */
+#pragma pack(1)
+struct icmp_hdr_s {
+	uint8_t type;
+	uint8_t code;
+	be16_t cksum;
+	be16_t ident;
+	be16_t seq_nb;
+};
+#pragma pack()
+/*
+ * FLOW_ELEM_TYPE_ETH specification
+ */
+#pragma pack(1)
+struct flow_elem_eth {
+	struct ether_addr_s d_addr;	/* DMAC */
+	struct ether_addr_s s_addr;	/* SMAC */
+	be16_t ether_type;	/* Frame type */
+};
+#pragma pack()
+
+/*
+ * FLOW_ELEM_TYPE_VLAN specification
+ */
+#pragma pack(1)
+struct flow_elem_vlan {
+	be16_t tci;	/* Tag control information */
+	be16_t inner_type;	/* Inner EtherType or TPID */
+};
+#pragma pack()
+
+/*
+ * FLOW_ELEM_TYPE_IPV4 specification
+ */
+struct flow_elem_ipv4 {
+	struct ipv4_hdr_s hdr;
+};
+
+/*
+ * FLOW_ELEM_TYPE_IPV6 specification
+ */
+struct flow_elem_ipv6 {
+	struct ipv6_hdr_s hdr;
+};
+
+/*
+ * FLOW_ELEM_TYPE_SCTP specification
+ */
+struct flow_elem_sctp {
+	struct sctp_hdr_s hdr;
+};
+
+/*
+ * FLOW_ELEM_TYPE_TCP specification
+ */
+struct flow_elem_tcp {
+	struct tcp_hdr_s hdr;
+};
+
+/*
+ * FLOW_ELEM_TYPE_UDP specification
+ */
+struct flow_elem_udp {
+	struct udp_hdr_s hdr;
+};
+
+/*
+ * FLOW_ELEM_TYPE_ICMP specification
+ */
+struct flow_elem_icmp {
+	struct icmp_hdr_s hdr;
+};
+
+/*
+ * FLOW_ELEM_TYPE_ICMP6 specification
+ */
+#pragma pack(1)
+struct flow_elem_icmp6 {
+	uint8_t type;	/**< ICMPv6 type. */
+	uint8_t code;	/**< ICMPv6 code. */
+	be16_t checksum;/**< ICMPv6 checksum. */
+};
+#pragma pack()
+
+/*
+ * FLOW_ELEM_TYPE_GTP specification
+ */
+#pragma pack(1)
+struct flow_elem_gtp {
+	uint8_t v_pt_rsv_flags;
+	uint8_t msg_type;
+	be16_t msg_len;
+	be32_t teid;
+};
+#pragma pack()
+
+/*
+ * FLOW_ELEM_TYPE_GTP_PSC specification
+ */
+#pragma pack(1)
+struct flow_elem_gtp_psc {
+	uint8_t hdr_len;
+	uint8_t pdu_type;
+	uint8_t qfi;
+};
+#pragma pack()
+
+/*
+ * FLOW_ELEM_TYPE_VXLAN specification (RFC 7348)
+ */
+#pragma pack(1)
+struct flow_elem_vxlan {
+	uint8_t flags;	/* Normally 0x08 (I flag) */
+	uint8_t rsvd0[3];
+	uint8_t vni[3];
+	uint8_t rsvd1;
+};
+#pragma pack()
+/*
+ * FLOW_ELEM_TYPE_PORT_ID specification
+ */
+struct flow_elem_port_id {
+	uint32_t id;	/* HW port no */
+};
+
+/*
+ * FLOW_ELEM_TYPE_TAG specification
+ */
+struct flow_elem_tag {
+	uint32_t data;
+	uint8_t index;
+};
+
+/*
+ * FLOW_ELEM_TYPE_ANY specification
+ */
+struct flow_elem_any {
+	uint32_t num;	/* *< Number of layers covered. */
+};
+
+struct flow_elem {
+	enum flow_elem_type type;	/* element type */
+	const void *spec;	/* Pointer to element specification structure */
+	const void *mask;	/* Bitmask applied to spec - same type */
+};
+
+/* Note: Keep in sync with the rte_eth_hash_function structure defined in rte_ethdev.h */
+enum nt_eth_hash_function {
+	NT_ETH_HASH_FUNCTION_DEFAULT = 0,
+	NT_ETH_HASH_FUNCTION_TOEPLITZ,
+	NT_ETH_HASH_FUNCTION_SIMPLE_XOR,
+	NT_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ,
+	NT_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ_SORT,
+	NT_ETH_HASH_FUNCTION_MAX,
+};
+
+struct flow_action_rss {
+	enum nt_eth_hash_function func;
+	/*
+	 * UNUSED; rte_flow_action_rss->level is used to set
+	 * RTE_ETH_RSS_LEVEL_OUTERMOST & RTE_ETH_RSS_LEVEL_INNERMOST
+	 * bits at 'flow_action_rss->types' below
+	 */
+	uint32_t level;
+	uint64_t types;	/* Specific RSS hash types (see like RTE_ETH_RSS_*) */
+	uint32_t key_len;	/* Hash key length in bytes supported for Toeplitz */
+	uint32_t queue_num;	/* Number of entries in queue */
+	const uint8_t *key;	/* Hash key supported for Toeplitz */
+	const uint16_t *queue;	/* Queue indices to use */
+};
+
+/*
+ * FLOW_ACTION_TYPE_PUSH_VLAN
+ * Push a new vlan TAG
+ */
+struct flow_action_push_vlan {
+	be16_t ethertype;
+};
+
+/*
+ * FLOW_ACTION_TYPE_SET_VLAN_VID
+ */
+struct flow_action_set_vlan_vid {
+	be16_t vlan_vid;
+};
+
+/*
+ * FLOW_ACTION_TYPE_SET_VLAN_PCP
+ */
+struct flow_action_set_vlan_pcp {
+	uint8_t vlan_pcp;	/* *< VLAN priority. */
+};
+
+/*
+ * FLOW_ACTION_TYPE_VXLAN_ENCAP specification
+ * Valid flow definition:
+ *
+ * - ETH / IPV4 / UDP / VXLAN / END
+ * - ETH / IPV6 / UDP / VXLAN / END
+ * - ETH / VLAN / IPV4 / UDP / VXLAN / END
+ */
+struct flow_action_vxlan_encap {
+	/* Encapsulating vxlan tunnel definition */
+	struct flow_elem *vxlan_tunnel;
+};
+
+/*
+ * FLOW_ACTION_TYPE_COUNT specification
+ */
+struct flow_action_count {
+	uint32_t id;	/* HW port no */
+};
+
+/*
+ * FLOW_ACTION_TYPE_COUNT specification (query)
+ */
+struct flow_query_count {
+	uint32_t reset : 1;
+	uint32_t hits_set : 1;
+	uint32_t bytes_set : 1;
+
+	uint32_t tcp_flags : 9;
+
+	uint32_t reserved : 20;
+	uint64_t hits;
+	uint64_t bytes;
+};
+
+/*
+ * FLOW_ACTION_TYPE_MARK specification
+ */
+struct flow_action_mark {
+	uint32_t id;	/* mark flow with this ID */
+};
+
+/*
+ * FLOW_ACTION_TYPE_TAG specification
+ */
+struct flow_action_tag {
+	uint32_t data;	/* tag flow with this value */
+	uint32_t mask;	/* bit-mask applied to "data" */
+	uint8_t index;	/* index of tag to set */
+};
+
+/*
+ * FLOW_ACTION_TYPE_PORT_ID specification
+ */
+struct flow_action_port_id {
+	uint32_t __rte_flags;	/* not used but to be binary compatible with rte flow */
+	uint32_t id;
+};
+
+/*
+ * FLOW_ACTION_TYPE_QUEUE
+ */
+struct flow_action_queue {
+	uint16_t index;
+};
+
+/*
+ * FLOW_ACTION_TYPE_JUMP
+ */
+struct flow_action_jump {
+	uint32_t group;
+};
+
+/*
+ * FLOW_ACTION_TYPE_METER
+ */
+struct flow_action_meter {
+	uint32_t mtr_id;
+};
+
+/*
+ * FLOW_ACTION_TYPE_RAW_ENCAP
+ */
+struct flow_action_raw_encap {
+	uint8_t *data;
+	uint8_t *preserve;
+	size_t size;
+	struct flow_elem items[RAW_ENCAP_DECAP_ELEMS_MAX];
+	int item_count;
+};
+
+/*
+ * FLOW_ACTION_TYPE_RAW_DECAP
+ */
+struct flow_action_raw_decap {
+	uint8_t *data;
+	size_t size;
+	struct flow_elem items[RAW_ENCAP_DECAP_ELEMS_MAX];
+	int item_count;
+};
+
+/*
+ * Field IDs for MODIFY_FIELD action.
+ */
+enum flow_field_id {
+	FLOW_FIELD_START = 0,	/* Start of a packet. */
+	FLOW_FIELD_MAC_DST,	/* Destination MAC Address. */
+	FLOW_FIELD_MAC_SRC,	/* Source MAC Address. */
+	FLOW_FIELD_VLAN_TYPE,	/* 802.1Q Tag Identifier. */
+	FLOW_FIELD_VLAN_ID,	/* 802.1Q VLAN Identifier. */
+	FLOW_FIELD_MAC_TYPE,	/* EtherType. */
+	FLOW_FIELD_IPV4_DSCP,	/* IPv4 DSCP. */
+	FLOW_FIELD_IPV4_TTL,	/* IPv4 Time To Live. */
+	FLOW_FIELD_IPV4_SRC,	/* IPv4 Source Address. */
+	FLOW_FIELD_IPV4_DST,	/* IPv4 Destination Address. */
+	FLOW_FIELD_IPV6_DSCP,	/* IPv6 DSCP. */
+	FLOW_FIELD_IPV6_HOPLIMIT,	/* IPv6 Hop Limit. */
+	FLOW_FIELD_IPV6_SRC,	/* IPv6 Source Address. */
+	FLOW_FIELD_IPV6_DST,	/* IPv6 Destination Address. */
+	FLOW_FIELD_TCP_PORT_SRC,/* TCP Source Port Number. */
+	FLOW_FIELD_TCP_PORT_DST,/* TCP Destination Port Number. */
+	FLOW_FIELD_TCP_SEQ_NUM,	/* TCP Sequence Number. */
+	FLOW_FIELD_TCP_ACK_NUM,	/* TCP Acknowledgment Number. */
+	FLOW_FIELD_TCP_FLAGS,	/* TCP Flags. */
+	FLOW_FIELD_UDP_PORT_SRC,/* UDP Source Port Number. */
+	FLOW_FIELD_UDP_PORT_DST,/* UDP Destination Port Number. */
+	FLOW_FIELD_VXLAN_VNI,	/* VXLAN Network Identifier. */
+	FLOW_FIELD_GENEVE_VNI,	/* GENEVE Network Identifier. */
+	FLOW_FIELD_GTP_TEID,	/* GTP Tunnel Endpoint Identifier. */
+	FLOW_FIELD_TAG,	/* Tag value. */
+	FLOW_FIELD_MARK,/* Mark value. */
+	FLOW_FIELD_META,/* Metadata value. */
+	FLOW_FIELD_POINTER,	/* Memory pointer. */
+	FLOW_FIELD_VALUE,	/* Immediate value. */
+	FLOW_FIELD_IPV4_ECN,	/* IPv4 ECN. */
+	FLOW_FIELD_IPV6_ECN,	/* IPv6 ECN. */
+	FLOW_FIELD_GTP_PSC_QFI,	/* GTP QFI. */
+	FLOW_FIELD_METER_COLOR,	/* Meter color marker. */
+};
+
+/*
+ * Field description for MODIFY_FIELD action.
+ */
+struct flow_action_modify_data {
+	enum flow_field_id field;	/* Field or memory type ID. */
+	union {
+		struct {
+			/* Encapsulation level or tag index. */
+			uint32_t level;
+			/* Number of bits to skip from a field. */
+			uint32_t offset;
+		};
+		/*
+		 * Immediate value for FLOW_FIELD_VALUE, presented in the
+		 * same byte order and length as in relevant rte_flow_item_xxx.
+		 */
+		uint8_t value[16];
+		/*
+		 * Memory address for FLOW_FIELD_POINTER, memory layout
+		 * should be the same as for relevant field in the
+		 * rte_flow_item_xxx structure.
+		 */
+		void *pvalue;
+	};
+};
+
+/*
+ * Operation types for MODIFY_FIELD action.
+ */
+enum flow_modify_op {
+	FLOW_MODIFY_SET = 0,
+	FLOW_MODIFY_ADD,
+	FLOW_MODIFY_SUB,
+};
+
+/*
+ * FLOW_ACTION_TYPE_MODIFY_FIELD
+ */
+struct flow_action_modify_field {
+	enum flow_modify_op operation;
+	struct flow_action_modify_data dst;
+	struct flow_action_modify_data src;
+	uint32_t width;
+};
+
+struct flow_action {
+	enum flow_action_type type;
+	const void *conf;
+};
+
+enum flow_error_e {
+	FLOW_ERROR_NONE,
+	FLOW_ERROR_SUCCESS,
+	FLOW_ERROR_GENERAL
+};
+
+struct flow_error {
+	enum flow_error_e type;
+	const char *message;
+};
+
+enum flow_lag_cmd {
+	FLOW_LAG_SET_ENTRY,
+	FLOW_LAG_SET_ALL,
+	FLOW_LAG_SET_BALANCE,
+};
+
+/*
+ * Tunnel definition for DPDK RTE tunnel helper function support
+ */
+struct tunnel_cfg_s {
+	union {
+		struct {
+			uint32_t src_ip;/* BE */
+			uint32_t dst_ip;/* BE */
+		} v4;
+		struct {
+			uint8_t src_ip[16];
+			uint8_t dst_ip[16];
+		} v6;
+		struct {
+			uint64_t src_ip[2];
+			uint64_t dst_ip[2];
+		} v6_long;
+	};
+	int ipversion;
+	uint16_t s_port;/* BE */
+	uint16_t d_port;/* BE */
+	int tun_type;
+};
+
+struct flow_eth_dev;	/* port device */
+struct flow_handle;
+
+struct flow_pattern_template;
+struct flow_actions_template;
+struct flow_template_table;
+
+/*
+ * Device Management API
+ */
+int flow_reset_nic_dev(uint8_t adapter_no);
+
+struct flow_eth_dev *flow_get_eth_dev(uint8_t adapter_no,
+	uint8_t hw_port_no,
+	uint32_t port_id,
+	int alloc_rx_queues,
+	struct flow_queue_id_s queue_ids[],
+	int *rss_target_id,
+	enum flow_eth_dev_profile flow_profile,
+	uint32_t exception_path);
+
+int flow_eth_dev_add_queue(struct flow_eth_dev *eth_dev, struct flow_queue_id_s *queue_id);
+
+int flow_delete_eth_dev(struct flow_eth_dev *eth_dev);
+
+int flow_get_tunnel_definition(struct tunnel_cfg_s *tun, uint32_t flow_stat_id, uint8_t vport);
+
+/*
+ * NT Flow API
+ */
+int flow_validate(struct flow_eth_dev *dev,
+	const struct flow_elem item[],
+	const struct flow_action action[],
+	struct flow_error *error);
+
+struct flow_handle *flow_create(struct flow_eth_dev *dev,
+	const struct flow_attr *attr,
+	const struct flow_elem item[],
+	const struct flow_action action[],
+	struct flow_error *error);
+
+int flow_destroy(struct flow_eth_dev *dev, struct flow_handle *flow, struct flow_error *error);
+
+int flow_flush(struct flow_eth_dev *dev, uint16_t caller_id, struct flow_error *error);
+
+int flow_actions_update(struct flow_eth_dev *dev,
+	struct flow_handle *flow,
+	const struct flow_action action[],
+	struct flow_error *error);
+
+int flow_query(struct flow_eth_dev *dev,
+	struct flow_handle *flow,
+	const struct flow_action *action,
+	void **data,
+	uint32_t *length,
+	struct flow_error *error);
+
+int flow_dev_dump(struct flow_eth_dev *dev,
+	struct flow_handle *flow,
+	uint16_t caller_id,
+	FILE *file,
+	struct flow_error *error);
+
+int flow_get_aged_flows(struct flow_eth_dev *dev,
+	void **context,
+	uint32_t nb_contexts,
+	struct flow_error *error);
+
+/*
+ * NT Flow asynchronous operations API
+ */
+struct flow_port_info {
+	/* maximum number of queues for asynchronous operations. */
+	uint32_t max_nb_queues;
+	/* maximum number of counters. see RTE_FLOW_ACTION_TYPE_COUNT */
+	uint32_t max_nb_counters;
+	/* maximum number of aging objects. see RTE_FLOW_ACTION_TYPE_AGE */
+	uint32_t max_nb_aging_objects;
+	/* maximum number traffic meters. see RTE_FLOW_ACTION_TYPE_METER */
+	uint32_t max_nb_meters;
+	/* maximum number connection trackings. see RTE_FLOW_ACTION_TYPE_CONNTRACK */
+	uint32_t max_nb_conn_tracks;
+	uint32_t supported_flags;	/* port supported flags (RTE_FLOW_PORT_FLAG_*). */
+};
+
+struct flow_queue_info {
+	uint32_t max_size;	/* maximum number of operations a queue can hold. */
+};
+
+struct flow_op_attr {
+	/* when set, the requested action will not be sent to the HW immediately. */
+	uint32_t postpone : 1;
+};
+
+struct flow_port_attr {
+	/* number of counters to configure. see RTE_FLOW_ACTION_TYPE_COUNT */
+	uint32_t nb_counters;
+	/* number of aging objects to configure. see RTE_FLOW_ACTION_TYPE_AGE */
+	uint32_t nb_aging_objects;
+	/* number of traffic meters to configure. see RTE_FLOW_ACTION_TYPE_METER */
+	uint32_t nb_meters;
+	/* number of connection trackings to configure. see RTE_FLOW_ACTION_TYPE_CONNTRACK */
+	uint32_t nb_conn_tracks;
+	uint32_t flags;	/* Port flags (RTE_FLOW_PORT_FLAG_*). */
+};
+
+struct flow_queue_attr {
+	uint32_t size;	/* number of flow rule operations a queue can hold. */
+};
+
+struct flow_pattern_template_attr {
+	/**
+	 * Relaxed matching policy.
+	 * - If 1, matching is performed only on items with the mask member set
+	 * and matching on protocol layers specified without any masks is skipped.
+	 * - If 0, matching on protocol layers specified without any masks is done
+	 * as well. This is the standard behaviour of Flow API now.
+	 */
+	uint32_t relaxed_matching : 1;
+	/* Flow direction for the pattern template. At least one direction must be specified. */
+	uint32_t ingress : 1;	/* pattern valid for rules applied to ingress traffic. */
+	uint32_t egress : 1;	/* pattern valid for rules applied to egress traffic. */
+	uint32_t transfer : 1;	/* pattern valid for rules applied to transfer traffic. */
+	uint32_t reserved : 28;
+	uint16_t caller_id;	/* Unique ID of caller application. */
+};
+
+struct flow_actions_template_attr {
+	/* Flow direction for the actions template. At least one direction must be specified. */
+	uint32_t ingress : 1;	/* action valid for rules applied to ingress traffic. */
+	uint32_t egress : 1;	/* action valid for rules applied to egress traffic. */
+	uint32_t transfer : 1;	/* action valid for rules applied to transfer traffic. */
+	uint32_t reserved : 29;
+	uint16_t caller_id;	/* Unique ID of caller application. */
+};
+
+struct async_flow_attr {
+	/* priority group. */
+	uint32_t group;
+	/* rule priority level within group. */
+	uint32_t priority;
+	/* the rule in question applies to ingress traffic (non-"transfer"). */
+	uint32_t ingress : 1;
+	/* the rule in question applies to egress traffic (non-"transfer"). */
+	uint32_t egress : 1;
+	/*
+	 * managing "transfer" flows requires that the user
+	 * communicate them through a suitable port.
+	 */
+	uint32_t transfer : 1;
+	uint32_t reserved : 29;	/* reserved, must be zero. */
+};
+
+struct flow_template_table_attr {
+	/* flow attributes to be used in each rule generated from this table. */
+	struct async_flow_attr flow_attr;
+	uint32_t nb_flows;	/* maximum number of flow rules that this table holds. */
+	uint16_t forced_vlan_vid;	/* Forced VLAN VID that filter must match. Ignored if 0. */
+	uint16_t caller_id;	/* Unique ID of caller application. */
+};
+
+enum flow_op_status {
+	FLOW_OP_SUCCESS,/* the operation was completed successfully. */
+	FLOW_OP_ERROR,	/* the operation was not completed successfully. */
+};
+
+struct flow_op_result {
+	/* returns the status of the operation that this completion signals. */
+	enum flow_op_status status;
+	void *user_data;/* the user data that will be returned on the completion events. */
+};
+
+struct flow_indir_action_conf {
+	uint32_t ingress : 1;	/* action valid for rules applied to ingress traffic. */
+	uint32_t egress : 1;	/* action valid for rules applied to egress traffic. */
+	/* action is valid for ransfer traffic; otherwise, for non-transfer traffic. */
+	uint32_t transfer : 1;
+};
+
+int flow_info_get(struct flow_eth_dev *dev, struct flow_port_info *port_info,
+	struct flow_queue_info *queue_info, struct flow_error *error);
+
+int flow_configure(struct flow_eth_dev *dev, uint8_t caller_id,
+	const struct flow_port_attr *port_attr, uint16_t nb_queue,
+	const struct flow_queue_attr *queue_attr[], struct flow_error *error);
+
+struct flow_pattern_template *
+flow_pattern_template_create(struct flow_eth_dev *dev,
+	const struct flow_pattern_template_attr *template_attr,
+	const struct flow_elem pattern[], struct flow_error *error);
+
+int flow_pattern_template_destroy(struct flow_eth_dev *dev,
+	struct flow_pattern_template *pattern_template,
+	struct flow_error *error);
+
+struct flow_actions_template *
+flow_actions_template_create(struct flow_eth_dev *dev,
+	const struct flow_actions_template_attr *template_attr,
+	const struct flow_action actions[], const struct flow_action masks[],
+	struct flow_error *error);
+
+int flow_actions_template_destroy(struct flow_eth_dev *dev,
+	struct flow_actions_template *actions_template,
+	struct flow_error *error);
+
+struct flow_template_table *flow_template_table_create(struct flow_eth_dev *dev,
+	const struct flow_template_table_attr *table_attr,
+	struct flow_pattern_template *pattern_templates[], uint8_t nb_pattern_templates,
+	struct flow_actions_template *actions_templates[], uint8_t nb_actions_templates,
+	struct flow_error *error);
+
+int flow_template_table_destroy(struct flow_eth_dev *dev,
+	struct flow_template_table *template_table,
+	struct flow_error *error);
+
+struct flow_handle *
+flow_async_create(struct flow_eth_dev *dev, uint32_t queue_id, const struct flow_op_attr *op_attr,
+	struct flow_template_table *template_table, const struct flow_elem pattern[],
+	uint8_t pattern_template_index, const struct flow_action actions[],
+	uint8_t actions_template_index, void *user_data, struct flow_error *error);
+
+int flow_async_destroy(struct flow_eth_dev *dev, uint32_t queue_id,
+	const struct flow_op_attr *op_attr, struct flow_handle *flow,
+	void *user_data, struct flow_error *error);
+
+int flow_push(struct flow_eth_dev *dev, uint32_t queue_id, struct flow_error *error);
+
+int flow_pull(struct flow_eth_dev *dev, uint32_t queue_id, struct flow_op_result res[],
+	uint16_t n_res, struct flow_error *error);
+
+/*
+ * NT Flow FLM Meter API
+ */
+int flow_mtr_supported(struct flow_eth_dev *dev);
+
+uint64_t flow_mtr_meter_policy_n_max(void);
+
+int flow_mtr_set_profile(struct flow_eth_dev *dev, uint32_t profile_id, uint64_t bucket_rate_a,
+	uint64_t bucket_size_a, uint64_t bucket_rate_b, uint64_t bucket_size_b);
+
+int flow_mtr_set_policy(struct flow_eth_dev *dev, uint32_t policy_id, int drop);
+
+int flow_mtr_create_meter(struct flow_eth_dev *dev, uint8_t caller_id, uint32_t mtr_id,
+	uint32_t profile_id, uint32_t policy_id, uint64_t stats_mask);
+
+int flow_mtr_probe_meter(struct flow_eth_dev *dev, uint8_t caller_id, uint32_t mtr_id);
+
+int flow_mtr_destroy_meter(struct flow_eth_dev *dev, uint8_t caller_id, uint32_t mtr_id);
+
+int flm_mtr_adjust_stats(struct flow_eth_dev *dev, uint8_t caller_id, uint32_t mtr_id,
+	uint32_t adjust_value);
+
+uint32_t flow_mtr_meters_supported(struct flow_eth_dev *dev, uint8_t caller_id);
+
+void flm_setup_queues(void);
+void flm_free_queues(void);
+uint32_t flm_lrn_update(struct flow_eth_dev *dev, uint32_t *inf_cnt);
+
+uint32_t flm_mtr_update_stats(struct flow_eth_dev *dev, uint32_t *inf_cnt);
+void flm_mtr_read_stats(struct flow_eth_dev *dev,
+	uint8_t caller_id,
+	uint32_t id,
+	uint64_t *stats_mask,
+	uint64_t *green_pkt,
+	uint64_t *green_bytes,
+	int clear);
+
+uint32_t flm_update(struct flow_eth_dev *dev);
+
+/*
+ * Config API
+ */
+int flow_set_mtu_inline(struct flow_eth_dev *dev, uint32_t port, uint16_t mtu);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* _STREAM_BINARY_FLOW_API_H_ */
-- 
2.44.0


^ permalink raw reply	[flat|nested] 238+ messages in thread

* [PATCH v1 09/17] net/ntnic: add VFIO module
  2024-05-30 14:48 [PATCH v1 01/17] net/ntnic: Add registers for NapaTech SmartNiC Serhii Iliushyk
                   ` (6 preceding siblings ...)
  2024-05-30 14:49 ` [PATCH v1 08/17] net/ntnic: add interfaces for flow API engine Serhii Iliushyk
@ 2024-05-30 14:49 ` Serhii Iliushyk
  2024-05-30 14:49 ` [PATCH v1 10/17] net/ntnic: add Logs and utilities implementation Serhii Iliushyk
                   ` (16 subsequent siblings)
  24 siblings, 0 replies; 238+ messages in thread
From: Serhii Iliushyk @ 2024-05-30 14:49 UTC (permalink / raw)
  To: dev; +Cc: mko-plv, ckm, andrew.rybchenko, ferruh.yigit

Add ntnic VFIO functionality.

Signed-off-by: Serhii Iliushyk <sil-plv@napatech.com>
---
 drivers/net/ntnic/ntnic_vfio.c | 232 +++++++++++++++++++++++++++++++++
 drivers/net/ntnic/ntnic_vfio.h |  21 +++
 2 files changed, 253 insertions(+)
 create mode 100644 drivers/net/ntnic/ntnic_vfio.c
 create mode 100644 drivers/net/ntnic/ntnic_vfio.h

diff --git a/drivers/net/ntnic/ntnic_vfio.c b/drivers/net/ntnic/ntnic_vfio.c
new file mode 100644
index 0000000000..116c238be6
--- /dev/null
+++ b/drivers/net/ntnic/ntnic_vfio.c
@@ -0,0 +1,232 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#include <sys/ioctl.h>
+
+#include <rte_malloc.h>
+#include <rte_memory.h>
+#include <rte_vfio.h>
+#include <rte_dev.h>
+#include <rte_bus_pci.h>
+#include <rte_spinlock.h>
+
+#include <ntlog.h>
+#include <nt_util.h>
+#include "ntnic_vfio.h"
+
+#define ONE_G_SIZE 0x40000000
+#define ONE_G_MASK (ONE_G_SIZE - 1)
+#define START_VF_IOVA 0x220000000000
+
+int nt_vfio_vf_num(const struct rte_pci_device *pdev)
+{
+	return ((pdev->addr.devid & 0x1f) << 3) + ((pdev->addr.function) & 0x7);
+}
+
+/* Internal API */
+struct vfio_dev {
+	int container_fd;
+	int group_fd;
+	int dev_fd;
+	uint64_t iova_addr;
+};
+
+static struct vfio_dev vfio_list[256];
+
+static struct vfio_dev *vfio_get(int vf_num)
+{
+	if (vf_num < 0 || vf_num > 255)
+		return NULL;
+
+	return &vfio_list[vf_num];
+}
+
+/* External API */
+int nt_vfio_setup(struct rte_pci_device *dev)
+{
+	char devname[RTE_DEV_NAME_MAX_LEN] = { 0 };
+	int iommu_group_num;
+	int vf_num;
+	struct vfio_dev *vfio;
+
+	NT_LOG(INF, ETHDEV, "NT VFIO device setup %s\n", dev->name);
+
+	vf_num = nt_vfio_vf_num(dev);
+
+	vfio = vfio_get(vf_num);
+
+	if (vfio == NULL) {
+		NT_LOG(ERR, ETHDEV, "VFIO device setup failed. Illegal device id\n");
+		return -1;
+	}
+
+	vfio->dev_fd = -1;
+	vfio->group_fd = -1;
+	vfio->container_fd = -1;
+	vfio->iova_addr = START_VF_IOVA;
+
+	rte_pci_device_name(&dev->addr, devname, RTE_DEV_NAME_MAX_LEN);
+	rte_vfio_get_group_num(rte_pci_get_sysfs_path(), devname, &iommu_group_num);
+
+	if (vf_num == 0) {
+		/* use default container for pf0 */
+		vfio->container_fd = RTE_VFIO_DEFAULT_CONTAINER_FD;
+
+	} else {
+		vfio->container_fd = rte_vfio_container_create();
+
+		if (vfio->container_fd < 0) {
+			NT_LOG(ERR, ETHDEV,
+				"VFIO device setup failed. VFIO container creation failed.\n");
+			return -1;
+		}
+	}
+
+	vfio->group_fd = rte_vfio_container_group_bind(vfio->container_fd, iommu_group_num);
+
+	if (vfio->group_fd < 0) {
+		NT_LOG(ERR, ETHDEV,
+			"VFIO device setup failed. VFIO container group bind failed.\n");
+		goto err;
+	}
+
+	if (vf_num > 0) {
+		if (rte_pci_map_device(dev)) {
+			NT_LOG(ERR, ETHDEV,
+				"Map VFIO device failed. is the vfio-pci driver loaded?\n");
+			goto err;
+		}
+	}
+
+	vfio->dev_fd = rte_intr_dev_fd_get(dev->intr_handle);
+
+	NT_LOG(DBG, ETHDEV,
+		"%s: VFIO id=%d, dev_fd=%d, container_fd=%d, group_fd=%d, iommu_group_num=%d\n",
+		dev->name, vf_num, vfio->dev_fd, vfio->container_fd, vfio->group_fd,
+		iommu_group_num);
+
+	return vf_num;
+
+err:
+
+	if (vfio->container_fd != RTE_VFIO_DEFAULT_CONTAINER_FD)
+		rte_vfio_container_destroy(vfio->container_fd);
+
+	return -1;
+}
+
+int nt_vfio_remove(int vf_num)
+{
+	struct vfio_dev *vfio;
+
+	NT_LOG(DBG, ETHDEV, "NT VFIO device remove VF=%d\n", vf_num);
+
+	vfio = vfio_get(vf_num);
+
+	if (!vfio) {
+		NT_LOG(ERR, ETHDEV, "VFIO device remove failed. Illegal device id\n");
+		return -1;
+	}
+
+	rte_vfio_container_destroy(vfio->container_fd);
+	return 0;
+}
+
+int nt_vfio_dma_map(int vf_num, void *virt_addr, uint64_t *iova_addr, uint64_t size)
+{
+	uint64_t gp_virt_base;
+	uint64_t gp_offset;
+
+	if (size == ONE_G_SIZE) {
+		gp_virt_base = (uint64_t)virt_addr & ~ONE_G_MASK;
+		gp_offset = (uint64_t)virt_addr & ONE_G_MASK;
+
+	} else {
+		gp_virt_base = (uint64_t)virt_addr;
+		gp_offset = 0;
+	}
+
+	struct vfio_dev *vfio;
+
+	vfio = vfio_get(vf_num);
+
+	if (vfio == NULL) {
+		NT_LOG(ERR, ETHDEV, "VFIO MAP: VF number %d invalid\n", vf_num);
+		return -1;
+	}
+
+	NT_LOG(DBG, ETHDEV,
+		"VFIO MMAP VF=%d VirtAddr=%" PRIX64 " HPA=%" PRIX64 " VirtBase=%" PRIX64
+		" IOVA Addr=%" PRIX64 " size=%d\n",
+		vf_num, virt_addr, rte_malloc_virt2iova(virt_addr), gp_virt_base, vfio->iova_addr,
+		size);
+
+	int res = rte_vfio_container_dma_map(vfio->container_fd, gp_virt_base, vfio->iova_addr,
+			size);
+
+	NT_LOG(DBG, ETHDEV, "VFIO MMAP res %i, container_fd %i, vf_num %i\n", res,
+		vfio->container_fd, vf_num);
+
+	if (res) {
+		NT_LOG(ERR, ETHDEV, "rte_vfio_container_dma_map failed: res %d\n", res);
+		return -1;
+	}
+
+	*iova_addr = vfio->iova_addr + gp_offset;
+
+	vfio->iova_addr += ONE_G_SIZE;
+
+	return 0;
+}
+
+int nt_vfio_dma_unmap(int vf_num, void *virt_addr, uint64_t iova_addr, uint64_t size)
+{
+	uint64_t gp_virt_base;
+	struct vfio_dev *vfio;
+
+	if (size == ONE_G_SIZE) {
+		uint64_t gp_offset;
+		gp_virt_base = (uint64_t)virt_addr & ~ONE_G_MASK;
+		gp_offset = (uint64_t)virt_addr & ONE_G_MASK;
+		iova_addr -= gp_offset;
+
+	} else {
+		gp_virt_base = (uint64_t)virt_addr;
+	}
+
+	vfio = vfio_get(vf_num);
+
+	if (vfio == NULL) {
+		NT_LOG(ERR, ETHDEV, "VFIO UNMAP: VF number %d invalid\n", vf_num);
+		return -1;
+	}
+
+	if (vfio->container_fd == -1)
+		return 0;
+
+	int res = rte_vfio_container_dma_unmap(vfio->container_fd, gp_virt_base, iova_addr, size);
+
+	if (res != 0) {
+		NT_LOG(ERR, ETHDEV,
+			"VFIO UNMMAP FAILED! res %i, container_fd %i, vf_num %i, virt_base=%" PRIX64
+			", IOVA=%" PRIX64 ", size=%llu\n",
+			res, vfio->container_fd, vf_num, gp_virt_base, iova_addr, size);
+		return -1;
+	}
+
+	return 0;
+}
+
+/* Internal init */
+
+RTE_INIT(nt_vfio_init);
+
+static void nt_vfio_init(void)
+{
+	struct nt_util_vfio_impl s = { .vfio_dma_map = nt_vfio_dma_map,
+		       .vfio_dma_unmap = nt_vfio_dma_unmap
+	};
+	nt_util_vfio_init(&s);
+}
diff --git a/drivers/net/ntnic/ntnic_vfio.h b/drivers/net/ntnic/ntnic_vfio.h
new file mode 100644
index 0000000000..0e3b12f847
--- /dev/null
+++ b/drivers/net/ntnic/ntnic_vfio.h
@@ -0,0 +1,21 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef _NTNIC_VFIO_H_
+#define _NTNIC_VFIO_H_
+
+#include <rte_dev.h>
+#include <rte_bus_pci.h>
+#include <ethdev_pci.h>
+
+int nt_vfio_setup(struct rte_pci_device *dev);
+int nt_vfio_remove(int vf_num);
+
+int nt_vfio_dma_map(int vf_num, void *virt_addr, uint64_t *iova_addr, uint64_t size);
+int nt_vfio_dma_unmap(int vf_num, void *virt_addr, uint64_t iova_addr, uint64_t size);
+
+/* Find device (PF/VF) number from device address */
+int nt_vfio_vf_num(const struct rte_pci_device *dev);
+#endif	/* _NTNIC_VFIO_H_ */
-- 
2.44.0


^ permalink raw reply	[flat|nested] 238+ messages in thread

* [PATCH v1 10/17] net/ntnic: add Logs and utilities implementation
  2024-05-30 14:48 [PATCH v1 01/17] net/ntnic: Add registers for NapaTech SmartNiC Serhii Iliushyk
                   ` (7 preceding siblings ...)
  2024-05-30 14:49 ` [PATCH v1 09/17] net/ntnic: add VFIO module Serhii Iliushyk
@ 2024-05-30 14:49 ` Serhii Iliushyk
  2024-05-30 14:49 ` [PATCH v1 11/17] net/ntnic: add ethdev and makes PMD available Serhii Iliushyk
                   ` (15 subsequent siblings)
  24 siblings, 0 replies; 238+ messages in thread
From: Serhii Iliushyk @ 2024-05-30 14:49 UTC (permalink / raw)
  To: dev; +Cc: mko-plv, ckm, andrew.rybchenko, ferruh.yigit

Add ntnic logging API and utilities.

Signed-off-by: Serhii Iliushyk <sil-plv@napatech.com>
---
 drivers/net/ntnic/ntlog/include/ntlog.h    | 162 +++++++++++++++++++++
 drivers/net/ntnic/ntlog/ntlog.c            | 108 ++++++++++++++
 drivers/net/ntnic/ntutil/include/nt_util.h |  51 +++++++
 drivers/net/ntnic/ntutil/nt_util.c         |  98 +++++++++++++
 4 files changed, 419 insertions(+)
 create mode 100644 drivers/net/ntnic/ntlog/include/ntlog.h
 create mode 100644 drivers/net/ntnic/ntlog/ntlog.c
 create mode 100644 drivers/net/ntnic/ntutil/include/nt_util.h
 create mode 100644 drivers/net/ntnic/ntutil/nt_util.c

diff --git a/drivers/net/ntnic/ntlog/include/ntlog.h b/drivers/net/ntnic/ntlog/include/ntlog.h
new file mode 100644
index 0000000000..75fc08d4e1
--- /dev/null
+++ b/drivers/net/ntnic/ntlog/include/ntlog.h
@@ -0,0 +1,162 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef NTOSS_SYSTEM_NTLOG_H
+#define NTOSS_SYSTEM_NTLOG_H
+
+#include <stdarg.h>
+#include <stdint.h>
+
+#ifndef NT_LOG_MODULE_PREFIX
+
+/* DPDK modules */
+#define NT_LOG_MODULE_EAL 0
+#define NT_LOG_MODULE_MALLOC 1
+#define NT_LOG_MODULE_RING 2
+#define NT_LOG_MODULE_MEMPOOL 3
+#define NT_LOG_MODULE_TIMER 4
+#define NT_LOG_MODULE_PMD 5
+#define NT_LOG_MODULE_HASH 6
+#define NT_LOG_MODULE_LPM 7
+#define NT_LOG_MODULE_KNI 8
+#define NT_LOG_MODULE_ACL 9
+#define NT_LOG_MODULE_POWER 10
+#define NT_LOG_MODULE_METER 11
+#define NT_LOG_MODULE_SCHED 12
+#define NT_LOG_MODULE_PORT 13
+#define NT_LOG_MODULE_TABLE 14
+#define NT_LOG_MODULE_PIPELINE 15
+#define NT_LOG_MODULE_MBUF 16
+#define NT_LOG_MODULE_CRYPTODEV 17
+#define NT_LOG_MODULE_EFD 18
+#define NT_LOG_MODULE_EVENTDEV 19
+#define NT_LOG_MODULE_GSO 20
+#define NT_LOG_MODULE_USER1 24
+#define NT_LOG_MODULE_USER2 25
+#define NT_LOG_MODULE_USER3 26
+#define NT_LOG_MODULE_USER4 27
+#define NT_LOG_MODULE_USER5 28
+#define NT_LOG_MODULE_USER6 29
+#define NT_LOG_MODULE_USER7 30
+#define NT_LOG_MODULE_USER8 31
+
+/* NT modules */
+#define NT_LOG_MODULE_GENERAL 10000	/* Should always be a first (smallest) */
+#define NT_LOG_MODULE_NTHW 10001
+#define NT_LOG_MODULE_FILTER 10002
+#define NT_LOG_MODULE_DRV 10003
+#define NT_LOG_MODULE_VDPA 10004
+#define NT_LOG_MODULE_FPGA 10005
+#define NT_LOG_MODULE_NTCONNECT 10006
+#define NT_LOG_MODULE_ETHDEV 10007
+#define NT_LOG_MODULE_SENSOR 10008
+#define NT_LOG_MODULE_END 10009	/* Mark for the range end of NT_LOG */
+
+#define NT_LOG_MODULE_COUNT (NT_LOG_MODULE_END - NT_LOG_MODULE_GENERAL)
+#define NT_LOG_MODULE_INDEX(module) ((module) - (NT_LOG_MODULE_GENERAL))
+#define NT_LOG_MODULE_PREFIX(type) NT_LOG_MODULE_##type
+
+#endif
+
+#ifndef NT_LOG_ENABLE
+#define NT_LOG_ENABLE 1
+#endif
+
+#if defined NT_LOG_ENABLE && NT_LOG_ENABLE > 0
+#ifndef NT_LOG_ENABLE_ERR
+#define NT_LOG_ENABLE_ERR 1
+#endif
+#ifndef NT_LOG_ENABLE_WRN
+#define NT_LOG_ENABLE_WRN 1
+#endif
+#ifndef NT_LOG_ENABLE_INF
+#define NT_LOG_ENABLE_INF 1
+#endif
+#ifndef NT_LOG_ENABLE_DBG
+#define NT_LOG_ENABLE_DBG 1
+#endif
+#ifndef NT_LOG_ENABLE_DB1
+#define NT_LOG_ENABLE_DB1 0
+#endif
+#ifndef NT_LOG_ENABLE_DB2
+#define NT_LOG_ENABLE_DB2 0
+#endif
+#endif
+
+#if defined NT_LOG_ENABLE_ERR && NT_LOG_ENABLE_ERR > 0
+#define NT_LOG_NT_LOG_ERR(...) nt_log(__VA_ARGS__)
+#else
+#define NT_LOG_NT_LOG_ERR(...)
+#endif
+
+#if defined NT_LOG_ENABLE_WRN && NT_LOG_ENABLE_WRN > 0
+#define NT_LOG_NT_LOG_WRN(...) nt_log(__VA_ARGS__)
+#else
+#define NT_LOG_NT_LOG_WRN(...)
+#endif
+
+#if defined NT_LOG_ENABLE_INF && NT_LOG_ENABLE_INF > 0
+#define NT_LOG_NT_LOG_INF(...) nt_log(__VA_ARGS__)
+#else
+#define NT_LOG_NT_LOG_INF(...)
+#endif
+
+#if defined NT_LOG_ENABLE_DBG && NT_LOG_ENABLE_DBG > 0
+#define NT_LOG_NT_LOG_DBG(...) nt_log(__VA_ARGS__)
+#else
+#define NT_LOG_NT_LOG_DBG(...)
+#endif
+
+#if defined NT_LOG_ENABLE_DB1 && NT_LOG_ENABLE_DB1 > 0
+#define NT_LOG_NT_LOG_DB1(...) nt_log(__VA_ARGS__)
+#else
+#define NT_LOG_NT_LOG_DB1(...)
+#endif
+
+#if defined NT_LOG_ENABLE_DB2 && NT_LOG_ENABLE_DB2 > 0
+#define NT_LOG_NT_LOG_DB2(...) nt_log(__VA_ARGS__)
+#else
+#define NT_LOG_NT_LOG_DB2(...)
+#endif
+
+#define NT_LOG(level, module, ...)                                                                \
+	NT_LOG_NT_LOG_##level(NT_LOG_##level, NT_LOG_MODULE_PREFIX(module),                       \
+			      #module ": " #level ": " __VA_ARGS__)
+
+enum nt_log_level {
+	NT_LOG_ERR = 0x001,
+	NT_LOG_WRN = 0x002,
+	NT_LOG_INF = 0x004,
+	NT_LOG_DBG = 0x008,
+	NT_LOG_DB1 = 0x010,
+	NT_LOG_DB2 = 0x020,
+};
+
+struct nt_log_impl {
+	int (*init)(void);
+	int (*log)(enum nt_log_level level, uint32_t module, const char *format, va_list args);
+	int (*is_debug)(uint32_t module);
+};
+
+int nt_log_init(struct nt_log_impl *impl);
+
+int nt_log(enum nt_log_level level, uint32_t module, const char *format, ...);
+
+/* Returns 1 if RTE_DEBUG, 0 if lower log level, -1 if incorrect module */
+int nt_log_is_debug(uint32_t module);
+
+/*
+ * nt log helper functions
+ * to create a string for NT_LOG usage to output a one-liner log
+ * to use when one single function call to NT_LOG is not optimal - that is
+ * you do not know the number of parameters at programming time or it is variable
+ */
+char *ntlog_helper_str_alloc(const char *sinit);
+
+void ntlog_helper_str_add(char *s, const char *format, ...);
+
+void ntlog_helper_str_free(char *s);
+
+#endif	/* NTOSS_SYSTEM_NTLOG_H */
diff --git a/drivers/net/ntnic/ntlog/ntlog.c b/drivers/net/ntnic/ntlog/ntlog.c
new file mode 100644
index 0000000000..a4f104efad
--- /dev/null
+++ b/drivers/net/ntnic/ntlog/ntlog.c
@@ -0,0 +1,108 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#include "ntlog.h"
+
+#include <stdarg.h>
+#include <stddef.h>
+#include <string.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <stdbool.h>
+
+#define NTLOG_HELPER_STR_SIZE_MAX (1024)
+
+static struct nt_log_impl *user_impl;
+
+int nt_log_init(struct nt_log_impl *impl)
+{
+	user_impl = impl;
+	return user_impl->init();
+}
+
+static char *last_trailing_eol(char *s)
+{
+	int i = strlen(s) - 1;
+
+	/* Skip spaces */
+	while (i > 0 && s[i] == ' ')
+		--i;
+
+	if (s[i] != '\n')
+		return NULL;
+
+	/*
+	 * Find the last trailing EOL "hello_world\n\n\n"
+	 *                                         ^
+	 */
+	while (i > 1 && s[i] == '\n' && s[i - 1] == '\n')
+		--i;
+
+	return &s[i];
+}
+
+/* Always terminates the NT_LOG statement with a !!!single!!! EOL. */
+int nt_log(enum nt_log_level level, uint32_t module, const char *format, ...)
+{
+	int rv = -1;
+	va_list args;
+
+	if (user_impl == NULL)
+		return rv;
+
+	char *actual_format = ntlog_helper_str_alloc(format);
+	char *eol = last_trailing_eol(actual_format);
+
+	if (!eol)	/* If log line is not terminated with '\n' we add it. */
+		strncat(actual_format, "\n", NTLOG_HELPER_STR_SIZE_MAX - strlen(actual_format));
+
+	else	/* If multiple trailing EOLs, then keep just one of them. */
+		*(eol + 1) = '\0';
+
+	va_start(args, format);
+	rv = user_impl->log(level, module, actual_format, args);
+	va_end(args);
+
+	ntlog_helper_str_free(actual_format);
+	return rv;
+}
+
+int nt_log_is_debug(uint32_t module)
+{
+	return user_impl->is_debug(module);
+}
+
+char *ntlog_helper_str_alloc(const char *sinit)
+{
+	char *s = malloc(NTLOG_HELPER_STR_SIZE_MAX);
+
+	if (!s)
+		return NULL;
+
+	if (sinit)
+		snprintf(s, NTLOG_HELPER_STR_SIZE_MAX, "%s", sinit);
+
+	else
+		s[0] = '\0';
+
+	return s;
+}
+
+void ntlog_helper_str_add(char *s, const char *format, ...)
+{
+	if (!s)
+		return;
+
+	va_list args;
+	va_start(args, format);
+	int len = strlen(s);
+	vsnprintf(&s[len], (NTLOG_HELPER_STR_SIZE_MAX - 1 - len), format, args);
+	va_end(args);
+}
+
+void ntlog_helper_str_free(char *s)
+{
+	free(s);
+}
diff --git a/drivers/net/ntnic/ntutil/include/nt_util.h b/drivers/net/ntnic/ntutil/include/nt_util.h
new file mode 100644
index 0000000000..0f27698a84
--- /dev/null
+++ b/drivers/net/ntnic/ntutil/include/nt_util.h
@@ -0,0 +1,51 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef NTOSS_SYSTEM_NT_UTIL_H
+#define NTOSS_SYSTEM_NT_UTIL_H
+
+#include <stdint.h>
+
+/*
+ * Windows size in seconds for measuring FLM load
+ * and Port load.
+ * The windows size must max be 3 min in order to
+ * prevent overflow.
+ */
+#define FLM_LOAD_WINDOWS_SIZE 2ULL
+#define PORT_LOAD_WINDOWS_SIZE 2ULL
+
+/* Total max VDPA ports */
+#define MAX_VDPA_PORTS 128UL
+
+#define PCIIDENT_TO_DOMAIN(pci_ident) ((uint16_t)(((unsigned int)(pci_ident) >> 16) & 0xFFFFU))
+#define PCIIDENT_TO_BUSNR(pci_ident) ((uint8_t)(((unsigned int)(pci_ident) >> 8) & 0xFFU))
+#define PCIIDENT_TO_DEVNR(pci_ident) ((uint8_t)(((unsigned int)(pci_ident) >> 3) & 0x1FU))
+#define PCIIDENT_TO_FUNCNR(pci_ident) ((uint8_t)(((unsigned int)(pci_ident) >> 0) & 0x7U))
+#define PCIIDENT_PRINT_STR "%04x:%02x:%02x.%x"
+#define BDF_TO_PCIIDENT(dom, bus, dev, fnc) (((dom) << 16) | ((bus) << 8) | ((dev) << 3) | (fnc))
+
+uint64_t nt_os_get_time_monotonic_counter(void);
+void nt_os_wait_usec(int val);
+
+uint64_t nt_util_align_size(uint64_t size);
+
+struct nt_dma_s {
+	uint64_t iova;
+	uint64_t addr;
+	uint64_t size;
+};
+
+struct nt_dma_s *nt_dma_alloc(uint64_t size, uint64_t align, int numa);
+void nt_dma_free(struct nt_dma_s *vfio_addr);
+
+struct nt_util_vfio_impl {
+	int (*vfio_dma_map)(int vf_num, void *virt_addr, uint64_t *iova_addr, uint64_t size);
+	int (*vfio_dma_unmap)(int vf_num, void *virt_addr, uint64_t iova_addr, uint64_t size);
+};
+
+void nt_util_vfio_init(struct nt_util_vfio_impl *impl);
+
+#endif	/* NTOSS_SYSTEM_NT_UTIL_H */
diff --git a/drivers/net/ntnic/ntutil/nt_util.c b/drivers/net/ntnic/ntutil/nt_util.c
new file mode 100644
index 0000000000..e4b18c1a7e
--- /dev/null
+++ b/drivers/net/ntnic/ntutil/nt_util.c
@@ -0,0 +1,98 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#include <unistd.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <inttypes.h>
+#include <stdio.h>
+#include <assert.h>
+
+#include <rte_cycles.h>
+#include "rte_malloc.h"
+
+#include "ntlog.h"
+#include "nt_util.h"
+
+static struct nt_util_vfio_impl vfio_cb;
+
+/* uses usleep which schedules out the calling thread */
+void nt_os_wait_usec(int val)
+{
+	rte_delay_us_sleep(val);
+}
+
+uint64_t nt_os_get_time_monotonic_counter(void)
+{
+	return rte_get_timer_cycles();
+}
+
+/* Allocation size matching minimum alignment of specified size */
+uint64_t nt_util_align_size(uint64_t size)
+{
+	return 1 << rte_log2_u64(size);
+}
+
+void nt_util_vfio_init(struct nt_util_vfio_impl *impl)
+{
+	vfio_cb = *impl;
+}
+
+struct nt_dma_s *nt_dma_alloc(uint64_t size, uint64_t align, int numa)
+{
+	int res;
+	struct nt_dma_s *vfio_addr;
+
+	vfio_addr = rte_malloc(NULL, sizeof(struct nt_dma_s), 0);
+
+	if (!vfio_addr) {
+		NT_LOG(ERR, GENERAL, "VFIO rte_malloc failed\n");
+		return NULL;
+	}
+
+	void *addr = rte_malloc_socket(NULL, size, align, numa);
+
+	if (!addr) {
+		rte_free(vfio_addr);
+		NT_LOG(ERR, GENERAL, "VFIO rte_malloc_socket failed\n");
+		return NULL;
+	}
+
+	res = vfio_cb.vfio_dma_map(0, addr, &vfio_addr->iova, nt_util_align_size(size));
+
+	if (res != 0) {
+		rte_free(addr);
+		rte_free(vfio_addr);
+		NT_LOG(ERR, GENERAL, "VFIO nt_dma_map failed\n");
+		return NULL;
+	}
+
+	vfio_addr->addr = (uint64_t)addr;
+	vfio_addr->size = nt_util_align_size(size);
+
+	NT_LOG(DBG, GENERAL,
+		"VFIO DMA alloc addr=%" PRIX64 ", iova=%" PRIX64 ", size=%u, align=0x%X\n",
+		vfio_addr->addr, vfio_addr->iova, vfio_addr->size, align);
+
+	return vfio_addr;
+}
+
+void nt_dma_free(struct nt_dma_s *vfio_addr)
+{
+	NT_LOG(DBG, GENERAL, "VFIO DMA free addr=%" PRIX64 ", iova=%" PRIX64 ", size=%u\n",
+		vfio_addr->addr, vfio_addr->iova, vfio_addr->size);
+
+	int res = vfio_cb.vfio_dma_unmap(0, (void *)vfio_addr->addr, vfio_addr->iova,
+			vfio_addr->size);
+
+	if (res != 0) {
+		NT_LOG(WRN, GENERAL,
+			"VFIO DMA free FAILED addr=%" PRIX64 ", iova=%" PRIX64 ", size=%u\n",
+			vfio_addr->addr, vfio_addr->iova, vfio_addr->size);
+	}
+
+	rte_free((void *)(vfio_addr->addr));
+	rte_free(vfio_addr);
+}
-- 
2.44.0


^ permalink raw reply	[flat|nested] 238+ messages in thread

* [PATCH v1 11/17] net/ntnic: add ethdev and makes PMD available
  2024-05-30 14:48 [PATCH v1 01/17] net/ntnic: Add registers for NapaTech SmartNiC Serhii Iliushyk
                   ` (8 preceding siblings ...)
  2024-05-30 14:49 ` [PATCH v1 10/17] net/ntnic: add Logs and utilities implementation Serhii Iliushyk
@ 2024-05-30 14:49 ` Serhii Iliushyk
  2024-05-30 14:49 ` [PATCH v1 12/17] net/ntnic: add support of the NT200A0X smartNIC Serhii Iliushyk
                   ` (14 subsequent siblings)
  24 siblings, 0 replies; 238+ messages in thread
From: Serhii Iliushyk @ 2024-05-30 14:49 UTC (permalink / raw)
  To: dev; +Cc: mko-plv, ckm, andrew.rybchenko, ferruh.yigit, Thomas Monjalon

Add ethdev to ntnic.

Signed-off-by: Serhii Iliushyk <sil-plv@napatech.com>
---
 .mailmap                           |    1 +
 MAINTAINERS                        |    6 +
 doc/guides/nics/features/ntnic.ini |    9 +
 doc/guides/nics/index.rst          |    1 +
 doc/guides/nics/ntnic.rst          |  115 +++
 drivers/net/meson.build            |    1 +
 drivers/net/ntnic/meson.build      |  101 ++
 drivers/net/ntnic/ntnic_ethdev.c   | 1551 ++++++++++++++++++++++++++++
 drivers/net/ntnic/ntnic_ethdev.h   |   32 +
 drivers/net/ntnic/rte_pmd_ntnic.h  |   43 +
 10 files changed, 1860 insertions(+)
 create mode 100644 doc/guides/nics/features/ntnic.ini
 create mode 100644 doc/guides/nics/ntnic.rst
 create mode 100644 drivers/net/ntnic/meson.build
 create mode 100644 drivers/net/ntnic/ntnic_ethdev.c
 create mode 100644 drivers/net/ntnic/ntnic_ethdev.h
 create mode 100644 drivers/net/ntnic/rte_pmd_ntnic.h

diff --git a/.mailmap b/.mailmap
index 87fa24714e..99719b74a1 100644
--- a/.mailmap
+++ b/.mailmap
@@ -1288,6 +1288,7 @@ Sergey Madaminov <sergey.madaminov@gmail.com>
 Sergey Mironov <grrwlf@gmail.com>
 Sergey Temerkhanov <sergey.temerkhanov@intel.com>
 Sergio Gonzalez Monroy <sergio.gonzalez.monroy@intel.com>
+Serhii Iliushyk <sil-plv@napatech.com>
 Seth Arnold <seth.arnold@canonical.com>
 Seth Howell <seth.howell@intel.com>
 Shachar Beiser <shacharbe@mellanox.com>
diff --git a/MAINTAINERS b/MAINTAINERS
index c9adff9846..27e818d050 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1063,6 +1063,12 @@ F: drivers/net/memif/
 F: doc/guides/nics/memif.rst
 F: doc/guides/nics/features/memif.ini
 
+NTNIC PMD
+M: Christian Koue Muf <ckm@napatech.com>
+M: Serhii Iliushyk <sil-plv@napatech.com>
+F: drivers/net/ntnic/
+F: doc/guides/nics/ntnic.rst
+F: doc/guides/nics/features/ntnic.ini
 
 Crypto Drivers
 --------------
diff --git a/doc/guides/nics/features/ntnic.ini b/doc/guides/nics/features/ntnic.ini
new file mode 100644
index 0000000000..25abc6df89
--- /dev/null
+++ b/doc/guides/nics/features/ntnic.ini
@@ -0,0 +1,9 @@
+;
+; Supported features of the 'ntnic' network poll mode driver.
+;
+; Refer to default.ini for the full list of available PMD features.
+;
+[Features]
+Link status          = Y
+Linux                = Y
+x86-64               = Y
diff --git a/doc/guides/nics/index.rst b/doc/guides/nics/index.rst
index 7bfcac880f..c14bc7988a 100644
--- a/doc/guides/nics/index.rst
+++ b/doc/guides/nics/index.rst
@@ -53,6 +53,7 @@ Network Interface Controller Drivers
     nfb
     nfp
     ngbe
+    ntnic
     null
     octeon_ep
     octeontx
diff --git a/doc/guides/nics/ntnic.rst b/doc/guides/nics/ntnic.rst
new file mode 100644
index 0000000000..aa043a0102
--- /dev/null
+++ b/doc/guides/nics/ntnic.rst
@@ -0,0 +1,115 @@
+..  SPDX-License-Identifier: BSD-3-Clause
+    Copyright(c) 2023 Napatech A/S
+
+NTNIC Poll Mode Driver
+======================
+
+The NTNIC PMD provides poll mode driver support for Napatech smartNICs.
+
+
+Design
+------
+
+The NTNIC PMD is designed as a pure user-space driver, and requires no special
+Napatech kernel modules.
+
+The Napatech smartNIC presents one control PCI device (PF0). NTNIC PMD accesses
+smartNIC PF0 via vfio-pci kernel driver. Access to PF0 for all purposes is
+exclusive, so only one process should access it. The physical ports are located
+behind PF0 as DPDK port 0 and 1.
+
+
+Supported NICs
+--------------
+
+- NT200A02 2x100G SmartNIC
+
+    - FPGA ID 9563 (Inline Flow Management)
+
+
+Features
+--------
+
+- Link state information.
+
+
+Limitations
+~~~~~~~~~~~
+
+Kernel versions before 5.7 are not supported. Kernel version 5.7 added vfio-pci
+support for creating VFs from the PF which is required for the PMD to use
+vfio-pci on the PF. This support has been back-ported to older Linux
+distributions and they are also supported. If vfio-pci is not required kernel
+version 4.18 is supported.
+
+Current NTNIC PMD implementation only supports one active adapter.
+
+
+Configuration
+-------------
+
+Command line arguments
+~~~~~~~~~~~~~~~~~~~~~~
+
+Following standard DPDK command line arguments are used by the PMD:
+
+    -a: Used to specifically define the NT adapter by PCI ID.
+    --iova-mode: Must be set to ‘pa’ for Physical Address mode.
+
+NTNIC specific arguments can be passed to the PMD in the PCI device parameter list::
+
+    <application> ... -a 0000:03:00.0[{,<NTNIC specific argument>}]
+
+The NTNIC specific argument format is::
+
+    <object>.<attribute>=[<object-ids>:]<value>
+
+Multiple arguments for the same device are separated by ‘,’ comma.
+<object-ids> can be a single value or a range.
+
+- ``supported-fpgas`` parameter [str]
+
+    List the supported FPGAs for a compiled NTNIC DPDK-driver.
+
+    This parameter has two options::
+
+        - list.
+        - verbose.
+
+    Example usages::
+
+        -a <domain>:<bus>:00.0,supported-fpgas=list
+        -a <domain>:<bus>:00.0,supported-fpgas=verbose
+
+- ``help`` parameter [none]
+
+    List all available NTNIC PMD parameters.
+
+
+Logging and Debugging
+---------------------
+
+NTNIC supports several groups of logging that can be enabled with ``log-level``
+parameter:
+
+- ETHDEV.
+
+    Logging info from the main PMD code. i.e. code that is related to DPDK::
+
+        --log-level=ntnic.ethdev,8
+
+- NTHW.
+
+    Logging info from NTHW. i.e. code that is related to the FPGA and the Adapter::
+
+        --log-level=ntnic.nthw,8
+
+- FPGA.
+
+    Logging related to FPGA::
+
+        --log-level=ntnic.fpga,8
+
+To enable logging on all levels use wildcard in the following way::
+
+    --log-level=ntnic.*,8
diff --git a/drivers/net/meson.build b/drivers/net/meson.build
index bd38b533c5..fb6d34b782 100644
--- a/drivers/net/meson.build
+++ b/drivers/net/meson.build
@@ -45,6 +45,7 @@ drivers = [
         'nfb',
         'nfp',
         'ngbe',
+        'ntnic',
         'null',
         'octeontx',
         'octeon_ep',
diff --git a/drivers/net/ntnic/meson.build b/drivers/net/ntnic/meson.build
new file mode 100644
index 0000000000..a9bf9b5906
--- /dev/null
+++ b/drivers/net/ntnic/meson.build
@@ -0,0 +1,101 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2020-2023 Napatech A/S
+
+allow_experimental_apis = true
+
+# config object
+ntoss_conf = configuration_data()
+
+# transfer options into config object
+ntoss_conf.set('NT_VF_VDPA', false)
+
+# cflags
+cflags += [
+    '-std=c11',
+    '-DNTHW_DPDK',
+]
+
+# check option 'debug' (boolean flag derived from meson buildtype)
+if get_option('debug')
+    cflags += '-DDEBUG'
+endif
+
+# check if VF and vDPA support should be compiled in
+if ntoss_conf.get('NT_VF_VDPA') == true
+  cflags += '-DNT_VF_VDPA'
+  # check if the relay core feature should be compiled in
+endif
+
+# includes
+includes = [
+    include_directories('..'),
+    include_directories('.'),
+    include_directories('include'),
+    include_directories('ntlog/include'),
+    include_directories('ntutil/include'),
+    include_directories('nthw'),
+    include_directories('nthw/supported'),
+    include_directories('nthw/model'),
+    # include_directories('sensors'),
+    # include_directories('sensors/avr_sensors'),
+    # include_directories('sensors/board_sensors'),
+    # include_directories('nim/nim_sensors'),
+    # include_directories('nim/include'),
+    # include_directories('nim/sfp_sensors'),
+    # include_directories('nim/qsfp_sensors'),
+    # include_directories('sensors/ntavr'),
+    # include_directories('ntconnect_modules'),
+]
+
+# ntnic_core
+includes += include_directories('nthw/core/include')
+includes += include_directories('nthw/core')
+if fs.is_dir('nthw/core/nt200a0x')
+    includes += include_directories('nthw/core/nt200a0x')
+    includes += include_directories('nthw/core/nt200a0x/reset')
+    includes += include_directories('nthw/core/nt200a0x/clock_profiles')
+endif
+if fs.is_dir('nthw/core/nt50b01')
+    includes += include_directories('nthw/core/nt50b01')
+    includes += include_directories('nthw/core/nt50b01/reset')
+    includes += include_directories('nthw/core/nt50b01/clock_profiles')
+endif
+if fs.is_dir('nthw/core/nt400dxx')
+    includes += include_directories('nthw/core/nt400dxx')
+    includes += include_directories('nthw/core/nt400dxx/reset')
+endif
+# includes += include_directories('adapter')
+# includes += include_directories('link_mgmt')
+# includes += include_directories('nim')
+# includes += include_directories('nim/nim_sensors')
+if fs.is_dir('nim/sfp_sensors')
+    includes += include_directories('nim/sfp_sensors')
+endif
+if fs.is_dir('nim/qsfp_sensors')
+    includes += include_directories('nim/qsfp_sensors')
+endif
+
+# deps
+deps += 'vhost'
+
+# headers
+headers = files('rte_pmd_ntnic.h')
+
+# all sources
+sources = files(
+    'dpdk_mod_reg.c',
+    'nthw/supported/nthw_fpga_9563_055_039_0000.c',
+    'nthw/supported/nthw_fpga_instances.c',
+    'nthw/supported/nthw_fpga_mod_str_map.c',
+    'nthw/model/nthw_fpga_model.c',
+    'nthw/nthw_epp.c',
+    'nthw/nthw_platform.c',
+    'nthw/nthw_rac.c',
+    'nthw/nthw_utils.c',
+    'ntlog/ntlog.c',
+    'ntnic_ethdev.c',
+    'ntnic_mod_reg.c',
+    'ntnic_vfio.c',
+    'ntutil/nt_util.c',
+)
+# END
diff --git a/drivers/net/ntnic/ntnic_ethdev.c b/drivers/net/ntnic/ntnic_ethdev.c
new file mode 100644
index 0000000000..86db8e8a6f
--- /dev/null
+++ b/drivers/net/ntnic/ntnic_ethdev.c
@@ -0,0 +1,1551 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#include <stdio.h>
+#include <errno.h>
+#include <stdint.h>
+#include <stdarg.h>
+#include <sys/queue.h>
+
+#include <ntdrv_4ga.h>
+
+#include <rte_common.h>
+#include <rte_kvargs.h>
+#include <rte_interrupts.h>
+#include <rte_byteorder.h>
+#include <rte_debug.h>
+#include <rte_pci.h>
+#include <rte_bus_pci.h>
+#include <rte_bus_vdev.h>
+#include <rte_ether.h>
+#include <ethdev_pci.h>
+#include <ethdev_driver.h>
+#include <rte_memory.h>
+#include <rte_eal.h>
+#include <rte_malloc.h>
+#include <rte_dev.h>
+#include <rte_vfio.h>
+#include <rte_flow_driver.h>
+#include <vdpa_driver.h>
+#include <rte_pmd_ntnic.h>
+
+#include "ntlog.h"
+
+#include "stream_binary_flow_api.h"
+#include "ntos_drv.h"
+#include "ntoss_virt_queue.h"
+#include "nthw_fpga.h"
+#include "nthw_fpga_instances.h"
+#include "ntnic_ethdev.h"
+#include "ntnic_vfio.h"
+#include "nthw_fpga_param_defs.h"
+#include "flow_api.h"
+#include "ntnic_mod_reg.h"
+#include "dpdk_mod_reg.h"
+#include "nt_util.h"
+
+/* Feature defines: */
+
+#undef DEBUG_REG_ACCESS
+
+#if defined(DEBUG_REG_ACCESS)
+#include "nthw_debug.h"
+#endif	/* DEBUG_REG_ACCESS */
+
+/* Defines: */
+#if RTE_VERSION_NUM(23, 11, 0, 0) < RTE_VERSION
+const rte_thread_attr_t thread_attr = { .priority = RTE_THREAD_PRIORITY_NORMAL };
+#define THREAD_CREATE(a, b, c) rte_thread_create(a, &thread_attr, b, c)
+#define THREAD_CTRL_CREATE(a, b, c, d) rte_thread_create_control(a, b, c, d)
+#define THREAD_JOIN(a) rte_thread_join(a, NULL)
+#define THREAD_FUNC static uint32_t
+#define THREAD_RETURN (0)
+#else
+#define THREAD_CREATE(a, b, c) pthread_create(a, NULL, b, c)
+#define THREAD_CTRL_CREATE(a, b, c, d) rte_ctrl_thread_create(a, b, NULL, c, d)
+#define THREAD_JOIN(a) pthread_join(a, NULL)
+#define THREAD_FUNC static void *
+#define THREAD_RETURN (NULL)
+#endif
+
+#define HW_MAX_PKT_LEN (10000)
+#define MAX_MTU (HW_MAX_PKT_LEN - RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN)
+#define MIN_MTU 46
+#define MIN_MTU_INLINE 512
+
+#define EXCEPTION_PATH_HID 0
+
+#define MAX_TOTAL_QUEUES 128
+
+#define ONE_G_SIZE 0x40000000
+#define ONE_G_MASK (ONE_G_SIZE - 1)
+
+#define VIRTUAL_TUNNEL_PORT_OFFSET 72
+
+#define MAX_RX_PACKETS 128
+#define MAX_TX_PACKETS 128
+
+
+/* Global statics: */
+struct pmd_internals *pmd_internals_base;
+uint64_t rte_tsc_freq;
+
+/* ------- Tables to store DPDK EAL log levels for nt log modules---------- */
+static int nt_log_module_logtype[NT_LOG_MODULE_COUNT] = { -1 };
+/* Register the custom module binding to EAL --log-level option here */
+static const char *nt_log_module_eal_name[NT_LOG_MODULE_COUNT] = {
+	[NT_LOG_MODULE_INDEX(NT_LOG_MODULE_GENERAL)] = "pmd.net.ntnic.general",
+	[NT_LOG_MODULE_INDEX(NT_LOG_MODULE_NTHW)] = "pmd.net.ntnic.nthw",
+	[NT_LOG_MODULE_INDEX(NT_LOG_MODULE_FILTER)] = "pmd.net.ntnic.filter",
+	[NT_LOG_MODULE_INDEX(NT_LOG_MODULE_DRV)] = "pmd.net.ntnic.drv",
+	[NT_LOG_MODULE_INDEX(NT_LOG_MODULE_VDPA)] = "pmd.net.ntnic.vdpa",
+	[NT_LOG_MODULE_INDEX(NT_LOG_MODULE_FPGA)] = "pmd.net.ntnic.fpga",
+	[NT_LOG_MODULE_INDEX(NT_LOG_MODULE_SENSOR)] = "pmd.net.ntnic.sensor",
+	[NT_LOG_MODULE_INDEX(NT_LOG_MODULE_NTCONNECT)] = "pmd.net.ntnic.ntconnect",
+	[NT_LOG_MODULE_INDEX(NT_LOG_MODULE_ETHDEV)] = "pmd.net.ntnic.ethdev"
+};
+/* -------------------------------------------------------------------------- */
+
+rte_spinlock_t hwlock = RTE_SPINLOCK_INITIALIZER;
+
+static void (*previous_handler)(int sig);
+#if RTE_VERSION_NUM(23, 11, 0, 0) < RTE_VERSION
+static rte_thread_t shutdown_tid;
+#else
+static pthread_t shutdown_tid;
+#endif
+int kill_pmd;
+
+#define ETH_DEV_NTNIC_HELP_ARG "help"
+#define ETH_DEV_NTHW_LINK_SPEED_ARG "port.link_speed"
+#define ETH_DEV_NTNIC_SUPPORTED_FPGAS_ARG "supported-fpgas"
+
+#define DVIO_VHOST_DIR_NAME "/usr/local/var/run/"
+
+static const char *const valid_arguments[] = {
+	ETH_DEV_NTNIC_HELP_ARG,
+	ETH_DEV_NTHW_LINK_SPEED_ARG,
+	ETH_DEV_NTNIC_SUPPORTED_FPGAS_ARG,
+	NULL,
+};
+
+/* Functions: */
+
+/*
+ * The set of PCI devices this driver supports
+ */
+static const struct rte_pci_id nthw_pci_id_map[] = {
+	{ RTE_PCI_DEVICE(NT_HW_PCI_VENDOR_ID_LENOVO, NT_HW_PCI_DEVICE_ID_NT200A02_LENOVO) },
+	{ RTE_PCI_DEVICE(NT_HW_PCI_VENDOR_ID, NT_HW_PCI_DEVICE_ID_NT200A02) },
+	{
+		.vendor_id = 0,
+	},	/* sentinel */
+};
+
+static const struct sg_ops_s *sg_ops;
+
+/*
+ * Store and get adapter info
+ */
+
+static struct drv_s *_g_p_drv[NUM_ADAPTER_MAX] = { NULL };
+
+static void store_pdrv(struct drv_s *p_drv)
+{
+	if (p_drv->adapter_no > NUM_ADAPTER_MAX) {
+		NT_LOG(ERR, ETHDEV,
+			"Internal error adapter number %u out of range. Max number of adapters: %u\n",
+			p_drv->adapter_no, NUM_ADAPTER_MAX);
+		return;
+	}
+
+	if (_g_p_drv[p_drv->adapter_no] != 0) {
+		NT_LOG(WRN, ETHDEV,
+			"Overwriting adapter structure for PCI  " PCIIDENT_PRINT_STR
+			" with adapter structure for PCI  " PCIIDENT_PRINT_STR "\n",
+			PCIIDENT_TO_DOMAIN(_g_p_drv[p_drv->adapter_no]->ntdrv.pciident),
+			PCIIDENT_TO_BUSNR(_g_p_drv[p_drv->adapter_no]->ntdrv.pciident),
+			PCIIDENT_TO_DEVNR(_g_p_drv[p_drv->adapter_no]->ntdrv.pciident),
+			PCIIDENT_TO_FUNCNR(_g_p_drv[p_drv->adapter_no]->ntdrv.pciident),
+			PCIIDENT_TO_DOMAIN(p_drv->ntdrv.pciident),
+			PCIIDENT_TO_BUSNR(p_drv->ntdrv.pciident),
+			PCIIDENT_TO_DEVNR(p_drv->ntdrv.pciident),
+			PCIIDENT_TO_FUNCNR(p_drv->ntdrv.pciident));
+	}
+
+	rte_spinlock_lock(&hwlock);
+	_g_p_drv[p_drv->adapter_no] = p_drv;
+	rte_spinlock_unlock(&hwlock);
+}
+
+static void clear_pdrv(struct drv_s *p_drv)
+{
+	if (p_drv->adapter_no > NUM_ADAPTER_MAX)
+		return;
+
+	rte_spinlock_lock(&hwlock);
+	_g_p_drv[p_drv->adapter_no] = NULL;
+	rte_spinlock_unlock(&hwlock);
+}
+
+struct drv_s *get_pdrv(uint8_t adapter_no)
+{
+	struct drv_s *pdrv;
+
+	if (adapter_no > NUM_ADAPTER_MAX) {
+		NT_LOG(ERR, ETHDEV,
+			"Internal error adapter number %u out of range. Max number of adapters: %u\n",
+			adapter_no, NUM_ADAPTER_MAX);
+		return NULL;
+	}
+
+	rte_spinlock_lock(&hwlock);
+	pdrv = _g_p_drv[adapter_no];
+	rte_spinlock_unlock(&hwlock);
+	return pdrv;
+}
+
+static struct drv_s *get_pdrv_from_pci(struct rte_pci_addr addr)
+{
+	int i;
+	struct drv_s *p_drv = NULL;
+	rte_spinlock_lock(&hwlock);
+
+	for (i = 0; i < NUM_ADAPTER_MAX; i++) {
+		if (_g_p_drv[i]) {
+			if (PCIIDENT_TO_DOMAIN(_g_p_drv[i]->ntdrv.pciident) == addr.domain &&
+				PCIIDENT_TO_BUSNR(_g_p_drv[i]->ntdrv.pciident) == addr.bus) {
+				p_drv = _g_p_drv[i];
+				break;
+			}
+		}
+	}
+
+	rte_spinlock_unlock(&hwlock);
+	return p_drv;
+}
+
+struct port_link_speed {
+	int port_id;
+	int link_speed;
+};
+
+/* Parse <port>:<link speed Mbps>, e.g 1:10000 */
+static int string_to_port_link_speed(const char *key_str __rte_unused, const char *value_str,
+	void *extra_args)
+{
+	if (!value_str || !extra_args)
+		return -1;
+
+	char *semicol;
+	const uint32_t pid = strtol(value_str, &semicol, 10);
+
+	if (*semicol != ':')
+		return -1;
+
+	const uint32_t lspeed = strtol(++semicol, NULL, 10);
+	struct port_link_speed *pls = *(struct port_link_speed **)extra_args;
+	pls->port_id = pid;
+	pls->link_speed = lspeed;
+	++(*((struct port_link_speed **)(extra_args)));
+	return 0;
+}
+
+/* NOTE: please note the difference between RTE_ETH_SPEED_NUM_xxx and RTE_ETH_LINK_SPEED_xxx */
+static int nt_link_speed_to_eth_speed_num(enum nt_link_speed_e nt_link_speed)
+{
+	int eth_speed_num = RTE_ETH_SPEED_NUM_NONE;
+
+	switch (nt_link_speed) {
+	case NT_LINK_SPEED_10M:
+		eth_speed_num = RTE_ETH_SPEED_NUM_10M;
+		break;
+
+	case NT_LINK_SPEED_100M:
+		eth_speed_num = RTE_ETH_SPEED_NUM_100M;
+		break;
+
+	case NT_LINK_SPEED_1G:
+		eth_speed_num = RTE_ETH_SPEED_NUM_1G;
+		break;
+
+	case NT_LINK_SPEED_10G:
+		eth_speed_num = RTE_ETH_SPEED_NUM_10G;
+		break;
+
+	case NT_LINK_SPEED_25G:
+		eth_speed_num = RTE_ETH_SPEED_NUM_25G;
+		break;
+
+	case NT_LINK_SPEED_40G:
+		eth_speed_num = RTE_ETH_SPEED_NUM_40G;
+		break;
+
+	case NT_LINK_SPEED_50G:
+		eth_speed_num = RTE_ETH_SPEED_NUM_50G;
+		break;
+
+	case NT_LINK_SPEED_100G:
+		eth_speed_num = RTE_ETH_SPEED_NUM_100G;
+		break;
+
+	default:
+		eth_speed_num = RTE_ETH_SPEED_NUM_NONE;
+		break;
+	}
+
+	return eth_speed_num;
+}
+
+static int nt_link_duplex_to_eth_duplex(enum nt_link_duplex_e nt_link_duplex)
+{
+	int eth_link_duplex = 0;
+
+	switch (nt_link_duplex) {
+	case NT_LINK_DUPLEX_FULL:
+		eth_link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
+		break;
+
+	case NT_LINK_DUPLEX_HALF:
+		eth_link_duplex = RTE_ETH_LINK_HALF_DUPLEX;
+		break;
+
+	case NT_LINK_DUPLEX_UNKNOWN:	/* fall-through */
+	default:
+		break;
+	}
+
+	return eth_link_duplex;
+}
+
+static int eth_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete __rte_unused)
+{
+	const struct port_ops *port_ops = get_port_ops();
+
+	if (port_ops == NULL) {
+		NT_LOG(ERR, ETHDEV, "%s: Link management module uninitialized\n", __func__);
+		return -1;
+	}
+
+	struct pmd_internals *internals = (struct pmd_internals *)eth_dev->data->dev_private;
+
+	const int n_intf_no = internals->if_index;
+	struct adapter_info_s *p_adapter_info = &internals->p_drv->ntdrv.adapter_info;
+
+	if (eth_dev->data->dev_started) {
+		if (internals->type == PORT_TYPE_VIRTUAL ||
+			internals->type == PORT_TYPE_OVERRIDE) {
+			eth_dev->data->dev_link.link_status =
+				((internals->vport_comm == VIRT_PORT_NEGOTIATED_NONE)
+					? RTE_ETH_LINK_DOWN
+					: RTE_ETH_LINK_UP);
+			eth_dev->data->dev_link.link_speed = RTE_ETH_SPEED_NUM_NONE;
+			eth_dev->data->dev_link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
+			return 0;
+		}
+
+		const bool port_link_status = port_ops->get_link_status(p_adapter_info, n_intf_no);
+		eth_dev->data->dev_link.link_status =
+			port_link_status ? RTE_ETH_LINK_UP : RTE_ETH_LINK_DOWN;
+
+		nt_link_speed_t port_link_speed =
+			port_ops->get_link_speed(p_adapter_info, n_intf_no);
+		eth_dev->data->dev_link.link_speed =
+			nt_link_speed_to_eth_speed_num(port_link_speed);
+
+		nt_link_duplex_t nt_link_duplex =
+			port_ops->get_link_duplex(p_adapter_info, n_intf_no);
+		eth_dev->data->dev_link.link_duplex = nt_link_duplex_to_eth_duplex(nt_link_duplex);
+
+	} else {
+		eth_dev->data->dev_link.link_status = RTE_ETH_LINK_DOWN;
+		eth_dev->data->dev_link.link_speed = RTE_ETH_SPEED_NUM_NONE;
+		eth_dev->data->dev_link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
+	}
+
+	return 0;
+}
+
+static uint32_t nt_link_speed_capa_to_eth_speed_capa(int nt_link_speed_capa)
+{
+	uint32_t eth_speed_capa = 0;
+
+	if (nt_link_speed_capa & NT_LINK_SPEED_10M)
+		eth_speed_capa |= RTE_ETH_LINK_SPEED_10M;
+
+	if (nt_link_speed_capa & NT_LINK_SPEED_100M)
+		eth_speed_capa |= RTE_ETH_LINK_SPEED_100M;
+
+	if (nt_link_speed_capa & NT_LINK_SPEED_1G)
+		eth_speed_capa |= RTE_ETH_LINK_SPEED_1G;
+
+	if (nt_link_speed_capa & NT_LINK_SPEED_10G)
+		eth_speed_capa |= RTE_ETH_LINK_SPEED_10G;
+
+	if (nt_link_speed_capa & NT_LINK_SPEED_25G)
+		eth_speed_capa |= RTE_ETH_LINK_SPEED_25G;
+
+	if (nt_link_speed_capa & NT_LINK_SPEED_40G)
+		eth_speed_capa |= RTE_ETH_LINK_SPEED_40G;
+
+	if (nt_link_speed_capa & NT_LINK_SPEED_50G)
+		eth_speed_capa |= RTE_ETH_LINK_SPEED_50G;
+
+	if (nt_link_speed_capa & NT_LINK_SPEED_100G)
+		eth_speed_capa |= RTE_ETH_LINK_SPEED_100G;
+
+	return eth_speed_capa;
+}
+
+static int eth_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *dev_info)
+{
+	const struct port_ops *port_ops = get_port_ops();
+
+	if (port_ops == NULL) {
+		NT_LOG(ERR, ETHDEV, "%s: Link management module uninitialized\n", __func__);
+		return -1;
+	}
+
+	struct pmd_internals *internals = (struct pmd_internals *)eth_dev->data->dev_private;
+
+	const int n_intf_no = internals->if_index;
+	struct adapter_info_s *p_adapter_info = &internals->p_drv->ntdrv.adapter_info;
+
+	dev_info->if_index = internals->if_index;
+	dev_info->driver_name = internals->name;
+	dev_info->max_mac_addrs = NUM_MAC_ADDRS_PER_PORT;
+	dev_info->max_rx_pktlen = HW_MAX_PKT_LEN;
+	dev_info->max_mtu = MAX_MTU;
+
+	if (p_adapter_info->fpga_info.profile == FPGA_INFO_PROFILE_INLINE) {
+		dev_info->min_mtu = MIN_MTU_INLINE;
+		dev_info->flow_type_rss_offloads = NT_ETH_RSS_OFFLOAD_MASK;
+		dev_info->hash_key_size = MAX_RSS_KEY_LEN;
+#if (RTE_VERSION_NUM(23, 11, 0, 0) <= RTE_VERSION)
+		dev_info->rss_algo_capa = RTE_ETH_HASH_ALGO_CAPA_MASK(DEFAULT) |
+			RTE_ETH_HASH_ALGO_CAPA_MASK(TOEPLITZ);
+#endif
+
+	} else {
+		dev_info->min_mtu = MIN_MTU;
+		/* NTH10 hashing algorithm for vswitch doesn't use key */
+		dev_info->flow_type_rss_offloads = RTE_ETH_RSS_IP | RTE_ETH_RSS_TCP |
+			RTE_ETH_RSS_UDP | RTE_ETH_RSS_C_VLAN | RTE_ETH_RSS_LEVEL_INNERMOST |
+			RTE_ETH_RSS_L3_SRC_ONLY | RTE_ETH_RSS_LEVEL_OUTERMOST |
+			RTE_ETH_RSS_L3_DST_ONLY;
+		dev_info->hash_key_size = 0;
+#if (RTE_VERSION_NUM(23, 11, 0, 0) <= RTE_VERSION)
+		dev_info->rss_algo_capa = RTE_ETH_HASH_ALGO_CAPA_MASK(DEFAULT);
+#endif
+	}
+
+	if (internals->p_drv) {
+		dev_info->max_rx_queues = internals->nb_rx_queues;
+		dev_info->max_tx_queues = internals->nb_tx_queues;
+
+		dev_info->min_rx_bufsize = 64;
+
+		const uint32_t nt_port_speed_capa =
+			port_ops->get_link_speed_capabilities(p_adapter_info, n_intf_no);
+		dev_info->speed_capa = nt_link_speed_capa_to_eth_speed_capa(nt_port_speed_capa);
+	}
+
+	return 0;
+}
+
+static void eth_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index)
+{
+	struct rte_ether_addr *const eth_addrs = eth_dev->data->mac_addrs;
+
+	assert(index < NUM_MAC_ADDRS_PER_PORT);
+
+	if (index >= NUM_MAC_ADDRS_PER_PORT) {
+		const struct pmd_internals *const internals =
+			(struct pmd_internals *)eth_dev->data->dev_private;
+		NT_LOG(ERR, ETHDEV, "%s: [%s:%i]: Port %i: illegal index %u (>= %u)\n", __FILE__,
+			__func__, __LINE__, internals->if_index, index, NUM_MAC_ADDRS_PER_PORT);
+		return;
+	}
+
+	(void)memset(&eth_addrs[index], 0, sizeof(eth_addrs[index]));
+}
+
+static int eth_mac_addr_add(struct rte_eth_dev *eth_dev,
+	struct rte_ether_addr *mac_addr,
+	uint32_t index,
+	uint32_t vmdq __rte_unused)
+{
+	struct rte_ether_addr *const eth_addrs = eth_dev->data->mac_addrs;
+
+	assert(index < NUM_MAC_ADDRS_PER_PORT);
+
+	if (index >= NUM_MAC_ADDRS_PER_PORT) {
+		const struct pmd_internals *const internals =
+			(struct pmd_internals *)eth_dev->data->dev_private;
+		NT_LOG(ERR, ETHDEV, "%s: [%s:%i]: Port %i: illegal index %u (>= %u)\n", __FILE__,
+			__func__, __LINE__, internals->if_index, index, NUM_MAC_ADDRS_PER_PORT);
+		return -1;
+	}
+
+	eth_addrs[index] = *mac_addr;
+
+	return 0;
+}
+
+static int eth_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr)
+{
+	struct rte_ether_addr *const eth_addrs = dev->data->mac_addrs;
+
+	eth_addrs[0U] = *mac_addr;
+
+	return 0;
+}
+
+static int eth_set_mc_addr_list(struct rte_eth_dev *eth_dev,
+	struct rte_ether_addr *mc_addr_set,
+	uint32_t nb_mc_addr)
+{
+	struct pmd_internals *const internals = (struct pmd_internals *)eth_dev->data->dev_private;
+	struct rte_ether_addr *const mc_addrs = internals->mc_addrs;
+	size_t i;
+
+	if (nb_mc_addr >= NUM_MULTICAST_ADDRS_PER_PORT) {
+		NT_LOG(ERR, ETHDEV,
+			"%s: [%s:%i]: Port %i: too many multicast addresses %u (>= %u)\n", __FILE__,
+			__func__, __LINE__, internals->if_index, nb_mc_addr,
+			NUM_MULTICAST_ADDRS_PER_PORT);
+		return -1;
+	}
+
+	for (i = 0U; i < NUM_MULTICAST_ADDRS_PER_PORT; i++)
+		if (i < nb_mc_addr)
+			mc_addrs[i] = mc_addr_set[i];
+
+		else
+			(void)memset(&mc_addrs[i], 0, sizeof(mc_addrs[i]));
+
+	return 0;
+}
+
+static int eth_dev_configure(struct rte_eth_dev *eth_dev)
+{
+	struct pmd_internals *internals = (struct pmd_internals *)eth_dev->data->dev_private;
+	struct drv_s *p_drv = internals->p_drv;
+
+	NT_LOG(DBG, ETHDEV, "%s: [%s:%u] Called for eth_dev %p\n", __func__, __func__, __LINE__,
+		eth_dev);
+
+	p_drv->probe_finished = 1;
+
+	/* The device is ALWAYS running promiscuous mode. */
+	eth_dev->data->promiscuous ^= ~eth_dev->data->promiscuous;
+	return 0;
+}
+
+static int eth_dev_start(struct rte_eth_dev *eth_dev)
+{
+	const struct port_ops *port_ops = get_port_ops();
+
+	if (port_ops == NULL) {
+		NT_LOG(ERR, ETHDEV, "%s: Link management module uninitialized\n", __func__);
+		return -1;
+	}
+
+	struct pmd_internals *internals = (struct pmd_internals *)eth_dev->data->dev_private;
+
+	const int n_intf_no = internals->if_index;
+	struct adapter_info_s *p_adapter_info = &internals->p_drv->ntdrv.adapter_info;
+
+	NT_LOG(DBG, ETHDEV, "%s: [%s:%u] - Port %u, %u\n", __func__, __func__, __LINE__,
+		internals->n_intf_no, internals->if_index);
+
+	if (internals->type == PORT_TYPE_VIRTUAL || internals->type == PORT_TYPE_OVERRIDE) {
+		eth_dev->data->dev_link.link_status = RTE_ETH_LINK_UP;
+
+	} else {
+		/* Enable the port */
+		port_ops->set_adm_state(p_adapter_info, internals->if_index, true);
+
+		/*
+		 * wait for link on port
+		 * If application starts sending too soon before FPGA port is ready, garbage is
+		 * produced
+		 */
+		int loop = 0;
+
+		while (port_ops->get_link_status(p_adapter_info, n_intf_no) == RTE_ETH_LINK_DOWN) {
+			/* break out after 5 sec */
+			if (++loop >= 50) {
+				NT_LOG(DBG, ETHDEV,
+					"%s: TIMEOUT No link on port %i (5sec timeout)\n", __func__,
+					internals->n_intf_no);
+				break;
+			}
+
+			nt_os_wait_usec(100 * 1000);
+		}
+
+		assert(internals->n_intf_no == internals->if_index);	/* Sanity check */
+
+		if (internals->lpbk_mode) {
+			if (internals->lpbk_mode & 1 << 0) {
+				port_ops->set_loopback_mode(p_adapter_info, n_intf_no,
+					NT_LINK_LOOPBACK_HOST);
+			}
+
+			if (internals->lpbk_mode & 1 << 1) {
+				port_ops->set_loopback_mode(p_adapter_info, n_intf_no,
+					NT_LINK_LOOPBACK_LINE);
+			}
+		}
+	}
+
+	return 0;
+}
+
+static int eth_dev_stop(struct rte_eth_dev *eth_dev)
+{
+	const struct port_ops *port_ops = get_port_ops();
+
+	if (port_ops == NULL) {
+		NT_LOG(ERR, ETHDEV, "%s: Link management module uninitialized\n", __func__);
+		return -1;
+	}
+
+	struct pmd_internals *internals = (struct pmd_internals *)eth_dev->data->dev_private;
+
+	NT_LOG(DBG, ETHDEV, "%s: [%s:%u] - Port %u, %u, type %u\n", __func__, __func__, __LINE__,
+		internals->n_intf_no, internals->if_index, internals->type);
+
+	eth_dev->data->dev_link.link_status = RTE_ETH_LINK_DOWN;
+	return 0;
+}
+
+static int eth_dev_set_link_up(struct rte_eth_dev *eth_dev)
+{
+	const struct port_ops *port_ops = get_port_ops();
+
+	if (port_ops == NULL) {
+		NT_LOG(ERR, ETHDEV, "%s: Link management module uninitialized\n", __func__);
+		return -1;
+	}
+
+	struct pmd_internals *const internals = (struct pmd_internals *)eth_dev->data->dev_private;
+
+	struct adapter_info_s *p_adapter_info = &internals->p_drv->ntdrv.adapter_info;
+	const int port = internals->if_index;
+
+	if (internals->type == PORT_TYPE_VIRTUAL || internals->type == PORT_TYPE_OVERRIDE)
+		return 0;
+
+	assert(port >= 0 && port < NUM_ADAPTER_PORTS_MAX);
+	assert(port == internals->n_intf_no);
+
+	port_ops->set_adm_state(p_adapter_info, port, true);
+
+	return 0;
+}
+
+static int eth_dev_set_link_down(struct rte_eth_dev *eth_dev)
+{
+	const struct port_ops *port_ops = get_port_ops();
+
+	if (port_ops == NULL) {
+		NT_LOG(ERR, ETHDEV, "%s: Link management module uninitialized\n", __func__);
+		return -1;
+	}
+
+	struct pmd_internals *const internals = (struct pmd_internals *)eth_dev->data->dev_private;
+
+	struct adapter_info_s *p_adapter_info = &internals->p_drv->ntdrv.adapter_info;
+	const int port = internals->if_index;
+
+	if (internals->type == PORT_TYPE_VIRTUAL || internals->type == PORT_TYPE_OVERRIDE)
+		return 0;
+
+	assert(port >= 0 && port < NUM_ADAPTER_PORTS_MAX);
+	assert(port == internals->n_intf_no);
+
+	port_ops->set_link_status(p_adapter_info, port, false);
+
+	return 0;
+}
+
+static void drv_deinit(struct drv_s *p_drv)
+{
+	const struct profile_inline_ops *profile_inline_ops = get_profile_inline_ops();
+
+	if (profile_inline_ops == NULL) {
+		NT_LOG(ERR, ETHDEV, "%s: profile_inline module uninitialized\n", __func__);
+		return;
+	}
+
+	const struct adapter_ops *adapter_ops = get_adapter_ops();
+
+	if (adapter_ops == NULL) {
+		NT_LOG(ERR, ETHDEV, "%s: Adapter module uninitialized\n", __func__);
+		return;
+	}
+
+	if (p_drv == NULL)
+		return;
+
+	ntdrv_4ga_t *p_nt_drv = &p_drv->ntdrv;
+
+	/*
+	 * Mark the global pdrv for cleared. Used by some threads to terminate.
+	 * 1 second to give the threads a chance to see the termonation.
+	 */
+	clear_pdrv(p_drv);
+	nt_os_wait_usec(1000000);
+
+	/* stop adapter */
+	adapter_ops->deinit(&p_nt_drv->adapter_info);
+
+	/* clean memory */
+	rte_free(p_drv);
+	p_drv = NULL;
+}
+
+static int eth_dev_close(struct rte_eth_dev *eth_dev)
+{
+	struct pmd_internals *internals = (struct pmd_internals *)eth_dev->data->dev_private;
+	struct drv_s *p_drv = internals->p_drv;
+
+	NT_LOG(DBG, ETHDEV, "%s: enter [%s:%u]\n", __func__, __func__, __LINE__);
+
+	internals->p_drv = NULL;
+
+	/* free */
+	rte_free(internals);
+	internals = NULL;
+	eth_dev->data->dev_private = NULL;
+	eth_dev->data->mac_addrs = NULL;
+
+#if RTE_VERSION_NUM(23, 11, 0, 0) > RTE_VERSION
+	/* release */
+	rte_eth_dev_release_port(eth_dev);
+#endif
+
+	NT_LOG(DBG, ETHDEV, "%s: %d [%s:%u]\n", __func__, p_drv->n_eth_dev_init_count, __func__,
+		__LINE__);
+	/* decrease initialized ethernet devices */
+	p_drv->n_eth_dev_init_count--;
+
+	/*
+	 * rte_pci_dev has no private member for p_drv
+	 * wait until all rte_eth_dev's are closed - then close adapters via p_drv
+	 */
+	if (!p_drv->n_eth_dev_init_count && p_drv) {
+		NT_LOG(DBG, ETHDEV, "%s: %d [%s:%u]\n", __func__, p_drv->n_eth_dev_init_count,
+			__func__, __LINE__);
+		drv_deinit(p_drv);
+	}
+
+	NT_LOG(DBG, ETHDEV, "%s: leave [%s:%u]\n", __func__, __func__, __LINE__);
+	return 0;
+}
+
+static int eth_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version, size_t fw_size)
+{
+	struct pmd_internals *internals = (struct pmd_internals *)eth_dev->data->dev_private;
+
+	if (internals->type == PORT_TYPE_VIRTUAL || internals->type == PORT_TYPE_OVERRIDE)
+		return 0;
+
+	fpga_info_t *fpga_info = &internals->p_drv->ntdrv.adapter_info.fpga_info;
+	const int length = snprintf(fw_version, fw_size, "%03d-%04d-%02d-%02d",
+			fpga_info->n_fpga_type_id, fpga_info->n_fpga_prod_id,
+			fpga_info->n_fpga_ver_id, fpga_info->n_fpga_rev_id);
+
+	if ((size_t)length < fw_size) {
+		/* We have space for the version string */
+		return 0;
+
+	} else {
+		/* We do not have space for the version string -return the needed space */
+		return length + 1;
+	}
+}
+
+static int promiscuous_enable(struct rte_eth_dev __rte_unused(*dev))
+{
+	NT_LOG(DBG, NTHW, "The device always run promiscuous mode.");
+	return 0;
+}
+
+static struct eth_dev_ops nthw_eth_dev_ops = {
+	.dev_configure = eth_dev_configure,
+	.dev_start = eth_dev_start,
+	.dev_stop = eth_dev_stop,
+	.dev_set_link_up = eth_dev_set_link_up,
+	.dev_set_link_down = eth_dev_set_link_down,
+	.dev_close = eth_dev_close,
+	.link_update = eth_link_update,
+	.stats_get = NULL,
+	.stats_reset = NULL,
+	.dev_infos_get = eth_dev_infos_get,
+	.fw_version_get = eth_fw_version_get,
+	.rx_queue_setup = NULL,
+	.rx_queue_start = NULL,
+	.rx_queue_stop = NULL,
+	.rx_queue_release = NULL,
+	.tx_queue_setup = NULL,
+	.tx_queue_start = NULL,
+	.tx_queue_stop = NULL,
+	.tx_queue_release = NULL,
+	.mac_addr_remove = eth_mac_addr_remove,
+	.mac_addr_add = eth_mac_addr_add,
+	.mac_addr_set = eth_mac_addr_set,
+	.set_mc_addr_list = eth_set_mc_addr_list,
+	.xstats_get = NULL,
+	.xstats_get_names = NULL,
+	.xstats_reset = NULL,
+	.xstats_get_by_id = NULL,
+	.xstats_get_names_by_id = NULL,
+	.mtu_set = NULL,
+	.mtr_ops_get = NULL,
+	.flow_ops_get = NULL,
+	.promiscuous_disable = NULL,
+	.promiscuous_enable = promiscuous_enable,
+	.rss_hash_update = NULL,
+	.rss_hash_conf_get = NULL,
+};
+
+/* Converts link speed provided in Mbps to NT specific definitions.*/
+static nt_link_speed_t convert_link_speed(int link_speed_mbps)
+{
+	switch (link_speed_mbps) {
+	case 10:
+		return NT_LINK_SPEED_10M;
+
+	case 100:
+		return NT_LINK_SPEED_100M;
+
+	case 1000:
+		return NT_LINK_SPEED_1G;
+
+	case 10000:
+		return NT_LINK_SPEED_10G;
+
+	case 40000:
+		return NT_LINK_SPEED_40G;
+
+	case 100000:
+		return NT_LINK_SPEED_100G;
+
+	case 50000:
+		return NT_LINK_SPEED_50G;
+
+	case 25000:
+		return NT_LINK_SPEED_25G;
+
+	default:
+		return NT_LINK_SPEED_UNKNOWN;
+	}
+}
+
+static int nthw_pci_dev_init(struct rte_pci_device *pci_dev)
+{
+	const struct flow_filter_ops *flow_filter_ops = get_flow_filter_ops();
+
+	if (flow_filter_ops == NULL) {
+		NT_LOG(ERR, ETHDEV, "%s: flow_filter module uninitialized\n", __func__);
+		/* Return statement is not neccessary here to allow traffic proccesing by SW  */
+	}
+
+	const struct profile_inline_ops *profile_inline_ops = get_profile_inline_ops();
+
+	if (profile_inline_ops == NULL) {
+		NT_LOG(ERR, ETHDEV, "%s: profile_inline module uninitialized\n", __func__);
+		/* Return statement is not neccessary here to allow traffic proccesing by SW  */
+	}
+
+	const struct port_ops *port_ops = get_port_ops();
+
+	if (port_ops == NULL) {
+		NT_LOG(ERR, ETHDEV, "%s: Link management module uninitialized\n", __func__);
+		return -1;
+	}
+
+	const struct adapter_ops *adapter_ops = get_adapter_ops();
+
+	if (adapter_ops == NULL) {
+		NT_LOG(ERR, ETHDEV, "%s: Adapter module uninitialized\n", __func__);
+		return -1;
+	}
+
+	int res;
+	struct drv_s *p_drv;
+	ntdrv_4ga_t *p_nt_drv;
+	fpga_info_t *fpga_info;
+	hw_info_t *p_hw_info;
+	(void)p_hw_info;
+	uint32_t n_port_mask = -1;	/* All ports enabled by default */
+	uint32_t nb_rx_queues = 1;
+	uint32_t nb_tx_queues = 1;
+	uint32_t exception_path = 0;
+	struct flow_queue_id_s queue_ids[FLOW_MAX_QUEUES];
+	int n_phy_ports;
+	struct port_link_speed pls_mbps[NUM_ADAPTER_PORTS_MAX] = { 0 };
+	int num_port_speeds = 0;
+	enum flow_eth_dev_profile profile;
+
+	NT_LOG(DBG, ETHDEV, "Dev %s PF #%i Init : %02x:%02x:%i %s\n", pci_dev->name,
+		pci_dev->addr.function, pci_dev->addr.bus, pci_dev->addr.devid,
+		pci_dev->addr.function, __func__);
+
+	/*
+	 * Process options/arguments
+	 */
+	if (pci_dev->device.devargs && pci_dev->device.devargs->args) {
+		struct rte_kvargs *kvlist =
+			rte_kvargs_parse(pci_dev->device.devargs->args, valid_arguments);
+
+		if (kvlist == NULL)
+			return -1;
+
+		/*
+		 * Argument: help
+		 * NOTE: this argument/option check should be the first as it will stop
+		 * execution after producing its output
+		 */
+		{
+			if (rte_kvargs_get(kvlist, ETH_DEV_NTNIC_HELP_ARG)) {
+				size_t i;
+
+				for (i = 0; i < RTE_DIM(valid_arguments); i++)
+					if (valid_arguments[i] == NULL)
+						break;
+
+				exit(0);
+			}
+		}
+
+		/*
+		 * Argument: supported-fpgas=list|verbose
+		 * NOTE: this argument/option check should be the first as it will stop
+		 * execution after producing its output
+		 */
+		{
+			const char *val_str =
+				rte_kvargs_get(kvlist, ETH_DEV_NTNIC_SUPPORTED_FPGAS_ARG);
+
+			if (val_str != NULL) {
+				int detail_level = 0;
+				nthw_fpga_mgr_t *p_fpga_mgr = NULL;
+
+				if (strcmp(val_str, "list") == 0) {
+					detail_level = 0;
+
+				} else if (strcmp(val_str, "verbose") == 0) {
+					detail_level = 1;
+
+				} else {
+					NT_LOG(ERR, ETHDEV,
+						"%s: argument '%s': '%s': unsupported value\n",
+						__func__, ETH_DEV_NTNIC_SUPPORTED_FPGAS_ARG,
+						val_str);
+					exit(1);
+				}
+
+				/* Produce fpgamgr output and exit hard */
+				p_fpga_mgr = nthw_fpga_mgr_new();
+
+				if (p_fpga_mgr) {
+					nthw_fpga_mgr_init(p_fpga_mgr, nthw_fpga_instances, NULL);
+					nthw_fpga_mgr_show(p_fpga_mgr, stdout, detail_level);
+					nthw_fpga_mgr_delete(p_fpga_mgr);
+					p_fpga_mgr = NULL;
+
+				} else {
+					NT_LOG(ERR, ETHDEV, "%s: %s cannot complete\n", __func__,
+						ETH_DEV_NTNIC_SUPPORTED_FPGAS_ARG);
+					exit(1);
+				}
+
+				exit(0);
+			}
+		}
+
+		/* link_speed options/argument only applicable for physical ports. */
+		num_port_speeds = rte_kvargs_count(kvlist, ETH_DEV_NTHW_LINK_SPEED_ARG);
+
+		if (num_port_speeds != 0) {
+			assert(num_port_speeds <= NUM_ADAPTER_PORTS_MAX);
+			void *pls_mbps_ptr = &pls_mbps[0];
+			res = rte_kvargs_process(kvlist, ETH_DEV_NTHW_LINK_SPEED_ARG,
+					&string_to_port_link_speed, &pls_mbps_ptr);
+
+			if (res < 0) {
+				NT_LOG(ERR, ETHDEV,
+					"%s: problem with port link speed command line arguments: res=%d\n",
+					__func__, res);
+				return -1;
+			}
+
+			for (int i = 0; i < num_port_speeds; ++i) {
+				int pid = pls_mbps[i].port_id;
+				int lspeed = pls_mbps[i].link_speed;
+				(void)lspeed;
+				NT_LOG(DBG, ETHDEV, "%s: devargs: %s=%d.%d\n", __func__,
+					ETH_DEV_NTHW_LINK_SPEED_ARG, pid, lspeed);
+
+				if (pls_mbps[i].port_id >= NUM_ADAPTER_PORTS_MAX) {
+					NT_LOG(ERR, ETHDEV,
+						"%s: problem with port link speed command line arguments: port id should be 0 to %d, got %d\n",
+						__func__, NUM_ADAPTER_PORTS_MAX, pid);
+					return -1;
+				}
+			}
+		}
+	}
+
+	/* alloc */
+	p_drv = rte_zmalloc_socket(pci_dev->name, sizeof(struct drv_s), RTE_CACHE_LINE_SIZE,
+			pci_dev->device.numa_node);
+
+	if (!p_drv) {
+		NT_LOG(ERR, ETHDEV, "%s: error %d (%s:%u)\n",
+			(pci_dev->name[0] ? pci_dev->name : "NA"), -1, __func__, __LINE__);
+		return -1;
+	}
+
+	/* Setup VFIO context */
+	int vfio = nt_vfio_setup(pci_dev);
+
+	if (vfio < 0) {
+		NT_LOG(ERR, ETHDEV, "%s: vfio_setup error %d (%s:%u)\n",
+			(pci_dev->name[0] ? pci_dev->name : "NA"), -1, __func__, __LINE__);
+		rte_free(p_drv);
+		return -1;
+	}
+
+	/* context */
+	p_nt_drv = &p_drv->ntdrv;
+	fpga_info = &p_nt_drv->adapter_info.fpga_info;
+	p_hw_info = &p_nt_drv->adapter_info.hw_info;
+
+	p_drv->p_dev = pci_dev;
+
+	/* Set context for NtDrv */
+	p_nt_drv->pciident = BDF_TO_PCIIDENT(pci_dev->addr.domain, pci_dev->addr.bus,
+			pci_dev->addr.devid, pci_dev->addr.function);
+	p_nt_drv->adapter_info.n_rx_host_buffers = nb_rx_queues;
+	p_nt_drv->adapter_info.n_tx_host_buffers = nb_tx_queues;
+
+	fpga_info->bar0_addr = (void *)pci_dev->mem_resource[0].addr;
+	fpga_info->bar0_size = pci_dev->mem_resource[0].len;
+	NT_LOG(DBG, ETHDEV, "bar0=0x%" PRIX64 " len=%d\n", fpga_info->bar0_addr,
+		fpga_info->bar0_size);
+	fpga_info->numa_node = pci_dev->device.numa_node;
+	fpga_info->pciident = p_nt_drv->pciident;
+	fpga_info->adapter_no = p_drv->adapter_no;
+
+	p_nt_drv->adapter_info.hw_info.pci_class_id = pci_dev->id.class_id;
+	p_nt_drv->adapter_info.hw_info.pci_vendor_id = pci_dev->id.vendor_id;
+	p_nt_drv->adapter_info.hw_info.pci_device_id = pci_dev->id.device_id;
+	p_nt_drv->adapter_info.hw_info.pci_sub_vendor_id = pci_dev->id.subsystem_vendor_id;
+	p_nt_drv->adapter_info.hw_info.pci_sub_device_id = pci_dev->id.subsystem_device_id;
+
+	NT_LOG(DBG, ETHDEV, "%s: " PCIIDENT_PRINT_STR " %04X:%04X: %04X:%04X:\n",
+		p_nt_drv->adapter_info.mp_adapter_id_str, PCIIDENT_TO_DOMAIN(p_nt_drv->pciident),
+		PCIIDENT_TO_BUSNR(p_nt_drv->pciident), PCIIDENT_TO_DEVNR(p_nt_drv->pciident),
+		PCIIDENT_TO_FUNCNR(p_nt_drv->pciident),
+		p_nt_drv->adapter_info.hw_info.pci_vendor_id,
+		p_nt_drv->adapter_info.hw_info.pci_device_id,
+		p_nt_drv->adapter_info.hw_info.pci_sub_vendor_id,
+		p_nt_drv->adapter_info.hw_info.pci_sub_device_id);
+
+	p_nt_drv->b_shutdown = false;
+	p_nt_drv->adapter_info.pb_shutdown = &p_nt_drv->b_shutdown;
+
+	for (int i = 0; i < num_port_speeds; ++i) {
+		struct adapter_info_s *p_adapter_info = &p_nt_drv->adapter_info;
+		nt_link_speed_t link_speed = convert_link_speed(pls_mbps[i].link_speed);
+		port_ops->set_link_speed(p_adapter_info, i, link_speed);
+	}
+
+	/* store context */
+	store_pdrv(p_drv);
+
+	/* initialize nt4ga nthw fpga module instance in drv */
+	int err = adapter_ops->init(&p_nt_drv->adapter_info);
+
+	if (err != 0) {
+		NT_LOG(ERR, ETHDEV, "%s: Cannot initialize the adapter instance\n",
+			p_nt_drv->adapter_info.mp_adapter_id_str);
+		return -1;
+	}
+
+	const struct meter_ops_s *meter_ops = get_meter_ops();
+
+	if (meter_ops != NULL)
+		nthw_eth_dev_ops.mtr_ops_get = meter_ops->eth_mtr_ops_get;
+
+	else
+		NT_LOG(DBG, ETHDEV, "%s: Meter module is not initialized\n", __func__);
+
+	/* Initialize the queue system */
+	if (err == 0) {
+		sg_ops = get_sg_ops();
+
+		if (sg_ops != NULL) {
+			err = sg_ops->nthw_virt_queue_init(fpga_info);
+
+			if (err != 0) {
+				NT_LOG(ERR, ETHDEV,
+					"%s: Cannot initialize scatter-gather queues\n",
+					p_nt_drv->adapter_info.mp_adapter_id_str);
+
+			} else {
+				NT_LOG(DBG, ETHDEV, "%s: Initialized scatter-gather queues\n",
+					p_nt_drv->adapter_info.mp_adapter_id_str);
+			}
+
+		} else {
+			NT_LOG(DBG, ETHDEV, "%s: SG module is not initialized\n", __func__);
+		}
+	}
+
+	switch (fpga_info->profile) {
+	case FPGA_INFO_PROFILE_VSWITCH:
+		profile = FLOW_ETH_DEV_PROFILE_VSWITCH;
+		break;
+
+	case FPGA_INFO_PROFILE_INLINE:
+		profile = FLOW_ETH_DEV_PROFILE_INLINE;
+		break;
+
+	case FPGA_INFO_PROFILE_UNKNOWN:
+
+	/* fallthrough */
+	case FPGA_INFO_PROFILE_CAPTURE:
+
+	/* fallthrough */
+	default:
+		NT_LOG(ERR, ETHDEV, "%s: fpga profile not supported [%s:%u]\n",
+			(pci_dev->name[0] ? pci_dev->name : "NA"), __func__, __LINE__);
+		return -1;
+	}
+
+#if defined(DEBUG_REG_ACCESS) && (DEBUG_REG_ACCESS)
+	{
+		int res;
+		NT_LOG(DBG, ETHDEV, "%s: DEBUG_REG_ACCESS: [%s:%u]\n", __func__, __func__,
+			__LINE__);
+		res = THREAD_CTRL_CREATE(&p_nt_drv->stat_thread, "reg_acc_thr",
+				nthw_debug_reg_access_thread_fn, (void *)fpga_info);
+
+		if (res) {
+			NT_LOG(ERR, ETHDEV, "%s: error=%d [%s:%u]\n",
+				(pci_dev->name[0] ? pci_dev->name : "NA"), res, __func__, __LINE__);
+			return -1;
+		}
+	}
+#endif	/* DEBUG_REG_ACCESS */
+
+	/* Start ctrl, monitor, stat thread only for primary process. */
+	if (err == 0) {
+		/* mp_adapter_id_str is initialized after nt4ga_adapter_init(p_nt_drv) */
+		const char *const p_adapter_id_str = p_nt_drv->adapter_info.mp_adapter_id_str;
+		(void)p_adapter_id_str;
+		NT_LOG(DBG, ETHDEV,
+			"%s: %s: AdapterPCI=" PCIIDENT_PRINT_STR " Hw=0x%02X_rev%d PhyPorts=%d\n",
+			(pci_dev->name[0] ? pci_dev->name : "NA"), p_adapter_id_str,
+			PCIIDENT_TO_DOMAIN(p_nt_drv->adapter_info.fpga_info.pciident),
+			PCIIDENT_TO_BUSNR(p_nt_drv->adapter_info.fpga_info.pciident),
+			PCIIDENT_TO_DEVNR(p_nt_drv->adapter_info.fpga_info.pciident),
+			PCIIDENT_TO_FUNCNR(p_nt_drv->adapter_info.fpga_info.pciident),
+			p_hw_info->hw_platform_id, fpga_info->nthw_hw_info.hw_id,
+			fpga_info->n_phy_ports);
+
+	} else {
+		NT_LOG(ERR, ETHDEV, "%s: error=%d [%s:%u]\n",
+			(pci_dev->name[0] ? pci_dev->name : "NA"), err, __func__, __LINE__);
+		return -1;
+	}
+
+	n_phy_ports = fpga_info->n_phy_ports;
+
+	for (int n_intf_no = 0; n_intf_no < n_phy_ports; n_intf_no++) {
+		const char *const p_port_id_str = p_nt_drv->adapter_info.mp_port_id_str[n_intf_no];
+		(void)p_port_id_str;
+		struct pmd_internals *internals = NULL;
+		struct rte_eth_dev *eth_dev = NULL;
+		char name[32];
+		int i;
+
+		if ((1 << n_intf_no) & ~n_port_mask) {
+			NT_LOG(DBG, ETHDEV,
+				"%s: %s: interface #%d: skipping due to portmask 0x%02X\n",
+				__func__, p_port_id_str, n_intf_no, n_port_mask);
+			continue;
+		}
+
+		snprintf(name, sizeof(name), "ntnic%d", n_intf_no);
+		NT_LOG(DBG, ETHDEV, "%s: %s: interface #%d: %s: '%s'\n", __func__, p_port_id_str,
+			n_intf_no, (pci_dev->name[0] ? pci_dev->name : "NA"), name);
+
+		internals = rte_zmalloc_socket(name, sizeof(struct pmd_internals),
+				RTE_CACHE_LINE_SIZE, pci_dev->device.numa_node);
+
+		if (!internals) {
+			NT_LOG(ERR, ETHDEV, "%s: %s: error=%d [%s:%u]\n",
+				(pci_dev->name[0] ? pci_dev->name : "NA"), name, -1, __func__,
+				__LINE__);
+			return -1;
+		}
+
+		internals->pci_dev = pci_dev;
+		internals->n_intf_no = n_intf_no;
+		internals->if_index = n_intf_no;
+		internals->min_tx_pkt_size = 64;
+		internals->max_tx_pkt_size = 10000;
+		internals->type = PORT_TYPE_PHYSICAL;
+		internals->vhid = -1;
+		internals->port = n_intf_no;
+		internals->nb_rx_queues = nb_rx_queues;
+		internals->nb_tx_queues = nb_tx_queues;
+
+		/* Not used queue index as dest port in bypass - use 0x80 + port nr */
+		for (i = 0; i < MAX_QUEUES; i++)
+			internals->vpq[i].hw_id = -1;
+
+		/* Setup queue_ids */
+		if (nb_rx_queues > 1) {
+			NT_LOG(DBG, ETHDEV,
+				"(%i) NTNIC configured with Rx multi queues. %i queues\n",
+				0 /*port*/, nb_rx_queues);
+		}
+
+		if (nb_tx_queues > 1) {
+			NT_LOG(DBG, ETHDEV,
+				"(%i) NTNIC configured with Tx multi queues. %i queues\n",
+				0 /*port*/, nb_tx_queues);
+		}
+
+		/* Set MAC address (but only if the MAC address is permitted) */
+		if (n_intf_no < fpga_info->nthw_hw_info.vpd_info.mn_mac_addr_count) {
+			const uint64_t mac =
+				fpga_info->nthw_hw_info.vpd_info.mn_mac_addr_value + n_intf_no;
+			internals->eth_addrs[0].addr_bytes[0] = (mac >> 40) & 0xFFu;
+			internals->eth_addrs[0].addr_bytes[1] = (mac >> 32) & 0xFFu;
+			internals->eth_addrs[0].addr_bytes[2] = (mac >> 24) & 0xFFu;
+			internals->eth_addrs[0].addr_bytes[3] = (mac >> 16) & 0xFFu;
+			internals->eth_addrs[0].addr_bytes[4] = (mac >> 8) & 0xFFu;
+			internals->eth_addrs[0].addr_bytes[5] = (mac >> 0) & 0xFFu;
+		}
+
+		eth_dev = rte_eth_dev_allocate(name);	/* TODO: name */
+
+		if (!eth_dev) {
+			NT_LOG(ERR, ETHDEV, "%s: %s: error=%d [%s:%u]\n",
+				(pci_dev->name[0] ? pci_dev->name : "NA"), name, -1, __func__,
+				__LINE__);
+			return -1;
+		}
+
+		if (flow_filter_ops != NULL) {
+			int *rss_target_id = &internals->txq_scg[0].rss_target_id;
+			internals->flw_dev =
+				flow_filter_ops->flow_get_eth_dev(0, n_intf_no,
+					eth_dev->data->port_id,
+					nb_rx_queues, queue_ids,
+					rss_target_id, profile,
+					exception_path);
+
+			if (!internals->flw_dev) {
+				NT_LOG(ERR, VDPA,
+					"Error creating port. Resource exhaustion in HW\n");
+				return -1;
+			}
+		}
+
+		NT_LOG(DBG, ETHDEV, "%s: [%s:%u] eth_dev %p, port_id %u, if_index %u\n", __func__,
+			__func__, __LINE__, eth_dev, eth_dev->data->port_id, n_intf_no);
+
+		/* connect structs */
+		internals->p_drv = p_drv;
+		eth_dev->data->dev_private = internals;
+		eth_dev->data->mac_addrs = internals->eth_addrs;
+
+		internals->port_id = eth_dev->data->port_id;
+
+		struct rte_eth_link pmd_link;
+		pmd_link.link_speed = RTE_ETH_SPEED_NUM_NONE;
+		pmd_link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
+		pmd_link.link_status = RTE_ETH_LINK_DOWN;
+		pmd_link.link_autoneg = RTE_ETH_LINK_AUTONEG;
+
+		eth_dev->device = &pci_dev->device;
+		eth_dev->data->dev_link = pmd_link;
+		eth_dev->data->numa_node = pci_dev->device.numa_node;
+		eth_dev->dev_ops = &nthw_eth_dev_ops;
+		eth_dev->state = RTE_ETH_DEV_ATTACHED;
+
+		rte_eth_copy_pci_info(eth_dev, pci_dev);
+		/* performs rte_eth_copy_pci_info() */
+		eth_dev_pci_specific_init(eth_dev, pci_dev);
+
+		/* increase initialized ethernet devices - PF */
+		p_drv->n_eth_dev_init_count++;
+	}
+
+	p_drv->setup_finished = 1;
+
+	return 0;
+}
+
+static int nthw_pci_dev_deinit(struct rte_eth_dev *eth_dev __rte_unused)
+{
+	NT_LOG(DBG, ETHDEV, "PCI device deinitialization %s\n", __func__);
+
+	if (sg_ops == NULL) {
+		nt_vfio_remove(EXCEPTION_PATH_HID);
+		return 0;
+	}
+
+	return 0;
+}
+
+static void signal_handler_func_int(int sig)
+{
+	if (sig != SIGINT) {
+		signal(sig, previous_handler);
+		raise(sig);
+		return;
+	}
+
+	kill_pmd = 1;
+}
+
+THREAD_FUNC shutdown_thread(void *arg __rte_unused)
+{
+	struct rte_eth_dev dummy;
+
+	while (!kill_pmd)
+		nt_os_wait_usec(100 * 1000);
+
+	NT_LOG(DBG, ETHDEV, "%s: Shutting down because of ctrl+C\n", __func__);
+	nthw_pci_dev_deinit(&dummy);
+
+	signal(SIGINT, previous_handler);
+	raise(SIGINT);
+
+	return THREAD_RETURN;
+}
+
+static int init_shutdown(void)
+{
+	NT_LOG(DBG, ETHDEV, "%s: Starting shutdown handler\n", __func__);
+	kill_pmd = 0;
+	previous_handler = signal(SIGINT, signal_handler_func_int);
+	THREAD_CREATE(&shutdown_tid, shutdown_thread, NULL);
+
+	/*
+	 * 1 time calculation of 1 sec stat update rtc cycles to prevent stat poll
+	 * flooding by OVS from multiple virtual port threads - no need to be precise
+	 */
+	uint64_t now_rtc = rte_get_tsc_cycles();
+	nt_os_wait_usec(10 * 1000);
+	rte_tsc_freq = 100 * (rte_get_tsc_cycles() - now_rtc);
+
+	return 0;
+}
+
+static int nthw_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
+	struct rte_pci_device *pci_dev)
+{
+	int res;
+
+#if defined(DEBUG)
+	NT_LOG(DBG, NTHW, "Testing NTHW %u [%s:%u]\n",
+		nt_log_module_logtype[NT_LOG_MODULE_INDEX(NT_LOG_MODULE_NTHW)], __func__, __LINE__);
+#endif
+
+	NT_LOG(DBG, ETHDEV, "%s: pcidev: name: '%s'\n", __func__, pci_dev->name);
+	NT_LOG(DBG, ETHDEV, "%s: devargs: name: '%s'\n", __func__, pci_dev->device.name);
+
+	if (pci_dev->device.devargs) {
+		NT_LOG(DBG, ETHDEV, "%s: devargs: args: '%s'\n", __func__,
+			(pci_dev->device.devargs->args ? pci_dev->device.devargs->args : "NULL"));
+		NT_LOG(DBG, ETHDEV, "%s: devargs: data: '%s'\n", __func__,
+			(pci_dev->device.devargs->data ? pci_dev->device.devargs->data : "NULL"));
+	}
+
+	const int n_rte_has_pci = rte_eal_has_pci();
+	NT_LOG(DBG, ETHDEV, "has_pci=%d\n", n_rte_has_pci);
+
+	if (n_rte_has_pci == 0) {
+		NT_LOG(ERR, ETHDEV, "has_pci=%d: this PMD needs hugepages\n", n_rte_has_pci);
+		return -1;
+	}
+
+	const int n_rte_vfio_no_io_mmu_enabled = rte_vfio_noiommu_is_enabled();
+	NT_LOG(DBG, ETHDEV, "vfio_no_iommu_enabled=%d\n", n_rte_vfio_no_io_mmu_enabled);
+
+	if (n_rte_vfio_no_io_mmu_enabled) {
+		NT_LOG(ERR, ETHDEV, "vfio_no_iommu_enabled=%d: this PMD needs VFIO IOMMU\n",
+			n_rte_vfio_no_io_mmu_enabled);
+		return -1;
+	}
+
+	const enum rte_iova_mode n_rte_io_va_mode = rte_eal_iova_mode();
+	NT_LOG(DBG, ETHDEV, "iova mode=%d\n", n_rte_io_va_mode);
+
+	if (n_rte_io_va_mode != RTE_IOVA_PA) {
+		NT_LOG(WRN, ETHDEV, "iova mode (%d) should be PA for performance reasons\n",
+			n_rte_io_va_mode);
+	}
+
+	const int n_rte_has_huge_pages = rte_eal_has_hugepages();
+	NT_LOG(DBG, ETHDEV, "has_hugepages=%d\n", n_rte_has_huge_pages);
+
+	if (n_rte_has_huge_pages == 0) {
+		NT_LOG(ERR, ETHDEV, "has_hugepages=%d: this PMD needs hugepages\n",
+			n_rte_has_huge_pages);
+		return -1;
+	}
+
+	NT_LOG(DBG, ETHDEV,
+		"busid=" PCI_PRI_FMT
+		" pciid=%04x:%04x_%04x:%04x locstr=%s @ numanode=%d: drv=%s drvalias=%s\n",
+		pci_dev->addr.domain, pci_dev->addr.bus, pci_dev->addr.devid,
+		pci_dev->addr.function, pci_dev->id.vendor_id, pci_dev->id.device_id,
+		pci_dev->id.subsystem_vendor_id, pci_dev->id.subsystem_device_id,
+		pci_dev->name[0] ? pci_dev->name : "NA",	/* locstr */
+		pci_dev->device.numa_node,
+		pci_dev->driver->driver.name ? pci_dev->driver->driver.name : "NA",
+		pci_dev->driver->driver.alias ? pci_dev->driver->driver.alias : "NA");
+
+	if (pci_dev->id.vendor_id == NT_HW_PCI_VENDOR_ID) {
+		if (pci_dev->id.device_id == NT_HW_PCI_DEVICE_ID_NT200A01 ||
+			pci_dev->id.device_id == NT_HW_PCI_DEVICE_ID_NT50B01) {
+			if (pci_dev->id.subsystem_device_id != 0x01) {
+				NT_LOG(DBG, ETHDEV,
+					"%s: PCIe bifurcation - secondary endpoint found - leaving probe\n",
+					__func__);
+				return -1;
+			}
+		}
+	}
+
+	res = nthw_pci_dev_init(pci_dev);
+
+	init_shutdown();
+
+	NT_LOG(DBG, ETHDEV, "%s: leave: res=%d\n", __func__, res);
+	return res;
+}
+
+static int nthw_pci_remove(struct rte_pci_device *pci_dev)
+{
+	NT_LOG(DBG, ETHDEV, "%s: [%s:%u]\n", __func__, __func__, __LINE__);
+
+	struct drv_s *p_drv = get_pdrv_from_pci(pci_dev->addr);
+	drv_deinit(p_drv);
+
+	return rte_eth_dev_pci_generic_remove(pci_dev, nthw_pci_dev_deinit);
+}
+
+static int nt_log_init_impl(void)
+{
+	rte_log_set_global_level(RTE_LOG_DEBUG);
+
+	NT_LOG(DBG, ETHDEV, "%s: [%s:%u]\n", __func__, __func__, __LINE__);
+
+	for (int i = NT_LOG_MODULE_GENERAL; i < NT_LOG_MODULE_END; ++i) {
+		int index = NT_LOG_MODULE_INDEX(i);
+		nt_log_module_logtype[index] =
+			rte_log_register_type_and_pick_level(nt_log_module_eal_name[index],
+				RTE_LOG_INFO);
+	}
+
+	NT_LOG(DBG, ETHDEV, "%s: [%s:%u]\n", __func__, __func__, __LINE__);
+
+	return 0;
+}
+
+static int nt_log_log_impl(enum nt_log_level level, uint32_t module, const char *format,
+	va_list args)
+{
+	uint32_t rte_level = 0;
+	uint32_t rte_module = 0;
+
+	switch (level) {
+	case NT_LOG_ERR:
+		rte_level = RTE_LOG_ERR;
+		break;
+
+	case NT_LOG_WRN:
+		rte_level = RTE_LOG_WARNING;
+		break;
+
+	case NT_LOG_INF:
+		rte_level = RTE_LOG_INFO;
+		break;
+
+	default:
+		rte_level = RTE_LOG_DEBUG;
+	}
+
+	rte_module = (module >= NT_LOG_MODULE_GENERAL && module < NT_LOG_MODULE_END)
+		? (uint32_t)nt_log_module_logtype[NT_LOG_MODULE_INDEX(module)]
+		: module;
+
+	return (int)rte_vlog(rte_level, rte_module, format, args);
+}
+
+static int nt_log_is_debug_impl(uint32_t module)
+{
+	if (module < NT_LOG_MODULE_GENERAL || module >= NT_LOG_MODULE_END)
+		return -1;
+
+	int index = NT_LOG_MODULE_INDEX(module);
+	return rte_log_get_level(nt_log_module_logtype[index]) == RTE_LOG_DEBUG;
+}
+
+RTE_INIT(ntnic_rte_init);	/* must go before function */
+
+static void ntnic_rte_init(void)
+{
+	static struct nt_log_impl impl = { .init = &nt_log_init_impl,
+		       .log = &nt_log_log_impl,
+		       .is_debug = &nt_log_is_debug_impl
+	};
+
+	nt_log_init(&impl);
+}
+
+static struct rte_pci_driver rte_nthw_pmd = {
+	.driver = {
+		.name = "net_ntnic",
+	},
+
+	.id_table = nthw_pci_id_map,
+	.drv_flags = RTE_PCI_DRV_NEED_MAPPING,
+	.probe = nthw_pci_probe,
+	.remove = nthw_pci_remove,
+};
+
+RTE_PMD_REGISTER_PCI(net_ntnic, rte_nthw_pmd);
+RTE_PMD_REGISTER_PCI_TABLE(net_ntnic, nthw_pci_id_map);
+RTE_PMD_REGISTER_KMOD_DEP(net_ntnic, "* vfio-pci");
+
+static inline const char *_rte_vdev_device_name(const struct rte_pci_device *dev)
+{
+	if (dev && dev->device.name)
+		return dev->device.name;
+
+	return NULL;
+}
+
+/*
+ * Necessary for satisfying version.map
+ * requirement for both 21.11 and 22.11
+ */
+void _dummy_(void);
+void _dummy_(void) {}
diff --git a/drivers/net/ntnic/ntnic_ethdev.h b/drivers/net/ntnic/ntnic_ethdev.h
new file mode 100644
index 0000000000..c82070e9de
--- /dev/null
+++ b/drivers/net/ntnic/ntnic_ethdev.h
@@ -0,0 +1,32 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef __NTNIC_ETHDEV_H__
+#define __NTNIC_ETHDEV_H__
+
+#include <rte_ether.h>
+#include <rte_version.h>/* RTE_VERSION, RTE_VERSION_NUM */
+#include <rte_mbuf.h>
+#include <rte_pci.h>
+#include <ethdev_pci.h>
+
+#include "ntos_drv.h"
+#include "ntos_system.h"
+#include "ntoss_virt_queue.h"
+#include "ntnic_stat.h"
+#include "nt_util.h"
+#include "stream_binary_flow_api.h"
+
+/* Total max ports per NT NFV NIC */
+#define MAX_NTNIC_PORTS 2
+
+/* Functions: */
+struct drv_s *get_pdrv(uint8_t adapter_no);
+
+extern uint64_t rte_tsc_freq;
+extern rte_spinlock_t hwlock;
+
+
+#endif	/* __NTNIC_ETHDEV_H__ */
diff --git a/drivers/net/ntnic/rte_pmd_ntnic.h b/drivers/net/ntnic/rte_pmd_ntnic.h
new file mode 100644
index 0000000000..e3dd143fb9
--- /dev/null
+++ b/drivers/net/ntnic/rte_pmd_ntnic.h
@@ -0,0 +1,43 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef NTNIC_EVENT_H_
+#define NTNIC_EVENT_H_
+
+#include <rte_ethdev.h>
+
+typedef struct ntnic_flm_load_s {
+	uint64_t lookup;
+	uint64_t lookup_maximum;
+	uint64_t access;
+	uint64_t access_maximum;
+} ntnic_flm_load_t;
+
+typedef struct ntnic_port_load_s {
+	uint64_t rx_pps;
+	uint64_t rx_pps_maximum;
+	uint64_t tx_pps;
+	uint64_t tx_pps_maximum;
+	uint64_t rx_bps;
+	uint64_t rx_bps_maximum;
+	uint64_t tx_bps;
+	uint64_t tx_bps_maximum;
+} ntnic_port_load_t;
+
+struct ntnic_flm_stats_s {
+	uint64_t bytes;
+	uint64_t packets;
+	uint64_t timestamp;
+	uint64_t id;
+	uint8_t cause;
+};
+
+enum rte_ntnic_event_type {
+	RTE_NTNIC_FLM_LOAD_EVENT = RTE_ETH_EVENT_MAX,
+	RTE_NTNIC_PORT_LOAD_EVENT,
+	RTE_NTNIC_FLM_STATS_EVENT,
+};
+
+#endif	/* NTNIC_EVENT_H_ */
-- 
2.44.0


^ permalink raw reply	[flat|nested] 238+ messages in thread

* [PATCH v1 12/17] net/ntnic: add support of the NT200A0X smartNIC
  2024-05-30 14:48 [PATCH v1 01/17] net/ntnic: Add registers for NapaTech SmartNiC Serhii Iliushyk
                   ` (9 preceding siblings ...)
  2024-05-30 14:49 ` [PATCH v1 11/17] net/ntnic: add ethdev and makes PMD available Serhii Iliushyk
@ 2024-05-30 14:49 ` Serhii Iliushyk
  2024-05-30 14:49 ` [PATCH v1 13/17] net/ntnic: add adapter initialization Serhii Iliushyk
                   ` (13 subsequent siblings)
  24 siblings, 0 replies; 238+ messages in thread
From: Serhii Iliushyk @ 2024-05-30 14:49 UTC (permalink / raw)
  To: dev; +Cc: mko-plv, ckm, andrew.rybchenko, ferruh.yigit

Add ntnic support for NT200A0X NIC

* Reset

* Clock profiles

* FPGA Registers

* API for FPGA registers

Signed-off-by: Serhii Iliushyk <sil-plv@napatech.com>
---
 .../NT200A02_U23_Si5340_adr0_v5-Registers.h   |  752 +++++++++++
 drivers/net/ntnic/meson.build                 |   16 +
 .../clock_profiles/nthw_fpga_clk9563.c        |   51 +
 .../clock_profiles/nthw_fpga_clk9563.h        |    9 +
 .../nthw/core/nt200a0x/nthw_fpga_nt200a0x.c   |  107 ++
 .../nthw/core/nt200a0x/nthw_fpga_nt200a0x.h   |    9 +
 .../core/nt200a0x/reset/nthw_fpga_rst9563.c   |  258 ++++
 .../core/nt200a0x/reset/nthw_fpga_rst9563.h   |    9 +
 .../nt200a0x/reset/nthw_fpga_rst_nt200a0x.c   |  729 ++++++++++
 .../nt200a0x/reset/nthw_fpga_rst_nt200a0x.h   |    9 +
 drivers/net/ntnic/nthw/core/nthw_fpga.c       |  888 +++++++++++++
 drivers/net/ntnic/nthw/core/nthw_fpga_rst.c   |   10 +
 drivers/net/ntnic/nthw/core/nthw_hif.c        |  312 +++++
 drivers/net/ntnic/nthw/core/nthw_iic.c        |  529 ++++++++
 .../net/ntnic/nthw/core/nthw_mac_pcs_xxv.c    | 1169 +++++++++++++++++
 drivers/net/ntnic/nthw/core/nthw_pcie3.c      |  270 ++++
 drivers/net/ntnic/nthw/core/nthw_sdc.c        |  176 +++
 drivers/net/ntnic/nthw/core/nthw_si5340.c     |  205 +++
 drivers/net/ntnic/nthw/core/nthw_spi_v3.c     |  356 +++++
 drivers/net/ntnic/nthw/core/nthw_spim.c       |  121 ++
 drivers/net/ntnic/nthw/core/nthw_spis.c       |  129 ++
 drivers/net/ntnic/nthw/core/nthw_tsm.c        |  167 +++
 22 files changed, 6281 insertions(+)
 create mode 100644 drivers/net/ntnic/include/NT200A02_U23_Si5340_adr0_v5-Registers.h
 create mode 100644 drivers/net/ntnic/nthw/core/nt200a0x/clock_profiles/nthw_fpga_clk9563.c
 create mode 100644 drivers/net/ntnic/nthw/core/nt200a0x/clock_profiles/nthw_fpga_clk9563.h
 create mode 100644 drivers/net/ntnic/nthw/core/nt200a0x/nthw_fpga_nt200a0x.c
 create mode 100644 drivers/net/ntnic/nthw/core/nt200a0x/nthw_fpga_nt200a0x.h
 create mode 100644 drivers/net/ntnic/nthw/core/nt200a0x/reset/nthw_fpga_rst9563.c
 create mode 100644 drivers/net/ntnic/nthw/core/nt200a0x/reset/nthw_fpga_rst9563.h
 create mode 100644 drivers/net/ntnic/nthw/core/nt200a0x/reset/nthw_fpga_rst_nt200a0x.c
 create mode 100644 drivers/net/ntnic/nthw/core/nt200a0x/reset/nthw_fpga_rst_nt200a0x.h
 create mode 100644 drivers/net/ntnic/nthw/core/nthw_fpga.c
 create mode 100644 drivers/net/ntnic/nthw/core/nthw_fpga_rst.c
 create mode 100644 drivers/net/ntnic/nthw/core/nthw_hif.c
 create mode 100644 drivers/net/ntnic/nthw/core/nthw_iic.c
 create mode 100644 drivers/net/ntnic/nthw/core/nthw_mac_pcs_xxv.c
 create mode 100644 drivers/net/ntnic/nthw/core/nthw_pcie3.c
 create mode 100644 drivers/net/ntnic/nthw/core/nthw_sdc.c
 create mode 100644 drivers/net/ntnic/nthw/core/nthw_si5340.c
 create mode 100644 drivers/net/ntnic/nthw/core/nthw_spi_v3.c
 create mode 100644 drivers/net/ntnic/nthw/core/nthw_spim.c
 create mode 100644 drivers/net/ntnic/nthw/core/nthw_spis.c
 create mode 100644 drivers/net/ntnic/nthw/core/nthw_tsm.c

diff --git a/drivers/net/ntnic/include/NT200A02_U23_Si5340_adr0_v5-Registers.h b/drivers/net/ntnic/include/NT200A02_U23_Si5340_adr0_v5-Registers.h
new file mode 100644
index 0000000000..c4185c77ff
--- /dev/null
+++ b/drivers/net/ntnic/include/NT200A02_U23_Si5340_adr0_v5-Registers.h
@@ -0,0 +1,752 @@
+/*
+ * Si5340 Rev D Configuration Register Export Header File
+ *
+ * This file represents a series of Silicon Labs Si5340 Rev D
+ * register writes that can be performed to load a single configuration
+ * on a device. It was created by a Silicon Labs ClockBuilder Pro
+ * export tool.
+ *
+ * Part:		                                       Si5340 Rev D
+ * Design ID:                                          05
+ * Includes Pre/Post Download Control Register Writes: Yes
+ * Created By:                                         ClockBuilder Pro v2.28.1 [2018-09-24]
+ * Timestamp:                                          2018-11-14 16:20:29 GMT+01:00
+ *
+ * A complete design report corresponding to this export is included at the end
+ * of this header file.
+ *
+ */
+
+#ifndef SI5340_REVD_REG_CONFIG_HEADER
+#define SI5340_REVD_REG_CONFIG_HEADER
+
+#define SI5340_REVD_REG_CONFIG_NUM_REGS 326
+
+typedef struct {
+	unsigned int address;	/* 16-bit register address */
+	unsigned char value;	/* 8-bit register data */
+
+} si5340_revd_register_t;
+
+static const si5340_revd_register_t si5340_revd_registers[SI5340_REVD_REG_CONFIG_NUM_REGS] = {
+	/* Start configuration preamble */
+	{ 0x0B24, 0xC0 },
+	{ 0x0B25, 0x00 },
+	/* Rev D stuck divider fix */
+	{ 0x0502, 0x01 },
+	{ 0x0505, 0x03 },
+	{ 0x0957, 0x17 },
+	{ 0x0B4E, 0x1A },
+	/* End configuration preamble */
+
+	/* Delay 300 msec */
+	/*    Delay is worst case time for device to complete any calibration */
+	/*    that is running due to device state change previous to this script */
+	/*    being processed. */
+
+	/* Start configuration registers */
+	{ 0x0006, 0x00 },
+	{ 0x0007, 0x00 },
+	{ 0x0008, 0x00 },
+	{ 0x000B, 0x74 },
+	{ 0x0017, 0xF0 },
+	{ 0x0018, 0xFF },
+	{ 0x0021, 0x0F },
+	{ 0x0022, 0x00 },
+	{ 0x002B, 0x0A },
+	{ 0x002C, 0x20 },
+	{ 0x002D, 0x00 },
+	{ 0x002E, 0x00 },
+	{ 0x002F, 0x00 },
+	{ 0x0030, 0x00 },
+	{ 0x0031, 0x00 },
+	{ 0x0032, 0x00 },
+	{ 0x0033, 0x00 },
+	{ 0x0034, 0x00 },
+	{ 0x0035, 0x00 },
+	{ 0x0036, 0x00 },
+	{ 0x0037, 0x00 },
+	{ 0x0038, 0x00 },
+	{ 0x0039, 0x00 },
+	{ 0x003A, 0x00 },
+	{ 0x003B, 0x00 },
+	{ 0x003C, 0x00 },
+	{ 0x003D, 0x00 },
+	{ 0x0041, 0x00 },
+	{ 0x0042, 0x00 },
+	{ 0x0043, 0x00 },
+	{ 0x0044, 0x00 },
+	{ 0x009E, 0x00 },
+	{ 0x0102, 0x01 },
+	{ 0x0112, 0x02 },
+	{ 0x0113, 0x09 },
+	{ 0x0114, 0x3E },
+	{ 0x0115, 0x19 },
+	{ 0x0117, 0x06 },
+	{ 0x0118, 0x09 },
+	{ 0x0119, 0x3E },
+	{ 0x011A, 0x18 },
+	{ 0x0126, 0x06 },
+	{ 0x0127, 0x09 },
+	{ 0x0128, 0x3E },
+	{ 0x0129, 0x18 },
+	{ 0x012B, 0x06 },
+	{ 0x012C, 0x09 },
+	{ 0x012D, 0x3E },
+	{ 0x012E, 0x1A },
+	{ 0x013F, 0x00 },
+	{ 0x0140, 0x00 },
+	{ 0x0141, 0x40 },
+	{ 0x0206, 0x00 },
+	{ 0x0208, 0x00 },
+	{ 0x0209, 0x00 },
+	{ 0x020A, 0x00 },
+	{ 0x020B, 0x00 },
+	{ 0x020C, 0x00 },
+	{ 0x020D, 0x00 },
+	{ 0x020E, 0x00 },
+	{ 0x020F, 0x00 },
+	{ 0x0210, 0x00 },
+	{ 0x0211, 0x00 },
+	{ 0x0212, 0x00 },
+	{ 0x0213, 0x00 },
+	{ 0x0214, 0x00 },
+	{ 0x0215, 0x00 },
+	{ 0x0216, 0x00 },
+	{ 0x0217, 0x00 },
+	{ 0x0218, 0x00 },
+	{ 0x0219, 0x00 },
+	{ 0x021A, 0x00 },
+	{ 0x021B, 0x00 },
+	{ 0x021C, 0x00 },
+	{ 0x021D, 0x00 },
+	{ 0x021E, 0x00 },
+	{ 0x021F, 0x00 },
+	{ 0x0220, 0x00 },
+	{ 0x0221, 0x00 },
+	{ 0x0222, 0x00 },
+	{ 0x0223, 0x00 },
+	{ 0x0224, 0x00 },
+	{ 0x0225, 0x00 },
+	{ 0x0226, 0x00 },
+	{ 0x0227, 0x00 },
+	{ 0x0228, 0x00 },
+	{ 0x0229, 0x00 },
+	{ 0x022A, 0x00 },
+	{ 0x022B, 0x00 },
+	{ 0x022C, 0x00 },
+	{ 0x022D, 0x00 },
+	{ 0x022E, 0x00 },
+	{ 0x022F, 0x00 },
+	{ 0x0235, 0x00 },
+	{ 0x0236, 0x00 },
+	{ 0x0237, 0x00 },
+	{ 0x0238, 0xA6 },
+	{ 0x0239, 0x8B },
+	{ 0x023A, 0x00 },
+	{ 0x023B, 0x00 },
+	{ 0x023C, 0x00 },
+	{ 0x023D, 0x00 },
+	{ 0x023E, 0x80 },
+	{ 0x0250, 0x03 },
+	{ 0x0251, 0x00 },
+	{ 0x0252, 0x00 },
+	{ 0x0253, 0x00 },
+	{ 0x0254, 0x00 },
+	{ 0x0255, 0x00 },
+	{ 0x025C, 0x00 },
+	{ 0x025D, 0x00 },
+	{ 0x025E, 0x00 },
+	{ 0x025F, 0x00 },
+	{ 0x0260, 0x00 },
+	{ 0x0261, 0x00 },
+	{ 0x026B, 0x30 },
+	{ 0x026C, 0x35 },
+	{ 0x026D, 0x00 },
+	{ 0x026E, 0x00 },
+	{ 0x026F, 0x00 },
+	{ 0x0270, 0x00 },
+	{ 0x0271, 0x00 },
+	{ 0x0272, 0x00 },
+	{ 0x0302, 0x00 },
+	{ 0x0303, 0x00 },
+	{ 0x0304, 0x00 },
+	{ 0x0305, 0x00 },
+	{ 0x0306, 0x0D },
+	{ 0x0307, 0x00 },
+	{ 0x0308, 0x00 },
+	{ 0x0309, 0x00 },
+	{ 0x030A, 0x00 },
+	{ 0x030B, 0x80 },
+	{ 0x030C, 0x00 },
+	{ 0x030D, 0x00 },
+	{ 0x030E, 0x00 },
+	{ 0x030F, 0x00 },
+	{ 0x0310, 0x61 },
+	{ 0x0311, 0x08 },
+	{ 0x0312, 0x00 },
+	{ 0x0313, 0x00 },
+	{ 0x0314, 0x00 },
+	{ 0x0315, 0x00 },
+	{ 0x0316, 0x80 },
+	{ 0x0317, 0x00 },
+	{ 0x0318, 0x00 },
+	{ 0x0319, 0x00 },
+	{ 0x031A, 0x00 },
+	{ 0x031B, 0xD0 },
+	{ 0x031C, 0x1A },
+	{ 0x031D, 0x00 },
+	{ 0x031E, 0x00 },
+	{ 0x031F, 0x00 },
+	{ 0x0320, 0x00 },
+	{ 0x0321, 0xA0 },
+	{ 0x0322, 0x00 },
+	{ 0x0323, 0x00 },
+	{ 0x0324, 0x00 },
+	{ 0x0325, 0x00 },
+	{ 0x0326, 0x00 },
+	{ 0x0327, 0x00 },
+	{ 0x0328, 0x00 },
+	{ 0x0329, 0x00 },
+	{ 0x032A, 0x00 },
+	{ 0x032B, 0x00 },
+	{ 0x032C, 0x00 },
+	{ 0x032D, 0x00 },
+	{ 0x0338, 0x00 },
+	{ 0x0339, 0x1F },
+	{ 0x033B, 0x00 },
+	{ 0x033C, 0x00 },
+	{ 0x033D, 0x00 },
+	{ 0x033E, 0x00 },
+	{ 0x033F, 0x00 },
+	{ 0x0340, 0x00 },
+	{ 0x0341, 0x00 },
+	{ 0x0342, 0x00 },
+	{ 0x0343, 0x00 },
+	{ 0x0344, 0x00 },
+	{ 0x0345, 0x00 },
+	{ 0x0346, 0x00 },
+	{ 0x0347, 0x00 },
+	{ 0x0348, 0x00 },
+	{ 0x0349, 0x00 },
+	{ 0x034A, 0x00 },
+	{ 0x034B, 0x00 },
+	{ 0x034C, 0x00 },
+	{ 0x034D, 0x00 },
+	{ 0x034E, 0x00 },
+	{ 0x034F, 0x00 },
+	{ 0x0350, 0x00 },
+	{ 0x0351, 0x00 },
+	{ 0x0352, 0x00 },
+	{ 0x0359, 0x00 },
+	{ 0x035A, 0x00 },
+	{ 0x035B, 0x00 },
+	{ 0x035C, 0x00 },
+	{ 0x035D, 0x00 },
+	{ 0x035E, 0x00 },
+	{ 0x035F, 0x00 },
+	{ 0x0360, 0x00 },
+	{ 0x0802, 0x00 },
+	{ 0x0803, 0x00 },
+	{ 0x0804, 0x00 },
+	{ 0x0805, 0x00 },
+	{ 0x0806, 0x00 },
+	{ 0x0807, 0x00 },
+	{ 0x0808, 0x00 },
+	{ 0x0809, 0x00 },
+	{ 0x080A, 0x00 },
+	{ 0x080B, 0x00 },
+	{ 0x080C, 0x00 },
+	{ 0x080D, 0x00 },
+	{ 0x080E, 0x00 },
+	{ 0x080F, 0x00 },
+	{ 0x0810, 0x00 },
+	{ 0x0811, 0x00 },
+	{ 0x0812, 0x00 },
+	{ 0x0813, 0x00 },
+	{ 0x0814, 0x00 },
+	{ 0x0815, 0x00 },
+	{ 0x0816, 0x00 },
+	{ 0x0817, 0x00 },
+	{ 0x0818, 0x00 },
+	{ 0x0819, 0x00 },
+	{ 0x081A, 0x00 },
+	{ 0x081B, 0x00 },
+	{ 0x081C, 0x00 },
+	{ 0x081D, 0x00 },
+	{ 0x081E, 0x00 },
+	{ 0x081F, 0x00 },
+	{ 0x0820, 0x00 },
+	{ 0x0821, 0x00 },
+	{ 0x0822, 0x00 },
+	{ 0x0823, 0x00 },
+	{ 0x0824, 0x00 },
+	{ 0x0825, 0x00 },
+	{ 0x0826, 0x00 },
+	{ 0x0827, 0x00 },
+	{ 0x0828, 0x00 },
+	{ 0x0829, 0x00 },
+	{ 0x082A, 0x00 },
+	{ 0x082B, 0x00 },
+	{ 0x082C, 0x00 },
+	{ 0x082D, 0x00 },
+	{ 0x082E, 0x00 },
+	{ 0x082F, 0x00 },
+	{ 0x0830, 0x00 },
+	{ 0x0831, 0x00 },
+	{ 0x0832, 0x00 },
+	{ 0x0833, 0x00 },
+	{ 0x0834, 0x00 },
+	{ 0x0835, 0x00 },
+	{ 0x0836, 0x00 },
+	{ 0x0837, 0x00 },
+	{ 0x0838, 0x00 },
+	{ 0x0839, 0x00 },
+	{ 0x083A, 0x00 },
+	{ 0x083B, 0x00 },
+	{ 0x083C, 0x00 },
+	{ 0x083D, 0x00 },
+	{ 0x083E, 0x00 },
+	{ 0x083F, 0x00 },
+	{ 0x0840, 0x00 },
+	{ 0x0841, 0x00 },
+	{ 0x0842, 0x00 },
+	{ 0x0843, 0x00 },
+	{ 0x0844, 0x00 },
+	{ 0x0845, 0x00 },
+	{ 0x0846, 0x00 },
+	{ 0x0847, 0x00 },
+	{ 0x0848, 0x00 },
+	{ 0x0849, 0x00 },
+	{ 0x084A, 0x00 },
+	{ 0x084B, 0x00 },
+	{ 0x084C, 0x00 },
+	{ 0x084D, 0x00 },
+	{ 0x084E, 0x00 },
+	{ 0x084F, 0x00 },
+	{ 0x0850, 0x00 },
+	{ 0x0851, 0x00 },
+	{ 0x0852, 0x00 },
+	{ 0x0853, 0x00 },
+	{ 0x0854, 0x00 },
+	{ 0x0855, 0x00 },
+	{ 0x0856, 0x00 },
+	{ 0x0857, 0x00 },
+	{ 0x0858, 0x00 },
+	{ 0x0859, 0x00 },
+	{ 0x085A, 0x00 },
+	{ 0x085B, 0x00 },
+	{ 0x085C, 0x00 },
+	{ 0x085D, 0x00 },
+	{ 0x085E, 0x00 },
+	{ 0x085F, 0x00 },
+	{ 0x0860, 0x00 },
+	{ 0x0861, 0x00 },
+	{ 0x090E, 0x02 },
+	{ 0x091C, 0x04 },
+	{ 0x0943, 0x00 },
+	{ 0x0949, 0x00 },
+	{ 0x094A, 0x00 },
+	{ 0x094E, 0x49 },
+	{ 0x094F, 0x02 },
+	{ 0x095E, 0x00 },
+	{ 0x0A02, 0x00 },
+	{ 0x0A03, 0x07 },
+	{ 0x0A04, 0x01 },
+	{ 0x0A05, 0x07 },
+	{ 0x0A14, 0x00 },
+	{ 0x0A1A, 0x00 },
+	{ 0x0A20, 0x00 },
+	{ 0x0A26, 0x00 },
+	{ 0x0B44, 0x0F },
+	{ 0x0B4A, 0x08 },
+	{ 0x0B57, 0x0E },
+	{ 0x0B58, 0x01 },
+	/* End configuration registers */
+
+	/* Start configuration postamble */
+	{ 0x001C, 0x01 },
+	{ 0x0B24, 0xC3 },
+	{ 0x0B25, 0x02 },
+	/* End configuration postamble */
+};
+
+/*
+ * Design Report
+ *
+ * Overview
+ * ========
+ * Part:               Si5340AB Rev D
+ * Project File:       P:\Hardware\NT
+ * Adapters\NT200A02\design\Clock_syn_design\NT200A02_U23_Si5340_adr0_v5.slabtimeproj Design ID: 05
+ * Created By:         ClockBuilder Pro v2.28.1 [2018-09-24]
+ * Timestamp:          2018-11-14 16:20:29 GMT+01:00
+ *
+ * Design Rule Check
+ * =================
+ * Errors:
+ * - No errors
+ *
+ * Warnings:
+ * - No warnings
+ *
+ * Device Grade
+ * ============
+ * Maximum Output Frequency: 257.8125 MHz
+ * Frequency Synthesis Mode: Fractional
+ * Frequency Plan Grade:     B
+ * Minimum Base OPN:         Si5340B*
+ *
+ * Base       Output Clock         Supported Frequency Synthesis Modes
+ * OPN Grade  Frequency Range      (Typical Jitter)
+ * ---------  -------------------  --------------------------------------------
+ * Si5340A    100 Hz to 1.028 GHz  Integer (< 100 fs) and fractional (< 150 fs)
+ * Si5340B*   100 Hz to 350 MHz    "
+ * Si5340C    100 Hz to 1.028 GHz  Integer only (< 100 fs)
+ * Si5340D    100 Hz to 350 MHz    "
+ *
+ * * Based on your calculated frequency plan, a Si5340B grade device is
+ * sufficient for your design. For more in-system configuration flexibility
+ * (higher frequencies and/or to enable fractional synthesis), consider
+ * selecting device grade Si5340A when specifying an ordering part number (OPN)
+ * for your application. See the datasheet Ordering Guide for more information.
+ *
+ * Design
+ * ======
+ * Host Interface:
+ *    I/O Power Supply: VDD (Core)
+ *    SPI Mode: 3-Wire
+ *    I2C Address Range: 116d to 119d / 0x74 to 0x77 (selected via A0/A1 pins)
+ *
+ * Inputs:
+ *    XAXB: 48 MHz
+ *          Crystal Mode
+ *     IN0: Unused
+ *     IN1: Unused
+ *     IN2: Unused
+ *   FB_IN: Unused
+ *
+ * Outputs:
+ *    OUT0: 100 MHz
+ *          Enabled, LVDS 1.8 V
+ *    OUT1: 257.8125 MHz [ 257 + 13/16 MHz ]
+ *          Enabled, LVDS 1.8 V
+ *    OUT2: 257.8125 MHz [ 257 + 13/16 MHz ]
+ *          Enabled, LVDS 1.8 V
+ *    OUT3: 156.25 MHz [ 156 + 1/4 MHz ]
+ *          Enabled, LVDS 1.8 V
+ *
+ * Frequency Plan
+ * ==============
+ * Priority: OUT1 is lowest jitter output
+ *
+ * Fpfd = 48 MHz
+ * Fvco = 13.40625 GHz [ 13 + 13/32 GHz ]
+ * Fms0 = 515.625 MHz [ 515 + 5/8 MHz ]
+ * Fms1 = 800 MHz
+ * Fms2 = 312.5 MHz [ 312 + 1/2 MHz ]
+ *
+ * P dividers:
+ *    P0  = Unused
+ *    P1  = Unused
+ *    P2  = Unused
+ *    P3  = Unused
+ *    Pxaxb = 1
+ *
+ * M = 279.296875 [ 279 + 19/64 ]
+ * N dividers:
+ *    N0:
+ *       Value: 26
+ *       Skew:  0.000 s
+ *       OUT1: 257.8125 MHz [ 257 + 13/16 MHz ]
+ *       OUT2: 257.8125 MHz [ 257 + 13/16 MHz ]
+ *    N1:
+ *       Value: 16.7578125 [ 16 + 97/128 ]
+ *       Skew:  0.000 s
+ *       OUT0: 100 MHz
+ *    N2:
+ *       Value: 42.9 [ 42 + 9/10 ]
+ *       Skew:  0.000 s
+ *       OUT3: 156.25 MHz [ 156 + 1/4 MHz ]
+ *    N3:
+ *       Unused
+ *
+ * R dividers:
+ *    R0 = 8
+ *    R1 = 2
+ *    R2 = 2
+ *    R3 = 2
+ *
+ * Dividers listed above show effective values. These values are translated to register settings by
+ * ClockBuilder Pro. For the actual register values, see below. Refer to the Family Reference
+ * Manual for information on registers related to frequency plan.
+ *
+ * Digitally Controlled Oscillator (DCO)
+ * =====================================
+ * Mode: FINC/FDEC
+ *
+ * N0: DCO Disabled
+ *
+ * N1: DCO Disabled
+ *
+ * N2: DCO Disabled
+ *
+ * N3: DCO Disabled
+ *
+ * Estimated Power & Junction Temperature
+ * ======================================
+ * Assumptions:
+ *
+ * Revision: D
+ * VDD:      1.8 V
+ * Ta:       70 °C
+ * Airflow:  None
+ *
+ * Total Power: 767 mW, On Chip Power: 743 mW, Tj: 87 °C
+ *
+ *            Frequency  Format   Voltage   Current     Power
+ *         ------------  ------  --------  --------  --------
+ * VDD                              1.8 V  146.3 mA    263 mW
+ * VDDA                             3.3 V  117.4 mA    387 mW
+ * VDDO0        100 MHz  LVDS       1.8 V   15.6 mA     28 mW
+ * VDDO1   257.8125 MHz  LVDS       1.8 V   16.6 mA     30 mW
+ * VDDO2   257.8125 MHz  LVDS       1.8 V   16.6 mA     30 mW
+ * VDDO3     156.25 MHz  LVDS       1.8 V   15.9 mA     29 mW
+ *                                         --------  --------
+ *                                  Total  328.4 mA    767 mW
+ *
+ * Note:
+ *
+ * -Total power includes on- and off-chip power. This is a typical value and estimate only.
+ * -Use an EVB for a more exact power measurement
+ * -On-chip power excludes power dissipated in external terminations.
+ * -Tj is junction temperature. Tj must be less than 125 °C (on Si5340 Revision D) for device to
+ * comply with datasheet specifications.
+ *
+ * Settings
+ * ========
+ *
+ * Location      Setting Name         Decimal Value      Hex Value
+ * ------------  -------------------  -----------------  -----------------
+ * 0x0006[23:0]  TOOL_VERSION         0                  0x000000
+ * 0x000B[6:0]   I2C_ADDR             116                0x74
+ * 0x0017[0]     SYSINCAL_INTR_MSK    0                  0x0
+ * 0x0017[1]     LOSXAXB_INTR_MSK     0                  0x0
+ * 0x0017[2]     LOSREF_INTR_MSK      0                  0x0
+ * 0x0017[3]     LOL_INTR_MSK         0                  0x0
+ * 0x0017[5]     SMB_TMOUT_INTR_MSK   1                  0x1
+ * 0x0018[3:0]   LOSIN_INTR_MSK       15                 0xF
+ * 0x0021[0]     IN_SEL_REGCTRL       1                  0x1
+ * 0x0021[2:1]   IN_SEL               3                  0x3
+ * 0x0022[1]     OE                   0                  0x0
+ * 0x002B[3]     SPI_3WIRE            1                  0x1
+ * 0x002B[5]     AUTO_NDIV_UPDATE     0                  0x0
+ * 0x002C[3:0]   LOS_EN               0                  0x0
+ * 0x002C[4]     LOSXAXB_DIS          0                  0x0
+ * 0x002D[1:0]   LOS0_VAL_TIME        0                  0x0
+ * 0x002D[3:2]   LOS1_VAL_TIME        0                  0x0
+ * 0x002D[5:4]   LOS2_VAL_TIME        0                  0x0
+ * 0x002D[7:6]   LOS3_VAL_TIME        0                  0x0
+ * 0x002E[15:0]  LOS0_TRG_THR         0                  0x0000
+ * 0x0030[15:0]  LOS1_TRG_THR         0                  0x0000
+ * 0x0032[15:0]  LOS2_TRG_THR         0                  0x0000
+ * 0x0034[15:0]  LOS3_TRG_THR         0                  0x0000
+ * 0x0036[15:0]  LOS0_CLR_THR         0                  0x0000
+ * 0x0038[15:0]  LOS1_CLR_THR         0                  0x0000
+ * 0x003A[15:0]  LOS2_CLR_THR         0                  0x0000
+ * 0x003C[15:0]  LOS3_CLR_THR         0                  0x0000
+ * 0x0041[4:0]   LOS0_DIV_SEL         0                  0x00
+ * 0x0042[4:0]   LOS1_DIV_SEL         0                  0x00
+ * 0x0043[4:0]   LOS2_DIV_SEL         0                  0x00
+ * 0x0044[4:0]   LOS3_DIV_SEL         0                  0x00
+ * 0x009E[7:4]   LOL_SET_THR          0                  0x0
+ * 0x0102[0]     OUTALL_DISABLE_LOW   1                  0x1
+ * 0x0112[0]     OUT0_PDN             0                  0x0
+ * 0x0112[1]     OUT0_OE              1                  0x1
+ * 0x0112[2]     OUT0_RDIV_FORCE2     0                  0x0
+ * 0x0113[2:0]   OUT0_FORMAT          1                  0x1
+ * 0x0113[3]     OUT0_SYNC_EN         1                  0x1
+ * 0x0113[5:4]   OUT0_DIS_STATE       0                  0x0
+ * 0x0113[7:6]   OUT0_CMOS_DRV        0                  0x0
+ * 0x0114[3:0]   OUT0_CM              14                 0xE
+ * 0x0114[6:4]   OUT0_AMPL            3                  0x3
+ * 0x0115[2:0]   OUT0_MUX_SEL         1                  0x1
+ * 0x0115[5:4]   OUT0_VDD_SEL         1                  0x1
+ * 0x0115[3]     OUT0_VDD_SEL_EN      1                  0x1
+ * 0x0115[7:6]   OUT0_INV             0                  0x0
+ * 0x0117[0]     OUT1_PDN             0                  0x0
+ * 0x0117[1]     OUT1_OE              1                  0x1
+ * 0x0117[2]     OUT1_RDIV_FORCE2     1                  0x1
+ * 0x0118[2:0]   OUT1_FORMAT          1                  0x1
+ * 0x0118[3]     OUT1_SYNC_EN         1                  0x1
+ * 0x0118[5:4]   OUT1_DIS_STATE       0                  0x0
+ * 0x0118[7:6]   OUT1_CMOS_DRV        0                  0x0
+ * 0x0119[3:0]   OUT1_CM              14                 0xE
+ * 0x0119[6:4]   OUT1_AMPL            3                  0x3
+ * 0x011A[2:0]   OUT1_MUX_SEL         0                  0x0
+ * 0x011A[5:4]   OUT1_VDD_SEL         1                  0x1
+ * 0x011A[3]     OUT1_VDD_SEL_EN      1                  0x1
+ * 0x011A[7:6]   OUT1_INV             0                  0x0
+ * 0x0126[0]     OUT2_PDN             0                  0x0
+ * 0x0126[1]     OUT2_OE              1                  0x1
+ * 0x0126[2]     OUT2_RDIV_FORCE2     1                  0x1
+ * 0x0127[2:0]   OUT2_FORMAT          1                  0x1
+ * 0x0127[3]     OUT2_SYNC_EN         1                  0x1
+ * 0x0127[5:4]   OUT2_DIS_STATE       0                  0x0
+ * 0x0127[7:6]   OUT2_CMOS_DRV        0                  0x0
+ * 0x0128[3:0]   OUT2_CM              14                 0xE
+ * 0x0128[6:4]   OUT2_AMPL            3                  0x3
+ * 0x0129[2:0]   OUT2_MUX_SEL         0                  0x0
+ * 0x0129[5:4]   OUT2_VDD_SEL         1                  0x1
+ * 0x0129[3]     OUT2_VDD_SEL_EN      1                  0x1
+ * 0x0129[7:6]   OUT2_INV             0                  0x0
+ * 0x012B[0]     OUT3_PDN             0                  0x0
+ * 0x012B[1]     OUT3_OE              1                  0x1
+ * 0x012B[2]     OUT3_RDIV_FORCE2     1                  0x1
+ * 0x012C[2:0]   OUT3_FORMAT          1                  0x1
+ * 0x012C[3]     OUT3_SYNC_EN         1                  0x1
+ * 0x012C[5:4]   OUT3_DIS_STATE       0                  0x0
+ * 0x012C[7:6]   OUT3_CMOS_DRV        0                  0x0
+ * 0x012D[3:0]   OUT3_CM              14                 0xE
+ * 0x012D[6:4]   OUT3_AMPL            3                  0x3
+ * 0x012E[2:0]   OUT3_MUX_SEL         2                  0x2
+ * 0x012E[5:4]   OUT3_VDD_SEL         1                  0x1
+ * 0x012E[3]     OUT3_VDD_SEL_EN      1                  0x1
+ * 0x012E[7:6]   OUT3_INV             0                  0x0
+ * 0x013F[11:0]  OUTX_ALWAYS_ON       0                  0x000
+ * 0x0141[5]     OUT_DIS_LOL_MSK      0                  0x0
+ * 0x0141[7]     OUT_DIS_MSK_LOS_PFD  0                  0x0
+ * 0x0206[1:0]   PXAXB                0                  0x0
+ * 0x0208[47:0]  P0                   0                  0x000000000000
+ * 0x020E[31:0]  P0_SET               0                  0x00000000
+ * 0x0212[47:0]  P1                   0                  0x000000000000
+ * 0x0218[31:0]  P1_SET               0                  0x00000000
+ * 0x021C[47:0]  P2                   0                  0x000000000000
+ * 0x0222[31:0]  P2_SET               0                  0x00000000
+ * 0x0226[47:0]  P3                   0                  0x000000000000
+ * 0x022C[31:0]  P3_SET               0                  0x00000000
+ * 0x0235[43:0]  M_NUM                599785472000       0x08BA6000000
+ * 0x023B[31:0]  M_DEN                2147483648         0x80000000
+ * 0x0250[23:0]  R0_REG               3                  0x000003
+ * 0x0253[23:0]  R1_REG               0                  0x000000
+ * 0x025C[23:0]  R2_REG               0                  0x000000
+ * 0x025F[23:0]  R3_REG               0                  0x000000
+ * 0x026B[7:0]   DESIGN_ID0           48                 0x30
+ * 0x026C[7:0]   DESIGN_ID1           53                 0x35
+ * 0x026D[7:0]   DESIGN_ID2           0                  0x00
+ * 0x026E[7:0]   DESIGN_ID3           0                  0x00
+ * 0x026F[7:0]   DESIGN_ID4           0                  0x00
+ * 0x0270[7:0]   DESIGN_ID5           0                  0x00
+ * 0x0271[7:0]   DESIGN_ID6           0                  0x00
+ * 0x0272[7:0]   DESIGN_ID7           0                  0x00
+ * 0x0302[43:0]  N0_NUM               55834574848        0x00D00000000
+ * 0x0308[31:0]  N0_DEN               2147483648         0x80000000
+ * 0x030C[0]     N0_UPDATE            0                  0x0
+ * 0x030D[43:0]  N1_NUM               35987128320        0x00861000000
+ * 0x0313[31:0]  N1_DEN               2147483648         0x80000000
+ * 0x0317[0]     N1_UPDATE            0                  0x0
+ * 0x0318[43:0]  N2_NUM               115158810624       0x01AD0000000
+ * 0x031E[31:0]  N2_DEN               2684354560         0xA0000000
+ * 0x0322[0]     N2_UPDATE            0                  0x0
+ * 0x0323[43:0]  N3_NUM               0                  0x00000000000
+ * 0x0329[31:0]  N3_DEN               0                  0x00000000
+ * 0x032D[0]     N3_UPDATE            0                  0x0
+ * 0x0338[1]     N_UPDATE             0                  0x0
+ * 0x0339[4:0]   N_FSTEP_MSK          31                 0x1F
+ * 0x033B[43:0]  N0_FSTEPW            0                  0x00000000000
+ * 0x0341[43:0]  N1_FSTEPW            0                  0x00000000000
+ * 0x0347[43:0]  N2_FSTEPW            0                  0x00000000000
+ * 0x034D[43:0]  N3_FSTEPW            0                  0x00000000000
+ * 0x0359[15:0]  N0_DELAY             0                  0x0000
+ * 0x035B[15:0]  N1_DELAY             0                  0x0000
+ * 0x035D[15:0]  N2_DELAY             0                  0x0000
+ * 0x035F[15:0]  N3_DELAY             0                  0x0000
+ * 0x0802[15:0]  FIXREGSA0            0                  0x0000
+ * 0x0804[7:0]   FIXREGSD0            0                  0x00
+ * 0x0805[15:0]  FIXREGSA1            0                  0x0000
+ * 0x0807[7:0]   FIXREGSD1            0                  0x00
+ * 0x0808[15:0]  FIXREGSA2            0                  0x0000
+ * 0x080A[7:0]   FIXREGSD2            0                  0x00
+ * 0x080B[15:0]  FIXREGSA3            0                  0x0000
+ * 0x080D[7:0]   FIXREGSD3            0                  0x00
+ * 0x080E[15:0]  FIXREGSA4            0                  0x0000
+ * 0x0810[7:0]   FIXREGSD4            0                  0x00
+ * 0x0811[15:0]  FIXREGSA5            0                  0x0000
+ * 0x0813[7:0]   FIXREGSD5            0                  0x00
+ * 0x0814[15:0]  FIXREGSA6            0                  0x0000
+ * 0x0816[7:0]   FIXREGSD6            0                  0x00
+ * 0x0817[15:0]  FIXREGSA7            0                  0x0000
+ * 0x0819[7:0]   FIXREGSD7            0                  0x00
+ * 0x081A[15:0]  FIXREGSA8            0                  0x0000
+ * 0x081C[7:0]   FIXREGSD8            0                  0x00
+ * 0x081D[15:0]  FIXREGSA9            0                  0x0000
+ * 0x081F[7:0]   FIXREGSD9            0                  0x00
+ * 0x0820[15:0]  FIXREGSA10           0                  0x0000
+ * 0x0822[7:0]   FIXREGSD10           0                  0x00
+ * 0x0823[15:0]  FIXREGSA11           0                  0x0000
+ * 0x0825[7:0]   FIXREGSD11           0                  0x00
+ * 0x0826[15:0]  FIXREGSA12           0                  0x0000
+ * 0x0828[7:0]   FIXREGSD12           0                  0x00
+ * 0x0829[15:0]  FIXREGSA13           0                  0x0000
+ * 0x082B[7:0]   FIXREGSD13           0                  0x00
+ * 0x082C[15:0]  FIXREGSA14           0                  0x0000
+ * 0x082E[7:0]   FIXREGSD14           0                  0x00
+ * 0x082F[15:0]  FIXREGSA15           0                  0x0000
+ * 0x0831[7:0]   FIXREGSD15           0                  0x00
+ * 0x0832[15:0]  FIXREGSA16           0                  0x0000
+ * 0x0834[7:0]   FIXREGSD16           0                  0x00
+ * 0x0835[15:0]  FIXREGSA17           0                  0x0000
+ * 0x0837[7:0]   FIXREGSD17           0                  0x00
+ * 0x0838[15:0]  FIXREGSA18           0                  0x0000
+ * 0x083A[7:0]   FIXREGSD18           0                  0x00
+ * 0x083B[15:0]  FIXREGSA19           0                  0x0000
+ * 0x083D[7:0]   FIXREGSD19           0                  0x00
+ * 0x083E[15:0]  FIXREGSA20           0                  0x0000
+ * 0x0840[7:0]   FIXREGSD20           0                  0x00
+ * 0x0841[15:0]  FIXREGSA21           0                  0x0000
+ * 0x0843[7:0]   FIXREGSD21           0                  0x00
+ * 0x0844[15:0]  FIXREGSA22           0                  0x0000
+ * 0x0846[7:0]   FIXREGSD22           0                  0x00
+ * 0x0847[15:0]  FIXREGSA23           0                  0x0000
+ * 0x0849[7:0]   FIXREGSD23           0                  0x00
+ * 0x084A[15:0]  FIXREGSA24           0                  0x0000
+ * 0x084C[7:0]   FIXREGSD24           0                  0x00
+ * 0x084D[15:0]  FIXREGSA25           0                  0x0000
+ * 0x084F[7:0]   FIXREGSD25           0                  0x00
+ * 0x0850[15:0]  FIXREGSA26           0                  0x0000
+ * 0x0852[7:0]   FIXREGSD26           0                  0x00
+ * 0x0853[15:0]  FIXREGSA27           0                  0x0000
+ * 0x0855[7:0]   FIXREGSD27           0                  0x00
+ * 0x0856[15:0]  FIXREGSA28           0                  0x0000
+ * 0x0858[7:0]   FIXREGSD28           0                  0x00
+ * 0x0859[15:0]  FIXREGSA29           0                  0x0000
+ * 0x085B[7:0]   FIXREGSD29           0                  0x00
+ * 0x085C[15:0]  FIXREGSA30           0                  0x0000
+ * 0x085E[7:0]   FIXREGSD30           0                  0x00
+ * 0x085F[15:0]  FIXREGSA31           0                  0x0000
+ * 0x0861[7:0]   FIXREGSD31           0                  0x00
+ * 0x090E[0]     XAXB_EXTCLK_EN       0                  0x0
+ * 0x090E[1]     XAXB_PDNB            1                  0x1
+ * 0x091C[2:0]   ZDM_EN               4                  0x4
+ * 0x0943[0]     IO_VDD_SEL           0                  0x0
+ * 0x0949[3:0]   IN_EN                0                  0x0
+ * 0x0949[7:4]   IN_PULSED_CMOS_EN    0                  0x0
+ * 0x094A[7:4]   INX_TO_PFD_EN        0                  0x0
+ * 0x094E[11:0]  REFCLK_HYS_SEL       585                0x249
+ * 0x095E[0]     M_INTEGER            0                  0x0
+ * 0x0A02[4:0]   N_ADD_0P5            0                  0x00
+ * 0x0A03[4:0]   N_CLK_TO_OUTX_EN     7                  0x07
+ * 0x0A04[4:0]   N_PIBYP              1                  0x01
+ * 0x0A05[4:0]   N_PDNB               7                  0x07
+ * 0x0A14[3]     N0_HIGH_FREQ         0                  0x0
+ * 0x0A1A[3]     N1_HIGH_FREQ         0                  0x0
+ * 0x0A20[3]     N2_HIGH_FREQ         0                  0x0
+ * 0x0A26[3]     N3_HIGH_FREQ         0                  0x0
+ * 0x0B44[3:0]   PDIV_ENB             15                 0xF
+ * 0x0B4A[4:0]   N_CLK_DIS            8                  0x08
+ * 0x0B57[11:0]  VCO_RESET_CALCODE    270                0x10E
+ *
+ *
+ */
+
+#endif
diff --git a/drivers/net/ntnic/meson.build b/drivers/net/ntnic/meson.build
index a9bf9b5906..14cd951d6d 100644
--- a/drivers/net/ntnic/meson.build
+++ b/drivers/net/ntnic/meson.build
@@ -87,6 +87,22 @@ sources = files(
     'nthw/supported/nthw_fpga_9563_055_039_0000.c',
     'nthw/supported/nthw_fpga_instances.c',
     'nthw/supported/nthw_fpga_mod_str_map.c',
+    'nthw/core/nt200a0x/clock_profiles/nthw_fpga_clk9563.c',
+    'nthw/core/nt200a0x/nthw_fpga_nt200a0x.c',
+    'nthw/core/nt200a0x/reset/nthw_fpga_rst9563.c',
+    'nthw/core/nt200a0x/reset/nthw_fpga_rst_nt200a0x.c',
+    'nthw/core/nthw_fpga.c',
+    'nthw/core/nthw_fpga_rst.c',
+    'nthw/core/nthw_hif.c',
+    'nthw/core/nthw_iic.c',
+    'nthw/core/nthw_mac_pcs_xxv.c',
+    'nthw/core/nthw_pcie3.c',
+    'nthw/core/nthw_sdc.c',
+    'nthw/core/nthw_si5340.c',
+    'nthw/core/nthw_spim.c',
+    'nthw/core/nthw_spis.c',
+    'nthw/core/nthw_spi_v3.c',
+    'nthw/core/nthw_tsm.c',
     'nthw/model/nthw_fpga_model.c',
     'nthw/nthw_epp.c',
     'nthw/nthw_platform.c',
diff --git a/drivers/net/ntnic/nthw/core/nt200a0x/clock_profiles/nthw_fpga_clk9563.c b/drivers/net/ntnic/nthw/core/nt200a0x/clock_profiles/nthw_fpga_clk9563.c
new file mode 100644
index 0000000000..f00e9ac053
--- /dev/null
+++ b/drivers/net/ntnic/nthw/core/nt200a0x/clock_profiles/nthw_fpga_clk9563.c
@@ -0,0 +1,51 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#include "nthw_clock_profiles.h"
+#include "nthw_fpga_clk9563.h"
+#include "ntnic_mod_reg.h"
+
+#define code	/* Remove this word from the array definitions */
+
+/*
+ * Clock profile for NT200A02 FPGA 9563
+ */
+#define si5340_revd_register_t type_9563_si5340_nt200a02_u23_v5
+#define si5340_revd_registers data_9563_si5340_nt200a02_u23_v5
+#include "NT200A02_U23_Si5340_adr0_v5-Registers.h"
+#ifdef __cplusplus
+static_assert(sizeof(type_9563_si5340_nt200a02_u23_v5) == sizeof(clk_profile_data_fmt2_t),
+	clk_profile_size_error_msg);
+#endif	/* __cplusplus */
+static const int n_data_9563_si5340_nt200a02_u23_v5 = SI5340_REVD_REG_CONFIG_NUM_REGS;
+static const clk_profile_data_fmt2_t *p_data_9563_si5340_nt200a02_u23_v5 =
+	(const clk_profile_data_fmt2_t *)&data_9563_si5340_nt200a02_u23_v5[0];
+
+static const int *get_n_data_9563_si5340_nt200a02_u23_v5(void)
+{
+	return &n_data_9563_si5340_nt200a02_u23_v5;
+}
+
+static const clk_profile_data_fmt2_t *get_p_data_9563_si5340_nt200a02_u23_v5(void)
+{
+	return p_data_9563_si5340_nt200a02_u23_v5;
+}
+
+static struct clk9563_ops ops = { .get_n_data_9563_si5340_nt200a02_u23_v5 =
+		get_n_data_9563_si5340_nt200a02_u23_v5,
+		.get_p_data_9563_si5340_nt200a02_u23_v5 =
+			get_p_data_9563_si5340_nt200a02_u23_v5
+};
+
+static void __attribute__((constructor(65535))) clk9563_ops_init(void)
+{
+	register_clk9563_ops(&ops);
+}
+
+#undef si5340_revd_registers
+#undef si5340_revd_register_t
+#undef SI5340_REVD_REG_CONFIG_HEADER	/* Disable the include once protection */
+
+#undef code
diff --git a/drivers/net/ntnic/nthw/core/nt200a0x/clock_profiles/nthw_fpga_clk9563.h b/drivers/net/ntnic/nthw/core/nt200a0x/clock_profiles/nthw_fpga_clk9563.h
new file mode 100644
index 0000000000..88d72cd334
--- /dev/null
+++ b/drivers/net/ntnic/nthw/core/nt200a0x/clock_profiles/nthw_fpga_clk9563.h
@@ -0,0 +1,9 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef _NTHW_FPGA_CLK_9563_H_
+#define _NTHW_FPGA_CLK_9563_H_
+
+#endif	/* _NTHW_FPGA_CLK_9563_H_ */
diff --git a/drivers/net/ntnic/nthw/core/nt200a0x/nthw_fpga_nt200a0x.c b/drivers/net/ntnic/nthw/core/nt200a0x/nthw_fpga_nt200a0x.c
new file mode 100644
index 0000000000..0f358da346
--- /dev/null
+++ b/drivers/net/ntnic/nthw/core/nt200a0x/nthw_fpga_nt200a0x.c
@@ -0,0 +1,107 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#include "ntlog.h"
+
+#include "nthw_fpga.h"
+#include "nthw_fpga_nt200a0x.h"
+#include "ntnic_mod_reg.h"
+
+static int nthw_fpga_nt200a0x_init(struct fpga_info_s *p_fpga_info)
+{
+	assert(p_fpga_info);
+
+	const char *const p_adapter_id_str = p_fpga_info->mp_adapter_id_str;
+	struct nthw_fpga_rst_nt200a0x rst;
+	int res = -1;
+	const struct rst_nt200a0x_ops *rst_nt200a0x_ops = get_rst_nt200a0x_ops();
+
+	if (rst_nt200a0x_ops == NULL) {
+		NT_LOG(ERR, NTHW, "RST NT200A0X NOT INCLUDED\n");
+		return -1;
+	}
+
+	/* reset common */
+	res = rst_nt200a0x_ops->nthw_fpga_rst_nt200a0x_init(p_fpga_info, &rst);
+
+	if (res) {
+		NT_LOG(ERR, NTHW, "%s: %s: loc=%u: FPGA=%04d res=%d\n", p_adapter_id_str, __func__,
+			__LINE__, p_fpga_info->n_fpga_prod_id, res);
+		return res;
+	}
+
+	bool included = true;
+	struct rst9530_ops *rst9530_ops = get_rst9530_ops();
+	struct rst9544_ops *rst9544_ops = get_rst9544_ops();
+	struct rst9563_ops *rst9563_ops = get_rst9563_ops();
+	struct rst9572_ops *rst9572_ops = get_rst9572_ops();
+
+	/* reset specific */
+	switch (p_fpga_info->n_fpga_prod_id) {
+	case 9530:
+		if (rst9530_ops != NULL)
+			res = rst9530_ops->nthw_fpga_rst9530_init(p_fpga_info, &rst);
+
+		else
+			included = false;
+
+		break;
+
+	case 9544:
+		if (rst9544_ops != NULL)
+			res = rst9544_ops->nthw_fpga_rst9544_init(p_fpga_info, &rst);
+
+		else
+			included = false;
+
+		break;
+
+	case 9563:
+		if (rst9563_ops != NULL)
+			res = rst9563_ops->nthw_fpga_rst9563_init(p_fpga_info, &rst);
+
+		else
+			included = false;
+
+		break;
+
+	case 9572:
+		if (rst9572_ops != NULL)
+			res = rst9572_ops->nthw_fpga_rst9572_init(p_fpga_info, &rst);
+
+		else
+			included = false;
+
+		break;
+
+	default:
+		NT_LOG(ERR, NTHW, "%s: Unsupported FPGA product: %04d\n", p_adapter_id_str,
+			p_fpga_info->n_fpga_prod_id);
+		res = -1;
+		break;
+	}
+
+	if (!included) {
+		NT_LOG(ERR, NTHW, "%s: NOT INCLUDED FPGA product: %04d\n", p_adapter_id_str,
+			p_fpga_info->n_fpga_prod_id);
+		res = -1;
+	}
+
+	if (res) {
+		NT_LOG(ERR, NTHW, "%s: %s: loc=%u: FPGA=%04d res=%d\n", p_adapter_id_str, __func__,
+			__LINE__, p_fpga_info->n_fpga_prod_id, res);
+		return res;
+	}
+
+	return res;
+}
+
+static struct nt200a0x_ops nt200a0x_ops = { .nthw_fpga_nt200a0x_init = nthw_fpga_nt200a0x_init };
+
+static void __attribute__((constructor(65535))) nt200a0x_ops_init(void)
+{
+	NT_LOG(INF, NTHW, "NT200A0X OPS INIT");
+	register_nt200a0x_ops(&nt200a0x_ops);
+}
diff --git a/drivers/net/ntnic/nthw/core/nt200a0x/nthw_fpga_nt200a0x.h b/drivers/net/ntnic/nthw/core/nt200a0x/nthw_fpga_nt200a0x.h
new file mode 100644
index 0000000000..26efe27e0f
--- /dev/null
+++ b/drivers/net/ntnic/nthw/core/nt200a0x/nthw_fpga_nt200a0x.h
@@ -0,0 +1,9 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2024 Napatech A/S
+ */
+
+#ifndef __NTHW_FPGA_NT200A0X_H__
+#define __NTHW_FPGA_NT200A0X_H__
+
+#endif	/* __NTHW_FPGA_NT200A0X_H__ */
diff --git a/drivers/net/ntnic/nthw/core/nt200a0x/reset/nthw_fpga_rst9563.c b/drivers/net/ntnic/nthw/core/nt200a0x/reset/nthw_fpga_rst9563.c
new file mode 100644
index 0000000000..c113bb04b7
--- /dev/null
+++ b/drivers/net/ntnic/nthw/core/nt200a0x/reset/nthw_fpga_rst9563.c
@@ -0,0 +1,258 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#include "ntlog.h"
+
+#include "nthw_drv.h"
+#include "nthw_register.h"
+#include "nthw_fpga.h"
+
+#include "nthw_fpga_rst9563.h"
+#include "nthw_fpga_nt200a0x.h"
+#include "nthw_fpga_rst_nt200a0x.h"
+#include "ntnic_mod_reg.h"
+
+static int nthw_fpga_rst9563_setup(nthw_fpga_t *p_fpga, struct nthw_fpga_rst_nt200a0x *const p)
+{
+	const char *const p_adapter_id_str = p_fpga->p_fpga_info->mp_adapter_id_str;
+	const int n_fpga_product_id = p_fpga->mn_product_id;
+	const int n_fpga_version = p_fpga->mn_fpga_version;
+	const int n_fpga_revision = p_fpga->mn_fpga_revision;
+
+	nthw_module_t *p_mod_rst;
+	nthw_register_t *p_curr_reg;
+
+	assert(p);
+	p->mn_fpga_product_id = n_fpga_product_id;
+	p->mn_fpga_version = n_fpga_version;
+	p->mn_fpga_revision = n_fpga_revision;
+
+	NT_LOG(DBG, NTHW, "%s: %s: FPGA reset setup: FPGA %04d-%02d-%02d\n", p_adapter_id_str,
+		__func__, n_fpga_product_id, n_fpga_version, n_fpga_revision);
+
+	p_mod_rst = nthw_fpga_query_module(p_fpga, MOD_RST9563, 0);
+
+	if (p_mod_rst == NULL) {
+		NT_LOG(ERR, NTHW, "%s: RST %d: no such instance\n", p_adapter_id_str, 0);
+		return -1;
+	}
+
+	p_mod_rst = nthw_fpga_query_module(p_fpga, MOD_RST9563, 0);
+
+	if (p_mod_rst == NULL) {
+		NT_LOG(ERR, NTHW, "%s: RST %d: no such instance\n", p_adapter_id_str, 0);
+		return -1;
+	}
+
+	/* RST register field pointers */
+	p_curr_reg = nthw_module_get_register(p_mod_rst, RST9563_RST);
+	p->mp_fld_rst_sys = nthw_register_get_field(p_curr_reg, RST9563_RST_SYS);
+	p->mp_fld_rst_sys_mmcm = nthw_register_get_field(p_curr_reg, RST9563_RST_SYS_MMCM);
+	p->mp_fld_rst_core_mmcm = nthw_register_get_field(p_curr_reg, RST9563_RST_CORE_MMCM);
+	p->mp_fld_rst_rpp = nthw_register_get_field(p_curr_reg, RST9563_RST_RPP);
+	p->mp_fld_rst_ddr4 = nthw_register_get_field(p_curr_reg, RST9563_RST_DDR4);
+	p->mp_fld_rst_sdc = nthw_register_get_field(p_curr_reg, RST9563_RST_SDC);
+	p->mp_fld_rst_phy = nthw_register_get_field(p_curr_reg, RST9563_RST_PHY);
+	p->mp_fld_rst_serdes_rx = NULL;	/* Field not present on 9563 */
+	p->mp_fld_rst_serdes_tx = NULL;	/* Field not present on 9563 */
+	p->mp_fld_rst_serdes_rx_datapath = NULL;/* Field not present on 9563 */
+	p->mp_fld_rst_pcs_rx = NULL;	/* Field not present on 9563 */
+	p->mp_fld_rst_mac_rx = nthw_register_get_field(p_curr_reg, RST9563_RST_MAC_RX);
+	p->mp_fld_rst_mac_tx = NULL;
+	p->mp_fld_rst_ptp = nthw_register_get_field(p_curr_reg, RST9563_RST_PTP);
+	p->mp_fld_rst_ptp = nthw_register_get_field(p_curr_reg, RST9563_RST_PTP);
+	p->mp_fld_rst_ts = nthw_register_get_field(p_curr_reg, RST9563_RST_TS);
+	p->mp_fld_rst_ptp_mmcm = nthw_register_get_field(p_curr_reg, RST9563_RST_PTP_MMCM);
+	p->mp_fld_rst_ts_mmcm = nthw_register_get_field(p_curr_reg, RST9563_RST_TS_MMCM);
+	/* referenced in separate function */
+	p->mp_fld_rst_periph = nthw_register_get_field(p_curr_reg, RST9563_RST_PERIPH);
+	p->mp_fld_rst_tsm_ref_mmcm =
+		nthw_register_query_field(p_curr_reg, RST9563_RST_TSM_REF_MMCM);
+	p->mp_fld_rst_tmc = nthw_register_query_field(p_curr_reg, RST9563_RST_TMC);
+
+	if (!p->mp_fld_rst_tsm_ref_mmcm)
+		NT_LOG(DBG, NTHW, "%s: No RST9563_RST_TSM_REF_MMCM found\n", p_adapter_id_str);
+
+	if (!p->mp_fld_rst_tmc)
+		NT_LOG(DBG, NTHW, "%s: No RST9563_RST_TMC found\n", p_adapter_id_str);
+
+	nthw_register_update(p_curr_reg);
+
+	/* CTRL register field pointers */
+	p_curr_reg = nthw_module_get_register(p_mod_rst, RST9563_CTRL);
+	p->mp_fld_ctrl_ts_clk_sel_override =
+		nthw_register_get_field(p_curr_reg, RST9563_CTRL_TS_CLKSEL_OVERRIDE);
+	/* Field not present on 9563 */
+	p->mp_fld_ctrl_ts_clk_sel = nthw_register_get_field(p_curr_reg, RST9563_CTRL_TS_CLKSEL);
+	p->mp_fld_ctrl_ts_clk_sel_ref = NULL;	/* Field not present on 9563 */
+	p->mp_fld_ctrl_ptp_mmcm_clk_sel =
+		nthw_register_get_field(p_curr_reg, RST9563_CTRL_PTP_MMCM_CLKSEL);
+	nthw_register_update(p_curr_reg);
+
+	/* STAT register field pointers */
+	p_curr_reg = nthw_module_get_register(p_mod_rst, RST9563_STAT);
+	p->mp_fld_stat_ddr4_mmcm_locked =
+		nthw_register_get_field(p_curr_reg, RST9563_STAT_DDR4_MMCM_LOCKED);
+	p->mp_fld_stat_sys_mmcm_locked =
+		nthw_register_get_field(p_curr_reg, RST9563_STAT_SYS_MMCM_LOCKED);
+	p->mp_fld_stat_core_mmcm_locked =
+		nthw_register_get_field(p_curr_reg, RST9563_STAT_CORE_MMCM_LOCKED);
+	p->mp_fld_stat_ddr4_pll_locked =
+		nthw_register_get_field(p_curr_reg, RST9563_STAT_DDR4_PLL_LOCKED);
+	p->mp_fld_stat_ptp_mmcm_locked =
+		nthw_register_get_field(p_curr_reg, RST9563_STAT_PTP_MMCM_LOCKED);
+	p->mp_fld_stat_ts_mmcm_locked =
+		nthw_register_get_field(p_curr_reg, RST9563_STAT_TS_MMCM_LOCKED);
+	p->mp_fld_stat_tsm_ref_mmcm_locked = NULL;	/* Field not present on 9563 */
+
+	if (!p->mp_fld_stat_tsm_ref_mmcm_locked) {
+		NT_LOG(DBG, NTHW, "%s: No RST9563_STAT_TSM_REF_MMCM_LOCKED found\n",
+			p_adapter_id_str);
+	}
+
+	nthw_register_update(p_curr_reg);
+
+	/* STICKY register field pointers */
+	p_curr_reg = nthw_module_get_register(p_mod_rst, RST9563_STICKY);
+	p->mp_fld_sticky_ptp_mmcm_unlocked =
+		nthw_register_get_field(p_curr_reg, RST9563_STICKY_PTP_MMCM_UNLOCKED);
+	p->mp_fld_sticky_ts_mmcm_unlocked =
+		nthw_register_get_field(p_curr_reg, RST9563_STICKY_TS_MMCM_UNLOCKED);
+	p->mp_fld_sticky_ddr4_mmcm_unlocked =
+		nthw_register_get_field(p_curr_reg, RST9563_STICKY_DDR4_MMCM_UNLOCKED);
+	p->mp_fld_sticky_ddr4_pll_unlocked =
+		nthw_register_get_field(p_curr_reg, RST9563_STICKY_DDR4_PLL_UNLOCKED);
+	p->mp_fld_sticky_core_mmcm_unlocked =
+		nthw_register_get_field(p_curr_reg, RST9563_STICKY_CORE_MMCM_UNLOCKED);
+	p->mp_fld_sticky_pci_sys_mmcm_unlocked = NULL;	/* Field not present on 9563 */
+	p->mp_fld_sticky_tsm_ref_mmcm_unlocked = NULL;	/* Field not present on 9563 */
+
+	if (!p->mp_fld_sticky_tsm_ref_mmcm_unlocked) {
+		NT_LOG(DBG, NTHW, "%s: No RST9563_STICKY_TSM_REF_MMCM_UNLOCKED found\n",
+			p_adapter_id_str);
+	}
+
+	nthw_register_update(p_curr_reg);
+
+	/* POWER register field pointers */
+	p_curr_reg = nthw_module_get_register(p_mod_rst, RST9563_POWER);
+	p->mp_fld_power_pu_phy = nthw_register_get_field(p_curr_reg, RST9563_POWER_PU_PHY);
+	p->mp_fld_power_pu_nseb = nthw_register_get_field(p_curr_reg, RST9563_POWER_PU_NSEB);
+	nthw_register_update(p_curr_reg);
+
+	return 0;
+}
+
+static int nthw_fpga_rst9563_periph_reset(nthw_fpga_t *p_fpga)
+{
+	const char *const p_adapter_id_str = p_fpga->p_fpga_info->mp_adapter_id_str;
+	(void)p_adapter_id_str;
+	nthw_module_t *p_mod_rst = nthw_fpga_query_module(p_fpga, MOD_RST9563, 0);
+
+	if (p_mod_rst) {
+		nthw_register_t *p_reg_rst;
+		nthw_field_t *p_fld_rst_periph;
+		NT_LOG(DBG, NTHW, "%s: PERIPH RST\n", p_adapter_id_str);
+		p_reg_rst = nthw_module_get_register(p_mod_rst, RST9563_RST);
+		p_fld_rst_periph = nthw_register_get_field(p_reg_rst, RST9563_RST_PERIPH);
+		nthw_field_set_flush(p_fld_rst_periph);
+		nthw_field_clr_flush(p_fld_rst_periph);
+
+	} else {
+		return -1;
+	}
+
+	return 0;
+}
+
+static int nthw_fpga_rst9563_clock_synth_init(nthw_fpga_t *p_fpga,
+	const int n_si_labs_clock_synth_model,
+	const uint8_t n_si_labs_clock_synth_i2c_addr)
+{
+	const char *const p_adapter_id_str = p_fpga->p_fpga_info->mp_adapter_id_str;
+	const int n_fpga_product_id = p_fpga->mn_product_id;
+	int res;
+	const struct clk9563_ops *clk9563_ops = get_clk9563_ops();
+
+	if (clk9563_ops == NULL) {
+		NT_LOG(INF, ETHDEV, "CLK9563 module not included\n");
+		return -1;
+	}
+
+	if (n_si_labs_clock_synth_model == 5340) {
+		res = nthw_fpga_si5340_clock_synth_init_fmt2(p_fpga, n_si_labs_clock_synth_i2c_addr,
+				clk9563_ops->get_p_data_9563_si5340_nt200a02_u23_v5(),
+				*clk9563_ops->get_n_data_9563_si5340_nt200a02_u23_v5());
+
+	} else {
+		NT_LOG(ERR, NTHW, "%s: Fpga %d: Unsupported clock synth model (%d)\n",
+			p_adapter_id_str, n_fpga_product_id, n_si_labs_clock_synth_model);
+		res = -1;
+	}
+
+	return res;
+}
+
+static int nthw_fpga_rst9563_init(struct fpga_info_s *p_fpga_info,
+	struct nthw_fpga_rst_nt200a0x *p_rst)
+{
+	assert(p_fpga_info);
+	assert(p_rst);
+
+	const char *const p_adapter_id_str = p_fpga_info->mp_adapter_id_str;
+	(void)p_adapter_id_str;
+	int res = -1;
+	int n_si_labs_clock_synth_model;
+	uint8_t n_si_labs_clock_synth_i2c_addr;
+	nthw_fpga_t *p_fpga = NULL;
+
+	p_fpga = p_fpga_info->mp_fpga;
+	n_si_labs_clock_synth_model = p_rst->mn_si_labs_clock_synth_model;
+	n_si_labs_clock_synth_i2c_addr = p_rst->mn_si_labs_clock_synth_i2c_addr;
+
+	res = nthw_fpga_rst9563_periph_reset(p_fpga);
+
+	if (res) {
+		NT_LOG(DBG, NTHW, "%s: ERROR: res=%d [%s:%u]\n", p_adapter_id_str, res, __func__,
+			__LINE__);
+		return res;
+	}
+
+	res = nthw_fpga_rst9563_clock_synth_init(p_fpga, n_si_labs_clock_synth_model,
+			n_si_labs_clock_synth_i2c_addr);
+
+	if (res) {
+		NT_LOG(DBG, NTHW, "%s: ERROR: res=%d [%s:%u]\n", p_adapter_id_str, res, __func__,
+			__LINE__);
+		return res;
+	}
+
+	res = nthw_fpga_rst9563_setup(p_fpga, p_rst);
+
+	if (res) {
+		NT_LOG(DBG, NTHW, "%s: ERROR: res=%d [%s:%u]\n", p_adapter_id_str, res, __func__,
+			__LINE__);
+		return res;
+	}
+
+	const struct rst_nt200a0x_ops *rst_ops = get_rst_nt200a0x_ops();
+	res = rst_ops != NULL ? rst_ops->nthw_fpga_rst_nt200a0x_reset(p_fpga, p_rst) : -1;
+
+	if (res) {
+		NT_LOG(DBG, NTHW, "%s: ERROR: res=%d [%s:%u]\n", p_adapter_id_str, res, __func__,
+			__LINE__);
+		return res;
+	}
+
+	return res;
+}
+
+static struct rst9563_ops rst9563_ops = { .nthw_fpga_rst9563_init = nthw_fpga_rst9563_init };
+
+static void __attribute__((constructor(65535))) rst9563_ops_init(void)
+{
+	NT_LOG(INF, NTHW, "RST9563 OPS INIT");
+	register_rst9563_ops(&rst9563_ops);
+}
diff --git a/drivers/net/ntnic/nthw/core/nt200a0x/reset/nthw_fpga_rst9563.h b/drivers/net/ntnic/nthw/core/nt200a0x/reset/nthw_fpga_rst9563.h
new file mode 100644
index 0000000000..e61cd32954
--- /dev/null
+++ b/drivers/net/ntnic/nthw/core/nt200a0x/reset/nthw_fpga_rst9563.h
@@ -0,0 +1,9 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef __NTHW_FPGA_RST9563_H__
+#define __NTHW_FPGA_RST9563_H__
+
+#endif	/* __NTHW_FPGA_RST9563_H__ */
diff --git a/drivers/net/ntnic/nthw/core/nt200a0x/reset/nthw_fpga_rst_nt200a0x.c b/drivers/net/ntnic/nthw/core/nt200a0x/reset/nthw_fpga_rst_nt200a0x.c
new file mode 100644
index 0000000000..d323d9a93f
--- /dev/null
+++ b/drivers/net/ntnic/nthw/core/nt200a0x/reset/nthw_fpga_rst_nt200a0x.c
@@ -0,0 +1,729 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#include "ntlog.h"
+
+#include "nthw_drv.h"
+#include "nthw_register.h"
+#include "nthw_fpga.h"
+
+#include "nthw_fpga_rst_nt200a0x.h"
+#include "nthw_fpga_nt200a0x.h"
+#include "ntnic_mod_reg.h"
+
+static const uint8_t si5338_u23_i2c_addr_7bit = 0x70;
+static const uint8_t si5340_u23_i2c_addr_7bit = 0x74;
+
+/*
+ * Wait until DDR4 PLL LOCKED
+ */
+static int nthw_fpga_rst_nt200a0x_wait_ddr4_pll_locked(nthw_fpga_t *p_fpga,
+	const struct nthw_fpga_rst_nt200a0x *p)
+{
+	const char *const p_adapter_id_str = p_fpga->p_fpga_info->mp_adapter_id_str;
+	uint32_t locked;
+	uint32_t retrycount = 5;
+	uint32_t timeout = 50000;	/* initial timeout must be set to 5 sec. */
+	/* 14: wait until DDR4 PLL LOCKED */
+	NT_LOG(DBG, NTHW, "%s: Waiting for DDR4 PLL to lock\n", p_adapter_id_str);
+
+	/*
+	 * The following retry count gives a total timeout of 1 * 5 + 5 * 8 = 45sec
+	 * It has been observed that at least 21sec can be necessary
+	 */
+	while (true) {
+		int locked =
+			nthw_field_wait_set_any32(p->mp_fld_stat_ddr4_pll_locked, timeout, 100);
+
+		if (locked == 0) {
+			break;
+
+		} else {
+			NT_LOG(DBG, NTHW, "%s: Waiting for DDR4 PLL to lock - timeout\n",
+				p_adapter_id_str);
+
+			if (retrycount <= 0) {
+				NT_LOG(ERR, NTHW, "%s: Waiting for DDR4 PLL to lock failed (%d)\n",
+					p_adapter_id_str, locked);
+				break;
+			}
+
+			nthw_field_set_flush(p->mp_fld_rst_ddr4);	/* Reset DDR PLL */
+			nthw_field_clr_flush(p->mp_fld_rst_ddr4);	/* Reset DDR PLL */
+			retrycount--;
+			timeout = 80000;/* Increase timeout for second attempt to 8 sec. */
+		}
+	}
+
+	NT_LOG(DBG, NTHW, "%s: Waiting for DDR4 MMCM to lock\n", p_adapter_id_str);
+	locked = nthw_field_wait_set_any32(p->mp_fld_stat_ddr4_mmcm_locked, -1, -1);
+
+	if (locked != 0) {
+		NT_LOG(ERR, NTHW, "%s: Waiting for DDR4 MMCM to lock failed (%d)\n",
+			p_adapter_id_str, locked);
+		return -1;
+	}
+
+	if (true && p->mp_fld_stat_tsm_ref_mmcm_locked) {
+		NT_LOG(DBG, NTHW, "%s: Waiting for TSM REF MMCM to lock\n", p_adapter_id_str);
+		locked = nthw_field_wait_set_any32(p->mp_fld_stat_tsm_ref_mmcm_locked, -1, -1);
+
+		if (locked != 0) {
+			NT_LOG(ERR, NTHW, "%s: Waiting for TSM REF MMCM to lock failed (%d)\n",
+				p_adapter_id_str, locked);
+			return -1;
+		}
+	}
+
+	/* 10: Clear all MMCM/PLL lock sticky bits before testing them */
+	NT_LOG(DBG, NTHW, "%s: Clear sticky MMCM unlock bits\n", p_adapter_id_str);
+	nthw_field_update_register(p->mp_fld_sticky_ptp_mmcm_unlocked);
+	/* Clear all sticky bits */
+	nthw_field_set_flush(p->mp_fld_sticky_ptp_mmcm_unlocked);
+	nthw_field_set_flush(p->mp_fld_sticky_ts_mmcm_unlocked);
+	nthw_field_set_flush(p->mp_fld_sticky_ddr4_mmcm_unlocked);
+	nthw_field_set_flush(p->mp_fld_sticky_ddr4_pll_unlocked);
+	nthw_field_set_flush(p->mp_fld_sticky_core_mmcm_unlocked);
+
+	if (p->mp_fld_sticky_tsm_ref_mmcm_unlocked)
+		nthw_field_set_flush(p->mp_fld_sticky_tsm_ref_mmcm_unlocked);
+
+	if (p->mp_fld_sticky_pci_sys_mmcm_unlocked)
+		nthw_field_set_flush(p->mp_fld_sticky_pci_sys_mmcm_unlocked);
+
+	/* 11: Ensure sticky bits are not unlocked except PTP MMCM and TS MMCM */
+	if (nthw_field_get_updated(p->mp_fld_sticky_ddr4_mmcm_unlocked)) {
+		NT_LOG(ERR, NTHW, "%s: get_sticky_ddr4_mmcm_unlocked() returned true\n",
+			p_adapter_id_str);
+	}
+
+	if (nthw_field_get_updated(p->mp_fld_sticky_ddr4_pll_unlocked)) {
+		NT_LOG(ERR, NTHW, "%s: get_sticky_ddr4_pll_unlocked() returned true\n",
+			p_adapter_id_str);
+	}
+
+	return 0;
+}
+
+/*
+ * Wait for SDRAM controller has been calibrated - On some adapters we have seen
+ * calibration time of 2.3 seconds
+ */
+static int nthw_fpga_rst_nt200a0x_wait_sdc_calibrated(nthw_fpga_t *p_fpga,
+	const struct nthw_fpga_rst_nt200a0x *p)
+{
+	const char *const p_adapter_id_str = p_fpga->p_fpga_info->mp_adapter_id_str;
+	nthw_sdc_t *p_nthw_sdc = NULL;
+	const int n_retry_cnt_max = 5;
+	int n_retry_cnt;
+	int res;
+
+	res = nthw_sdc_init(NULL, p_fpga, 0);	/* probe for module */
+
+	if (res == 0) {
+		p_nthw_sdc = nthw_sdc_new();
+
+		if (p_nthw_sdc) {
+			res = nthw_sdc_init(p_nthw_sdc, p_fpga, 0);
+
+			if (res) {
+				NT_LOG(ERR, NTHW, "%s: SDC init failed: res=%d [%s:%d]\n",
+					p_adapter_id_str, res, __func__, __LINE__);
+				nthw_sdc_delete(p_nthw_sdc);
+				p_nthw_sdc = NULL;
+				return -1;
+			}
+
+		} else {
+			nthw_sdc_delete(p_nthw_sdc);
+			p_nthw_sdc = NULL;
+		}
+
+	} else {
+		NT_LOG(DBG, NTHW, "%s: No SDC found\n", p_adapter_id_str);
+	}
+
+	n_retry_cnt = 0;
+	res = -1;
+
+	while ((res != 0) && (n_retry_cnt <= n_retry_cnt_max)) {
+		/* wait until DDR4 PLL LOCKED */
+		res = nthw_fpga_rst_nt200a0x_wait_ddr4_pll_locked(p_fpga, p);
+
+		if (res == 0) {
+			if (p_nthw_sdc) {
+				/*
+				 * Wait for SDRAM controller has been calibrated
+				 * On some adapters we have seen calibration time of 2.3 seconds
+				 */
+				NT_LOG(DBG, NTHW, "%s: Waiting for SDRAM to calibrate\n",
+					p_adapter_id_str);
+				res = nthw_sdc_wait_states(p_nthw_sdc, 10000, 1000);
+				{
+					uint64_t n_result_mask;
+					int n_state_code =
+						nthw_sdc_get_states(p_nthw_sdc, &n_result_mask);
+					(void)n_state_code;
+					NT_LOG(DBG, NTHW,
+						"%s: SDRAM state=0x%08lX state_code=%d retry=%d code=%d\n",
+						p_adapter_id_str, n_result_mask, n_state_code,
+						n_retry_cnt, res);
+				}
+
+				if (res == 0)
+					break;
+			}
+
+			if (n_retry_cnt >= n_retry_cnt_max) {
+				uint64_t n_result_mask;
+				int n_state_code = nthw_sdc_get_states(p_nthw_sdc, &n_result_mask);
+				(void)n_state_code;
+
+				NT_LOG(DBG, NTHW,
+					"%s: SDRAM state=0x%08lX state_code=%d retry=%d code=%d\n",
+					p_adapter_id_str, n_result_mask, n_state_code, n_retry_cnt,
+					res);
+
+				if (res != 0) {
+					NT_LOG(ERR, NTHW,
+						"%s: Timeout waiting for SDRAM controller calibration\n",
+						p_adapter_id_str);
+				}
+			}
+		}
+
+		/*
+		 * SDRAM controller is not calibrated with DDR4 ram blocks:
+		 * reset DDR and perform calibration retry
+		 */
+		nthw_field_set_flush(p->mp_fld_rst_ddr4);	/* Reset DDR PLL */
+		nt_os_wait_usec(100);
+		nthw_field_clr_flush(p->mp_fld_rst_ddr4);
+
+		n_retry_cnt++;
+	}
+
+	nthw_sdc_delete(p_nthw_sdc);
+
+	return res;
+}
+
+static int nthw_fpga_rst_nt200a0x_reset(nthw_fpga_t *p_fpga,
+	const struct nthw_fpga_rst_nt200a0x *p)
+{
+	const char *const p_adapter_id_str = p_fpga->p_fpga_info->mp_adapter_id_str;
+	const fpga_info_t *const p_fpga_info = p_fpga->p_fpga_info;
+
+	const int n_fpga_product_id = p->mn_fpga_product_id;
+	const int n_fpga_version = p->mn_fpga_version;
+	const int n_fpga_revision = p->mn_fpga_revision;
+	const int n_nthw_adapter_id = p_fpga_info->n_nthw_adapter_id;
+	const bool b_is_nt200a01 = (n_nthw_adapter_id == NT_HW_ADAPTER_ID_NT200A01);
+	const int n_hw_id = p_fpga_info->nthw_hw_info.hw_id;
+	const uint8_t index = 0;
+	int locked;
+	int res = -1;
+
+	NT_LOG(DBG, NTHW, "%s: %s: FPGA reset sequence: FPGA %04d-%02d-%02d @ HWId%d\n",
+		p_adapter_id_str, __func__, n_fpga_product_id, n_fpga_version, n_fpga_revision,
+		n_hw_id);
+	assert(n_fpga_product_id == p_fpga->mn_product_id);
+
+	/*
+	 * Reset all domains / modules except peripherals
+	 * Set default reset values to ensure that all modules are reset correctly
+	 * no matter if nic has been powercycled or ntservice has been reloaded
+	 */
+
+	/*
+	 * reset to defaults
+	 * 1: Reset all domains
+	 */
+	NT_LOG(DBG, NTHW, "%s: RST defaults\n", p_adapter_id_str);
+
+	nthw_field_update_register(p->mp_fld_rst_sys);
+	nthw_field_set_flush(p->mp_fld_rst_sys);
+
+	if (p->mp_fld_rst_tmc)
+		nthw_field_set_flush(p->mp_fld_rst_tmc);
+
+	nthw_field_set_flush(p->mp_fld_rst_rpp);
+	nthw_field_set_flush(p->mp_fld_rst_ddr4);	/* 0x07 3 banks */
+	nthw_field_set_flush(p->mp_fld_rst_sdc);
+
+	/* Reset port 0 and 1 in the following registers: */
+	nthw_field_set_flush(p->mp_fld_rst_phy);/* 0x03 2 ports */
+
+	if (p->mp_fld_rst_mac_rx)
+		nthw_field_set_flush(p->mp_fld_rst_mac_rx);	/* 0x03 2 ports */
+
+	if (p->mp_fld_rst_mac_tx)
+		nthw_field_set_flush(p->mp_fld_rst_mac_tx);	/* 0x03 2 ports */
+
+	if (p->mp_fld_rst_pcs_rx)
+		nthw_field_set_flush(p->mp_fld_rst_pcs_rx);	/* 0x03 2 ports */
+
+	if (p->mp_fld_rst_serdes_rx)
+		nthw_field_set_flush(p->mp_fld_rst_serdes_rx);	/* 0x03 2 ports */
+
+	if (p->mp_fld_rst_serdes_rx_datapath) {
+		nthw_field_set_flush(p->mp_fld_rst_serdes_rx_datapath);
+		nthw_field_clr_flush(p->mp_fld_rst_serdes_rx);
+	}
+
+	if (p->mp_fld_rst_serdes_tx)
+		nthw_field_set_flush(p->mp_fld_rst_serdes_tx);
+
+	nthw_field_set_flush(p->mp_fld_rst_ptp);
+	nthw_field_set_flush(p->mp_fld_rst_ts);
+	nthw_field_set_flush(p->mp_fld_rst_sys_mmcm);
+	nthw_field_set_flush(p->mp_fld_rst_core_mmcm);
+	nthw_field_set_flush(p->mp_fld_rst_ptp_mmcm);
+	nthw_field_set_flush(p->mp_fld_rst_ts_mmcm);
+
+	if (true && p->mp_fld_rst_tsm_ref_mmcm)
+		nthw_field_set_flush(p->mp_fld_rst_tsm_ref_mmcm);
+
+	/* Write all changes to register */
+	nthw_field_flush_register(p->mp_fld_rst_sys);
+
+	if (b_is_nt200a01 && n_hw_id == 2) {	/* Not relevant to NT200A02 */
+		if (p->mp_fld_rst_tsm_ref_mmcm) {
+			nthw_field_update_register(p->mp_fld_rst_tsm_ref_mmcm);
+			nthw_field_set_flush(p->mp_fld_rst_tsm_ref_mmcm);
+		}
+	}
+
+	/*
+	 * 2: Force use of 50 MHz reference clock for timesync;
+	 * NOTE: From 9508-05-18 this is a 20 MHz clock
+	 */
+	NT_LOG(DBG, NTHW, "%s: Setting TS CLK SEL OVERRIDE\n", p_adapter_id_str);
+	nthw_field_update_register(p->mp_fld_ctrl_ts_clk_sel_override);
+	nthw_field_set_flush(p->mp_fld_ctrl_ts_clk_sel_override);
+
+	NT_LOG(DBG, NTHW, "%s: Setting TS CLK SEL\n", p_adapter_id_str);
+	nthw_field_update_register(p->mp_fld_ctrl_ts_clk_sel);
+	nthw_field_set_flush(p->mp_fld_ctrl_ts_clk_sel);
+
+	if (b_is_nt200a01 && n_hw_id == 2) {	/* Not relevant to NT200A02 */
+		NT_LOG(DBG, NTHW, "%s: Selecting 20MHz TS CLK SEL REF\n", p_adapter_id_str);
+
+		if (p->mp_fld_ctrl_ts_clk_sel_ref) {
+			nthw_field_update_register(p->mp_fld_ctrl_ts_clk_sel_ref);
+			nthw_field_clr_flush(p->mp_fld_ctrl_ts_clk_sel_ref);
+		}
+	}
+
+	/* 4: De-assert sys reset, CORE and SYS MMCM resets */
+	NT_LOG(DBG, NTHW, "%s: De-asserting SYS, CORE and SYS MMCM resets\n", p_adapter_id_str);
+	nthw_field_update_register(p->mp_fld_rst_sys);
+	nthw_field_clr_flush(p->mp_fld_rst_sys);
+	nthw_field_clr_flush(p->mp_fld_rst_sys_mmcm);
+	nthw_field_clr_flush(p->mp_fld_rst_core_mmcm);
+
+	/* 5: wait until CORE MMCM and SYS MMCM are LOCKED */
+	NT_LOG(DBG, NTHW, "%s: Waiting for SYS MMCM to lock\n", p_adapter_id_str);
+	locked = nthw_field_wait_set_any32(p->mp_fld_stat_sys_mmcm_locked, -1, -1);
+
+	if (locked != 0) {
+		NT_LOG(ERR, NTHW, "%s: Waiting for SYS MMCM to lock failed (%d)\n",
+			p_adapter_id_str, locked);
+	}
+
+	NT_LOG(DBG, NTHW, "%s: Waiting for CORE MMCM to lock\n", p_adapter_id_str);
+	locked = nthw_field_wait_set_any32(p->mp_fld_stat_core_mmcm_locked, -1, -1);
+
+	if (locked != 0) {
+		NT_LOG(ERR, NTHW, "%s: Waiting for CORE MMCM to lock failed (%d)\n",
+			p_adapter_id_str, locked);
+	}
+
+	/*
+	 * RAC RAB bus "flip/flip" reset second stage - new impl (ref RMT#37020)
+	 * RAC/RAB init - SYS/CORE MMCM is locked - pull the remaining RAB busses out of reset
+	 */
+	{
+		nthw_rac_t *p_nthw_rac = p_fpga_info->mp_nthw_rac;
+		NT_LOG(DBG, NTHW, "%s: De-asserting remaining RAB busses\n", p_adapter_id_str);
+		nthw_rac_rab_init(p_nthw_rac, 0);
+	}
+
+	if (true && p->mp_fld_rst_tsm_ref_mmcm) {
+		NT_LOG(DBG, NTHW, "%s: De-asserting TSM REF MMCM\n", p_adapter_id_str);
+		nthw_field_clr_flush(p->mp_fld_rst_tsm_ref_mmcm);
+
+		if (p->mp_fld_stat_tsm_ref_mmcm_locked) {
+			NT_LOG(DBG, NTHW, "%s: Waiting for TSM REF MMCM to lock\n",
+				p_adapter_id_str);
+			locked = nthw_field_wait_set_any32(p->mp_fld_stat_tsm_ref_mmcm_locked, -1,
+					-1);
+
+			if (locked != 0) {
+				NT_LOG(ERR, NTHW,
+					"%s: Waiting for TSM REF MMCM to lock failed (%d)\n",
+					p_adapter_id_str, locked);
+			}
+		}
+	}
+
+	/*
+	 * 5.2: Having ensured CORE MMCM and SYS MMCM are LOCKED,
+	 * we need to select the alternative 20 MHz reference clock,
+	 * the external TSM reference clock
+	 * on NT200A01 - build 2 HW only (see SSF00024 p.32)
+	 */
+	if (b_is_nt200a01 && n_hw_id == 2) {	/* Not relevant to NT200A02 */
+		NT_LOG(DBG, NTHW, "%s: Setting TS CLK SEL REF\n", p_adapter_id_str);
+
+		if (p->mp_fld_ctrl_ts_clk_sel_ref)
+			nthw_field_set_flush(p->mp_fld_ctrl_ts_clk_sel_ref);
+
+		if (p->mp_fld_rst_tsm_ref_mmcm) {
+			NT_LOG(DBG, NTHW, "%s: De-asserting TSM REF MMCM\n", p_adapter_id_str);
+			nthw_field_clr_flush(p->mp_fld_rst_tsm_ref_mmcm);
+		}
+
+		NT_LOG(DBG, NTHW, "%s: Waiting for TSM REF MMCM to lock\n", p_adapter_id_str);
+
+		if (p->mp_fld_stat_tsm_ref_mmcm_locked) {
+			locked = nthw_field_wait_set_any32(p->mp_fld_stat_tsm_ref_mmcm_locked, -1,
+					-1);
+
+			if (locked != 0) {
+				NT_LOG(ERR, NTHW,
+					"%s: Waiting for TSM REF MMCM to lock failed (%d)\n",
+					p_adapter_id_str, locked);
+			}
+		}
+	}
+
+	NT_LOG(DBG, NTHW, "%s: De-asserting all PHY resets\n", p_adapter_id_str);
+	nthw_field_update_register(p->mp_fld_rst_phy);
+	nthw_field_clr_flush(p->mp_fld_rst_phy);
+
+	/* MAC_PCS_XXV 10G/25G: 9530 / 9544 */
+	if (n_fpga_product_id == 9530 || n_fpga_product_id == 9544) {
+		{
+			/* Based on nt200e3_2_ptp.cpp My25GbPhy::resetRx */
+			nthw_mac_pcs_xxv_t *p_nthw_mac_pcs_xxv0 = nthw_mac_pcs_xxv_new();
+			assert(p_nthw_mac_pcs_xxv0);
+			nthw_mac_pcs_xxv_init(p_nthw_mac_pcs_xxv0, p_fpga, 0, 1, false);
+
+			nthw_mac_pcs_xxv_reset_rx_gt_data(p_nthw_mac_pcs_xxv0, true, index);
+			nt_os_wait_usec(1000);
+
+			nthw_mac_pcs_xxv_reset_rx_gt_data(p_nthw_mac_pcs_xxv0, false, index);
+			nt_os_wait_usec(1000);
+
+			nthw_mac_pcs_xxv_delete(p_nthw_mac_pcs_xxv0);
+		}
+
+		{
+			/* Based on nt200e3_2_ptp.cpp My25GbPhy::resetRx */
+			nthw_mac_pcs_xxv_t *p_nthw_mac_pcs_xxv1 = nthw_mac_pcs_xxv_new();
+			assert(p_nthw_mac_pcs_xxv1);
+			nthw_mac_pcs_xxv_init(p_nthw_mac_pcs_xxv1, p_fpga, 1, 1, false);
+
+			nthw_mac_pcs_xxv_reset_rx_gt_data(p_nthw_mac_pcs_xxv1, true, index);
+			nt_os_wait_usec(1000);
+
+			nthw_mac_pcs_xxv_reset_rx_gt_data(p_nthw_mac_pcs_xxv1, false, index);
+			nt_os_wait_usec(1000);
+
+			nthw_mac_pcs_xxv_delete(p_nthw_mac_pcs_xxv1);
+		}
+		nt_os_wait_usec(3000);
+	}
+
+	/* MAC_PCS_XXV 8x10G: 9572 */
+	if (n_fpga_product_id == 9572) {
+		{
+			nthw_mac_pcs_xxv_t *p_nthw_mac_pcs_xxv0 = nthw_mac_pcs_xxv_new();
+			assert(p_nthw_mac_pcs_xxv0);
+			nthw_mac_pcs_xxv_init(p_nthw_mac_pcs_xxv0, p_fpga, 0, 4, true);
+
+			for (int i = 0; i < 4; i++) {
+				nthw_mac_pcs_xxv_reset_rx_gt_data(p_nthw_mac_pcs_xxv0, true, i);
+				nthw_mac_pcs_xxv_set_rx_mac_pcs_rst(p_nthw_mac_pcs_xxv0, true, i);
+				nt_os_wait_usec(1000);
+
+				nthw_mac_pcs_xxv_reset_rx_gt_data(p_nthw_mac_pcs_xxv0, false, i);
+				nthw_mac_pcs_xxv_set_rx_mac_pcs_rst(p_nthw_mac_pcs_xxv0, false, i);
+				nt_os_wait_usec(1000);
+			}
+
+			nthw_mac_pcs_xxv_delete(p_nthw_mac_pcs_xxv0);
+		}
+
+		{
+			nthw_mac_pcs_xxv_t *p_nthw_mac_pcs_xxv1 = nthw_mac_pcs_xxv_new();
+			assert(p_nthw_mac_pcs_xxv1);
+			nthw_mac_pcs_xxv_init(p_nthw_mac_pcs_xxv1, p_fpga, 1, 4, true);
+
+			for (int i = 0; i < 4; i++) {
+				nthw_mac_pcs_xxv_reset_rx_gt_data(p_nthw_mac_pcs_xxv1, true, i);
+				nthw_mac_pcs_xxv_set_rx_mac_pcs_rst(p_nthw_mac_pcs_xxv1, true, i);
+				nt_os_wait_usec(1000);
+
+				nthw_mac_pcs_xxv_reset_rx_gt_data(p_nthw_mac_pcs_xxv1, false, i);
+				nthw_mac_pcs_xxv_set_rx_mac_pcs_rst(p_nthw_mac_pcs_xxv1, false, i);
+				nt_os_wait_usec(1000);
+			}
+
+			nthw_mac_pcs_xxv_delete(p_nthw_mac_pcs_xxv1);
+		}
+		nt_os_wait_usec(3000);
+	}
+
+	/*
+	 * 8: De-assert reset for remaining domains/modules resets except
+	 * TS, PTP, PTP_MMCM and TS_MMCM
+	 */
+	NT_LOG(DBG, NTHW, "%s: De-asserting TMC RST\n", p_adapter_id_str);
+
+	if (p->mp_fld_rst_tmc) {
+		nthw_field_update_register(p->mp_fld_rst_tmc);
+		nthw_field_clr_flush(p->mp_fld_rst_tmc);
+	}
+
+	NT_LOG(DBG, NTHW, "%s: De-asserting RPP RST\n", p_adapter_id_str);
+	nthw_field_update_register(p->mp_fld_rst_rpp);
+	nthw_field_clr_flush(p->mp_fld_rst_rpp);
+
+	NT_LOG(DBG, NTHW, "%s: De-asserting DDR4 RST\n", p_adapter_id_str);
+	nthw_field_update_register(p->mp_fld_rst_ddr4);
+	nthw_field_clr_flush(p->mp_fld_rst_ddr4);
+
+	NT_LOG(DBG, NTHW, "%s: De-asserting SDC RST\n", p_adapter_id_str);
+	nthw_field_update_register(p->mp_fld_rst_sdc);
+	nthw_field_clr_flush(p->mp_fld_rst_sdc);
+
+	/* NOTE: 9522 implements PHY10G_QPLL reset and lock at this stage in mac_rx_rst() */
+	NT_LOG(DBG, NTHW, "%s: De-asserting MAC RX RST\n", p_adapter_id_str);
+
+	if (p->mp_fld_rst_mac_rx) {
+		nthw_field_update_register(p->mp_fld_rst_mac_rx);
+		nthw_field_clr_flush(p->mp_fld_rst_mac_rx);
+	}
+
+	/* await until DDR4 PLL LOCKED and SDRAM controller has been calibrated */
+	res = nthw_fpga_rst_nt200a0x_wait_sdc_calibrated(p_fpga, p);
+
+	if (res) {
+		NT_LOG(ERR, NTHW,
+			"%s: nthw_fpga_rst_nt200a0x_wait_sdc_calibrated() returned true\n",
+			p_adapter_id_str);
+		return -1;
+	}
+
+	if (nthw_field_get_updated(p->mp_fld_sticky_core_mmcm_unlocked)) {
+		NT_LOG(ERR, NTHW, "%s: get_sticky_core_mmcm_unlocked() returned true\n",
+			p_adapter_id_str);
+		return -1;
+	}
+
+	if (p->mp_fld_sticky_pci_sys_mmcm_unlocked &&
+		nthw_field_get_updated(p->mp_fld_sticky_pci_sys_mmcm_unlocked)) {
+		NT_LOG(ERR, NTHW, "%s: get_sticky_pci_sys_mmcm_unlocked() returned true\n",
+			p_adapter_id_str);
+		return -1;
+	}
+
+	if (b_is_nt200a01 && n_hw_id == 2) {	/* Not relevant to NT200A02 */
+		if (p->mp_fld_sticky_tsm_ref_mmcm_unlocked &&
+			nthw_field_get_updated(p->mp_fld_sticky_tsm_ref_mmcm_unlocked)) {
+			NT_LOG(ERR, NTHW, "%s: get_sticky_tsm_ref_mmcm_unlocked returned true\n",
+				p_adapter_id_str);
+			return -1;
+		}
+	}
+
+	/*
+	 * Timesync/PTP reset sequence
+	 * De-assert TS_MMCM reset
+	 */
+	NT_LOG(DBG, NTHW, "%s: De-asserting TS MMCM RST\n", p_adapter_id_str);
+	nthw_field_clr_flush(p->mp_fld_rst_ts_mmcm);
+
+	/* Wait until TS_MMCM LOCKED (NT_RAB0_REG_P9508_RST9508_STAT_TS_MMCM_LOCKED=1); */
+	NT_LOG(DBG, NTHW, "%s: Waiting for TS MMCM to lock\n", p_adapter_id_str);
+	locked = nthw_field_wait_set_any32(p->mp_fld_stat_ts_mmcm_locked, -1, -1);
+
+	if (locked != 0) {
+		NT_LOG(ERR, NTHW, "%s: Waiting for TS MMCM to lock failed (%d)\n",
+			p_adapter_id_str, locked);
+	}
+
+	NT_LOG(DBG, NTHW, "%s: Calling clear_sticky_mmcm_unlock_bits()\n", p_adapter_id_str);
+	nthw_field_update_register(p->mp_fld_sticky_ptp_mmcm_unlocked);
+	/* Clear all sticky bits */
+	nthw_field_set_flush(p->mp_fld_sticky_ptp_mmcm_unlocked);
+	nthw_field_set_flush(p->mp_fld_sticky_ts_mmcm_unlocked);
+	nthw_field_set_flush(p->mp_fld_sticky_ddr4_mmcm_unlocked);
+	nthw_field_set_flush(p->mp_fld_sticky_ddr4_pll_unlocked);
+	nthw_field_set_flush(p->mp_fld_sticky_core_mmcm_unlocked);
+
+	if (p->mp_fld_sticky_tsm_ref_mmcm_unlocked)
+		nthw_field_set_flush(p->mp_fld_sticky_tsm_ref_mmcm_unlocked);
+
+	if (p->mp_fld_sticky_pci_sys_mmcm_unlocked)
+		nthw_field_set_flush(p->mp_fld_sticky_pci_sys_mmcm_unlocked);
+
+	/* De-assert TS reset bit */
+	NT_LOG(DBG, NTHW, "%s: De-asserting TS RST\n", p_adapter_id_str);
+	nthw_field_clr_flush(p->mp_fld_rst_ts);
+
+	if (nthw_field_get_updated(p->mp_fld_sticky_ts_mmcm_unlocked)) {
+		NT_LOG(ERR, NTHW, "%s: get_sticky_ts_mmcm_unlocked() returned true\n",
+			p_adapter_id_str);
+		return -1;
+	}
+
+	if (nthw_field_get_updated(p->mp_fld_sticky_ddr4_mmcm_unlocked)) {
+		NT_LOG(ERR, NTHW, "%s: get_sticky_ddr4_mmcm_unlocked() returned true\n",
+			p_adapter_id_str);
+		return -1;
+	}
+
+	if (nthw_field_get_updated(p->mp_fld_sticky_ddr4_pll_unlocked)) {
+		NT_LOG(ERR, NTHW, "%s: get_sticky_ddr4_pll_unlocked() returned true\n",
+			p_adapter_id_str);
+		return -1;
+	}
+
+	if (nthw_field_get_updated(p->mp_fld_sticky_core_mmcm_unlocked)) {
+		NT_LOG(ERR, NTHW, "%s: get_sticky_core_mmcm_unlocked() returned true\n",
+			p_adapter_id_str);
+		return -1;
+	}
+
+	if (p->mp_fld_sticky_pci_sys_mmcm_unlocked &&
+		nthw_field_get_updated(p->mp_fld_sticky_pci_sys_mmcm_unlocked)) {
+		NT_LOG(ERR, NTHW, "%s: get_sticky_pci_sys_mmcm_unlocked() returned true\n",
+			p_adapter_id_str);
+		return -1;
+	}
+
+	if (b_is_nt200a01 && n_hw_id == 2) {	/* Not relevant to NT200A02 */
+		if (p->mp_fld_sticky_tsm_ref_mmcm_unlocked &&
+			nthw_field_get_updated(p->mp_fld_sticky_tsm_ref_mmcm_unlocked)) {
+			NT_LOG(ERR, NTHW, "%s: get_sticky_tsm_ref_mmcm_unlocked() returned true\n",
+				p_adapter_id_str);
+			return -1;
+		}
+	}
+
+	if (false) {
+		/* Deassert PTP_MMCM */
+		NT_LOG(DBG, NTHW, "%s: De-asserting PTP MMCM RST\n", p_adapter_id_str);
+		nthw_field_clr_flush(p->mp_fld_rst_ptp_mmcm);
+
+		if ((b_is_nt200a01 && n_fpga_version >= 9) || !b_is_nt200a01) {
+			/* Wait until PTP_MMCM LOCKED */
+			NT_LOG(DBG, NTHW, "%s: Waiting for PTP MMCM to lock\n", p_adapter_id_str);
+			locked = nthw_field_wait_set_any32(p->mp_fld_stat_ptp_mmcm_locked, -1, -1);
+
+			if (locked != 0) {
+				NT_LOG(ERR, NTHW, "%s: Waiting for PTP MMCM to lock failed (%d)\n",
+					p_adapter_id_str, locked);
+			}
+		}
+
+		/* Switch PTP MMCM sel to use ptp clk */
+		NT_LOG(DBG, NTHW, "%s: Setting PTP MMCM CLK SEL\n", p_adapter_id_str);
+		nthw_field_set_flush(p->mp_fld_ctrl_ptp_mmcm_clk_sel);
+
+		/* Wait until TS_MMCM LOCKED (NT_RAB0_REG_P9508_RST9508_STAT_TS_MMCM_LOCKED=1); */
+		NT_LOG(DBG, NTHW, "%s: Waiting for TS MMCM to re-lock\n", p_adapter_id_str);
+		locked = nthw_field_wait_set_any32(p->mp_fld_stat_ts_mmcm_locked, -1, -1);
+
+		if (locked != 0) {
+			NT_LOG(ERR, NTHW, "%s: Waiting for TS MMCM to re-lock failed (%d)\n",
+				p_adapter_id_str, locked);
+		}
+	}
+
+	NT_LOG(DBG, NTHW, "%s: De-asserting PTP RST\n", p_adapter_id_str);
+	nthw_field_clr_flush(p->mp_fld_rst_ptp);
+
+	/* POWER staging introduced in 9508-05-09 and always for 9512 */
+	if (n_fpga_product_id == 9508 && n_fpga_version <= 5 && n_fpga_revision <= 8) {
+		NT_LOG(DBG, NTHW, "%s: No power staging\n", p_adapter_id_str);
+
+	} else {
+		NT_LOG(DBG, NTHW, "%s: Staging power\n", p_adapter_id_str);
+		nthw_field_set_flush(p->mp_fld_power_pu_phy);	/* PHY power up */
+		nthw_field_clr_flush(p->mp_fld_power_pu_nseb);	/* NSEB power down */
+	}
+
+	NT_LOG(DBG, NTHW, "%s: %s: END\n", p_adapter_id_str, __func__);
+
+	return 0;
+}
+
+static int nthw_fpga_rst_nt200a0x_init(struct fpga_info_s *p_fpga_info,
+	struct nthw_fpga_rst_nt200a0x *p_rst)
+{
+	assert(p_fpga_info);
+
+	const char *const p_adapter_id_str = p_fpga_info->mp_adapter_id_str;
+	int res = -1;
+	int n_si_labs_clock_synth_model = -1;
+	uint8_t n_si_labs_clock_synth_i2c_addr = 0;
+	nthw_fpga_t *p_fpga = NULL;
+
+	p_fpga = p_fpga_info->mp_fpga;
+
+	NT_LOG(DBG, NTHW, "%s: %s: RAB init/reset\n", p_adapter_id_str, __func__);
+	nthw_rac_rab_reset(p_fpga_info->mp_nthw_rac);
+	nthw_rac_rab_setup(p_fpga_info->mp_nthw_rac);
+
+	res = nthw_fpga_avr_probe(p_fpga, 0);
+
+	res = nthw_fpga_iic_scan(p_fpga, 0, 0);
+	res = nthw_fpga_iic_scan(p_fpga, 2, 3);
+
+	/*
+	 * Detect clock synth model
+	 * check for NT200A02/NT200A01 HW-build2 - most commonly seen
+	 */
+	n_si_labs_clock_synth_i2c_addr = si5340_u23_i2c_addr_7bit;
+	n_si_labs_clock_synth_model =
+		nthw_fpga_silabs_detect(p_fpga, 0, n_si_labs_clock_synth_i2c_addr, 1);
+
+	if (n_si_labs_clock_synth_model == -1) {
+		/* check for old NT200A01 HW-build1 */
+		n_si_labs_clock_synth_i2c_addr = si5338_u23_i2c_addr_7bit;
+		n_si_labs_clock_synth_model =
+			nthw_fpga_silabs_detect(p_fpga, 0, n_si_labs_clock_synth_i2c_addr, 255);
+
+		if (n_si_labs_clock_synth_model == -1) {
+			NT_LOG(ERR, NTHW, "%s: Failed to detect clock synth model (%d)\n",
+				p_adapter_id_str, n_si_labs_clock_synth_model);
+			return -1;
+		}
+	}
+
+	p_rst->mn_si_labs_clock_synth_model = n_si_labs_clock_synth_model;
+	p_rst->mn_si_labs_clock_synth_i2c_addr = n_si_labs_clock_synth_i2c_addr;
+	p_rst->mn_hw_id = p_fpga_info->nthw_hw_info.hw_id;
+	NT_LOG(DBG, NTHW, "%s: %s: Si%04d @ 0x%02x\n", p_adapter_id_str, __func__,
+		p_rst->mn_si_labs_clock_synth_model, p_rst->mn_si_labs_clock_synth_i2c_addr);
+
+	return res;
+}
+
+static struct rst_nt200a0x_ops rst_nt200a0x_ops = { .nthw_fpga_rst_nt200a0x_init =
+		nthw_fpga_rst_nt200a0x_init,
+		.nthw_fpga_rst_nt200a0x_reset =
+			nthw_fpga_rst_nt200a0x_reset
+};
+
+static void __attribute__((constructor(65535))) rst_nt200a0x_ops_init(void)
+{
+	NT_LOG(INF, NTHW, "RST NT200A0X OPS INIT");
+	register_rst_nt200a0x_ops(&rst_nt200a0x_ops);
+}
diff --git a/drivers/net/ntnic/nthw/core/nt200a0x/reset/nthw_fpga_rst_nt200a0x.h b/drivers/net/ntnic/nthw/core/nt200a0x/reset/nthw_fpga_rst_nt200a0x.h
new file mode 100644
index 0000000000..af508bd2bd
--- /dev/null
+++ b/drivers/net/ntnic/nthw/core/nt200a0x/reset/nthw_fpga_rst_nt200a0x.h
@@ -0,0 +1,9 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef __NTHW_FPGA_RST_NT200A0X_H__
+#define __NTHW_FPGA_RST_NT200A0X_H__
+
+#endif	/* __NTHW_FPGA_RST_NT200A0X_H__ */
diff --git a/drivers/net/ntnic/nthw/core/nthw_fpga.c b/drivers/net/ntnic/nthw/core/nthw_fpga.c
new file mode 100644
index 0000000000..bc03ff97d2
--- /dev/null
+++ b/drivers/net/ntnic/nthw/core/nthw_fpga.c
@@ -0,0 +1,888 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#include "ntlog.h"
+
+#include "nthw_drv.h"
+#include "nthw_register.h"
+
+#include "nthw_fpga.h"
+
+#include "nthw_fpga_instances.h"
+#include "nthw_fpga_mod_str_map.h"
+
+#include "nthw_spi_v3.h"
+
+#include <arpa/inet.h>
+
+int nthw_fpga_get_param_info(struct fpga_info_s *p_fpga_info, nthw_fpga_t *p_fpga)
+{
+	mcu_info_t *p_mcu_info = &p_fpga_info->mcu_info;
+
+	const int n_nims = nthw_fpga_get_product_param(p_fpga, NT_NIMS, -1);
+	const int n_phy_ports = nthw_fpga_get_product_param(p_fpga, NT_PHY_PORTS, -1);
+	const int n_phy_quads = nthw_fpga_get_product_param(p_fpga, NT_PHY_QUADS, -1);
+	const int n_rx_ports = nthw_fpga_get_product_param(p_fpga, NT_RX_PORTS, -1);
+	const int n_tx_ports = nthw_fpga_get_product_param(p_fpga, NT_TX_PORTS, -1);
+	const int n_vf_offset = nthw_fpga_get_product_param(p_fpga, NT_HIF_VF_OFFSET, 4);
+
+	p_fpga_info->n_nims = n_nims;
+	p_fpga_info->n_phy_ports = n_phy_ports;
+	p_fpga_info->n_phy_quads = n_phy_quads;
+	p_fpga_info->n_rx_ports = n_rx_ports;
+	p_fpga_info->n_tx_ports = n_tx_ports;
+	p_fpga_info->n_vf_offset = n_vf_offset;
+	p_fpga_info->profile = FPGA_INFO_PROFILE_UNKNOWN;
+
+	/* Check for MCU */
+	if (nthw_fpga_get_product_param(p_fpga, NT_MCU_PRESENT, 0) != 0) {
+		p_mcu_info->mb_has_mcu = true;
+		/* Check MCU Type */
+		p_mcu_info->mn_mcu_type = nthw_fpga_get_product_param(p_fpga, NT_MCU_TYPE, -1);
+		/* MCU DRAM size */
+		p_mcu_info->mn_mcu_dram_size =
+			nthw_fpga_get_product_param(p_fpga, NT_MCU_DRAM_SIZE, -1);
+
+	} else {
+		p_mcu_info->mb_has_mcu = false;
+		p_mcu_info->mn_mcu_type = -1;
+		p_mcu_info->mn_mcu_dram_size = -1;
+	}
+
+	/* Check for VSWITCH FPGA */
+	if (nthw_fpga_get_product_param(p_fpga, NT_NFV_OVS_PRODUCT, 0) != 0) {
+		p_fpga_info->profile = FPGA_INFO_PROFILE_VSWITCH;
+
+	} else if (nthw_fpga_get_product_param(p_fpga, NT_IOA_PRESENT, 0) != 0) {
+		/* Check for VSWITCH FPGA - legacy */
+		p_fpga_info->profile = FPGA_INFO_PROFILE_VSWITCH;
+
+	} else if (nthw_fpga_get_product_param(p_fpga, NT_QM_PRESENT, 0) != 0) {
+		p_fpga_info->profile = FPGA_INFO_PROFILE_CAPTURE;
+
+	} else {
+		p_fpga_info->profile = FPGA_INFO_PROFILE_INLINE;
+	}
+
+	return 0;
+}
+
+int nthw_fpga_iic_scan(nthw_fpga_t *p_fpga, const int n_instance_no_begin,
+	const int n_instance_no_end)
+{
+	int i;
+
+	assert(n_instance_no_begin <= n_instance_no_end);
+
+	for (i = n_instance_no_begin; i <= n_instance_no_end; i++) {
+		nthw_iic_t *p_nthw_iic = nthw_iic_new();
+
+		if (p_nthw_iic) {
+			const int rc = nthw_iic_init(p_nthw_iic, p_fpga, i, 8);
+
+			if (rc == 0) {
+				nthw_iic_set_retry_params(p_nthw_iic, -1, 100, 100, 3, 3);
+				nthw_iic_scan(p_nthw_iic);
+			}
+
+			nthw_iic_delete(p_nthw_iic);
+			p_nthw_iic = NULL;
+		}
+	}
+
+	return 0;
+}
+
+int nthw_fpga_silabs_detect(nthw_fpga_t *p_fpga, const int n_instance_no, const int n_dev_addr,
+	const int n_page_reg_addr)
+{
+	const char *const p_adapter_id_str = p_fpga->p_fpga_info->mp_adapter_id_str;
+	(void)p_adapter_id_str;
+	uint64_t ident = -1;
+	int res = -1;
+
+	nthw_iic_t *p_nthw_iic = nthw_iic_new();
+
+	if (p_nthw_iic) {
+		uint8_t data;
+		uint8_t a_silabs_ident[8];
+		nthw_iic_init(p_nthw_iic, p_fpga, n_instance_no, 8);
+
+		data = 0;
+		/* switch to page 0 */
+		nthw_iic_write_data(p_nthw_iic, (uint8_t)n_dev_addr, (uint8_t)n_page_reg_addr, 1,
+			&data);
+		res = nthw_iic_read_data(p_nthw_iic, (uint8_t)n_dev_addr, 0x00,
+				sizeof(a_silabs_ident), a_silabs_ident);
+
+		if (res == 0) {
+			int i;
+
+			for (i = 0; i < (int)sizeof(a_silabs_ident); i++) {
+				ident <<= 8;
+				ident |= a_silabs_ident[i];
+			}
+		}
+
+		nthw_iic_delete(p_nthw_iic);
+		p_nthw_iic = NULL;
+
+		/* Conclude SiLabs part */
+		if (res == 0) {
+			if (a_silabs_ident[3] == 0x53) {
+				if (a_silabs_ident[2] == 0x40)
+					res = 5340;
+
+				else if (a_silabs_ident[2] == 0x41)
+					res = 5341;
+
+			} else if (a_silabs_ident[2] == 38) {
+				res = 5338;
+
+			} else {
+				res = -1;
+			}
+		}
+	}
+
+	NT_LOG(DBG, NTHW, "%s: %016" PRIX64 ": %d\n", p_adapter_id_str, ident, res);
+	return res;
+}
+
+/*
+ * Calculate CRC-16-CCITT of passed data
+ * CRC-16-CCITT ^16 + ^12 + ^5 + 1 (0x1021) (X.25, HDLC, XMODEM, Bluetooth,
+ *   SD, many others; known as CRC-CCITT)
+ */
+static uint16_t _crc16(uint8_t *buffer, size_t length)
+{
+	uint16_t seed = 0;
+
+	while (length--) {
+		seed = (uint16_t)(seed >> 8 | seed << 8);
+		seed = (uint16_t)(seed ^ *buffer++);
+		seed = (uint16_t)(seed ^ (seed & 0xff) >> 4);
+		seed = (uint16_t)(seed ^ seed << 8 << 4);
+		seed = (uint16_t)(seed ^ (seed & 0xff) << 4 << 1);
+	}
+
+	return seed;
+}
+
+int nthw_fpga_avr_probe(nthw_fpga_t *p_fpga, const int n_instance_no)
+{
+	struct fpga_info_s *p_fpga_info = p_fpga->p_fpga_info;
+	const char *const p_adapter_id_str = p_fpga_info->mp_adapter_id_str;
+	nthw_spi_v3_t *p_avr_spi;
+	int res = -1;
+
+	p_avr_spi = nthw_spi_v3_new();
+
+	if (p_avr_spi) {
+		struct avr_vpd_info_s {
+			/* avr info */
+			uint32_t n_avr_spi_version;
+			uint8_t n_avr_fw_ver_major;
+			uint8_t n_avr_fw_ver_minor;
+			uint8_t n_avr_fw_ver_micro;
+			uint8_t a_avr_fw_ver_str[50];
+			uint8_t a_avr_fw_plat_id_str[20];
+
+			/* vpd_eeprom_t */
+			uint8_t psu_hw_version;
+			uint8_t vpd_pn[GEN2_PN_SIZE];
+			uint8_t vpd_pba[GEN2_PBA_SIZE];
+			uint8_t vpd_sn[GEN2_SN_SIZE];
+			uint8_t vpd_board_name[GEN2_BNAME_SIZE];
+			uint8_t vpd_platform_section[GEN2_PLATFORM_SIZE];
+
+			/* board_info_t aka vpd_platform_section: */
+			uint32_t product_family;/* uint8_t 1: capture, 2: Inline, 3: analysis */
+			uint32_t feature_mask;	/* Bit 0: OC192 capable */
+			uint32_t invfeature_mask;
+			uint8_t no_of_macs;
+			uint8_t mac_address[6];
+			uint16_t custom_id;
+			uint8_t user_id[8];
+			/*
+			 * Reserved NT operations to monitor the reprogram count of user_id with
+			 * vpduser
+			 */
+			uint16_t user_id_erase_write_count;
+
+			/*
+			 * AVR_OP_SYSINFO: struct version_sysinfo_request_container
+			 * Which version of the sysinfo container to retrieve. Set to zero to fetch
+			 * latest. Offset zero of latest always contain an uint8_t version info
+			 */
+			uint8_t sysinfo_container_version;
+
+			/* AVR_OP_SYSINFO: struct AvrLibcVersion */
+			/* The constant __AVR_LIBC_VERSION__ */
+			uint32_t sysinfo_avr_libc_version;
+
+			/* AVR_OP_SYSINFO: struct AvrLibcSignature */
+			uint8_t sysinfo_signature_0;	/* The constant SIGNATURE_0 */
+			uint8_t sysinfo_signature_1;	/* The constant SIGNATURE_1 */
+			uint8_t sysinfo_signature_2;	/* The constant SIGNATURE_2 */
+
+			/* AVR_OP_SYSINFO: struct AvrOs */
+			uint8_t sysinfo_spi_version;	/* SPI command layer version */
+			/*
+			 * Hardware revision. Locked to eeprom address zero. Is also available via
+			 * VPD read opcode (prior to v1.4b, this is required)
+			 */
+			uint8_t sysinfo_hw_revision;
+			/*
+			 * Number of ticks/second (Note: Be aware this may become zero if timer
+			 * module is rewritten to a tickles system!)
+			 */
+			uint8_t sysinfo_ticks_per_second;
+			uint32_t sysinfo_uptime;/* Uptime in seconds since last AVR reset */
+			uint8_t sysinfo_osccal;	/* OSCCAL value */
+
+			/*
+			 * Meta data concluded/calculated from req/reply
+			 */
+			bool b_feature_mask_valid;
+			bool b_crc16_valid;
+			uint16_t n_crc16_stored;
+			uint16_t n_crc16_calced;
+			uint64_t n_mac_val;
+		};
+
+		struct avr_vpd_info_s avr_vpd_info;
+		struct tx_rx_buf tx_buf;
+		struct tx_rx_buf rx_buf;
+		char rx_data[MAX_AVR_CONTAINER_SIZE];
+		uint32_t u32;
+
+		memset(&avr_vpd_info, 0, sizeof(avr_vpd_info));
+
+		nthw_spi_v3_init(p_avr_spi, p_fpga, n_instance_no);
+
+		/* AVR_OP_SPI_VERSION */
+		tx_buf.size = 0;
+		tx_buf.p_buf = NULL;
+		rx_buf.size = sizeof(u32);
+		rx_buf.p_buf = &u32;
+		u32 = 0;
+		res = nthw_spi_v3_transfer(p_avr_spi, AVR_OP_SPI_VERSION, &tx_buf, &rx_buf);
+		avr_vpd_info.n_avr_spi_version = u32;
+		NT_LOG(DBG, NTHW, "%s: AVR%d: SPI_VER: %d\n", p_adapter_id_str, n_instance_no,
+			avr_vpd_info.n_avr_spi_version);
+
+		/* AVR_OP_VERSION */
+		tx_buf.size = 0;
+		tx_buf.p_buf = NULL;
+		rx_buf.size = sizeof(rx_data);
+		rx_buf.p_buf = &rx_data;
+		res = nthw_spi_v3_transfer(p_avr_spi, AVR_OP_VERSION, &tx_buf, &rx_buf);
+
+		avr_vpd_info.n_avr_fw_ver_major = rx_data[0];
+		avr_vpd_info.n_avr_fw_ver_minor = rx_data[1];
+		avr_vpd_info.n_avr_fw_ver_micro = rx_data[2];
+		NT_LOG(DBG, NTHW, "%s: AVR%d: FW_VER: %c.%c.%c\n", p_adapter_id_str, n_instance_no,
+			avr_vpd_info.n_avr_fw_ver_major, avr_vpd_info.n_avr_fw_ver_minor,
+			avr_vpd_info.n_avr_fw_ver_micro);
+
+		memcpy(avr_vpd_info.a_avr_fw_ver_str, &rx_data[0 + 3],
+			sizeof(avr_vpd_info.a_avr_fw_ver_str));
+		NT_LOG(DBG, NTHW, "%s: AVR%d: FW_VER_STR: '%.*s'\n", p_adapter_id_str,
+			n_instance_no, (int)sizeof(avr_vpd_info.a_avr_fw_ver_str),
+			avr_vpd_info.a_avr_fw_ver_str);
+
+		memcpy(avr_vpd_info.a_avr_fw_plat_id_str, &rx_data[0 + 3 + 50],
+			sizeof(avr_vpd_info.a_avr_fw_plat_id_str));
+		NT_LOG(DBG, NTHW, "%s: AVR%d: FW_HW_ID_STR: '%.*s'\n", p_adapter_id_str,
+			n_instance_no, (int)sizeof(avr_vpd_info.a_avr_fw_plat_id_str),
+			avr_vpd_info.a_avr_fw_plat_id_str);
+
+		snprintf(p_fpga_info->nthw_hw_info.hw_plat_id_str,
+			sizeof(p_fpga_info->nthw_hw_info.hw_plat_id_str), "%s",
+			(char *)avr_vpd_info.a_avr_fw_plat_id_str);
+		p_fpga_info->nthw_hw_info
+		.hw_plat_id_str[sizeof(p_fpga_info->nthw_hw_info.hw_plat_id_str) - 1] = 0;
+
+		/* AVR_OP_SYSINFO_2 */
+		tx_buf.size = 0;
+		tx_buf.p_buf = NULL;
+		rx_buf.size = sizeof(rx_data);
+		rx_buf.p_buf = &rx_data;
+		res = nthw_spi_v3_transfer(p_avr_spi, AVR_OP_SYSINFO_2, &tx_buf, &rx_buf);
+
+		if (res == 0 && avr_vpd_info.n_avr_spi_version >= 3 && rx_buf.size >= 16) {
+			if (rx_buf.size != 16) {
+				NT_LOG(WRN, NTHW,
+					"%s: AVR%d: SYSINFO2: reply is larger than expected: %04X %04X\n",
+					p_adapter_id_str, n_instance_no, rx_buf.size, 16);
+
+			} else {
+				NT_LOG(DBG, NTHW, "%s: AVR%d: SYSINFO2: OK: res=%d sz=%d\n",
+					p_adapter_id_str, n_instance_no, res, rx_buf.size);
+			}
+
+			avr_vpd_info.sysinfo_container_version = rx_data[0];
+			NT_LOG(DBG, NTHW, "%s: AVR%d: SYSINFO_REQ_VER: %d\n", p_adapter_id_str,
+				n_instance_no, avr_vpd_info.sysinfo_container_version);
+
+			memcpy(&avr_vpd_info.sysinfo_avr_libc_version, &rx_data[0 + 1],
+				sizeof(avr_vpd_info.sysinfo_avr_libc_version));
+			NT_LOG(DBG, NTHW, "%s: AVR%d: LIBC_VER: %d\n", p_adapter_id_str,
+				n_instance_no, avr_vpd_info.sysinfo_avr_libc_version);
+
+			avr_vpd_info.sysinfo_signature_0 = rx_data[5];
+			avr_vpd_info.sysinfo_signature_1 = rx_data[6];
+			avr_vpd_info.sysinfo_signature_2 = rx_data[7];
+			NT_LOG(DBG, NTHW, "%s: AVR%d: SIGNATURE: %02x%02x%02x\n", p_adapter_id_str,
+				n_instance_no, avr_vpd_info.sysinfo_signature_0,
+				avr_vpd_info.sysinfo_signature_1, avr_vpd_info.sysinfo_signature_2);
+
+			avr_vpd_info.sysinfo_spi_version = rx_data[8];
+			NT_LOG(DBG, NTHW, "%s: AVR%d: SPI_VER: %d\n", p_adapter_id_str,
+				n_instance_no, avr_vpd_info.sysinfo_spi_version);
+
+			avr_vpd_info.sysinfo_hw_revision = rx_data[9];
+			NT_LOG(DBG, NTHW, "%s: AVR%d: HW_REV: %d\n", p_adapter_id_str,
+				n_instance_no, avr_vpd_info.sysinfo_hw_revision);
+
+			avr_vpd_info.sysinfo_ticks_per_second = rx_data[10];
+			NT_LOG(DBG, NTHW, "%s: AVR%d: TICKS_PER_SEC: %d\n", p_adapter_id_str,
+				n_instance_no, avr_vpd_info.sysinfo_ticks_per_second);
+
+			memcpy(&avr_vpd_info.sysinfo_uptime, &rx_data[11],
+				sizeof(avr_vpd_info.sysinfo_uptime));
+			NT_LOG(DBG, NTHW, "%s: AVR%d: UPTIME: %d\n", p_adapter_id_str,
+				n_instance_no, avr_vpd_info.sysinfo_uptime);
+
+			avr_vpd_info.sysinfo_osccal = rx_data[15];
+			NT_LOG(DBG, NTHW, "%s: AVR%d: OSCCAL: %d\n", p_adapter_id_str,
+				n_instance_no, avr_vpd_info.sysinfo_osccal);
+
+			{
+				bool b_spi_ver_match = (avr_vpd_info.n_avr_spi_version ==
+						avr_vpd_info.sysinfo_spi_version);
+				(void)b_spi_ver_match;
+				NT_LOG(DBG, NTHW, "%s: AVR%d: SPI_VER_TST: %s (%d %d)\n",
+					p_adapter_id_str, n_instance_no,
+					(b_spi_ver_match ? "OK" : "MISMATCH"),
+					avr_vpd_info.n_avr_spi_version,
+					avr_vpd_info.sysinfo_spi_version);
+			}
+			/* SYSINFO2: if response: only populate hw_id not hw_id_emulated */
+			p_fpga_info->nthw_hw_info.hw_id = avr_vpd_info.sysinfo_hw_revision;
+
+		} else {
+			/* AVR_OP_SYSINFO */
+			tx_buf.size = 0;
+			tx_buf.p_buf = NULL;
+			rx_buf.size = sizeof(rx_data);
+			rx_buf.p_buf = &rx_data;
+			res = nthw_spi_v3_transfer(p_avr_spi, AVR_OP_SYSINFO, &tx_buf, &rx_buf);
+
+			if (res == 0 && avr_vpd_info.n_avr_spi_version >= 3 && rx_buf.size >= 16) {
+				if (rx_buf.size != 16) {
+					NT_LOG(WRN, NTHW,
+						"%s: AVR%d: SYSINFO: reply is larger than expected: %04X %04X\n",
+						p_adapter_id_str, n_instance_no, rx_buf.size, 16);
+
+				} else {
+					NT_LOG(DBG, NTHW, "%s: AVR%d: SYSINFO: OK: res=%d sz=%d\n",
+						p_adapter_id_str, n_instance_no, res, rx_buf.size);
+				}
+
+				avr_vpd_info.sysinfo_container_version = rx_data[0];
+				NT_LOG(DBG, NTHW, "%s: AVR%d: SYSINFO_REQ_VER: %d\n",
+					p_adapter_id_str, n_instance_no,
+					avr_vpd_info.sysinfo_container_version);
+
+				memcpy(&avr_vpd_info.sysinfo_avr_libc_version, &rx_data[0 + 1],
+					sizeof(avr_vpd_info.sysinfo_avr_libc_version));
+				NT_LOG(DBG, NTHW, "%s: AVR%d: LIBC_VER: %d\n", p_adapter_id_str,
+					n_instance_no, avr_vpd_info.sysinfo_avr_libc_version);
+
+				avr_vpd_info.sysinfo_signature_0 = rx_data[5];
+				avr_vpd_info.sysinfo_signature_1 = rx_data[6];
+				avr_vpd_info.sysinfo_signature_2 = rx_data[7];
+				NT_LOG(DBG, NTHW, "%s: AVR%d: SIGNATURE: %02x%02x%02x\n",
+					p_adapter_id_str, n_instance_no,
+					avr_vpd_info.sysinfo_signature_0,
+					avr_vpd_info.sysinfo_signature_1,
+					avr_vpd_info.sysinfo_signature_2);
+
+				avr_vpd_info.sysinfo_spi_version = rx_data[8];
+				NT_LOG(DBG, NTHW, "%s: AVR%d: SPI_VER: %d\n", p_adapter_id_str,
+					n_instance_no, avr_vpd_info.sysinfo_spi_version);
+
+				avr_vpd_info.sysinfo_hw_revision = rx_data[9];
+				NT_LOG(DBG, NTHW, "%s: AVR%d: HW_REV: %d\n", p_adapter_id_str,
+					n_instance_no, avr_vpd_info.sysinfo_hw_revision);
+				NT_LOG(INF, NTHW, "%s: AVR%d: HW_REV: %d\n", p_adapter_id_str,
+					n_instance_no, avr_vpd_info.sysinfo_hw_revision);
+
+				avr_vpd_info.sysinfo_ticks_per_second = rx_data[10];
+				NT_LOG(DBG, NTHW, "%s: AVR%d: TICKS_PER_SEC: %d\n",
+					p_adapter_id_str, n_instance_no,
+					avr_vpd_info.sysinfo_ticks_per_second);
+
+				memcpy(&avr_vpd_info.sysinfo_uptime, &rx_data[11],
+					sizeof(avr_vpd_info.sysinfo_uptime));
+				NT_LOG(DBG, NTHW, "%s: AVR%d: UPTIME: %d\n", p_adapter_id_str,
+					n_instance_no, avr_vpd_info.sysinfo_uptime);
+
+				avr_vpd_info.sysinfo_osccal = rx_data[15];
+				NT_LOG(DBG, NTHW, "%s: AVR%d: OSCCAL: %d\n", p_adapter_id_str,
+					n_instance_no, avr_vpd_info.sysinfo_osccal);
+
+				{
+					bool b_spi_ver_match = (avr_vpd_info.n_avr_spi_version ==
+							avr_vpd_info.sysinfo_spi_version);
+					(void)b_spi_ver_match;
+					NT_LOG(DBG, NTHW, "%s: AVR%d: SPI_VER_TST: %s (%d %d)\n",
+						p_adapter_id_str, n_instance_no,
+						(b_spi_ver_match ? "OK" : "MISMATCH"),
+						avr_vpd_info.n_avr_spi_version,
+						avr_vpd_info.sysinfo_spi_version);
+				}
+
+				p_fpga_info->nthw_hw_info.hw_id = avr_vpd_info.sysinfo_hw_revision;
+				p_fpga_info->nthw_hw_info.hw_id_emulated =
+					avr_vpd_info.sysinfo_hw_revision;
+
+			} else {
+				NT_LOG(ERR, NTHW, "%s: AVR%d: SYSINFO: NA: res=%d sz=%d\n",
+					p_adapter_id_str, n_instance_no, res, rx_buf.size);
+			}
+		}
+
+		/* AVR_OP_VPD_READ */
+		tx_buf.size = 0;
+		tx_buf.p_buf = NULL;
+		rx_buf.size = sizeof(rx_data);
+		rx_buf.p_buf = &rx_data;
+		res = nthw_spi_v3_transfer(p_avr_spi, AVR_OP_VPD_READ, &tx_buf, &rx_buf);
+
+		if (res == 0 && avr_vpd_info.n_avr_spi_version >= 3 &&
+			rx_buf.size >= GEN2_VPD_SIZE_TOTAL) {
+			avr_vpd_info.n_crc16_calced = _crc16(rx_buf.p_buf, rx_buf.size - 2);
+			memcpy(&avr_vpd_info.n_crc16_stored, &rx_data[rx_buf.size - 2],
+				sizeof(avr_vpd_info.n_crc16_stored));
+			NT_LOG(DBG, NTHW, "%s: AVR%d: VPD_CRC: %04X %04X\n", p_adapter_id_str,
+				n_instance_no, avr_vpd_info.n_crc16_stored,
+				avr_vpd_info.n_crc16_calced);
+
+			avr_vpd_info.b_crc16_valid =
+				(avr_vpd_info.n_crc16_stored == avr_vpd_info.n_crc16_calced);
+			NT_LOG(DBG, NTHW, "%s: AVR%d: CRC_TST: %s\n", p_adapter_id_str,
+				n_instance_no, (avr_vpd_info.b_crc16_valid ? "OK" : "ERROR"));
+
+			if (avr_vpd_info.b_crc16_valid) {
+				memcpy(&avr_vpd_info.psu_hw_version, &rx_data[0],
+					sizeof(avr_vpd_info.psu_hw_version));
+				NT_LOG(DBG, NTHW, "%s: AVR%d: PSU_HW_VER: %d\n", p_adapter_id_str,
+					n_instance_no, avr_vpd_info.psu_hw_version);
+
+				memcpy(&avr_vpd_info.vpd_pn, &rx_data[0 + 1],
+					sizeof(avr_vpd_info.vpd_pn));
+				NT_LOG(DBG, NTHW, "%s: AVR%d: PN: '%.*s'\n", p_adapter_id_str,
+					n_instance_no, GEN2_PN_SIZE, avr_vpd_info.vpd_pn);
+
+				memcpy(&avr_vpd_info.vpd_pba, &rx_data[0 + 1 + GEN2_PN_SIZE],
+					sizeof(avr_vpd_info.vpd_pba));
+				NT_LOG(DBG, NTHW, "%s: AVR%d: PBA: '%.*s'\n", p_adapter_id_str,
+					n_instance_no, GEN2_PBA_SIZE, avr_vpd_info.vpd_pba);
+
+				memcpy(&avr_vpd_info.vpd_sn,
+					&rx_data[0 + 1 + GEN2_PN_SIZE + GEN2_PBA_SIZE],
+					sizeof(avr_vpd_info.vpd_sn));
+				NT_LOG(DBG, NTHW, "%s: AVR%d: SN: '%.*s'\n", p_adapter_id_str,
+					n_instance_no, GEN2_SN_SIZE, avr_vpd_info.vpd_sn);
+
+				memcpy(&avr_vpd_info.vpd_board_name,
+					&rx_data[0 + 1 + GEN2_PN_SIZE + GEN2_PBA_SIZE +
+						GEN2_SN_SIZE],
+					sizeof(avr_vpd_info.vpd_board_name));
+				NT_LOG(DBG, NTHW, "%s: AVR%d: BN: '%.*s'\n", p_adapter_id_str,
+					n_instance_no, GEN2_BNAME_SIZE,
+					avr_vpd_info.vpd_board_name);
+
+				union mac_u {
+					uint8_t a_u8[8];
+					uint16_t a_u16[4];
+					uint32_t a_u32[2];
+					uint64_t a_u64[1];
+				} mac;
+
+				/* vpd_platform_section */
+				uint8_t *p_vpd_board_info =
+					(uint8_t *)(&rx_data[1 + GEN2_PN_SIZE + GEN2_PBA_SIZE +
+							GEN2_SN_SIZE + GEN2_BNAME_SIZE]);
+				memcpy(&avr_vpd_info.product_family, &p_vpd_board_info[0],
+					sizeof(avr_vpd_info.product_family));
+				NT_LOG(DBG, NTHW, "%s: AVR%d: PROD_FAM: %d\n", p_adapter_id_str,
+					n_instance_no, avr_vpd_info.product_family);
+
+				memcpy(&avr_vpd_info.feature_mask, &p_vpd_board_info[0 + 4],
+					sizeof(avr_vpd_info.feature_mask));
+				NT_LOG(DBG, NTHW, "%s: AVR%d: FMSK_VAL: 0x%08X\n",
+					p_adapter_id_str, n_instance_no, avr_vpd_info.feature_mask);
+
+				memcpy(&avr_vpd_info.invfeature_mask, &p_vpd_board_info[0 + 4 + 4],
+					sizeof(avr_vpd_info.invfeature_mask));
+				NT_LOG(DBG, NTHW, "%s: AVR%d: FMSK_INV: 0x%08X\n",
+					p_adapter_id_str, n_instance_no,
+					avr_vpd_info.invfeature_mask);
+
+				avr_vpd_info.b_feature_mask_valid =
+					(avr_vpd_info.feature_mask ==
+						~avr_vpd_info.invfeature_mask);
+				NT_LOG(DBG, NTHW, "%s: AVR%d: FMSK_TST: %s\n", p_adapter_id_str,
+					n_instance_no,
+					(avr_vpd_info.b_feature_mask_valid ? "OK" : "ERROR"));
+
+				memcpy(&avr_vpd_info.no_of_macs, &p_vpd_board_info[0 + 4 + 4 + 4],
+					sizeof(avr_vpd_info.no_of_macs));
+				NT_LOG(DBG, NTHW, "%s: AVR%d: NUM_MACS: %d\n", p_adapter_id_str,
+					n_instance_no, avr_vpd_info.no_of_macs);
+
+				memcpy(&avr_vpd_info.mac_address,
+					&p_vpd_board_info[0 + 4 + 4 + 4 + 1],
+					sizeof(avr_vpd_info.mac_address));
+				NT_LOG(DBG, NTHW,
+					"%s: AVR%d: MAC_ADDR: %02x:%02x:%02x:%02x:%02x:%02x\n",
+					p_adapter_id_str, n_instance_no,
+					avr_vpd_info.mac_address[0], avr_vpd_info.mac_address[1],
+					avr_vpd_info.mac_address[2], avr_vpd_info.mac_address[3],
+					avr_vpd_info.mac_address[4], avr_vpd_info.mac_address[5]);
+
+				mac.a_u64[0] = 0;
+				memcpy(&mac.a_u8[2], &avr_vpd_info.mac_address,
+					sizeof(avr_vpd_info.mac_address));
+				{
+					const uint32_t u1 = ntohl(mac.a_u32[0]);
+
+					if (u1 != mac.a_u32[0]) {
+						const uint32_t u0 = ntohl(mac.a_u32[1]);
+						mac.a_u32[0] = u0;
+						mac.a_u32[1] = u1;
+					}
+				}
+				avr_vpd_info.n_mac_val = mac.a_u64[0];
+				NT_LOG(DBG, NTHW, "%s: AVR%d: MAC_U64: %012" PRIX64 "\n",
+					p_adapter_id_str, n_instance_no, avr_vpd_info.n_mac_val);
+			}
+
+			p_fpga_info->nthw_hw_info.vpd_info.mn_mac_addr_count =
+				avr_vpd_info.no_of_macs;
+			p_fpga_info->nthw_hw_info.vpd_info.mn_mac_addr_value =
+				avr_vpd_info.n_mac_val;
+			memcpy(p_fpga_info->nthw_hw_info.vpd_info.ma_mac_addr_octets,
+				avr_vpd_info.mac_address,
+				ARRAY_SIZE(p_fpga_info->nthw_hw_info.vpd_info.ma_mac_addr_octets));
+
+		} else {
+			NT_LOG(ERR, NTHW, "%s:%u: res=%d\n", __func__, __LINE__, res);
+			NT_LOG(ERR, NTHW, "%s: AVR%d: SYSINFO2: NA: res=%d sz=%d\n",
+				p_adapter_id_str, n_instance_no, res, rx_buf.size);
+		}
+	}
+
+	return res;
+}
+
+/*
+ * NT50B01, NT200A02, NT200A01-HWbuild2
+ */
+int nthw_fpga_si5340_clock_synth_init_fmt2(nthw_fpga_t *p_fpga, const uint8_t n_iic_addr,
+	const clk_profile_data_fmt2_t *p_clk_profile,
+	const int n_clk_profile_rec_cnt)
+{
+	int res;
+	nthw_iic_t *p_nthw_iic = nthw_iic_new();
+	nthw_si5340_t *p_nthw_si5340 = nthw_si5340_new();
+
+	assert(p_nthw_iic);
+	assert(p_nthw_si5340);
+	nthw_iic_init(p_nthw_iic, p_fpga, 0, 8);/* I2C cycle time 125Mhz ~ 8ns */
+
+	nthw_si5340_init(p_nthw_si5340, p_nthw_iic, n_iic_addr);/* si5340_u23_i2c_addr_7bit */
+	res = nthw_si5340_config_fmt2(p_nthw_si5340, p_clk_profile, n_clk_profile_rec_cnt);
+	nthw_si5340_delete(p_nthw_si5340);
+	p_nthw_si5340 = NULL;
+
+	return res;
+}
+
+int nthw_fpga_init(struct fpga_info_s *p_fpga_info)
+{
+	const char *const p_adapter_id_str = p_fpga_info->mp_adapter_id_str;
+
+	nthw_hif_t *p_nthw_hif = NULL;
+	nthw_pcie3_t *p_nthw_pcie3 = NULL;
+	nthw_rac_t *p_nthw_rac = NULL;
+	nthw_tsm_t *p_nthw_tsm = NULL;
+
+	mcu_info_t *p_mcu_info = &p_fpga_info->mcu_info;
+	(void)p_mcu_info;
+	uint64_t n_fpga_ident = 0;
+	nthw_fpga_mgr_t *p_fpga_mgr = NULL;
+	nthw_fpga_t *p_fpga = NULL;
+
+	char s_fpga_prod_ver_rev_str[32] = { 0 };
+
+	int res = 0;
+
+	assert(p_fpga_info);
+
+	{
+		const uint64_t n_fpga_ident = nthw_fpga_read_ident(p_fpga_info);
+		const uint32_t n_fpga_build_time = nthw_fpga_read_buildtime(p_fpga_info);
+		const int n_fpga_type_id = nthw_fpga_extract_type_id(n_fpga_ident);
+		const int n_fpga_prod_id = nthw_fpga_extract_prod_id(n_fpga_ident);
+		const int n_fpga_ver_id = nthw_fpga_extract_ver_id(n_fpga_ident);
+		const int n_fpga_rev_id = nthw_fpga_extract_rev_id(n_fpga_ident);
+
+		p_fpga_info->n_fpga_ident = n_fpga_ident;
+		p_fpga_info->n_fpga_type_id = n_fpga_type_id;
+		p_fpga_info->n_fpga_prod_id = n_fpga_prod_id;
+		p_fpga_info->n_fpga_ver_id = n_fpga_ver_id;
+		p_fpga_info->n_fpga_rev_id = n_fpga_rev_id;
+		p_fpga_info->n_fpga_build_time = n_fpga_build_time;
+
+		snprintf(s_fpga_prod_ver_rev_str, sizeof(s_fpga_prod_ver_rev_str),
+			"%04d-%04d-%02d-%02d", n_fpga_type_id, n_fpga_prod_id, n_fpga_ver_id,
+			n_fpga_rev_id);
+
+		NT_LOG(INF, NTHW, "%s: FPGA %s (%" PRIX64 ") [%08X]\n", p_adapter_id_str,
+			s_fpga_prod_ver_rev_str, n_fpga_ident, n_fpga_build_time);
+	}
+
+	n_fpga_ident = p_fpga_info->n_fpga_ident;
+
+	p_fpga_mgr = nthw_fpga_mgr_new();
+	nthw_fpga_mgr_init(p_fpga_mgr, nthw_fpga_instances,
+		(const void *)sa_nthw_fpga_mod_str_map);
+	nthw_fpga_mgr_log_dump(p_fpga_mgr);
+	p_fpga = nthw_fpga_mgr_query_fpga(p_fpga_mgr, n_fpga_ident, p_fpga_info);
+	p_fpga_info->mp_fpga = p_fpga;
+
+	if (p_fpga == NULL) {
+		NT_LOG(ERR, NTHW, "%s: Unsupported FPGA: %s (%08X)\n", p_adapter_id_str,
+			s_fpga_prod_ver_rev_str, p_fpga_info->n_fpga_build_time);
+		return -1;
+	}
+
+	if (p_fpga_mgr) {
+		nthw_fpga_mgr_delete(p_fpga_mgr);
+		p_fpga_mgr = NULL;
+	}
+
+	/* Read Fpga param info */
+	nthw_fpga_get_param_info(p_fpga_info, p_fpga);
+
+	/* debug: report params */
+	NT_LOG(DBG, NTHW, "%s: NT_NIMS=%d\n", p_adapter_id_str, p_fpga_info->n_nims);
+	NT_LOG(DBG, NTHW, "%s: NT_PHY_PORTS=%d\n", p_adapter_id_str, p_fpga_info->n_phy_ports);
+	NT_LOG(DBG, NTHW, "%s: NT_PHY_QUADS=%d\n", p_adapter_id_str, p_fpga_info->n_phy_quads);
+	NT_LOG(DBG, NTHW, "%s: NT_RX_PORTS=%d\n", p_adapter_id_str, p_fpga_info->n_rx_ports);
+	NT_LOG(DBG, NTHW, "%s: NT_TX_PORTS=%d\n", p_adapter_id_str, p_fpga_info->n_tx_ports);
+	NT_LOG(DBG, NTHW, "%s: nProfile=%d\n", p_adapter_id_str, (int)p_fpga_info->profile);
+	NT_LOG(DBG, NTHW, "%s: bHasMcu=%d\n", p_adapter_id_str, p_mcu_info->mb_has_mcu);
+	NT_LOG(DBG, NTHW, "%s: McuType=%d\n", p_adapter_id_str, p_mcu_info->mn_mcu_type);
+	NT_LOG(DBG, NTHW, "%s: McuDramSize=%d\n", p_adapter_id_str, p_mcu_info->mn_mcu_dram_size);
+
+	p_nthw_rac = nthw_rac_new();
+
+	if (p_nthw_rac == NULL) {
+		NT_LOG(ERR, NTHW, "%s: Unsupported FPGA: RAC is not found: %s (%08X)\n",
+			p_adapter_id_str, s_fpga_prod_ver_rev_str, p_fpga_info->n_fpga_build_time);
+		return -1;
+	}
+
+	nthw_rac_init(p_nthw_rac, p_fpga, p_fpga_info);
+	nthw_rac_rab_flush(p_nthw_rac);
+	p_fpga_info->mp_nthw_rac = p_nthw_rac;
+
+	/* special case: values below 0x100 will disable debug on RAC communication */
+	{
+		const int n_fpga_initial_debug_mode = p_fpga_info->n_fpga_debug_mode;
+		nthw_fpga_set_debug_mode(p_fpga, n_fpga_initial_debug_mode);
+	}
+	bool included = true;
+	struct nt200a0x_ops *nt200a0x_ops = get_nt200a0x_ops();
+	struct nt50b0x_ops *nt50b0x_ops = get_nt50b0x_ops();
+	struct nt400dxx_ops *nt400dxx_ops = get_nt400dxx_ops();
+
+	switch (p_fpga_info->n_nthw_adapter_id) {
+	case NT_HW_ADAPTER_ID_NT200A01:	/* fallthrough */
+	case NT_HW_ADAPTER_ID_NT200A02:
+		if (nt200a0x_ops != NULL)
+			res = nt200a0x_ops->nthw_fpga_nt200a0x_init(p_fpga_info);
+
+		else
+			included = false;
+
+		break;
+
+	case NT_HW_ADAPTER_ID_NT50B01:
+		if (nt50b0x_ops)
+			res = nt50b0x_ops->nthw_fpga_nt50b0x_init(p_fpga_info);
+
+		else
+			included = false;
+
+		break;
+
+	case NT_HW_ADAPTER_ID_NT400D11:
+		if (nt400dxx_ops != NULL)
+			res = nt400dxx_ops->nthw_fpga_nt400dxx_init(p_fpga_info);
+
+		else
+			included = false;
+
+		break;
+
+	default:
+		NT_LOG(ERR, NTHW, "%s: Unsupported HW product id: %d\n", p_adapter_id_str,
+			p_fpga_info->n_nthw_adapter_id);
+		res = -1;
+		break;
+	}
+
+	if (!included) {
+		NT_LOG(ERR, NTHW, "%s: NOT INCLUDED HW product: %d\n", p_adapter_id_str,
+			p_fpga_info->n_nthw_adapter_id);
+		res = -1;
+	}
+
+	if (res) {
+		NT_LOG(ERR, NTHW, "%s: status: 0x%08X\n", p_adapter_id_str, res);
+		return res;
+	}
+
+	res = nthw_pcie3_init(NULL, p_fpga, 0);	/* Probe for module */
+
+	if (res == 0) {
+		p_nthw_pcie3 = nthw_pcie3_new();
+
+		if (p_nthw_pcie3) {
+			res = nthw_pcie3_init(p_nthw_pcie3, p_fpga, 0);
+
+			if (res == 0) {
+				NT_LOG(DBG, NTHW, "%s: Pcie3 module found\n", p_adapter_id_str);
+				nthw_pcie3_trigger_sample_time(p_nthw_pcie3);
+
+			} else {
+				nthw_pcie3_delete(p_nthw_pcie3);
+				p_nthw_pcie3 = NULL;
+			}
+		}
+
+		p_fpga_info->mp_nthw_pcie3 = p_nthw_pcie3;
+	}
+
+	if (p_nthw_pcie3 == NULL) {
+		p_nthw_hif = nthw_hif_new();
+
+		if (p_nthw_hif) {
+			res = nthw_hif_init(p_nthw_hif, p_fpga, 0);
+
+			if (res == 0) {
+				NT_LOG(DBG, NTHW, "%s: Hif module found\n", p_adapter_id_str);
+				nthw_hif_trigger_sample_time(p_nthw_hif);
+
+			} else {
+				nthw_hif_delete(p_nthw_hif);
+				p_nthw_hif = NULL;
+			}
+		}
+	}
+
+	p_fpga_info->mp_nthw_hif = p_nthw_hif;
+
+	p_nthw_tsm = nthw_tsm_new();
+
+	if (p_nthw_tsm) {
+		nthw_tsm_init(p_nthw_tsm, p_fpga, 0);
+
+		nthw_tsm_set_config_ts_format(p_nthw_tsm, 1);	/* 1 = TSM: TS format native */
+
+		/* Timer T0 - stat toggle timer */
+		nthw_tsm_set_timer_t0_enable(p_nthw_tsm, false);
+		nthw_tsm_set_timer_t0_max_count(p_nthw_tsm, 50 * 1000 * 1000);	/* ns */
+		nthw_tsm_set_timer_t0_enable(p_nthw_tsm, true);
+
+		/* Timer T1 - keep alive timer */
+		nthw_tsm_set_timer_t1_enable(p_nthw_tsm, false);
+		nthw_tsm_set_timer_t1_max_count(p_nthw_tsm, 100 * 1000 * 1000);	/* ns */
+		nthw_tsm_set_timer_t1_enable(p_nthw_tsm, true);
+	}
+
+	p_fpga_info->mp_nthw_tsm = p_nthw_tsm;
+
+	/* TSM sample triggering: test validation... */
+#if defined(DEBUG) && (1)
+	{
+		uint64_t n_time, n_ts;
+		int i;
+
+		for (i = 0; i < 4; i++) {
+			if (p_nthw_hif)
+				nthw_hif_trigger_sample_time(p_nthw_hif);
+
+			else if (p_nthw_pcie3)
+				nthw_pcie3_trigger_sample_time(p_nthw_pcie3);
+
+			nthw_tsm_get_time(p_nthw_tsm, &n_time);
+			nthw_tsm_get_ts(p_nthw_tsm, &n_ts);
+
+			NT_LOG(DBG, NTHW, "%s: TSM time: %016" PRIX64 " %016" PRIX64 "\n",
+				p_adapter_id_str, n_time, n_ts);
+
+			nt_os_wait_usec(1000);
+		}
+	}
+#endif
+
+	return res;
+}
+
+int nthw_fpga_shutdown(struct fpga_info_s *p_fpga_info)
+{
+	int res = -1;
+
+	if (p_fpga_info) {
+		if (p_fpga_info && p_fpga_info->mp_nthw_rac)
+			res = nthw_rac_rab_reset(p_fpga_info->mp_nthw_rac);
+	}
+
+	return res;
+}
+
+static struct nt200a0x_ops *nt200a0x_ops;
+
+void register_nt200a0x_ops(struct nt200a0x_ops *ops)
+{
+	nt200a0x_ops = ops;
+}
+
+struct nt200a0x_ops *get_nt200a0x_ops(void)
+{
+	return nt200a0x_ops;
+}
+
+static struct nt50b0x_ops *nt50b0x_ops;
+
+struct nt50b0x_ops *get_nt50b0x_ops(void)
+{
+	return nt50b0x_ops;
+}
+
+static struct nt400dxx_ops *nt400dxx_ops;
+
+struct nt400dxx_ops *get_nt400dxx_ops(void)
+{
+	return nt400dxx_ops;
+}
diff --git a/drivers/net/ntnic/nthw/core/nthw_fpga_rst.c b/drivers/net/ntnic/nthw/core/nthw_fpga_rst.c
new file mode 100644
index 0000000000..e0fb0ec3d8
--- /dev/null
+++ b/drivers/net/ntnic/nthw/core/nthw_fpga_rst.c
@@ -0,0 +1,10 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#include "ntlog.h"
+
+#include "nthw_fpga.h"
+
+#include "nthw_fpga_rst.h"
diff --git a/drivers/net/ntnic/nthw/core/nthw_hif.c b/drivers/net/ntnic/nthw/core/nthw_hif.c
new file mode 100644
index 0000000000..b35b456528
--- /dev/null
+++ b/drivers/net/ntnic/nthw/core/nthw_hif.c
@@ -0,0 +1,312 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#include "nt_util.h"
+#include "ntlog.h"
+
+#include "nthw_drv.h"
+#include "nthw_register.h"
+
+#include "nthw_hif.h"
+
+nthw_hif_t *nthw_hif_new(void)
+{
+	nthw_hif_t *p = malloc(sizeof(nthw_hif_t));
+
+	if (p)
+		memset(p, 0, sizeof(nthw_hif_t));
+
+	return p;
+}
+
+void nthw_hif_delete(nthw_hif_t *p)
+{
+	if (p) {
+		memset(p, 0, sizeof(nthw_hif_t));
+		free(p);
+	}
+}
+
+int nthw_hif_init(nthw_hif_t *p, nthw_fpga_t *p_fpga, int n_instance)
+{
+	const char *const p_adapter_id_str = p_fpga->p_fpga_info->mp_adapter_id_str;
+	(void)p_adapter_id_str;
+	nthw_module_t *mod = nthw_fpga_query_module(p_fpga, MOD_HIF, n_instance);
+
+	if (p == NULL)
+		return mod == NULL ? -1 : 0;
+
+	if (mod == NULL) {
+		NT_LOG(ERR, NTHW, "%s: HIF %d: no such instance\n",
+			p_fpga->p_fpga_info->mp_adapter_id_str, n_instance);
+		return -1;
+	}
+
+	p->mp_fpga = p_fpga;
+	p->mn_instance = n_instance;
+	p->mp_mod_hif = mod;
+
+	/* default for (Xilinx-based) products until august 2022: (1e6/4000 = 250 MHz) */
+	p->mn_fpga_param_hif_per_ps = nthw_fpga_get_product_param(p->mp_fpga, NT_HIF_PER_PS, 4000);
+	p->mn_fpga_hif_ref_clk_freq =
+		(uint32_t)(1000000000000ULL / (unsigned int)p->mn_fpga_param_hif_per_ps);
+
+	p->mp_reg_prod_id_lsb = nthw_module_get_register(p->mp_mod_hif, HIF_PROD_ID_LSB);
+	p->mp_fld_prod_id_lsb_rev_id =
+		nthw_register_get_field(p->mp_reg_prod_id_lsb, HIF_PROD_ID_LSB_REV_ID);
+	p->mp_fld_prod_id_lsb_ver_id =
+		nthw_register_get_field(p->mp_reg_prod_id_lsb, HIF_PROD_ID_LSB_VER_ID);
+	p->mp_fld_prod_id_lsb_group_id =
+		nthw_register_get_field(p->mp_reg_prod_id_lsb, HIF_PROD_ID_LSB_GROUP_ID);
+
+	p->mp_reg_prod_id_msb = nthw_module_get_register(p->mp_mod_hif, HIF_PROD_ID_MSB);
+	p->mp_fld_prod_id_msb_type_id =
+		nthw_register_get_field(p->mp_reg_prod_id_msb, HIF_PROD_ID_MSB_TYPE_ID);
+	p->mp_fld_prod_id_msb_build_no =
+		nthw_register_get_field(p->mp_reg_prod_id_msb, HIF_PROD_ID_MSB_BUILD_NO);
+
+	p->mp_reg_build_time = nthw_module_get_register(p->mp_mod_hif, HIF_BUILD_TIME);
+	p->mp_fld_build_time = nthw_register_get_field(p->mp_reg_build_time, HIF_BUILD_TIME_TIME);
+
+	p->mn_fpga_id_prod = nthw_field_get_updated(p->mp_fld_prod_id_lsb_group_id);
+	p->mn_fpga_id_ver = nthw_field_get_updated(p->mp_fld_prod_id_lsb_ver_id);
+	p->mn_fpga_id_rev = nthw_field_get_updated(p->mp_fld_prod_id_lsb_rev_id);
+	p->mn_fpga_id_build_no = nthw_field_get_updated(p->mp_fld_prod_id_msb_build_no);
+	p->mn_fpga_id_item = nthw_field_get_updated(p->mp_fld_prod_id_msb_type_id);
+
+	NT_LOG(DBG, NTHW, "%s: HIF %d: %s: %d-%d-%d-%d-%d\n", p_adapter_id_str, p->mn_instance,
+		__func__, p->mn_fpga_id_item, p->mn_fpga_id_prod, p->mn_fpga_id_ver,
+		p->mn_fpga_id_rev, p->mn_fpga_id_build_no);
+	NT_LOG(DBG, NTHW, "%s: HIF %d: %s: HIF ref clock: %d Hz (%d ticks/ps)\n", p_adapter_id_str,
+		p->mn_instance, __func__, p->mn_fpga_hif_ref_clk_freq, p->mn_fpga_param_hif_per_ps);
+
+	p->mp_reg_build_seed = NULL;	/* Reg/Fld not present on HIF */
+
+	if (p->mp_reg_build_seed)
+		p->mp_fld_build_seed = NULL;	/* Reg/Fld not present on HIF */
+	else
+		p->mp_fld_build_seed = NULL;
+
+	p->mp_reg_core_speed = NULL;	/* Reg/Fld not present on HIF */
+
+	if (p->mp_reg_core_speed) {
+		p->mp_fld_core_speed = NULL;	/* Reg/Fld not present on HIF */
+		p->mp_fld_ddr3_speed = NULL;	/* Reg/Fld not present on HIF */
+
+	} else {
+		p->mp_reg_core_speed = NULL;
+		p->mp_fld_core_speed = NULL;
+		p->mp_fld_ddr3_speed = NULL;
+	}
+
+	/* Optional registers since: 2018-04-25 */
+	p->mp_reg_int_mask = NULL;	/* Reg/Fld not present on HIF */
+	p->mp_reg_int_clr = NULL;	/* Reg/Fld not present on HIF */
+	p->mp_reg_int_force = NULL;	/* Reg/Fld not present on HIF */
+
+	p->mp_fld_int_mask_timer = NULL;
+	p->mp_fld_int_clr_timer = NULL;
+	p->mp_fld_int_force_timer = NULL;
+
+	p->mp_fld_int_mask_port = NULL;
+	p->mp_fld_int_clr_port = NULL;
+	p->mp_fld_int_force_port = NULL;
+
+	p->mp_fld_int_mask_pps = NULL;
+	p->mp_fld_int_clr_pps = NULL;
+	p->mp_fld_int_force_pps = NULL;
+
+	p->mp_reg_ctrl = nthw_module_get_register(p->mp_mod_hif, HIF_CONTROL);
+	p->mp_fld_ctrl_fsr = nthw_register_query_field(p->mp_reg_ctrl, HIF_CONTROL_FSR);
+
+	p->mp_reg_stat_ctrl = nthw_module_get_register(p->mp_mod_hif, HIF_STAT_CTRL);
+	p->mp_fld_stat_ctrl_ena =
+		nthw_register_get_field(p->mp_reg_stat_ctrl, HIF_STAT_CTRL_STAT_ENA);
+	p->mp_fld_stat_ctrl_req =
+		nthw_register_get_field(p->mp_reg_stat_ctrl, HIF_STAT_CTRL_STAT_REQ);
+
+	p->mp_reg_stat_rx = nthw_module_get_register(p->mp_mod_hif, HIF_STAT_RX);
+	p->mp_fld_stat_rx_counter =
+		nthw_register_get_field(p->mp_reg_stat_rx, HIF_STAT_RX_COUNTER);
+
+	p->mp_reg_stat_tx = nthw_module_get_register(p->mp_mod_hif, HIF_STAT_TX);
+	p->mp_fld_stat_tx_counter =
+		nthw_register_get_field(p->mp_reg_stat_tx, HIF_STAT_TX_COUNTER);
+
+	p->mp_reg_stat_ref_clk = nthw_module_get_register(p->mp_mod_hif, HIF_STAT_REFCLK);
+	p->mp_fld_stat_ref_clk_ref_clk =
+		nthw_register_get_field(p->mp_reg_stat_ref_clk, HIF_STAT_REFCLK_REFCLK250);
+
+	p->mp_reg_status = nthw_module_query_register(p->mp_mod_hif, HIF_STATUS);
+
+	if (p->mp_reg_status) {
+		p->mp_fld_status_tags_in_use =
+			nthw_register_query_field(p->mp_reg_status, HIF_STATUS_TAGS_IN_USE);
+		p->mp_fld_status_wr_err =
+			nthw_register_query_field(p->mp_reg_status, HIF_STATUS_WR_ERR);
+		p->mp_fld_status_rd_err =
+			nthw_register_query_field(p->mp_reg_status, HIF_STATUS_RD_ERR);
+
+	} else {
+		p->mp_reg_status = nthw_module_query_register(p->mp_mod_hif, HIF_STATUS);
+		p->mp_fld_status_tags_in_use =
+			nthw_register_query_field(p->mp_reg_status, HIF_STATUS_TAGS_IN_USE);
+		p->mp_fld_status_wr_err = NULL;
+		p->mp_fld_status_rd_err = NULL;
+	}
+
+	p->mp_reg_pci_test0 = nthw_module_get_register(p->mp_mod_hif, HIF_TEST0);
+	p->mp_fld_pci_test0 = nthw_register_get_field(p->mp_reg_pci_test0, HIF_TEST0_DATA);
+
+	p->mp_reg_pci_test1 = nthw_module_get_register(p->mp_mod_hif, HIF_TEST1);
+	p->mp_fld_pci_test1 = nthw_register_get_field(p->mp_reg_pci_test1, HIF_TEST1_DATA);
+
+	/* Module::Version({2, 0})+ */
+	p->mp_reg_pci_test2 = nthw_module_query_register(p->mp_mod_hif, HIF_TEST2);
+
+	if (p->mp_reg_pci_test2)
+		p->mp_fld_pci_test2 = nthw_register_get_field(p->mp_reg_pci_test2, HIF_TEST2_DATA);
+
+	else
+		p->mp_fld_pci_test2 = NULL;
+
+	/* Module::Version({1, 2})+ */
+	p->mp_reg_pci_test3 = nthw_module_query_register(p->mp_mod_hif, HIF_TEST3);
+
+	if (p->mp_reg_pci_test3)
+		p->mp_fld_pci_test3 = nthw_register_get_field(p->mp_reg_pci_test3, HIF_TEST3_DATA);
+
+	else
+		p->mp_fld_pci_test3 = NULL;
+
+	/* Required to run TSM */
+	p->mp_reg_sample_time = nthw_module_get_register(p->mp_mod_hif, HIF_SAMPLE_TIME);
+
+	if (p->mp_reg_sample_time) {
+		p->mp_fld_sample_time = nthw_register_get_field(p->mp_reg_sample_time,
+				HIF_SAMPLE_TIME_SAMPLE_TIME);
+
+	} else {
+		p->mp_fld_sample_time = NULL;
+	}
+
+	/* We need to optimize PCIe3 TLP-size read-request and extended tag usage */
+	{
+		p->mp_reg_config = nthw_module_query_register(p->mp_mod_hif, HIF_CONFIG);
+
+		if (p->mp_reg_config) {
+			p->mp_fld_max_tlp =
+				nthw_register_get_field(p->mp_reg_config, HIF_CONFIG_MAX_TLP);
+			p->mp_fld_max_read =
+				nthw_register_get_field(p->mp_reg_config, HIF_CONFIG_MAX_READ);
+			p->mp_fld_ext_tag =
+				nthw_register_get_field(p->mp_reg_config, HIF_CONFIG_EXT_TAG);
+
+		} else {
+			p->mp_fld_max_tlp = NULL;
+			p->mp_fld_max_read = NULL;
+			p->mp_fld_ext_tag = NULL;
+		}
+	}
+
+	return 0;
+}
+
+int nthw_hif_trigger_sample_time(nthw_hif_t *p)
+{
+	nthw_field_set_val_flush32(p->mp_fld_sample_time, 0xfee1dead);
+
+	return 0;
+}
+
+int nthw_hif_get_stat(nthw_hif_t *p, uint32_t *p_rx_cnt, uint32_t *p_tx_cnt,
+	uint32_t *p_ref_clk_cnt, uint32_t *p_tg_unit_size, uint32_t *p_tg_ref_freq,
+	uint64_t *p_tags_in_use, uint64_t *p_rd_err, uint64_t *p_wr_err)
+{
+	*p_rx_cnt = nthw_field_get_updated(p->mp_fld_stat_rx_counter);
+	*p_tx_cnt = nthw_field_get_updated(p->mp_fld_stat_tx_counter);
+
+	*p_ref_clk_cnt = nthw_field_get_updated(p->mp_fld_stat_ref_clk_ref_clk);
+
+	*p_tg_unit_size = NTHW_TG_CNT_SIZE;
+	*p_tg_ref_freq = p->mn_fpga_hif_ref_clk_freq;
+
+	*p_tags_in_use = (p->mp_fld_status_tags_in_use
+			? nthw_field_get_updated(p->mp_fld_status_tags_in_use)
+			: 0);
+
+	*p_rd_err =
+		(p->mp_fld_status_rd_err ? nthw_field_get_updated(p->mp_fld_status_rd_err) : 0);
+	*p_wr_err =
+		(p->mp_fld_status_wr_err ? nthw_field_get_updated(p->mp_fld_status_wr_err) : 0);
+
+	return 0;
+}
+
+int nthw_hif_get_stat_rate(nthw_hif_t *p, uint64_t *p_pci_rx_rate, uint64_t *p_pci_tx_rate,
+	uint64_t *p_ref_clk_cnt, uint64_t *p_tags_in_use,
+	uint64_t *p_rd_err_cnt, uint64_t *p_wr_err_cnt)
+{
+	uint32_t rx_cnt, tx_cnt, ref_clk_cnt, tg_unit_size, tg_ref_freq;
+	uint64_t n_tags_in_use, n_rd_err, n_wr_err;
+
+	nthw_hif_get_stat(p, &rx_cnt, &tx_cnt, &ref_clk_cnt, &tg_unit_size, &tg_ref_freq,
+		&n_tags_in_use, &n_rd_err, &n_wr_err);
+
+	*p_tags_in_use = n_tags_in_use;
+
+	if (n_rd_err)
+		(*p_rd_err_cnt)++;
+
+	if (n_wr_err)
+		(*p_wr_err_cnt)++;
+
+	if (ref_clk_cnt) {
+		uint64_t rx_rate;
+		uint64_t tx_rate;
+
+		*p_ref_clk_cnt = ref_clk_cnt;
+
+		rx_rate = ((uint64_t)rx_cnt * tg_unit_size * tg_ref_freq) / (uint64_t)ref_clk_cnt;
+		*p_pci_rx_rate = rx_rate;
+
+		tx_rate = ((uint64_t)tx_cnt * tg_unit_size * tg_ref_freq) / (uint64_t)ref_clk_cnt;
+		*p_pci_tx_rate = tx_rate;
+
+	} else {
+		*p_pci_rx_rate = 0;
+		*p_pci_tx_rate = 0;
+		*p_ref_clk_cnt = 0;
+	}
+
+	return 0;
+}
+
+int nthw_hif_stat_req_enable(nthw_hif_t *p)
+{
+	nthw_field_set_all(p->mp_fld_stat_ctrl_ena);
+	nthw_field_set_all(p->mp_fld_stat_ctrl_req);
+	nthw_field_flush_register(p->mp_fld_stat_ctrl_req);
+	return 0;
+}
+
+int nthw_hif_stat_req_disable(nthw_hif_t *p)
+{
+	nthw_field_clr_all(p->mp_fld_stat_ctrl_ena);
+	nthw_field_set_all(p->mp_fld_stat_ctrl_req);
+	nthw_field_flush_register(p->mp_fld_stat_ctrl_req);
+	return 0;
+}
+
+int nthw_hif_end_point_counters_sample(nthw_hif_t *p, struct nthw_hif_end_point_counters *epc)
+{
+	assert(epc);
+
+	/* Get stat rate and maintain rx/tx min/max */
+	nthw_hif_get_stat_rate(p, &epc->cur_tx, &epc->cur_rx, &epc->n_ref_clk_cnt,
+		&epc->n_tags_in_use, &epc->n_rd_err, &epc->n_wr_err);
+
+	return 0;
+}
diff --git a/drivers/net/ntnic/nthw/core/nthw_iic.c b/drivers/net/ntnic/nthw/core/nthw_iic.c
new file mode 100644
index 0000000000..cdaee20e8a
--- /dev/null
+++ b/drivers/net/ntnic/nthw/core/nthw_iic.c
@@ -0,0 +1,529 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#include "nt_util.h"
+#include "ntlog.h"
+
+#include "nthw_drv.h"
+#include "nthw_register.h"
+
+#include "nthw_iic.h"
+
+#define I2C_TRANSMIT_WR (0x00)
+#define I2C_TRANSMIT_RD (0x01)
+
+#define I2C_WAIT_US(x) nt_os_wait_usec(x)
+
+/*
+ * Minimum timing values for I2C for a Marvel 88E11111 Phy.
+ * This Phy is used in many Trispeed NIMs.
+ * In order to access this Phy, the I2C clock speed is needed to be set to 100KHz.
+ */
+static const uint32_t SUSTA = 4700;	/* ns */
+static const uint32_t SUSTO = 4000;	/* ns */
+static const uint32_t HDSTA = 4000;	/* ns */
+static const uint32_t SUDAT = 250;	/* ns */
+static const uint32_t BUF = 4700;	/* ns */
+static const uint32_t HIGH = 4000;	/* ns */
+static const uint32_t LOW = 4700;	/* ns */
+static const uint32_t HDDAT = 300;	/* ns */
+
+static int nthw_iic_reg_control_txfifo_reset(nthw_iic_t *p)
+{
+	nthw_field_update_register(p->mp_fld_cr_txfifo_reset);
+
+	nthw_field_set_all(p->mp_fld_cr_txfifo_reset);
+	nthw_field_flush_register(p->mp_fld_cr_txfifo_reset);
+
+	nthw_field_clr_all(p->mp_fld_cr_txfifo_reset);
+	nthw_field_flush_register(p->mp_fld_cr_txfifo_reset);
+
+	return 0;
+}
+
+static int nthw_iic_reg_tx_fifo_write(nthw_iic_t *p, uint32_t data, bool start, bool stop)
+{
+	if (start)
+		nthw_field_set_all(p->mp_fld_tx_fifo_start);
+
+	else
+		nthw_field_clr_all(p->mp_fld_tx_fifo_start);
+
+	if (stop)
+		nthw_field_set_all(p->mp_fld_tx_fifo_stop);
+
+	else
+		nthw_field_clr_all(p->mp_fld_tx_fifo_stop);
+
+	nthw_field_set_val32(p->mp_fld_tx_fifo_txdata, data);
+
+	nthw_register_flush(p->mp_reg_tx_fifo, 1);
+
+	return 0;
+}
+
+static int nthw_iic_reg_read_i2c_rx_fifo(nthw_iic_t *p, uint8_t *p_data)
+{
+	assert(p_data);
+
+	*p_data = (uint8_t)nthw_field_get_updated(p->mp_fld_rx_fifo_rxdata);
+
+	return 0;
+}
+
+static int nthw_iic_reg_softr(nthw_iic_t *p)
+{
+	nthw_field_update_register(p->mp_fld_cr_en);
+	nthw_field_set_val_flush32(p->mp_fld_softr_rkey, 0x0A);
+
+	return 0;
+}
+
+static int nthw_iic_reg_enable(nthw_iic_t *p)
+{
+	nthw_field_update_register(p->mp_fld_cr_en);
+	nthw_field_set_flush(p->mp_fld_cr_en);
+
+	return 0;
+}
+
+static int nthw_iic_reg_busbusy(nthw_iic_t *p, bool *pb_flag)
+{
+	assert(pb_flag);
+
+	*pb_flag = nthw_field_get_updated(p->mp_fld_sr_bb) ? true : false;
+
+	return 0;
+}
+
+static int nthw_iic_reg_rxfifo_empty(nthw_iic_t *p, bool *pb_flag)
+{
+	assert(pb_flag);
+
+	*pb_flag = nthw_field_get_updated(p->mp_fld_sr_rxfifo_empty) ? true : false;
+
+	return 0;
+}
+
+/*
+ * n_iic_cycle_time is the I2C clock cycle time in ns ie 125MHz = 8ns
+ */
+static int nthw_iic_reg_set_timing(nthw_iic_t *p, uint32_t n_iic_cycle_time)
+{
+	uint32_t val;
+
+	val = SUSTA / n_iic_cycle_time;
+	nthw_field_set_val_flush(p->mp_fld_tsusta, &val, 1);
+
+	val = SUSTO / n_iic_cycle_time;
+	nthw_field_set_val_flush(p->mp_fld_tsusto, &val, 1);
+
+	val = HDSTA / n_iic_cycle_time;
+	nthw_field_set_val_flush(p->mp_fld_thdsta, &val, 1);
+
+	val = SUDAT / n_iic_cycle_time;
+	nthw_field_set_val_flush(p->mp_fld_tsudat, &val, 1);
+
+	val = BUF / n_iic_cycle_time;
+	nthw_field_set_val_flush(p->mp_fld_tbuf, &val, 1);
+
+	val = HIGH / n_iic_cycle_time;
+	nthw_field_set_val_flush(p->mp_fld_thigh, &val, 1);
+
+	val = LOW / n_iic_cycle_time;
+	nthw_field_set_val_flush(p->mp_fld_tlow, &val, 1);
+
+	val = HDDAT / n_iic_cycle_time;
+	nthw_field_set_val_flush(p->mp_fld_thddat, &val, 1);
+
+	return 0;
+}
+
+nthw_iic_t *nthw_iic_new(void)
+{
+	nthw_iic_t *p = malloc(sizeof(nthw_iic_t));
+
+	if (p)
+		memset(p, 0, sizeof(nthw_iic_t));
+
+	return p;
+}
+
+int nthw_iic_init(nthw_iic_t *p, nthw_fpga_t *p_fpga, int n_iic_instance,
+	uint32_t n_iic_cycle_time)
+{
+	const char *const p_adapter_id_str = p_fpga->p_fpga_info->mp_adapter_id_str;
+	nthw_module_t *mod = nthw_fpga_query_module(p_fpga, MOD_IIC, n_iic_instance);
+
+	if (p == NULL)
+		return mod == NULL ? -1 : 0;
+
+	if (mod == NULL) {
+		NT_LOG(ERR, NTHW, "%s: I2C %d: no such instance\n", p_adapter_id_str,
+			n_iic_instance);
+		return -1;
+	}
+
+	p->mp_fpga = p_fpga;
+	p->mn_iic_instance = n_iic_instance;
+
+	p->mn_iic_cycle_time = n_iic_cycle_time;
+
+	nthw_iic_set_retry_params(p, -1, -1, -1, -1, -1);
+
+	p->mp_mod_iic = mod;
+
+	/* I2C is a primary communication channel - turn off debug by default */
+	nthw_module_set_debug_mode(p->mp_mod_iic, 0x00);
+
+	p->mp_reg_tsusta = nthw_module_get_register(p->mp_mod_iic, IIC_TSUSTA);
+	p->mp_fld_tsusta = nthw_register_get_field(p->mp_reg_tsusta, IIC_TSUSTA_TSUSTA_VAL);
+
+	p->mp_reg_tsusto = nthw_module_get_register(p->mp_mod_iic, IIC_TSUSTO);
+	p->mp_fld_tsusto = nthw_register_get_field(p->mp_reg_tsusto, IIC_TSUSTO_TSUSTO_VAL);
+
+	p->mp_reg_thdsta = nthw_module_get_register(p->mp_mod_iic, IIC_THDSTA);
+	p->mp_fld_thdsta = nthw_register_get_field(p->mp_reg_thdsta, IIC_THDSTA_THDSTA_VAL);
+
+	p->mp_reg_tsudat = nthw_module_get_register(p->mp_mod_iic, IIC_TSUDAT);
+	p->mp_fld_tsudat = nthw_register_get_field(p->mp_reg_tsudat, IIC_TSUDAT_TSUDAT_VAL);
+
+	p->mp_reg_tbuf = nthw_module_get_register(p->mp_mod_iic, IIC_TBUF);
+	p->mp_fld_tbuf = nthw_register_get_field(p->mp_reg_tbuf, IIC_TBUF_TBUF_VAL);
+
+	p->mp_reg_thigh = nthw_module_get_register(p->mp_mod_iic, IIC_THIGH);
+	p->mp_fld_thigh = nthw_register_get_field(p->mp_reg_thigh, IIC_THIGH_THIGH_VAL);
+
+	p->mp_reg_tlow = nthw_module_get_register(p->mp_mod_iic, IIC_TLOW);
+	p->mp_fld_tlow = nthw_register_get_field(p->mp_reg_tlow, IIC_TLOW_TLOW_VAL);
+
+	p->mp_reg_thddat = nthw_module_get_register(p->mp_mod_iic, IIC_THDDAT);
+	p->mp_fld_thddat = nthw_register_get_field(p->mp_reg_thddat, IIC_THDDAT_THDDAT_VAL);
+
+	p->mp_reg_cr = nthw_module_get_register(p->mp_mod_iic, IIC_CR);
+	p->mp_fld_cr_en = nthw_register_get_field(p->mp_reg_cr, IIC_CR_EN);
+	p->mp_fld_cr_msms = nthw_register_get_field(p->mp_reg_cr, IIC_CR_MSMS);
+	p->mp_fld_cr_txfifo_reset = nthw_register_get_field(p->mp_reg_cr, IIC_CR_TXFIFO_RESET);
+	p->mp_fld_cr_txak = nthw_register_get_field(p->mp_reg_cr, IIC_CR_TXAK);
+
+	p->mp_reg_sr = nthw_module_get_register(p->mp_mod_iic, IIC_SR);
+	p->mp_fld_sr_bb = nthw_register_get_field(p->mp_reg_sr, IIC_SR_BB);
+	p->mp_fld_sr_rxfifo_full = nthw_register_get_field(p->mp_reg_sr, IIC_SR_RXFIFO_FULL);
+	p->mp_fld_sr_rxfifo_empty = nthw_register_get_field(p->mp_reg_sr, IIC_SR_RXFIFO_EMPTY);
+	p->mp_fld_sr_txfifo_full = nthw_register_get_field(p->mp_reg_sr, IIC_SR_TXFIFO_FULL);
+	p->mp_fld_sr_txfifo_empty = nthw_register_get_field(p->mp_reg_sr, IIC_SR_TXFIFO_EMPTY);
+
+	p->mp_reg_tx_fifo = nthw_module_get_register(p->mp_mod_iic, IIC_TX_FIFO);
+	p->mp_fld_tx_fifo_txdata = nthw_register_get_field(p->mp_reg_tx_fifo, IIC_TX_FIFO_TXDATA);
+	p->mp_fld_tx_fifo_start = nthw_register_get_field(p->mp_reg_tx_fifo, IIC_TX_FIFO_START);
+	p->mp_fld_tx_fifo_stop = nthw_register_get_field(p->mp_reg_tx_fifo, IIC_TX_FIFO_STOP);
+
+	p->mp_reg_rx_fifo_pirq = nthw_module_get_register(p->mp_mod_iic, IIC_RX_FIFO_PIRQ);
+	p->mp_fld_rx_fifo_pirq_cmp_val =
+		nthw_register_get_field(p->mp_reg_rx_fifo_pirq, IIC_RX_FIFO_PIRQ_CMP_VAL);
+
+	p->mp_reg_rx_fifo = nthw_module_get_register(p->mp_mod_iic, IIC_RX_FIFO);
+	p->mp_fld_rx_fifo_rxdata = nthw_register_get_field(p->mp_reg_rx_fifo, IIC_RX_FIFO_RXDATA);
+
+	p->mp_reg_softr = nthw_module_get_register(p->mp_mod_iic, IIC_SOFTR);
+	p->mp_fld_softr_rkey = nthw_register_get_field(p->mp_reg_softr, IIC_SOFTR_RKEY);
+
+	/*
+	 * Initialize I2C controller by applying soft reset and enable the controller
+	 */
+	nthw_iic_reg_softr(p);
+	/* Enable the controller */
+	nthw_iic_reg_enable(p);
+
+	/* Setup controller timing */
+	if (p->mn_iic_cycle_time) {
+		NT_LOG(DBG, NTHW, "%s: I2C%d: cycletime=%d\n", p_adapter_id_str,
+			p->mn_iic_instance, p->mn_iic_cycle_time);
+		nthw_iic_reg_set_timing(p, p->mn_iic_cycle_time);
+	}
+
+	/* Reset TX fifo - must be after enable */
+	nthw_iic_reg_control_txfifo_reset(p);
+	nthw_iic_reg_tx_fifo_write(p, 0, 0, 0);
+
+	return 0;
+}
+
+void nthw_iic_delete(nthw_iic_t *p)
+{
+	if (p) {
+		memset(p, 0, sizeof(nthw_iic_t));
+		free(p);
+	}
+}
+
+int nthw_iic_set_retry_params(nthw_iic_t *p, const int n_poll_delay, const int n_bus_ready_retry,
+	const int n_data_ready_retry, const int n_read_data_retry,
+	const int n_write_data_retry)
+{
+	p->mn_poll_delay = n_poll_delay >= 0 ? n_poll_delay : 10;
+
+	p->mn_bus_ready_retry = n_bus_ready_retry >= 0 ? n_bus_ready_retry : 1000;
+	p->mn_data_ready_retry = n_data_ready_retry >= 0 ? n_data_ready_retry : 1000;
+
+	p->mn_read_data_retry = n_read_data_retry >= 0 ? n_read_data_retry : 10;
+	p->mn_write_data_retry = n_write_data_retry >= 0 ? n_write_data_retry : 10;
+
+	return 0;
+}
+
+int nthw_iic_read_data(nthw_iic_t *p, uint8_t dev_addr, uint8_t a_reg_addr, uint8_t data_len,
+	void *p_void)
+{
+	const char *const p_adapter_id_str = p->mp_fpga->p_fpga_info->mp_adapter_id_str;
+	const int n_debug_mode = nthw_module_get_debug_mode(p->mp_mod_iic);
+
+	uint8_t *pb = (uint8_t *)p_void;
+	int retry = (p->mn_read_data_retry >= 0 ? p->mn_read_data_retry : 10);
+
+	if (n_debug_mode == 0xff) {
+		NT_LOG(DBG, NTHW, "%s: adr=0x%2.2x, reg=%d, len=%d\n", p_adapter_id_str, dev_addr,
+			a_reg_addr, data_len);
+	}
+
+	while (nthw_iic_readbyte(p, dev_addr, a_reg_addr, data_len, pb) != 0) {
+		retry--;
+
+		if (retry <= 0) {
+			NT_LOG(ERR, NTHW,
+				"%s: I2C%d: Read retry exhausted (dev_addr=%d a_reg_addr=%d)\n",
+				p_adapter_id_str, p->mn_iic_instance, dev_addr, a_reg_addr);
+			return -1;
+
+		} else {
+			NT_LOG(DBG, NTHW, "%s: I2C%d: Read retry=%d (dev_addr=%d a_reg_addr=%d)\n",
+				p_adapter_id_str, p->mn_iic_instance, retry, dev_addr, a_reg_addr);
+		}
+	}
+
+	if (n_debug_mode == 0xff) {
+		NT_LOG(DBG, NTHW, "%s: adr=0x%2.2x, reg=%d, len=%d, retries remaining: %d\n",
+			p_adapter_id_str, dev_addr, a_reg_addr, data_len, retry);
+	}
+
+	return 0;
+}
+
+int nthw_iic_readbyte(nthw_iic_t *p, uint8_t dev_addr, uint8_t a_reg_addr, uint8_t data_len,
+	uint8_t *p_byte)
+{
+	const char *const p_adapter_id_str = p->mp_fpga->p_fpga_info->mp_adapter_id_str;
+
+	uint32_t value;
+	uint32_t i;
+
+	if (nthw_iic_bus_ready(p)) {
+		/* Reset TX fifo */
+		nthw_iic_reg_control_txfifo_reset(p);
+
+		/* Write device address to TX_FIFO and set start bit!! */
+		value = (dev_addr << 1) | I2C_TRANSMIT_WR;
+		nthw_iic_reg_tx_fifo_write(p, value, 1, 0);
+
+		/* Write a_reg_addr to TX FIFO */
+		nthw_iic_reg_tx_fifo_write(p, a_reg_addr, 0, 1);
+
+		if (!nthw_iic_bus_ready(p)) {
+			NT_LOG(ERR, NTHW, "%s: error: (%s:%u)\n", p_adapter_id_str, __func__,
+				__LINE__);
+			return -1;
+		}
+
+		/* Write device address + RD bit to TX_FIFO and set start bit!! */
+		value = (dev_addr << 1) | I2C_TRANSMIT_RD;
+		nthw_iic_reg_tx_fifo_write(p, value, 1, 0);
+
+		/* Write data_len to TX_FIFO and set stop bit!! */
+		nthw_iic_reg_tx_fifo_write(p, data_len, 0, 1);
+
+		for (i = 0; i < data_len; i++) {
+			/* Wait for RX FIFO not empty */
+			if (!nthw_iic_data_ready(p))
+				return -1;
+
+			/* Read data_len bytes from RX_FIFO */
+			nthw_iic_reg_read_i2c_rx_fifo(p, p_byte);
+			p_byte++;
+		}
+
+		return 0;
+
+	} else {
+		NT_LOG(ERR, NTHW, "%s: error: (%s:%u)\n", p_adapter_id_str, __func__, __LINE__);
+		return -1;
+	}
+
+	return 0;
+}
+
+int nthw_iic_write_data(nthw_iic_t *p, uint8_t dev_addr, uint8_t a_reg_addr, uint8_t data_len,
+	void *p_void)
+{
+	const char *const p_adapter_id_str = p->mp_fpga->p_fpga_info->mp_adapter_id_str;
+	int retry = (p->mn_write_data_retry >= 0 ? p->mn_write_data_retry : 10);
+	uint8_t *pb = (uint8_t *)p_void;
+
+	while (nthw_iic_writebyte(p, dev_addr, a_reg_addr, data_len, pb) != 0) {
+		retry--;
+
+		if (retry <= 0) {
+			NT_LOG(ERR, NTHW,
+				"%s: I2C%d: Write retry exhausted (dev_addr=%d a_reg_addr=%d)\n",
+				p_adapter_id_str, p->mn_iic_instance, dev_addr, a_reg_addr);
+			return -1;
+
+		} else {
+			NT_LOG(DBG, NTHW,
+				"%s: I2C%d: Write retry=%d (dev_addr=%d a_reg_addr=%d)\n",
+				p_adapter_id_str, p->mn_iic_instance, retry, dev_addr, a_reg_addr);
+		}
+	}
+
+	return 0;
+}
+
+int nthw_iic_writebyte(nthw_iic_t *p, uint8_t dev_addr, uint8_t a_reg_addr, uint8_t data_len,
+	uint8_t *p_byte)
+{
+	const char *const p_adapter_id_str = p->mp_fpga->p_fpga_info->mp_adapter_id_str;
+	uint32_t value;
+	int count;
+	int i;
+
+	if (data_len == 0)
+		return -1;
+
+	count = data_len - 1;
+
+	if (nthw_iic_bus_ready(p)) {
+		/* Reset TX fifo */
+		nthw_iic_reg_control_txfifo_reset(p);
+
+		/* Write device address to TX_FIFO and set start bit!! */
+		value = (dev_addr << 1) | I2C_TRANSMIT_WR;
+		nthw_iic_reg_tx_fifo_write(p, value, 1, 0);
+
+		/* Write a_reg_addr to TX FIFO */
+		nthw_iic_reg_tx_fifo_write(p, a_reg_addr, 0, 0);
+
+		for (i = 0; i < count; i++) {
+			/* Write data byte to TX fifo and set stop bit */
+			nthw_iic_reg_tx_fifo_write(p, *p_byte, 0, 0);
+			p_byte++;
+		}
+
+		/* Write data byte to TX fifo and set stop bit */
+		nthw_iic_reg_tx_fifo_write(p, *p_byte, 0, 1);
+
+		if (!nthw_iic_bus_ready(p)) {
+			NT_LOG(WRN, NTHW, "%s: warn: !busReady (%s:%u)\n", p_adapter_id_str,
+				__func__, __LINE__);
+
+			while (true)
+				if (nthw_iic_bus_ready(p)) {
+					NT_LOG(DBG, NTHW, "%s: info: busReady (%s:%u)\n",
+						p_adapter_id_str, __func__, __LINE__);
+					break;
+				}
+		}
+
+		return 0;
+
+	} else {
+		NT_LOG(WRN, NTHW, "%s: (%s:%u)\n", p_adapter_id_str, __func__, __LINE__);
+		return -1;
+	}
+}
+
+/*
+ * Support function for read/write functions below. Waits for bus ready.
+ */
+bool nthw_iic_bus_ready(nthw_iic_t *p)
+{
+	int count = (p->mn_bus_ready_retry >= 0 ? p->mn_bus_ready_retry : 1000);
+	bool b_bus_busy = true;
+
+	while (true) {
+		nthw_iic_reg_busbusy(p, &b_bus_busy);
+
+		if (!b_bus_busy)
+			break;
+
+		count--;
+
+		if (count <= 0)	/* Test for timeout */
+			break;
+
+		if (p->mn_poll_delay != 0)
+			I2C_WAIT_US(p->mn_poll_delay);
+	}
+
+	if (count == 0)
+		return false;
+
+	return true;
+}
+
+/*
+ * Support function for read function. Waits for data ready.
+ */
+bool nthw_iic_data_ready(nthw_iic_t *p)
+{
+	int count = (p->mn_data_ready_retry >= 0 ? p->mn_data_ready_retry : 1000);
+	bool b_rx_fifo_empty = true;
+
+	while (true) {
+		nthw_iic_reg_rxfifo_empty(p, &b_rx_fifo_empty);
+
+		if (!b_rx_fifo_empty)
+			break;
+
+		count--;
+
+		if (count <= 0)	/* Test for timeout */
+			break;
+
+		if (p->mn_poll_delay != 0)
+			I2C_WAIT_US(p->mn_poll_delay);
+	}
+
+	if (count == 0)
+		return false;
+
+	return true;
+}
+
+int nthw_iic_scan_dev_addr(nthw_iic_t *p, int n_dev_addr, int n_reg_addr)
+{
+	const char *const p_adapter_id_str = p->mp_fpga->p_fpga_info->mp_adapter_id_str;
+	(void)p_adapter_id_str;
+	int res;
+	uint8_t data_val = -1;
+	res = nthw_iic_readbyte(p, (uint8_t)n_dev_addr, (uint8_t)n_reg_addr, 1, &data_val);
+
+	if (res == 0) {
+		NT_LOG(DBG, NTHW,
+			"%s: I2C%d: devaddr=0x%02X (%03d) regaddr=%02X val=%02X (%03d) res=%d\n",
+			p_adapter_id_str, p->mn_iic_instance, n_dev_addr, n_dev_addr, n_reg_addr,
+			data_val, data_val, res);
+	}
+
+	return res;
+}
+
+int nthw_iic_scan(nthw_iic_t *p)
+{
+	int i;
+
+	for (i = 0; i < 128; i++)
+		(void)nthw_iic_scan_dev_addr(p, i, 0x00);
+
+	return 0;
+}
diff --git a/drivers/net/ntnic/nthw/core/nthw_mac_pcs_xxv.c b/drivers/net/ntnic/nthw/core/nthw_mac_pcs_xxv.c
new file mode 100644
index 0000000000..abffd34fc3
--- /dev/null
+++ b/drivers/net/ntnic/nthw/core/nthw_mac_pcs_xxv.c
@@ -0,0 +1,1169 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#include "ntlog.h"
+
+#include "nthw_drv.h"
+#include "nthw_register.h"
+
+#include "nthw_mac_pcs_xxv.h"
+
+static void nthw_mac_pcs_xxv_field_set_or_clr_flush(const nthw_field_t *f, bool set)
+{
+	if (f) {
+		nthw_field_get_updated(f);
+
+		if (set)
+			nthw_field_set_flush(f);
+
+		else
+			nthw_field_clr_flush(f);
+	}
+}
+
+nthw_mac_pcs_xxv_t *nthw_mac_pcs_xxv_new(void)
+{
+	nthw_mac_pcs_xxv_t *p = malloc(sizeof(nthw_mac_pcs_xxv_t));
+
+	if (p)
+		memset(p, 0, sizeof(nthw_mac_pcs_xxv_t));
+
+	return p;
+}
+
+void nthw_mac_pcs_xxv_delete(nthw_mac_pcs_xxv_t *p)
+{
+	if (p) {
+		memset(p, 0, sizeof(nthw_mac_pcs_xxv_t));
+		free(p);
+	}
+}
+
+void nthw_mac_pcs_xxv_get_link_summary(nthw_mac_pcs_xxv_t *p,
+	uint32_t *p_abs,
+	uint32_t *p_nt_phy_link_state,
+	uint32_t *p_lh_abs,
+	uint32_t *p_ll_nt_phy_link_state,
+	uint32_t *p_link_down_cnt,
+	uint32_t *p_nim_interr,
+	uint32_t *p_lh_local_fault,
+	uint32_t *p_lh_remote_fault,
+	uint32_t *p_lh_internal_local_fault,
+	uint32_t *p_lh_received_local_fault,
+	uint8_t index)
+{
+	struct nthw_mac_pcs_xxv_registers_fields *r = &p->regs[index];	/* register and fields */
+
+	assert(p);
+
+	nthw_register_update(r->mp_reg_link_summary);
+
+	if (p_abs)
+		*p_abs = nthw_field_get_val32(r->mp_fld_link_summary_abs);
+
+	if (p_nt_phy_link_state) {
+		*p_nt_phy_link_state =
+			nthw_field_get_val32(r->mp_fld_link_summary_nt_phy_link_state);
+	}
+
+	if (p_lh_abs)
+		*p_lh_abs = nthw_field_get_val32(r->mp_fld_link_summary_lh_abs);
+
+	if (p_ll_nt_phy_link_state) {
+		*p_ll_nt_phy_link_state =
+			nthw_field_get_val32(r->mp_fld_link_summary_ll_nt_phy_link_state);
+	}
+
+	if (p_link_down_cnt)
+		*p_link_down_cnt = nthw_field_get_val32(r->mp_fld_link_summary_link_down_cnt);
+
+	if (p_nim_interr)
+		*p_nim_interr = nthw_field_get_val32(r->mp_fld_link_summary_nim_interr);
+
+	if (p_lh_local_fault)
+		*p_lh_local_fault = nthw_field_get_val32(r->mp_fld_link_summary_lh_local_fault);
+
+	if (p_lh_remote_fault)
+		*p_lh_remote_fault = nthw_field_get_val32(r->mp_fld_link_summary_lh_remote_fault);
+
+	if (p_lh_internal_local_fault) {
+		*p_lh_internal_local_fault =
+			nthw_field_get_val32(r->mp_fld_link_summary_lh_internal_local_fault);
+	}
+
+	if (p_lh_received_local_fault) {
+		*p_lh_received_local_fault =
+			nthw_field_get_val32(r->mp_fld_link_summary_lh_received_local_fault);
+	}
+}
+
+void nthw_mac_pcs_xxv_reset_rx_gt_data(nthw_mac_pcs_xxv_t *p, bool enable, uint8_t index)
+{
+	const nthw_field_t *const f = p->regs[index].mp_fld_sub_rst_rx_gt_data;
+
+	nthw_mac_pcs_xxv_field_