From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1329245628; Tue, 16 Jul 2024 14:05:08 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6C1E843397; Tue, 16 Jul 2024 14:02:54 +0200 (CEST) Received: from egress-ip11b.ess.de.barracuda.com (egress-ip11b.ess.de.barracuda.com [18.185.115.215]) by mails.dpdk.org (Postfix) with ESMTP id 8826C43357 for ; Tue, 16 Jul 2024 14:02:41 +0200 (CEST) Received: from EUR05-AM6-obe.outbound.protection.outlook.com (mail-am6eur05lp2105.outbound.protection.outlook.com [104.47.18.105]) by mx-outbound21-91.eu-central-1b.ess.aws.cudaops.com (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Tue, 16 Jul 2024 12:02:40 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=OHmBYcQLgrm+mPGrEY5j7CcvgX6bD8/cncO6Pq7+Es7sEiz7ZFV60cH2YXIHZvANC2menSdr6Q5Ty8BfIXVMaZ1W1ie9SkLaFFnu8YT9Js0nhlN0u/Ck3b67TwiZkn2hwZB9CsCxBXeY/fhcSij+QKtfOM4EFBOpTqfnPdhBE7UYZQtT6EUBMkwqM2P7yi2DZOav3kd4sZOj0UWO40umAubMPSq3Gm+JZSKBdhCfH3pfxnQdxJ6TruNJcXdEXBiyIinaB8mjTIG3k6O+opfksyToQ+ynwnyNcRuqWuhTy3HJSNFh9S5JfdQFIyHao8aKSQSZzZNbvOUJ+WZKexpL9A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=F2z6nTRFOzWTveMuQoNVRw45bq+KVxHyYibSaAwmBac=; b=bTac8qcdVOyFS658083kereCazcxz9W4NAhhd+KE/9LlT9lFUX63p0nc7vO6xCQXYWMiFpda75ye2duQUeM1RZEMpsmYz4twkwBO9Ksh7zEqD/ck+GlFwSPClmZKLYU3pDCQodKBq4C8P7LSmAXLMTX0c/jReaIzb+tzQiZSRcshCZPF8GzfR/kWt+tUpAM1ZKo83Fsw+8mulU4TvIbhzd1Is38BemCsT13XgcrKb7QbCMzN8ux7QRbTGvHVlkjaXedSipOiPJzGtMfXVwTfraRVdC+7T6JV05X46+VL8rHFJ2KhbtXl0ZIpCpJ4Yc2wznuuSAFghYpbItpkSEcstw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=fail (sender ip is 178.72.21.4) smtp.rcpttodomain=dpdk.org smtp.mailfrom=napatech.com; dmarc=fail (p=reject sp=reject pct=100) action=oreject header.from=napatech.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=napatech.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=F2z6nTRFOzWTveMuQoNVRw45bq+KVxHyYibSaAwmBac=; b=QYC4vLf5YE0AtRLr37g8cZEdafMGOwKKKecSaMIj/8ADms/STF4QbIWzvkcXf/YTLxvBZ2u9WxN5qT2fReBihMsBCfV1gOdfVFsJP2sJAz/eGisjLLjbV0kM33hzMRNwcr6fiSLXzcuTLfdYsdP9yChuOvvhxWE+DYYlTJczPAQ= Received: from DU7P195CA0005.EURP195.PROD.OUTLOOK.COM (2603:10a6:10:54d::24) by AS8P190MB1080.EURP190.PROD.OUTLOOK.COM (2603:10a6:20b:2e5::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7784.14; Tue, 16 Jul 2024 12:02:37 +0000 Received: from DU6PEPF0000A7DD.eurprd02.prod.outlook.com (2603:10a6:10:54d:cafe::9f) by DU7P195CA0005.outlook.office365.com (2603:10a6:10:54d::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7762.29 via Frontend Transport; Tue, 16 Jul 2024 12:02:37 +0000 X-MS-Exchange-Authentication-Results: spf=fail (sender IP is 178.72.21.4) smtp.mailfrom=napatech.com; dkim=none (message not signed) header.d=none;dmarc=fail action=oreject header.from=napatech.com; Received-SPF: Fail (protection.outlook.com: domain of napatech.com does not designate 178.72.21.4 as permitted sender) receiver=protection.outlook.com; client-ip=178.72.21.4; helo=localhost.localdomain; Received: from localhost.localdomain (178.72.21.4) by DU6PEPF0000A7DD.mail.protection.outlook.com (10.167.8.37) with Microsoft SMTP Server id 15.20.7784.11 via Frontend Transport; Tue, 16 Jul 2024 12:02:37 +0000 From: Serhii Iliushyk To: dev@dpdk.org Cc: mko-plv@napatech.com, sil-plv@napatech.com, ckm@napatech.com, andrew.rybchenko@oktetlabs.ru, ferruh.yigit@amd.com Subject: [PATCH v9 20/21] net/ntnic: add GPIO communication for NIMs Date: Tue, 16 Jul 2024 14:02:09 +0200 Message-ID: <20240716120216.3032484-20-sil-plv@napatech.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20240716120216.3032484-1-sil-plv@napatech.com> References: <20240530144929.4127931-1-sil-plv@napatech.com> <20240716120216.3032484-1-sil-plv@napatech.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DU6PEPF0000A7DD:EE_|AS8P190MB1080:EE_ Content-Type: text/plain X-MS-Office365-Filtering-Correlation-Id: f2a801d7-0306-42d9-5ba7-08dca58f2f8b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|82310400026|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?GtI+vq8dLkC5if3kFYc526vbJJTPm3TQkYNJQRoSHCuHOeGjbpyXepCSXdyE?= =?us-ascii?Q?8RHI1hjovMQ4iN62SnsXdtWbUhclJb8Ha4YP8VqB7NZ30HPwSSQkI7q+3UaF?= =?us-ascii?Q?9aRip73F7bZI7Cmz2JoJrDaNanASx8i7ls0Q/EP9i7Z9+5tmGYzBAmJUM81G?= =?us-ascii?Q?e6+7AYPZGf1uVe4sbT2z7FVG2rRdDJb/n08kVsomrTyl5qDVZhGCDttUrmI9?= =?us-ascii?Q?fuLAhlUa68GWkAQzoPN0QHVvqvX/qRghwQxplrwIUm7UIBe7u/51pPiNXEvW?= =?us-ascii?Q?UWh6zt/Dlx7BcwuCj3jyOpnucwlzKhFZ0aVJaiTot+z8kWuNoua0c5xz4Yjw?= =?us-ascii?Q?aBggvEX6Vf1j22zK81EnIxHH4zoK95E654emhjZY11PuFEaEs6kR1+j6NMWP?= =?us-ascii?Q?7XrnhgGtuTnL0bzfdpxudZpp+nr3TljrvawCsLmk3o6xxO0gtNfti5JvBSB9?= =?us-ascii?Q?q37iLQ85rvP+oU9TOjBXMaDlnsWlALLDHJdfQgqGOIQ86HUxi6MZJ97Bd83h?= =?us-ascii?Q?b4MADR+qIWzAlCJs67pRLYgHzhiOmjyV0WcxrJg53jl+VkFzQ+AE7m2NhyNF?= =?us-ascii?Q?uIR5LXMqRmGNmsOTTKUh6ftNWJndJp7Js2Ak7F+0W314irL5UyQTn792lGor?= =?us-ascii?Q?m/jYw4DV8QH1Zncae7cTRr7Vhq3sZh7tD4HMTbPx84JqHg5PHc/Zlts7fm4L?= =?us-ascii?Q?HmwT0A7H5A36hLWCveC2puGuHiDsG6U/0DV9XhjtwYELy6+nRM9ts9rYnvFd?= =?us-ascii?Q?NKtWxVcGNL1va2sbeH0xyWAGGJpmbPyI4OJU5l9kGnJUrpEGyExCCMpoaJv5?= =?us-ascii?Q?M9rVun1cGbSlS+cS1RJqSXdaO7UW0e9u3LTXyc3zABF/oE1G/hMBiKRaLIz7?= =?us-ascii?Q?qYJGyU2F8uSlTeURyYMr6KXQbvGpP/W0uq59SoizQ9umQsMTmbmewc/ZLxzx?= =?us-ascii?Q?ESFgfqrt0760Wc7nPacz91RwApCxfw+CCyqh+3hMvhj+3uImVSIxltz5ZJFy?= =?us-ascii?Q?y0Gs5UPGl3kFxVL2rrnzDyQrA1nooz1yPSmQo1E/RFkB2QquEMwiq23PLLR3?= =?us-ascii?Q?DuyQMctppPFRmram+SsMfq7xLkB1p+dCcv5B8m5BPY2Y/GlwqDSye39i9/iJ?= =?us-ascii?Q?5uMfu6rzAWUHjX65kRHI8pJ5wkncMvDH5C983Co3Z47nBei1CL55m6mWVnZc?= =?us-ascii?Q?3p6iSvAee6MBHKmnwCvHE5E2QVhG6Giqbp+TccEUENnhXMcalzPbyJQNaTaK?= =?us-ascii?Q?MkdnVrqDSWLvpICeOoQZnsyI2QVjmQ5J6c8lJ464YvpUnswJqAgxqNKn6Q3J?= =?us-ascii?Q?Fnm8en9VJCF/8rGhDnCFtdh5XAM3RJUmnsALFtpgsR9pzrnxEC+GytU0qaXk?= =?us-ascii?Q?SCsfzAdHEeRnwiDYO1KuIeja7xXw+exd3Fo4nqmk4YCnbwFUx+vCjBKgG838?= =?us-ascii?Q?HJGtE2zycqjEfmIKiYDyX/XV0q/6ek0A?= X-Forefront-Antispam-Report: CIP:178.72.21.4; CTRY:DK; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:localhost.localdomain; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(376014)(82310400026)(1800799024)(36860700013); DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-ExternalHop-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-ExternalHop-MessageData-0: 6RD6vjsgDVzSpp+WiLRMfgf9Wmu43J+q3Da4MjTTse7lzsinQ5TEMesGomDZLQ7AmJO7MMZTJQq5Y8dnFlmlwTZueEBu2wH7tzmSWFID12XbZl/IVh03zJc+lJNOTmwUtLK7MiR+DiM5eVGXi7HPCkTQ59+chjSewIHbOUuQGvCIgOCUb99WiiDt4QoYadLeO1BHqmKmlWWsHIFFY7t/qO9HdqUv5lQOeYUknMQOXheWwe+i0D0SG48Xd2PAsTQfajzsLTkHVTGP1eDWZuLzlwkDFU4O1NVkUq6Nyn5qpgTpiNpI3R7N3lnuO5jf940iofw0E+B10wRM+XXcmxHhk1ZaBM70fibYWYl328eNW8HE8WWWhmUmZ8YGP1goRjS90Ln+ZRcsqaQ0aWxKlweNjIWSD3UVaZz9rK7/rIMgPx/3yPqAJbWMGSIYeOZkoXSpsPMxubV4J3jCgvxSrfBNRn+ZIOJQzezdw3lJc2CSWbETdd+IriZotQH4ikJXsxSaXxodWZUzzEfeSLbOLQK/zxL0ytz5XmjBq6NNmjRkF74fxWIFLzYDjkFC7lOb934fkZ/apLTdz2izaxaWt3dvBNYhZ2Xo9l3MJT83BaZPOgpWIxPv6pFz8nMNtm0Ojzrj1+v0zh0YbcGcsMC2DQYyE+YjVJk4J7Zor2Xboio3icY= X-OriginatorOrg: napatech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jul 2024 12:02:37.3367 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f2a801d7-0306-42d9-5ba7-08dca58f2f8b X-MS-Exchange-CrossTenant-Id: c4540d0b-728a-4233-9da5-9ea30c7ec3ed X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=c4540d0b-728a-4233-9da5-9ea30c7ec3ed; Ip=[178.72.21.4]; Helo=[localhost.localdomain] X-MS-Exchange-CrossTenant-AuthSource: DU6PEPF0000A7DD.eurprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8P190MB1080 X-BESS-ID: 1721131360-305467-20588-17431-1 X-BESS-VER: 2019.1_20240702.1505 X-BESS-Apparent-Source-IP: 104.47.18.105 X-BESS-Parts: H4sIAAAAAAACA4uuVkqtKFGyUioBkjpK+cVKVoYmJsaGQGYGUNQgKS0tzTDJOM UiMTktyTLJzNDc3NIi1STN0sjUOM04Wak2FgBzZeCUQgAAAA== X-BESS-Outbound-Spam-Score: 0.50 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.257662 [from cloudscan14-254.eu-central-1a.ess.aws.cudaops.com] Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.50 BSF_RULE7568M META: Custom Rule 7568M 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.50 using account:ESS113687 scores of KILL_LEVEL=7.0 tests=BSF_RULE7568M, BSF_BESS_OUTBOUND X-BESS-BRTS-Status: 1 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org For NIM reset sequence GPIO communication is used. After this commit the NIMs supported by ntnic is able to start up and be controlled fully by the adapter. Signed-off-by: Serhii Iliushyk --- v5 * Fix Typo/Spelling --- drivers/net/ntnic/include/nt4ga_link.h | 1 + .../link_mgmt/link_100g/nt4ga_link_100g.c | 71 ++++++++- drivers/net/ntnic/meson.build | 1 + .../net/ntnic/nthw/core/include/nthw_core.h | 1 + .../ntnic/nthw/core/include/nthw_gpio_phy.h | 48 ++++++ drivers/net/ntnic/nthw/core/nthw_gpio_phy.c | 145 ++++++++++++++++++ 6 files changed, 263 insertions(+), 4 deletions(-) create mode 100644 drivers/net/ntnic/nthw/core/include/nthw_gpio_phy.h create mode 100644 drivers/net/ntnic/nthw/core/nthw_gpio_phy.c diff --git a/drivers/net/ntnic/include/nt4ga_link.h b/drivers/net/ntnic/include/nt4ga_link.h index 0851057f81..5a16afea2a 100644 --- a/drivers/net/ntnic/include/nt4ga_link.h +++ b/drivers/net/ntnic/include/nt4ga_link.h @@ -78,6 +78,7 @@ typedef struct port_action_s { typedef struct adapter_100g_s { nim_i2c_ctx_t nim_ctx[NUM_ADAPTER_PORTS_MAX]; /* Should be the first field */ + nthw_gpio_phy_t gpio_phy[NUM_ADAPTER_PORTS_MAX]; } adapter_100g_t; typedef union adapter_var_s { diff --git a/drivers/net/ntnic/link_mgmt/link_100g/nt4ga_link_100g.c b/drivers/net/ntnic/link_mgmt/link_100g/nt4ga_link_100g.c index 69d0a5d24a..ed0b89d417 100644 --- a/drivers/net/ntnic/link_mgmt/link_100g/nt4ga_link_100g.c +++ b/drivers/net/ntnic/link_mgmt/link_100g/nt4ga_link_100g.c @@ -10,13 +10,24 @@ #include "i2c_nim.h" #include "ntnic_mod_reg.h" +/* + * Check whether a NIM module is present + */ +static bool _nim_is_present(nthw_gpio_phy_t *gpio_phy, uint8_t if_no) +{ + assert(if_no < NUM_ADAPTER_PORTS_MAX); + + return nthw_gpio_phy_is_module_present(gpio_phy, if_no); +} + /* * Initialize NIM, Code based on nt200e3_2_ptp.cpp: MyPort::createNim() */ -static int _create_nim(adapter_info_t *drv, int port) +static int _create_nim(adapter_info_t *drv, int port, bool enable) { int res = 0; const uint8_t valid_nim_id = 17U; + nthw_gpio_phy_t *gpio_phy; nim_i2c_ctx_t *nim_ctx; sfp_nim_state_t nim; nt4ga_link_t *link_info = &drv->nt4ga_link; @@ -24,14 +35,43 @@ static int _create_nim(adapter_info_t *drv, int port) assert(port >= 0 && port < NUM_ADAPTER_PORTS_MAX); assert(link_info->variables_initialized); + gpio_phy = &link_info->u.var100g.gpio_phy[port]; nim_ctx = &link_info->u.var100g.nim_ctx[port]; + /* + * Check NIM is present before doing GPIO PHY reset. + */ + if (!_nim_is_present(gpio_phy, (uint8_t)port)) { + NT_LOG(INF, NTNIC, "%s: NIM module is absent\n", drv->mp_port_id_str[port]); + return 0; + } + + /* + * Perform PHY reset. + */ + NT_LOG(DBG, NTNIC, "%s: Performing NIM reset\n", drv->mp_port_id_str[port]); + nthw_gpio_phy_set_reset(gpio_phy, (uint8_t)port, true); + nt_os_wait_usec(100000);/* pause 0.1s */ + nthw_gpio_phy_set_reset(gpio_phy, (uint8_t)port, false); + /* * Wait a little after a module has been inserted before trying to access I2C * data, otherwise the module will not respond correctly. */ nt_os_wait_usec(1000000); /* pause 1.0s */ + if (!_nim_is_present(gpio_phy, (uint8_t)port)) { + NT_LOG(DBG, NTNIC, "%s: NIM module is no longer absent!\n", + drv->mp_port_id_str[port]); + return -1; + } + + if (!_nim_is_present(gpio_phy, (uint8_t)port)) { + NT_LOG(DBG, NTNIC, "%s: NIM module is no longer absent!\n", + drv->mp_port_id_str[port]); + return -1; + } + res = construct_and_preinit_nim(nim_ctx, NULL); if (res) @@ -57,6 +97,15 @@ static int _create_nim(adapter_info_t *drv, int port) return -1; } + if (enable) { + NT_LOG(DBG, NTNIC, "%s: De-asserting low power\n", drv->mp_port_id_str[port]); + nthw_gpio_phy_set_low_power(gpio_phy, (uint8_t)port, false); + + } else { + NT_LOG(DBG, NTNIC, "%s: Asserting low power\n", drv->mp_port_id_str[port]); + nthw_gpio_phy_set_low_power(gpio_phy, (uint8_t)port, true); + } + return res; } @@ -89,7 +138,7 @@ static int _port_init(adapter_info_t *drv, int port) /* Phase 3. Link state machine steps */ /* 3.1) Create NIM, ::createNim() */ - res = _create_nim(drv, port); + res = _create_nim(drv, port, true); if (res) { NT_LOG(WRN, NTNIC, "%s: NIM initialization failed\n", drv->mp_port_id_str[port]); @@ -115,6 +164,7 @@ static int _common_ptp_nim_state_machine(void *data) uint32_t last_lpbk_mode[NUM_ADAPTER_PORTS_MAX]; link_state_t *link_state; + nthw_gpio_phy_t *gpio_phy; if (!fpga) { NT_LOG(ERR, NTNIC, "%s: fpga is NULL\n", drv->mp_adapter_id_str); @@ -123,6 +173,7 @@ static int _common_ptp_nim_state_machine(void *data) assert(adapter_no >= 0 && adapter_no < NUM_ADAPTER_MAX); link_state = link_info->link_state; + gpio_phy = link_info->u.var100g.gpio_phy; monitor_task_is_running[adapter_no] = 1; memset(last_lpbk_mode, 0, sizeof(last_lpbk_mode)); @@ -150,7 +201,7 @@ static int _common_ptp_nim_state_machine(void *data) link_info->link_info[i].link_speed = NT_LINK_SPEED_UNKNOWN; link_state[i].link_disabled = true; /* Turn off laser and LED, etc. */ - (void)_create_nim(drv, i); + (void)_create_nim(drv, i, false); NT_LOG(DBG, NTNIC, "%s: Port %i is disabled\n", drv->mp_port_id_str[i], i); continue; @@ -167,7 +218,13 @@ static int _common_ptp_nim_state_machine(void *data) if (link_info->port_action[i].port_lpbk_mode != last_lpbk_mode[i]) { /* Loopback mode has changed. Do something */ - _port_init(drv, i); + if (!_nim_is_present(&gpio_phy[i], (uint8_t)i)) { + /* + * If there is no Nim present, we need to initialize the + * port anyway + */ + _port_init(drv, i); + } NT_LOG(INF, NTNIC, "%s: Loopback mode changed=%u\n", drv->mp_port_id_str[i], @@ -224,6 +281,7 @@ static int nt4ga_link_100g_ports_init(struct adapter_info_s *p_adapter_info, nth if (res == 0 && !p_adapter_info->nt4ga_link.variables_initialized) { nim_i2c_ctx_t *nim_ctx = p_adapter_info->nt4ga_link.u.var100g.nim_ctx; + nthw_gpio_phy_t *gpio_phy = p_adapter_info->nt4ga_link.u.var100g.gpio_phy; int i; for (i = 0; i < nb_ports; i++) { @@ -239,6 +297,11 @@ static int nt4ga_link_100g_ports_init(struct adapter_info_s *p_adapter_info, nth nim_ctx[i].devaddr = 0x50; /* 0xA0 / 2 */ nim_ctx[i].regaddr = 0U; nim_ctx[i].type = I2C_HWIIC; + + res = nthw_gpio_phy_init(&gpio_phy[i], fpga, 0 /* Only one instance */); + + if (res != 0) + break; } if (res == 0) { diff --git a/drivers/net/ntnic/meson.build b/drivers/net/ntnic/meson.build index efea37e61a..e995ed75b0 100644 --- a/drivers/net/ntnic/meson.build +++ b/drivers/net/ntnic/meson.build @@ -34,6 +34,7 @@ sources = files( 'nthw/core/nt200a0x/reset/nthw_fpga_rst9563.c', 'nthw/core/nt200a0x/reset/nthw_fpga_rst_nt200a0x.c', 'nthw/core/nthw_fpga.c', + 'nthw/core/nthw_gpio_phy.c', 'nthw/core/nthw_hif.c', 'nthw/core/nthw_i2cm.c', 'nthw/core/nthw_iic.c', diff --git a/drivers/net/ntnic/nthw/core/include/nthw_core.h b/drivers/net/ntnic/nthw/core/include/nthw_core.h index 8d9d78b86d..5cce56e13f 100644 --- a/drivers/net/ntnic/nthw/core/include/nthw_core.h +++ b/drivers/net/ntnic/nthw/core/include/nthw_core.h @@ -17,6 +17,7 @@ #include "nthw_iic.h" #include "nthw_i2cm.h" +#include "nthw_gpio_phy.h" #include "nthw_sdc.h" #include "nthw_si5340.h" diff --git a/drivers/net/ntnic/nthw/core/include/nthw_gpio_phy.h b/drivers/net/ntnic/nthw/core/include/nthw_gpio_phy.h new file mode 100644 index 0000000000..d4641cdb5d --- /dev/null +++ b/drivers/net/ntnic/nthw/core/include/nthw_gpio_phy.h @@ -0,0 +1,48 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#ifndef NTHW_GPIO_PHY_H_ +#define NTHW_GPIO_PHY_H_ + +#define GPIO_PHY_INTERFACES (2) + +typedef struct { + nthw_field_t *cfg_fld_lp_mode; /* Cfg Low Power Mode */ + nthw_field_t *cfg_int; /* Cfg Port Interrupt */ + nthw_field_t *cfg_reset;/* Cfg Reset */ + nthw_field_t *cfg_mod_prs; /* Cfg Module Present */ + nthw_field_t *cfg_pll_int; /* Cfg PLL Interrupt */ + nthw_field_t *cfg_port_rxlos; /* Emulate Cfg Port RXLOS */ + + nthw_field_t *gpio_fld_lp_mode; /* Gpio Low Power Mode */ + nthw_field_t *gpio_int; /* Gpio Port Interrupt */ + nthw_field_t *gpio_reset; /* Gpio Reset */ + nthw_field_t *gpio_mod_prs; /* Gpio Module Present */ + nthw_field_t *gpio_pll_int; /* Gpio PLL Interrupt */ + nthw_field_t *gpio_port_rxlos; /* Emulate Gpio Port RXLOS */ +} gpio_phy_fields_t; + +struct nthw_gpio_phy { + nthw_fpga_t *mp_fpga; + nthw_module_t *mp_mod_gpio_phy; + int mn_instance; + + /* Registers */ + nthw_register_t *mp_reg_config; + nthw_register_t *mp_reg_gpio; + + /* Fields */ + gpio_phy_fields_t mpa_fields[GPIO_PHY_INTERFACES]; +}; + +typedef struct nthw_gpio_phy nthw_gpio_phy_t; + +int nthw_gpio_phy_init(nthw_gpio_phy_t *p, nthw_fpga_t *p_fpga, int n_instance); + +bool nthw_gpio_phy_is_module_present(nthw_gpio_phy_t *p, uint8_t if_no); +void nthw_gpio_phy_set_low_power(nthw_gpio_phy_t *p, uint8_t if_no, bool enable); +void nthw_gpio_phy_set_reset(nthw_gpio_phy_t *p, uint8_t if_no, bool enable); + +#endif /* NTHW_GPIO_PHY_H_ */ diff --git a/drivers/net/ntnic/nthw/core/nthw_gpio_phy.c b/drivers/net/ntnic/nthw/core/nthw_gpio_phy.c new file mode 100644 index 0000000000..754a8ca5a4 --- /dev/null +++ b/drivers/net/ntnic/nthw/core/nthw_gpio_phy.c @@ -0,0 +1,145 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#include "ntlog.h" +#include "nt_util.h" + +#include "nthw_drv.h" +#include "nthw_register.h" + +#include "nthw_gpio_phy.h" + +int nthw_gpio_phy_init(nthw_gpio_phy_t *p, nthw_fpga_t *p_fpga, int n_instance) +{ + nthw_module_t *p_mod = nthw_fpga_query_module(p_fpga, MOD_GPIO_PHY, n_instance); + + if (p == NULL) + return p_mod == NULL ? -1 : 0; + + if (p_mod == NULL) { + NT_LOG(ERR, NTHW, "%s: GPIO_PHY %d: no such instance\n", + p_fpga->p_fpga_info->mp_adapter_id_str, n_instance); + return -1; + } + + p->mp_fpga = p_fpga; + p->mn_instance = n_instance; + p->mp_mod_gpio_phy = p_mod; + + /* Registers */ + p->mp_reg_config = nthw_module_get_register(p->mp_mod_gpio_phy, GPIO_PHY_CFG); + p->mp_reg_gpio = nthw_module_get_register(p->mp_mod_gpio_phy, GPIO_PHY_GPIO); + + /* PORT-0, config fields */ + p->mpa_fields[0].cfg_fld_lp_mode = + nthw_register_get_field(p->mp_reg_config, GPIO_PHY_CFG_PORT0_LPMODE); + p->mpa_fields[0].cfg_int = + nthw_register_get_field(p->mp_reg_config, GPIO_PHY_CFG_PORT0_INT_B); + p->mpa_fields[0].cfg_reset = + nthw_register_get_field(p->mp_reg_config, GPIO_PHY_CFG_PORT0_RESET_B); + p->mpa_fields[0].cfg_mod_prs = + nthw_register_get_field(p->mp_reg_config, GPIO_PHY_CFG_PORT0_MODPRS_B); + + /* PORT-0, Non-mandatory fields (query_field) */ + p->mpa_fields[0].cfg_pll_int = + nthw_register_query_field(p->mp_reg_config, GPIO_PHY_CFG_PORT0_PLL_INTR); + p->mpa_fields[0].cfg_port_rxlos = + nthw_register_query_field(p->mp_reg_config, GPIO_PHY_CFG_E_PORT0_RXLOS); + + /* PORT-1, config fields */ + p->mpa_fields[1].cfg_fld_lp_mode = + nthw_register_get_field(p->mp_reg_config, GPIO_PHY_CFG_PORT1_LPMODE); + p->mpa_fields[1].cfg_int = + nthw_register_get_field(p->mp_reg_config, GPIO_PHY_CFG_PORT1_INT_B); + p->mpa_fields[1].cfg_reset = + nthw_register_get_field(p->mp_reg_config, GPIO_PHY_CFG_PORT1_RESET_B); + p->mpa_fields[1].cfg_mod_prs = + nthw_register_get_field(p->mp_reg_config, GPIO_PHY_CFG_PORT1_MODPRS_B); + + /* PORT-1, Non-mandatory fields (query_field) */ + p->mpa_fields[1].cfg_pll_int = + nthw_register_query_field(p->mp_reg_config, GPIO_PHY_CFG_PORT1_PLL_INTR); + p->mpa_fields[1].cfg_port_rxlos = + nthw_register_query_field(p->mp_reg_config, GPIO_PHY_CFG_E_PORT1_RXLOS); + + /* PORT-0, gpio fields */ + p->mpa_fields[0].gpio_fld_lp_mode = + nthw_register_get_field(p->mp_reg_gpio, GPIO_PHY_GPIO_PORT0_LPMODE); + p->mpa_fields[0].gpio_int = + nthw_register_get_field(p->mp_reg_gpio, GPIO_PHY_GPIO_PORT0_INT_B); + p->mpa_fields[0].gpio_reset = + nthw_register_get_field(p->mp_reg_gpio, GPIO_PHY_GPIO_PORT0_RESET_B); + p->mpa_fields[0].gpio_mod_prs = + nthw_register_get_field(p->mp_reg_gpio, GPIO_PHY_GPIO_PORT0_MODPRS_B); + + /* PORT-0, Non-mandatory fields (query_field) */ + p->mpa_fields[0].gpio_pll_int = + nthw_register_query_field(p->mp_reg_gpio, GPIO_PHY_GPIO_PORT0_PLL_INTR); + p->mpa_fields[0].gpio_port_rxlos = + nthw_register_query_field(p->mp_reg_gpio, GPIO_PHY_GPIO_E_PORT0_RXLOS); + + /* PORT-1, gpio fields */ + p->mpa_fields[1].gpio_fld_lp_mode = + nthw_register_get_field(p->mp_reg_gpio, GPIO_PHY_GPIO_PORT1_LPMODE); + p->mpa_fields[1].gpio_int = + nthw_register_get_field(p->mp_reg_gpio, GPIO_PHY_GPIO_PORT1_INT_B); + p->mpa_fields[1].gpio_reset = + nthw_register_get_field(p->mp_reg_gpio, GPIO_PHY_GPIO_PORT1_RESET_B); + p->mpa_fields[1].gpio_mod_prs = + nthw_register_get_field(p->mp_reg_gpio, GPIO_PHY_GPIO_PORT1_MODPRS_B); + + /* PORT-1, Non-mandatory fields (query_field) */ + p->mpa_fields[1].gpio_pll_int = + nthw_register_query_field(p->mp_reg_gpio, GPIO_PHY_GPIO_PORT1_PLL_INTR); + p->mpa_fields[1].gpio_port_rxlos = + nthw_register_query_field(p->mp_reg_gpio, GPIO_PHY_GPIO_E_PORT1_RXLOS); + + nthw_register_update(p->mp_reg_config); + + return 0; +} + +bool nthw_gpio_phy_is_module_present(nthw_gpio_phy_t *p, uint8_t if_no) +{ + if (if_no >= ARRAY_SIZE(p->mpa_fields)) { + assert(false); + return false; + } + + /* NOTE: This is a negated GPIO PIN "MODPRS_B" */ + return nthw_field_get_updated(p->mpa_fields[if_no].gpio_mod_prs) == 0U ? true : false; +} + +void nthw_gpio_phy_set_low_power(nthw_gpio_phy_t *p, uint8_t if_no, bool enable) +{ + if (if_no >= ARRAY_SIZE(p->mpa_fields)) { + assert(false); + return; + } + + if (enable) + nthw_field_set_flush(p->mpa_fields[if_no].gpio_fld_lp_mode); + + else + nthw_field_clr_flush(p->mpa_fields[if_no].gpio_fld_lp_mode); + + nthw_field_clr_flush(p->mpa_fields[if_no].cfg_fld_lp_mode); /* enable output */ +} + +void nthw_gpio_phy_set_reset(nthw_gpio_phy_t *p, uint8_t if_no, bool enable) +{ + if (if_no >= ARRAY_SIZE(p->mpa_fields)) { + assert(false); + return; + } + + if (enable) + nthw_field_clr_flush(p->mpa_fields[if_no].gpio_reset); + + else + nthw_field_set_flush(p->mpa_fields[if_no].gpio_reset); + + nthw_field_clr_flush(p->mpa_fields[if_no].cfg_reset); /* enable output */ +} -- 2.45.0