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Ip=[178.72.21.4]; Helo=[localhost.localdomain] X-MS-Exchange-CrossTenant-AuthSource: AM3PEPF0000A799.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU5P190MB2051 X-BESS-ID: 1721223203-305921-12774-14950-1 X-BESS-VER: 2019.1_20240716.1757 X-BESS-Apparent-Source-IP: 104.47.17.169 X-BESS-Parts: H4sIAAAAAAACA4uuVkqtKFGyUioBkjpK+cVKViaWxiZAVgZQ0NDAyCLNMs3cIj XVPC3VyDLFxCTVJC3JOC051dDA3MBMqTYWABaLKq1BAAAA X-BESS-Outbound-Spam-Score: 0.00 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.257687 [from cloudscan15-51.eu-central-1a.ess.aws.cudaops.com] Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.00 using account:ESS113687 scores of KILL_LEVEL=7.0 tests=BSF_BESS_OUTBOUND X-BESS-BRTS-Status: 1 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Adds many of the high level structures needed by the ntnic FPGA modules and adapter control. This is considered the first part of the skeleton of ntnic FPGA support Signed-off-by: Serhii Iliushyk --- v10 * Use 8 spaces as indentation in meson --- drivers/net/ntnic/include/ntos_drv.h | 2 + drivers/net/ntnic/meson.build | 2 + drivers/net/ntnic/nthw/nthw_drv.h | 88 ++++++++++++++++++++++ drivers/net/ntnic/nthw/nthw_platform.c | 14 ++++ drivers/net/ntnic/nthw/nthw_platform_drv.h | 21 ++++++ 5 files changed, 127 insertions(+) create mode 100644 drivers/net/ntnic/nthw/nthw_drv.h create mode 100644 drivers/net/ntnic/nthw/nthw_platform.c create mode 100644 drivers/net/ntnic/nthw/nthw_platform_drv.h diff --git a/drivers/net/ntnic/include/ntos_drv.h b/drivers/net/ntnic/include/ntos_drv.h index 3c0a62cc85..3f621143d9 100644 --- a/drivers/net/ntnic/include/ntos_drv.h +++ b/drivers/net/ntnic/include/ntos_drv.h @@ -13,6 +13,8 @@ #include +#include "nthw_drv.h" + #define NUM_MAC_ADDRS_PER_PORT (16U) #define NUM_MULTICAST_ADDRS_PER_PORT (16U) diff --git a/drivers/net/ntnic/meson.build b/drivers/net/ntnic/meson.build index 47c4b6357a..04e31b4729 100644 --- a/drivers/net/ntnic/meson.build +++ b/drivers/net/ntnic/meson.build @@ -13,10 +13,12 @@ includes = [ include_directories('include'), include_directories('ntlog'), include_directories('ntutil'), + include_directories('nthw'), ] # all sources sources = files( + 'nthw/nthw_platform.c', 'ntlog/ntlog.c', 'ntutil/nt_util.c', 'ntnic_vfio.c', diff --git a/drivers/net/ntnic/nthw/nthw_drv.h b/drivers/net/ntnic/nthw/nthw_drv.h new file mode 100644 index 0000000000..0b89a5c5a0 --- /dev/null +++ b/drivers/net/ntnic/nthw/nthw_drv.h @@ -0,0 +1,88 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#ifndef __NTHW_DRV_H__ +#define __NTHW_DRV_H__ + +#include +#include "nthw_platform_drv.h" + +typedef enum nt_meta_port_type_e { + PORT_TYPE_PHYSICAL, + PORT_TYPE_VIRTUAL, + PORT_TYPE_OVERRIDE, +} nt_meta_port_type_t; + +enum fpga_info_profile { + FPGA_INFO_PROFILE_UNKNOWN = 0, + FPGA_INFO_PROFILE_VSWITCH = 1, + FPGA_INFO_PROFILE_INLINE = 2, + FPGA_INFO_PROFILE_CAPTURE = 3, +}; + +typedef struct mcu_info_s { + int mn_mcu_type; + int mn_mcu_dram_size; +} mcu_info_t; + +typedef struct nthw_hw_info_s { + /* From FW */ + int hw_id; + int hw_id_emulated; + char hw_plat_id_str[32]; + + struct vpd_info_s { + int mn_mac_addr_count; + uint64_t mn_mac_addr_value; + uint8_t ma_mac_addr_octets[6]; + } vpd_info; +} nthw_hw_info_t; + +typedef struct fpga_info_s { + uint64_t n_fpga_ident; + + int n_fpga_type_id; + int n_fpga_prod_id; + int n_fpga_ver_id; + int n_fpga_rev_id; + + int n_fpga_build_time; + + int n_fpga_debug_mode; + + int n_phy_ports; + int n_phy_quads; + int n_rx_ports; + int n_tx_ports; + int n_vf_offset; + + enum fpga_info_profile profile; + + struct nthw_fpga_s *mp_fpga; + + struct nthw_rac *mp_nthw_rac; + struct nthw_hif *mp_nthw_hif; + struct nthw_pcie3 *mp_nthw_pcie3; + struct nthw_tsm *mp_nthw_tsm; + + uint8_t *bar0_addr; /* Needed for register read/write */ + size_t bar0_size; + + int adapter_no; /* Needed for nthw_rac DMA array indexing */ + uint32_t pciident; /* Needed for nthw_rac DMA memzone_reserve */ + int numa_node; /* Needed for nthw_rac DMA memzone_reserve */ + + char *mp_adapter_id_str;/* Pointer to string literal used in nthw log messages */ + + struct mcu_info_s mcu_info; + + struct nthw_hw_info_s nthw_hw_info; + + nthw_adapter_id_t n_nthw_adapter_id; + +} fpga_info_t; + + +#endif /* __NTHW_DRV_H__ */ diff --git a/drivers/net/ntnic/nthw/nthw_platform.c b/drivers/net/ntnic/nthw/nthw_platform.c new file mode 100644 index 0000000000..181330dd37 --- /dev/null +++ b/drivers/net/ntnic/nthw/nthw_platform.c @@ -0,0 +1,14 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#include "nthw_platform_drv.h" + +nthw_adapter_id_t nthw_platform_get_nthw_adapter_id(const uint16_t n_pci_device_id) +{ + switch (n_pci_device_id) { + default: + return NT_HW_ADAPTER_ID_UNKNOWN; + } +} diff --git a/drivers/net/ntnic/nthw/nthw_platform_drv.h b/drivers/net/ntnic/nthw/nthw_platform_drv.h new file mode 100644 index 0000000000..ab26d8149a --- /dev/null +++ b/drivers/net/ntnic/nthw/nthw_platform_drv.h @@ -0,0 +1,21 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#ifndef __NTHW_PLATFORM_DRV_H__ +#define __NTHW_PLATFORM_DRV_H__ + +#include + +#define NT_HW_PCI_VENDOR_ID (0x18f4) + +enum nthw_adapter_id_e { + NT_HW_ADAPTER_ID_UNKNOWN = 0, +}; + +typedef enum nthw_adapter_id_e nthw_adapter_id_t; + +nthw_adapter_id_t nthw_platform_get_nthw_adapter_id(const uint16_t n_pci_device_id); + +#endif /* __NTHW_PLATFORM_DRV_H__ */ -- 2.43.0