From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D9FE945A1C; Tue, 24 Sep 2024 11:27:49 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6D27740295; Tue, 24 Sep 2024 11:27:49 +0200 (CEST) Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) by mails.dpdk.org (Postfix) with ESMTP id 3A4AA4028E for ; Tue, 24 Sep 2024 11:27:47 +0200 (CEST) X-SpamFilter-By: ArmorX SpamTrap 5.78 with qID 48O9Ri3N22756427, This message is accepted by code: ctloc85258 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=realsil.com.cn; s=dkim; t=1727170064; bh=crLw59+6x5l/BJmhbC/ycTi/NPBUIHrMd70k6uirKC0=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version: Content-Transfer-Encoding:Content-Type; b=abNGZTd98QMY9Hip4M6d+k44rk4hrApydfaZS1uKhkOmbD9hMRFg8B3wsLm2kOf1D zj40d06vluMdZOuZLxrLTKM4DnzZ3Lda+SG1ePtt6XxcsB3Jw4gOhTZ02rjtcYzbdy jhliQVQlWe/uzWc6qBXPkph/SF3bqbFaF8yl310Hz6W1FiE8ErZDLG0Z2xLonZfNu9 WyCsPnhzNKAYwzGfcHgE+YyVWD0st98PmwQaNJtgwgpjS5mmf/soMp4C04mjPY3w/I xlLTxH6wHpDoU01Yjm+/SEXGo2MbwsaUtX5Ep3fCn528Fn3k+aMtyBcxxDnSnu1qvA eUsiP0z0v87Og== Received: from RSEXMBS01.realsil.com.cn ([172.29.17.195]) by rtits2.realtek.com.tw (8.15.2/3.05/5.92) with ESMTPS id 48O9Ri3N22756427 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=FAIL) for ; Tue, 24 Sep 2024 17:27:44 +0800 Received: from RSEXH36501.realsil.com.cn (172.29.17.2) by RSEXMBS01.realsil.com.cn (172.29.17.195) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 24 Sep 2024 17:27:44 +0800 Received: from 172.29.32.27 (172.29.32.27) by RSEXH36501.realsil.com.cn (172.29.17.2) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Tue, 24 Sep 2024 17:27:44 +0800 From: Howard Wang To: CC: , Howard Wang Subject: [PATCH] net/r8169: add phy registers access routines Date: Tue, 24 Sep 2024 17:27:43 +0800 Message-ID: <20240924092743.7943-1-howard_wang@realsil.com.cn> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Signed-off-by: Howard Wang --- drivers/net/r8169/r8169_ethdev.h | 1 + drivers/net/r8169/r8169_phy.c | 219 +++++++++++++++++++++++++++++++ drivers/net/r8169/r8169_phy.h | 18 +++ 3 files changed, 238 insertions(+) diff --git a/drivers/net/r8169/r8169_ethdev.h b/drivers/net/r8169/r8169_ethdev.h index 20dbf06c9b..9656a26eb0 100644 --- a/drivers/net/r8169/r8169_ethdev.h +++ b/drivers/net/r8169/r8169_ethdev.h @@ -18,6 +18,7 @@ struct rtl_hw { u8 *mmio_addr; u32 mcfg; u8 HwSuppIntMitiVer; + u16 cur_page; /* Enable Tx No Close */ u8 EnableTxNoClose; diff --git a/drivers/net/r8169/r8169_phy.c b/drivers/net/r8169/r8169_phy.c index f0a880eeca..cfec426ee1 100644 --- a/drivers/net/r8169/r8169_phy.c +++ b/drivers/net/r8169/r8169_phy.c @@ -39,3 +39,222 @@ rtl_set_mac_ocp_bit(struct rtl_hw *hw, u16 addr, u16 mask) rtl_clear_set_mac_ocp_bit(hw, addr, 0, mask); } +static u16 +rtl_map_phy_ocp_addr(u16 PageNum, u8 RegNum) +{ + u8 ocp_reg_num = 0; + u16 ocp_page_num = 0; + u16 ocp_phy_address = 0; + + if (PageNum == 0) { + ocp_page_num = OCP_STD_PHY_BASE_PAGE + (RegNum / 8); + ocp_reg_num = 0x10 + (RegNum % 8); + } else { + ocp_page_num = PageNum; + ocp_reg_num = RegNum; + } + + ocp_page_num <<= 4; + + if (ocp_reg_num < 16) + ocp_phy_address = 0; + else { + ocp_reg_num -= 16; + ocp_reg_num <<= 1; + + ocp_phy_address = ocp_page_num + ocp_reg_num; + } + + return ocp_phy_address; +} + +static u32 +rtl_mdio_real_read_phy_ocp(struct rtl_hw *hw, u32 RegAddr) +{ + u32 data32; + int i, value = 0; + + data32 = RegAddr / 2; + data32 <<= OCPR_Addr_Reg_shift; + + RTL_W32(hw, PHYOCP, data32); + for (i = 0; i < 100; i++) { + udelay(1); + + if (RTL_R32(hw, PHYOCP) & OCPR_Flag) + break; + } + value = RTL_R32(hw, PHYOCP) & OCPDR_Data_Mask; + + return value; +} + +u32 +rtl_mdio_direct_read_phy_ocp(struct rtl_hw *hw, u32 RegAddr) +{ + return rtl_mdio_real_read_phy_ocp(hw, RegAddr); +} + +static u32 +rtl_mdio_read_phy_ocp(struct rtl_hw *hw, u16 PageNum, u32 RegAddr) +{ + u16 ocp_addr; + + ocp_addr = rtl_map_phy_ocp_addr(PageNum, RegAddr); + + return rtl_mdio_direct_read_phy_ocp(hw, ocp_addr); +} + +static u32 +rtl_mdio_real_read(struct rtl_hw *hw, u32 RegAddr) +{ + return rtl_mdio_read_phy_ocp(hw, hw->cur_page, RegAddr); +} + +static void +rtl_mdio_real_write_phy_ocp(struct rtl_hw *hw, u32 RegAddr, u32 value) +{ + u32 data32; + int i; + + data32 = RegAddr / 2; + data32 <<= OCPR_Addr_Reg_shift; + data32 |= OCPR_Write | value; + + RTL_W32(hw, PHYOCP, data32); + for (i = 0; i < 100; i++) { + udelay(1); + + if (!(RTL_R32(hw, PHYOCP) & OCPR_Flag)) + break; + } +} + +void +rtl_mdio_direct_write_phy_ocp(struct rtl_hw *hw, u32 RegAddr, u32 value) +{ + rtl_mdio_real_write_phy_ocp(hw, RegAddr, value); +} + +static void +rtl_mdio_write_phy_ocp(struct rtl_hw *hw, u16 PageNum, u32 RegAddr, u32 value) +{ + u16 ocp_addr; + + ocp_addr = rtl_map_phy_ocp_addr(PageNum, RegAddr); + + rtl_mdio_direct_write_phy_ocp(hw, ocp_addr, value); +} + +static void +rtl_mdio_real_write(struct rtl_hw *hw, u32 RegAddr, u32 value) +{ + if (RegAddr == 0x1F) + hw->cur_page = value; + rtl_mdio_write_phy_ocp(hw, hw->cur_page, RegAddr, value); +} + +u32 +rtl_mdio_read(struct rtl_hw *hw, u32 RegAddr) +{ + return rtl_mdio_real_read(hw, RegAddr); +} + +void +rtl_mdio_write(struct rtl_hw *hw, u32 RegAddr, u32 value) +{ + rtl_mdio_real_write(hw, RegAddr, value); +} + +void +rtl_clear_and_set_eth_phy_ocp_bit(struct rtl_hw *hw, u16 addr, u16 clearmask, + u16 setmask) +{ + u16 phy_reg_value; + + phy_reg_value = rtl_mdio_direct_read_phy_ocp(hw, addr); + phy_reg_value &= ~clearmask; + phy_reg_value |= setmask; + rtl_mdio_direct_write_phy_ocp(hw, addr, phy_reg_value); +} + +void +rtl_clear_eth_phy_ocp_bit(struct rtl_hw *hw, u16 addr, u16 mask) +{ + rtl_clear_and_set_eth_phy_ocp_bit(hw, addr, mask, 0); +} + +void +rtl_set_eth_phy_ocp_bit(struct rtl_hw *hw, u16 addr, u16 mask) +{ + rtl_clear_and_set_eth_phy_ocp_bit(hw, addr, 0, mask); +} + +void +rtl_ephy_write(struct rtl_hw *hw, int addr, int value) +{ + int i; + + RTL_W32(hw, EPHYAR, EPHYAR_Write | + (addr & EPHYAR_Reg_Mask_v2) << EPHYAR_Reg_shift | + (value & EPHYAR_Data_Mask)); + + for (i = 0; i < 10; i++) { + udelay(100); + + /* Check if the NIC has completed EPHY write */ + if (!(RTL_R32(hw, EPHYAR) & EPHYAR_Flag)) + break; + } + + udelay(20); +} + +static u16 +rtl_ephy_read(struct rtl_hw *hw, int addr) +{ + int i; + u16 value = 0xffff; + + RTL_W32(hw, EPHYAR, EPHYAR_Read | (addr & EPHYAR_Reg_Mask_v2) << + EPHYAR_Reg_shift); + + for (i = 0; i < 10; i++) { + udelay(100); + + /* Check if the NIC has completed EPHY read */ + if (RTL_R32(hw, EPHYAR) & EPHYAR_Flag) { + value = (u16)(RTL_R32(hw, EPHYAR) & EPHYAR_Data_Mask); + break; + } + } + + udelay(20); + + return value; +} + +void +rtl_clear_and_set_pcie_phy_bit(struct rtl_hw *hw, u8 addr, u16 clearmask, + u16 setmask) +{ + u16 ephy_value; + + ephy_value = rtl_ephy_read(hw, addr); + ephy_value &= ~clearmask; + ephy_value |= setmask; + rtl_ephy_write(hw, addr, ephy_value); +} + +void +rtl_clear_pcie_phy_bit(struct rtl_hw *hw, u8 addr, u16 mask) +{ + rtl_clear_and_set_pcie_phy_bit(hw, addr, mask, 0); +} + +void +rtl_set_pcie_phy_bit(struct rtl_hw *hw, u8 addr, u16 mask) +{ + rtl_clear_and_set_pcie_phy_bit(hw, addr, 0, mask); +} + diff --git a/drivers/net/r8169/r8169_phy.h b/drivers/net/r8169/r8169_phy.h index f31eb163d8..da5a6575d4 100644 --- a/drivers/net/r8169/r8169_phy.h +++ b/drivers/net/r8169/r8169_phy.h @@ -17,5 +17,23 @@ void rtl_clear_mac_ocp_bit(struct rtl_hw *hw, u16 addr, u16 mask); void rtl_set_mac_ocp_bit(struct rtl_hw *hw, u16 addr, u16 mask); +u32 rtl_mdio_direct_read_phy_ocp(struct rtl_hw *hw, u32 RegAddr); +void rtl_mdio_direct_write_phy_ocp(struct rtl_hw *hw, u32 RegAddr, u32 value); + +u32 rtl_mdio_read(struct rtl_hw *hw, u32 RegAddr); +void rtl_mdio_write(struct rtl_hw *hw, u32 RegAddr, u32 value); + +void rtl_clear_and_set_eth_phy_ocp_bit(struct rtl_hw *hw, u16 addr, + u16 clearmask, u16 setmask); +void rtl_clear_eth_phy_ocp_bit(struct rtl_hw *hw, u16 addr, u16 mask); +void rtl_set_eth_phy_ocp_bit(struct rtl_hw *hw, u16 addr, u16 mask); + +void rtl_ephy_write(struct rtl_hw *hw, int addr, int value); + +void rtl_clear_and_set_pcie_phy_bit(struct rtl_hw *hw, u8 addr, u16 clearmask, + u16 setmask); +void rtl_clear_pcie_phy_bit(struct rtl_hw *hw, u8 addr, u16 mask); +void rtl_set_pcie_phy_bit(struct rtl_hw *hw, u8 addr, u16 mask); + #endif -- 2.34.1