From: Sriharsha Basavapatna <sriharsha.basavapatna@broadcom.com> To: dev@dpdk.org Cc: Shuanglin Wang <shuanglin.wang@broadcom.com>, Mike Baucom <michael.baucom@broadcom.com>, Kishore Padmanabha <kishore.padmanabha@broadcom.com>, Manish Kurup <manish.kurup@broadcom.com>, Sriharsha Basavapatna <sriharsha.basavapatna@broadcom.com>, Shahaji Bhosle <sbhosle@broadcom.com>, Randy Schacher <stuart.schacher@broadcom.com>, Ajit Khaparde <ajit.khaparde@broadcom.com> Subject: [PATCH v2 17/47] net/bnxt: tf_ulp: support for Thor2 ulp layer Date: Fri, 27 Sep 2024 23:37:59 +0530 [thread overview] Message-ID: <20240927180829.525350-18-sriharsha.basavapatna@broadcom.com> (raw) In-Reply-To: <20240927180829.525350-1-sriharsha.basavapatna@broadcom.com> From: Shuanglin Wang <shuanglin.wang@broadcom.com> This patch includes the support for following features that enable Thor2 support in the ULP layer: 1. Added support for ulp initialization on Thor2 platform. This involved breaking the functionality that is common and not common between Thor and Thor2 platforms. 2. MPC support for Thor2. This feature enables the access of the DRAM memory location in the HOST CPU for Exact match flows and Action records for those flows. 3. Added support for VF's on Thor2 platform. 4. Added support to offload traffic between two VF's on the system. 5. Renamed all BNXT_TF_DBG macros to BNXT_DRV_DBG. 6. Added logic to get error conditions in the flow create path. 7. Added support for Geneve header and set TTL action parsing. 8. Add mpc batching to ulp flow create for Thor2. This patch also updates the template files for the changes that are being added in this patch. Signed-off-by: Shuanglin Wang <shuanglin.wang@broadcom.com> Signed-off-by: Mike Baucom <michael.baucom@broadcom.com> Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Signed-off-by: Manish Kurup <manish.kurup@broadcom.com> Signed-off-by: Sriharsha Basavapatna <sriharsha.basavapatna@broadcom.com> Reviewed-by: Shahaji Bhosle <sbhosle@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com> --- drivers/net/bnxt/bnxt.h | 32 +- drivers/net/bnxt/bnxt_cpr.c | 63 +- drivers/net/bnxt/bnxt_ethdev.c | 95 +- drivers/net/bnxt/bnxt_flow.c | 5 +- drivers/net/bnxt/bnxt_hwrm.c | 218 +- drivers/net/bnxt/bnxt_hwrm.h | 11 + drivers/net/bnxt/bnxt_reps.c | 59 +- drivers/net/bnxt/bnxt_rxr.c | 5 +- drivers/net/bnxt/bnxt_txr.c | 30 +- drivers/net/bnxt/bnxt_vnic.h | 2 + drivers/net/bnxt/tf_ulp/bnxt_tf_common.h | 9 +- drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.c | 123 +- drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.h | 8 +- drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 2073 +- drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 163 +- drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c | 226 +- drivers/net/bnxt/tf_ulp/bnxt_ulp_meter.c | 76 +- drivers/net/bnxt/tf_ulp/bnxt_ulp_tf.c | 1513 + drivers/net/bnxt/tf_ulp/bnxt_ulp_tf.h | 24 + drivers/net/bnxt/tf_ulp/bnxt_ulp_tfc.c | 971 + .../bnxt/tf_ulp/generic_templates/meson.build | 16 +- .../generic_templates/ulp_template_db_act.c | 9563 +-- .../generic_templates/ulp_template_db_class.c | 48974 ++---------- .../generic_templates/ulp_template_db_enum.h | 3625 +- .../generic_templates/ulp_template_db_field.h | 1180 +- .../generic_templates/ulp_template_db_tbl.c | 3069 +- .../generic_templates/ulp_template_db_tbl.h | 63 +- .../ulp_template_db_thor2_act.c | 7459 ++ .../ulp_template_db_thor2_class.c | 51668 ++++++++++++ .../ulp_template_db_thor_act.c | 4140 +- .../ulp_template_db_thor_class.c | 65676 ++++++++-------- .../ulp_template_db_wh_plus_act.c | 807 +- .../ulp_template_db_wh_plus_class.c | 7608 +- drivers/net/bnxt/tf_ulp/meson.build | 8 +- drivers/net/bnxt/tf_ulp/ulp_def_rules.c | 116 +- drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c | 327 +- drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h | 26 +- drivers/net/bnxt/tf_ulp/ulp_fc_mgr_tf.c | 255 + drivers/net/bnxt/tf_ulp/ulp_fc_mgr_tfc.c | 108 + drivers/net/bnxt/tf_ulp/ulp_flow_db.c | 252 +- drivers/net/bnxt/tf_ulp/ulp_flow_db.h | 8 +- drivers/net/bnxt/tf_ulp/ulp_gen_hash.c | 41 +- drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c | 254 +- drivers/net/bnxt/tf_ulp/ulp_gen_tbl.h | 42 +- drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c | 187 +- drivers/net/bnxt/tf_ulp/ulp_mapper.c | 3444 +- drivers/net/bnxt/tf_ulp/ulp_mapper.h | 276 +- drivers/net/bnxt/tf_ulp/ulp_mapper_tf.c | 1363 + drivers/net/bnxt/tf_ulp/ulp_mapper_tfc.c | 1735 + drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c | 40 +- drivers/net/bnxt/tf_ulp/ulp_matcher.c | 456 +- drivers/net/bnxt/tf_ulp/ulp_matcher.h | 42 +- drivers/net/bnxt/tf_ulp/ulp_port_db.c | 65 +- drivers/net/bnxt/tf_ulp/ulp_port_db.h | 16 +- drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c | 18 +- drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 369 +- drivers/net/bnxt/tf_ulp/ulp_rte_parser.h | 21 +- drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 47 +- drivers/net/bnxt/tf_ulp/ulp_tun.c | 13 +- drivers/net/bnxt/tf_ulp/ulp_utils.c | 71 +- drivers/net/bnxt/tf_ulp/ulp_utils.h | 6 + 61 files changed, 118264 insertions(+), 100896 deletions(-) create mode 100644 drivers/net/bnxt/tf_ulp/bnxt_ulp_tf.c create mode 100644 drivers/net/bnxt/tf_ulp/bnxt_ulp_tf.h create mode 100644 drivers/net/bnxt/tf_ulp/bnxt_ulp_tfc.c create mode 100644 drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor2_act.c create mode 100644 drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor2_class.c create mode 100644 drivers/net/bnxt/tf_ulp/ulp_fc_mgr_tf.c create mode 100644 drivers/net/bnxt/tf_ulp/ulp_fc_mgr_tfc.c create mode 100644 drivers/net/bnxt/tf_ulp/ulp_mapper_tf.c create mode 100644 drivers/net/bnxt/tf_ulp/ulp_mapper_tfc.c diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h index 2ee053b912..36ba1e1e8d 100644 --- a/drivers/net/bnxt/bnxt.h +++ b/drivers/net/bnxt/bnxt.h @@ -557,6 +557,13 @@ struct bnxt_ctx_mem_info { uint16_t tim_entry_size; uint32_t tim_max_entries; uint8_t tqm_entries_multiple; + uint8_t mpc_tqm_entries_multiple; + uint32_t mpc_tqm_max_num_entries; + uint32_t mpc_tqm_min_num_entries; + uint32_t instance_bit_map; /* MPC TQM: TE_CFA(2), RE_CFA (3) */ + uint16_t mpc_tqm_entry_size; + uint8_t ctx_init_value; + uint8_t ctx_init_offset; struct bnxt_ctx_pg_info qp_mem; struct bnxt_ctx_pg_info srq_mem; @@ -564,6 +571,8 @@ struct bnxt_ctx_mem_info { struct bnxt_ctx_pg_info vnic_mem; struct bnxt_ctx_pg_info stat_mem; struct bnxt_ctx_pg_info *tqm_mem[BNXT_MAX_TQM_RINGS]; +#define BNXT_MAX_BMAP 0x5 + struct bnxt_ctx_pg_info *mpc_tqm_mem[BNXT_MAX_BMAP]; }; struct bnxt_ctx_mem_buf_info { @@ -796,8 +805,11 @@ struct bnxt { #define BNXT_FLAG_FLOW_XSTATS_EN BIT(25) #define BNXT_FLAG_DFLT_MAC_SET BIT(26) #define BNXT_FLAG_GFID_ENABLE BIT(27) -#define BNXT_FLAG_CHIP_P7 BIT(30) -#define BNXT_FLAG_FW_TIMEDOUT BIT(31) +#define BNXT_FLAG_CHIP_P7 BIT(28) +#define BNXT_FLAG_FW_TIMEDOUT BIT(29) +#define BNXT_FLAG_RFS_NEEDS_VNIC BIT(30) +#define BNXT_FLAG_FLOW_CFA_RFS_RING_TBL_IDX_V2 BIT(31) +#define BNXT_RFS_NEEDS_VNIC(bp) ((bp)->flags & BNXT_FLAG_RFS_NEEDS_VNIC) #define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF)) #define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF) #define BNXT_NPAR(bp) ((bp)->flags & BNXT_FLAG_NPAR_PF) @@ -829,8 +841,6 @@ struct bnxt { uint16_t multi_host_pf_pci_id; uint16_t chip_num; -#define CHIP_NUM_58818 0xd818 -#define BNXT_CHIP_SR2(bp) ((bp)->chip_num == CHIP_NUM_58818) #define BNXT_FLAGS2_MULTIROOT_EN BIT(4) #define BNXT_MULTIROOT_EN(bp) \ ((bp)->flags2 & BNXT_FLAGS2_MULTIROOT_EN) @@ -847,7 +857,8 @@ struct bnxt { #define BNXT_FW_CAP_LINK_ADMIN BIT(7) #define BNXT_FW_CAP_TRUFLOW_EN BIT(8) #define BNXT_FW_CAP_VLAN_TX_INSERT BIT(9) -#define BNXT_FW_CAP_RX_ALL_PKT_TS BIT(10) +#define BNXT_FW_CAP_TX_COAL_CMPL BIT(10) +#define BNXT_FW_CAP_RX_ALL_PKT_TS BIT(11) #define BNXT_FW_CAP_BACKING_STORE_V2 BIT(12) #define BNXT_FW_BACKING_STORE_V2_EN(bp) \ ((bp)->fw_cap & BNXT_FW_CAP_BACKING_STORE_V2) @@ -1031,11 +1042,12 @@ struct bnxt { uint16_t port_svif; struct tf tfp[BNXT_SESSION_TYPE_LAST]; + struct tfc tfcp; struct bnxt_ulp_context *ulp_ctx; struct bnxt_flow_stat_info *flow_stat; uint16_t max_num_kflows; uint8_t app_id; - uint16_t tx_cfa_action; + uint32_t tx_cfa_action; struct bnxt_ring_stats *prev_rx_ring_stats; struct bnxt_ring_stats *prev_tx_ring_stats; struct bnxt_ring_stats_ext *prev_rx_ring_stats_ext; @@ -1052,6 +1064,7 @@ struct bnxt { struct rte_eth_rss_conf rss_conf; /* RSS configuration. */ uint16_t tunnel_disable_flag; /* tunnel stateless offloads status */ + uint8_t chip_rev; }; static @@ -1123,7 +1136,7 @@ struct bnxt_representor { #define BNXT_DFLT_VNIC_ID_INVALID 0xFFFF uint16_t dflt_vnic_id; uint16_t svif; - uint16_t vfr_tx_cfa_action; + uint32_t vfr_tx_cfa_action; uint8_t parent_pf_idx; /* Logical PF index */ uint32_t dpdk_port_id; uint32_t rep_based_pf; @@ -1214,6 +1227,9 @@ extern const struct rte_flow_ops bnxt_flow_meter_ops; } \ } while (0) +#define BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev) \ + ((eth_dev)->data->dev_flags & RTE_ETH_DEV_REPRESENTOR) + extern int bnxt_logtype_driver; #define RTE_LOGTYPE_BNXT bnxt_logtype_driver #define PMD_DRV_LOG_RAW(level, fmt, args...) \ @@ -1251,6 +1267,6 @@ int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev); void bnxt_handle_vf_cfg_change(void *arg); int bnxt_flow_meter_ops_get(struct rte_eth_dev *eth_dev, void *arg); struct bnxt_vnic_info *bnxt_get_default_vnic(struct bnxt *bp); -struct tf *bnxt_get_tfp_session(struct bnxt *bp, enum bnxt_session_type type); uint64_t bnxt_eth_rss_support(struct bnxt *bp); +struct bnxt *bnxt_pmd_get_bp(uint16_t port); #endif diff --git a/drivers/net/bnxt/bnxt_cpr.c b/drivers/net/bnxt/bnxt_cpr.c index a4509abd60..c9bfad41b2 100644 --- a/drivers/net/bnxt/bnxt_cpr.c +++ b/drivers/net/bnxt/bnxt_cpr.c @@ -11,6 +11,7 @@ #include "bnxt_hwrm.h" #include "bnxt_ring.h" #include "hsi_struct_def_dpdk.h" +#include "tfc_vf2pf_msg.h" void bnxt_wait_for_device_shutdown(struct bnxt *bp) { @@ -135,6 +136,7 @@ static void bnxt_process_vf_flr(struct bnxt *bp, uint32_t data1) { uint16_t pfid, vfid; + int rc; if (!BNXT_TRUFLOW_EN(bp)) return; @@ -145,7 +147,11 @@ bnxt_process_vf_flr(struct bnxt *bp, uint32_t data1) HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_SFT; PMD_DRV_LOG(INFO, "VF FLR async event received pfid: %u, vfid: %u\n", - pfid, vfid); + pfid, vfid); + + rc = tfc_tbl_scope_func_reset(&bp->tfcp, vfid); + if (rc != 0) + PMD_DRV_LOG(ERR, "Failed to reset vf\n"); } /* @@ -360,6 +366,61 @@ void bnxt_handle_fwd_req(struct bnxt *bp, struct cmpl_base *cmpl) HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ANYVLAN_NONVLAN); } + if (fwd_cmd->req_type == HWRM_OEM_CMD) { + struct hwrm_oem_cmd_input *oem_cmd = (void *)fwd_cmd; + struct hwrm_oem_cmd_output oem_out = { 0 }; + + if (oem_cmd->oem_id == 0x14e4 && + oem_cmd->naming_authority + == HWRM_OEM_CMD_INPUT_NAMING_AUTHORITY_PCI_SIG && + oem_cmd->message_family + == HWRM_OEM_CMD_INPUT_MESSAGE_FAMILY_TRUFLOW) { + uint32_t resp[18] = { 0 }; + uint16_t oem_data_len = sizeof(oem_out.oem_data); + uint16_t resp_len = oem_data_len; + + rc = tfc_oem_cmd_process(&bp->tfcp, + oem_cmd->oem_data, + resp, + &resp_len); + if (rc) { + PMD_DRV_LOG(ERR, + "OEM cmd process error id 0x%x, name 0x%x, family 0x%x.\n", + oem_cmd->oem_id, + oem_cmd->naming_authority, + oem_cmd->message_family); + goto reject; + } + + oem_out.error_code = 0; + oem_out.req_type = oem_cmd->req_type; + oem_out.seq_id = oem_cmd->seq_id; + oem_out.resp_len = rte_cpu_to_le_16(sizeof(oem_out)); + oem_out.oem_id = oem_cmd->oem_id; + oem_out.naming_authority = oem_cmd->naming_authority; + oem_out.message_family = oem_cmd->message_family; + memcpy(oem_out.oem_data, resp, resp_len); + oem_out.valid = 1; + + rc = bnxt_hwrm_fwd_resp(bp, fw_vf_id, &oem_out, oem_out.resp_len, + oem_cmd->resp_addr, oem_cmd->cmpl_ring); + if (rc) { + PMD_DRV_LOG(ERR, + "Failed to send HWRM_FWD_RESP VF 0x%x, type .\n", + fw_vf_id - bp->pf->first_vf_id); + } + } else { + PMD_DRV_LOG(ERR, + "Unsupported OEM cmd id 0x%x, name 0x%x, family 0x%x.\n", + oem_cmd->oem_id, + oem_cmd->naming_authority, + oem_cmd->message_family); + goto reject; + } + + return; + } + /* Forward */ rc = bnxt_hwrm_exec_fwd_resp(bp, fw_vf_id, fwd_cmd, req_len); if (rc) { diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c index e63febe782..2c638193a5 100644 --- a/drivers/net/bnxt/bnxt_ethdev.c +++ b/drivers/net/bnxt/bnxt_ethdev.c @@ -105,6 +105,7 @@ static const struct rte_pci_id bnxt_pci_id_map[] = { #define BNXT_DEVARG_APP_ID "app-id" #define BNXT_DEVARG_IEEE_1588 "ieee-1588" #define BNXT_DEVARG_CQE_MODE "cqe-mode" +#define BNXT_DEVARG_MPC "mpc" static const char *const bnxt_dev_args[] = { BNXT_DEVARG_REPRESENTOR, @@ -119,6 +120,7 @@ static const char *const bnxt_dev_args[] = { BNXT_DEVARG_APP_ID, BNXT_DEVARG_IEEE_1588, BNXT_DEVARG_CQE_MODE, + BNXT_DEVARG_MPC, NULL }; @@ -127,6 +129,11 @@ static const char *const bnxt_dev_args[] = { */ #define BNXT_DEVARG_CQE_MODE_INVALID(val) ((val) > 1) +/* + * mpc = an non-negative 8-bit number + */ +#define BNXT_DEVARG_MPC_INVALID(val) ((val) > 1) + /* * app-id = an non-negative 8-bit number */ @@ -174,6 +181,7 @@ static const char *const bnxt_dev_args[] = { #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r) ((rep_fc_f2r) > 1) int bnxt_cfa_code_dynfield_offset = -1; +unsigned long mpc; /* * max_num_kflows must be >= 32 @@ -1687,6 +1695,10 @@ static int bnxt_dev_stop(struct rte_eth_dev *eth_dev) bnxt_free_rx_mbufs(bp); /* Process any remaining notifications in default completion queue */ bnxt_int_handler(eth_dev); + + if (mpc != 0) + bnxt_mpc_close(bp); + bnxt_shutdown_nic(bp); bnxt_hwrm_if_change(bp, false); @@ -1764,6 +1776,12 @@ int bnxt_dev_start_op(struct rte_eth_dev *eth_dev) if (rc) goto error; + if (mpc != 0) { + rc = bnxt_mpc_open(bp); + if (rc != 0) + PMD_DRV_LOG(DEBUG, "MPC open failed\n"); + } + rc = bnxt_alloc_prev_ring_stats(bp); if (rc) goto error; @@ -2220,6 +2238,11 @@ static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev, continue; rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]); + if (!rxq) { + PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n"); + return -EINVAL; + } + if (BNXT_CHIP_P5_P7(bp)) { vnic->rss_table[i * 2] = rxq->rx_ring->rx_ring_struct->fw_ring_id; @@ -3752,6 +3775,7 @@ bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts) if (!ptp) return -ENOTSUP; + /* TODO Revisit for Thor 2 */ if (BNXT_CHIP_P5(bp)) rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME, &systime_cycles); @@ -3801,6 +3825,7 @@ bnxt_timesync_enable(struct rte_eth_dev *dev) ptp->tx_tstamp_tc.cc_shift = shift; ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; + /* TODO Revisit for Thor 2 */ if (!BNXT_CHIP_P5(bp)) bnxt_map_ptp_regs(bp); else @@ -3825,6 +3850,7 @@ bnxt_timesync_disable(struct rte_eth_dev *dev) bnxt_hwrm_ptp_cfg(bp); + /* TODO Revisit for Thor 2 */ bp->ptp_all_rx_tstamp = 0; if (!BNXT_CHIP_P5(bp)) bnxt_unmap_ptp_regs(bp); @@ -3847,6 +3873,7 @@ bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev, if (!ptp) return -ENOTSUP; + /* TODO Revisit for Thor 2 */ if (BNXT_CHIP_P5(bp)) rx_tstamp_cycles = ptp->rx_timestamp; else @@ -3870,6 +3897,7 @@ bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev, if (!ptp) return -ENOTSUP; + /* TODO Revisit for Thor 2 */ if (BNXT_CHIP_P5(bp)) rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX, &tx_tstamp_cycles); @@ -5885,6 +5913,38 @@ bnxt_parse_devarg_app_id(__rte_unused const char *key, return 0; } +static int +bnxt_parse_devarg_mpc(__rte_unused const char *key, + const char *value, __rte_unused void *opaque_arg) +{ + char *end = NULL; + + if (!value || !opaque_arg) { + PMD_DRV_LOG(ERR, + "Invalid parameter passed to app-id " + "devargs.\n"); + return -EINVAL; + } + + mpc = strtoul(value, &end, 10); + if (end == NULL || *end != '\0' || + (mpc == ULONG_MAX && errno == ERANGE)) { + PMD_DRV_LOG(ERR, + "Invalid parameter passed to mpc " + "devargs.\n"); + return -EINVAL; + } + + if (BNXT_DEVARG_MPC_INVALID(mpc)) { + PMD_DRV_LOG(ERR, "Invalid mpc(%d) devargs.\n", + (uint16_t)mpc); + return -EINVAL; + } + + PMD_DRV_LOG(INFO, "MPC%d feature enabled.\n", (uint16_t)mpc); + return 0; +} + static int bnxt_parse_devarg_ieee_1588(__rte_unused const char *key, const char *value, void *opaque_arg) @@ -6190,6 +6250,13 @@ bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs) rte_kvargs_process(kvlist, BNXT_DEVARG_IEEE_1588, bnxt_parse_devarg_ieee_1588, bp); + /* + * Handler for "mpc" devarg. + * Invoked as for ex: "-a 000:00:0d.0,mpc=1" + */ + rte_kvargs_process(kvlist, BNXT_DEVARG_MPC, + bnxt_parse_devarg_mpc, bp); + /* * Handler for "cqe-mode" devarg. * Invoked as for ex: "-a 000:00:0d.0,cqe-mode=1" @@ -6817,10 +6884,30 @@ bool is_bnxt_supported(struct rte_eth_dev *dev) return is_device_supported(dev, &bnxt_rte_pmd); } -struct tf *bnxt_get_tfp_session(struct bnxt *bp, enum bnxt_session_type type) +struct bnxt * +bnxt_pmd_get_bp(uint16_t port) { - return (type >= BNXT_SESSION_TYPE_LAST) ? - &bp->tfp[BNXT_SESSION_TYPE_REGULAR] : &bp->tfp[type]; + struct bnxt *bp; + struct rte_eth_dev *dev; + + if (!rte_eth_dev_is_valid_port(port)) { + PMD_DRV_LOG(ERR, "Invalid port %d\n", port); + return NULL; + } + + dev = &rte_eth_devices[port]; + if (!is_bnxt_supported(dev)) { + PMD_DRV_LOG(ERR, "Device %d not supported\n", port); + return NULL; + } + + bp = (struct bnxt *)dev->data->dev_private; + if (!BNXT_TRUFLOW_EN(bp)) { + PMD_DRV_LOG(ERR, "TRUFLOW not enabled\n"); + return NULL; + } + + return bp; } /* check if ULP should be enabled or not */ @@ -6830,7 +6917,7 @@ static bool bnxt_enable_ulp(struct bnxt *bp) /* not enabling ulp for cli and no truflow apps */ if (BNXT_TRUFLOW_EN(bp) && bp->app_id != 254 && bp->app_id != 255) { - if (BNXT_CHIP_P7(bp)) + if (BNXT_CHIP_P7(bp) && !mpc) return false; return true; } diff --git a/drivers/net/bnxt/bnxt_flow.c b/drivers/net/bnxt/bnxt_flow.c index f25bc6ff78..76e238ac46 100644 --- a/drivers/net/bnxt/bnxt_flow.c +++ b/drivers/net/bnxt/bnxt_flow.c @@ -1247,6 +1247,7 @@ bnxt_vnic_rss_cfg_update(struct bnxt *bp, RTE_FLOW_ERROR_TYPE_ACTION, act, "VNIC RSS configure failed"); + vnic->rss_types_local = 0; rc = -rte_errno; goto ret; } @@ -1698,8 +1699,10 @@ bnxt_validate_and_parse_flow(struct rte_eth_dev *dev, } if (rte_errno) { - if (vnic && STAILQ_EMPTY(&vnic->filter)) + if (vnic && STAILQ_EMPTY(&vnic->filter)) { vnic->rx_queue_cnt = 0; + vnic->rss_types_local = 0; + } if (rxq && !vnic->rx_queue_cnt) rxq->vnic = &bp->vnic_info[0]; diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c index e49e0754c6..d0a6a56845 100644 --- a/drivers/net/bnxt/bnxt_hwrm.c +++ b/drivers/net/bnxt/bnxt_hwrm.c @@ -375,6 +375,25 @@ bnxt_get_ring_info_by_id(struct bnxt *bp, uint16_t rid, uint16_t type) return txq->cp_ring; } } + + /* MPC ring is of type TX. MPC is not allocated on Thor, Wh+. */ + if (bp->mpc == NULL) + goto skip_mpc; + + for (i = 0; i < BNXT_MPC_CHNL_MAX; i++) { + struct bnxt_mpc_txq *mpc_queue; + + if (!(bp->mpc->mpc_chnls_en & (1 << i))) + continue; + mpc_queue = bp->mpc->mpc_txq[i]; + if (!mpc_queue) + continue; + + if (mpc_queue->cp_ring->cp_ring_struct->fw_ring_id == + rte_cpu_to_le_16(rid)) + return mpc_queue->cp_ring; + } +skip_mpc: break; default: return cp_ring; @@ -410,7 +429,7 @@ bnxt_check_cq_hwrm_done(struct bnxt_cp_ring_info *cpr, */ if (!done && timeout) { done = 1; - PMD_DRV_LOG(DEBUG, "Timing out for %s ring\n", + PMD_DRV_LOG(ERR, "Timing out for %s ring\n", rx ? "Rx" : "Tx"); } } else { @@ -980,6 +999,7 @@ static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp) HWRM_CHECK_RESULT(); + /* TODO Revisit for Thor 2 */ if (BNXT_CHIP_P5(bp)) { if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS)) return 0; @@ -1180,6 +1200,23 @@ static int __bnxt_hwrm_func_qcaps(struct bnxt *bp) if (BNXT_CHIP_P7(bp)) bp->fw_cap |= BNXT_FW_CAP_BACKING_STORE_V2; } + + /* only initialize the mpc capability one time */ + if (resp->mpc_chnls_cap && !bp->mpc) { + struct bnxt_mpc *mpc; + + mpc = rte_zmalloc("bnxt_mpc", sizeof(*mpc), 0); + if (!mpc) { + /* no impact to basic NIC functionalities. Truflow + * will be disabled if mpc is not setup. + */ + PMD_DRV_LOG(ERR, "Fail allocate mpc memory\n"); + } else { + mpc->mpc_chnls_cap = resp->mpc_chnls_cap; + bp->mpc = mpc; + } + } + if (!(flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VLAN_ACCELERATION_TX_DISABLED)) { bp->fw_cap |= BNXT_FW_CAP_VLAN_TX_INSERT; PMD_DRV_LOG(DEBUG, "VLAN acceleration for TX is enabled\n"); @@ -1411,6 +1448,7 @@ int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test) uint32_t enables; struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr; struct hwrm_func_vf_cfg_input req = {0}; + uint8_t mpc_ring_cnt = bp->mpc ? BNXT_MPC_RINGS_SUPPORTED : 0; HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB); @@ -1425,13 +1463,16 @@ int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test) req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings); } - req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings); + req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings + mpc_ring_cnt); req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings * AGG_RING_MULTIPLIER); - req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings); + req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + + bp->tx_nr_rings + + mpc_ring_cnt); req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings + - BNXT_NUM_ASYNC_CPR(bp)); + BNXT_NUM_ASYNC_CPR(bp) + + mpc_ring_cnt); if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) { req.num_vnics = rte_cpu_to_le_16(RTE_MIN(BNXT_VNIC_MAX_SUPPORTED_ID, bp->max_vnics)); @@ -1597,6 +1638,7 @@ int bnxt_hwrm_ver_get(struct bnxt *bp, uint32_t timeout) RTE_VERIFY(max_resp_len <= bp->max_resp_len); bp->max_resp_len = max_resp_len; + bp->chip_rev = resp->chip_rev; if ((dev_caps_cfg & HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) && @@ -2086,6 +2128,13 @@ int bnxt_hwrm_queue_qportcfg(struct bnxt *bp) return rc; } +static const uint8_t +mpc_chnl_types[] = {HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_TCE, + HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_RCE, + HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_TE_CFA, + HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_RE_CFA, + HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_PRIMATE}; + int bnxt_hwrm_ring_alloc(struct bnxt *bp, struct bnxt_ring *ring, uint32_t ring_type, uint32_t map_index, @@ -2112,7 +2161,21 @@ int bnxt_hwrm_ring_alloc(struct bnxt *bp, req.ring_type = ring_type; req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id); req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id); - req.queue_id = rte_cpu_to_le_16(tx_cosq_id); + if (bp->fw_cap & BNXT_FW_CAP_TX_COAL_CMPL) + req.cmpl_coal_cnt = + HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_OFF; + if (tx_cosq_id != MPC_HW_COS_ID) { + req.queue_id = rte_cpu_to_le_16(tx_cosq_id); + } else { + uint32_t mpc_chnl = BNXT_MPC_CHNL(map_index); + + req.logical_id = + rte_cpu_to_le_16(BNXT_MPC_QIDX(map_index)); + if (mpc_chnl >= BNXT_MPC_CHNL_MAX) + return -EINVAL; + enables |= HWRM_RING_ALLOC_INPUT_ENABLES_MPC_CHNLS_TYPE; + req.mpc_chnls_type = mpc_chnl_types[mpc_chnl]; + } if (stats_ctx_id != INVALID_STATS_CTX_ID) enables |= HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID; @@ -2848,6 +2911,10 @@ bnxt_hwrm_vnic_rss_cfg_hash_mode_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic (!BNXT_CHIP_P5(bp) && !(bp->vnic_cap_flags & BNXT_VNIC_CAP_OUTER_RSS))) return 0; + /* TODO Revisit for Thor 2 */ + /* if (BNXT_CHIP_P5_P7(bp)) + * bnxt_hwrm_vnic_rss_cfg_p5(bp, vnic); + */ /* Don't call RSS hash level configuration if the current * hash level is the same as the hash level that is requested. */ @@ -3274,7 +3341,8 @@ void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr) { struct bnxt_ring *cp_ring = cpr->cp_ring_struct; - bnxt_hwrm_ring_free(bp, cp_ring, + bnxt_hwrm_ring_free(bp, + cp_ring, HWRM_RING_FREE_INPUT_RING_TYPE_NQ, INVALID_HW_RING_ID); memset(cpr->cp_desc_ring, 0, @@ -3284,9 +3352,15 @@ void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr) void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr) { - struct bnxt_ring *cp_ring = cpr->cp_ring_struct; + struct bnxt_ring *cp_ring; + + cp_ring = cpr ? cpr->cp_ring_struct : NULL; - bnxt_hwrm_ring_free(bp, cp_ring, + if (cp_ring == NULL || cpr->cp_desc_ring == NULL) + return; + + bnxt_hwrm_ring_free(bp, + cp_ring, HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL, INVALID_HW_RING_ID); memset(cpr->cp_desc_ring, 0, @@ -4194,6 +4268,27 @@ int bnxt_hwrm_parent_pf_qcfg(struct bnxt *bp) return 0; } +static int bnxt_hwrm_set_tpa(struct bnxt *bp) +{ + struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; + uint64_t rx_offloads = dev_conf->rxmode.offloads; + bool tpa_flags = 0; + int rc, i; + + tpa_flags = (rx_offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO) ? true : false; + for (i = 0; i < bp->max_vnics; i++) { + struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; + + if (vnic->fw_vnic_id == INVALID_HW_RING_ID) + continue; + + rc = bnxt_hwrm_vnic_tpa_cfg(bp, vnic, tpa_flags); + if (rc) + return rc; + } + return 0; +} + int bnxt_hwrm_get_dflt_vnic_svif(struct bnxt *bp, uint16_t fid, uint16_t *vnic_id, uint16_t *svif) { @@ -4218,6 +4313,8 @@ int bnxt_hwrm_get_dflt_vnic_svif(struct bnxt *bp, uint16_t fid, HWRM_UNLOCK(); + bnxt_hwrm_set_tpa(bp); + return rc; } @@ -4764,27 +4861,6 @@ int bnxt_hwrm_pf_evb_mode(struct bnxt *bp) return rc; } -static int bnxt_hwrm_set_tpa(struct bnxt *bp) -{ - struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; - uint64_t rx_offloads = dev_conf->rxmode.offloads; - bool tpa_flags = 0; - int rc, i; - - tpa_flags = (rx_offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO) ? true : false; - for (i = 0; i < bp->max_vnics; i++) { - struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; - - if (vnic->fw_vnic_id == INVALID_HW_RING_ID) - continue; - - rc = bnxt_hwrm_vnic_tpa_cfg(bp, vnic, tpa_flags); - if (rc) - return rc; - } - return 0; -} - int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port, uint8_t tunnel_type) { @@ -5190,6 +5266,34 @@ int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id, return rc; } +int bnxt_hwrm_fwd_resp(struct bnxt *bp, uint16_t target_id, + void *encaped, size_t ec_size, + uint64_t encap_resp_addr, uint16_t cmpl_ring) +{ + int rc = 0; + struct hwrm_fwd_resp_input req = {.req_type = 0}; + struct hwrm_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr; + + if (ec_size > sizeof(req.encap_resp)) + return -1; + + HWRM_PREP(&req, HWRM_FWD_RESP, BNXT_USE_CHIMP_MB); + + req.target_id = rte_cpu_to_le_16(target_id); + req.encap_resp_target_id = rte_cpu_to_le_16(target_id); + req.encap_resp_len = rte_cpu_to_le_16(ec_size); + req.encap_resp_addr = encap_resp_addr; + req.encap_resp_cmpl_ring = cmpl_ring; + memcpy(req.encap_resp, encaped, ec_size); + + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); + + HWRM_CHECK_RESULT(); + HWRM_UNLOCK(); + + return rc; +} + static void bnxt_update_prev_stat(uint64_t *cntr, uint64_t *prev_cntr) { /* One of the HW stat values that make up this counter was zero as @@ -7436,7 +7540,8 @@ void bnxt_free_hwrm_tx_ring(struct bnxt *bp, int queue_index) struct bnxt_ring *ring = txr->tx_ring_struct; struct bnxt_cp_ring_info *cpr = txq->cp_ring; - bnxt_hwrm_ring_free(bp, ring, + bnxt_hwrm_ring_free(bp, + ring, HWRM_RING_FREE_INPUT_RING_TYPE_TX, cpr->cp_ring_struct->fw_ring_id); txr->tx_raw_prod = 0; @@ -7576,3 +7681,56 @@ int bnxt_hwrm_tf_oem_cmd(struct bnxt *bp, return rc; } + +int +bnxt_hwrm_vnic_update(struct bnxt *bp, + struct bnxt_vnic_info *vnic, + uint8_t valid) +{ + struct hwrm_vnic_update_input req = {0}; + struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr; + int rc; + + HWRM_PREP(&req, HWRM_VNIC_UPDATE, BNXT_USE_CHIMP_MB); + + req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id); + + if (valid & HWRM_VNIC_UPDATE_INPUT_ENABLES_METADATA_FORMAT_TYPE_VALID) + req.metadata_format_type = vnic->metadata_format; + if (valid & HWRM_VNIC_UPDATE_INPUT_ENABLES_VNIC_STATE_VALID) + req.vnic_state = vnic->state; + if (valid & HWRM_VNIC_UPDATE_INPUT_ENABLES_MRU_VALID) + req.mru = rte_cpu_to_le_16(vnic->mru); + + req.enables = rte_cpu_to_le_32(valid); + + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); + + HWRM_CHECK_RESULT(); + HWRM_UNLOCK(); + + return rc; +} + +int +bnxt_hwrm_release_afm_func(struct bnxt *bp, uint16_t fid, uint16_t rfid, + uint8_t type, uint32_t flags) +{ + int rc = 0; + struct hwrm_cfa_release_afm_func_input req = { 0 }; + struct hwrm_cfa_release_afm_func_output *resp = bp->hwrm_cmd_resp_addr; + + HWRM_PREP(&req, HWRM_CFA_RELEASE_AFM_FUNC, BNXT_USE_CHIMP_MB); + + req.fid = rte_le_to_cpu_16(fid); + req.rfid = rte_le_to_cpu_16(rfid); + req.flags = rte_le_to_cpu_32(flags); + req.type = type; + + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); + + HWRM_CHECK_RESULT(); + HWRM_UNLOCK(); + + return rc; +} diff --git a/drivers/net/bnxt/bnxt_hwrm.h b/drivers/net/bnxt/bnxt_hwrm.h index ec639bdbce..2346ae637d 100644 --- a/drivers/net/bnxt/bnxt_hwrm.h +++ b/drivers/net/bnxt/bnxt_hwrm.h @@ -193,6 +193,9 @@ int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id, void *encaped, size_t ec_size); int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id, void *encaped, size_t ec_size); +int bnxt_hwrm_fwd_resp(struct bnxt *bp, uint16_t target_id, + void *encaped, size_t ec_size, + uint64_t encap_resp_addr, uint16_t cmpl_ring); int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp, int num_vfs); int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp); @@ -241,6 +244,9 @@ int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic); int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic, bool enable); +int bnxt_hwrm_vnic_update(struct bnxt *bp, + struct bnxt_vnic_info *vnic, + uint8_t valid); int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp); int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp); @@ -384,4 +390,9 @@ int bnxt_hwrm_tf_oem_cmd(struct bnxt *bp, uint16_t in_len, uint32_t *out, uint16_t out_len); +int bnxt_hwrm_release_afm_func(struct bnxt *bp, + uint16_t fid, + uint16_t rfid, + uint8_t type, + uint32_t flags); #endif diff --git a/drivers/net/bnxt/bnxt_reps.c b/drivers/net/bnxt/bnxt_reps.c index 79b3583636..701f75f53c 100644 --- a/drivers/net/bnxt/bnxt_reps.c +++ b/drivers/net/bnxt/bnxt_reps.c @@ -324,20 +324,21 @@ static int bnxt_tf_vfr_alloc(struct rte_eth_dev *vfr_ethdev) struct bnxt *parent_bp = parent_dev->data->dev_private; if (!parent_bp || !parent_bp->ulp_ctx) { - BNXT_TF_DBG(ERR, "Invalid arguments\n"); + PMD_DRV_LOG(ERR, "Invalid arguments\n"); return 0; } /* update the port id so you can backtrack to ethdev */ vfr->dpdk_port_id = vfr_ethdev->data->port_id; /* If pair is present, then delete the pair */ - if (bnxt_hwrm_cfa_pair_exists(parent_bp, vfr)) - (void)bnxt_hwrm_cfa_pair_free(parent_bp, vfr); + if (!BNXT_CHIP_P7(parent_bp)) + if (bnxt_hwrm_cfa_pair_exists(parent_bp, vfr)) + (void)bnxt_hwrm_cfa_pair_free(parent_bp, vfr); /* Update the ULP portdata base with the new VFR interface */ rc = ulp_port_db_port_update(parent_bp->ulp_ctx, vfr_ethdev); if (rc) { - BNXT_TF_DBG(ERR, "Failed to update ulp port details vfr:%u\n", + PMD_DRV_LOG(ERR, "Failed to update ulp port details vfr:%u\n", vfr->vf_id); return rc; } @@ -345,21 +346,39 @@ static int bnxt_tf_vfr_alloc(struct rte_eth_dev *vfr_ethdev) /* Create the default rules for the VFR */ rc = bnxt_ulp_create_vfr_default_rules(vfr_ethdev); if (rc) { - BNXT_TF_DBG(ERR, "Failed to create VFR default rules vfr:%u\n", + PMD_DRV_LOG(ERR, "Failed to create VFR default rules vfr:%u\n", vfr->vf_id); return rc; } /* update the port id so you can backtrack to ethdev */ vfr->dpdk_port_id = vfr_ethdev->data->port_id; - rc = bnxt_hwrm_cfa_pair_alloc(parent_bp, vfr); - if (rc) { - BNXT_TF_DBG(ERR, "Failed in hwrm vfr alloc vfr:%u rc=%d\n", + if (BNXT_CHIP_P7(parent_bp)) { + rc = bnxt_hwrm_release_afm_func(parent_bp, + vfr->fw_fid, + parent_bp->fw_fid, + HWRM_CFA_RELEASE_AFM_FUNC_INPUT_TYPE_RFID, + 0); + + if (rc) + PMD_DRV_LOG(ERR, + "Failed in hwrm release afm func:%u rc=%d\n", vfr->vf_id, rc); - (void)bnxt_ulp_delete_vfr_default_rules(vfr); + } else { + rc = bnxt_hwrm_cfa_pair_alloc(parent_bp, vfr); + if (rc) + PMD_DRV_LOG(ERR, + "Failed in hwrm vfr alloc vfr:%u rc=%d\n", + vfr->vf_id, rc); } - BNXT_TF_DBG(DEBUG, "BNXT Port:%d VFR created and initialized\n", - vfr->dpdk_port_id); + + if (rc) + (void)bnxt_ulp_delete_vfr_default_rules(vfr); + else + PMD_DRV_LOG(DEBUG, + "BNXT Port:%d VFR created and initialized\n", + vfr->dpdk_port_id); + return rc; } @@ -444,7 +463,7 @@ int bnxt_rep_dev_start_op(struct rte_eth_dev *eth_dev) parent_bp = rep_bp->parent_dev->data->dev_private; rep_info = &parent_bp->rep_info[rep_bp->vf_id]; - BNXT_TF_DBG(DEBUG, "BNXT Port:%d VFR start\n", eth_dev->data->port_id); + PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR start\n", eth_dev->data->port_id); pthread_mutex_lock(&rep_info->vfr_start_lock); if (!rep_info->conduit_valid) { rc = bnxt_get_dflt_vnic_svif(parent_bp, rep_bp); @@ -470,7 +489,7 @@ int bnxt_rep_dev_start_op(struct rte_eth_dev *eth_dev) static int bnxt_tf_vfr_free(struct bnxt_representor *vfr) { - BNXT_TF_DBG(DEBUG, "BNXT Port:%d VFR ulp free\n", vfr->dpdk_port_id); + PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR ulp free\n", vfr->dpdk_port_id); return bnxt_ulp_delete_vfr_default_rules(vfr); } @@ -507,7 +526,8 @@ static int bnxt_vfr_free(struct bnxt_representor *vfr) vfr->vf_id); vfr->vfr_tx_cfa_action = 0; - rc = bnxt_hwrm_cfa_pair_free(parent_bp, vfr); + if (!BNXT_CHIP_P7(parent_bp)) + rc = bnxt_hwrm_cfa_pair_free(parent_bp, vfr); return rc; } @@ -519,7 +539,7 @@ int bnxt_rep_dev_stop_op(struct rte_eth_dev *eth_dev) /* Avoid crashes as we are about to free queues */ bnxt_stop_rxtx(eth_dev); - BNXT_TF_DBG(DEBUG, "BNXT Port:%d VFR stop\n", eth_dev->data->port_id); + PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR stop\n", eth_dev->data->port_id); bnxt_vfr_free(vfr_bp); @@ -533,7 +553,7 @@ int bnxt_rep_dev_stop_op(struct rte_eth_dev *eth_dev) int bnxt_rep_dev_close_op(struct rte_eth_dev *eth_dev) { - BNXT_TF_DBG(DEBUG, "BNXT Port:%d VFR close\n", eth_dev->data->port_id); + PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR close\n", eth_dev->data->port_id); bnxt_representor_uninit(eth_dev); return 0; } @@ -706,8 +726,13 @@ int bnxt_rep_rx_queue_setup_op(struct rte_eth_dev *eth_dev, return 0; out: - if (rxq) + if (rxq) { + #if (RTE_VERSION_NUM(21, 8, 0, 0) < RTE_VERSION) bnxt_rep_rx_queue_release_op(eth_dev, queue_idx); + #else + bnxt_rx_queue_release_op(rxq); + #endif + } return rc; } diff --git a/drivers/net/bnxt/bnxt_rxr.c b/drivers/net/bnxt/bnxt_rxr.c index b59989b5a1..6895e03151 100644 --- a/drivers/net/bnxt/bnxt_rxr.c +++ b/drivers/net/bnxt/bnxt_rxr.c @@ -19,9 +19,8 @@ #include "bnxt_rxq.h" #include "hsi_struct_def_dpdk.h" #include "bnxt_hwrm.h" - -#include <bnxt_tf_common.h> -#include <ulp_mark_mgr.h> +#include "bnxt_tf_common.h" +#include "ulp_mark_mgr.h" /* * RX Ring handling diff --git a/drivers/net/bnxt/bnxt_txr.c b/drivers/net/bnxt/bnxt_txr.c index 83c003d258..2a2dbba015 100644 --- a/drivers/net/bnxt/bnxt_txr.c +++ b/drivers/net/bnxt/bnxt_txr.c @@ -522,6 +522,13 @@ static void bnxt_tx_cmp(struct bnxt_tx_queue *txq, int nr_pkts) txr->tx_raw_cons = raw_cons; } +static bool bnxt_is_tx_cmpl_type(uint16_t type) +{ + return (type == CMPL_BASE_TYPE_TX_L2_PKT_TS || + type == CMPL_BASE_TYPE_TX_L2_COAL || + type == CMPL_BASE_TYPE_TX_L2); +} + static int bnxt_handle_tx_cp(struct bnxt_tx_queue *txq) { uint32_t nb_tx_pkts = 0, cons, ring_mask, opaque; @@ -545,7 +552,7 @@ static int bnxt_handle_tx_cp(struct bnxt_tx_queue *txq) opaque = rte_le_to_cpu_32(txcmp->opaque); - if (CMP_TYPE(txcmp) == TX_CMPL_TYPE_TX_L2) + if (bnxt_is_tx_cmpl_type(CMP_TYPE(txcmp))) nb_tx_pkts += opaque; else RTE_LOG_DP(ERR, BNXT, @@ -637,6 +644,16 @@ int bnxt_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id) if (rc) return rc; + /* reset the previous stats for the tx_queue since the counters + * will be cleared when the queue is started. + */ + if (BNXT_TPA_V2_P7(bp)) + memset(&bp->prev_tx_ring_stats_ext[tx_queue_id], 0, + sizeof(struct bnxt_ring_stats)); + else + memset(&bp->prev_tx_ring_stats[tx_queue_id], 0, + sizeof(struct bnxt_ring_stats)); + dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED; txq->tx_started = true; PMD_DRV_LOG(DEBUG, "Tx queue started\n"); @@ -664,6 +681,15 @@ int bnxt_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id) return 0; } +static bool bnxt_is_tx_mpc_flush_cmpl_type(uint16_t type) +{ + return (type == CMPL_BASE_TYPE_TX_L2_PKT_TS || + type == CMPL_BASE_TYPE_TX_L2_COAL || + type == CMPL_BASE_TYPE_TX_L2 || + type == CMPL_BASE_TYPE_MID_PATH_SHORT || + type == CMPL_BASE_TYPE_MID_PATH_LONG); +} + /* Sweep the Tx completion queue till HWRM_DONE for ring flush is received. * The mbufs will not be freed in this call. * They will be freed during ring free as a part of mem cleanup. @@ -689,7 +715,7 @@ int bnxt_flush_tx_cmp(struct bnxt_cp_ring_info *cpr) opaque = rte_cpu_to_le_32(txcmp->opaque); raw_cons = NEXT_RAW_CMP(raw_cons); - if (CMP_TYPE(txcmp) == TX_CMPL_TYPE_TX_L2) + if (bnxt_is_tx_mpc_flush_cmpl_type(CMP_TYPE(txcmp))) nb_tx_pkts += opaque; else if (CMP_TYPE(txcmp) == HWRM_CMPL_TYPE_HWRM_DONE) return 1; diff --git a/drivers/net/bnxt/bnxt_vnic.h b/drivers/net/bnxt/bnxt_vnic.h index 93155648e2..fe3fc4e540 100644 --- a/drivers/net/bnxt/bnxt_vnic.h +++ b/drivers/net/bnxt/bnxt_vnic.h @@ -81,6 +81,8 @@ struct bnxt_vnic_info { uint8_t ring_select_mode; enum rte_eth_hash_function hash_f_local; uint64_t rss_types_local; + uint8_t metadata_format; + uint8_t state; }; struct bnxt_vnic_queue_db { diff --git a/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h b/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h index cd4cd8ac74..bfbbf76c16 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h +++ b/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h @@ -11,9 +11,13 @@ #include "bnxt_ulp.h" #include "ulp_template_db_enum.h" -#define BNXT_TF_DBG(lvl, fmt, args...) PMD_DRV_LOG(lvl, fmt, ## args) +#define BNXT_DRV_DBG(lvl, fmt, args...) PMD_DRV_LOG(lvl, fmt, ## args) -#define BNXT_TF_INF(fmt, args...) +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG +#define BNXT_DRV_INF(fmt, args...) PMD_DRV_LOG(INFO, fmt, ## args) +#else +#define BNXT_DRV_INF(fmt, args...) +#endif #define BNXT_ULP_EM_FLOWS 8192 #define BNXT_ULP_1M_FLOWS 1000000 @@ -68,4 +72,5 @@ bnxt_ulp_cntxt_ptr2_mark_db_get(struct bnxt_ulp_context *ulp_ctx); int32_t bnxt_ulp_cntxt_ptr2_mark_db_set(struct bnxt_ulp_context *ulp_ctx, struct bnxt_ulp_mark_tbl *mark_tbl); + #endif /* _BNXT_TF_COMMON_H_ */ diff --git a/drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.c b/drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.c index 5bee25d9d3..dd67165a78 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.c @@ -57,32 +57,6 @@ bnxt_tunnel_upar_id_get(struct bnxt *bp, type); } -struct bnxt * -bnxt_pmd_get_bp(uint16_t port) -{ - struct bnxt *bp; - struct rte_eth_dev *dev; - - if (!rte_eth_dev_is_valid_port(port)) { - PMD_DRV_LOG(ERR, "Invalid port %d\n", port); - return NULL; - } - - dev = &rte_eth_devices[port]; - if (!is_bnxt_supported(dev)) { - PMD_DRV_LOG(ERR, "Device %d not supported\n", port); - return NULL; - } - - bp = (struct bnxt *)dev->data->dev_private; - if (!BNXT_TRUFLOW_EN(bp)) { - PMD_DRV_LOG(ERR, "TRUFLOW not enabled\n"); - return NULL; - } - - return bp; -} - int32_t bnxt_rss_config_action_apply(struct bnxt_ulp_mapper_parms *parms) { struct bnxt_vnic_info *vnic = NULL; @@ -93,20 +67,24 @@ int32_t bnxt_rss_config_action_apply(struct bnxt_ulp_mapper_parms *parms) uint8_t *rss_key; struct ulp_rte_act_prop *ap = parms->act_prop; int32_t rc = -EINVAL; + uint8_t rss_func; bp = bnxt_pmd_get_bp(parms->port_id); if (bp == NULL) { - BNXT_TF_DBG(ERR, "Invalid bp for port_id %u\n", parms->port_id); + BNXT_DRV_DBG(ERR, "Invalid bp for port_id %u\n", + parms->port_id); return rc; } vnic = bnxt_get_default_vnic(bp); if (vnic == NULL) { - BNXT_TF_DBG(ERR, "default vnic not available for %u\n", - parms->port_id); + BNXT_DRV_DBG(ERR, "default vnic not available for %u\n", + parms->port_id); return rc; } /* get the details */ + memcpy(&rss_func, &ap->act_details[BNXT_ULP_ACT_PROP_IDX_RSS_FUNC], + BNXT_ULP_ACT_PROP_SZ_RSS_FUNC); memcpy(&rss_types, &ap->act_details[BNXT_ULP_ACT_PROP_IDX_RSS_TYPES], BNXT_ULP_ACT_PROP_SZ_RSS_TYPES); memcpy(&rss_level, &ap->act_details[BNXT_ULP_ACT_PROP_IDX_RSS_LEVEL], @@ -115,9 +93,16 @@ int32_t bnxt_rss_config_action_apply(struct bnxt_ulp_mapper_parms *parms) BNXT_ULP_ACT_PROP_SZ_RSS_KEY_LEN); rss_key = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_RSS_KEY]; + rc = bnxt_rte_flow_to_hwrm_ring_select_mode((enum rte_eth_hash_function)rss_func, + rss_types, bp, vnic); + if (rc != 0) { + BNXT_DRV_DBG(ERR, "Error unsupported rss hash func\n"); + return rc; + } + hwrm_type = bnxt_rte_to_hwrm_hash_types(rss_types); if (!hwrm_type) { - BNXT_TF_DBG(ERR, "Error unsupported rss config type\n"); + BNXT_DRV_DBG(ERR, "Error unsupported rss config type\n"); return rc; } /* Configure RSS only if the queue count is > 1 */ @@ -129,10 +114,10 @@ int32_t bnxt_rss_config_action_apply(struct bnxt_ulp_mapper_parms *parms) BNXT_ULP_ACT_PROP_SZ_RSS_KEY); rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic); if (rc) { - BNXT_TF_DBG(ERR, "Error configuring vnic RSS config\n"); + BNXT_DRV_DBG(ERR, "Error configuring vnic RSS config\n"); return rc; } - BNXT_TF_DBG(INFO, "Rss config successfully applied\n"); + BNXT_DRV_DBG(INFO, "Rss config successfully applied\n"); } return 0; } @@ -144,7 +129,7 @@ int32_t bnxt_rss_config_action_apply(struct bnxt_ulp_mapper_parms *parms) static int32_t glob_error_fn(const char *epath, int32_t eerrno) { - BNXT_TF_DBG(ERR, "path %s error %d\n", epath, eerrno); + BNXT_DRV_DBG(ERR, "path %s error %d\n", epath, eerrno); return 0; } @@ -170,13 +155,13 @@ static int32_t ulp_pmd_get_mac_by_pci(const char *pci_name, uint8_t *mac) fp = fopen(path, "r"); if (!fp) { - BNXT_TF_DBG(ERR, "Error in getting bond mac address\n"); + BNXT_DRV_DBG(ERR, "Error in getting bond mac address\n"); return rc; } memset(dev_str, 0, sizeof(dev_str)); if (fgets(dev_str, sizeof(dev_str), fp) == NULL) { - BNXT_TF_DBG(ERR, "Error in reading %s\n", path); + BNXT_DRV_DBG(ERR, "Error in reading %s\n", path); fclose(fp); return rc; } @@ -198,7 +183,8 @@ int32_t bnxt_pmd_get_parent_mac_addr(struct bnxt_ulp_mapper_parms *parms, bp = bnxt_pmd_get_bp(parms->port_id); if (bp == NULL) { - BNXT_TF_DBG(ERR, "Invalid bp for port_id %u\n", parms->port_id); + BNXT_DRV_DBG(ERR, "Invalid bp for port_id %u\n", + parms->port_id); return rc; } return ulp_pmd_get_mac_by_pci(bp->pdev->name, &mac[2]); @@ -424,7 +410,8 @@ int32_t bnxt_pmd_queue_action_create(struct bnxt_ulp_mapper_parms *parms, bp = bnxt_pmd_get_bp(parms->port_id); if (bp == NULL) { - BNXT_TF_DBG(ERR, "Invalid bp for port_id %u\n", parms->port_id); + BNXT_DRV_DBG(ERR, "Invalid bp for port_id %u\n", + parms->port_id); return -EINVAL; } @@ -434,15 +421,8 @@ int32_t bnxt_pmd_queue_action_create(struct bnxt_ulp_mapper_parms *parms, return bnxt_vnic_queue_action_alloc(bp, q_index, vnic_idx, vnic_id); } -int32_t bnxt_pmd_queue_action_delete(struct tf *tfp, uint16_t vnic_idx) +int32_t bnxt_pmd_queue_action_delete(struct bnxt *bp, uint16_t vnic_idx) { - struct bnxt *bp = NULL; - - bp = tfp->bp; - if (bp == NULL) { - BNXT_TF_DBG(ERR, "Invalid bp\n"); - return -EINVAL; - } return bnxt_vnic_queue_action_free(bp, vnic_idx); } @@ -455,12 +435,16 @@ int32_t bnxt_pmd_rss_action_create(struct bnxt_ulp_mapper_parms *parms, bp = bnxt_pmd_get_bp(parms->port_id); if (bp == NULL) { - BNXT_TF_DBG(ERR, "Invalid bp for port_id %u\n", parms->port_id); + BNXT_DRV_DBG(ERR, "Invalid bp for port_id %u\n", + parms->port_id); return -EINVAL; } /* get the details */ memset(&rss_info, 0, sizeof(rss_info)); + memcpy(&rss_info.rss_func, + &ap->act_details[BNXT_ULP_ACT_PROP_IDX_RSS_FUNC], + BNXT_ULP_ACT_PROP_SZ_RSS_FUNC); memcpy(&rss_info.rss_types, &ap->act_details[BNXT_ULP_ACT_PROP_IDX_RSS_TYPES], BNXT_ULP_ACT_PROP_SZ_RSS_TYPES); @@ -478,7 +462,7 @@ int32_t bnxt_pmd_rss_action_create(struct bnxt_ulp_mapper_parms *parms, /* Validate the size of the queue list */ if (sizeof(rss_info.queue_list) < BNXT_ULP_ACT_PROP_SZ_RSS_QUEUE) { - BNXT_TF_DBG(ERR, "Mismatch of RSS queue size in template\n"); + BNXT_DRV_DBG(ERR, "Mismatch of RSS queue size in template\n"); return -EINVAL; } memcpy(rss_info.queue_list, @@ -488,14 +472,8 @@ int32_t bnxt_pmd_rss_action_create(struct bnxt_ulp_mapper_parms *parms, return bnxt_vnic_rss_action_alloc(bp, &rss_info, vnic_idx, vnic_id); } -int32_t bnxt_pmd_rss_action_delete(struct tf *tfp, uint16_t vnic_idx) +int32_t bnxt_pmd_rss_action_delete(struct bnxt *bp, uint16_t vnic_idx) { - struct bnxt *bp = tfp->bp; - - if (bp == NULL) { - BNXT_TF_DBG(ERR, "Invalid bp\n"); - return -EINVAL; - } return bnxt_vnic_rss_action_free(bp, vnic_idx); } @@ -563,14 +541,14 @@ bnxt_pmd_global_tunnel_set(uint16_t port_id, uint8_t type, hwtype = HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6; break; default: - BNXT_TF_DBG(ERR, "Tunnel Type (%d) invalid\n", type); + BNXT_DRV_DBG(ERR, "Tunnel Type (%d) invalid\n", type); return -EINVAL; } if (!udp_port) { /* Free based on the handle */ if (!handle) { - BNXT_TF_DBG(ERR, "Free with invalid handle\n"); + BNXT_DRV_DBG(ERR, "Free with invalid handle\n"); return -EINVAL; } bnxt_pmd_global_reg_hndl_to_data(*handle, &lport_id, @@ -578,8 +556,8 @@ bnxt_pmd_global_tunnel_set(uint16_t port_id, uint8_t type, bp = bnxt_pmd_get_bp(lport_id); if (!bp) { - BNXT_TF_DBG(ERR, "Unable to get dev by port %d\n", - lport_id); + BNXT_DRV_DBG(ERR, "Unable to get dev by port %d\n", + lport_id); return -EINVAL; } @@ -588,9 +566,9 @@ bnxt_pmd_global_tunnel_set(uint16_t port_id, uint8_t type, ldport = ulp_global_tunnel_db[ltype].dport; rc = bnxt_hwrm_tunnel_dst_port_free(bp, ldport, hwtype); if (rc) { - BNXT_TF_DBG(ERR, - "Unable to free tunnel dst port (%d)\n", - ldport); + BNXT_DRV_DBG(ERR, + "Unable to free tunnel dst port (%d)\n", + ldport); return rc; } ulp_global_tunnel_db[ltype].ref_cnt--; @@ -599,8 +577,8 @@ bnxt_pmd_global_tunnel_set(uint16_t port_id, uint8_t type, } else { bp = bnxt_pmd_get_bp(port_id); if (!bp) { - BNXT_TF_DBG(ERR, "Unable to get dev by port %d\n", - port_id); + BNXT_DRV_DBG(ERR, "Unable to get dev by port %d\n", + port_id); return -EINVAL; } @@ -638,6 +616,25 @@ static bool bnxt_pmd_get_hot_upgrade_env(void) return hot_up; } +int32_t bnxt_pmd_bd_act_set(uint16_t port_id, uint32_t act) +{ + struct rte_eth_dev *eth_dev; + int32_t rc = -EINVAL; + + eth_dev = &rte_eth_devices[port_id]; + if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { + struct bnxt_representor *vfr = eth_dev->data->dev_private; + if (!vfr) + return rc; + vfr->vfr_tx_cfa_action = act; + } else { + struct bnxt *bp = eth_dev->data->dev_private; + bp->tx_cfa_action = act; + } + + return 0; +} + static bool hot_up_api; static bool hot_up_configured_by_api; /* There are two ways to configure hot upgrade. diff --git a/drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.h b/drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.h index 10c146e494..a2feeda528 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.h +++ b/drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.h @@ -43,10 +43,10 @@ enum bnxt_ulp_intf_type bnxt_pmd_get_interface_type(uint16_t port); int32_t bnxt_pmd_set_unicast_rxmask(struct rte_eth_dev *eth_dev); int32_t bnxt_pmd_queue_action_create(struct bnxt_ulp_mapper_parms *parms, uint16_t *vnic_idx, uint16_t *vnic_id); -int32_t bnxt_pmd_queue_action_delete(struct tf *tfp, uint16_t vnic_idx); +int32_t bnxt_pmd_queue_action_delete(struct bnxt *bp, uint16_t vnic_idx); int32_t bnxt_pmd_rss_action_create(struct bnxt_ulp_mapper_parms *parms, uint16_t *vnic_idx, uint16_t *vnic_id); -int32_t bnxt_pmd_rss_action_delete(struct tf *tfp, uint16_t vnic_idx); +int32_t bnxt_pmd_rss_action_delete(struct bnxt *bp, uint16_t vnic_idx); int32_t bnxt_tunnel_dst_port_free(struct bnxt *bp, uint16_t port, uint8_t type); @@ -61,4 +61,8 @@ bnxt_tunnel_upar_id_get(struct bnxt *bp, uint8_t type, uint8_t *upar_id); bool bnxt_pmd_get_hot_up_config(void); +int32_t ulp_ctx_mh_get_session_name(struct bnxt *bp, + struct tf_open_session_parms *parms); + +int32_t bnxt_pmd_bd_act_set(uint16_t port_id, uint32_t act); #endif /* _BNXT_TF_PMD_ABSTRACT_H_ */ diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c index a7df525c16..4e64434b4a 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c @@ -13,6 +13,7 @@ #include "bnxt.h" #include "bnxt_ulp.h" #include "bnxt_tf_common.h" +#include "bnxt_hwrm.h" #include "hsi_struct_def_dpdk.h" #include "tf_core.h" #include "tf_ext_flow_handle.h" @@ -23,11 +24,13 @@ #include "ulp_fc_mgr.h" #include "ulp_flow_db.h" #include "ulp_mapper.h" +#include "ulp_matcher.h" #include "ulp_port_db.h" #include "ulp_tun.h" #include "ulp_ha_mgr.h" #include "bnxt_tf_pmd_shim.h" #include "ulp_template_db_tbl.h" +#include "ulp_utils.h" /* Linked list of all TF sessions. */ STAILQ_HEAD(, bnxt_ulp_session_state) bnxt_ulp_session_list = @@ -43,11 +46,6 @@ TAILQ_HEAD(cntx_list_entry_list, ulp_context_list_entry); static struct cntx_list_entry_list ulp_cntx_list = TAILQ_HEAD_INITIALIZER(ulp_cntx_list); -/* Static function declarations */ -static int32_t bnxt_ulp_cntxt_list_init(void); -static int32_t bnxt_ulp_cntxt_list_add(struct bnxt_ulp_context *ulp_ctx); -static void bnxt_ulp_cntxt_list_del(struct bnxt_ulp_context *ulp_ctx); - bool ulp_is_default_session_active(struct bnxt_ulp_context *ulp_ctx) { @@ -56,6 +54,7 @@ ulp_is_default_session_active(struct bnxt_ulp_context *ulp_ctx) return true; } + /* * Allow the deletion of context only for the bnxt device that * created the session. @@ -67,17 +66,22 @@ ulp_ctx_deinit_allowed(struct bnxt_ulp_context *ulp_ctx) return false; if (!ulp_ctx->cfg_data->ref_cnt) { - BNXT_TF_DBG(DEBUG, "ulp ctx shall initiate deinit\n"); + BNXT_DRV_DBG(DEBUG, "ulp ctx shall initiate deinit\n"); return true; } return false; } -static int32_t +int32_t bnxt_ulp_devid_get(struct bnxt *bp, enum bnxt_ulp_device_id *ulp_dev_id) { + if (BNXT_CHIP_P7(bp)) { + *ulp_dev_id = BNXT_ULP_DEVICE_ID_THOR2; + return 0; + } + if (BNXT_CHIP_P5(bp)) { *ulp_dev_id = BNXT_ULP_DEVICE_ID_THOR; return 0; @@ -86,7 +90,7 @@ bnxt_ulp_devid_get(struct bnxt *bp, if (BNXT_STINGRAY(bp)) *ulp_dev_id = BNXT_ULP_DEVICE_ID_STINGRAY; else - /* Assuming P4 */ + /* Assuming Whitney */ *ulp_dev_id = BNXT_ULP_DEVICE_ID_WH_PLUS; return 0; @@ -112,7 +116,7 @@ bnxt_ulp_shared_act_info_get(uint32_t *num_entries) return ulp_shared_act_info; } -static struct bnxt_ulp_resource_resv_info * +struct bnxt_ulp_resource_resv_info * bnxt_ulp_app_resource_resv_list_get(uint32_t *num_entries) { if (num_entries == NULL) @@ -139,365 +143,9 @@ bnxt_ulp_app_glb_resource_info_list_get(uint32_t *num_entries) return ulp_app_glb_resource_tbl; } -static int32_t -bnxt_ulp_named_resources_calc(struct bnxt_ulp_context *ulp_ctx, - struct bnxt_ulp_glb_resource_info *info, - uint32_t num, - enum bnxt_ulp_session_type stype, - struct tf_session_resources *res) -{ - uint32_t dev_id = BNXT_ULP_DEVICE_ID_LAST, res_type, i; - enum tf_dir dir; - uint8_t app_id; - int32_t rc = 0; - - if (ulp_ctx == NULL || info == NULL || res == NULL || num == 0) { - BNXT_TF_DBG(ERR, "Invalid parms to named resources calc.\n"); - return -EINVAL; - } - - rc = bnxt_ulp_cntxt_app_id_get(ulp_ctx, &app_id); - if (rc) { - BNXT_TF_DBG(ERR, "Unable to get the app id from ulp.\n"); - return -EINVAL; - } - - rc = bnxt_ulp_cntxt_dev_id_get(ulp_ctx, &dev_id); - if (rc) { - BNXT_TF_DBG(ERR, "Unable to get the dev id from ulp.\n"); - return -EINVAL; - } - - for (i = 0; i < num; i++) { - if (dev_id != info[i].device_id || app_id != info[i].app_id) - continue; - /* check to see if the session type matches only then include */ - if ((stype || info[i].session_type) && - !(info[i].session_type & stype)) - continue; - - dir = info[i].direction; - res_type = info[i].resource_type; - - switch (info[i].resource_func) { - case BNXT_ULP_RESOURCE_FUNC_IDENTIFIER: - res->ident_cnt[dir].cnt[res_type]++; - break; - case BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE: - res->tbl_cnt[dir].cnt[res_type]++; - break; - case BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE: - res->tcam_cnt[dir].cnt[res_type]++; - break; - case BNXT_ULP_RESOURCE_FUNC_EM_TABLE: - res->em_cnt[dir].cnt[res_type]++; - break; - default: - BNXT_TF_DBG(ERR, "Unknown resource func (0x%x)\n,", - info[i].resource_func); - continue; - } - } - - return 0; -} - -static int32_t -bnxt_ulp_unnamed_resources_calc(struct bnxt_ulp_context *ulp_ctx, - struct bnxt_ulp_resource_resv_info *info, - uint32_t num, - enum bnxt_ulp_session_type stype, - struct tf_session_resources *res) -{ - uint32_t dev_id, res_type, i; - enum tf_dir dir; - uint8_t app_id; - int32_t rc = 0; - - if (ulp_ctx == NULL || res == NULL || info == NULL || num == 0) { - BNXT_TF_DBG(ERR, "Invalid arguments to get resources.\n"); - return -EINVAL; - } - - rc = bnxt_ulp_cntxt_app_id_get(ulp_ctx, &app_id); - if (rc) { - BNXT_TF_DBG(ERR, "Unable to get the app id from ulp.\n"); - return -EINVAL; - } - - rc = bnxt_ulp_cntxt_dev_id_get(ulp_ctx, &dev_id); - if (rc) { - BNXT_TF_DBG(ERR, "Unable to get the dev id from ulp.\n"); - return -EINVAL; - } - - for (i = 0; i < num; i++) { - if (app_id != info[i].app_id || dev_id != info[i].device_id) - continue; - - /* check to see if the session type matches only then include */ - if ((stype || info[i].session_type) && - !(info[i].session_type & stype)) - continue; - - dir = info[i].direction; - res_type = info[i].resource_type; - - switch (info[i].resource_func) { - case BNXT_ULP_RESOURCE_FUNC_IDENTIFIER: - res->ident_cnt[dir].cnt[res_type] = info[i].count; - break; - case BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE: - res->tbl_cnt[dir].cnt[res_type] = info[i].count; - break; - case BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE: - res->tcam_cnt[dir].cnt[res_type] = info[i].count; - break; - case BNXT_ULP_RESOURCE_FUNC_EM_TABLE: - res->em_cnt[dir].cnt[res_type] = info[i].count; - break; - default: - break; - } - } - return 0; -} - -static int32_t -bnxt_ulp_tf_resources_get(struct bnxt_ulp_context *ulp_ctx, - enum bnxt_ulp_session_type stype, - struct tf_session_resources *res) -{ - struct bnxt_ulp_resource_resv_info *unnamed = NULL; - uint32_t unum; - int32_t rc = 0; - - if (ulp_ctx == NULL || res == NULL) { - BNXT_TF_DBG(ERR, "Invalid arguments to get resources.\n"); - return -EINVAL; - } - - /* use DEFAULT_NON_HA instead of DEFAULT resources if HA is disabled */ - if (ULP_APP_HA_IS_DYNAMIC(ulp_ctx)) - stype = ulp_ctx->cfg_data->def_session_type; - - unnamed = bnxt_ulp_resource_resv_list_get(&unum); - if (unnamed == NULL) { - BNXT_TF_DBG(ERR, "Unable to get resource resv list.\n"); - return -EINVAL; - } - - rc = bnxt_ulp_unnamed_resources_calc(ulp_ctx, unnamed, unum, stype, - res); - if (rc) - BNXT_TF_DBG(ERR, "Unable to calc resources for session.\n"); - - return rc; -} - -static int32_t -bnxt_ulp_tf_shared_session_resources_get(struct bnxt_ulp_context *ulp_ctx, - enum bnxt_ulp_session_type stype, - struct tf_session_resources *res) -{ - struct bnxt_ulp_resource_resv_info *unnamed; - struct bnxt_ulp_glb_resource_info *named; - uint32_t unum = 0, nnum = 0; - int32_t rc; - - if (ulp_ctx == NULL || res == NULL) { - BNXT_TF_DBG(ERR, "Invalid arguments to get resources.\n"); - return -EINVAL; - } - - /* Make sure the resources are zero before accumulating. */ - memset(res, 0, sizeof(struct tf_session_resources)); - - if (bnxt_ulp_cntxt_ha_enabled(ulp_ctx) && - stype == BNXT_ULP_SESSION_TYPE_SHARED) - stype = ulp_ctx->cfg_data->hu_session_type; - - /* - * Shared resources are comprised of both named and unnamed resources. - * First get the unnamed counts, and then add the named to the result. - */ - /* Get the baseline counts */ - unnamed = bnxt_ulp_app_resource_resv_list_get(&unum); - if (unum) { - rc = bnxt_ulp_unnamed_resources_calc(ulp_ctx, unnamed, unum, stype, - res); - if (rc) { - BNXT_TF_DBG(ERR, - "Unable to calc resources for shared session.\n"); - return -EINVAL; - } - } - - /* Get the named list and add the totals */ - named = bnxt_ulp_app_glb_resource_info_list_get(&nnum); - if (!nnum) - return 0; - - rc = bnxt_ulp_named_resources_calc(ulp_ctx, named, nnum, stype, res); - if (rc) - BNXT_TF_DBG(ERR, "Unable to calc named resources\n"); - - return rc; -} - -/* Function to set the hot upgrade support into the context */ -static int -bnxt_ulp_multi_shared_session_support_set(struct bnxt *bp, - enum bnxt_ulp_device_id devid, - uint32_t fw_hu_update) -{ - struct bnxt_ulp_context *ulp_ctx = bp->ulp_ctx; - struct tf_get_version_parms v_params = { 0 }; - struct tf *tfp; - int32_t rc = 0; - int32_t new_fw = 0; - - v_params.device_type = bnxt_ulp_cntxt_convert_dev_id(devid); - v_params.bp = bp; - - tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_DEFAULT); - rc = tf_get_version(tfp, &v_params); - if (rc) { - BNXT_TF_DBG(ERR, "Unable to get tf version.\n"); - return rc; - } - - if (v_params.major == 1 && v_params.minor == 0 && - v_params.update == 1) { - new_fw = 1; - } - /* if the version update is greater than 0 then set support for - * multiple version - */ - if (new_fw) { - ulp_ctx->cfg_data->ulp_flags |= BNXT_ULP_MULTI_SHARED_SUPPORT; - ulp_ctx->cfg_data->hu_session_type = - BNXT_ULP_SESSION_TYPE_SHARED; - } - if (!new_fw && fw_hu_update) { - ulp_ctx->cfg_data->ulp_flags &= ~BNXT_ULP_HIGH_AVAIL_ENABLED; - ulp_ctx->cfg_data->hu_session_type = - BNXT_ULP_SESSION_TYPE_SHARED | - BNXT_ULP_SESSION_TYPE_SHARED_OWC; - } - - if (!new_fw && !fw_hu_update) { - ulp_ctx->cfg_data->hu_session_type = - BNXT_ULP_SESSION_TYPE_SHARED | - BNXT_ULP_SESSION_TYPE_SHARED_OWC; - } - - return rc; -} - -int32_t -bnxt_ulp_cntxt_app_caps_init(struct bnxt *bp, - uint8_t app_id, uint32_t dev_id) -{ - struct bnxt_ulp_app_capabilities_info *info; - uint32_t num = 0, fw = 0; - uint16_t i; - bool found = false; - struct bnxt_ulp_context *ulp_ctx = bp->ulp_ctx; - - if (ULP_APP_DEV_UNSUPPORTED_ENABLED(ulp_ctx->cfg_data->ulp_flags)) { - BNXT_TF_DBG(ERR, "APP ID %d, Device ID: 0x%x not supported.\n", - app_id, dev_id); - return -EINVAL; - } - - info = bnxt_ulp_app_cap_list_get(&num); - if (!info || !num) { - BNXT_TF_DBG(ERR, "Failed to get app capabilities.\n"); - return -EINVAL; - } - - for (i = 0; i < num; i++) { - if (info[i].app_id != app_id || info[i].device_id != dev_id) - continue; - found = true; - if (info[i].flags & BNXT_ULP_APP_CAP_SHARED_EN) - ulp_ctx->cfg_data->ulp_flags |= - BNXT_ULP_SHARED_SESSION_ENABLED; - if (info[i].flags & BNXT_ULP_APP_CAP_HOT_UPGRADE_EN) - ulp_ctx->cfg_data->ulp_flags |= - BNXT_ULP_HIGH_AVAIL_ENABLED; - if (info[i].flags & BNXT_ULP_APP_CAP_UNICAST_ONLY) - ulp_ctx->cfg_data->ulp_flags |= - BNXT_ULP_APP_UNICAST_ONLY; - if (info[i].flags & BNXT_ULP_APP_CAP_IP_TOS_PROTO_SUPPORT) - ulp_ctx->cfg_data->ulp_flags |= - BNXT_ULP_APP_TOS_PROTO_SUPPORT; - if (info[i].flags & BNXT_ULP_APP_CAP_BC_MC_SUPPORT) - ulp_ctx->cfg_data->ulp_flags |= - BNXT_ULP_APP_BC_MC_SUPPORT; - if (info[i].flags & BNXT_ULP_APP_CAP_SOCKET_DIRECT) { - /* Enable socket direction only if MR is enabled in fw*/ - if (BNXT_MULTIROOT_EN(bp)) { - ulp_ctx->cfg_data->ulp_flags |= - BNXT_ULP_APP_SOCKET_DIRECT; - BNXT_TF_DBG(INFO, - "Socket Direct feature is enabled\n"); - } - } - if (info[i].flags & BNXT_ULP_APP_CAP_HA_DYNAMIC) { - /* Read the environment variable to determine hot up */ - if (!bnxt_pmd_get_hot_up_config()) { - ulp_ctx->cfg_data->ulp_flags |= - BNXT_ULP_APP_HA_DYNAMIC; - /* reset Hot upgrade, dynamically disabled */ - ulp_ctx->cfg_data->ulp_flags &= - ~BNXT_ULP_HIGH_AVAIL_ENABLED; - ulp_ctx->cfg_data->def_session_type = - BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA; - BNXT_TF_DBG(INFO, "Hot upgrade disabled.\n"); - } - } - - if (info[i].flags & BNXT_ULP_APP_CAP_L2_ETYPE) - ulp_ctx->cfg_data->ulp_flags |= - BNXT_ULP_APP_L2_ETYPE; - - if (info[i].flags & BNXT_ULP_APP_CAP_CUST_VXLAN) - ulp_ctx->cfg_data->ulp_flags |= - BNXT_ULP_CUST_VXLAN_SUPPORT; - - bnxt_ulp_vxlan_ip_port_set(ulp_ctx, info[i].vxlan_ip_port); - bnxt_ulp_vxlan_port_set(ulp_ctx, info[i].vxlan_port); - bnxt_ulp_ecpri_udp_port_set(ulp_ctx, info[i].ecpri_udp_port); - bnxt_ulp_vxlan_gpe_next_proto_set(ulp_ctx, info[i].tunnel_next_proto); - - /* set the shared session support from firmware */ - fw = info[i].upgrade_fw_update; - if (ULP_HIGH_AVAIL_IS_ENABLED(ulp_ctx->cfg_data->ulp_flags) && - bnxt_ulp_multi_shared_session_support_set(bp, dev_id, fw)) { - BNXT_TF_DBG(ERR, - "Unable to get shared session support\n"); - return -EINVAL; - } - bnxt_ulp_ha_reg_set(ulp_ctx, info[i].ha_reg_state, - info[i].ha_reg_cnt); - ulp_ctx->cfg_data->ha_pool_id = info[i].ha_pool_id; - ulp_ctx->cfg_data->default_priority = info[i].default_priority; - } - if (!found) { - BNXT_TF_DBG(ERR, "APP ID %d, Device ID: 0x%x not supported.\n", - app_id, dev_id); - ulp_ctx->cfg_data->ulp_flags |= BNXT_ULP_APP_DEV_UNSUPPORTED; - return -EINVAL; - } - - return 0; -} - -/* Function to retrieve the vxlan_ip (ecpri) port from the context. */ +/* Function to set the number for vxlan_ip (custom vxlan) port into the context */ int -bnxt_ulp_ecpri_udp_port_set(struct bnxt_ulp_context *ulp_ctx, +bnxt_ulp_cntxt_ecpri_udp_port_set(struct bnxt_ulp_context *ulp_ctx, uint32_t ecpri_udp_port) { if (!ulp_ctx || !ulp_ctx->cfg_data) @@ -508,9 +156,9 @@ bnxt_ulp_ecpri_udp_port_set(struct bnxt_ulp_context *ulp_ctx, return 0; } -/* Function to retrieve the vxlan_ip (ecpri) port from the context. */ +/* Function to retrieve the vxlan_ip (custom vxlan) port from the context. */ unsigned int -bnxt_ulp_ecpri_udp_port_get(struct bnxt_ulp_context *ulp_ctx) +bnxt_ulp_cntxt_ecpri_udp_port_get(struct bnxt_ulp_context *ulp_ctx) { if (!ulp_ctx || !ulp_ctx->cfg_data) return 0; @@ -520,7 +168,7 @@ bnxt_ulp_ecpri_udp_port_get(struct bnxt_ulp_context *ulp_ctx) /* Function to set the number for vxlan_ip (custom vxlan) port into the context */ int -bnxt_ulp_vxlan_ip_port_set(struct bnxt_ulp_context *ulp_ctx, +bnxt_ulp_cntxt_vxlan_ip_port_set(struct bnxt_ulp_context *ulp_ctx, uint32_t vxlan_ip_port) { if (!ulp_ctx || !ulp_ctx->cfg_data) @@ -533,7 +181,7 @@ bnxt_ulp_vxlan_ip_port_set(struct bnxt_ulp_context *ulp_ctx, /* Function to retrieve the vxlan_ip (custom vxlan) port from the context. */ unsigned int -bnxt_ulp_vxlan_ip_port_get(struct bnxt_ulp_context *ulp_ctx) +bnxt_ulp_cntxt_vxlan_ip_port_get(struct bnxt_ulp_context *ulp_ctx) { if (!ulp_ctx || !ulp_ctx->cfg_data) return 0; @@ -566,7 +214,7 @@ bnxt_ulp_vxlan_gpe_next_proto_get(struct bnxt_ulp_context *ulp_ctx) /* Function to set the number for vxlan port into the context */ int -bnxt_ulp_vxlan_port_set(struct bnxt_ulp_context *ulp_ctx, +bnxt_ulp_cntxt_vxlan_port_set(struct bnxt_ulp_context *ulp_ctx, uint32_t vxlan_port) { if (!ulp_ctx || !ulp_ctx->cfg_data) @@ -579,7 +227,7 @@ bnxt_ulp_vxlan_port_set(struct bnxt_ulp_context *ulp_ctx, /* Function to retrieve the vxlan port from the context. */ unsigned int -bnxt_ulp_vxlan_port_get(struct bnxt_ulp_context *ulp_ctx) +bnxt_ulp_cntxt_vxlan_port_get(struct bnxt_ulp_context *ulp_ctx) { if (!ulp_ctx || !ulp_ctx->cfg_data) return 0; @@ -597,99 +245,23 @@ bnxt_ulp_default_app_priority_get(struct bnxt_ulp_context *ulp_ctx) return (unsigned int)ulp_ctx->cfg_data->default_priority; } -static inline uint32_t -bnxt_ulp_session_idx_get(enum bnxt_ulp_session_type session_type) { - if (session_type & BNXT_ULP_SESSION_TYPE_SHARED) - return 1; - else if (session_type & BNXT_ULP_SESSION_TYPE_SHARED_WC) - return 2; - return 0; -} - -/* Function to set the tfp session details in session */ +/* The function to initialize bp flags with truflow features */ static int32_t -bnxt_ulp_session_tfp_set(struct bnxt_ulp_session_state *session, - enum bnxt_ulp_session_type session_type, - struct tf *tfp) -{ - uint32_t idx = bnxt_ulp_session_idx_get(session_type); - int32_t rc = 0; - - if (!session->session_opened[idx]) { - session->g_tfp[idx] = rte_zmalloc("bnxt_ulp_session_tfp", - sizeof(struct tf), 0); - if (!session->g_tfp[idx]) { - BNXT_TF_DBG(DEBUG, "Failed to alloc session tfp\n"); - return -ENOMEM; - } - session->g_tfp[idx]->session = tfp->session; - session->session_opened[idx] = 1; - } - return rc; -} - -/* Function to get the tfp session details in session */ -static struct tf_session_info * -bnxt_ulp_session_tfp_get(struct bnxt_ulp_session_state *session, - enum bnxt_ulp_session_type session_type) -{ - uint32_t idx = bnxt_ulp_session_idx_get(session_type); - - if (session->session_opened[idx]) - return session->g_tfp[idx]->session; - return NULL; -} - -static uint32_t -bnxt_ulp_session_is_open(struct bnxt_ulp_session_state *session, - enum bnxt_ulp_session_type session_type) -{ - uint32_t idx = bnxt_ulp_session_idx_get(session_type); - - return session->session_opened[idx]; -} - -/* Function to reset the tfp session details in session */ -static void -bnxt_ulp_session_tfp_reset(struct bnxt_ulp_session_state *session, - enum bnxt_ulp_session_type session_type) +ulp_dparms_dev_port_intf_update(struct bnxt *bp, + struct bnxt_ulp_context *ulp_ctx) { - uint32_t idx = bnxt_ulp_session_idx_get(session_type); - - if (session->session_opened[idx]) { - session->session_opened[idx] = 0; - rte_free(session->g_tfp[idx]); - session->g_tfp[idx] = NULL; - } -} + enum bnxt_ulp_flow_mem_type mtype; -static void -ulp_ctx_shared_session_close(struct bnxt *bp, - enum bnxt_ulp_session_type session_type, - struct bnxt_ulp_session_state *session) -{ - struct tf *tfp; - int32_t rc; + if (bnxt_ulp_cntxt_mem_type_get(ulp_ctx, &mtype)) + return -EINVAL; + /* Update the bp flag with gfid flag */ + if (mtype == BNXT_ULP_FLOW_MEM_TYPE_EXT) + bp->flags |= BNXT_FLAG_GFID_ENABLE; - tfp = bnxt_ulp_cntxt_tfp_get(bp->ulp_ctx, session_type); - if (!tfp) { - /* - * Log it under debug since this is likely a case of the - * shared session not being created. For example, a failed - * initialization. - */ - BNXT_TF_DBG(DEBUG, "Failed to get shared tfp on close.\n"); - return; - } - rc = tf_close_session(tfp); - if (rc) - BNXT_TF_DBG(ERR, "Failed to close the shared session rc=%d.\n", - rc); - (void)bnxt_ulp_cntxt_tfp_set(bp->ulp_ctx, session_type, NULL); - bnxt_ulp_session_tfp_reset(session, session_type); + return 0; } -static int32_t +int32_t ulp_ctx_mh_get_session_name(struct bnxt *bp, struct tf_open_session_parms *parms) { @@ -713,7 +285,7 @@ ulp_ctx_mh_get_session_name(struct bnxt *bp, &slot, &device); if (rc != 3) { - BNXT_TF_DBG(DEBUG, + BNXT_DRV_DBG(DEBUG, "Failed to scan device ctrl_chan_name\n"); return -EINVAL; } @@ -727,752 +299,68 @@ ulp_ctx_mh_get_session_name(struct bnxt *bp, bus, slot, device); - BNXT_TF_DBG(DEBUG, + BNXT_DRV_DBG(DEBUG, "Session name for Multi-Host: ctrl_chan_name:%s\n", parms->ctrl_chan_name); return 0; } -static int32_t -ulp_ctx_shared_session_open(struct bnxt *bp, - enum bnxt_ulp_session_type session_type, - struct bnxt_ulp_session_state *session) -{ - struct rte_eth_dev *ethdev = bp->eth_dev; - struct tf_session_resources *resources; - struct tf_open_session_parms parms; - size_t nb; - uint32_t ulp_dev_id = BNXT_ULP_DEVICE_ID_LAST; - int32_t rc = 0; - uint8_t app_id; - struct tf *tfp; - uint8_t pool_id; - - memset(&parms, 0, sizeof(parms)); - rc = rte_eth_dev_get_name_by_port(ethdev->data->port_id, - parms.ctrl_chan_name); - if (rc) { - BNXT_TF_DBG(ERR, "Invalid port %d, rc = %d\n", - ethdev->data->port_id, rc); - return rc; - } +/* + * Initialize the state of an ULP session. + * If the state of an ULP session is not initialized, set it's state to + * initialized. If the state is already initialized, do nothing. + */ +static void +ulp_context_initialized(struct bnxt_ulp_session_state *session, bool *init) +{ + pthread_mutex_lock(&session->bnxt_ulp_mutex); - /* On multi-host system, adjust ctrl_chan_name to avoid confliction */ - if (BNXT_MH(bp)) { - rc = ulp_ctx_mh_get_session_name(bp, &parms); - if (rc) - return rc; + if (!session->bnxt_ulp_init) { + session->bnxt_ulp_init = true; + *init = false; + } else { + *init = true; } - resources = &parms.resources; + pthread_mutex_unlock(&session->bnxt_ulp_mutex); +} - /* - * Need to account for size of ctrl_chan_name and 1 extra for Null - * terminator - */ - nb = sizeof(parms.ctrl_chan_name) - strlen(parms.ctrl_chan_name) - 1; +/* + * Check if an ULP session is already allocated for a specific PCI + * domain & bus. If it is already allocated simply return the session + * pointer, otherwise allocate a new session. + */ +static struct bnxt_ulp_session_state * +ulp_get_session(struct bnxt *bp, struct rte_pci_addr *pci_addr) +{ + struct bnxt_ulp_session_state *session; - /* - * Build the ctrl_chan_name with shared token. - * When HA is enabled, the WC TCAM needs extra management by the core, - * so add the wc_tcam string to the control channel. - */ - pool_id = bp->ulp_ctx->cfg_data->ha_pool_id; - if (!bnxt_ulp_cntxt_multi_shared_session_enabled(bp->ulp_ctx)) { - if (bnxt_ulp_cntxt_ha_enabled(bp->ulp_ctx)) - strncat(parms.ctrl_chan_name, "-tf_shared-wc_tcam", nb); - else - strncat(parms.ctrl_chan_name, "-tf_shared", nb); - } else if (bnxt_ulp_cntxt_multi_shared_session_enabled(bp->ulp_ctx)) { - if (session_type == BNXT_ULP_SESSION_TYPE_SHARED) { - strncat(parms.ctrl_chan_name, "-tf_shared", nb); - } else if (session_type == BNXT_ULP_SESSION_TYPE_SHARED_WC) { - char session_pool_name[64]; - - sprintf(session_pool_name, "-tf_shared-pool%d", - pool_id); - - if (nb >= strlen(session_pool_name)) { - strncat(parms.ctrl_chan_name, session_pool_name, nb); - } else { - BNXT_TF_DBG(ERR, "No space left for session_name\n"); - return -EINVAL; + /* if multi root capability is enabled, then ignore the pci bus id */ + STAILQ_FOREACH(session, &bnxt_ulp_session_list, next) { + if (BNXT_MULTIROOT_EN(bp)) { + if (!memcmp(bp->dsn, session->dsn, + sizeof(session->dsn))) { + return session; } + } else if (session->pci_info.domain == pci_addr->domain && + session->pci_info.bus == pci_addr->bus) { + return session; } } + return NULL; +} - rc = bnxt_ulp_tf_shared_session_resources_get(bp->ulp_ctx, session_type, - resources); - if (rc) - return rc; - - rc = bnxt_ulp_cntxt_app_id_get(bp->ulp_ctx, &app_id); - if (rc) { - BNXT_TF_DBG(ERR, "Unable to get the app id from ulp.\n"); - return -EINVAL; - } - - rc = bnxt_ulp_cntxt_dev_id_get(bp->ulp_ctx, &ulp_dev_id); - if (rc) { - BNXT_TF_DBG(ERR, "Unable to get device id from ulp.\n"); - return rc; - } - - tfp = bnxt_ulp_bp_tfp_get(bp, session_type); - parms.device_type = bnxt_ulp_cntxt_convert_dev_id(ulp_dev_id); - parms.bp = bp; - - /* - * Open the session here, but the collect the resources during the - * mapper initialization. - */ - rc = tf_open_session(tfp, &parms); - if (rc) - return rc; - - if (parms.shared_session_creator) - BNXT_TF_DBG(DEBUG, "Shared session creator.\n"); - else - BNXT_TF_DBG(DEBUG, "Shared session attached.\n"); - - /* Save the shared session in global data */ - rc = bnxt_ulp_session_tfp_set(session, session_type, tfp); - if (rc) { - BNXT_TF_DBG(ERR, "Failed to add shared tfp to session\n"); - return rc; - } - - rc = bnxt_ulp_cntxt_tfp_set(bp->ulp_ctx, session_type, tfp); - if (rc) { - BNXT_TF_DBG(ERR, "Failed to add shared tfp to ulp (%d)\n", rc); - return rc; - } - - return rc; -} - -static int32_t -ulp_ctx_shared_session_attach(struct bnxt *bp, - struct bnxt_ulp_session_state *ses) -{ - enum bnxt_ulp_session_type type; - struct tf *tfp; - int32_t rc = 0; - - /* Simply return success if shared session not enabled */ - if (bnxt_ulp_cntxt_shared_session_enabled(bp->ulp_ctx)) { - type = BNXT_ULP_SESSION_TYPE_SHARED; - tfp = bnxt_ulp_bp_tfp_get(bp, type); - tfp->session = bnxt_ulp_session_tfp_get(ses, type); - rc = ulp_ctx_shared_session_open(bp, type, ses); - } - - if (bnxt_ulp_cntxt_multi_shared_session_enabled(bp->ulp_ctx)) { - type = BNXT_ULP_SESSION_TYPE_SHARED_WC; - tfp = bnxt_ulp_bp_tfp_get(bp, type); - tfp->session = bnxt_ulp_session_tfp_get(ses, type); - rc = ulp_ctx_shared_session_open(bp, type, ses); - } - - if (!rc) - bnxt_ulp_cntxt_num_shared_clients_set(bp->ulp_ctx, true); - - return rc; -} - -static void -ulp_ctx_shared_session_detach(struct bnxt *bp) -{ - struct tf *tfp; - - if (bnxt_ulp_cntxt_shared_session_enabled(bp->ulp_ctx)) { - tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_SHARED); - if (tfp->session) { - tf_close_session(tfp); - tfp->session = NULL; - } - } - if (bnxt_ulp_cntxt_multi_shared_session_enabled(bp->ulp_ctx)) { - tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_SHARED_WC); - if (tfp->session) { - tf_close_session(tfp); - tfp->session = NULL; - } - } - bnxt_ulp_cntxt_num_shared_clients_set(bp->ulp_ctx, false); -} - -/* - * Initialize an ULP session. - * An ULP session will contain all the resources needed to support rte flow - * offloads. A session is initialized as part of rte_eth_device start. - * A single vswitch instance can have multiple uplinks which means - * rte_eth_device start will be called for each of these devices. - * ULP session manager will make sure that a single ULP session is only - * initialized once. Apart from this, it also initializes MARK database, - * EEM table & flow database. ULP session manager also manages a list of - * all opened ULP sessions. - */ -static int32_t -ulp_ctx_session_open(struct bnxt *bp, - struct bnxt_ulp_session_state *session) -{ - struct rte_eth_dev *ethdev = bp->eth_dev; - int32_t rc = 0; - struct tf_open_session_parms params; - struct tf_session_resources *resources; - uint32_t ulp_dev_id = BNXT_ULP_DEVICE_ID_LAST; - uint8_t app_id; - struct tf *tfp; - - memset(¶ms, 0, sizeof(params)); - - rc = rte_eth_dev_get_name_by_port(ethdev->data->port_id, - params.ctrl_chan_name); - if (rc) { - BNXT_TF_DBG(ERR, "Invalid port %d, rc = %d\n", - ethdev->data->port_id, rc); - return rc; - } - - /* On multi-host system, adjust ctrl_chan_name to avoid confliction */ - if (BNXT_MH(bp)) { - rc = ulp_ctx_mh_get_session_name(bp, ¶ms); - if (rc) - return rc; - } - - rc = bnxt_ulp_cntxt_app_id_get(bp->ulp_ctx, &app_id); - if (rc) { - BNXT_TF_DBG(ERR, "Unable to get the app id from ulp.\n"); - return -EINVAL; - } - - rc = bnxt_ulp_cntxt_dev_id_get(bp->ulp_ctx, &ulp_dev_id); - if (rc) { - BNXT_TF_DBG(ERR, "Unable to get device id from ulp.\n"); - return rc; - } - - params.device_type = bnxt_ulp_cntxt_convert_dev_id(ulp_dev_id); - resources = ¶ms.resources; - rc = bnxt_ulp_tf_resources_get(bp->ulp_ctx, - BNXT_ULP_SESSION_TYPE_DEFAULT, - resources); - if (rc) - return rc; - - params.bp = bp; - - tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_DEFAULT); - rc = tf_open_session(tfp, ¶ms); - if (rc) { - BNXT_TF_DBG(ERR, "Failed to open TF session - %s, rc = %d\n", - params.ctrl_chan_name, rc); - return -EINVAL; - } - rc = bnxt_ulp_session_tfp_set(session, - BNXT_ULP_SESSION_TYPE_DEFAULT, tfp); - if (rc) { - BNXT_TF_DBG(ERR, "Failed to set TF session - %s, rc = %d\n", - params.ctrl_chan_name, rc); - return -EINVAL; - } - return rc; -} - -/* - * Close the ULP session. - * It takes the ulp context pointer. - */ -static void -ulp_ctx_session_close(struct bnxt *bp, - struct bnxt_ulp_session_state *session) -{ - struct tf *tfp; - - /* close the session in the hardware */ - if (bnxt_ulp_session_is_open(session, BNXT_ULP_SESSION_TYPE_DEFAULT)) { - tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_DEFAULT); - tf_close_session(tfp); - } - bnxt_ulp_session_tfp_reset(session, BNXT_ULP_SESSION_TYPE_DEFAULT); -} - -static void -bnxt_init_tbl_scope_parms(struct bnxt *bp, - struct tf_alloc_tbl_scope_parms *params) -{ - struct bnxt_ulp_device_params *dparms; - uint32_t dev_id; - int rc; - - rc = bnxt_ulp_cntxt_dev_id_get(bp->ulp_ctx, &dev_id); - if (rc) - /* TBD: For now, just use default. */ - dparms = 0; - else - dparms = bnxt_ulp_device_params_get(dev_id); - - /* - * Set the flush timer for EEM entries. The value is in 100ms intervals, - * so 100 is 10s. - */ - params->hw_flow_cache_flush_timer = 100; - - if (!dparms) { - params->rx_max_key_sz_in_bits = BNXT_ULP_DFLT_RX_MAX_KEY; - params->rx_max_action_entry_sz_in_bits = - BNXT_ULP_DFLT_RX_MAX_ACTN_ENTRY; - params->rx_mem_size_in_mb = BNXT_ULP_DFLT_RX_MEM; - params->rx_num_flows_in_k = BNXT_ULP_RX_NUM_FLOWS; - - params->tx_max_key_sz_in_bits = BNXT_ULP_DFLT_TX_MAX_KEY; - params->tx_max_action_entry_sz_in_bits = - BNXT_ULP_DFLT_TX_MAX_ACTN_ENTRY; - params->tx_mem_size_in_mb = BNXT_ULP_DFLT_TX_MEM; - params->tx_num_flows_in_k = BNXT_ULP_TX_NUM_FLOWS; - } else { - params->rx_max_key_sz_in_bits = BNXT_ULP_DFLT_RX_MAX_KEY; - params->rx_max_action_entry_sz_in_bits = - BNXT_ULP_DFLT_RX_MAX_ACTN_ENTRY; - params->rx_mem_size_in_mb = BNXT_ULP_DFLT_RX_MEM; - params->rx_num_flows_in_k = - dparms->ext_flow_db_num_entries / 1024; - - params->tx_max_key_sz_in_bits = BNXT_ULP_DFLT_TX_MAX_KEY; - params->tx_max_action_entry_sz_in_bits = - BNXT_ULP_DFLT_TX_MAX_ACTN_ENTRY; - params->tx_mem_size_in_mb = BNXT_ULP_DFLT_TX_MEM; - params->tx_num_flows_in_k = - dparms->ext_flow_db_num_entries / 1024; - } - BNXT_TF_DBG(INFO, "Table Scope initialized with %uK flows.\n", - params->rx_num_flows_in_k); -} - -/* Initialize Extended Exact Match host memory. */ -static int32_t -ulp_eem_tbl_scope_init(struct bnxt *bp) -{ - struct tf_alloc_tbl_scope_parms params = {0}; - struct bnxt_ulp_device_params *dparms; - enum bnxt_ulp_flow_mem_type mtype; - uint32_t dev_id; - struct tf *tfp; - int rc; - - /* Get the dev specific number of flows that needed to be supported. */ - if (bnxt_ulp_cntxt_dev_id_get(bp->ulp_ctx, &dev_id)) { - BNXT_TF_DBG(ERR, "Invalid device id\n"); - return -EINVAL; - } - - dparms = bnxt_ulp_device_params_get(dev_id); - if (!dparms) { - BNXT_TF_DBG(ERR, "could not fetch the device params\n"); - return -ENODEV; - } - - if (bnxt_ulp_cntxt_mem_type_get(bp->ulp_ctx, &mtype)) - return -EINVAL; - if (mtype != BNXT_ULP_FLOW_MEM_TYPE_EXT) { - BNXT_TF_DBG(INFO, "Table Scope alloc is not required\n"); - return 0; - } - - bnxt_init_tbl_scope_parms(bp, ¶ms); - tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_DEFAULT); - rc = tf_alloc_tbl_scope(tfp, ¶ms); - if (rc) { - BNXT_TF_DBG(ERR, "Unable to allocate eem table scope rc = %d\n", - rc); - return rc; - } - - rc = bnxt_ulp_cntxt_tbl_scope_id_set(bp->ulp_ctx, params.tbl_scope_id); - if (rc) { - BNXT_TF_DBG(ERR, "Unable to set table scope id\n"); - return rc; - } - - return 0; -} - -/* Free Extended Exact Match host memory */ -static int32_t -ulp_eem_tbl_scope_deinit(struct bnxt *bp, struct bnxt_ulp_context *ulp_ctx) -{ - struct tf_free_tbl_scope_parms params = {0}; - struct tf *tfp; - int32_t rc = 0; - struct bnxt_ulp_device_params *dparms; - enum bnxt_ulp_flow_mem_type mtype; - uint32_t dev_id; - - if (!ulp_ctx || !ulp_ctx->cfg_data) - return -EINVAL; - - tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx, BNXT_ULP_SESSION_TYPE_DEFAULT); - if (!tfp) { - BNXT_TF_DBG(ERR, "Failed to get the truflow pointer\n"); - return -EINVAL; - } - - /* Get the dev specific number of flows that needed to be supported. */ - if (bnxt_ulp_cntxt_dev_id_get(bp->ulp_ctx, &dev_id)) { - BNXT_TF_DBG(ERR, "Invalid device id\n"); - return -EINVAL; - } - - dparms = bnxt_ulp_device_params_get(dev_id); - if (!dparms) { - BNXT_TF_DBG(ERR, "could not fetch the device params\n"); - return -ENODEV; - } - - if (bnxt_ulp_cntxt_mem_type_get(ulp_ctx, &mtype)) - return -EINVAL; - if (mtype != BNXT_ULP_FLOW_MEM_TYPE_EXT) { - BNXT_TF_DBG(INFO, "Table Scope free is not required\n"); - return 0; - } - - rc = bnxt_ulp_cntxt_tbl_scope_id_get(ulp_ctx, ¶ms.tbl_scope_id); - if (rc) { - BNXT_TF_DBG(ERR, "Failed to get the table scope id\n"); - return -EINVAL; - } - - rc = tf_free_tbl_scope(tfp, ¶ms); - if (rc) { - BNXT_TF_DBG(ERR, "Unable to free table scope\n"); - return -EINVAL; - } - return rc; -} - -/* The function to free and deinit the ulp context data. */ -static int32_t -ulp_ctx_deinit(struct bnxt *bp, - struct bnxt_ulp_session_state *session) -{ - /* close the tf session */ - ulp_ctx_session_close(bp, session); - - /* The shared session must be closed last. */ - if (bnxt_ulp_cntxt_shared_session_enabled(bp->ulp_ctx)) - ulp_ctx_shared_session_close(bp, BNXT_ULP_SESSION_TYPE_SHARED, - session); - - if (bnxt_ulp_cntxt_multi_shared_session_enabled(bp->ulp_ctx)) - ulp_ctx_shared_session_close(bp, - BNXT_ULP_SESSION_TYPE_SHARED_WC, - session); - - bnxt_ulp_cntxt_num_shared_clients_set(bp->ulp_ctx, false); - - /* Free the contents */ - if (session->cfg_data) { - rte_free(session->cfg_data); - bp->ulp_ctx->cfg_data = NULL; - session->cfg_data = NULL; - } - return 0; -} - -/* The function to allocate and initialize the ulp context data. */ -static int32_t -ulp_ctx_init(struct bnxt *bp, - struct bnxt_ulp_session_state *session) -{ - struct bnxt_ulp_data *ulp_data; - int32_t rc = 0; - enum bnxt_ulp_device_id devid; - enum bnxt_ulp_session_type stype; - struct tf *tfp; - - /* Initialize the context entries list */ - bnxt_ulp_cntxt_list_init(); - - /* Add the context to the context entries list */ - rc = bnxt_ulp_cntxt_list_add(bp->ulp_ctx); - if (rc) { - BNXT_TF_DBG(ERR, "Failed to add the context list entry\n"); - return -ENOMEM; - } - - /* Allocate memory to hold ulp context data. */ - ulp_data = rte_zmalloc("bnxt_ulp_data", - sizeof(struct bnxt_ulp_data), 0); - if (!ulp_data) { - BNXT_TF_DBG(ERR, "Failed to allocate memory for ulp data\n"); - return -ENOMEM; - } - - /* Increment the ulp context data reference count usage. */ - bp->ulp_ctx->cfg_data = ulp_data; - session->cfg_data = ulp_data; - ulp_data->ref_cnt++; - ulp_data->ulp_flags |= BNXT_ULP_VF_REP_ENABLED; - - rc = bnxt_ulp_devid_get(bp, &devid); - if (rc) { - BNXT_TF_DBG(ERR, "Unable to determine device for ULP init.\n"); - goto error_deinit; - } - - rc = bnxt_ulp_cntxt_dev_id_set(bp->ulp_ctx, devid); - if (rc) { - BNXT_TF_DBG(ERR, "Unable to set device for ULP init.\n"); - goto error_deinit; - } - - rc = bnxt_ulp_cntxt_app_id_set(bp->ulp_ctx, bp->app_id); - if (rc) { - BNXT_TF_DBG(ERR, "Unable to set app_id for ULP init.\n"); - goto error_deinit; - } - BNXT_TF_DBG(DEBUG, "Ulp initialized with app id %d\n", bp->app_id); - - rc = bnxt_ulp_cntxt_app_caps_init(bp, bp->app_id, devid); - if (rc) { - BNXT_TF_DBG(ERR, "Unable to set caps for app(%x)/dev(%x)\n", - bp->app_id, devid); - goto error_deinit; - } - - if (BNXT_TESTPMD_EN(bp)) { - ulp_data->ulp_flags &= ~BNXT_ULP_VF_REP_ENABLED; - BNXT_TF_DBG(ERR, "Enabled Testpmd forward mode\n"); - } - - /* - * Shared session must be created before first regular session but after - * the ulp_ctx is valid. - */ - if (bnxt_ulp_cntxt_shared_session_enabled(bp->ulp_ctx)) { - rc = ulp_ctx_shared_session_open(bp, - BNXT_ULP_SESSION_TYPE_SHARED, - session); - if (rc) { - BNXT_TF_DBG(ERR, "Unable to open shared session (%d)\n", - rc); - goto error_deinit; - } - } - - /* Multiple session support */ - if (bnxt_ulp_cntxt_multi_shared_session_enabled(bp->ulp_ctx)) { - stype = BNXT_ULP_SESSION_TYPE_SHARED_WC; - rc = ulp_ctx_shared_session_open(bp, stype, session); - if (rc) { - BNXT_TF_DBG(ERR, - "Unable to open shared wc session (%d)\n", - rc); - goto error_deinit; - } - } - bnxt_ulp_cntxt_num_shared_clients_set(bp->ulp_ctx, true); - - /* Open the ulp session. */ - rc = ulp_ctx_session_open(bp, session); - if (rc) - goto error_deinit; - - tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_DEFAULT); - bnxt_ulp_cntxt_tfp_set(bp->ulp_ctx, BNXT_ULP_SESSION_TYPE_DEFAULT, tfp); - return rc; - -error_deinit: - session->session_opened[BNXT_ULP_SESSION_TYPE_DEFAULT] = 1; - (void)ulp_ctx_deinit(bp, session); - return rc; -} - -/* The function to initialize ulp dparms with devargs */ -static int32_t -ulp_dparms_init(struct bnxt *bp, struct bnxt_ulp_context *ulp_ctx) -{ - struct bnxt_ulp_device_params *dparms; - uint32_t dev_id = BNXT_ULP_DEVICE_ID_LAST; - - if (!bp->max_num_kflows) { - /* Defaults to Internal */ - bnxt_ulp_cntxt_mem_type_set(ulp_ctx, - BNXT_ULP_FLOW_MEM_TYPE_INT); - return 0; - } - - /* The max_num_kflows were set, so move to external */ - if (bnxt_ulp_cntxt_mem_type_set(ulp_ctx, BNXT_ULP_FLOW_MEM_TYPE_EXT)) - return -EINVAL; - - if (bnxt_ulp_cntxt_dev_id_get(ulp_ctx, &dev_id)) { - BNXT_TF_DBG(DEBUG, "Failed to get device id\n"); - return -EINVAL; - } - - dparms = bnxt_ulp_device_params_get(dev_id); - if (!dparms) { - BNXT_TF_DBG(DEBUG, "Failed to get device parms\n"); - return -EINVAL; - } - - /* num_flows = max_num_kflows * 1024 */ - dparms->ext_flow_db_num_entries = bp->max_num_kflows * 1024; - /* GFID = 2 * num_flows */ - dparms->mark_db_gfid_entries = dparms->ext_flow_db_num_entries * 2; - BNXT_TF_DBG(DEBUG, "Set the number of flows = %" PRIu64 "\n", - dparms->ext_flow_db_num_entries); - - return 0; -} - -/* The function to initialize bp flags with truflow features */ -static int32_t -ulp_dparms_dev_port_intf_update(struct bnxt *bp, - struct bnxt_ulp_context *ulp_ctx) -{ - enum bnxt_ulp_flow_mem_type mtype; - - if (bnxt_ulp_cntxt_mem_type_get(ulp_ctx, &mtype)) - return -EINVAL; - /* Update the bp flag with gfid flag */ - if (mtype == BNXT_ULP_FLOW_MEM_TYPE_EXT) - bp->flags |= BNXT_FLAG_GFID_ENABLE; - - return 0; -} - -static int32_t -ulp_ctx_attach(struct bnxt *bp, - struct bnxt_ulp_session_state *session) -{ - int32_t rc = 0; - uint32_t flags, dev_id = BNXT_ULP_DEVICE_ID_LAST; - struct tf *tfp; - uint8_t app_id; - - /* Increment the ulp context data reference count usage. */ - bp->ulp_ctx->cfg_data = session->cfg_data; - bp->ulp_ctx->cfg_data->ref_cnt++; - - /* update the session details in bnxt tfp */ - tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_DEFAULT); - tfp->session = bnxt_ulp_session_tfp_get(session, - BNXT_ULP_SESSION_TYPE_DEFAULT); - - /* Add the context to the context entries list */ - rc = bnxt_ulp_cntxt_list_add(bp->ulp_ctx); - if (rc) { - BNXT_TF_DBG(ERR, "Failed to add the context list entry\n"); - return -EINVAL; - } - - /* - * The supported flag will be set during the init. Use it now to - * know if we should go through the attach. - */ - rc = bnxt_ulp_cntxt_app_id_get(bp->ulp_ctx, &app_id); - if (rc) { - BNXT_TF_DBG(ERR, "Unable to get the app id from ulp.\n"); - return -EINVAL; - } - - rc = bnxt_ulp_cntxt_dev_id_get(bp->ulp_ctx, &dev_id); - if (rc) { - BNXT_TF_DBG(ERR, "Unable do get the dev_id.\n"); - return -EINVAL; - } - - flags = bp->ulp_ctx->cfg_data->ulp_flags; - if (ULP_APP_DEV_UNSUPPORTED_ENABLED(flags)) { - BNXT_TF_DBG(ERR, "APP ID %d, Device ID: 0x%x not supported.\n", - app_id, dev_id); - return -EINVAL; - } - - /* Create a TF Client */ - rc = ulp_ctx_session_open(bp, session); - if (rc) { - PMD_DRV_LOG(ERR, "Failed to open ctxt session, rc:%d\n", rc); - tfp->session = NULL; - return rc; - } - tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_DEFAULT); - bnxt_ulp_cntxt_tfp_set(bp->ulp_ctx, BNXT_ULP_SESSION_TYPE_DEFAULT, tfp); - return rc; -} - -static void -ulp_ctx_detach(struct bnxt *bp) -{ - struct tf *tfp; - - tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_DEFAULT); - if (tfp->session) { - tf_close_session(tfp); - tfp->session = NULL; - } -} - -/* - * Initialize the state of an ULP session. - * If the state of an ULP session is not initialized, set it's state to - * initialized. If the state is already initialized, do nothing. - */ -static void -ulp_context_initialized(struct bnxt_ulp_session_state *session, bool *init) -{ - pthread_mutex_lock(&session->bnxt_ulp_mutex); - - if (!session->bnxt_ulp_init) { - session->bnxt_ulp_init = true; - *init = false; - } else { - *init = true; - } - - pthread_mutex_unlock(&session->bnxt_ulp_mutex); -} - -/* - * Check if an ULP session is already allocated for a specific PCI - * domain & bus. If it is already allocated simply return the session - * pointer, otherwise allocate a new session. - */ -static struct bnxt_ulp_session_state * -ulp_get_session(struct bnxt *bp, struct rte_pci_addr *pci_addr) -{ - struct bnxt_ulp_session_state *session; - - /* if multi root capability is enabled, then ignore the pci bus id */ - STAILQ_FOREACH(session, &bnxt_ulp_session_list, next) { - if (BNXT_MULTIROOT_EN(bp)) { - if (!memcmp(bp->dsn, session->dsn, - sizeof(session->dsn))) { - return session; - } - } else if (session->pci_info.domain == pci_addr->domain && - session->pci_info.bus == pci_addr->bus) { - return session; - } - } - return NULL; -} - -/* - * Allocate and Initialize an ULP session and set it's state to INITIALIZED. - * If it's already initialized simply return the already existing session. - */ -static struct bnxt_ulp_session_state * -ulp_session_init(struct bnxt *bp, - bool *init) -{ - struct rte_pci_device *pci_dev; - struct rte_pci_addr *pci_addr; - struct bnxt_ulp_session_state *session; - int rc = 0; +/* + * Allocate and Initialize an ULP session and set it's state to INITIALIZED. + * If it's already initialized simply return the already existing session. + */ +static struct bnxt_ulp_session_state * +ulp_session_init(struct bnxt *bp, + bool *init) +{ + struct rte_pci_device *pci_dev; + struct rte_pci_addr *pci_addr; + struct bnxt_ulp_session_state *session; + int rc = 0; if (!bp) return NULL; @@ -1489,7 +377,7 @@ ulp_session_init(struct bnxt *bp, sizeof(struct bnxt_ulp_session_state), 0); if (!session) { - BNXT_TF_DBG(ERR, + BNXT_DRV_DBG(ERR, "Allocation failed for bnxt_ulp_session\n"); pthread_mutex_unlock(&bnxt_ulp_global_mutex); return NULL; @@ -1501,7 +389,7 @@ ulp_session_init(struct bnxt *bp, memcpy(session->dsn, bp->dsn, sizeof(session->dsn)); rc = pthread_mutex_init(&session->bnxt_ulp_mutex, NULL); if (rc) { - BNXT_TF_DBG(ERR, "mutex create failed\n"); + BNXT_DRV_DBG(ERR, "mutex create failed\n"); pthread_mutex_unlock(&bnxt_ulp_global_mutex); return NULL; } @@ -1534,326 +422,80 @@ ulp_session_deinit(struct bnxt_ulp_session_state *session) } } -/* - * Internal api to enable NAT feature. - * Set set_flag to 1 to set the value or zero to reset the value. - * returns 0 on success. - */ -static int32_t -bnxt_ulp_global_cfg_update(struct bnxt *bp, - enum tf_dir dir, - enum tf_global_config_type type, - uint32_t offset, - uint32_t value, - uint32_t set_flag) -{ - uint32_t global_cfg = 0; - int rc; - struct tf_global_cfg_parms parms = { 0 }; - struct tf *tfp; - - /* Initialize the params */ - parms.dir = dir, - parms.type = type, - parms.offset = offset, - parms.config = (uint8_t *)&global_cfg, - parms.config_sz_in_bytes = sizeof(global_cfg); - - tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_DEFAULT); - rc = tf_get_global_cfg(tfp, &parms); - if (rc) { - BNXT_TF_DBG(ERR, "Failed to get global cfg 0x%x rc:%d\n", - type, rc); - return rc; - } - - if (set_flag) - global_cfg |= value; - else - global_cfg &= ~value; - - /* SET the register RE_CFA_REG_ACT_TECT */ - rc = tf_set_global_cfg(tfp, &parms); - if (rc) { - BNXT_TF_DBG(ERR, "Failed to set global cfg 0x%x rc:%d\n", - type, rc); - return rc; - } - return rc; -} - /* Internal function to delete all the flows belonging to the given port */ static void bnxt_ulp_flush_port_flows(struct bnxt *bp) { uint16_t func_id; - /* it is assumed that port is either TVF or PF */ - if (ulp_port_db_port_func_id_get(bp->ulp_ctx, - bp->eth_dev->data->port_id, - &func_id)) { - BNXT_TF_DBG(ERR, "Invalid argument\n"); - return; - } - (void)ulp_flow_db_function_flow_flush(bp->ulp_ctx, func_id); -} - -/* Internal function to delete the VFR default flows */ -static void -bnxt_ulp_destroy_vfr_default_rules(struct bnxt *bp, bool global) -{ - struct bnxt_ulp_vfr_rule_info *info; - uint16_t port_id; - struct rte_eth_dev *vfr_eth_dev; - struct bnxt_representor *vfr_bp; - - if (!BNXT_TRUFLOW_EN(bp) || rte_eth_dev_is_repr(bp->eth_dev)) - return; - - if (!bp->ulp_ctx || !bp->ulp_ctx->cfg_data) - return; - - /* Delete default rules for all ports */ - for (port_id = 0; port_id < RTE_MAX_ETHPORTS; port_id++) { - info = &bp->ulp_ctx->cfg_data->vfr_rule_info[port_id]; - if (!info->valid) - continue; - - if (!global && info->parent_port_id != - bp->eth_dev->data->port_id) - continue; - - /* Destroy the flows */ - ulp_default_flow_destroy(bp->eth_dev, info->vfr_flow_id); - /* Clean up the tx action pointer */ - vfr_eth_dev = &rte_eth_devices[port_id]; - if (vfr_eth_dev) { - vfr_bp = vfr_eth_dev->data->dev_private; - vfr_bp->vfr_tx_cfa_action = 0; - } - memset(info, 0, sizeof(struct bnxt_ulp_vfr_rule_info)); - } -} - -static void -ulp_cust_vxlan_free(struct bnxt *bp) -{ - int rc; - - if (ULP_APP_CUST_VXLAN_SUPPORT(bp->ulp_ctx)) { - rc = bnxt_tunnel_dst_port_free(bp, - bp->ulp_ctx->cfg_data->vxlan_port, - HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN); - if (rc) - BNXT_TF_DBG(ERR, "Failed to clear global vxlan port\n"); - } - - if (ULP_APP_CUST_VXLAN_IP_SUPPORT(bp->ulp_ctx)) { - rc = bnxt_tunnel_dst_port_free(bp, - bp->ulp_ctx->cfg_data->vxlan_ip_port, - HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4); - if (rc) - BNXT_TF_DBG(ERR, "Failed to clear global custom vxlan port\n"); - } -} - -/* - * When a port is deinit'ed by dpdk. This function is called - * and this function clears the ULP context and rest of the - * infrastructure associated with it. - */ -static void -bnxt_ulp_deinit(struct bnxt *bp, - struct bnxt_ulp_session_state *session) -{ - bool ha_enabled; - - if (!bp->ulp_ctx || !bp->ulp_ctx->cfg_data) - return; - - ha_enabled = bnxt_ulp_cntxt_ha_enabled(bp->ulp_ctx); - if (ha_enabled && - bnxt_ulp_session_is_open(session, BNXT_ULP_SESSION_TYPE_DEFAULT)) { - int32_t rc = ulp_ha_mgr_close(bp->ulp_ctx); - if (rc) - BNXT_TF_DBG(ERR, "Failed to close HA (%d)\n", rc); - } - - /* Free tunnel configuration */ - ulp_cust_vxlan_free(bp); - - /* clean up default flows */ - bnxt_ulp_destroy_df_rules(bp, true); - - /* clean up default VFR flows */ - bnxt_ulp_destroy_vfr_default_rules(bp, true); - - /* clean up regular flows */ - ulp_flow_db_flush_flows(bp->ulp_ctx, BNXT_ULP_FDB_TYPE_REGULAR); - - /* cleanup the eem table scope */ - ulp_eem_tbl_scope_deinit(bp, bp->ulp_ctx); - - /* cleanup the flow database */ - ulp_flow_db_deinit(bp->ulp_ctx); - - /* Delete the Mark database */ - ulp_mark_db_deinit(bp->ulp_ctx); - - /* cleanup the ulp mapper */ - ulp_mapper_deinit(bp->ulp_ctx); - - /* Delete the Flow Counter Manager */ - ulp_fc_mgr_deinit(bp->ulp_ctx); - - /* Delete the Port database */ - ulp_port_db_deinit(bp->ulp_ctx); - - /* Disable NAT feature */ - (void)bnxt_ulp_global_cfg_update(bp, TF_DIR_RX, TF_TUNNEL_ENCAP, - TF_TUNNEL_ENCAP_NAT, - BNXT_ULP_NAT_OUTER_MOST_FLAGS, 0); - - (void)bnxt_ulp_global_cfg_update(bp, TF_DIR_TX, TF_TUNNEL_ENCAP, - TF_TUNNEL_ENCAP_NAT, - BNXT_ULP_NAT_OUTER_MOST_FLAGS, 0); - - /* free the flow db lock */ - pthread_mutex_destroy(&bp->ulp_ctx->cfg_data->flow_db_lock); - - if (ha_enabled) - ulp_ha_mgr_deinit(bp->ulp_ctx); - - /* Delete the ulp context and tf session and free the ulp context */ - ulp_ctx_deinit(bp, session); - BNXT_TF_DBG(DEBUG, "ulp ctx has been deinitialized\n"); -} - -/* - * When a port is initialized by dpdk. This functions is called - * and this function initializes the ULP context and rest of the - * infrastructure associated with it. - */ -static int32_t -bnxt_ulp_init(struct bnxt *bp, - struct bnxt_ulp_session_state *session) -{ - int rc; - uint32_t ulp_dev_id = BNXT_ULP_DEVICE_ID_LAST; - - /* Allocate and Initialize the ulp context. */ - rc = ulp_ctx_init(bp, session); - if (rc) { - BNXT_TF_DBG(ERR, "Failed to create the ulp context\n"); - goto jump_to_error; - } - - rc = pthread_mutex_init(&bp->ulp_ctx->cfg_data->flow_db_lock, NULL); - if (rc) { - BNXT_TF_DBG(ERR, "Unable to initialize flow db lock\n"); - goto jump_to_error; - } - - /* Initialize ulp dparms with values devargs passed */ - rc = ulp_dparms_init(bp, bp->ulp_ctx); - if (rc) { - BNXT_TF_DBG(ERR, "Failed to initialize the dparms\n"); - goto jump_to_error; - } - - /* create the port database */ - rc = ulp_port_db_init(bp->ulp_ctx, bp->port_cnt); - if (rc) { - BNXT_TF_DBG(ERR, "Failed to create the port database\n"); - goto jump_to_error; - } - - /* Create the Mark database. */ - rc = ulp_mark_db_init(bp->ulp_ctx); - if (rc) { - BNXT_TF_DBG(ERR, "Failed to create the mark database\n"); - goto jump_to_error; - } - - /* Create the flow database. */ - rc = ulp_flow_db_init(bp->ulp_ctx); - if (rc) { - BNXT_TF_DBG(ERR, "Failed to create the flow database\n"); - goto jump_to_error; + /* it is assumed that port is either TVF or PF */ + if (ulp_port_db_port_func_id_get(bp->ulp_ctx, + bp->eth_dev->data->port_id, + &func_id)) { + BNXT_DRV_DBG(ERR, "Invalid argument\n"); + return; } + (void)ulp_flow_db_function_flow_flush(bp->ulp_ctx, func_id); +} - /* Create the eem table scope. */ - rc = ulp_eem_tbl_scope_init(bp); - if (rc) { - BNXT_TF_DBG(ERR, "Failed to create the eem scope table\n"); - goto jump_to_error; - } +/* Internal function to delete the VFR default flows */ +void +bnxt_ulp_destroy_vfr_default_rules(struct bnxt *bp, bool global) +{ + struct bnxt_ulp_vfr_rule_info *info; + uint16_t port_id; + struct rte_eth_dev *vfr_eth_dev; + struct bnxt_representor *vfr_bp; - rc = ulp_mapper_init(bp->ulp_ctx); - if (rc) { - BNXT_TF_DBG(ERR, "Failed to initialize ulp mapper\n"); - goto jump_to_error; - } + if (!BNXT_TRUFLOW_EN(bp) || BNXT_ETH_DEV_IS_REPRESENTOR(bp->eth_dev)) + return; - rc = ulp_fc_mgr_init(bp->ulp_ctx); - if (rc) { - BNXT_TF_DBG(ERR, "Failed to initialize ulp flow counter mgr\n"); - goto jump_to_error; - } + if (!bp->ulp_ctx || !bp->ulp_ctx->cfg_data) + return; - /* - * Enable NAT feature. Set the global configuration register - * Tunnel encap to enable NAT with the reuse of existing inner - * L2 header smac and dmac - */ - rc = bnxt_ulp_global_cfg_update(bp, TF_DIR_RX, TF_TUNNEL_ENCAP, - TF_TUNNEL_ENCAP_NAT, - BNXT_ULP_NAT_OUTER_MOST_FLAGS, 1); - if (rc) { - BNXT_TF_DBG(ERR, "Failed to set rx global configuration\n"); - goto jump_to_error; - } + /* Delete default rules for all ports */ + for (port_id = 0; port_id < RTE_MAX_ETHPORTS; port_id++) { + info = &bp->ulp_ctx->cfg_data->vfr_rule_info[port_id]; + if (!info->valid) + continue; - rc = bnxt_ulp_global_cfg_update(bp, TF_DIR_TX, TF_TUNNEL_ENCAP, - TF_TUNNEL_ENCAP_NAT, - BNXT_ULP_NAT_OUTER_MOST_FLAGS, 1); - if (rc) { - BNXT_TF_DBG(ERR, "Failed to set tx global configuration\n"); - goto jump_to_error; - } + if (!global && info->parent_port_id != + bp->eth_dev->data->port_id) + continue; - if (bnxt_ulp_cntxt_ha_enabled(bp->ulp_ctx)) { - rc = ulp_ha_mgr_init(bp->ulp_ctx); - if (rc) { - BNXT_TF_DBG(ERR, "Failed to initialize HA %d\n", rc); - goto jump_to_error; - } - rc = ulp_ha_mgr_open(bp->ulp_ctx); - if (rc) { - BNXT_TF_DBG(ERR, "Failed to Process HA Open %d\n", rc); - goto jump_to_error; + /* Destroy the flows */ + ulp_default_flow_destroy(bp->eth_dev, info->vfr_flow_id); + /* Clean up the tx action pointer */ + vfr_eth_dev = &rte_eth_devices[port_id]; + if (vfr_eth_dev) { + vfr_bp = vfr_eth_dev->data->dev_private; + vfr_bp->vfr_tx_cfa_action = 0; } + memset(info, 0, sizeof(struct bnxt_ulp_vfr_rule_info)); } +} - rc = bnxt_ulp_cntxt_dev_id_get(bp->ulp_ctx, &ulp_dev_id); - if (rc) { - BNXT_TF_DBG(ERR, "Unable to get device id from ulp.\n"); - return rc; - } +static int +ulp_cust_vxlan_alloc(struct bnxt *bp) +{ + int rc = 0; - if (ulp_dev_id == BNXT_ULP_DEVICE_ID_THOR) { - rc = bnxt_flow_meter_init(bp); - if (rc) { - BNXT_TF_DBG(ERR, "Failed to config meter\n"); - goto jump_to_error; - } + if (ULP_APP_CUST_VXLAN_SUPPORT(bp->ulp_ctx)) { + rc = bnxt_tunnel_dst_port_alloc(bp, + bp->ulp_ctx->cfg_data->vxlan_port, + HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN); + if (rc) + BNXT_DRV_DBG(ERR, "Failed to set global vxlan port\n"); } - BNXT_TF_DBG(DEBUG, "ulp ctx has been initialized\n"); - return rc; + if (ULP_APP_CUST_VXLAN_IP_SUPPORT(bp->ulp_ctx)) { + rc = bnxt_tunnel_dst_port_alloc(bp, + bp->ulp_ctx->cfg_data->vxlan_ip_port, + HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4); + if (rc) + BNXT_DRV_DBG(ERR, "Failed to set global custom vxlan_ip port\n"); + } -jump_to_error: - bnxt_ulp_deinit(bp, session); return rc; } @@ -1866,42 +508,45 @@ ulp_l2_etype_tunnel_alloc(struct bnxt *bp) return rc; if (bp->l2_etype_tunnel_cnt) { - BNXT_TF_DBG(DEBUG, "L2 ETYPE Custom Tunnel already allocated\n"); - return rc; + BNXT_DRV_DBG(DEBUG, "L2 ETYPE Custom Tunnel already allocated\n"); + return 0; } rc = bnxt_tunnel_dst_port_alloc(bp, BNXT_L2_ETYPE_TUNNEL_ID, HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE); if (rc) - BNXT_TF_DBG(ERR, "Failed to set global L2 ETYPE Custom Tunnel\n"); + BNXT_DRV_DBG(ERR, "Failed to set global L2 ETYPE Custom Tunnel\n"); else bp->l2_etype_tunnel_cnt++; return rc; } -static int -ulp_cust_vxlan_alloc(struct bnxt *bp) +static const struct bnxt_ulp_core_ops * +bnxt_ulp_port_func_ops_get(struct bnxt *bp) { - int rc = 0; + int32_t rc; + enum bnxt_ulp_device_id dev_id; + const struct bnxt_ulp_core_ops *func_ops; - if (ULP_APP_CUST_VXLAN_SUPPORT(bp->ulp_ctx)) { - rc = bnxt_tunnel_dst_port_alloc(bp, - bp->ulp_ctx->cfg_data->vxlan_port, - HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN); - if (rc) - BNXT_TF_DBG(ERR, "Failed to set global vxlan port\n"); - } + rc = bnxt_ulp_devid_get(bp, &dev_id); + if (rc) + return NULL; - if (ULP_APP_CUST_VXLAN_IP_SUPPORT(bp->ulp_ctx)) { - rc = bnxt_tunnel_dst_port_alloc(bp, - bp->ulp_ctx->cfg_data->vxlan_ip_port, - HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4); - if (rc) - BNXT_TF_DBG(ERR, "Failed to set global custom vxlan_ip port\n"); + switch (dev_id) { + case BNXT_ULP_DEVICE_ID_THOR2: + func_ops = &bnxt_ulp_tfc_core_ops; + break; + case BNXT_ULP_DEVICE_ID_THOR: + case BNXT_ULP_DEVICE_ID_STINGRAY: + case BNXT_ULP_DEVICE_ID_WH_PLUS: + func_ops = &bnxt_ulp_tf_core_ops; + break; + default: + func_ops = NULL; + break; } - - return rc; + return func_ops; } /* @@ -1913,36 +558,61 @@ bnxt_ulp_port_init(struct bnxt *bp) { struct bnxt_ulp_session_state *session; bool initialized; - enum bnxt_ulp_device_id devid = BNXT_ULP_DEVICE_ID_LAST; uint32_t ulp_flags; int32_t rc = 0; + enum bnxt_ulp_device_id dev_id; if (!BNXT_TRUFLOW_EN(bp)) { - BNXT_TF_DBG(DEBUG, - "Skip ulp init for port: %d, TF is not enabled\n", - bp->eth_dev->data->port_id); + BNXT_DRV_DBG(DEBUG, + "Skip ulp init for port: %d, TF is not enabled\n", + bp->eth_dev->data->port_id); return rc; } if (!BNXT_PF(bp) && !BNXT_VF_IS_TRUSTED(bp)) { - BNXT_TF_DBG(DEBUG, - "Skip ulp init for port: %d, not a TVF or PF\n", - bp->eth_dev->data->port_id); + BNXT_DRV_DBG(DEBUG, + "Skip ulp init for port: %d, not a TVF or PF\n", + bp->eth_dev->data->port_id); + return rc; + } + + rc = bnxt_ulp_devid_get(bp, &dev_id); + if (rc) { + BNXT_DRV_DBG(DEBUG, "Unsupported device %x\n", rc); return rc; } + /* Disable VFR support and support egress temporarily for Thor2 */ + if (dev_id == BNXT_ULP_DEVICE_ID_THOR2) + bp->flags2 |= BNXT_FLAGS2_TESTPMD_EN; + if (bp->ulp_ctx) { - BNXT_TF_DBG(DEBUG, "ulp ctx already allocated\n"); + BNXT_DRV_DBG(DEBUG, "ulp ctx already allocated\n"); return rc; } bp->ulp_ctx = rte_zmalloc("bnxt_ulp_ctx", sizeof(struct bnxt_ulp_context), 0); if (!bp->ulp_ctx) { - BNXT_TF_DBG(ERR, "Failed to allocate ulp ctx\n"); + BNXT_DRV_DBG(ERR, "Failed to allocate ulp ctx\n"); return -ENOMEM; } + rc = bnxt_ulp_cntxt_bp_set(bp->ulp_ctx, bp); + if (rc) { + BNXT_DRV_DBG(ERR, "Failed to set bp in ulp_ctx\n"); + rte_free(bp->ulp_ctx); + return -EIO; + } + + /* This shouldn't fail, unless we have a unknown device */ + bp->ulp_ctx->ops = bnxt_ulp_port_func_ops_get(bp); + if (!bp->ulp_ctx->ops) { + BNXT_DRV_DBG(ERR, "Failed to get ulp ops\n"); + rte_free(bp->ulp_ctx); + return -EIO; + } + /* * Multiple uplink ports can be associated with a single vswitch. * Make sure only the port that is started first will initialize @@ -1950,7 +620,7 @@ bnxt_ulp_port_init(struct bnxt *bp) */ session = ulp_session_init(bp, &initialized); if (!session) { - BNXT_TF_DBG(ERR, "Failed to initialize the tf session\n"); + BNXT_DRV_DBG(ERR, "Failed to initialize the tf session\n"); rc = -EIO; goto jump_to_error; } @@ -1960,27 +630,15 @@ bnxt_ulp_port_init(struct bnxt *bp) * If ULP is already initialized for a specific domain then * simply assign the ulp context to this rte_eth_dev. */ - rc = ulp_ctx_attach(bp, session); - if (rc) { - BNXT_TF_DBG(ERR, "Failed to attach the ulp context\n"); - goto jump_to_error; - } - - /* - * Attach to the shared session, must be called after the - * ulp_ctx_attach in order to ensure that ulp data is available - * for attaching. - */ - rc = ulp_ctx_shared_session_attach(bp, session); + rc = bp->ulp_ctx->ops->ulp_ctx_attach(bp, session); if (rc) { - BNXT_TF_DBG(ERR, - "Failed attach to shared session (%d)", rc); + BNXT_DRV_DBG(ERR, "Failed to attach the ulp context\n"); goto jump_to_error; } } else { - rc = bnxt_ulp_init(bp, session); + rc = bp->ulp_ctx->ops->ulp_init(bp, session); if (rc) { - BNXT_TF_DBG(ERR, "Failed to initialize the ulp init\n"); + BNXT_DRV_DBG(ERR, "Failed to initialize the ulp init\n"); goto jump_to_error; } } @@ -1990,46 +648,54 @@ bnxt_ulp_port_init(struct bnxt *bp) if (rc) goto jump_to_error; + /* Update bnxt driver flags */ rc = ulp_dparms_dev_port_intf_update(bp, bp->ulp_ctx); if (rc) { - BNXT_TF_DBG(ERR, "Failed to update driver flags\n"); + BNXT_DRV_DBG(ERR, "Failed to update driver flags\n"); goto jump_to_error; } /* update the port database for the given interface */ rc = ulp_port_db_port_update(bp->ulp_ctx, bp->eth_dev); if (rc) { - BNXT_TF_DBG(ERR, "Failed to update port database\n"); + BNXT_DRV_DBG(ERR, "Failed to update port database\n"); goto jump_to_error; } /* create the default rules */ rc = bnxt_ulp_create_df_rules(bp); if (rc) { - BNXT_TF_DBG(ERR, "Failed to create default flow\n"); - goto jump_to_error; - } - - rc = bnxt_ulp_devid_get(bp, &devid); - if (rc) { - BNXT_TF_DBG(ERR, "Unable to determine device for ULP port init.\n"); + BNXT_DRV_DBG(ERR, "Failed to create default flow\n"); goto jump_to_error; } /* set the unicast mode */ if (bnxt_ulp_cntxt_ptr2_ulp_flags_get(bp->ulp_ctx, &ulp_flags)) { - BNXT_TF_DBG(ERR, "Error in getting ULP context flags\n"); + BNXT_DRV_DBG(ERR, "Error in getting ULP context flags\n"); goto jump_to_error; } if (ulp_flags & BNXT_ULP_APP_UNICAST_ONLY) { if (bnxt_pmd_set_unicast_rxmask(bp->eth_dev)) { - BNXT_TF_DBG(ERR, "Error in setting unicast rxmode\n"); + BNXT_DRV_DBG(ERR, "Error in setting unicast rxmode\n"); + goto jump_to_error; + } + } + + /* Make sure that custom header data is selected */ + if (dev_id > BNXT_ULP_DEVICE_ID_WH_PLUS) { + struct bnxt_vnic_info *vnic = bp->vnic_info; + vnic->metadata_format = HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_3; + rc = bnxt_hwrm_vnic_update(bp, + vnic, + HWRM_VNIC_UPDATE_INPUT_ENABLES_METADATA_FORMAT_TYPE_VALID); + if (rc) { + BNXT_DRV_DBG(ERR, "Failed to set metadata format\n"); goto jump_to_error; } } - rc = ulp_cust_vxlan_alloc(bp); + rc = ulp_cust_vxlan_alloc(bp); /* BAUCOM: Is this safe and generic? */ if (rc) goto jump_to_error; @@ -2044,6 +710,28 @@ bnxt_ulp_port_init(struct bnxt *bp) return rc; } +static void +ulp_cust_vxlan_free(struct bnxt *bp) +{ + int rc; + + if (ULP_APP_CUST_VXLAN_SUPPORT(bp->ulp_ctx)) { + rc = bnxt_tunnel_dst_port_free(bp, + bp->ulp_ctx->cfg_data->vxlan_port, + HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN); + if (rc) + BNXT_DRV_DBG(ERR, "Failed to clear global vxlan port\n"); + } + + if (ULP_APP_CUST_VXLAN_IP_SUPPORT(bp->ulp_ctx)) { + rc = bnxt_tunnel_dst_port_free(bp, + bp->ulp_ctx->cfg_data->vxlan_ip_port, + HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4); + if (rc) + BNXT_DRV_DBG(ERR, "Failed to clear global custom vxlan port\n"); + } +} + static void ulp_l2_etype_tunnel_free(struct bnxt *bp) { @@ -2053,15 +741,14 @@ ulp_l2_etype_tunnel_free(struct bnxt *bp) return; if (bp->l2_etype_tunnel_cnt == 0) { - BNXT_TF_DBG(DEBUG, "L2 ETYPE Custom Tunnel already freed\n"); + BNXT_DRV_DBG(DEBUG, "L2 ETYPE Custom Tunnel already freed\n"); return; } - rc = bnxt_tunnel_dst_port_free(bp, BNXT_L2_ETYPE_TUNNEL_ID, HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE); if (rc) - BNXT_TF_DBG(ERR, "Failed to clear L2 ETYPE Custom Tunnel\n"); + BNXT_DRV_DBG(ERR, "Failed to clear L2 ETYPE Custom Tunnel\n"); bp->l2_etype_tunnel_cnt--; } @@ -2078,26 +765,26 @@ bnxt_ulp_port_deinit(struct bnxt *bp) struct rte_pci_addr *pci_addr; if (!BNXT_TRUFLOW_EN(bp)) { - BNXT_TF_DBG(DEBUG, - "Skip ULP deinit for port:%d, TF is not enabled\n", - bp->eth_dev->data->port_id); + BNXT_DRV_DBG(DEBUG, + "Skip ULP deinit for port:%d, TF is not enabled\n", + bp->eth_dev->data->port_id); return; } if (!BNXT_PF(bp) && !BNXT_VF_IS_TRUSTED(bp)) { - BNXT_TF_DBG(DEBUG, - "Skip ULP deinit port:%d, not a TVF or PF\n", - bp->eth_dev->data->port_id); + BNXT_DRV_DBG(DEBUG, + "Skip ULP deinit port:%d, not a TVF or PF\n", + bp->eth_dev->data->port_id); return; } if (!bp->ulp_ctx) { - BNXT_TF_DBG(DEBUG, "ulp ctx already de-allocated\n"); + BNXT_DRV_DBG(DEBUG, "ulp ctx already de-allocated\n"); return; } - BNXT_TF_DBG(DEBUG, "BNXT Port:%d ULP port deinit\n", - bp->eth_dev->data->port_id); + BNXT_DRV_DBG(DEBUG, "BNXT Port:%d ULP port deinit\n", + bp->eth_dev->data->port_id); /* Get the session details */ pci_dev = RTE_DEV_TO_PCI(bp->eth_dev->device); @@ -2118,27 +805,34 @@ bnxt_ulp_port_deinit(struct bnxt *bp) if (bp->ulp_ctx->cfg_data && bp->ulp_ctx->cfg_data->ref_cnt) { bp->ulp_ctx->cfg_data->ref_cnt--; /* Free tunnels for each port */ + ulp_cust_vxlan_free(bp); ulp_l2_etype_tunnel_free(bp); if (bp->ulp_ctx->cfg_data->ref_cnt) { + /* Free the ulp context in the context entry list */ + bnxt_ulp_cntxt_list_del(bp->ulp_ctx); + /* free the port details */ /* Free the default flow rule associated to this port */ bnxt_ulp_destroy_df_rules(bp, false); bnxt_ulp_destroy_vfr_default_rules(bp, false); - /* Free the ulp context in the context entry list */ - bnxt_ulp_cntxt_list_del(bp->ulp_ctx); - /* free flows associated with this port */ bnxt_ulp_flush_port_flows(bp); /* close the session associated with this port */ - ulp_ctx_detach(bp); - - /* always detach/close shared after the session. */ - ulp_ctx_shared_session_detach(bp); + bp->ulp_ctx->ops->ulp_ctx_detach(bp, session); } else { + /* clean up default flows */ + bnxt_ulp_destroy_df_rules(bp, true); + + /* clean up default VFR flows */ + bnxt_ulp_destroy_vfr_default_rules(bp, true); + + /* clean up regular flows */ + ulp_flow_db_flush_flows(bp->ulp_ctx, BNXT_ULP_FDB_TYPE_REGULAR); + /* Perform ulp ctx deinit */ - bnxt_ulp_deinit(bp, session); + bp->ulp_ctx->ops->ulp_deinit(bp, session); } } @@ -2157,7 +851,7 @@ bnxt_ulp_cntxt_ptr2_mark_db_set(struct bnxt_ulp_context *ulp_ctx, struct bnxt_ulp_mark_tbl *mark_tbl) { if (!ulp_ctx || !ulp_ctx->cfg_data) { - BNXT_TF_DBG(ERR, "Invalid ulp context data\n"); + BNXT_DRV_DBG(ERR, "Invalid ulp context data\n"); return -EINVAL; } @@ -2230,7 +924,7 @@ bnxt_ulp_cntxt_dev_id_get(struct bnxt_ulp_context *ulp_ctx, return 0; } *dev_id = BNXT_ULP_DEVICE_ID_LAST; - BNXT_TF_DBG(ERR, "Failed to read dev_id from ulp ctxt\n"); + BNXT_DRV_DBG(ERR, "Failed to read dev_id from ulp ctxt\n"); return -EINVAL; } @@ -2242,7 +936,7 @@ bnxt_ulp_cntxt_mem_type_set(struct bnxt_ulp_context *ulp_ctx, ulp_ctx->cfg_data->mem_type = mem_type; return 0; } - BNXT_TF_DBG(ERR, "Failed to write mem_type in ulp ctxt\n"); + BNXT_DRV_DBG(ERR, "Failed to write mem_type in ulp ctxt\n"); return -EINVAL; } @@ -2255,7 +949,7 @@ bnxt_ulp_cntxt_mem_type_get(struct bnxt_ulp_context *ulp_ctx, return 0; } *mem_type = BNXT_ULP_FLOW_MEM_TYPE_LAST; - BNXT_TF_DBG(ERR, "Failed to read mem_type in ulp ctxt\n"); + BNXT_DRV_DBG(ERR, "Failed to read mem_type in ulp ctxt\n"); return -EINVAL; } @@ -2285,12 +979,83 @@ bnxt_ulp_cntxt_tbl_scope_id_set(struct bnxt_ulp_context *ulp_ctx, return -EINVAL; } +/* Function to set the v3 table scope id, only works for tfc objects */ +int32_t +bnxt_ulp_cntxt_tsid_set(struct bnxt_ulp_context *ulp_ctx, uint8_t tsid) +{ + if (ulp_ctx && ulp_ctx->tfo_type == BNXT_ULP_TFO_TYPE_TFC) { + ulp_ctx->tsid = tsid; + ULP_BITMAP_SET(ulp_ctx->tfo_flags, BNXT_ULP_TFO_TSID_FLAG); + return 0; + } + return -EINVAL; +} + +/* Function to reset the v3 table scope id, only works for tfc objects */ +void +bnxt_ulp_cntxt_tsid_reset(struct bnxt_ulp_context *ulp_ctx) +{ + if (ulp_ctx && ulp_ctx->tfo_type == BNXT_ULP_TFO_TYPE_TFC) + ULP_BITMAP_RESET(ulp_ctx->tfo_flags, BNXT_ULP_TFO_TSID_FLAG); +} + +/* Function to set the v3 table scope id, only works for tfc objects */ +int32_t +bnxt_ulp_cntxt_tsid_get(struct bnxt_ulp_context *ulp_ctx, uint8_t *tsid) +{ + if (ulp_ctx && tsid && + ulp_ctx->tfo_type == BNXT_ULP_TFO_TYPE_TFC && + ULP_BITMAP_ISSET(ulp_ctx->tfo_flags, BNXT_ULP_TFO_TSID_FLAG)) { + *tsid = ulp_ctx->tsid; + return 0; + } + return -EINVAL; +} + +/* Function to set the v3 session id, only works for tfc objects */ +int32_t +bnxt_ulp_cntxt_sid_set(struct bnxt_ulp_context *ulp_ctx, + uint16_t sid) +{ + if (ulp_ctx && ulp_ctx->tfo_type == BNXT_ULP_TFO_TYPE_TFC) { + ulp_ctx->sid = sid; + ULP_BITMAP_SET(ulp_ctx->tfo_flags, BNXT_ULP_TFO_SID_FLAG); + return 0; + } + return -EINVAL; +} + +/* + * Function to reset the v3 session id, only works for tfc objects + * There isn't a known invalid value for sid, so this is necessary + */ +void +bnxt_ulp_cntxt_sid_reset(struct bnxt_ulp_context *ulp_ctx) +{ + if (ulp_ctx && ulp_ctx->tfo_type == BNXT_ULP_TFO_TYPE_TFC) + ULP_BITMAP_RESET(ulp_ctx->tfo_flags, BNXT_ULP_TFO_SID_FLAG); +} + +/* Function to get the v3 session id, only works for tfc objects */ +int32_t +bnxt_ulp_cntxt_sid_get(struct bnxt_ulp_context *ulp_ctx, + uint16_t *sid) +{ + if (ulp_ctx && sid && + ulp_ctx->tfo_type == BNXT_ULP_TFO_TYPE_TFC && + ULP_BITMAP_ISSET(ulp_ctx->tfo_flags, BNXT_ULP_TFO_SID_FLAG)) { + *sid = ulp_ctx->sid; + return 0; + } + return -EINVAL; +} + /* Function to get the number of shared clients attached */ uint8_t bnxt_ulp_cntxt_num_shared_clients_get(struct bnxt_ulp_context *ulp) { if (ulp == NULL || ulp->cfg_data == NULL) { - BNXT_TF_DBG(ERR, "Invalid arguments\n"); + BNXT_DRV_DBG(ERR, "Invalid arguments\n"); return 0; } return ulp->cfg_data->num_shared_clients; @@ -2301,7 +1066,7 @@ int bnxt_ulp_cntxt_num_shared_clients_set(struct bnxt_ulp_context *ulp, bool incr) { if (ulp == NULL || ulp->cfg_data == NULL) { - BNXT_TF_DBG(ERR, "Invalid arguments\n"); + BNXT_DRV_DBG(ERR, "Invalid arguments\n"); return 0; } if (incr) @@ -2309,62 +1074,41 @@ bnxt_ulp_cntxt_num_shared_clients_set(struct bnxt_ulp_context *ulp, bool incr) else if (ulp->cfg_data->num_shared_clients) ulp->cfg_data->num_shared_clients--; - BNXT_TF_DBG(DEBUG, "%d:clients(%d)\n", incr, - ulp->cfg_data->num_shared_clients); + BNXT_DRV_DBG(DEBUG, "%d:clients(%d)\n", incr, + ulp->cfg_data->num_shared_clients); return 0; } -/* Function to set the tfp session details from the ulp context. */ int32_t -bnxt_ulp_cntxt_tfp_set(struct bnxt_ulp_context *ulp, - enum bnxt_ulp_session_type s_type, - struct tf *tfp) +bnxt_ulp_cntxt_bp_set(struct bnxt_ulp_context *ulp, struct bnxt *bp) { - uint32_t idx = 0; - - if (!ulp) { - BNXT_TF_DBG(ERR, "Invalid arguments\n"); + if (ulp == NULL) { + BNXT_DRV_DBG(ERR, "Invalid arguments\n"); return -EINVAL; } - if (ULP_MULTI_SHARED_IS_SUPPORTED(ulp)) { - if (s_type & BNXT_ULP_SESSION_TYPE_SHARED) - idx = 1; - else if (s_type & BNXT_ULP_SESSION_TYPE_SHARED_WC) - idx = 2; - - } else { - if ((s_type & BNXT_ULP_SESSION_TYPE_SHARED) || - (s_type & BNXT_ULP_SESSION_TYPE_SHARED_WC)) - idx = 1; - } - - ulp->g_tfp[idx] = tfp; + ulp->bp = bp; return 0; } -/* Function to get the tfp session details from the ulp context. */ -struct tf * -bnxt_ulp_cntxt_tfp_get(struct bnxt_ulp_context *ulp, - enum bnxt_ulp_session_type s_type) +struct bnxt* +bnxt_ulp_cntxt_bp_get(struct bnxt_ulp_context *ulp) { - uint32_t idx = 0; - - if (!ulp) { - BNXT_TF_DBG(ERR, "Invalid arguments\n"); + if (ulp == NULL) { + BNXT_DRV_DBG(ERR, "Invalid arguments\n"); return NULL; } - if (ULP_MULTI_SHARED_IS_SUPPORTED(ulp)) { - if (s_type & BNXT_ULP_SESSION_TYPE_SHARED) - idx = 1; - else if (s_type & BNXT_ULP_SESSION_TYPE_SHARED_WC) - idx = 2; - } else { - if ((s_type & BNXT_ULP_SESSION_TYPE_SHARED) || - (s_type & BNXT_ULP_SESSION_TYPE_SHARED_WC)) - idx = 1; - } - return ulp->g_tfp[idx]; + return ulp->bp; +} + +int32_t +bnxt_ulp_cntxt_fid_get(struct bnxt_ulp_context *ulp, uint16_t *fid) +{ + if (ulp == NULL || fid == NULL) + return -EINVAL; + + *fid = ulp->bp->fw_fid; + return 0; } /* @@ -2420,14 +1164,14 @@ bnxt_ulp_eth_dev_ptr2_cntxt_get(struct rte_eth_dev *dev) { struct bnxt *bp = (struct bnxt *)dev->data->dev_private; - if (rte_eth_dev_is_repr(dev)) { + if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) { struct bnxt_representor *vfr = dev->data->dev_private; bp = vfr->parent_dev->data->dev_private; } if (!bp) { - BNXT_TF_DBG(ERR, "Bnxt private data is not initialized\n"); + BNXT_DRV_DBG(ERR, "Bnxt private data is not initialized\n"); return NULL; } return bp->ulp_ctx; @@ -2438,7 +1182,7 @@ bnxt_ulp_cntxt_ptr2_mapper_data_set(struct bnxt_ulp_context *ulp_ctx, void *mapper_data) { if (!ulp_ctx || !ulp_ctx->cfg_data) { - BNXT_TF_DBG(ERR, "Invalid ulp context data\n"); + BNXT_DRV_DBG(ERR, "Invalid ulp context data\n"); return -EINVAL; } @@ -2450,13 +1194,37 @@ void * bnxt_ulp_cntxt_ptr2_mapper_data_get(struct bnxt_ulp_context *ulp_ctx) { if (!ulp_ctx || !ulp_ctx->cfg_data) { - BNXT_TF_DBG(ERR, "Invalid ulp context data\n"); + BNXT_DRV_DBG(ERR, "Invalid ulp context data\n"); return NULL; } return ulp_ctx->cfg_data->mapper_data; } +int32_t +bnxt_ulp_cntxt_ptr2_matcher_data_set(struct bnxt_ulp_context *ulp_ctx, + void *matcher_data) +{ + if (!ulp_ctx || !ulp_ctx->cfg_data) { + BNXT_DRV_DBG(ERR, "Invalid ulp context data\n"); + return -EINVAL; + } + + ulp_ctx->cfg_data->matcher_data = matcher_data; + return 0; +} + +void * +bnxt_ulp_cntxt_ptr2_matcher_data_get(struct bnxt_ulp_context *ulp_ctx) +{ + if (!ulp_ctx || !ulp_ctx->cfg_data) { + BNXT_DRV_DBG(ERR, "Invalid ulp context data\n"); + return NULL; + } + + return ulp_ctx->cfg_data->matcher_data; +} + /* Function to set the port database to the ulp context. */ int32_t bnxt_ulp_cntxt_ptr2_port_db_set(struct bnxt_ulp_context *ulp_ctx, @@ -2485,7 +1253,7 @@ bnxt_ulp_cntxt_ptr2_fc_info_set(struct bnxt_ulp_context *ulp_ctx, struct bnxt_ulp_fc_info *ulp_fc_info) { if (!ulp_ctx || !ulp_ctx->cfg_data) { - BNXT_TF_DBG(ERR, "Invalid ulp context data\n"); + BNXT_DRV_DBG(ERR, "Invalid ulp context data\n"); return -EINVAL; } @@ -2535,7 +1303,7 @@ bnxt_ulp_cntxt_acquire_fdb_lock(struct bnxt_ulp_context *ulp_ctx) return -1; if (pthread_mutex_lock(&ulp_ctx->cfg_data->flow_db_lock)) { - BNXT_TF_DBG(ERR, "unable to acquire fdb lock\n"); + BNXT_DRV_DBG(ERR, "unable to acquire fdb lock\n"); return -1; } return 0; @@ -2596,7 +1364,7 @@ bnxt_ulp_cntxt_ptr2_ha_info_set(struct bnxt_ulp_context *ulp_ctx, struct bnxt_ulp_ha_mgr_info *ulp_ha_info) { if (ulp_ctx == NULL || ulp_ctx->cfg_data == NULL) { - BNXT_TF_DBG(ERR, "Invalid ulp context data\n"); + BNXT_DRV_DBG(ERR, "Invalid ulp context data\n"); return -EINVAL; } ulp_ctx->cfg_data->ha_info = ulp_ha_info; @@ -2620,7 +1388,7 @@ bnxt_ulp_cntxt_ha_enabled(struct bnxt_ulp_context *ulp_ctx) return !!ULP_HIGH_AVAIL_IS_ENABLED(ulp_ctx->cfg_data->ulp_flags); } -static int32_t +int32_t bnxt_ulp_cntxt_list_init(void) { /* Create the cntxt spin lock only once*/ @@ -2630,14 +1398,14 @@ bnxt_ulp_cntxt_list_init(void) return 0; } -static int32_t +int32_t bnxt_ulp_cntxt_list_add(struct bnxt_ulp_context *ulp_ctx) { struct ulp_context_list_entry *entry; entry = rte_zmalloc(NULL, sizeof(struct ulp_context_list_entry), 0); if (entry == NULL) { - BNXT_TF_DBG(ERR, "unable to allocate memory\n"); + BNXT_DRV_DBG(ERR, "unable to allocate memory\n"); return -ENOMEM; } @@ -2648,7 +1416,7 @@ bnxt_ulp_cntxt_list_add(struct bnxt_ulp_context *ulp_ctx) return 0; } -static void +void bnxt_ulp_cntxt_list_del(struct bnxt_ulp_context *ulp_ctx) { struct ulp_context_list_entry *entry, *temp; @@ -2719,7 +1487,7 @@ bnxt_ulp_cntxt_convert_dev_id(uint32_t ulp_dev_id) type = TF_DEVICE_TYPE_P5; break; default: - BNXT_TF_DBG(ERR, "Invalid device id\n"); + BNXT_DRV_DBG(ERR, "Invalid device id\n"); break; } return type; @@ -2730,7 +1498,7 @@ bnxt_ulp_cntxt_convert_dev_id(uint32_t ulp_dev_id) * the firmware. */ int32_t -bnxt_ulp_ha_reg_set(struct bnxt_ulp_context *ulp_ctx, +bnxt_ulp_cntxt_ha_reg_set(struct bnxt_ulp_context *ulp_ctx, uint8_t state, uint8_t cnt) { if (!ulp_ctx || !ulp_ctx->cfg_data) @@ -2751,7 +1519,7 @@ bnxt_ulp_ha_reg_set(struct bnxt_ulp_context *ulp_ctx, * the firmware. */ uint32_t -bnxt_ulp_ha_reg_state_get(struct bnxt_ulp_context *ulp_ctx) +bnxt_ulp_cntxt_ha_reg_state_get(struct bnxt_ulp_context *ulp_ctx) { if (!ulp_ctx || !ulp_ctx->cfg_data) return 0; @@ -2764,7 +1532,7 @@ bnxt_ulp_ha_reg_state_get(struct bnxt_ulp_context *ulp_ctx) * the firmware. */ uint32_t -bnxt_ulp_ha_reg_cnt_get(struct bnxt_ulp_context *ulp_ctx) +bnxt_ulp_cntxt_ha_reg_cnt_get(struct bnxt_ulp_context *ulp_ctx) { if (!ulp_ctx || !ulp_ctx->cfg_data) return 0; @@ -2772,17 +1540,24 @@ bnxt_ulp_ha_reg_cnt_get(struct bnxt_ulp_context *ulp_ctx) return (uint32_t)ulp_ctx->cfg_data->hu_reg_cnt; } -struct tf* -bnxt_ulp_bp_tfp_get(struct bnxt *bp, enum bnxt_ulp_session_type type) +/* This function sets the number of key recipes supported + * Generally, this should be set to the number of flexible keys + * supported + */ +void +bnxt_ulp_num_key_recipes_set(struct bnxt_ulp_context *ulp_ctx, + uint16_t num_recipes) { - enum bnxt_session_type btype; - - if (type & BNXT_ULP_SESSION_TYPE_SHARED) - btype = BNXT_SESSION_TYPE_SHARED_COMMON; - else if (type & BNXT_ULP_SESSION_TYPE_SHARED_WC) - btype = BNXT_SESSION_TYPE_SHARED_WC; - else - btype = BNXT_SESSION_TYPE_REGULAR; + if (!ulp_ctx || !ulp_ctx->cfg_data) + return; + ulp_ctx->cfg_data->num_key_recipes_per_dir = num_recipes; +} - return bnxt_get_tfp_session(bp, btype); +/* This function gets the number of key recipes supported */ +int32_t +bnxt_ulp_num_key_recipes_get(struct bnxt_ulp_context *ulp_ctx) +{ + if (!ulp_ctx || !ulp_ctx->cfg_data) + return 0; + return ulp_ctx->cfg_data->num_key_recipes_per_dir; } diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h index 32a7455bd6..7b6fd58acb 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h @@ -40,7 +40,9 @@ #define BNXT_ULP_CUST_VXLAN_SUPPORT 0x100 #define BNXT_ULP_MULTI_SHARED_SUPPORT 0x200 #define BNXT_ULP_APP_HA_DYNAMIC 0x400 -#define BNXT_ULP_APP_L2_ETYPE 0x800 +#define BNXT_ULP_APP_SRV6 0x800 +#define BNXT_ULP_APP_L2_ETYPE 0x1000 +#define BNXT_ULP_SHARED_TBL_SCOPE_ENABLED 0x2000 #define ULP_VF_REP_IS_ENABLED(flag) ((flag) & BNXT_ULP_VF_REP_ENABLED) #define ULP_SHARED_SESSION_IS_ENABLED(flag) ((flag) &\ @@ -106,6 +108,7 @@ struct bnxt_ulp_data { struct bnxt_ulp_flow_db *flow_db; pthread_mutex_t flow_db_lock; void *mapper_data; + void *matcher_data; struct bnxt_ulp_port_db *port_db; struct bnxt_ulp_fc_info *fc_info; struct bnxt_ulp_ha_mgr_info *ha_info; @@ -125,17 +128,47 @@ struct bnxt_ulp_data { uint32_t vxlan_ip_port; uint32_t ecpri_udp_port; uint32_t hu_session_type; + uint32_t max_pools; + uint32_t num_rx_flows; + uint32_t num_tx_flows; + uint16_t act_rx_max_sz; + uint16_t act_tx_max_sz; + uint16_t em_rx_key_max_sz; + uint16_t em_tx_key_max_sz; + uint32_t page_sz; uint8_t hu_reg_state; uint8_t hu_reg_cnt; uint8_t ha_pool_id; uint8_t tunnel_next_proto; + uint8_t em_multiplier; enum bnxt_ulp_session_type def_session_type; + uint16_t num_key_recipes_per_dir; +}; + +enum bnxt_ulp_tfo_type { + BNXT_ULP_TFO_TYPE_INVALID = 0, + BNXT_ULP_TFO_TYPE_TF, + BNXT_ULP_TFO_TYPE_TFC }; #define BNXT_ULP_SESSION_MAX 3 +#define BNXT_ULP_TFO_SID_FLAG (1) +#define BNXT_ULP_TFO_TSID_FLAG (1 << 1) + struct bnxt_ulp_context { struct bnxt_ulp_data *cfg_data; - struct tf *g_tfp[BNXT_ULP_SESSION_MAX]; + struct bnxt *bp; + enum bnxt_ulp_tfo_type tfo_type; + union { + void *g_tfp[BNXT_ULP_SESSION_MAX]; + struct { + uint32_t tfo_flags; + void *tfcp; + uint16_t sid; + uint8_t tsid; + }; + }; + const struct bnxt_ulp_core_ops *ops; }; struct bnxt_ulp_pci_info { @@ -153,6 +186,8 @@ struct bnxt_ulp_session_state { struct bnxt_ulp_data *cfg_data; struct tf *g_tfp[BNXT_ULP_SESSION_MAX]; uint32_t session_opened[BNXT_ULP_SESSION_MAX]; + /* Need to revisit a union for the tf related data */ + uint16_t session_id; }; /* ULP flow id structure */ @@ -171,6 +206,28 @@ struct ulp_context_list_entry { struct bnxt_ulp_context *ulp_ctx; }; +struct bnxt_ulp_core_ops { + int32_t + (*ulp_init)(struct bnxt *bp, + struct bnxt_ulp_session_state *session); + void + (*ulp_deinit)(struct bnxt *bp, + struct bnxt_ulp_session_state *session); + int32_t + (*ulp_ctx_attach)(struct bnxt *bp, + struct bnxt_ulp_session_state *session); + void + (*ulp_ctx_detach)(struct bnxt *bp, + struct bnxt_ulp_session_state *session); +}; + +extern const struct bnxt_ulp_core_ops bnxt_ulp_tf_core_ops; +extern const struct bnxt_ulp_core_ops bnxt_ulp_tfc_core_ops; + +int32_t +bnxt_ulp_devid_get(struct bnxt *bp, + enum bnxt_ulp_device_id *ulp_dev_id); + bool ulp_is_default_session_active(struct bnxt_ulp_context *ulp_ctx); @@ -209,7 +266,7 @@ int32_t bnxt_ulp_cntxt_tbl_scope_id_get(struct bnxt_ulp_context *ulp_ctx, uint32_t *tbl_scope_id); -/* Function to set the tfp session details in the ulp context. */ +/* Function to set the bp associated with the ulp_ctx */ int32_t bnxt_ulp_cntxt_tfp_set(struct bnxt_ulp_context *ulp, enum bnxt_ulp_session_type s_type, @@ -220,6 +277,48 @@ struct tf * bnxt_ulp_cntxt_tfp_get(struct bnxt_ulp_context *ulp, enum bnxt_ulp_session_type s_type); +int32_t +bnxt_ulp_cntxt_bp_set(struct bnxt_ulp_context *ulp, struct bnxt *bp); + +/* Function to get the bp associated with the ulp_ctx */ +struct bnxt * +bnxt_ulp_cntxt_bp_get(struct bnxt_ulp_context *ulp); + +/* Function to set the v3 table scope id, only works for tfc objects */ +int32_t +bnxt_ulp_cntxt_tsid_set(struct bnxt_ulp_context *ulp_ctx, uint8_t tsid); + +/* + * Function to set the v3 table scope id, only works for tfc objects + * There isn't a known invalid value for tsid, so this is necessary in order to + * know that the tsid is not set. + */ +void +bnxt_ulp_cntxt_tsid_reset(struct bnxt_ulp_context *ulp_ctx); + +/* Function to set the v3 table scope id, only works for tfc objects */ +int32_t +bnxt_ulp_cntxt_tsid_get(struct bnxt_ulp_context *ulp_ctx, uint8_t *tsid); + +/* Function to set the v3 session id, only works for tfc objects */ +int32_t +bnxt_ulp_cntxt_sid_set(struct bnxt_ulp_context *ulp_ctx, uint16_t session_id); + +/* + * Function to reset the v3 session id, only works for tfc objects + * There isn't a known invalid value for sid, so this is necessary in order to + * know that the sid is not set. + */ +void +bnxt_ulp_cntxt_sid_reset(struct bnxt_ulp_context *ulp_ctx); + +/* Function to get the v3 session id, only works for tfc objects */ +int32_t +bnxt_ulp_cntxt_sid_get(struct bnxt_ulp_context *ulp_ctx, uint16_t *sid); + +int32_t +bnxt_ulp_cntxt_fid_get(struct bnxt_ulp_context *ulp, uint16_t *fw_fid); + /* Get the device table entry based on the device id. */ struct bnxt_ulp_device_params * bnxt_ulp_device_params_get(uint32_t dev_id); @@ -257,6 +356,15 @@ bnxt_ulp_cntxt_ptr2_mapper_data_set(struct bnxt_ulp_context *ulp_ctx, void * bnxt_ulp_cntxt_ptr2_mapper_data_get(struct bnxt_ulp_context *ulp_ctx); +/* Function to add the ulp matcher data to the ulp context */ +int32_t +bnxt_ulp_cntxt_ptr2_matcher_data_set(struct bnxt_ulp_context *ulp_ctx, + void *matcher_data); + +/* Function to get the ulp matcher data from the ulp context */ +void * +bnxt_ulp_cntxt_ptr2_matcher_data_get(struct bnxt_ulp_context *ulp_ctx); + /* Function to set the port database to the ulp context. */ int32_t bnxt_ulp_cntxt_ptr2_port_db_set(struct bnxt_ulp_context *ulp_ctx, @@ -340,9 +448,8 @@ bnxt_ulp_cntxt_multi_shared_session_enabled(struct bnxt_ulp_context *ulp_ctx); struct bnxt_ulp_app_capabilities_info * bnxt_ulp_app_cap_list_get(uint32_t *num_entries); -int32_t -bnxt_ulp_cntxt_app_caps_init(struct bnxt *bp, - uint8_t app_id, uint32_t dev_id); +struct bnxt_ulp_resource_resv_info * +bnxt_ulp_app_resource_resv_list_get(uint32_t *num_entries); struct bnxt_ulp_resource_resv_info * bnxt_ulp_resource_resv_list_get(uint32_t *num_entries); @@ -407,6 +514,26 @@ bnxt_ulp_vxlan_gpe_next_proto_set(struct bnxt_ulp_context *ulp_ctx, uint8_t bnxt_ulp_vxlan_gpe_next_proto_get(struct bnxt_ulp_context *ulp_ctx); +int +bnxt_ulp_cntxt_vxlan_port_set(struct bnxt_ulp_context *ulp_ctx, + uint32_t vxlan_port); +unsigned int +bnxt_ulp_cntxt_vxlan_port_get(struct bnxt_ulp_context *ulp_ctx); + +unsigned int +bnxt_ulp_default_app_priority_get(struct bnxt_ulp_context *ulp_ctx); + +int +bnxt_ulp_cntxt_vxlan_ip_port_set(struct bnxt_ulp_context *ulp_ctx, + uint32_t vxlan_ip_port); +unsigned int +bnxt_ulp_cntxt_vxlan_ip_port_get(struct bnxt_ulp_context *ulp_ctx); +int +bnxt_ulp_cntxt_ecpri_udp_port_set(struct bnxt_ulp_context *ulp_ctx, + uint32_t ecpri_udp_port); +unsigned int +bnxt_ulp_cntxt_ecpri_udp_port_get(struct bnxt_ulp_context *ulp_ctx); + int32_t bnxt_flow_meter_init(struct bnxt *bp); @@ -425,4 +552,28 @@ bnxt_ulp_ha_reg_cnt_get(struct bnxt_ulp_context *ulp_ctx); struct tf* bnxt_ulp_bp_tfp_get(struct bnxt *bp, enum bnxt_ulp_session_type type); + +int32_t +bnxt_ulp_cntxt_ha_reg_set(struct bnxt_ulp_context *ulp_ctx, + uint8_t state, uint8_t cnt); + +uint32_t +bnxt_ulp_cntxt_ha_reg_state_get(struct bnxt_ulp_context *ulp_ctx); + +uint32_t +bnxt_ulp_cntxt_ha_reg_cnt_get(struct bnxt_ulp_context *ulp_ctx); + +int32_t bnxt_ulp_cntxt_list_init(void); + +int32_t bnxt_ulp_cntxt_list_add(struct bnxt_ulp_context *ulp_ctx); + +void bnxt_ulp_cntxt_list_del(struct bnxt_ulp_context *ulp_ctx); + +void +bnxt_ulp_destroy_vfr_default_rules(struct bnxt *bp, bool global); + +void bnxt_ulp_num_key_recipes_set(struct bnxt_ulp_context *ulp_ctx, + uint16_t recipes); + +int32_t bnxt_ulp_num_key_recipes_get(struct bnxt_ulp_context *ulp_ctx); #endif /* _BNXT_ULP_H_ */ diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c index 2f159ae486..189d4c76d9 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c @@ -91,42 +91,73 @@ bnxt_ulp_init_parser_cf_defaults(struct ulp_rte_parser_params *params, BNXT_ULP_INVALID_SVIF_VAL); } +static void +bnxt_ulp_init_cf_header_bitmap(struct ulp_rte_parser_params *params) +{ + uint64_t hdr_bits = 0; + + /* Remove the internal tunnel bits */ + hdr_bits = params->hdr_bitmap.bits; + ULP_BITMAP_RESET(hdr_bits, BNXT_ULP_HDR_BIT_F2); + + /* Add untag bits */ + if (!ULP_BITMAP_ISSET(hdr_bits, BNXT_ULP_HDR_BIT_OO_VLAN) && + !ULP_BITMAP_ISSET(hdr_bits, BNXT_ULP_HDR_BIT_OI_VLAN)) { + ULP_BITMAP_SET(hdr_bits, BNXT_ULP_HDR_BIT_O_UNTAGGED); + } + if (!ULP_BITMAP_ISSET(hdr_bits, BNXT_ULP_HDR_BIT_IO_VLAN) && + !ULP_BITMAP_ISSET(hdr_bits, BNXT_ULP_HDR_BIT_II_VLAN)) { + ULP_BITMAP_SET(hdr_bits, BNXT_ULP_HDR_BIT_I_UNTAGGED); + } + /* Add non-tunnel bit */ + if (!ULP_BITMAP_SET(params->cf_bitmap, BNXT_ULP_CF_BIT_IS_TUNNEL)) + ULP_BITMAP_SET(hdr_bits, BNXT_ULP_HDR_BIT_NON_TUNNEL); + + /*update the comp field header bits */ + ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_HDR_BITMAP, hdr_bits); +} + void -bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_create_parms *mapper_cparms, +bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_parms *mparms, struct ulp_rte_parser_params *params, enum bnxt_ulp_fdb_type flow_type) { uint32_t ulp_flags = 0; - memset(mapper_cparms, 0, sizeof(*mapper_cparms)); - mapper_cparms->flow_type = flow_type; - mapper_cparms->app_priority = params->priority; - mapper_cparms->dir_attr = params->dir_attr; - mapper_cparms->class_tid = params->class_id; - mapper_cparms->act_tid = params->act_tmpl; - mapper_cparms->func_id = params->func_id; - mapper_cparms->hdr_bitmap = ¶ms->hdr_bitmap; - mapper_cparms->enc_hdr_bitmap = ¶ms->enc_hdr_bitmap; - mapper_cparms->hdr_field = params->hdr_field; - mapper_cparms->enc_field = params->enc_field; - mapper_cparms->comp_fld = params->comp_fld; - mapper_cparms->act = ¶ms->act_bitmap; - mapper_cparms->act_prop = ¶ms->act_prop; - mapper_cparms->flow_id = params->fid; - mapper_cparms->parent_flow = params->parent_flow; - mapper_cparms->child_flow = params->child_flow; - mapper_cparms->fld_bitmap = ¶ms->fld_bitmap; - mapper_cparms->flow_pattern_id = params->flow_pattern_id; - mapper_cparms->act_pattern_id = params->act_pattern_id; - mapper_cparms->app_id = params->app_id; - mapper_cparms->port_id = params->port_id; - mapper_cparms->tun_idx = params->tun_idx; + mparms->flow_type = flow_type; + mparms->app_priority = params->priority; + mparms->class_tid = params->class_id; + mparms->act_tid = params->act_tmpl; + mparms->func_id = params->func_id; + mparms->hdr_bitmap = ¶ms->hdr_bitmap; + mparms->enc_hdr_bitmap = ¶ms->enc_hdr_bitmap; + mparms->hdr_field = params->hdr_field; + mparms->enc_field = params->enc_field; + mparms->comp_fld = params->comp_fld; + mparms->act_bitmap = ¶ms->act_bitmap; + mparms->act_prop = ¶ms->act_prop; + mparms->parent_flow = params->parent_flow; + mparms->child_flow = params->child_flow; + mparms->fld_bitmap = ¶ms->fld_bitmap; + mparms->flow_pattern_id = params->flow_pattern_id; + mparms->act_pattern_id = params->act_pattern_id; + mparms->wc_field_bitmap = params->wc_field_bitmap; + mparms->app_id = params->app_id; + mparms->tun_idx = params->tun_idx; + mparms->cf_bitmap = params->cf_bitmap; + mparms->exclude_field_bitmap = params->exclude_field_bitmap; /* update the signature fields into the computed field list */ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_HDR_SIG_ID, - params->hdr_sig_id); + params->class_info_idx); + + /* update the header bitmap */ + bnxt_ulp_init_cf_header_bitmap(params); + ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_FLOW_SIG_ID, params->flow_sig_id); + ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_FUNCTION_ID, + params->func_id); if (bnxt_ulp_cntxt_ptr2_ulp_flags_get(params->ulp_ctx, &ulp_flags)) return; @@ -138,7 +169,7 @@ bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_create_parms *mapper_cparms, rc = ulp_ha_mgr_region_get(params->ulp_ctx, ®ion); if (rc) - BNXT_TF_DBG(ERR, "Unable to get WC region\n"); + BNXT_DRV_DBG(ERR, "Unable to get WC region\n"); if (region == ULP_HA_REGION_HI) ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_WC_IS_HA_HIGH_REG, @@ -159,13 +190,14 @@ bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_create_parms *mapper_cparms, if (ulp_port_db_dev_port_to_ulp_index(params->ulp_ctx, params->port_id, &ifindex)) { - BNXT_TF_DBG(ERR, "Invalid port id %u\n", - params->port_id); + BNXT_DRV_DBG(ERR, "Invalid port id %u\n", + params->port_id); return; } /* Update the phy port of the other interface */ if (ulp_port_db_vport_get(params->ulp_ctx, ifindex, &vport)) { - BNXT_TF_DBG(ERR, "Invalid port if index %u\n", ifindex); + BNXT_DRV_DBG(ERR, "Invalid port if index %u\n", + ifindex); return; } ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_SOCKET_DIRECT_VPORT, @@ -181,7 +213,7 @@ bnxt_ulp_flow_create(struct rte_eth_dev *dev, const struct rte_flow_action actions[], struct rte_flow_error *error) { - struct bnxt_ulp_mapper_create_parms mapper_cparms = { 0 }; + struct bnxt_ulp_mapper_parms mparms = { 0 }; struct ulp_rte_parser_params params; struct bnxt_ulp_context *ulp_ctx; int rc, ret = BNXT_TF_RC_ERROR; @@ -189,16 +221,19 @@ bnxt_ulp_flow_create(struct rte_eth_dev *dev, uint16_t func_id; uint32_t fid; + if (error != NULL) + error->type = RTE_FLOW_ERROR_TYPE_NONE; + if (bnxt_ulp_flow_validate_args(attr, pattern, actions, error) == BNXT_TF_RC_ERROR) { - BNXT_TF_DBG(ERR, "Invalid arguments being passed\n"); + BNXT_DRV_DBG(ERR, "Invalid arguments being passed\n"); goto flow_error; } ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(dev); if (!ulp_ctx) { - BNXT_TF_DBG(ERR, "ULP context is not initialized\n"); + BNXT_DRV_DBG(ERR, "ULP context is not initialized\n"); goto flow_error; } @@ -207,7 +242,7 @@ bnxt_ulp_flow_create(struct rte_eth_dev *dev, params.ulp_ctx = ulp_ctx; if (bnxt_ulp_cntxt_app_id_get(params.ulp_ctx, ¶ms.app_id)) { - BNXT_TF_DBG(ERR, "failed to get the app id\n"); + BNXT_DRV_DBG(ERR, "failed to get the app id\n"); goto flow_error; } @@ -220,13 +255,13 @@ bnxt_ulp_flow_create(struct rte_eth_dev *dev, if (ulp_port_db_port_func_id_get(ulp_ctx, dev->data->port_id, &func_id)) { - BNXT_TF_DBG(ERR, "conversion of port to func id failed\n"); + BNXT_DRV_DBG(ERR, "conversion of port to func id failed\n"); goto flow_error; } /* Protect flow creation */ if (bnxt_ulp_cntxt_acquire_fdb_lock(ulp_ctx)) { - BNXT_TF_DBG(ERR, "Flow db lock acquire failed\n"); + BNXT_DRV_DBG(ERR, "Flow db lock acquire failed\n"); goto flow_error; } @@ -237,7 +272,7 @@ bnxt_ulp_flow_create(struct rte_eth_dev *dev, rc = ulp_flow_db_fid_alloc(ulp_ctx, BNXT_ULP_FDB_TYPE_REGULAR, func_id, &fid); if (rc) { - BNXT_TF_DBG(ERR, "Unable to allocate flow table entry\n"); + BNXT_DRV_DBG(ERR, "Unable to allocate flow table entry\n"); goto release_lock; } @@ -251,10 +286,10 @@ bnxt_ulp_flow_create(struct rte_eth_dev *dev, if (ret != BNXT_TF_RC_SUCCESS) goto free_fid; - params.fid = fid; - params.func_id = func_id; - params.priority = attr->priority; - params.port_id = dev->data->port_id; + mparms.flow_id = fid; + mparms.func_id = func_id; + mparms.app_priority = attr->priority; + mparms.port_id = dev->data->port_id; /* Perform the rte flow post process */ bnxt_ulp_rte_parser_post_process(¶ms); @@ -272,10 +307,11 @@ bnxt_ulp_flow_create(struct rte_eth_dev *dev, if (ret != BNXT_TF_RC_SUCCESS) goto free_fid; - bnxt_ulp_init_mapper_params(&mapper_cparms, ¶ms, + bnxt_ulp_init_mapper_params(&mparms, ¶ms, BNXT_ULP_FDB_TYPE_REGULAR); /* Call the ulp mapper to create the flow in the hardware. */ - ret = ulp_mapper_flow_create(ulp_ctx, &mapper_cparms); + ret = ulp_mapper_flow_create(ulp_ctx, &mparms, + (void *)error); if (ret) goto free_fid; @@ -289,7 +325,10 @@ bnxt_ulp_flow_create(struct rte_eth_dev *dev, release_lock: bnxt_ulp_cntxt_release_fdb_lock(ulp_ctx); flow_error: - rte_flow_error_set(error, ret, RTE_FLOW_ERROR_TYPE_HANDLE, NULL, + if (error != NULL && + error->type == RTE_FLOW_ERROR_TYPE_NONE) + rte_flow_error_set(error, ret, + RTE_FLOW_ERROR_TYPE_HANDLE, NULL, "Failed to create flow."); return NULL; } @@ -310,13 +349,13 @@ bnxt_ulp_flow_validate(struct rte_eth_dev *dev, if (bnxt_ulp_flow_validate_args(attr, pattern, actions, error) == BNXT_TF_RC_ERROR) { - BNXT_TF_DBG(ERR, "Invalid arguments being passed\n"); + BNXT_DRV_DBG(ERR, "Invalid arguments being passed\n"); goto parse_error; } ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(dev); if (!ulp_ctx) { - BNXT_TF_DBG(ERR, "ULP context is not initialized\n"); + BNXT_DRV_DBG(ERR, "ULP context is not initialized\n"); goto parse_error; } @@ -325,7 +364,7 @@ bnxt_ulp_flow_validate(struct rte_eth_dev *dev, params.ulp_ctx = ulp_ctx; if (bnxt_ulp_cntxt_app_id_get(params.ulp_ctx, ¶ms.app_id)) { - BNXT_TF_DBG(ERR, "failed to get the app id\n"); + BNXT_DRV_DBG(ERR, "failed to get the app id\n"); goto parse_error; } @@ -380,9 +419,12 @@ bnxt_ulp_flow_destroy(struct rte_eth_dev *dev, uint16_t func_id; int ret; + if (error != NULL) + error->type = RTE_FLOW_ERROR_TYPE_NONE; + ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(dev); if (!ulp_ctx) { - BNXT_TF_DBG(ERR, "ULP context is not initialized\n"); + BNXT_DRV_DBG(ERR, "ULP context is not initialized\n"); if (error) rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_HANDLE, NULL, @@ -395,7 +437,7 @@ bnxt_ulp_flow_destroy(struct rte_eth_dev *dev, if (ulp_port_db_port_func_id_get(ulp_ctx, dev->data->port_id, &func_id)) { - BNXT_TF_DBG(ERR, "conversion of port to func id failed\n"); + BNXT_DRV_DBG(ERR, "conversion of port to func id failed\n"); if (error) rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_HANDLE, NULL, @@ -405,7 +447,7 @@ bnxt_ulp_flow_destroy(struct rte_eth_dev *dev, if (ulp_flow_db_validate_flow_func(ulp_ctx, flow_id, func_id) == false) { - BNXT_TF_DBG(ERR, "Incorrect device params\n"); + BNXT_DRV_DBG(ERR, "Incorrect device params\n"); if (error) rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_HANDLE, NULL, @@ -414,14 +456,15 @@ bnxt_ulp_flow_destroy(struct rte_eth_dev *dev, } if (bnxt_ulp_cntxt_acquire_fdb_lock(ulp_ctx)) { - BNXT_TF_DBG(ERR, "Flow db lock acquire failed\n"); + BNXT_DRV_DBG(ERR, "Flow db lock acquire failed\n"); return -EINVAL; } ret = ulp_mapper_flow_destroy(ulp_ctx, BNXT_ULP_FDB_TYPE_REGULAR, - flow_id); + flow_id, (void *)error); if (ret) { - BNXT_TF_DBG(ERR, "Failed to destroy flow.\n"); - if (error) + BNXT_DRV_DBG(ERR, "Failed to destroy flow.\n"); + if (error != NULL && + error->type == RTE_FLOW_ERROR_TYPE_NONE) rte_flow_error_set(error, -ret, RTE_FLOW_ERROR_TYPE_HANDLE, NULL, "Failed to destroy flow."); @@ -455,7 +498,7 @@ bnxt_ulp_flow_flush(struct rte_eth_dev *eth_dev, if (!ret) ret = ulp_flow_db_function_flow_flush(ulp_ctx, func_id); else - BNXT_TF_DBG(ERR, "convert port to func id failed\n"); + BNXT_DRV_DBG(ERR, "convert port to func id failed\n"); } if (ret) rte_flow_error_set(error, ret, @@ -479,7 +522,7 @@ bnxt_ulp_flow_query(struct rte_eth_dev *eth_dev, ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(eth_dev); if (!ulp_ctx) { - BNXT_TF_DBG(ERR, "ULP context is not initialized\n"); + BNXT_DRV_DBG(ERR, "ULP context is not initialized\n"); rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_HANDLE, NULL, "Failed to query flow."); @@ -538,7 +581,7 @@ bnxt_ulp_action_handle_create(struct rte_eth_dev *dev, struct rte_flow_error *error) { enum bnxt_ulp_intf_type port_type = BNXT_ULP_INTF_TYPE_INVALID; - struct bnxt_ulp_mapper_create_parms mparms = { 0 }; + struct bnxt_ulp_mapper_parms mparms = { 0 }; struct ulp_rte_parser_params params; struct bnxt_ulp_context *ulp_ctx; uint32_t act_tid; @@ -555,12 +598,15 @@ bnxt_ulp_action_handle_create(struct rte_eth_dev *dev, } }; + if (error != NULL) + error->type = RTE_FLOW_ERROR_TYPE_NONE; + if (bnxt_ulp_action_handle_chk_args(action, conf) != BNXT_TF_RC_SUCCESS) goto parse_error; ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(dev); if (!ulp_ctx) { - BNXT_TF_DBG(ERR, "ULP context is not initialized\n"); + BNXT_DRV_DBG(ERR, "ULP context is not initialized\n"); goto parse_error; } @@ -577,12 +623,12 @@ bnxt_ulp_action_handle_create(struct rte_eth_dev *dev, if (ulp_port_db_dev_port_to_ulp_index(ulp_ctx, dev->data->port_id, &ifindex)) { - BNXT_TF_DBG(ERR, "Port id is not valid\n"); + BNXT_DRV_DBG(ERR, "Port id is not valid\n"); goto parse_error; } port_type = ulp_port_db_port_type_get(ulp_ctx, ifindex); if (port_type == BNXT_ULP_INTF_TYPE_INVALID) { - BNXT_TF_DBG(ERR, "Port type is not valid\n"); + BNXT_DRV_DBG(ERR, "Port type is not valid\n"); goto parse_error; } @@ -610,12 +656,12 @@ bnxt_ulp_action_handle_create(struct rte_eth_dev *dev, if (ulp_port_db_dev_port_to_ulp_index(ulp_ctx, dev->data->port_id, &ifindex)) { - BNXT_TF_DBG(ERR, "Port id is not valid\n"); + BNXT_DRV_DBG(ERR, "Port id is not valid\n"); goto parse_error; } port_type = ulp_port_db_port_type_get(ulp_ctx, ifindex); if (port_type == BNXT_ULP_INTF_TYPE_INVALID) { - BNXT_TF_DBG(ERR, "Port type is not valid\n"); + BNXT_DRV_DBG(ERR, "Port type is not valid\n"); goto parse_error; } @@ -638,6 +684,7 @@ bnxt_ulp_action_handle_create(struct rte_eth_dev *dev, ULP_COMP_FLD_IDX_WR(¶ms, BNXT_ULP_CF_IDX_DIRECTION, BNXT_ULP_DIR_EGRESS); } + /* Parse the shared action */ ret = bnxt_ulp_rte_parser_act_parse(actions, ¶ms); if (ret != BNXT_TF_RC_SUCCESS) @@ -663,17 +710,18 @@ bnxt_ulp_action_handle_create(struct rte_eth_dev *dev, if (ulp_port_db_port_func_id_get(ulp_ctx, dev->data->port_id, &func_id)) { - BNXT_TF_DBG(ERR, "conversion of port to func id failed\n"); + BNXT_DRV_DBG(ERR, "conversion of port to func id failed\n"); goto parse_error; } /* Protect flow creation */ if (bnxt_ulp_cntxt_acquire_fdb_lock(ulp_ctx)) { - BNXT_TF_DBG(ERR, "Flow db lock acquire failed\n"); + BNXT_DRV_DBG(ERR, "Flow db lock acquire failed\n"); goto parse_error; } - ret = ulp_mapper_flow_create(params.ulp_ctx, &mparms); + ret = ulp_mapper_flow_create(params.ulp_ctx, &mparms, + (void *)error); bnxt_ulp_cntxt_release_fdb_lock(ulp_ctx); if (ret) @@ -682,7 +730,9 @@ bnxt_ulp_action_handle_create(struct rte_eth_dev *dev, return (struct rte_flow_action_handle *)((uintptr_t)mparms.shared_hndl); parse_error: - rte_flow_error_set(error, ret, RTE_FLOW_ERROR_TYPE_HANDLE, NULL, + if (error != NULL && + error->type == RTE_FLOW_ERROR_TYPE_NONE) + rte_flow_error_set(error, ret, RTE_FLOW_ERROR_TYPE_HANDLE, NULL, "Failed to create shared action."); return NULL; } @@ -692,7 +742,7 @@ bnxt_ulp_action_handle_destroy(struct rte_eth_dev *dev, struct rte_flow_action_handle *shared_hndl, struct rte_flow_error *error) { - struct bnxt_ulp_mapper_create_parms mparms = { 0 }; + struct bnxt_ulp_mapper_parms mparms = { 0 }; struct bnxt_ulp_shared_act_info *act_info; struct ulp_rte_parser_params params; struct ulp_rte_act_prop *act_prop; @@ -703,14 +753,17 @@ bnxt_ulp_action_handle_destroy(struct rte_eth_dev *dev, uint32_t shared_action_type; uint64_t tmp64; + if (error != NULL) + error->type = RTE_FLOW_ERROR_TYPE_NONE; + ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(dev); if (!ulp_ctx) { - BNXT_TF_DBG(ERR, "ULP context is not initialized\n"); + BNXT_DRV_DBG(ERR, "ULP context is not initialized\n"); goto parse_error; } if (!shared_hndl) { - BNXT_TF_DBG(ERR, "Invalid argument of shared handle\n"); + BNXT_DRV_DBG(ERR, "Invalid argument of shared handle\n"); goto parse_error; } @@ -719,19 +772,19 @@ bnxt_ulp_action_handle_destroy(struct rte_eth_dev *dev, params.ulp_ctx = ulp_ctx; if (bnxt_ulp_cntxt_app_id_get(ulp_ctx, ¶ms.app_id)) { - BNXT_TF_DBG(ERR, "failed to get the app id\n"); + BNXT_DRV_DBG(ERR, "failed to get the app id\n"); goto parse_error; } /* The template will delete the entry if there are no references */ if (bnxt_get_action_handle_type(shared_hndl, &shared_action_type)) { - BNXT_TF_DBG(ERR, "Invalid shared handle\n"); + BNXT_DRV_DBG(ERR, "Invalid shared handle\n"); goto parse_error; } act_info_entries = 0; act_info = bnxt_ulp_shared_act_info_get(&act_info_entries); if (shared_action_type >= act_info_entries || !act_info) { - BNXT_TF_DBG(ERR, "Invalid shared handle\n"); + BNXT_DRV_DBG(ERR, "Invalid shared handle\n"); goto parse_error; } @@ -741,7 +794,7 @@ bnxt_ulp_action_handle_destroy(struct rte_eth_dev *dev, ret = bnxt_get_action_handle_direction(shared_hndl, &dir); if (ret) { - BNXT_TF_DBG(ERR, "Invalid shared handle dir\n"); + BNXT_DRV_DBG(ERR, "Invalid shared handle dir\n"); goto parse_error; } @@ -770,11 +823,12 @@ bnxt_ulp_action_handle_destroy(struct rte_eth_dev *dev, mparms.act_tid = act_tid; if (bnxt_ulp_cntxt_acquire_fdb_lock(ulp_ctx)) { - BNXT_TF_DBG(ERR, "Flow db lock acquire failed\n"); + BNXT_DRV_DBG(ERR, "Flow db lock acquire failed\n"); goto parse_error; } - ret = ulp_mapper_flow_create(ulp_ctx, &mparms); + ret = ulp_mapper_flow_create(ulp_ctx, &mparms, + (void *)error); bnxt_ulp_cntxt_release_fdb_lock(ulp_ctx); if (ret) goto parse_error; @@ -782,7 +836,9 @@ bnxt_ulp_action_handle_destroy(struct rte_eth_dev *dev, return 0; parse_error: - rte_flow_error_set(error, BNXT_TF_RC_ERROR, + if (error != NULL && + error->type == RTE_FLOW_ERROR_TYPE_NONE) + rte_flow_error_set(error, BNXT_TF_RC_ERROR, RTE_FLOW_ERROR_TYPE_HANDLE, NULL, "Failed to destroy shared action."); return -EINVAL; @@ -804,7 +860,7 @@ bnxt_ulp_tunnel_decap_set(struct rte_eth_dev *eth_dev, ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(eth_dev); if (ulp_ctx == NULL) { - BNXT_TF_DBG(ERR, "ULP context is not initialized\n"); + BNXT_DRV_DBG(ERR, "ULP context is not initialized\n"); rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_HANDLE, NULL, "ULP context uninitialized"); @@ -812,7 +868,7 @@ bnxt_ulp_tunnel_decap_set(struct rte_eth_dev *eth_dev, } if (tunnel == NULL) { - BNXT_TF_DBG(ERR, "No tunnel specified\n"); + BNXT_DRV_DBG(ERR, "No tunnel specified\n"); rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ATTR, NULL, "no tunnel specified"); @@ -820,7 +876,7 @@ bnxt_ulp_tunnel_decap_set(struct rte_eth_dev *eth_dev, } if (tunnel->type != RTE_FLOW_ITEM_TYPE_VXLAN) { - BNXT_TF_DBG(ERR, "Tunnel type unsupported\n"); + BNXT_DRV_DBG(ERR, "Tunnel type unsupported\n"); rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ATTR, NULL, "tunnel type unsupported"); @@ -861,7 +917,7 @@ bnxt_ulp_tunnel_match(struct rte_eth_dev *eth_dev, ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(eth_dev); if (ulp_ctx == NULL) { - BNXT_TF_DBG(ERR, "ULP context is not initialized\n"); + BNXT_DRV_DBG(ERR, "ULP context is not initialized\n"); rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_HANDLE, NULL, "ULP context uninitialized"); @@ -869,7 +925,7 @@ bnxt_ulp_tunnel_match(struct rte_eth_dev *eth_dev, } if (tunnel == NULL) { - BNXT_TF_DBG(ERR, "No tunnel specified\n"); + BNXT_DRV_DBG(ERR, "No tunnel specified\n"); rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_HANDLE, NULL, "no tunnel specified"); @@ -877,7 +933,7 @@ bnxt_ulp_tunnel_match(struct rte_eth_dev *eth_dev, } if (tunnel->type != RTE_FLOW_ITEM_TYPE_VXLAN) { - BNXT_TF_DBG(ERR, "Tunnel type unsupported\n"); + BNXT_DRV_DBG(ERR, "Tunnel type unsupported\n"); rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_HANDLE, NULL, "tunnel type unsupported"); @@ -917,14 +973,14 @@ bnxt_ulp_tunnel_decap_release(struct rte_eth_dev *eth_dev, ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(eth_dev); if (ulp_ctx == NULL) { - BNXT_TF_DBG(ERR, "ULP context is not initialized\n"); + BNXT_DRV_DBG(ERR, "ULP context is not initialized\n"); rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_HANDLE, NULL, "ULP context uninitialized"); return -EINVAL; } if (num_actions != BNXT_ULP_TUNNEL_OFFLOAD_NUM_ITEMS) { - BNXT_TF_DBG(ERR, "num actions is invalid\n"); + BNXT_DRV_DBG(ERR, "num actions is invalid\n"); rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ATTR, NULL, "num actions is invalid"); @@ -953,14 +1009,14 @@ bnxt_ulp_tunnel_item_release(struct rte_eth_dev *eth_dev, ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(eth_dev); if (ulp_ctx == NULL) { - BNXT_TF_DBG(ERR, "ULP context is not initialized\n"); + BNXT_DRV_DBG(ERR, "ULP context is not initialized\n"); rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_HANDLE, NULL, "ULP context uninitialized"); return -EINVAL; } if (num_items != BNXT_ULP_TUNNEL_OFFLOAD_NUM_ITEMS) { - BNXT_TF_DBG(ERR, "num items is invalid\n"); + BNXT_DRV_DBG(ERR, "num items is invalid\n"); rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ATTR, NULL, "num items is invalid"); diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp_meter.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp_meter.c index 894f0d9704..61d006fc08 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp_meter.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp_meter.c @@ -27,6 +27,7 @@ #include "tfp.h" #include "bnxt_tf_common.h" +#include "bnxt_ulp_tf.h" #include "ulp_rte_parser.h" #include "ulp_matcher.h" #include "ulp_flow_db.h" @@ -67,8 +68,8 @@ bnxt_meter_global_cfg_update(struct bnxt *bp, tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_DEFAULT); rc = tf_get_global_cfg(tfp, &parms); if (rc) { - BNXT_TF_DBG(ERR, "Failed to get global cfg 0x%x rc:%d\n", - type, rc); + BNXT_DRV_DBG(ERR, "Failed to get global cfg 0x%x rc:%d\n", + type, rc); return rc; } @@ -79,8 +80,8 @@ bnxt_meter_global_cfg_update(struct bnxt *bp, rc = tf_set_global_cfg(tfp, &parms); if (rc) { - BNXT_TF_DBG(ERR, "Failed to set global cfg 0x%x rc:%d\n", - type, rc); + BNXT_DRV_DBG(ERR, "Failed to set global cfg 0x%x rc:%d\n", + type, rc); return rc; } return rc; @@ -107,7 +108,7 @@ bnxt_flow_meter_init(struct bnxt *bp) BNXT_THOR_FMTCR_NUM_MET_MET_1K, 1); if (rc) { - BNXT_TF_DBG(ERR, "Failed to set rx meter configuration\n"); + BNXT_DRV_DBG(ERR, "Failed to set rx meter configuration\n"); goto jump_to_error; } @@ -116,7 +117,7 @@ bnxt_flow_meter_init(struct bnxt *bp) BNXT_THOR_FMTCR_NUM_MET_MET_1K, 1); if (rc) { - BNXT_TF_DBG(ERR, "Failed to set tx meter configuration\n"); + BNXT_DRV_DBG(ERR, "Failed to set tx meter configuration\n"); goto jump_to_error; } @@ -129,7 +130,7 @@ bnxt_flow_meter_init(struct bnxt *bp) BNXT_THOR_FMTCR_INTERVAL_1K, 1); if (rc) { - BNXT_TF_DBG(ERR, "Failed to set rx meter interval\n"); + BNXT_DRV_DBG(ERR, "Failed to set rx meter interval\n"); goto jump_to_error; } @@ -138,12 +139,12 @@ bnxt_flow_meter_init(struct bnxt *bp) BNXT_THOR_FMTCR_INTERVAL_1K, 1); if (rc) { - BNXT_TF_DBG(ERR, "Failed to set tx meter interval\n"); + BNXT_DRV_DBG(ERR, "Failed to set tx meter interval\n"); goto jump_to_error; } bnxt_meter_initialized = 1; - BNXT_TF_DBG(DEBUG, "Bnxt flow meter has been initialized\n"); + BNXT_DRV_DBG(DEBUG, "Bnxt flow meter has been initialized\n"); return rc; jump_to_error: @@ -399,7 +400,7 @@ bnxt_flow_meter_profile_add(struct rte_eth_dev *dev, struct bnxt_ulp_context *ulp_ctx; struct ulp_rte_parser_params params; struct ulp_rte_act_prop *act_prop = ¶ms.act_prop; - struct bnxt_ulp_mapper_create_parms mparms = { 0 }; + struct bnxt_ulp_mapper_parms mparms = { 0 }; uint32_t act_tid; uint16_t func_id; int ret; @@ -446,17 +447,18 @@ bnxt_flow_meter_profile_add(struct rte_eth_dev *dev, if (ulp_port_db_port_func_id_get(ulp_ctx, dev->data->port_id, &func_id)) { - BNXT_TF_DBG(ERR, "conversion of port to func id failed\n"); + BNXT_DRV_DBG(ERR, "conversion of port to func id failed\n"); goto act_error; } /* Protect flow creation */ if (bnxt_ulp_cntxt_acquire_fdb_lock(ulp_ctx)) { - BNXT_TF_DBG(ERR, "Flow db lock acquire failed\n"); + BNXT_DRV_DBG(ERR, "Flow db lock acquire failed\n"); goto act_error; } - ret = ulp_mapper_flow_create(params.ulp_ctx, &mparms); + ret = ulp_mapper_flow_create(params.ulp_ctx, &mparms, + (void *)error); bnxt_ulp_cntxt_release_fdb_lock(ulp_ctx); if (ret) @@ -483,7 +485,7 @@ bnxt_flow_meter_profile_delete(struct rte_eth_dev *dev, struct bnxt_ulp_context *ulp_ctx; struct ulp_rte_parser_params params; struct ulp_rte_act_prop *act_prop = ¶ms.act_prop; - struct bnxt_ulp_mapper_create_parms mparms = { 0 }; + struct bnxt_ulp_mapper_parms mparms = { 0 }; uint32_t act_tid; uint16_t func_id; int ret; @@ -527,24 +529,25 @@ bnxt_flow_meter_profile_delete(struct rte_eth_dev *dev, if (ulp_port_db_port_func_id_get(ulp_ctx, dev->data->port_id, &func_id)) { - BNXT_TF_DBG(ERR, "conversion of port to func id failed\n"); + BNXT_DRV_DBG(ERR, "conversion of port to func id failed\n"); goto parse_error; } /* Protect flow creation */ if (bnxt_ulp_cntxt_acquire_fdb_lock(ulp_ctx)) { - BNXT_TF_DBG(ERR, "Flow db lock acquire failed\n"); + BNXT_DRV_DBG(ERR, "Flow db lock acquire failed\n"); goto parse_error; } - ret = ulp_mapper_flow_create(params.ulp_ctx, &mparms); + ret = ulp_mapper_flow_create(params.ulp_ctx, &mparms, + (void *)error); bnxt_ulp_cntxt_release_fdb_lock(ulp_ctx); if (ret) goto parse_error; - BNXT_TF_DBG(DEBUG, "Bnxt flow meter profile %d deleted\n", - meter_profile_id); + BNXT_DRV_DBG(DEBUG, "Bnxt flow meter profile %d deleted\n", + meter_profile_id); return 0; @@ -566,7 +569,7 @@ bnxt_flow_meter_create(struct rte_eth_dev *dev, uint32_t meter_id, struct bnxt_ulp_context *ulp_ctx; struct ulp_rte_parser_params pparams; struct ulp_rte_act_prop *act_prop = &pparams.act_prop; - struct bnxt_ulp_mapper_create_parms mparms = { 0 }; + struct bnxt_ulp_mapper_parms mparms = { 0 }; uint32_t act_tid; uint16_t func_id; bool meter_en = params->meter_enable ? true : false; @@ -619,23 +622,24 @@ bnxt_flow_meter_create(struct rte_eth_dev *dev, uint32_t meter_id, if (ulp_port_db_port_func_id_get(ulp_ctx, dev->data->port_id, &func_id)) { - BNXT_TF_DBG(ERR, "conversion of port to func id failed\n"); + BNXT_DRV_DBG(ERR, "conversion of port to func id failed\n"); goto parse_error; } /* Protect flow creation */ if (bnxt_ulp_cntxt_acquire_fdb_lock(ulp_ctx)) { - BNXT_TF_DBG(ERR, "Flow db lock acquire failed\n"); + BNXT_DRV_DBG(ERR, "Flow db lock acquire failed\n"); goto parse_error; } - ret = ulp_mapper_flow_create(pparams.ulp_ctx, &mparms); + ret = ulp_mapper_flow_create(pparams.ulp_ctx, &mparms, + (void *)error); bnxt_ulp_cntxt_release_fdb_lock(ulp_ctx); if (ret) goto parse_error; - BNXT_TF_DBG(DEBUG, "Bnxt flow meter %d is created\n", meter_id); + BNXT_DRV_DBG(DEBUG, "Bnxt flow meter %d is created\n", meter_id); return 0; parse_error: @@ -656,7 +660,7 @@ bnxt_flow_meter_destroy(struct rte_eth_dev *dev, struct bnxt_ulp_context *ulp_ctx; struct ulp_rte_parser_params pparams; struct ulp_rte_act_prop *act_prop = &pparams.act_prop; - struct bnxt_ulp_mapper_create_parms mparms = { 0 }; + struct bnxt_ulp_mapper_parms mparms = { 0 }; uint32_t act_tid; uint16_t func_id; int ret; @@ -700,23 +704,24 @@ bnxt_flow_meter_destroy(struct rte_eth_dev *dev, if (ulp_port_db_port_func_id_get(ulp_ctx, dev->data->port_id, &func_id)) { - BNXT_TF_DBG(ERR, "conversion of port to func id failed\n"); + BNXT_DRV_DBG(ERR, "conversion of port to func id failed\n"); goto parse_error; } /* Protect flow creation */ if (bnxt_ulp_cntxt_acquire_fdb_lock(ulp_ctx)) { - BNXT_TF_DBG(ERR, "Flow db lock acquire failed\n"); + BNXT_DRV_DBG(ERR, "Flow db lock acquire failed\n"); goto parse_error; } - ret = ulp_mapper_flow_create(pparams.ulp_ctx, &mparms); + ret = ulp_mapper_flow_create(pparams.ulp_ctx, &mparms, + (void *)error); bnxt_ulp_cntxt_release_fdb_lock(ulp_ctx); if (ret) goto parse_error; - BNXT_TF_DBG(DEBUG, "Bnxt flow meter %d is deleted\n", meter_id); + BNXT_DRV_DBG(DEBUG, "Bnxt flow meter %d is deleted\n", meter_id); return 0; parse_error: @@ -738,7 +743,7 @@ bnxt_flow_meter_enable_set(struct rte_eth_dev *dev, struct bnxt_ulp_context *ulp_ctx; struct ulp_rte_parser_params pparams; struct ulp_rte_act_prop *act_prop = &pparams.act_prop; - struct bnxt_ulp_mapper_create_parms mparms = { 0 }; + struct bnxt_ulp_mapper_parms mparms = { 0 }; uint32_t act_tid; uint16_t func_id; int ret; @@ -784,24 +789,25 @@ bnxt_flow_meter_enable_set(struct rte_eth_dev *dev, if (ulp_port_db_port_func_id_get(ulp_ctx, dev->data->port_id, &func_id)) { - BNXT_TF_DBG(ERR, "conversion of port to func id failed\n"); + BNXT_DRV_DBG(ERR, "conversion of port to func id failed\n"); goto parse_error; } /* Protect flow creation */ if (bnxt_ulp_cntxt_acquire_fdb_lock(ulp_ctx)) { - BNXT_TF_DBG(ERR, "Flow db lock acquire failed\n"); + BNXT_DRV_DBG(ERR, "Flow db lock acquire failed\n"); goto parse_error; } - ret = ulp_mapper_flow_create(pparams.ulp_ctx, &mparms); + ret = ulp_mapper_flow_create(pparams.ulp_ctx, &mparms, + (void *)error); bnxt_ulp_cntxt_release_fdb_lock(ulp_ctx); if (ret) goto parse_error; - BNXT_TF_DBG(DEBUG, "Bnxt flow meter %d is %s\n", - meter_id, val ? "enabled" : "disabled"); + BNXT_DRV_DBG(DEBUG, "Bnxt flow meter %d is %s\n", + meter_id, val ? "enabled" : "disabled"); return 0; parse_error: diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp_tf.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp_tf.c new file mode 100644 index 0000000000..1908cd1854 --- /dev/null +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp_tf.c @@ -0,0 +1,1513 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2019-2021 Broadcom + * All rights reserved. + */ + +#include <rte_log.h> +#include <rte_malloc.h> +#include <rte_flow.h> +#include <rte_flow_driver.h> +#include <rte_tailq.h> +#include <rte_spinlock.h> + +#include "bnxt.h" +#include "bnxt_ulp.h" +#include "bnxt_ulp_tf.h" +#include "bnxt_tf_common.h" +#include "hsi_struct_def_dpdk.h" +#include "tf_core.h" +#include "tf_ext_flow_handle.h" + +#include "ulp_template_db_enum.h" +#include "ulp_template_struct.h" +#include "ulp_mark_mgr.h" +#include "ulp_fc_mgr.h" +#include "ulp_flow_db.h" +#include "ulp_mapper.h" +#include "ulp_matcher.h" +#include "ulp_port_db.h" +#include "ulp_tun.h" +#include "ulp_ha_mgr.h" +#include "bnxt_tf_pmd_shim.h" +#include "ulp_template_db_tbl.h" + +/* Function to set the tfp session details from the ulp context. */ +int32_t +bnxt_ulp_cntxt_tfp_set(struct bnxt_ulp_context *ulp, + enum bnxt_ulp_session_type s_type, + struct tf *tfp) +{ + uint32_t idx = 0; + enum bnxt_ulp_tfo_type tfo_type = BNXT_ULP_TFO_TYPE_TF; + + if (ulp == NULL) + return -EINVAL; + + if (ULP_MULTI_SHARED_IS_SUPPORTED(ulp)) { + if (s_type & BNXT_ULP_SESSION_TYPE_SHARED) + idx = 1; + else if (s_type & BNXT_ULP_SESSION_TYPE_SHARED_WC) + idx = 2; + + } else { + if ((s_type & BNXT_ULP_SESSION_TYPE_SHARED) || + (s_type & BNXT_ULP_SESSION_TYPE_SHARED_WC)) + idx = 1; + } + + ulp->g_tfp[idx] = tfp; + + if (tfp == NULL) { + uint32_t i = 0; + while (i < BNXT_ULP_SESSION_MAX && ulp->g_tfp[i] == NULL) + i++; + if (i == BNXT_ULP_SESSION_MAX) + ulp->tfo_type = BNXT_ULP_TFO_TYPE_INVALID; + } else { + ulp->tfo_type = tfo_type; + } + return 0; +} + +/* Function to get the tfp session details from the ulp context. */ +struct tf * +bnxt_ulp_cntxt_tfp_get(struct bnxt_ulp_context *ulp, + enum bnxt_ulp_session_type s_type) +{ + uint32_t idx = 0; + + if (ulp == NULL) + return NULL; + + if (ulp->tfo_type != BNXT_ULP_TFO_TYPE_TF) { + BNXT_DRV_DBG(ERR, "Wrong tf type %d != %d\n", + ulp->tfo_type, BNXT_ULP_TFO_TYPE_TF); + return NULL; + } + + if (ULP_MULTI_SHARED_IS_SUPPORTED(ulp)) { + if (s_type & BNXT_ULP_SESSION_TYPE_SHARED) + idx = 1; + else if (s_type & BNXT_ULP_SESSION_TYPE_SHARED_WC) + idx = 2; + } else { + if ((s_type & BNXT_ULP_SESSION_TYPE_SHARED) || + (s_type & BNXT_ULP_SESSION_TYPE_SHARED_WC)) + idx = 1; + } + return (struct tf *)ulp->g_tfp[idx]; +} + +struct tf *bnxt_get_tfp_session(struct bnxt *bp, enum bnxt_session_type type) +{ + return (type >= BNXT_SESSION_TYPE_LAST) ? + &bp->tfp[BNXT_SESSION_TYPE_REGULAR] : &bp->tfp[type]; +} + +struct tf * +bnxt_ulp_bp_tfp_get(struct bnxt *bp, enum bnxt_ulp_session_type type) +{ + enum bnxt_session_type btype; + + if (type & BNXT_ULP_SESSION_TYPE_SHARED) + btype = BNXT_SESSION_TYPE_SHARED_COMMON; + else if (type & BNXT_ULP_SESSION_TYPE_SHARED_WC) + btype = BNXT_SESSION_TYPE_SHARED_WC; + else + btype = BNXT_SESSION_TYPE_REGULAR; + + return bnxt_get_tfp_session(bp, btype); +} + +static int32_t +ulp_tf_named_resources_calc(struct bnxt_ulp_context *ulp_ctx, + struct bnxt_ulp_glb_resource_info *info, + uint32_t num, + enum bnxt_ulp_session_type stype, + struct tf_session_resources *res) +{ + uint32_t dev_id = BNXT_ULP_DEVICE_ID_LAST, res_type, i; + enum tf_dir dir; + uint8_t app_id; + int32_t rc = 0; + + if (ulp_ctx == NULL || info == NULL || res == NULL || num == 0) { + BNXT_DRV_DBG(ERR, "Invalid parms to named resources calc.\n"); + return -EINVAL; + } + + rc = bnxt_ulp_cntxt_app_id_get(ulp_ctx, &app_id); + if (rc) { + BNXT_DRV_DBG(ERR, "Unable to get the app id from ulp.\n"); + return -EINVAL; + } + + rc = bnxt_ulp_cntxt_dev_id_get(ulp_ctx, &dev_id); + if (rc) { + BNXT_DRV_DBG(ERR, "Unable to get the dev id from ulp.\n"); + return -EINVAL; + } + + for (i = 0; i < num; i++) { + if (dev_id != info[i].device_id || app_id != info[i].app_id) + continue; + /* check to see if the session type matches only then include */ + if ((stype || info[i].session_type) && + !(info[i].session_type & stype)) + continue; + + dir = info[i].direction; + res_type = info[i].resource_type; + + switch (info[i].resource_func) { + case BNXT_ULP_RESOURCE_FUNC_IDENTIFIER: + res->ident_cnt[dir].cnt[res_type]++; + break; + case BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE: + res->tbl_cnt[dir].cnt[res_type]++; + break; + case BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE: + res->tcam_cnt[dir].cnt[res_type]++; + break; + case BNXT_ULP_RESOURCE_FUNC_EM_TABLE: + res->em_cnt[dir].cnt[res_type]++; + break; + default: + BNXT_DRV_DBG(ERR, "Unknown resource func (0x%x)\n,", + info[i].resource_func); + continue; + } + } + + return 0; +} + +static int32_t +ulp_tf_unnamed_resources_calc(struct bnxt_ulp_context *ulp_ctx, + struct bnxt_ulp_resource_resv_info *info, + uint32_t num, + enum bnxt_ulp_session_type stype, + struct tf_session_resources *res) +{ + uint32_t dev_id, res_type, i; + enum tf_dir dir; + uint8_t app_id; + int32_t rc = 0; + + if (ulp_ctx == NULL || res == NULL || info == NULL || num == 0) { + BNXT_DRV_DBG(ERR, "Invalid arguments to get resources.\n"); + return -EINVAL; + } + + rc = bnxt_ulp_cntxt_app_id_get(ulp_ctx, &app_id); + if (rc) { + BNXT_DRV_DBG(ERR, "Unable to get the app id from ulp.\n"); + return -EINVAL; + } + + rc = bnxt_ulp_cntxt_dev_id_get(ulp_ctx, &dev_id); + if (rc) { + BNXT_DRV_DBG(ERR, "Unable to get the dev id from ulp.\n"); + return -EINVAL; + } + + for (i = 0; i < num; i++) { + if (app_id != info[i].app_id || dev_id != info[i].device_id) + continue; + + /* check to see if the session type matches only then include */ + if ((stype || info[i].session_type) && + !(info[i].session_type & stype)) + continue; + + dir = info[i].direction; + res_type = info[i].resource_type; + + switch (info[i].resource_func) { + case BNXT_ULP_RESOURCE_FUNC_IDENTIFIER: + res->ident_cnt[dir].cnt[res_type] = info[i].count; + break; + case BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE: + res->tbl_cnt[dir].cnt[res_type] = info[i].count; + break; + case BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE: + res->tcam_cnt[dir].cnt[res_type] = info[i].count; + break; + case BNXT_ULP_RESOURCE_FUNC_EM_TABLE: + res->em_cnt[dir].cnt[res_type] = info[i].count; + break; + default: + break; + } + } + return 0; +} + +static int32_t +ulp_tf_resources_get(struct bnxt_ulp_context *ulp_ctx, + enum bnxt_ulp_session_type stype, + struct tf_session_resources *res) +{ + struct bnxt_ulp_resource_resv_info *unnamed = NULL; + uint32_t unum; + int32_t rc = 0; + + if (ulp_ctx == NULL || res == NULL) { + BNXT_DRV_DBG(ERR, "Invalid arguments to get resources.\n"); + return -EINVAL; + } + + unnamed = bnxt_ulp_resource_resv_list_get(&unum); + if (unnamed == NULL) { + BNXT_DRV_DBG(ERR, "Unable to get resource resv list.\n"); + return -EINVAL; + } + + rc = ulp_tf_unnamed_resources_calc(ulp_ctx, unnamed, unum, stype, res); + if (rc) + BNXT_DRV_DBG(ERR, "Unable to calc resources for session.\n"); + + return rc; +} + +static int32_t +ulp_tf_shared_session_resources_get(struct bnxt_ulp_context *ulp_ctx, + enum bnxt_ulp_session_type stype, + struct tf_session_resources *res) +{ + struct bnxt_ulp_resource_resv_info *unnamed; + struct bnxt_ulp_glb_resource_info *named; + uint32_t unum = 0, nnum = 0; + int32_t rc; + + if (ulp_ctx == NULL || res == NULL) { + BNXT_DRV_DBG(ERR, "Invalid arguments to get resources.\n"); + return -EINVAL; + } + + /* Make sure the resources are zero before accumulating. */ + memset(res, 0, sizeof(struct tf_session_resources)); + + if (bnxt_ulp_cntxt_ha_enabled(ulp_ctx) && + stype == BNXT_ULP_SESSION_TYPE_SHARED) + stype = ulp_ctx->cfg_data->hu_session_type; + + /* + * Shared resources are comprised of both named and unnamed resources. + * First get the unnamed counts, and then add the named to the result. + */ + /* Get the baseline counts */ + unnamed = bnxt_ulp_app_resource_resv_list_get(&unum); + if (unum) { + rc = ulp_tf_unnamed_resources_calc(ulp_ctx, unnamed, + unum, stype, res); + if (rc) { + BNXT_DRV_DBG(ERR, + "Unable to calc resources for shared session.\n"); + return -EINVAL; + } + } + + /* Get the named list and add the totals */ + named = bnxt_ulp_app_glb_resource_info_list_get(&nnum); + /* No need to calc resources, none to calculate */ + if (!nnum) + return 0; + + rc = ulp_tf_named_resources_calc(ulp_ctx, named, nnum, stype, res); + if (rc) + BNXT_DRV_DBG(ERR, "Unable to calc named resources\n"); + + return rc; +} + +/* Function to set the hot upgrade support into the context */ +static int +ulp_tf_multi_shared_session_support_set(struct bnxt *bp, + enum bnxt_ulp_device_id devid, + uint32_t fw_hu_update) +{ + struct bnxt_ulp_context *ulp_ctx = bp->ulp_ctx; + struct tf_get_version_parms v_params = { 0 }; + struct tf *tfp; + int32_t rc = 0; + int32_t new_fw = 0; + + v_params.device_type = bnxt_ulp_cntxt_convert_dev_id(devid); + v_params.bp = bp; + + tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_DEFAULT); + rc = tf_get_version(tfp, &v_params); + if (rc) { + BNXT_DRV_DBG(ERR, "Unable to get tf version.\n"); + return rc; + } + + if (v_params.major == 1 && v_params.minor == 0 && + v_params.update == 1) { + new_fw = 1; + } + /* if the version update is greater than 0 then set support for + * multiple version + */ + if (new_fw) { + ulp_ctx->cfg_data->ulp_flags |= BNXT_ULP_MULTI_SHARED_SUPPORT; + ulp_ctx->cfg_data->hu_session_type = + BNXT_ULP_SESSION_TYPE_SHARED; + } + if (!new_fw && fw_hu_update) { + ulp_ctx->cfg_data->ulp_flags &= ~BNXT_ULP_HIGH_AVAIL_ENABLED; + ulp_ctx->cfg_data->hu_session_type = + BNXT_ULP_SESSION_TYPE_SHARED | + BNXT_ULP_SESSION_TYPE_SHARED_OWC; + } + + if (!new_fw && !fw_hu_update) { + ulp_ctx->cfg_data->hu_session_type = + BNXT_ULP_SESSION_TYPE_SHARED | + BNXT_ULP_SESSION_TYPE_SHARED_OWC; + } + + return rc; +} + +static int32_t +ulp_tf_cntxt_app_caps_init(struct bnxt *bp, + uint8_t app_id, uint32_t dev_id) +{ + struct bnxt_ulp_app_capabilities_info *info; + uint32_t num = 0, fw = 0; + uint16_t i; + bool found = false; + struct bnxt_ulp_context *ulp_ctx = bp->ulp_ctx; + + if (ULP_APP_DEV_UNSUPPORTED_ENABLED(ulp_ctx->cfg_data->ulp_flags)) { + BNXT_DRV_DBG(ERR, "APP ID %d, Device ID: 0x%x not supported.\n", + app_id, dev_id); + return -EINVAL; + } + + info = bnxt_ulp_app_cap_list_get(&num); + if (!info || !num) { + BNXT_DRV_DBG(ERR, "Failed to get app capabilities.\n"); + return -EINVAL; + } + + for (i = 0; i < num; i++) { + if (info[i].app_id != app_id || info[i].device_id != dev_id) + continue; + found = true; + if (info[i].flags & BNXT_ULP_APP_CAP_SHARED_EN) + ulp_ctx->cfg_data->ulp_flags |= + BNXT_ULP_SHARED_SESSION_ENABLED; + if (info[i].flags & BNXT_ULP_APP_CAP_HOT_UPGRADE_EN) + ulp_ctx->cfg_data->ulp_flags |= + BNXT_ULP_HIGH_AVAIL_ENABLED; + if (info[i].flags & BNXT_ULP_APP_CAP_UNICAST_ONLY) + ulp_ctx->cfg_data->ulp_flags |= + BNXT_ULP_APP_UNICAST_ONLY; + if (info[i].flags & BNXT_ULP_APP_CAP_IP_TOS_PROTO_SUPPORT) + ulp_ctx->cfg_data->ulp_flags |= + BNXT_ULP_APP_TOS_PROTO_SUPPORT; + if (info[i].flags & BNXT_ULP_APP_CAP_BC_MC_SUPPORT) + ulp_ctx->cfg_data->ulp_flags |= + BNXT_ULP_APP_BC_MC_SUPPORT; + if (info[i].flags & BNXT_ULP_APP_CAP_SOCKET_DIRECT) { + /* Enable socket direction only if MR is enabled in fw*/ + if (BNXT_MULTIROOT_EN(bp)) { + ulp_ctx->cfg_data->ulp_flags |= + BNXT_ULP_APP_SOCKET_DIRECT; + BNXT_DRV_DBG(INFO, + "Socket Direct feature is enabled\n"); + } + } + if (info[i].flags & BNXT_ULP_APP_CAP_HA_DYNAMIC) { + /* Read the environment variable to determine hot up */ + if (!bnxt_pmd_get_hot_up_config()) { + ulp_ctx->cfg_data->ulp_flags |= + BNXT_ULP_APP_HA_DYNAMIC; + /* reset Hot upgrade, dynamically disabled */ + ulp_ctx->cfg_data->ulp_flags &= + ~BNXT_ULP_HIGH_AVAIL_ENABLED; + ulp_ctx->cfg_data->def_session_type = + BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA; + BNXT_DRV_DBG(INFO, "Hot upgrade disabled.\n"); + } + } + if (info[i].flags & BNXT_ULP_APP_CAP_SRV6) + ulp_ctx->cfg_data->ulp_flags |= + BNXT_ULP_APP_SRV6; + + if (info[i].flags & BNXT_ULP_APP_CAP_L2_ETYPE) + ulp_ctx->cfg_data->ulp_flags |= + BNXT_ULP_APP_L2_ETYPE; + + if (info[i].flags & BNXT_ULP_APP_CAP_CUST_VXLAN) + ulp_ctx->cfg_data->ulp_flags |= + BNXT_ULP_CUST_VXLAN_SUPPORT; + + bnxt_ulp_cntxt_vxlan_ip_port_set(ulp_ctx, info[i].vxlan_ip_port); + bnxt_ulp_cntxt_vxlan_port_set(ulp_ctx, info[i].vxlan_port); + bnxt_ulp_cntxt_ecpri_udp_port_set(ulp_ctx, info[i].ecpri_udp_port); + bnxt_ulp_vxlan_gpe_next_proto_set(ulp_ctx, info[i].tunnel_next_proto); + bnxt_ulp_num_key_recipes_set(ulp_ctx, + info[i].num_key_recipes_per_dir); + + /* set the shared session support from firmware */ + fw = info[i].upgrade_fw_update; + if (ULP_HIGH_AVAIL_IS_ENABLED(ulp_ctx->cfg_data->ulp_flags) && + ulp_tf_multi_shared_session_support_set(bp, dev_id, fw)) { + BNXT_DRV_DBG(ERR, + "Unable to get shared session support\n"); + return -EINVAL; + } + bnxt_ulp_cntxt_ha_reg_set(ulp_ctx, info[i].ha_reg_state, + info[i].ha_reg_cnt); + ulp_ctx->cfg_data->ha_pool_id = info[i].ha_pool_id; + ulp_ctx->cfg_data->default_priority = info[i].default_priority; + } + if (!found) { + BNXT_DRV_DBG(ERR, "APP ID %d, Device ID: 0x%x not supported.\n", + app_id, dev_id); + ulp_ctx->cfg_data->ulp_flags |= BNXT_ULP_APP_DEV_UNSUPPORTED; + return -EINVAL; + } + + return 0; +} + +static inline uint32_t +ulp_tf_session_idx_get(enum bnxt_ulp_session_type session_type) { + if (session_type & BNXT_ULP_SESSION_TYPE_SHARED) + return 1; + else if (session_type & BNXT_ULP_SESSION_TYPE_SHARED_WC) + return 2; + return 0; +} + +/* Function to set the tfp session details in session */ +static int32_t +ulp_tf_session_tfp_set(struct bnxt_ulp_session_state *session, + enum bnxt_ulp_session_type session_type, + struct tf *tfp) +{ + uint32_t idx = ulp_tf_session_idx_get(session_type); + struct tf *local_tfp; + int32_t rc = 0; + + if (!session->session_opened[idx]) { + local_tfp = rte_zmalloc("bnxt_ulp_session_tfp", + sizeof(struct tf), 0); + + if (local_tfp == NULL) { + BNXT_DRV_DBG(DEBUG, "Failed to alloc session tfp\n"); + return -ENOMEM; + } + local_tfp->session = tfp->session; + session->g_tfp[idx] = local_tfp; + session->session_opened[idx] = 1; + } + return rc; +} + +/* Function to get the tfp session details in session */ +static struct tf_session_info * +ulp_tf_session_tfp_get(struct bnxt_ulp_session_state *session, + enum bnxt_ulp_session_type session_type) +{ + uint32_t idx = ulp_tf_session_idx_get(session_type); + struct tf *local_tfp = session->g_tfp[idx]; + + if (session->session_opened[idx]) + return local_tfp->session; + return NULL; +} + +static uint32_t +ulp_tf_session_is_open(struct bnxt_ulp_session_state *session, + enum bnxt_ulp_session_type session_type) +{ + uint32_t idx = ulp_tf_session_idx_get(session_type); + + return session->session_opened[idx]; +} + +/* Function to reset the tfp session details in session */ +static void +ulp_tf_session_tfp_reset(struct bnxt_ulp_session_state *session, + enum bnxt_ulp_session_type session_type) +{ + uint32_t idx = ulp_tf_session_idx_get(session_type); + + if (session->session_opened[idx]) { + session->session_opened[idx] = 0; + rte_free(session->g_tfp[idx]); + session->g_tfp[idx] = NULL; + } +} + +static void +ulp_tf_ctx_shared_session_close(struct bnxt *bp, + enum bnxt_ulp_session_type session_type, + struct bnxt_ulp_session_state *session) +{ + struct tf *tfp; + int32_t rc; + + tfp = bnxt_ulp_cntxt_tfp_get(bp->ulp_ctx, session_type); + if (!tfp) { + /* + * Log it under debug since this is likely a case of the + * shared session not being created. For example, a failed + * initialization. + */ + BNXT_DRV_DBG(DEBUG, "Failed to get shared tfp on close.\n"); + return; + } + rc = tf_close_session(tfp); + if (rc) + BNXT_DRV_DBG(ERR, "Failed to close the shared session rc=%d.\n", + rc); + (void)bnxt_ulp_cntxt_tfp_set(bp->ulp_ctx, session_type, NULL); + ulp_tf_session_tfp_reset(session, session_type); +} + +static int32_t +ulp_tf_ctx_shared_session_open(struct bnxt *bp, + enum bnxt_ulp_session_type session_type, + struct bnxt_ulp_session_state *session) +{ + struct rte_eth_dev *ethdev = bp->eth_dev; + struct tf_session_resources *resources; + struct tf_open_session_parms parms; + size_t nb; + uint32_t ulp_dev_id = BNXT_ULP_DEVICE_ID_LAST; + int32_t rc = 0; + uint8_t app_id; + struct tf *tfp; + uint8_t pool_id; + + memset(&parms, 0, sizeof(parms)); + rc = rte_eth_dev_get_name_by_port(ethdev->data->port_id, + parms.ctrl_chan_name); + if (rc) { + BNXT_DRV_DBG(ERR, "Invalid port %d, rc = %d\n", + ethdev->data->port_id, rc); + return rc; + } + + /* On multi-host system, adjust ctrl_chan_name to avoid confliction */ + if (BNXT_MH(bp)) { + rc = ulp_ctx_mh_get_session_name(bp, &parms); + if (rc) + return rc; + } + + resources = &parms.resources; + + /* + * Need to account for size of ctrl_chan_name and 1 extra for Null + * terminator + */ + nb = sizeof(parms.ctrl_chan_name) - strlen(parms.ctrl_chan_name) - 1; + + /* + * Build the ctrl_chan_name with shared token. + * When HA is enabled, the WC TCAM needs extra management by the core, + * so add the wc_tcam string to the control channel. + */ + pool_id = bp->ulp_ctx->cfg_data->ha_pool_id; + if (!bnxt_ulp_cntxt_multi_shared_session_enabled(bp->ulp_ctx)) { + if (bnxt_ulp_cntxt_ha_enabled(bp->ulp_ctx)) + strncat(parms.ctrl_chan_name, "-tf_shared-wc_tcam", nb); + else + strncat(parms.ctrl_chan_name, "-tf_shared", nb); + } else if (bnxt_ulp_cntxt_multi_shared_session_enabled(bp->ulp_ctx)) { + if (session_type == BNXT_ULP_SESSION_TYPE_SHARED) { + strncat(parms.ctrl_chan_name, "-tf_shared", nb); + } else if (session_type == BNXT_ULP_SESSION_TYPE_SHARED_WC) { + char session_pool_name[64]; + + sprintf(session_pool_name, "-tf_shared-pool%d", + pool_id); + + if (nb >= strlen(session_pool_name)) { + strncat(parms.ctrl_chan_name, session_pool_name, nb); + } else { + BNXT_DRV_DBG(ERR, "No space left for session_name\n"); + return -EINVAL; + } + } + } + + rc = ulp_tf_shared_session_resources_get(bp->ulp_ctx, session_type, + resources); + if (rc) + return rc; + + rc = bnxt_ulp_cntxt_app_id_get(bp->ulp_ctx, &app_id); + if (rc) { + BNXT_DRV_DBG(ERR, "Unable to get the app id from ulp.\n"); + return -EINVAL; + } + + rc = bnxt_ulp_cntxt_dev_id_get(bp->ulp_ctx, &ulp_dev_id); + if (rc) { + BNXT_DRV_DBG(ERR, "Unable to get device id from ulp.\n"); + return rc; + } + + tfp = bnxt_ulp_bp_tfp_get(bp, session_type); + parms.device_type = bnxt_ulp_cntxt_convert_dev_id(ulp_dev_id); + parms.bp = bp; + + /* + * Open the session here, but the collect the resources during the + * mapper initialization. + */ + rc = tf_open_session(tfp, &parms); + if (rc) + return rc; + + if (parms.shared_session_creator) + BNXT_DRV_DBG(DEBUG, "Shared session creator.\n"); + else + BNXT_DRV_DBG(DEBUG, "Shared session attached.\n"); + + /* Save the shared session in global data */ + rc = ulp_tf_session_tfp_set(session, session_type, tfp); + if (rc) { + BNXT_DRV_DBG(ERR, "Failed to add shared tfp to session\n"); + return rc; + } + + rc = bnxt_ulp_cntxt_tfp_set(bp->ulp_ctx, session_type, tfp); + if (rc) { + BNXT_DRV_DBG(ERR, "Failed to add shared tfp to ulp (%d)\n", rc); + return rc; + } + + return rc; +} + +static int32_t +ulp_tf_ctx_shared_session_attach(struct bnxt *bp, + struct bnxt_ulp_session_state *ses) +{ + enum bnxt_ulp_session_type type; + struct tf *tfp; + int32_t rc = 0; + + /* Simply return success if shared session not enabled */ + if (bnxt_ulp_cntxt_shared_session_enabled(bp->ulp_ctx)) { + type = BNXT_ULP_SESSION_TYPE_SHARED; + tfp = bnxt_ulp_bp_tfp_get(bp, type); + tfp->session = ulp_tf_session_tfp_get(ses, type); + rc = ulp_tf_ctx_shared_session_open(bp, type, ses); + } + + if (bnxt_ulp_cntxt_multi_shared_session_enabled(bp->ulp_ctx)) { + type = BNXT_ULP_SESSION_TYPE_SHARED_WC; + tfp = bnxt_ulp_bp_tfp_get(bp, type); + tfp->session = ulp_tf_session_tfp_get(ses, type); + rc = ulp_tf_ctx_shared_session_open(bp, type, ses); + } + + if (!rc) + bnxt_ulp_cntxt_num_shared_clients_set(bp->ulp_ctx, true); + + return rc; +} + +static void +ulp_tf_ctx_shared_session_detach(struct bnxt *bp) +{ + struct tf *tfp; + + if (bnxt_ulp_cntxt_shared_session_enabled(bp->ulp_ctx)) { + tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_SHARED); + if (tfp->session) { + tf_close_session(tfp); + tfp->session = NULL; + } + } + if (bnxt_ulp_cntxt_multi_shared_session_enabled(bp->ulp_ctx)) { + tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_SHARED_WC); + if (tfp->session) { + tf_close_session(tfp); + tfp->session = NULL; + } + } + bnxt_ulp_cntxt_num_shared_clients_set(bp->ulp_ctx, false); +} + +/* + * Initialize an ULP session. + * An ULP session will contain all the resources needed to support rte flow + * offloads. A session is initialized as part of rte_eth_device start. + * A single vswitch instance can have multiple uplinks which means + * rte_eth_device start will be called for each of these devices. + * ULP session manager will make sure that a single ULP session is only + * initialized once. Apart from this, it also initializes MARK database, + * EEM table & flow database. ULP session manager also manages a list of + * all opened ULP sessions. + */ +static int32_t +ulp_tf_ctx_session_open(struct bnxt *bp, + struct bnxt_ulp_session_state *session) +{ + struct rte_eth_dev *ethdev = bp->eth_dev; + int32_t rc = 0; + struct tf_open_session_parms params; + struct tf_session_resources *resources; + uint32_t ulp_dev_id = BNXT_ULP_DEVICE_ID_LAST; + uint8_t app_id; + struct tf *tfp; + + memset(¶ms, 0, sizeof(params)); + + rc = rte_eth_dev_get_name_by_port(ethdev->data->port_id, + params.ctrl_chan_name); + if (rc) { + BNXT_DRV_DBG(ERR, "Invalid port %d, rc = %d\n", + ethdev->data->port_id, rc); + return rc; + } + + /* On multi-host system, adjust ctrl_chan_name to avoid confliction */ + if (BNXT_MH(bp)) { + rc = ulp_ctx_mh_get_session_name(bp, ¶ms); + if (rc) + return rc; + } + + rc = bnxt_ulp_cntxt_app_id_get(bp->ulp_ctx, &app_id); + if (rc) { + BNXT_DRV_DBG(ERR, "Unable to get the app id from ulp.\n"); + return -EINVAL; + } + + rc = bnxt_ulp_cntxt_dev_id_get(bp->ulp_ctx, &ulp_dev_id); + if (rc) { + BNXT_DRV_DBG(ERR, "Unable to get device id from ulp.\n"); + return rc; + } + + params.device_type = bnxt_ulp_cntxt_convert_dev_id(ulp_dev_id); + resources = ¶ms.resources; + rc = ulp_tf_resources_get(bp->ulp_ctx, + BNXT_ULP_SESSION_TYPE_DEFAULT, + resources); + if (rc) + return rc; + + params.bp = bp; + + tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_DEFAULT); + rc = tf_open_session(tfp, ¶ms); + if (rc) { + BNXT_DRV_DBG(ERR, "Failed to open TF session - %s, rc = %d\n", + params.ctrl_chan_name, rc); + return -EINVAL; + } + rc = ulp_tf_session_tfp_set(session, BNXT_ULP_SESSION_TYPE_DEFAULT, tfp); + if (rc) { + BNXT_DRV_DBG(ERR, "Failed to set TF session - %s, rc = %d\n", + params.ctrl_chan_name, rc); + return -EINVAL; + } + return rc; +} + +/* + * Close the ULP session. + * It takes the ulp context pointer. + */ +static void +ulp_tf_ctx_session_close(struct bnxt *bp, + struct bnxt_ulp_session_state *session) +{ + struct tf *tfp; + + /* close the session in the hardware */ + if (ulp_tf_session_is_open(session, BNXT_ULP_SESSION_TYPE_DEFAULT)) { + tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_DEFAULT); + tf_close_session(tfp); + } + ulp_tf_session_tfp_reset(session, BNXT_ULP_SESSION_TYPE_DEFAULT); +} + +static void +ulp_tf_init_tbl_scope_parms(struct bnxt *bp, + struct tf_alloc_tbl_scope_parms *params) +{ + struct bnxt_ulp_device_params *dparms; + uint32_t dev_id; + int rc; + + rc = bnxt_ulp_cntxt_dev_id_get(bp->ulp_ctx, &dev_id); + if (rc) + /* TBD: For now, just use default. */ + dparms = 0; + else + dparms = bnxt_ulp_device_params_get(dev_id); + + /* + * Set the flush timer for EEM entries. The value is in 100ms intervals, + * so 100 is 10s. + */ + params->hw_flow_cache_flush_timer = 100; + + if (!dparms) { + params->rx_max_key_sz_in_bits = BNXT_ULP_DFLT_RX_MAX_KEY; + params->rx_max_action_entry_sz_in_bits = + BNXT_ULP_DFLT_RX_MAX_ACTN_ENTRY; + params->rx_mem_size_in_mb = BNXT_ULP_DFLT_RX_MEM; + params->rx_num_flows_in_k = BNXT_ULP_RX_NUM_FLOWS; + + params->tx_max_key_sz_in_bits = BNXT_ULP_DFLT_TX_MAX_KEY; + params->tx_max_action_entry_sz_in_bits = + BNXT_ULP_DFLT_TX_MAX_ACTN_ENTRY; + params->tx_mem_size_in_mb = BNXT_ULP_DFLT_TX_MEM; + params->tx_num_flows_in_k = BNXT_ULP_TX_NUM_FLOWS; + } else { + params->rx_max_key_sz_in_bits = BNXT_ULP_DFLT_RX_MAX_KEY; + params->rx_max_action_entry_sz_in_bits = + BNXT_ULP_DFLT_RX_MAX_ACTN_ENTRY; + params->rx_mem_size_in_mb = BNXT_ULP_DFLT_RX_MEM; + params->rx_num_flows_in_k = + dparms->ext_flow_db_num_entries / 1024; + + params->tx_max_key_sz_in_bits = BNXT_ULP_DFLT_TX_MAX_KEY; + params->tx_max_action_entry_sz_in_bits = + BNXT_ULP_DFLT_TX_MAX_ACTN_ENTRY; + params->tx_mem_size_in_mb = BNXT_ULP_DFLT_TX_MEM; + params->tx_num_flows_in_k = + dparms->ext_flow_db_num_entries / 1024; + } + BNXT_DRV_DBG(INFO, "Table Scope initialized with %uK flows.\n", + params->rx_num_flows_in_k); +} + +/* Initialize Extended Exact Match host memory. */ +static int32_t +ulp_tf_eem_tbl_scope_init(struct bnxt *bp) +{ + struct tf_alloc_tbl_scope_parms params = {0}; + struct bnxt_ulp_device_params *dparms; + enum bnxt_ulp_flow_mem_type mtype; + uint32_t dev_id; + struct tf *tfp; + int rc; + + /* Get the dev specific number of flows that needed to be supported. */ + if (bnxt_ulp_cntxt_dev_id_get(bp->ulp_ctx, &dev_id)) { + BNXT_DRV_DBG(ERR, "Invalid device id\n"); + return -EINVAL; + } + + dparms = bnxt_ulp_device_params_get(dev_id); + if (!dparms) { + BNXT_DRV_DBG(ERR, "could not fetch the device params\n"); + return -ENODEV; + } + + if (bnxt_ulp_cntxt_mem_type_get(bp->ulp_ctx, &mtype)) + return -EINVAL; + if (mtype != BNXT_ULP_FLOW_MEM_TYPE_EXT) { + BNXT_DRV_DBG(INFO, "Table Scope alloc is not required\n"); + return 0; + } + + ulp_tf_init_tbl_scope_parms(bp, ¶ms); + tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_DEFAULT); + rc = tf_alloc_tbl_scope(tfp, ¶ms); + if (rc) { + BNXT_DRV_DBG(ERR, + "Unable to allocate eem table scope rc = %d\n", + rc); + return rc; + } + +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG + BNXT_DRV_DBG(DEBUG, "TableScope=0x%0x %d\n", + params.tbl_scope_id, + params.tbl_scope_id); +#endif + + rc = bnxt_ulp_cntxt_tbl_scope_id_set(bp->ulp_ctx, params.tbl_scope_id); + if (rc) { + BNXT_DRV_DBG(ERR, "Unable to set table scope id\n"); + return rc; + } + + return 0; +} + +/* Free Extended Exact Match host memory */ +static int32_t +ulp_tf_eem_tbl_scope_deinit(struct bnxt *bp, struct bnxt_ulp_context *ulp_ctx) +{ + struct tf_free_tbl_scope_parms params = {0}; + struct tf *tfp; + int32_t rc = 0; + struct bnxt_ulp_device_params *dparms; + enum bnxt_ulp_flow_mem_type mtype; + uint32_t dev_id; + + if (!ulp_ctx || !ulp_ctx->cfg_data) + return -EINVAL; + + tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx, BNXT_ULP_SESSION_TYPE_DEFAULT); + if (!tfp) { + BNXT_DRV_DBG(ERR, "Failed to get the truflow pointer\n"); + return -EINVAL; + } + + /* Get the dev specific number of flows that needed to be supported. */ + if (bnxt_ulp_cntxt_dev_id_get(bp->ulp_ctx, &dev_id)) { + BNXT_DRV_DBG(ERR, "Invalid device id\n"); + return -EINVAL; + } + + dparms = bnxt_ulp_device_params_get(dev_id); + if (!dparms) { + BNXT_DRV_DBG(ERR, "could not fetch the device params\n"); + return -ENODEV; + } + + if (bnxt_ulp_cntxt_mem_type_get(ulp_ctx, &mtype)) + return -EINVAL; + if (mtype != BNXT_ULP_FLOW_MEM_TYPE_EXT) { + BNXT_DRV_DBG(INFO, "Table Scope free is not required\n"); + return 0; + } + + rc = bnxt_ulp_cntxt_tbl_scope_id_get(ulp_ctx, ¶ms.tbl_scope_id); + if (rc) { + BNXT_DRV_DBG(ERR, "Failed to get the table scope id\n"); + return -EINVAL; + } + + rc = tf_free_tbl_scope(tfp, ¶ms); + if (rc) { + BNXT_DRV_DBG(ERR, "Unable to free table scope\n"); + return -EINVAL; + } + return rc; +} + +/* The function to free and deinit the ulp context data. */ +static int32_t +ulp_tf_ctx_deinit(struct bnxt *bp, + struct bnxt_ulp_session_state *session) +{ + /* close the tf session */ + ulp_tf_ctx_session_close(bp, session); + + /* The shared session must be closed last. */ + if (bnxt_ulp_cntxt_shared_session_enabled(bp->ulp_ctx)) + ulp_tf_ctx_shared_session_close(bp, BNXT_ULP_SESSION_TYPE_SHARED, + session); + + if (bnxt_ulp_cntxt_multi_shared_session_enabled(bp->ulp_ctx)) + ulp_tf_ctx_shared_session_close(bp, + BNXT_ULP_SESSION_TYPE_SHARED_WC, + session); + + bnxt_ulp_cntxt_num_shared_clients_set(bp->ulp_ctx, false); + + /* Free the contents */ + if (session->cfg_data) { + rte_free(session->cfg_data); + bp->ulp_ctx->cfg_data = NULL; + session->cfg_data = NULL; + } + return 0; +} + +/* The function to allocate and initialize the ulp context data. */ +static int32_t +ulp_tf_ctx_init(struct bnxt *bp, + struct bnxt_ulp_session_state *session) +{ + struct bnxt_ulp_data *ulp_data; + int32_t rc = 0; + enum bnxt_ulp_device_id devid; + enum bnxt_ulp_session_type stype; + struct tf *tfp; + + /* Initialize the context entries list */ + bnxt_ulp_cntxt_list_init(); + + /* Add the context to the context entries list */ + rc = bnxt_ulp_cntxt_list_add(bp->ulp_ctx); + if (rc) { + BNXT_DRV_DBG(ERR, "Failed to add the context list entry\n"); + return -ENOMEM; + } + + /* Allocate memory to hold ulp context data. */ + ulp_data = rte_zmalloc("bnxt_ulp_data", + sizeof(struct bnxt_ulp_data), 0); + if (!ulp_data) { + BNXT_DRV_DBG(ERR, "Failed to allocate memory for ulp data\n"); + return -ENOMEM; + } + + /* Increment the ulp context data reference count usage. */ + bp->ulp_ctx->cfg_data = ulp_data; + session->cfg_data = ulp_data; + ulp_data->ref_cnt++; + ulp_data->ulp_flags |= BNXT_ULP_VF_REP_ENABLED; + + rc = bnxt_ulp_devid_get(bp, &devid); + if (rc) { + BNXT_DRV_DBG(ERR, "Unable to determine device for ULP init.\n"); + goto error_deinit; + } + + rc = bnxt_ulp_cntxt_dev_id_set(bp->ulp_ctx, devid); + if (rc) { + BNXT_DRV_DBG(ERR, "Unable to set device for ULP init.\n"); + goto error_deinit; + } + + rc = bnxt_ulp_cntxt_app_id_set(bp->ulp_ctx, bp->app_id); + if (rc) { + BNXT_DRV_DBG(ERR, "Unable to set app_id for ULP init.\n"); + goto error_deinit; + } + BNXT_DRV_DBG(DEBUG, "Ulp initialized with app id %d\n", bp->app_id); + + rc = ulp_tf_cntxt_app_caps_init(bp, bp->app_id, devid); + if (rc) { + BNXT_DRV_DBG(ERR, "Unable to set caps for app(%x)/dev(%x)\n", + bp->app_id, devid); + goto error_deinit; + } + + if (BNXT_TESTPMD_EN(bp)) { + ulp_data->ulp_flags &= ~BNXT_ULP_VF_REP_ENABLED; + BNXT_DRV_DBG(ERR, "Enabled Testpmd forward mode\n"); + } + + /* + * Shared session must be created before first regular session but after + * the ulp_ctx is valid. + */ + if (bnxt_ulp_cntxt_shared_session_enabled(bp->ulp_ctx)) { + rc = ulp_tf_ctx_shared_session_open(bp, + BNXT_ULP_SESSION_TYPE_SHARED, + session); + if (rc) { + BNXT_DRV_DBG(ERR, "Unable to open shared session (%d)\n", + rc); + goto error_deinit; + } + } + + /* Multiple session support */ + if (bnxt_ulp_cntxt_multi_shared_session_enabled(bp->ulp_ctx)) { + stype = BNXT_ULP_SESSION_TYPE_SHARED_WC; + rc = ulp_tf_ctx_shared_session_open(bp, stype, session); + if (rc) { + BNXT_DRV_DBG(ERR, + "Unable to open shared wc session (%d)\n", + rc); + goto error_deinit; + } + } + bnxt_ulp_cntxt_num_shared_clients_set(bp->ulp_ctx, true); + + /* Open the ulp session. */ + rc = ulp_tf_ctx_session_open(bp, session); + if (rc) + goto error_deinit; + + tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_DEFAULT); + bnxt_ulp_cntxt_tfp_set(bp->ulp_ctx, BNXT_ULP_SESSION_TYPE_DEFAULT, tfp); + return rc; + +error_deinit: + session->session_opened[BNXT_ULP_SESSION_TYPE_DEFAULT] = 1; + (void)ulp_tf_ctx_deinit(bp, session); + return rc; +} + +/* The function to initialize ulp dparms with devargs */ +static int32_t +ulp_tf_dparms_init(struct bnxt *bp, struct bnxt_ulp_context *ulp_ctx) +{ + struct bnxt_ulp_device_params *dparms; + uint32_t dev_id = BNXT_ULP_DEVICE_ID_LAST; + + if (!bp->max_num_kflows) { + /* Defaults to Internal */ + bnxt_ulp_cntxt_mem_type_set(ulp_ctx, + BNXT_ULP_FLOW_MEM_TYPE_INT); + return 0; + } + + /* The max_num_kflows were set, so move to external */ + if (bnxt_ulp_cntxt_mem_type_set(ulp_ctx, BNXT_ULP_FLOW_MEM_TYPE_EXT)) + return -EINVAL; + + if (bnxt_ulp_cntxt_dev_id_get(ulp_ctx, &dev_id)) { + BNXT_DRV_DBG(DEBUG, "Failed to get device id\n"); + return -EINVAL; + } + + dparms = bnxt_ulp_device_params_get(dev_id); + if (!dparms) { + BNXT_DRV_DBG(DEBUG, "Failed to get device parms\n"); + return -EINVAL; + } + + /* num_flows = max_num_kflows * 1024 */ + dparms->ext_flow_db_num_entries = bp->max_num_kflows * 1024; + /* GFID = 2 * num_flows */ + dparms->mark_db_gfid_entries = dparms->ext_flow_db_num_entries * 2; + BNXT_DRV_DBG(DEBUG, "Set the number of flows = %" PRIu64 "\n", + dparms->ext_flow_db_num_entries); + + return 0; +} + +static int32_t +ulp_tf_ctx_attach(struct bnxt *bp, + struct bnxt_ulp_session_state *session) +{ + int32_t rc = 0; + uint32_t flags, dev_id = BNXT_ULP_DEVICE_ID_LAST; + struct tf *tfp; + uint8_t app_id; + + /* Increment the ulp context data reference count usage. */ + bp->ulp_ctx->cfg_data = session->cfg_data; + bp->ulp_ctx->cfg_data->ref_cnt++; + + /* update the session details in bnxt tfp */ + tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_DEFAULT); + tfp->session = ulp_tf_session_tfp_get(session, + BNXT_ULP_SESSION_TYPE_DEFAULT); + + /* Add the context to the context entries list */ + rc = bnxt_ulp_cntxt_list_add(bp->ulp_ctx); + if (rc) { + BNXT_DRV_DBG(ERR, "Failed to add the context list entry\n"); + return -EINVAL; + } + + /* + * The supported flag will be set during the init. Use it now to + * know if we should go through the attach. + */ + rc = bnxt_ulp_cntxt_app_id_get(bp->ulp_ctx, &app_id); + if (rc) { + BNXT_DRV_DBG(ERR, "Unable to get the app id from ulp.\n"); + return -EINVAL; + } + + rc = bnxt_ulp_cntxt_dev_id_get(bp->ulp_ctx, &dev_id); + if (rc) { + BNXT_DRV_DBG(ERR, "Unable do get the dev_id.\n"); + return -EINVAL; + } + + flags = bp->ulp_ctx->cfg_data->ulp_flags; + if (ULP_APP_DEV_UNSUPPORTED_ENABLED(flags)) { + BNXT_DRV_DBG(ERR, "APP ID %d, Device ID: 0x%x not supported.\n", + app_id, dev_id); + return -EINVAL; + } + + /* Create a TF Client */ + rc = ulp_tf_ctx_session_open(bp, session); + if (rc) { + BNXT_DRV_DBG(ERR, "Failed to open ctxt session, rc:%d\n", rc); + tfp->session = NULL; + return rc; + } + tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_DEFAULT); + bnxt_ulp_cntxt_tfp_set(bp->ulp_ctx, BNXT_ULP_SESSION_TYPE_DEFAULT, tfp); + + /* + * Attach to the shared session, must be called after the + * ulp_ctx_attach in order to ensure that ulp data is available + * for attaching. + */ + rc = ulp_tf_ctx_shared_session_attach(bp, session); + if (rc) + BNXT_DRV_DBG(ERR, "Failed attach to shared session (%d)", rc); + + return rc; +} + +static void +ulp_tf_ctx_detach(struct bnxt *bp, + struct bnxt_ulp_session_state *session __rte_unused) +{ + struct tf *tfp; + + tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_DEFAULT); + if (tfp->session) { + tf_close_session(tfp); + tfp->session = NULL; + } + + /* always detach/close shared after the session. */ + ulp_tf_ctx_shared_session_detach(bp); +} + +/* + * Internal api to enable NAT feature. + * Set set_flag to 1 to set the value or zero to reset the value. + * returns 0 on success. + */ +static int32_t +ulp_tf_global_cfg_update(struct bnxt *bp, + enum tf_dir dir, + enum tf_global_config_type type, + uint32_t offset, + uint32_t value, + uint32_t set_flag) +{ + uint32_t global_cfg = 0; + int rc; + struct tf_global_cfg_parms parms = { 0 }; + struct tf *tfp; + + /* Initialize the params */ + parms.dir = dir, + parms.type = type, + parms.offset = offset, + parms.config = (uint8_t *)&global_cfg, + parms.config_sz_in_bytes = sizeof(global_cfg); + + tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_DEFAULT); + rc = tf_get_global_cfg(tfp, &parms); + if (rc) { + BNXT_DRV_DBG(ERR, "Failed to get global cfg 0x%x rc:%d\n", + type, rc); + return rc; + } + + if (set_flag) + global_cfg |= value; + else + global_cfg &= ~value; + + /* SET the register RE_CFA_REG_ACT_TECT */ + rc = tf_set_global_cfg(tfp, &parms); + if (rc) { + BNXT_DRV_DBG(ERR, "Failed to set global cfg 0x%x rc:%d\n", + type, rc); + return rc; + } + return rc; +} + +/* + * When a port is deinit'ed by dpdk. This function is called + * and this function clears the ULP context and rest of the + * infrastructure associated with it. + */ +static void +ulp_tf_deinit(struct bnxt *bp, + struct bnxt_ulp_session_state *session) +{ + bool ha_enabled; + + if (!bp->ulp_ctx || !bp->ulp_ctx->cfg_data) + return; + + ha_enabled = bnxt_ulp_cntxt_ha_enabled(bp->ulp_ctx); + if (ha_enabled && + ulp_tf_session_is_open(session, BNXT_ULP_SESSION_TYPE_DEFAULT)) { + int32_t rc = ulp_ha_mgr_close(bp->ulp_ctx); + if (rc) + BNXT_DRV_DBG(ERR, "Failed to close HA (%d)\n", rc); + } + + /* cleanup the eem table scope */ + ulp_tf_eem_tbl_scope_deinit(bp, bp->ulp_ctx); + + /* cleanup the flow database */ + ulp_flow_db_deinit(bp->ulp_ctx); + + /* Delete the Mark database */ + ulp_mark_db_deinit(bp->ulp_ctx); + + /* cleanup the ulp mapper */ + ulp_mapper_deinit(bp->ulp_ctx); + + /* cleanup the ulp matcher */ + ulp_matcher_deinit(bp->ulp_ctx); + + /* Delete the Flow Counter Manager */ + ulp_fc_mgr_deinit(bp->ulp_ctx); + + /* Delete the Port database */ + ulp_port_db_deinit(bp->ulp_ctx); + + /* Disable NAT feature */ + (void)ulp_tf_global_cfg_update(bp, TF_DIR_RX, TF_TUNNEL_ENCAP, + TF_TUNNEL_ENCAP_NAT, + BNXT_ULP_NAT_OUTER_MOST_FLAGS, 0); + + (void)ulp_tf_global_cfg_update(bp, TF_DIR_TX, TF_TUNNEL_ENCAP, + TF_TUNNEL_ENCAP_NAT, + BNXT_ULP_NAT_OUTER_MOST_FLAGS, 0); + + /* free the flow db lock */ + pthread_mutex_destroy(&bp->ulp_ctx->cfg_data->flow_db_lock); + + if (ha_enabled) + ulp_ha_mgr_deinit(bp->ulp_ctx); + + /* Delete the ulp context and tf session and free the ulp context */ + ulp_tf_ctx_deinit(bp, session); + BNXT_DRV_DBG(DEBUG, "ulp ctx has been deinitialized\n"); +} + +/* + * When a port is initialized by dpdk. This functions is called + * and this function initializes the ULP context and rest of the + * infrastructure associated with it. + */ +static int32_t +ulp_tf_init(struct bnxt *bp, + struct bnxt_ulp_session_state *session) +{ + int rc; + uint32_t ulp_dev_id = BNXT_ULP_DEVICE_ID_LAST; + + /* Allocate and Initialize the ulp context. */ + rc = ulp_tf_ctx_init(bp, session); + if (rc) { + BNXT_DRV_DBG(ERR, "Failed to create the ulp context\n"); + goto jump_to_error; + } + + rc = pthread_mutex_init(&bp->ulp_ctx->cfg_data->flow_db_lock, NULL); + if (rc) { + BNXT_DRV_DBG(ERR, "Unable to initialize flow db lock\n"); + goto jump_to_error; + } + + /* Initialize ulp dparms with values devargs passed */ + rc = ulp_tf_dparms_init(bp, bp->ulp_ctx); + if (rc) { + BNXT_DRV_DBG(ERR, "Failed to initialize the dparms\n"); + goto jump_to_error; + } + + /* create the port database */ + rc = ulp_port_db_init(bp->ulp_ctx, bp->port_cnt); + if (rc) { + BNXT_DRV_DBG(ERR, "Failed to create the port database\n"); + goto jump_to_error; + } + + /* Create the Mark database. */ + rc = ulp_mark_db_init(bp->ulp_ctx); + if (rc) { + BNXT_DRV_DBG(ERR, "Failed to create the mark database\n"); + goto jump_to_error; + } + + /* Create the flow database. */ + rc = ulp_flow_db_init(bp->ulp_ctx); + if (rc) { + BNXT_DRV_DBG(ERR, "Failed to create the flow database\n"); + goto jump_to_error; + } + + /* Create the eem table scope. */ + rc = ulp_tf_eem_tbl_scope_init(bp); + if (rc) { + BNXT_DRV_DBG(ERR, "Failed to create the eem scope table\n"); + goto jump_to_error; + } + + rc = ulp_matcher_init(bp->ulp_ctx); + if (rc) { + BNXT_DRV_DBG(ERR, "Failed to initialize ulp matcher\n"); + goto jump_to_error; + } + + rc = ulp_mapper_init(bp->ulp_ctx); + if (rc) { + BNXT_DRV_DBG(ERR, "Failed to initialize ulp mapper\n"); + goto jump_to_error; + } + + rc = ulp_fc_mgr_init(bp->ulp_ctx); + if (rc) { + BNXT_DRV_DBG(ERR, "Failed to initialize ulp flow counter mgr\n"); + goto jump_to_error; + } + + /* + * Enable NAT feature. Set the global configuration register + * Tunnel encap to enable NAT with the reuse of existing inner + * L2 header smac and dmac + */ + rc = ulp_tf_global_cfg_update(bp, TF_DIR_RX, TF_TUNNEL_ENCAP, + TF_TUNNEL_ENCAP_NAT, + BNXT_ULP_NAT_OUTER_MOST_FLAGS, 1); + if (rc) { + BNXT_DRV_DBG(ERR, "Failed to set rx global configuration\n"); + goto jump_to_error; + } + + rc = ulp_tf_global_cfg_update(bp, TF_DIR_TX, TF_TUNNEL_ENCAP, + TF_TUNNEL_ENCAP_NAT, + BNXT_ULP_NAT_OUTER_MOST_FLAGS, 1); + if (rc) { + BNXT_DRV_DBG(ERR, "Failed to set tx global configuration\n"); + goto jump_to_error; + } + + if (bnxt_ulp_cntxt_ha_enabled(bp->ulp_ctx)) { + rc = ulp_ha_mgr_init(bp->ulp_ctx); + if (rc) { + BNXT_DRV_DBG(ERR, "Failed to initialize HA %d\n", rc); + goto jump_to_error; + } + rc = ulp_ha_mgr_open(bp->ulp_ctx); + if (rc) { + BNXT_DRV_DBG(ERR, "Failed to Process HA Open %d\n", rc); + goto jump_to_error; + } + } + + rc = bnxt_ulp_cntxt_dev_id_get(bp->ulp_ctx, &ulp_dev_id); + if (rc) { + BNXT_DRV_DBG(ERR, "Unable to get device id from ulp.\n"); + return rc; + } + + if (ulp_dev_id == BNXT_ULP_DEVICE_ID_THOR) { + rc = bnxt_flow_meter_init(bp); + if (rc) { + BNXT_DRV_DBG(ERR, "Failed to config meter\n"); + goto jump_to_error; + } + } + + BNXT_DRV_DBG(DEBUG, "ulp ctx has been initialized\n"); + return rc; + +jump_to_error: + bp->ulp_ctx->ops->ulp_deinit(bp, session); + return rc; +} + +const struct bnxt_ulp_core_ops bnxt_ulp_tf_core_ops = { + .ulp_ctx_attach = ulp_tf_ctx_attach, + .ulp_ctx_detach = ulp_tf_ctx_detach, + .ulp_deinit = ulp_tf_deinit, + .ulp_init = ulp_tf_init, +}; diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp_tf.h b/drivers/net/bnxt/tf_ulp/bnxt_ulp_tf.h new file mode 100644 index 0000000000..79b8b5e483 --- /dev/null +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp_tf.h @@ -0,0 +1,24 @@ +#ifndef _BNXT_ULP_TF_H_ +#define _BNXT_ULP_TF_H_ + +#include "bnxt.h" +#include <inttypes.h> +#include "ulp_template_db_enum.h" + +struct tf * +bnxt_ulp_bp_tfp_get(struct bnxt *bp, enum bnxt_ulp_session_type type); + +struct tf * +bnxt_get_tfp_session(struct bnxt *bp, enum bnxt_session_type type); + +/* Function to set the tfp session details in the ulp context. */ +int32_t +bnxt_ulp_cntxt_tfp_set(struct bnxt_ulp_context *ulp, + enum bnxt_ulp_session_type s_type, + struct tf *tfp); + +/* Function to get the tfp session details from ulp context. */ +struct tf * +bnxt_ulp_cntxt_tfp_get(struct bnxt_ulp_context *ulp, + enum bnxt_ulp_session_type s_type); +#endif diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp_tfc.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp_tfc.c new file mode 100644 index 0000000000..191eb09160 --- /dev/null +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp_tfc.c @@ -0,0 +1,971 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2019-2021 Broadcom + * All rights reserved. + */ + +#include <rte_log.h> +#include <rte_malloc.h> +#include <rte_flow.h> +#include <rte_flow_driver.h> +#include <rte_tailq.h> +#include <rte_spinlock.h> + +#include "bnxt.h" +#include "bnxt_ulp.h" +#include "bnxt_ulp_tfc.h" +#include "bnxt_tf_common.h" +#include "hsi_struct_def_dpdk.h" +#include "tf_core.h" +#include "tf_ext_flow_handle.h" + +#include "ulp_template_db_enum.h" +#include "ulp_template_struct.h" +#include "ulp_mark_mgr.h" +#include "ulp_fc_mgr.h" +#include "ulp_flow_db.h" +#include "ulp_mapper.h" +#include "ulp_matcher.h" +#include "ulp_port_db.h" +#include "ulp_tun.h" +#include "ulp_ha_mgr.h" +#include "bnxt_tf_pmd_shim.h" +#include "ulp_template_db_tbl.h" + +/* define to enable shared table scope */ +#define TFC_SHARED_TBL_SCOPE_ENABLE 0 + +bool +bnxt_ulp_cntxt_shared_tbl_scope_enabled(struct bnxt_ulp_context *ulp_ctx) +{ + uint32_t flags = 0; + int rc; + + rc = bnxt_ulp_cntxt_ptr2_ulp_flags_get(ulp_ctx, &flags); + if (rc) + return false; + return !!(flags & BNXT_ULP_SHARED_TBL_SCOPE_ENABLED); +} + +int32_t +bnxt_ulp_cntxt_tfcp_set(struct bnxt_ulp_context *ulp, struct tfc *tfcp) +{ + enum bnxt_ulp_tfo_type tfo_type = BNXT_ULP_TFO_TYPE_TFC; + + if (ulp == NULL) + return -EINVAL; + + /* If NULL, this is invalidating an entry */ + if (tfcp == NULL) + tfo_type = BNXT_ULP_TFO_TYPE_INVALID; + ulp->tfo_type = tfo_type; + ulp->tfcp = tfcp; + + return 0; +} + +struct tfc * +bnxt_ulp_cntxt_tfcp_get(struct bnxt_ulp_context *ulp) +{ + if (ulp == NULL) + return NULL; + + if (ulp->tfo_type != BNXT_ULP_TFO_TYPE_TFC) { + BNXT_DRV_DBG(ERR, "Wrong tf type %d != %d\n", + ulp->tfo_type, BNXT_ULP_TFO_TYPE_TFC); + return NULL; + } + + return (struct tfc *)ulp->tfcp; +} + +uint32_t +bnxt_ulp_cntxt_tbl_scope_max_pools_get(struct bnxt_ulp_context *ulp_ctx) +{ + /* Max pools can be 1 or greater, always return workable value */ + if (ulp_ctx != NULL && + ulp_ctx->cfg_data != NULL && + ulp_ctx->cfg_data->max_pools) + return ulp_ctx->cfg_data->max_pools; + return 1; +} + +int32_t +bnxt_ulp_cntxt_tbl_scope_max_pools_set(struct bnxt_ulp_context *ulp_ctx, + uint32_t max) +{ + if (ulp_ctx == NULL || ulp_ctx->cfg_data == NULL) + return -EINVAL; + + /* make sure that max is at least 1 */ + if (max == 0) + max = 1; + + ulp_ctx->cfg_data->max_pools = max; + return 0; +} + +enum tfc_tbl_scope_bucket_factor +bnxt_ulp_cntxt_em_mulitplier_get(struct bnxt_ulp_context *ulp_ctx) +{ + if (ulp_ctx == NULL || ulp_ctx->cfg_data == NULL) + return TFC_TBL_SCOPE_BUCKET_FACTOR_1; + + return ulp_ctx->cfg_data->em_multiplier; +} + +int32_t +bnxt_ulp_cntxt_em_mulitplier_set(struct bnxt_ulp_context *ulp_ctx, + enum tfc_tbl_scope_bucket_factor factor) +{ + if (ulp_ctx == NULL || ulp_ctx->cfg_data == NULL) + return -EINVAL; + ulp_ctx->cfg_data->em_multiplier = factor; + return 0; +} + +uint32_t +bnxt_ulp_cntxt_num_rx_flows_get(struct bnxt_ulp_context *ulp_ctx) +{ + if (ulp_ctx == NULL || ulp_ctx->cfg_data == NULL) + return 0; + return ulp_ctx->cfg_data->num_rx_flows; +} + +int32_t +bnxt_ulp_cntxt_num_rx_flows_set(struct bnxt_ulp_context *ulp_ctx, uint32_t num) +{ + if (ulp_ctx == NULL || ulp_ctx->cfg_data == NULL) + return -EINVAL; + ulp_ctx->cfg_data->num_rx_flows = num; + return 0; +} + +uint32_t +bnxt_ulp_cntxt_num_tx_flows_get(struct bnxt_ulp_context *ulp_ctx) +{ + if (ulp_ctx == NULL || ulp_ctx->cfg_data == NULL) + return 0; + return ulp_ctx->cfg_data->num_tx_flows; +} + +int32_t +bnxt_ulp_cntxt_num_tx_flows_set(struct bnxt_ulp_context *ulp_ctx, uint32_t num) +{ + if (ulp_ctx == NULL || ulp_ctx->cfg_data == NULL) + return -EINVAL; + ulp_ctx->cfg_data->num_tx_flows = num; + return 0; +} + +uint16_t +bnxt_ulp_cntxt_em_rx_key_max_sz_get(struct bnxt_ulp_context *ulp_ctx) +{ + if (ulp_ctx == NULL || ulp_ctx->cfg_data == NULL) + return 0; + return ulp_ctx->cfg_data->em_rx_key_max_sz; +} + +int32_t +bnxt_ulp_cntxt_em_rx_key_max_sz_set(struct bnxt_ulp_context *ulp_ctx, + uint16_t max) +{ + if (ulp_ctx == NULL || ulp_ctx->cfg_data == NULL) + return -EINVAL; + + ulp_ctx->cfg_data->em_rx_key_max_sz = max; + return 0; +} + +uint16_t +bnxt_ulp_cntxt_em_tx_key_max_sz_get(struct bnxt_ulp_context *ulp_ctx) +{ + if (ulp_ctx == NULL || ulp_ctx->cfg_data == NULL) + return 0; + return ulp_ctx->cfg_data->em_tx_key_max_sz; +} + +int32_t +bnxt_ulp_cntxt_em_tx_key_max_sz_set(struct bnxt_ulp_context *ulp_ctx, + uint16_t max) +{ + if (ulp_ctx == NULL || ulp_ctx->cfg_data == NULL) + return -EINVAL; + + ulp_ctx->cfg_data->em_tx_key_max_sz = max; + return 0; +} + +uint16_t +bnxt_ulp_cntxt_act_rec_rx_max_sz_get(struct bnxt_ulp_context *ulp_ctx) +{ + if (ulp_ctx == NULL || ulp_ctx->cfg_data == NULL) + return 0; + return ulp_ctx->cfg_data->act_rx_max_sz; +} + +int32_t +bnxt_ulp_cntxt_act_rec_rx_max_sz_set(struct bnxt_ulp_context *ulp_ctx, + int16_t max) +{ + if (ulp_ctx == NULL || ulp_ctx->cfg_data == NULL) + return -EINVAL; + + ulp_ctx->cfg_data->act_rx_max_sz = max; + return 0; +} + +uint16_t +bnxt_ulp_cntxt_act_rec_tx_max_sz_get(struct bnxt_ulp_context *ulp_ctx) +{ + if (ulp_ctx == NULL || ulp_ctx->cfg_data == NULL) + return 0; + return ulp_ctx->cfg_data->act_tx_max_sz; +} + +int32_t +bnxt_ulp_cntxt_act_rec_tx_max_sz_set(struct bnxt_ulp_context *ulp_ctx, + int16_t max) +{ + if (ulp_ctx == NULL || ulp_ctx->cfg_data == NULL) + return -EINVAL; + + ulp_ctx->cfg_data->act_tx_max_sz = max; + return 0; +} + +uint32_t +bnxt_ulp_cntxt_page_sz_get(struct bnxt_ulp_context *ulp_ctx) +{ + if (ulp_ctx == NULL) + return 0; + + return ulp_ctx->cfg_data->page_sz; +} + +int32_t +bnxt_ulp_cntxt_page_sz_set(struct bnxt_ulp_context *ulp_ctx, + uint32_t page_sz) +{ + if (ulp_ctx == NULL) + return -EINVAL; + ulp_ctx->cfg_data->page_sz = page_sz; + return 0; +} + +static int32_t +ulp_tfc_dparms_init(struct bnxt *bp, + struct bnxt_ulp_context *ulp_ctx, + uint32_t dev_id) +{ + struct bnxt_ulp_device_params *dparms; + uint32_t num_flows = 0, num_rx_flows = 0, num_tx_flows = 0; + + /* The max_num_kflows were set, so move to external */ + if (bnxt_ulp_cntxt_mem_type_set(ulp_ctx, BNXT_ULP_FLOW_MEM_TYPE_EXT)) + return -EINVAL; + + dparms = bnxt_ulp_device_params_get(dev_id); + if (!dparms) { + BNXT_DRV_DBG(DEBUG, "Failed to get device parms\n"); + return -EINVAL; + } + + if (bp->max_num_kflows) { + num_flows = bp->max_num_kflows * 1024; + dparms->ext_flow_db_num_entries = bp->max_num_kflows * 1024; + } else { + num_rx_flows = bnxt_ulp_cntxt_num_rx_flows_get(ulp_ctx); + num_tx_flows = bnxt_ulp_cntxt_num_tx_flows_get(ulp_ctx); + num_flows = num_rx_flows + num_tx_flows; + } + + dparms->ext_flow_db_num_entries = num_flows; + + /* GFID = 2 * num_flows */ + dparms->mark_db_gfid_entries = dparms->ext_flow_db_num_entries * 2; + BNXT_DRV_DBG(DEBUG, "Set the number of flows = %" PRIu64 "\n", + dparms->ext_flow_db_num_entries); + + return 0; +} + +static void +ulp_tfc_tbl_scope_deinit(struct bnxt *bp) +{ + uint16_t fid = 0, fid_cnt = 0; + struct tfc *tfcp; + uint8_t tsid = 0; + int32_t rc; + + tfcp = bnxt_ulp_cntxt_tfcp_get(bp->ulp_ctx); + if (tfcp == NULL) + return; + + rc = bnxt_ulp_cntxt_tsid_get(bp->ulp_ctx, &tsid); + + rc = bnxt_ulp_cntxt_fid_get(bp->ulp_ctx, &fid); + if (rc) + return; + + rc = tfc_tbl_scope_cpm_free(tfcp, tsid); + if (rc) + BNXT_DRV_DBG(ERR, "Failed Freeing CPM TSID:%d FID:%d\n", + tsid, fid); + else + BNXT_DRV_DBG(DEBUG, "Freed CPM TSID:%d FID: %d\n", tsid, fid); + + rc = tfc_tbl_scope_mem_free(tfcp, fid, tsid); + if (rc) + BNXT_DRV_DBG(ERR, "Failed freeing tscope mem TSID:%d FID:%d\n", + tsid, fid); + else + BNXT_DRV_DBG(DEBUG, "Freed tscope mem TSID:%d FID:%d\n", + tsid, fid); + + rc = tfc_tbl_scope_fid_rem(tfcp, fid, tsid, &fid_cnt); + if (rc) + BNXT_DRV_DBG(ERR, "Failed removing FID from TSID:%d FID:%d\n", + tsid, fid); + else + BNXT_DRV_DBG(DEBUG, "Removed FID from TSID:%d FID:%d\n", + tsid, fid); +} + +static int32_t +ulp_tfc_tbl_scope_init(struct bnxt *bp) +{ + struct tfc_tbl_scope_mem_alloc_parms mem_parms; + struct tfc_tbl_scope_size_query_parms qparms = { 0 }; + uint8_t max_lkup_sz[CFA_DIR_MAX], max_act_sz[CFA_DIR_MAX]; + struct tfc_tbl_scope_cpm_alloc_parms cparms; + uint16_t fid, max_pools; + bool first = true, shared = false; + uint8_t tsid = 0; + struct tfc *tfcp; + int32_t rc = 0; + + tfcp = bnxt_ulp_cntxt_tfcp_get(bp->ulp_ctx); + if (tfcp == NULL) + return -EINVAL; + + fid = bp->fw_fid; + + max_pools = bnxt_ulp_cntxt_tbl_scope_max_pools_get(bp->ulp_ctx); + max_lkup_sz[CFA_DIR_RX] = + bnxt_ulp_cntxt_em_rx_key_max_sz_get(bp->ulp_ctx); + max_lkup_sz[CFA_DIR_TX] = + bnxt_ulp_cntxt_em_tx_key_max_sz_get(bp->ulp_ctx); + max_act_sz[CFA_DIR_RX] = + bnxt_ulp_cntxt_act_rec_rx_max_sz_get(bp->ulp_ctx); + max_act_sz[CFA_DIR_TX] = + bnxt_ulp_cntxt_act_rec_tx_max_sz_get(bp->ulp_ctx); + + shared = bnxt_ulp_cntxt_shared_tbl_scope_enabled(bp->ulp_ctx); + +#if (TFC_SHARED_TBL_SCOPE_ENABLE == 1) + /* Temporary code for testing shared table scopes until ULP + * usage defined. + */ + if (!BNXT_PF(bp)) { + shared = true; + max_pools = 8; + } +#endif + /* Calculate the sizes for setting up memory */ + qparms.shared = shared; + qparms.max_pools = max_pools; + qparms.factor = bnxt_ulp_cntxt_em_mulitplier_get(bp->ulp_ctx); + qparms.flow_cnt[CFA_DIR_RX] = + bnxt_ulp_cntxt_num_rx_flows_get(bp->ulp_ctx); + qparms.flow_cnt[CFA_DIR_TX] = + bnxt_ulp_cntxt_num_tx_flows_get(bp->ulp_ctx); + qparms.key_sz_in_bytes[CFA_DIR_RX] = max_lkup_sz[CFA_DIR_RX]; + qparms.key_sz_in_bytes[CFA_DIR_TX] = max_lkup_sz[CFA_DIR_TX]; + qparms.act_rec_sz_in_bytes[CFA_DIR_RX] = max_act_sz[CFA_DIR_RX]; + qparms.act_rec_sz_in_bytes[CFA_DIR_TX] = max_act_sz[CFA_DIR_TX]; + rc = tfc_tbl_scope_size_query(tfcp, &qparms); + if (rc) + return rc; + + + + rc = tfc_tbl_scope_id_alloc(tfcp, shared, CFA_APP_TYPE_TF, &tsid, + &first); + if (rc) { + BNXT_DRV_DBG(ERR, "Failed to allocate tscope\n"); + return rc; + } + BNXT_DRV_DBG(DEBUG, "Allocated tscope TSID:%d\n", tsid); + + rc = bnxt_ulp_cntxt_tsid_set(bp->ulp_ctx, tsid); + if (rc) + return rc; + + /* If we are shared and not the first table scope creator + */ + if (shared && !first) { + bool configured; + #define ULP_SHARED_TSID_WAIT_TIMEOUT 5000 + #define ULP_SHARED_TSID_WAIT_TIME 50 + int32_t timeout = ULP_SHARED_TSID_WAIT_TIMEOUT; + do { + rte_delay_ms(ULP_SHARED_TSID_WAIT_TIME); + rc = tfc_tbl_scope_config_state_get(tfcp, tsid, &configured); + if (rc) { + BNXT_DRV_DBG(ERR, + "Failed get tsid(%d) config state\n", + rc); + return rc; + } + timeout -= ULP_SHARED_TSID_WAIT_TIME; + BNXT_DRV_DBG(INFO, + "Waiting %d ms for shared tsid(%d)\n", + timeout, tsid); + } while (!configured && timeout > 0); + if (timeout <= 0) { + BNXT_DRV_DBG(ERR, "Timed out on shared tsid(%d)\n", + tsid); + return -ETIMEDOUT; + } + } + mem_parms.first = first; + mem_parms.static_bucket_cnt_exp[CFA_DIR_RX] = + qparms.static_bucket_cnt_exp[CFA_DIR_RX]; + mem_parms.static_bucket_cnt_exp[CFA_DIR_TX] = + qparms.static_bucket_cnt_exp[CFA_DIR_TX]; + mem_parms.lkup_rec_cnt[CFA_DIR_RX] = qparms.lkup_rec_cnt[CFA_DIR_RX]; + mem_parms.lkup_rec_cnt[CFA_DIR_TX] = qparms.lkup_rec_cnt[CFA_DIR_TX]; + mem_parms.act_rec_cnt[CFA_DIR_RX] = qparms.act_rec_cnt[CFA_DIR_RX]; + mem_parms.act_rec_cnt[CFA_DIR_TX] = qparms.act_rec_cnt[CFA_DIR_TX]; + mem_parms.pbl_page_sz_in_bytes = + bnxt_ulp_cntxt_page_sz_get(bp->ulp_ctx); + mem_parms.max_pools = max_pools; + + mem_parms.lkup_pool_sz_exp[CFA_DIR_RX] = + qparms.lkup_pool_sz_exp[CFA_DIR_RX]; + mem_parms.lkup_pool_sz_exp[CFA_DIR_TX] = + qparms.lkup_pool_sz_exp[CFA_DIR_TX]; + + mem_parms.act_pool_sz_exp[CFA_DIR_RX] = + qparms.act_pool_sz_exp[CFA_DIR_RX]; + mem_parms.act_pool_sz_exp[CFA_DIR_TX] = + qparms.act_pool_sz_exp[CFA_DIR_TX]; + mem_parms.local = true; + rc = tfc_tbl_scope_mem_alloc(tfcp, fid, tsid, &mem_parms); + if (rc) { + BNXT_DRV_DBG(ERR, + "Failed to allocate tscope mem TSID:%d on FID:%d\n", + tsid, fid); + return rc; + } + + BNXT_DRV_DBG(DEBUG, "Allocated or set tscope mem TSID:%d on FID:%d\n", + tsid, fid); + + + /* The max contiguous is in 32 Bytes records, so convert Bytes to 32 + * Byte records. + */ + cparms.lkup_max_contig_rec[CFA_DIR_RX] = (max_lkup_sz[CFA_DIR_RX] + 31) / 32; + cparms.lkup_max_contig_rec[CFA_DIR_TX] = (max_lkup_sz[CFA_DIR_TX] + 31) / 32; + cparms.act_max_contig_rec[CFA_DIR_RX] = (max_act_sz[CFA_DIR_RX] + 31) / 32; + cparms.act_max_contig_rec[CFA_DIR_TX] = (max_act_sz[CFA_DIR_TX] + 31) / 32; + cparms.max_pools = max_pools; + + rc = tfc_tbl_scope_cpm_alloc(tfcp, tsid, &cparms); + if (rc) + BNXT_DRV_DBG(ERR, "Failed to allocate CPM TSID:%d FID:%d\n", + tsid, fid); + else + BNXT_DRV_DBG(DEBUG, "Allocated CPM TSID:%d FID:%d\n", tsid, fid); + + return rc; +} + +static int32_t +ulp_tfc_cntxt_app_caps_init(struct bnxt *bp, uint8_t app_id, uint32_t dev_id) +{ + struct bnxt_ulp_app_capabilities_info *info; + struct bnxt_ulp_context *ulp_ctx = bp->ulp_ctx; + uint32_t num = 0, rc; + bool found = false; + uint16_t i; + + if (ULP_APP_DEV_UNSUPPORTED_ENABLED(ulp_ctx->cfg_data->ulp_flags)) { + BNXT_DRV_DBG(ERR, "APP ID %d, Device ID: 0x%x not supported.\n", + app_id, dev_id); + return -EINVAL; + } + + info = bnxt_ulp_app_cap_list_get(&num); + if (!info || !num) { + BNXT_DRV_DBG(ERR, "Failed to get app capabilities.\n"); + return -EINVAL; + } + + for (i = 0; i < num && !found; i++) { + if (info[i].app_id != app_id || info[i].device_id != dev_id) + continue; + found = true; + if (info[i].flags & BNXT_ULP_APP_CAP_SHARED_EN) + ulp_ctx->cfg_data->ulp_flags |= + BNXT_ULP_SHARED_SESSION_ENABLED; + if (info[i].flags & BNXT_ULP_APP_CAP_HOT_UPGRADE_EN) + ulp_ctx->cfg_data->ulp_flags |= + BNXT_ULP_HIGH_AVAIL_ENABLED; + if (info[i].flags & BNXT_ULP_APP_CAP_UNICAST_ONLY) + ulp_ctx->cfg_data->ulp_flags |= + BNXT_ULP_APP_UNICAST_ONLY; + if (info[i].flags & BNXT_ULP_APP_CAP_IP_TOS_PROTO_SUPPORT) + ulp_ctx->cfg_data->ulp_flags |= + BNXT_ULP_APP_TOS_PROTO_SUPPORT; + if (info[i].flags & BNXT_ULP_APP_CAP_BC_MC_SUPPORT) + ulp_ctx->cfg_data->ulp_flags |= + BNXT_ULP_APP_BC_MC_SUPPORT; + if (info[i].flags & BNXT_ULP_APP_CAP_SOCKET_DIRECT) { + /* Enable socket direction only if MR is enabled in fw*/ + if (BNXT_MULTIROOT_EN(bp)) { + ulp_ctx->cfg_data->ulp_flags |= + BNXT_ULP_APP_SOCKET_DIRECT; + BNXT_DRV_DBG(DEBUG, + "Socket Direct feature is enabled\n"); + } + } + + rc = bnxt_ulp_cntxt_tbl_scope_max_pools_set(ulp_ctx, + info[i].max_pools); + if (rc) + return rc; + rc = bnxt_ulp_cntxt_em_mulitplier_set(ulp_ctx, + info[i].em_multiplier); + if (rc) + return rc; + + rc = bnxt_ulp_cntxt_num_rx_flows_set(ulp_ctx, + info[i].num_rx_flows); + if (rc) + return rc; + + rc = bnxt_ulp_cntxt_num_tx_flows_set(ulp_ctx, + info[i].num_tx_flows); + if (rc) + return rc; + + rc = bnxt_ulp_cntxt_em_rx_key_max_sz_set(ulp_ctx, + info[i].em_rx_key_max_sz); + if (rc) + return rc; + + rc = bnxt_ulp_cntxt_em_tx_key_max_sz_set(ulp_ctx, + info[i].em_tx_key_max_sz); + if (rc) + return rc; + + rc = bnxt_ulp_cntxt_act_rec_rx_max_sz_set(ulp_ctx, + info[i].act_rx_max_sz); + if (rc) + return rc; + + rc = bnxt_ulp_cntxt_act_rec_tx_max_sz_set(ulp_ctx, + info[i].act_tx_max_sz); + if (rc) + return rc; + + rc = bnxt_ulp_cntxt_page_sz_set(ulp_ctx, + info[i].pbl_page_sz_in_bytes); + if (rc) + return rc; + bnxt_ulp_num_key_recipes_set(ulp_ctx, + info[i].num_key_recipes_per_dir); + } + if (!found) { + BNXT_DRV_DBG(ERR, "APP ID %d, Device ID: 0x%x not supported.\n", + app_id, dev_id); + ulp_ctx->cfg_data->ulp_flags |= BNXT_ULP_APP_DEV_UNSUPPORTED; + return -EINVAL; + } + + return 0; +} + +/* The function to free and deinit the ulp context data. */ +static int32_t +ulp_tfc_ctx_deinit(struct bnxt *bp, + struct bnxt_ulp_session_state *session) +{ + /* Free the contents */ + if (session->cfg_data) { + rte_free(session->cfg_data); + bp->ulp_ctx->cfg_data = NULL; + session->cfg_data = NULL; + } + return 0; +} + +/* The function to allocate and initialize the ulp context data. */ +static int32_t +ulp_tfc_ctx_init(struct bnxt *bp, + struct bnxt_ulp_session_state *session) +{ + struct bnxt_ulp_data *ulp_data; + enum bnxt_ulp_device_id devid; + int32_t rc = 0; + + /* Initialize the context entries list */ + bnxt_ulp_cntxt_list_init(); + + /* Add the context to the context entries list */ + rc = bnxt_ulp_cntxt_list_add(bp->ulp_ctx); + if (rc) { + BNXT_DRV_DBG(ERR, "Failed to add the context list entry\n"); + return -ENOMEM; + } + + /* Allocate memory to hold ulp context data. */ + ulp_data = rte_zmalloc("bnxt_ulp_data", + sizeof(struct bnxt_ulp_data), 0); + if (!ulp_data) { + BNXT_DRV_DBG(ERR, "Failed to allocate memory for ulp data\n"); + return -ENOMEM; + } + + /* Increment the ulp context data reference count usage. */ + bp->ulp_ctx->cfg_data = ulp_data; + session->cfg_data = ulp_data; + ulp_data->ref_cnt++; + ulp_data->ulp_flags |= BNXT_ULP_VF_REP_ENABLED; + + rc = bnxt_ulp_devid_get(bp, &devid); + if (rc) { + BNXT_DRV_DBG(ERR, "Unable to determine device for ULP init.\n"); + goto error_deinit; + } + + rc = bnxt_ulp_cntxt_dev_id_set(bp->ulp_ctx, devid); + if (rc) { + BNXT_DRV_DBG(ERR, "Unable to set device for ULP init.\n"); + goto error_deinit; + } + + rc = bnxt_ulp_cntxt_app_id_set(bp->ulp_ctx, bp->app_id); + if (rc) { + BNXT_DRV_DBG(ERR, "Unable to set app_id for ULP init.\n"); + goto error_deinit; + } + BNXT_DRV_DBG(DEBUG, "Ulp initialized with app id %d\n", bp->app_id); + + rc = ulp_tfc_dparms_init(bp, bp->ulp_ctx, devid); + if (rc) { + BNXT_DRV_DBG(ERR, "Unable to init dparms for app(%x)/dev(%x)\n", + bp->app_id, devid); + goto error_deinit; + } + + rc = ulp_tfc_cntxt_app_caps_init(bp, bp->app_id, devid); + if (rc) { + BNXT_DRV_DBG(ERR, "Unable to set caps for app(%x)/dev(%x)\n", + bp->app_id, devid); + goto error_deinit; + } + + if (BNXT_TESTPMD_EN(bp)) { + ulp_data->ulp_flags &= ~BNXT_ULP_VF_REP_ENABLED; + BNXT_DRV_DBG(ERR, "Enabled Testpmd forward mode\n"); + } + + return rc; + +error_deinit: + session->session_opened[BNXT_ULP_SESSION_TYPE_DEFAULT] = 1; + (void)ulp_tfc_ctx_deinit(bp, session); + return rc; +} + +static int32_t +ulp_tfc_ctx_attach(struct bnxt *bp, + struct bnxt_ulp_session_state *session) +{ + uint32_t flags, dev_id = BNXT_ULP_DEVICE_ID_LAST; + uint16_t fid_cnt = 0; + int32_t rc = 0; + uint8_t app_id; + + bp->tfcp.bp = bp; + rc = tfc_open(&bp->tfcp); + if (rc) { + BNXT_DRV_DBG(ERR, "Failed to initialize the tfc object\n"); + return rc; + } + + rc = bnxt_ulp_cntxt_tfcp_set(bp->ulp_ctx, &bp->tfcp); + if (rc) { + BNXT_DRV_DBG(ERR, "Failed to add tfcp to ulp ctxt\n"); + return rc; + } + + /* Increment the ulp context data reference count usage. */ + bp->ulp_ctx->cfg_data = session->cfg_data; + bp->ulp_ctx->cfg_data->ref_cnt++; + + rc = tfc_session_fid_add(&bp->tfcp, bp->fw_fid, + session->session_id, &fid_cnt); + if (rc) { + BNXT_DRV_DBG(ERR, "Failed to add FID:%d to SID:%d.\n", + bp->fw_fid, session->session_id); + return rc; + } + BNXT_DRV_DBG(DEBUG, "SID:%d added FID:%d\n", + session->session_id, bp->fw_fid); + + rc = bnxt_ulp_cntxt_sid_set(bp->ulp_ctx, session->session_id); + if (rc) { + BNXT_DRV_DBG(ERR, "Failed to add fid to session.\n"); + return rc; + } + + /* Add the context to the context entries list */ + rc = bnxt_ulp_cntxt_list_add(bp->ulp_ctx); + if (rc) { + BNXT_DRV_DBG(ERR, "Failed to add the context list entry\n"); + return -EINVAL; + } + + /* + * The supported flag will be set during the init. Use it now to + * know if we should go through the attach. + */ + rc = bnxt_ulp_cntxt_app_id_get(bp->ulp_ctx, &app_id); + if (rc) { + BNXT_DRV_DBG(ERR, "Unable to get the app id from ulp.\n"); + return -EINVAL; + } + + rc = bnxt_ulp_cntxt_dev_id_get(bp->ulp_ctx, &dev_id); + if (rc) { + BNXT_DRV_DBG(ERR, "Unable do get the dev_id.\n"); + return -EINVAL; + } + + flags = bp->ulp_ctx->cfg_data->ulp_flags; + if (ULP_APP_DEV_UNSUPPORTED_ENABLED(flags)) { + BNXT_DRV_DBG(ERR, "APP ID %d, Device ID: 0x%x not supported.\n", + app_id, dev_id); + return -EINVAL; + } + + rc = ulp_tfc_tbl_scope_init(bp); + + return rc; +} + +static void +ulp_tfc_ctx_detach(struct bnxt *bp, + struct bnxt_ulp_session_state *session) +{ + uint16_t fid_cnt = 0; + int32_t rc; + + ulp_tfc_tbl_scope_deinit(bp); + + rc = tfc_session_fid_rem(&bp->tfcp, bp->fw_fid, &fid_cnt); + if (rc) + BNXT_DRV_DBG(ERR, "Failed to remove FID:%d from SID:%d\n", + bp->fw_fid, session->session_id); + else + BNXT_DRV_DBG(DEBUG, "SID:%d removed FID:%d CNT:%d\n", + session->session_id, bp->fw_fid, fid_cnt); + bnxt_ulp_cntxt_sid_reset(bp->ulp_ctx); + (void)tfc_close(&bp->tfcp); +} + +/* + * When a port is deinit'ed by dpdk. This function is called + * and this function clears the ULP context and rest of the + * infrastructure associated with it. + */ +static void +ulp_tfc_deinit(struct bnxt *bp, + struct bnxt_ulp_session_state *session) +{ + bool ha_enabled; + uint16_t fid_cnt = 0; + int32_t rc; + + if (!bp->ulp_ctx || !bp->ulp_ctx->cfg_data) + return; + + ha_enabled = bnxt_ulp_cntxt_ha_enabled(bp->ulp_ctx); + if (ha_enabled) { + rc = ulp_ha_mgr_close(bp->ulp_ctx); + if (rc) + BNXT_DRV_DBG(ERR, "Failed to close HA (%d)\n", rc); + } + + /* cleanup the flow database */ + ulp_flow_db_deinit(bp->ulp_ctx); + + /* Delete the Mark database */ + ulp_mark_db_deinit(bp->ulp_ctx); + + /* cleanup the ulp mapper */ + ulp_mapper_deinit(bp->ulp_ctx); + + /* cleanup the ulp matcher */ + ulp_matcher_deinit(bp->ulp_ctx); + + /* Delete the Flow Counter Manager */ + ulp_fc_mgr_deinit(bp->ulp_ctx); + + /* Delete the Port database */ + ulp_port_db_deinit(bp->ulp_ctx); + + /* free the flow db lock */ + pthread_mutex_destroy(&bp->ulp_ctx->cfg_data->flow_db_lock); + + ulp_tfc_tbl_scope_deinit(bp); + + rc = tfc_session_fid_rem(&bp->tfcp, bp->fw_fid, &fid_cnt); + if (rc) + BNXT_DRV_DBG(ERR, "Failed to remove FID:%d from SID:%d\n", + bp->fw_fid, session->session_id); + else + BNXT_DRV_DBG(DEBUG, "SID:%d removed FID:%d CNT:%d\n", + session->session_id, bp->fw_fid, fid_cnt); + bnxt_ulp_cntxt_sid_reset(bp->ulp_ctx); + (void)tfc_close(&bp->tfcp); + + /* Delete the ulp context and tf session and free the ulp context */ + ulp_tfc_ctx_deinit(bp, session); + + BNXT_DRV_DBG(DEBUG, "ulp ctx has been deinitialized\n"); +} + +/* + * When a port is initialized by dpdk. This functions is called + * and this function initializes the ULP context and rest of the + * infrastructure associated with it. + */ +static int32_t +ulp_tfc_init(struct bnxt *bp, + struct bnxt_ulp_session_state *session) +{ + uint32_t ulp_dev_id = BNXT_ULP_DEVICE_ID_LAST; + uint16_t sid; + int rc; + + bp->tfcp.bp = bp; + rc = tfc_open(&bp->tfcp); + if (rc) { + BNXT_DRV_DBG(ERR, "Failed to initialize the tfc object\n"); + return rc; + } + + rc = bnxt_ulp_cntxt_tfcp_set(bp->ulp_ctx, &bp->tfcp); + if (rc) { + BNXT_DRV_DBG(ERR, "Failed to add tfcp to ulp cntxt\n"); + return rc; + } + + /* First time, so allocate a session and save it. */ + rc = tfc_session_id_alloc(&bp->tfcp, bp->fw_fid, &sid); + if (rc) { + BNXT_DRV_DBG(ERR, "Failed to allocate a session id\n"); + return rc; + } + BNXT_DRV_DBG(DEBUG, "SID:%d allocated with FID:%d\n", sid, bp->fw_fid); + session->session_id = sid; + rc = bnxt_ulp_cntxt_sid_set(bp->ulp_ctx, sid); + if (rc) { + BNXT_DRV_DBG(ERR, "Failed to sid to ulp cntxt\n"); + return rc; + } + + /* Allocate and Initialize the ulp context. */ + rc = ulp_tfc_ctx_init(bp, session); + if (rc) { + BNXT_DRV_DBG(ERR, "Failed to create the ulp context\n"); + goto jump_to_error; + } + + rc = ulp_tfc_tbl_scope_init(bp); + if (rc) { + BNXT_DRV_DBG(ERR, "Failed to create the ulp context\n"); + goto jump_to_error; + } + + rc = pthread_mutex_init(&bp->ulp_ctx->cfg_data->flow_db_lock, NULL); + if (rc) { + BNXT_DRV_DBG(ERR, "Unable to initialize flow db lock\n"); + goto jump_to_error; + } + + /* Initialize ulp dparms with values devargs passed */ + rc = bnxt_ulp_cntxt_dev_id_get(bp->ulp_ctx, &ulp_dev_id); + if (rc) { + BNXT_DRV_DBG(ERR, "Unable to get device id from ulp.\n"); + return rc; + } + + rc = ulp_tfc_dparms_init(bp, bp->ulp_ctx, ulp_dev_id); + if (rc) { + BNXT_DRV_DBG(ERR, "Failed to initialize the dparms\n"); + goto jump_to_error; + } + + /* create the port database */ + rc = ulp_port_db_init(bp->ulp_ctx, bp->port_cnt); + if (rc) { + BNXT_DRV_DBG(ERR, "Failed to create the port database\n"); + goto jump_to_error; + } + + /* BAUCOM TODO: Mark database assumes LFID/GFID Parms, need to look at + * alternatives. + */ + /* Create the Mark database. */ + rc = ulp_mark_db_init(bp->ulp_ctx); + if (rc) { + BNXT_DRV_DBG(ERR, "Failed to create the mark database\n"); + goto jump_to_error; + } + + /* Create the flow database. */ + rc = ulp_flow_db_init(bp->ulp_ctx); + if (rc) { + BNXT_DRV_DBG(ERR, "Failed to create the flow database\n"); + goto jump_to_error; + } + + rc = ulp_matcher_init(bp->ulp_ctx); + if (rc) { + BNXT_DRV_DBG(ERR, "Failed to initialize ulp matcher\n"); + goto jump_to_error; + } + + rc = ulp_mapper_init(bp->ulp_ctx); + if (rc) { + BNXT_DRV_DBG(ERR, "Failed to initialize ulp mapper\n"); + goto jump_to_error; + } + + /* BAUCOM TODO: need to make FC Mgr not start the thread. */ + rc = ulp_fc_mgr_init(bp->ulp_ctx); + if (rc) { + BNXT_DRV_DBG(ERR, "Failed to initialize ulp flow counter mgr\n"); + goto jump_to_error; + } + + BNXT_DRV_DBG(DEBUG, "ulp ctx has been initialized\n"); + return rc; + +jump_to_error: + bp->ulp_ctx->ops->ulp_deinit(bp, session); + return rc; +} + +const struct bnxt_ulp_core_ops bnxt_ulp_tfc_core_ops = { + .ulp_ctx_attach = ulp_tfc_ctx_attach, + .ulp_ctx_detach = ulp_tfc_ctx_detach, + .ulp_deinit = ulp_tfc_deinit, + .ulp_init = ulp_tfc_init, +}; diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/meson.build b/drivers/net/bnxt/tf_ulp/generic_templates/meson.build index b1e7b8cc32..196dcef447 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/meson.build +++ b/drivers/net/bnxt/tf_ulp/generic_templates/meson.build @@ -4,10 +4,12 @@ includes += include_directories('.') sources += files( - 'ulp_template_db_class.c', - 'ulp_template_db_act.c', - 'ulp_template_db_tbl.c', - 'ulp_template_db_wh_plus_act.c', - 'ulp_template_db_wh_plus_class.c', - 'ulp_template_db_thor_act.c', - 'ulp_template_db_thor_class.c') + 'ulp_template_db_class.c', + 'ulp_template_db_act.c', + 'ulp_template_db_tbl.c', + 'ulp_template_db_wh_plus_act.c', + 'ulp_template_db_wh_plus_class.c', + 'ulp_template_db_thor_act.c', + 'ulp_template_db_thor_class.c', + 'ulp_template_db_thor2_act.c', + 'ulp_template_db_thor2_class.c') diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c index fad593fa24..353de019de 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c @@ -8,9525 +8,151 @@ #include "ulp_template_struct.h" #include "ulp_template_db_tbl.h" -/* - * Action signature table: - * maps hash id to ulp_act_match_list[] index - */ -uint16_t ulp_act_sig_tbl[BNXT_ULP_ACT_SIG_TBL_MAX_SZ] = { - [BNXT_ULP_ACT_HID_0000] = 1, - [BNXT_ULP_ACT_HID_0040] = 2, - [BNXT_ULP_ACT_HID_10000] = 3, - [BNXT_ULP_ACT_HID_cc40] = 4, - [BNXT_ULP_ACT_HID_0400] = 5, - [BNXT_ULP_ACT_HID_1cc40] = 6, - [BNXT_ULP_ACT_HID_d040] = 7, - [BNXT_ULP_ACT_HID_0080] = 8, - [BNXT_ULP_ACT_HID_0200] = 9, - [BNXT_ULP_ACT_HID_0280] = 10, - [BNXT_ULP_ACT_HID_00c0] = 11, - [BNXT_ULP_ACT_HID_10080] = 12, - [BNXT_ULP_ACT_HID_ccc0] = 13, - [BNXT_ULP_ACT_HID_0480] = 14, - [BNXT_ULP_ACT_HID_1ccc0] = 15, - [BNXT_ULP_ACT_HID_d0c0] = 16, - [BNXT_ULP_ACT_HID_19742] = 17, - [BNXT_ULP_ACT_HID_19782] = 18, - [BNXT_ULP_ACT_HID_29742] = 19, - [BNXT_ULP_ACT_HID_26382] = 20, - [BNXT_ULP_ACT_HID_19b42] = 21, - [BNXT_ULP_ACT_HID_36382] = 22, - [BNXT_ULP_ACT_HID_26782] = 23, - [BNXT_ULP_ACT_HID_197c2] = 24, - [BNXT_ULP_ACT_HID_19802] = 25, - [BNXT_ULP_ACT_HID_297c2] = 26, - [BNXT_ULP_ACT_HID_26402] = 27, - [BNXT_ULP_ACT_HID_19bc2] = 28, - [BNXT_ULP_ACT_HID_36402] = 29, - [BNXT_ULP_ACT_HID_26802] = 30, - [BNXT_ULP_ACT_HID_bca0] = 31, - [BNXT_ULP_ACT_HID_bce0] = 32, - [BNXT_ULP_ACT_HID_1bca0] = 33, - [BNXT_ULP_ACT_HID_168e0] = 34, - [BNXT_ULP_ACT_HID_a0a0] = 35, - [BNXT_ULP_ACT_HID_268e0] = 36, - [BNXT_ULP_ACT_HID_16ce0] = 37, - [BNXT_ULP_ACT_HID_bd20] = 38, - [BNXT_ULP_ACT_HID_bd60] = 39, - [BNXT_ULP_ACT_HID_1bd20] = 40, - [BNXT_ULP_ACT_HID_16960] = 41, - [BNXT_ULP_ACT_HID_a120] = 42, - [BNXT_ULP_ACT_HID_26960] = 43, - [BNXT_ULP_ACT_HID_16d60] = 44, - [BNXT_ULP_ACT_HID_4040] = 45, - [BNXT_ULP_ACT_HID_8040] = 46, - [BNXT_ULP_ACT_HID_c040] = 47, - [BNXT_ULP_ACT_HID_40c0] = 48, - [BNXT_ULP_ACT_HID_80c0] = 49, - [BNXT_ULP_ACT_HID_c0c0] = 50, - [BNXT_ULP_ACT_HID_4400] = 51, - [BNXT_ULP_ACT_HID_8400] = 52, - [BNXT_ULP_ACT_HID_c400] = 53, - [BNXT_ULP_ACT_HID_4480] = 54, - [BNXT_ULP_ACT_HID_8480] = 55, - [BNXT_ULP_ACT_HID_c480] = 56, - [BNXT_ULP_ACT_HID_1d782] = 57, - [BNXT_ULP_ACT_HID_21782] = 58, - [BNXT_ULP_ACT_HID_25782] = 59, - [BNXT_ULP_ACT_HID_1d802] = 60, - [BNXT_ULP_ACT_HID_21802] = 61, - [BNXT_ULP_ACT_HID_25802] = 62, - [BNXT_ULP_ACT_HID_1db42] = 63, - [BNXT_ULP_ACT_HID_21b42] = 64, - [BNXT_ULP_ACT_HID_25b42] = 65, - [BNXT_ULP_ACT_HID_1dbc2] = 66, - [BNXT_ULP_ACT_HID_21bc2] = 67, - [BNXT_ULP_ACT_HID_25bc2] = 68, - [BNXT_ULP_ACT_HID_fce0] = 69, - [BNXT_ULP_ACT_HID_13ce0] = 70, - [BNXT_ULP_ACT_HID_17ce0] = 71, - [BNXT_ULP_ACT_HID_fd60] = 72, - [BNXT_ULP_ACT_HID_13d60] = 73, - [BNXT_ULP_ACT_HID_17d60] = 74, - [BNXT_ULP_ACT_HID_e0a0] = 75, - [BNXT_ULP_ACT_HID_120a0] = 76, - [BNXT_ULP_ACT_HID_160a0] = 77, - [BNXT_ULP_ACT_HID_e120] = 78, - [BNXT_ULP_ACT_HID_12120] = 79, - [BNXT_ULP_ACT_HID_16120] = 80, - [BNXT_ULP_ACT_HID_32061] = 81, - [BNXT_ULP_ACT_HID_320e1] = 82, - [BNXT_ULP_ACT_HID_388a] = 83, - [BNXT_ULP_ACT_HID_4000] = 84, - [BNXT_ULP_ACT_HID_8000] = 85, - [BNXT_ULP_ACT_HID_c000] = 86, - [BNXT_ULP_ACT_HID_4080] = 87, - [BNXT_ULP_ACT_HID_8080] = 88, - [BNXT_ULP_ACT_HID_c080] = 89, - [BNXT_ULP_ACT_HID_8880] = 90, - [BNXT_ULP_ACT_HID_22100] = 91, - [BNXT_ULP_ACT_HID_11100] = 92, - [BNXT_ULP_ACT_HID_6420] = 93, - [BNXT_ULP_ACT_HID_1fca0] = 94, - [BNXT_ULP_ACT_HID_19980] = 95, - [BNXT_ULP_ACT_HID_28520] = 96, - [BNXT_ULP_ACT_HID_c880] = 97, - [BNXT_ULP_ACT_HID_26100] = 98, - [BNXT_ULP_ACT_HID_15100] = 99, - [BNXT_ULP_ACT_HID_a420] = 100, - [BNXT_ULP_ACT_HID_23ca0] = 101, - [BNXT_ULP_ACT_HID_1d980] = 102, - [BNXT_ULP_ACT_HID_2c520] = 103, - [BNXT_ULP_ACT_HID_10880] = 104, - [BNXT_ULP_ACT_HID_2a100] = 105, - [BNXT_ULP_ACT_HID_19100] = 106, - [BNXT_ULP_ACT_HID_e420] = 107, - [BNXT_ULP_ACT_HID_27ca0] = 108, - [BNXT_ULP_ACT_HID_21980] = 109, - [BNXT_ULP_ACT_HID_30520] = 110, - [BNXT_ULP_ACT_HID_14880] = 111, - [BNXT_ULP_ACT_HID_2e100] = 112, - [BNXT_ULP_ACT_HID_1d100] = 113, - [BNXT_ULP_ACT_HID_12420] = 114, - [BNXT_ULP_ACT_HID_2bca0] = 115, - [BNXT_ULP_ACT_HID_25980] = 116, - [BNXT_ULP_ACT_HID_34520] = 117, - [BNXT_ULP_ACT_HID_8900] = 118, - [BNXT_ULP_ACT_HID_22180] = 119, - [BNXT_ULP_ACT_HID_11180] = 120, - [BNXT_ULP_ACT_HID_64a0] = 121, - [BNXT_ULP_ACT_HID_1fd20] = 122, - [BNXT_ULP_ACT_HID_19a00] = 123, - [BNXT_ULP_ACT_HID_285a0] = 124, - [BNXT_ULP_ACT_HID_c900] = 125, - [BNXT_ULP_ACT_HID_26180] = 126, - [BNXT_ULP_ACT_HID_15180] = 127, - [BNXT_ULP_ACT_HID_a4a0] = 128, - [BNXT_ULP_ACT_HID_23d20] = 129, - [BNXT_ULP_ACT_HID_1da00] = 130, - [BNXT_ULP_ACT_HID_2c5a0] = 131, - [BNXT_ULP_ACT_HID_10900] = 132, - [BNXT_ULP_ACT_HID_2a180] = 133, - [BNXT_ULP_ACT_HID_19180] = 134, - [BNXT_ULP_ACT_HID_e4a0] = 135, - [BNXT_ULP_ACT_HID_27d20] = 136, - [BNXT_ULP_ACT_HID_21a00] = 137, - [BNXT_ULP_ACT_HID_305a0] = 138, - [BNXT_ULP_ACT_HID_14900] = 139, - [BNXT_ULP_ACT_HID_2e180] = 140, - [BNXT_ULP_ACT_HID_1d180] = 141, - [BNXT_ULP_ACT_HID_124a0] = 142, - [BNXT_ULP_ACT_HID_2bd20] = 143, - [BNXT_ULP_ACT_HID_25a00] = 144, - [BNXT_ULP_ACT_HID_345a0] = 145, - [BNXT_ULP_ACT_HID_154c0] = 146, - [BNXT_ULP_ACT_HID_2ed40] = 147, - [BNXT_ULP_ACT_HID_1dd40] = 148, - [BNXT_ULP_ACT_HID_13060] = 149, - [BNXT_ULP_ACT_HID_2c8e0] = 150, - [BNXT_ULP_ACT_HID_35160] = 151, - [BNXT_ULP_ACT_HID_15540] = 152, - [BNXT_ULP_ACT_HID_2edc0] = 153, - [BNXT_ULP_ACT_HID_1ddc0] = 154, - [BNXT_ULP_ACT_HID_130e0] = 155, - [BNXT_ULP_ACT_HID_2c960] = 156, - [BNXT_ULP_ACT_HID_351e0] = 157, - [BNXT_ULP_ACT_HID_194c0] = 158, - [BNXT_ULP_ACT_HID_32d40] = 159, - [BNXT_ULP_ACT_HID_21d40] = 160, - [BNXT_ULP_ACT_HID_17060] = 161, - [BNXT_ULP_ACT_HID_308e0] = 162, - [BNXT_ULP_ACT_HID_39160] = 163, - [BNXT_ULP_ACT_HID_19540] = 164, - [BNXT_ULP_ACT_HID_32dc0] = 165, - [BNXT_ULP_ACT_HID_21dc0] = 166, - [BNXT_ULP_ACT_HID_170e0] = 167, - [BNXT_ULP_ACT_HID_30960] = 168, - [BNXT_ULP_ACT_HID_391e0] = 169, - [BNXT_ULP_ACT_HID_1d4c0] = 170, - [BNXT_ULP_ACT_HID_36d40] = 171, - [BNXT_ULP_ACT_HID_25d40] = 172, - [BNXT_ULP_ACT_HID_1b060] = 173, - [BNXT_ULP_ACT_HID_348e0] = 174, - [BNXT_ULP_ACT_HID_3d160] = 175, - [BNXT_ULP_ACT_HID_1d540] = 176, - [BNXT_ULP_ACT_HID_36dc0] = 177, - [BNXT_ULP_ACT_HID_25dc0] = 178, - [BNXT_ULP_ACT_HID_1b0e0] = 179, - [BNXT_ULP_ACT_HID_34960] = 180, - [BNXT_ULP_ACT_HID_3d1e0] = 181, - [BNXT_ULP_ACT_HID_214c0] = 182, - [BNXT_ULP_ACT_HID_3ad40] = 183, - [BNXT_ULP_ACT_HID_29d40] = 184, - [BNXT_ULP_ACT_HID_1f060] = 185, - [BNXT_ULP_ACT_HID_388e0] = 186, - [BNXT_ULP_ACT_HID_3380] = 187, - [BNXT_ULP_ACT_HID_21540] = 188, - [BNXT_ULP_ACT_HID_3adc0] = 189, - [BNXT_ULP_ACT_HID_29dc0] = 190, - [BNXT_ULP_ACT_HID_1f0e0] = 191, - [BNXT_ULP_ACT_HID_38960] = 192, - [BNXT_ULP_ACT_HID_3400] = 193, - [BNXT_ULP_ACT_HID_1d742] = 194, - [BNXT_ULP_ACT_HID_21742] = 195, - [BNXT_ULP_ACT_HID_25742] = 196, - [BNXT_ULP_ACT_HID_1d7c2] = 197, - [BNXT_ULP_ACT_HID_217c2] = 198, - [BNXT_ULP_ACT_HID_257c2] = 199, - [BNXT_ULP_ACT_HID_21fc2] = 200, - [BNXT_ULP_ACT_HID_3b842] = 201, - [BNXT_ULP_ACT_HID_2a842] = 202, - [BNXT_ULP_ACT_HID_1fb62] = 203, - [BNXT_ULP_ACT_HID_393e2] = 204, - [BNXT_ULP_ACT_HID_330c2] = 205, - [BNXT_ULP_ACT_HID_3e82] = 206, - [BNXT_ULP_ACT_HID_25fc2] = 207, - [BNXT_ULP_ACT_HID_1a62] = 208, - [BNXT_ULP_ACT_HID_2e842] = 209, - [BNXT_ULP_ACT_HID_23b62] = 210, - [BNXT_ULP_ACT_HID_3d3e2] = 211, - [BNXT_ULP_ACT_HID_370c2] = 212, - [BNXT_ULP_ACT_HID_7e82] = 213, - [BNXT_ULP_ACT_HID_29fc2] = 214, - [BNXT_ULP_ACT_HID_5a62] = 215, - [BNXT_ULP_ACT_HID_32842] = 216, - [BNXT_ULP_ACT_HID_27b62] = 217, - [BNXT_ULP_ACT_HID_3602] = 218, - [BNXT_ULP_ACT_HID_3b0c2] = 219, - [BNXT_ULP_ACT_HID_be82] = 220, - [BNXT_ULP_ACT_HID_2dfc2] = 221, - [BNXT_ULP_ACT_HID_9a62] = 222, - [BNXT_ULP_ACT_HID_36842] = 223, - [BNXT_ULP_ACT_HID_2bb62] = 224, - [BNXT_ULP_ACT_HID_7602] = 225, - [BNXT_ULP_ACT_HID_12e2] = 226, - [BNXT_ULP_ACT_HID_fe82] = 227, - [BNXT_ULP_ACT_HID_22042] = 228, - [BNXT_ULP_ACT_HID_3b8c2] = 229, - [BNXT_ULP_ACT_HID_2a8c2] = 230, - [BNXT_ULP_ACT_HID_1fbe2] = 231, - [BNXT_ULP_ACT_HID_39462] = 232, - [BNXT_ULP_ACT_HID_33142] = 233, - [BNXT_ULP_ACT_HID_3f02] = 234, - [BNXT_ULP_ACT_HID_26042] = 235, - [BNXT_ULP_ACT_HID_1ae2] = 236, - [BNXT_ULP_ACT_HID_2e8c2] = 237, - [BNXT_ULP_ACT_HID_23be2] = 238, - [BNXT_ULP_ACT_HID_3d462] = 239, - [BNXT_ULP_ACT_HID_37142] = 240, - [BNXT_ULP_ACT_HID_7f02] = 241, - [BNXT_ULP_ACT_HID_2a042] = 242, - [BNXT_ULP_ACT_HID_5ae2] = 243, - [BNXT_ULP_ACT_HID_328c2] = 244, - [BNXT_ULP_ACT_HID_27be2] = 245, - [BNXT_ULP_ACT_HID_3682] = 246, - [BNXT_ULP_ACT_HID_3b142] = 247, - [BNXT_ULP_ACT_HID_bf02] = 248, - [BNXT_ULP_ACT_HID_2e042] = 249, - [BNXT_ULP_ACT_HID_9ae2] = 250, - [BNXT_ULP_ACT_HID_368c2] = 251, - [BNXT_ULP_ACT_HID_2bbe2] = 252, - [BNXT_ULP_ACT_HID_7682] = 253, - [BNXT_ULP_ACT_HID_1362] = 254, - [BNXT_ULP_ACT_HID_ff02] = 255, - [BNXT_ULP_ACT_HID_2ec02] = 256, - [BNXT_ULP_ACT_HID_a6a2] = 257, - [BNXT_ULP_ACT_HID_37482] = 258, - [BNXT_ULP_ACT_HID_2c7a2] = 259, - [BNXT_ULP_ACT_HID_8242] = 260, - [BNXT_ULP_ACT_HID_10ac2] = 261, - [BNXT_ULP_ACT_HID_2ec82] = 262, - [BNXT_ULP_ACT_HID_a722] = 263, - [BNXT_ULP_ACT_HID_37502] = 264, - [BNXT_ULP_ACT_HID_2c822] = 265, - [BNXT_ULP_ACT_HID_82c2] = 266, - [BNXT_ULP_ACT_HID_10b42] = 267, - [BNXT_ULP_ACT_HID_32c02] = 268, - [BNXT_ULP_ACT_HID_e6a2] = 269, - [BNXT_ULP_ACT_HID_3b482] = 270, - [BNXT_ULP_ACT_HID_307a2] = 271, - [BNXT_ULP_ACT_HID_c242] = 272, - [BNXT_ULP_ACT_HID_14ac2] = 273, - [BNXT_ULP_ACT_HID_32c82] = 274, - [BNXT_ULP_ACT_HID_e722] = 275, - [BNXT_ULP_ACT_HID_3b502] = 276, - [BNXT_ULP_ACT_HID_30822] = 277, - [BNXT_ULP_ACT_HID_c2c2] = 278, - [BNXT_ULP_ACT_HID_14b42] = 279, - [BNXT_ULP_ACT_HID_36c02] = 280, - [BNXT_ULP_ACT_HID_126a2] = 281, - [BNXT_ULP_ACT_HID_16a2] = 282, - [BNXT_ULP_ACT_HID_347a2] = 283, - [BNXT_ULP_ACT_HID_10242] = 284, - [BNXT_ULP_ACT_HID_18ac2] = 285, - [BNXT_ULP_ACT_HID_36c82] = 286, - [BNXT_ULP_ACT_HID_12722] = 287, - [BNXT_ULP_ACT_HID_1722] = 288, - [BNXT_ULP_ACT_HID_34822] = 289, - [BNXT_ULP_ACT_HID_102c2] = 290, - [BNXT_ULP_ACT_HID_18b42] = 291, - [BNXT_ULP_ACT_HID_3ac02] = 292, - [BNXT_ULP_ACT_HID_166a2] = 293, - [BNXT_ULP_ACT_HID_56a2] = 294, - [BNXT_ULP_ACT_HID_387a2] = 295, - [BNXT_ULP_ACT_HID_14242] = 296, - [BNXT_ULP_ACT_HID_1cac2] = 297, - [BNXT_ULP_ACT_HID_3ac82] = 298, - [BNXT_ULP_ACT_HID_16722] = 299, - [BNXT_ULP_ACT_HID_5722] = 300, - [BNXT_ULP_ACT_HID_38822] = 301, - [BNXT_ULP_ACT_HID_142c2] = 302, - [BNXT_ULP_ACT_HID_1cb42] = 303, - [BNXT_ULP_ACT_HID_12520] = 304, - [BNXT_ULP_ACT_HID_2bda0] = 305, - [BNXT_ULP_ACT_HID_1ada0] = 306, - [BNXT_ULP_ACT_HID_120c0] = 307, - [BNXT_ULP_ACT_HID_2b940] = 308, - [BNXT_ULP_ACT_HID_23620] = 309, - [BNXT_ULP_ACT_HID_321c0] = 310, - [BNXT_ULP_ACT_HID_125a0] = 311, - [BNXT_ULP_ACT_HID_2be20] = 312, - [BNXT_ULP_ACT_HID_1ae20] = 313, - [BNXT_ULP_ACT_HID_12140] = 314, - [BNXT_ULP_ACT_HID_2b9c0] = 315, - [BNXT_ULP_ACT_HID_236a0] = 316, - [BNXT_ULP_ACT_HID_32240] = 317, - [BNXT_ULP_ACT_HID_1f160] = 318, - [BNXT_ULP_ACT_HID_3a9e0] = 319, - [BNXT_ULP_ACT_HID_279e0] = 320, - [BNXT_ULP_ACT_HID_1ed00] = 321, - [BNXT_ULP_ACT_HID_36580] = 322, - [BNXT_ULP_ACT_HID_3020] = 323, - [BNXT_ULP_ACT_HID_1f1e0] = 324, - [BNXT_ULP_ACT_HID_3aa60] = 325, - [BNXT_ULP_ACT_HID_27a60] = 326, - [BNXT_ULP_ACT_HID_1ed80] = 327, - [BNXT_ULP_ACT_HID_36600] = 328, - [BNXT_ULP_ACT_HID_30a0] = 329, - [BNXT_ULP_ACT_HID_0100] = 330, - [BNXT_ULP_ACT_HID_0180] = 331, - [BNXT_ULP_ACT_HID_32e84] = 332, - [BNXT_ULP_ACT_HID_32f04] = 333, - [BNXT_ULP_ACT_HID_19842] = 334, - [BNXT_ULP_ACT_HID_198c2] = 335, - [BNXT_ULP_ACT_HID_e7e6] = 336, - [BNXT_ULP_ACT_HID_e866] = 337, - [BNXT_ULP_ACT_HID_a3e0] = 338, - [BNXT_ULP_ACT_HID_240e0] = 339, - [BNXT_ULP_ACT_HID_322c8] = 340, - [BNXT_ULP_ACT_HID_e228] = 341, - [BNXT_ULP_ACT_HID_36130] = 342, - [BNXT_ULP_ACT_HID_2e840] = 343, - [BNXT_ULP_ACT_HID_2e880] = 344, - [BNXT_ULP_ACT_HID_2e900] = 345, - [BNXT_ULP_ACT_HID_170c0] = 346, - [BNXT_ULP_ACT_HID_14ea0] = 347, - [BNXT_ULP_ACT_HID_3b480] = 348, - [BNXT_ULP_ACT_HID_23d00] = 349, - [BNXT_ULP_ACT_HID_21ae0] = 350, - [BNXT_ULP_ACT_HID_2e8c0] = 351, - [BNXT_ULP_ACT_HID_17140] = 352, - [BNXT_ULP_ACT_HID_14f20] = 353, - [BNXT_ULP_ACT_HID_3b500] = 354, - [BNXT_ULP_ACT_HID_23d80] = 355, - [BNXT_ULP_ACT_HID_21b60] = 356, - [BNXT_ULP_ACT_HID_a1a2] = 357, - [BNXT_ULP_ACT_HID_a1e2] = 358, - [BNXT_ULP_ACT_HID_a262] = 359, - [BNXT_ULP_ACT_HID_30802] = 360, - [BNXT_ULP_ACT_HID_2e5e2] = 361, - [BNXT_ULP_ACT_HID_16de2] = 362, - [BNXT_ULP_ACT_HID_3d442] = 363, - [BNXT_ULP_ACT_HID_3b222] = 364, - [BNXT_ULP_ACT_HID_a222] = 365, - [BNXT_ULP_ACT_HID_30882] = 366, - [BNXT_ULP_ACT_HID_2e662] = 367, - [BNXT_ULP_ACT_HID_16e62] = 368, - [BNXT_ULP_ACT_HID_3d4c2] = 369, - [BNXT_ULP_ACT_HID_3b2a2] = 370, - [BNXT_ULP_ACT_HID_3a4e0] = 371, - [BNXT_ULP_ACT_HID_3a520] = 372, - [BNXT_ULP_ACT_HID_3a5a0] = 373, - [BNXT_ULP_ACT_HID_22d60] = 374, - [BNXT_ULP_ACT_HID_1eb40] = 375, - [BNXT_ULP_ACT_HID_7340] = 376, - [BNXT_ULP_ACT_HID_2f9a0] = 377, - [BNXT_ULP_ACT_HID_2b780] = 378, - [BNXT_ULP_ACT_HID_3a560] = 379, - [BNXT_ULP_ACT_HID_22de0] = 380, - [BNXT_ULP_ACT_HID_1ebc0] = 381, - [BNXT_ULP_ACT_HID_73c0] = 382, - [BNXT_ULP_ACT_HID_2fa20] = 383, - [BNXT_ULP_ACT_HID_2b800] = 384, - [BNXT_ULP_ACT_HID_32840] = 385, - [BNXT_ULP_ACT_HID_36840] = 386, - [BNXT_ULP_ACT_HID_3a840] = 387, - [BNXT_ULP_ACT_HID_328c0] = 388, - [BNXT_ULP_ACT_HID_368c0] = 389, - [BNXT_ULP_ACT_HID_3a8c0] = 390, - [BNXT_ULP_ACT_HID_370c0] = 391, - [BNXT_ULP_ACT_HID_12b60] = 392, - [BNXT_ULP_ACT_HID_1b60] = 393, - [BNXT_ULP_ACT_HID_34c60] = 394, - [BNXT_ULP_ACT_HID_10700] = 395, - [BNXT_ULP_ACT_HID_18f80] = 396, - [BNXT_ULP_ACT_HID_3b0c0] = 397, - [BNXT_ULP_ACT_HID_16b60] = 398, - [BNXT_ULP_ACT_HID_5b60] = 399, - [BNXT_ULP_ACT_HID_38c60] = 400, - [BNXT_ULP_ACT_HID_14700] = 401, - [BNXT_ULP_ACT_HID_1cf80] = 402, - [BNXT_ULP_ACT_HID_12e0] = 403, - [BNXT_ULP_ACT_HID_1ab60] = 404, - [BNXT_ULP_ACT_HID_9b60] = 405, - [BNXT_ULP_ACT_HID_3cc60] = 406, - [BNXT_ULP_ACT_HID_18700] = 407, - [BNXT_ULP_ACT_HID_20f80] = 408, - [BNXT_ULP_ACT_HID_52e0] = 409, - [BNXT_ULP_ACT_HID_1eb60] = 410, - [BNXT_ULP_ACT_HID_db60] = 411, - [BNXT_ULP_ACT_HID_2e80] = 412, - [BNXT_ULP_ACT_HID_1c700] = 413, - [BNXT_ULP_ACT_HID_24f80] = 414, - [BNXT_ULP_ACT_HID_37140] = 415, - [BNXT_ULP_ACT_HID_12be0] = 416, - [BNXT_ULP_ACT_HID_1be0] = 417, - [BNXT_ULP_ACT_HID_34ce0] = 418, - [BNXT_ULP_ACT_HID_10780] = 419, - [BNXT_ULP_ACT_HID_19000] = 420, - [BNXT_ULP_ACT_HID_3b140] = 421, - [BNXT_ULP_ACT_HID_16be0] = 422, - [BNXT_ULP_ACT_HID_5be0] = 423, - [BNXT_ULP_ACT_HID_38ce0] = 424, - [BNXT_ULP_ACT_HID_14780] = 425, - [BNXT_ULP_ACT_HID_1d000] = 426, - [BNXT_ULP_ACT_HID_1360] = 427, - [BNXT_ULP_ACT_HID_1abe0] = 428, - [BNXT_ULP_ACT_HID_9be0] = 429, - [BNXT_ULP_ACT_HID_3cce0] = 430, - [BNXT_ULP_ACT_HID_18780] = 431, - [BNXT_ULP_ACT_HID_21000] = 432, - [BNXT_ULP_ACT_HID_5360] = 433, - [BNXT_ULP_ACT_HID_1ebe0] = 434, - [BNXT_ULP_ACT_HID_dbe0] = 435, - [BNXT_ULP_ACT_HID_2f00] = 436, - [BNXT_ULP_ACT_HID_1c780] = 437, - [BNXT_ULP_ACT_HID_25000] = 438, - [BNXT_ULP_ACT_HID_5f20] = 439, - [BNXT_ULP_ACT_HID_1f7a0] = 440, - [BNXT_ULP_ACT_HID_e7a0] = 441, - [BNXT_ULP_ACT_HID_3ac0] = 442, - [BNXT_ULP_ACT_HID_1d340] = 443, - [BNXT_ULP_ACT_HID_25bc0] = 444, - [BNXT_ULP_ACT_HID_5fa0] = 445, - [BNXT_ULP_ACT_HID_1f820] = 446, - [BNXT_ULP_ACT_HID_e820] = 447, - [BNXT_ULP_ACT_HID_3b40] = 448, - [BNXT_ULP_ACT_HID_1d3c0] = 449, - [BNXT_ULP_ACT_HID_25c40] = 450, - [BNXT_ULP_ACT_HID_237a0] = 451, - [BNXT_ULP_ACT_HID_127a0] = 452, - [BNXT_ULP_ACT_HID_7ac0] = 453, - [BNXT_ULP_ACT_HID_9f20] = 454, - [BNXT_ULP_ACT_HID_21340] = 455, - [BNXT_ULP_ACT_HID_29bc0] = 456, - [BNXT_ULP_ACT_HID_9fa0] = 457, - [BNXT_ULP_ACT_HID_23820] = 458, - [BNXT_ULP_ACT_HID_12820] = 459, - [BNXT_ULP_ACT_HID_7b40] = 460, - [BNXT_ULP_ACT_HID_213c0] = 461, - [BNXT_ULP_ACT_HID_29c40] = 462, - [BNXT_ULP_ACT_HID_df20] = 463, - [BNXT_ULP_ACT_HID_277a0] = 464, - [BNXT_ULP_ACT_HID_167a0] = 465, - [BNXT_ULP_ACT_HID_bac0] = 466, - [BNXT_ULP_ACT_HID_25340] = 467, - [BNXT_ULP_ACT_HID_2dbc0] = 468, - [BNXT_ULP_ACT_HID_dfa0] = 469, - [BNXT_ULP_ACT_HID_27820] = 470, - [BNXT_ULP_ACT_HID_16820] = 471, - [BNXT_ULP_ACT_HID_bb40] = 472, - [BNXT_ULP_ACT_HID_253c0] = 473, - [BNXT_ULP_ACT_HID_2dc40] = 474, - [BNXT_ULP_ACT_HID_11f20] = 475, - [BNXT_ULP_ACT_HID_2b7a0] = 476, - [BNXT_ULP_ACT_HID_1a7a0] = 477, - [BNXT_ULP_ACT_HID_fac0] = 478, - [BNXT_ULP_ACT_HID_29340] = 479, - [BNXT_ULP_ACT_HID_31bc0] = 480, - [BNXT_ULP_ACT_HID_11fa0] = 481, - [BNXT_ULP_ACT_HID_2b820] = 482, - [BNXT_ULP_ACT_HID_1a820] = 483, - [BNXT_ULP_ACT_HID_fb40] = 484, - [BNXT_ULP_ACT_HID_293c0] = 485, - [BNXT_ULP_ACT_HID_31c40] = 486, - [BNXT_ULP_ACT_HID_e1a2] = 487, - [BNXT_ULP_ACT_HID_121a2] = 488, - [BNXT_ULP_ACT_HID_161a2] = 489, - [BNXT_ULP_ACT_HID_e222] = 490, - [BNXT_ULP_ACT_HID_12222] = 491, - [BNXT_ULP_ACT_HID_16222] = 492, - [BNXT_ULP_ACT_HID_12a22] = 493, - [BNXT_ULP_ACT_HID_2c2a2] = 494, - [BNXT_ULP_ACT_HID_1b2a2] = 495, - [BNXT_ULP_ACT_HID_105c2] = 496, - [BNXT_ULP_ACT_HID_29e42] = 497, - [BNXT_ULP_ACT_HID_326c2] = 498, - [BNXT_ULP_ACT_HID_16a22] = 499, - [BNXT_ULP_ACT_HID_302a2] = 500, - [BNXT_ULP_ACT_HID_1f2a2] = 501, - [BNXT_ULP_ACT_HID_145c2] = 502, - [BNXT_ULP_ACT_HID_2de42] = 503, - [BNXT_ULP_ACT_HID_366c2] = 504, - [BNXT_ULP_ACT_HID_1aa22] = 505, - [BNXT_ULP_ACT_HID_342a2] = 506, - [BNXT_ULP_ACT_HID_232a2] = 507, - [BNXT_ULP_ACT_HID_185c2] = 508, - [BNXT_ULP_ACT_HID_31e42] = 509, - [BNXT_ULP_ACT_HID_3a6c2] = 510, - [BNXT_ULP_ACT_HID_1ea22] = 511, - [BNXT_ULP_ACT_HID_382a2] = 512, - [BNXT_ULP_ACT_HID_272a2] = 513, - [BNXT_ULP_ACT_HID_1c5c2] = 514, - [BNXT_ULP_ACT_HID_35e42] = 515, - [BNXT_ULP_ACT_HID_08e2] = 516, - [BNXT_ULP_ACT_HID_12aa2] = 517, - [BNXT_ULP_ACT_HID_2c322] = 518, - [BNXT_ULP_ACT_HID_1b322] = 519, - [BNXT_ULP_ACT_HID_10642] = 520, - [BNXT_ULP_ACT_HID_29ec2] = 521, - [BNXT_ULP_ACT_HID_32742] = 522, - [BNXT_ULP_ACT_HID_16aa2] = 523, - [BNXT_ULP_ACT_HID_30322] = 524, - [BNXT_ULP_ACT_HID_1f322] = 525, - [BNXT_ULP_ACT_HID_14642] = 526, - [BNXT_ULP_ACT_HID_2dec2] = 527, - [BNXT_ULP_ACT_HID_36742] = 528, - [BNXT_ULP_ACT_HID_1aaa2] = 529, - [BNXT_ULP_ACT_HID_34322] = 530, - [BNXT_ULP_ACT_HID_23322] = 531, - [BNXT_ULP_ACT_HID_18642] = 532, - [BNXT_ULP_ACT_HID_31ec2] = 533, - [BNXT_ULP_ACT_HID_3a742] = 534, - [BNXT_ULP_ACT_HID_1eaa2] = 535, - [BNXT_ULP_ACT_HID_38322] = 536, - [BNXT_ULP_ACT_HID_27322] = 537, - [BNXT_ULP_ACT_HID_1c642] = 538, - [BNXT_ULP_ACT_HID_35ec2] = 539, - [BNXT_ULP_ACT_HID_0962] = 540, - [BNXT_ULP_ACT_HID_1f662] = 541, - [BNXT_ULP_ACT_HID_38ee2] = 542, - [BNXT_ULP_ACT_HID_27ee2] = 543, - [BNXT_ULP_ACT_HID_1d202] = 544, - [BNXT_ULP_ACT_HID_36a82] = 545, - [BNXT_ULP_ACT_HID_1522] = 546, - [BNXT_ULP_ACT_HID_1f6e2] = 547, - [BNXT_ULP_ACT_HID_38f62] = 548, - [BNXT_ULP_ACT_HID_27f62] = 549, - [BNXT_ULP_ACT_HID_1d282] = 550, - [BNXT_ULP_ACT_HID_36b02] = 551, - [BNXT_ULP_ACT_HID_15a2] = 552, - [BNXT_ULP_ACT_HID_3cee2] = 553, - [BNXT_ULP_ACT_HID_2bee2] = 554, - [BNXT_ULP_ACT_HID_21202] = 555, - [BNXT_ULP_ACT_HID_23662] = 556, - [BNXT_ULP_ACT_HID_3aa82] = 557, - [BNXT_ULP_ACT_HID_5522] = 558, - [BNXT_ULP_ACT_HID_236e2] = 559, - [BNXT_ULP_ACT_HID_3cf62] = 560, - [BNXT_ULP_ACT_HID_2bf62] = 561, - [BNXT_ULP_ACT_HID_21282] = 562, - [BNXT_ULP_ACT_HID_3ab02] = 563, - [BNXT_ULP_ACT_HID_55a2] = 564, - [BNXT_ULP_ACT_HID_27662] = 565, - [BNXT_ULP_ACT_HID_3102] = 566, - [BNXT_ULP_ACT_HID_2fee2] = 567, - [BNXT_ULP_ACT_HID_25202] = 568, - [BNXT_ULP_ACT_HID_0ca2] = 569, - [BNXT_ULP_ACT_HID_9522] = 570, - [BNXT_ULP_ACT_HID_276e2] = 571, - [BNXT_ULP_ACT_HID_3182] = 572, - [BNXT_ULP_ACT_HID_2ff62] = 573, - [BNXT_ULP_ACT_HID_25282] = 574, - [BNXT_ULP_ACT_HID_0d22] = 575, - [BNXT_ULP_ACT_HID_95a2] = 576, - [BNXT_ULP_ACT_HID_2b662] = 577, - [BNXT_ULP_ACT_HID_7102] = 578, - [BNXT_ULP_ACT_HID_33ee2] = 579, - [BNXT_ULP_ACT_HID_29202] = 580, - [BNXT_ULP_ACT_HID_4ca2] = 581, - [BNXT_ULP_ACT_HID_d522] = 582, - [BNXT_ULP_ACT_HID_2b6e2] = 583, - [BNXT_ULP_ACT_HID_7182] = 584, - [BNXT_ULP_ACT_HID_33f62] = 585, - [BNXT_ULP_ACT_HID_29282] = 586, - [BNXT_ULP_ACT_HID_4d22] = 587, - [BNXT_ULP_ACT_HID_d5a2] = 588, - [BNXT_ULP_ACT_HID_3e4e0] = 589, - [BNXT_ULP_ACT_HID_2700] = 590, - [BNXT_ULP_ACT_HID_6700] = 591, - [BNXT_ULP_ACT_HID_3e560] = 592, - [BNXT_ULP_ACT_HID_2780] = 593, - [BNXT_ULP_ACT_HID_6780] = 594, - [BNXT_ULP_ACT_HID_2f80] = 595, - [BNXT_ULP_ACT_HID_1e800] = 596, - [BNXT_ULP_ACT_HID_b800] = 597, - [BNXT_ULP_ACT_HID_2b20] = 598, - [BNXT_ULP_ACT_HID_1a3a0] = 599, - [BNXT_ULP_ACT_HID_22c20] = 600, - [BNXT_ULP_ACT_HID_6f80] = 601, - [BNXT_ULP_ACT_HID_22800] = 602, - [BNXT_ULP_ACT_HID_f800] = 603, - [BNXT_ULP_ACT_HID_6b20] = 604, - [BNXT_ULP_ACT_HID_1e3a0] = 605, - [BNXT_ULP_ACT_HID_26c20] = 606, - [BNXT_ULP_ACT_HID_af80] = 607, - [BNXT_ULP_ACT_HID_26800] = 608, - [BNXT_ULP_ACT_HID_13800] = 609, - [BNXT_ULP_ACT_HID_ab20] = 610, - [BNXT_ULP_ACT_HID_223a0] = 611, - [BNXT_ULP_ACT_HID_2ac20] = 612, - [BNXT_ULP_ACT_HID_ef80] = 613, - [BNXT_ULP_ACT_HID_2a800] = 614, - [BNXT_ULP_ACT_HID_17800] = 615, - [BNXT_ULP_ACT_HID_eb20] = 616, - [BNXT_ULP_ACT_HID_263a0] = 617, - [BNXT_ULP_ACT_HID_2ec20] = 618, - [BNXT_ULP_ACT_HID_3000] = 619, - [BNXT_ULP_ACT_HID_1e880] = 620, - [BNXT_ULP_ACT_HID_b880] = 621, - [BNXT_ULP_ACT_HID_2ba0] = 622, - [BNXT_ULP_ACT_HID_1a420] = 623, - [BNXT_ULP_ACT_HID_22ca0] = 624, - [BNXT_ULP_ACT_HID_7000] = 625, - [BNXT_ULP_ACT_HID_22880] = 626, - [BNXT_ULP_ACT_HID_f880] = 627, - [BNXT_ULP_ACT_HID_6ba0] = 628, - [BNXT_ULP_ACT_HID_1e420] = 629, - [BNXT_ULP_ACT_HID_26ca0] = 630, - [BNXT_ULP_ACT_HID_b000] = 631, - [BNXT_ULP_ACT_HID_26880] = 632, - [BNXT_ULP_ACT_HID_13880] = 633, - [BNXT_ULP_ACT_HID_aba0] = 634, - [BNXT_ULP_ACT_HID_22420] = 635, - [BNXT_ULP_ACT_HID_2aca0] = 636, - [BNXT_ULP_ACT_HID_f000] = 637, - [BNXT_ULP_ACT_HID_2a880] = 638, - [BNXT_ULP_ACT_HID_17880] = 639, - [BNXT_ULP_ACT_HID_eba0] = 640, - [BNXT_ULP_ACT_HID_26420] = 641, - [BNXT_ULP_ACT_HID_2eca0] = 642, - [BNXT_ULP_ACT_HID_fbc0] = 643, - [BNXT_ULP_ACT_HID_2b440] = 644, - [BNXT_ULP_ACT_HID_1a440] = 645, - [BNXT_ULP_ACT_HID_f760] = 646, - [BNXT_ULP_ACT_HID_26fe0] = 647, - [BNXT_ULP_ACT_HID_2f860] = 648, - [BNXT_ULP_ACT_HID_fc40] = 649, - [BNXT_ULP_ACT_HID_2b4c0] = 650, - [BNXT_ULP_ACT_HID_1a4c0] = 651, - [BNXT_ULP_ACT_HID_f7e0] = 652, - [BNXT_ULP_ACT_HID_27060] = 653, - [BNXT_ULP_ACT_HID_2f8e0] = 654, - [BNXT_ULP_ACT_HID_2f440] = 655, - [BNXT_ULP_ACT_HID_1e440] = 656, - [BNXT_ULP_ACT_HID_13760] = 657, - [BNXT_ULP_ACT_HID_13bc0] = 658, - [BNXT_ULP_ACT_HID_2afe0] = 659, - [BNXT_ULP_ACT_HID_33860] = 660, - [BNXT_ULP_ACT_HID_13c40] = 661, - [BNXT_ULP_ACT_HID_2f4c0] = 662, - [BNXT_ULP_ACT_HID_1e4c0] = 663, - [BNXT_ULP_ACT_HID_137e0] = 664, - [BNXT_ULP_ACT_HID_2b060] = 665, - [BNXT_ULP_ACT_HID_338e0] = 666, - [BNXT_ULP_ACT_HID_17bc0] = 667, - [BNXT_ULP_ACT_HID_33440] = 668, - [BNXT_ULP_ACT_HID_22440] = 669, - [BNXT_ULP_ACT_HID_17760] = 670, - [BNXT_ULP_ACT_HID_2efe0] = 671, - [BNXT_ULP_ACT_HID_37860] = 672, - [BNXT_ULP_ACT_HID_17c40] = 673, - [BNXT_ULP_ACT_HID_334c0] = 674, - [BNXT_ULP_ACT_HID_224c0] = 675, - [BNXT_ULP_ACT_HID_177e0] = 676, - [BNXT_ULP_ACT_HID_2f060] = 677, - [BNXT_ULP_ACT_HID_378e0] = 678, - [BNXT_ULP_ACT_HID_1bbc0] = 679, - [BNXT_ULP_ACT_HID_37440] = 680, - [BNXT_ULP_ACT_HID_26440] = 681, - [BNXT_ULP_ACT_HID_1b760] = 682, - [BNXT_ULP_ACT_HID_32fe0] = 683, - [BNXT_ULP_ACT_HID_3b860] = 684, - [BNXT_ULP_ACT_HID_1bc40] = 685, - [BNXT_ULP_ACT_HID_374c0] = 686, - [BNXT_ULP_ACT_HID_264c0] = 687, - [BNXT_ULP_ACT_HID_1b7e0] = 688, - [BNXT_ULP_ACT_HID_33060] = 689, - [BNXT_ULP_ACT_HID_3b8e0] = 690, - [BNXT_ULP_ACT_HID_18e80] = 691, - [BNXT_ULP_ACT_HID_18f00] = 692, - [BNXT_ULP_ACT_HID_1ce80] = 693, - [BNXT_ULP_ACT_HID_1cf00] = 694, - [BNXT_ULP_ACT_HID_20e80] = 695, - [BNXT_ULP_ACT_HID_20f00] = 696, - [BNXT_ULP_ACT_HID_24e80] = 697, - [BNXT_ULP_ACT_HID_24f00] = 698, - [BNXT_ULP_ACT_HID_325c2] = 699, - [BNXT_ULP_ACT_HID_32642] = 700, - [BNXT_ULP_ACT_HID_365c2] = 701, - [BNXT_ULP_ACT_HID_36642] = 702, - [BNXT_ULP_ACT_HID_3a5c2] = 703, - [BNXT_ULP_ACT_HID_3a642] = 704, - [BNXT_ULP_ACT_HID_07e2] = 705, - [BNXT_ULP_ACT_HID_0862] = 706, - [BNXT_ULP_ACT_HID_22b20] = 707, - [BNXT_ULP_ACT_HID_22ba0] = 708, - [BNXT_ULP_ACT_HID_26b20] = 709, - [BNXT_ULP_ACT_HID_26ba0] = 710, - [BNXT_ULP_ACT_HID_2ab20] = 711, - [BNXT_ULP_ACT_HID_2aba0] = 712, - [BNXT_ULP_ACT_HID_2eb20] = 713, - [BNXT_ULP_ACT_HID_2eba0] = 714, - [BNXT_ULP_ACT_HID_199e0] = 715, - [BNXT_ULP_ACT_HID_19960] = 716, - [BNXT_ULP_ACT_HID_33122] = 717, - [BNXT_ULP_ACT_HID_331a2] = 718, - [BNXT_ULP_ACT_HID_23580] = 719, - [BNXT_ULP_ACT_HID_23700] = 720, - [BNXT_ULP_ACT_HID_db61] = 721, - [BNXT_ULP_ACT_HID_dbe1] = 722, - [BNXT_ULP_ACT_HID_320ca] = 723 -}; - /* Array for the act matcher list */ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [1] = { - .act_hid = BNXT_ULP_ACT_HID_0000, - .act_pattern_id = 0, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [2] = { - .act_hid = BNXT_ULP_ACT_HID_0040, - .act_pattern_id = 1, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_DROP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [3] = { - .act_hid = BNXT_ULP_ACT_HID_10000, - .act_pattern_id = 2, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_POP_VLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [4] = { - .act_hid = BNXT_ULP_ACT_HID_cc40, - .act_pattern_id = 3, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [5] = { - .act_hid = BNXT_ULP_ACT_HID_0400, - .act_pattern_id = 4, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_VXLAN_DECAP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [6] = { - .act_hid = BNXT_ULP_ACT_HID_1cc40, - .act_pattern_id = 5, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_POP_VLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [7] = { - .act_hid = BNXT_ULP_ACT_HID_d040, - .act_pattern_id = 6, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_VXLAN_DECAP | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [8] = { - .act_hid = BNXT_ULP_ACT_HID_0080, - .act_pattern_id = 7, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [9] = { - .act_hid = BNXT_ULP_ACT_HID_0200, - .act_pattern_id = 8, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_METER | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [10] = { - .act_hid = BNXT_ULP_ACT_HID_0280, - .act_pattern_id = 9, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_METER | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [11] = { - .act_hid = BNXT_ULP_ACT_HID_00c0, - .act_pattern_id = 10, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_DROP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [12] = { - .act_hid = BNXT_ULP_ACT_HID_10080, - .act_pattern_id = 11, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_POP_VLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [13] = { - .act_hid = BNXT_ULP_ACT_HID_ccc0, - .act_pattern_id = 12, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [14] = { - .act_hid = BNXT_ULP_ACT_HID_0480, - .act_pattern_id = 13, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_VXLAN_DECAP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [15] = { - .act_hid = BNXT_ULP_ACT_HID_1ccc0, - .act_pattern_id = 14, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_POP_VLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [16] = { - .act_hid = BNXT_ULP_ACT_HID_d0c0, - .act_pattern_id = 15, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_VXLAN_DECAP | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [17] = { - .act_hid = BNXT_ULP_ACT_HID_19742, - .act_pattern_id = 16, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [18] = { - .act_hid = BNXT_ULP_ACT_HID_19782, - .act_pattern_id = 17, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_DROP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [19] = { - .act_hid = BNXT_ULP_ACT_HID_29742, - .act_pattern_id = 18, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_POP_VLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [20] = { - .act_hid = BNXT_ULP_ACT_HID_26382, - .act_pattern_id = 19, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [21] = { - .act_hid = BNXT_ULP_ACT_HID_19b42, - .act_pattern_id = 20, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_VXLAN_DECAP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [22] = { - .act_hid = BNXT_ULP_ACT_HID_36382, - .act_pattern_id = 21, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_POP_VLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [23] = { - .act_hid = BNXT_ULP_ACT_HID_26782, - .act_pattern_id = 22, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_VXLAN_DECAP | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [24] = { - .act_hid = BNXT_ULP_ACT_HID_197c2, - .act_pattern_id = 23, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [25] = { - .act_hid = BNXT_ULP_ACT_HID_19802, - .act_pattern_id = 24, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_DROP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [26] = { - .act_hid = BNXT_ULP_ACT_HID_297c2, - .act_pattern_id = 25, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_POP_VLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [27] = { - .act_hid = BNXT_ULP_ACT_HID_26402, - .act_pattern_id = 26, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [28] = { - .act_hid = BNXT_ULP_ACT_HID_19bc2, - .act_pattern_id = 27, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_VXLAN_DECAP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [29] = { - .act_hid = BNXT_ULP_ACT_HID_36402, - .act_pattern_id = 28, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_POP_VLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [30] = { - .act_hid = BNXT_ULP_ACT_HID_26802, - .act_pattern_id = 29, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_VXLAN_DECAP | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [31] = { - .act_hid = BNXT_ULP_ACT_HID_bca0, - .act_pattern_id = 30, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [32] = { - .act_hid = BNXT_ULP_ACT_HID_bce0, - .act_pattern_id = 31, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_DROP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [33] = { - .act_hid = BNXT_ULP_ACT_HID_1bca0, - .act_pattern_id = 32, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_POP_VLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [34] = { - .act_hid = BNXT_ULP_ACT_HID_168e0, - .act_pattern_id = 33, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [35] = { - .act_hid = BNXT_ULP_ACT_HID_a0a0, - .act_pattern_id = 34, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_VXLAN_DECAP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [36] = { - .act_hid = BNXT_ULP_ACT_HID_268e0, - .act_pattern_id = 35, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_POP_VLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [37] = { - .act_hid = BNXT_ULP_ACT_HID_16ce0, - .act_pattern_id = 36, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_VXLAN_DECAP | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [38] = { - .act_hid = BNXT_ULP_ACT_HID_bd20, - .act_pattern_id = 37, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [39] = { - .act_hid = BNXT_ULP_ACT_HID_bd60, - .act_pattern_id = 38, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_COUNT | + .act_bitmap = { .bits = BNXT_ULP_ACT_BIT_DROP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [40] = { - .act_hid = BNXT_ULP_ACT_HID_1bd20, - .act_pattern_id = 39, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_POP_VLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [41] = { - .act_hid = BNXT_ULP_ACT_HID_16960, - .act_pattern_id = 40, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [42] = { - .act_hid = BNXT_ULP_ACT_HID_a120, - .act_pattern_id = 41, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_VXLAN_DECAP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [43] = { - .act_hid = BNXT_ULP_ACT_HID_26960, - .act_pattern_id = 42, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_DEC_TTL | BNXT_ULP_ACT_BIT_POP_VLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [44] = { - .act_hid = BNXT_ULP_ACT_HID_16d60, - .act_pattern_id = 43, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_VXLAN_DECAP | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [45] = { - .act_hid = BNXT_ULP_ACT_HID_4040, - .act_pattern_id = 44, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DROP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [46] = { - .act_hid = BNXT_ULP_ACT_HID_8040, - .act_pattern_id = 45, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DROP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [47] = { - .act_hid = BNXT_ULP_ACT_HID_c040, - .act_pattern_id = 46, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DROP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [48] = { - .act_hid = BNXT_ULP_ACT_HID_40c0, - .act_pattern_id = 47, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_DROP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [49] = { - .act_hid = BNXT_ULP_ACT_HID_80c0, - .act_pattern_id = 48, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_DROP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [50] = { - .act_hid = BNXT_ULP_ACT_HID_c0c0, - .act_pattern_id = 49, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_DROP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [51] = { - .act_hid = BNXT_ULP_ACT_HID_4400, - .act_pattern_id = 50, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_VXLAN_DECAP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [52] = { - .act_hid = BNXT_ULP_ACT_HID_8400, - .act_pattern_id = 51, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_VXLAN_DECAP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [53] = { - .act_hid = BNXT_ULP_ACT_HID_c400, - .act_pattern_id = 52, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_VXLAN_DECAP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [54] = { - .act_hid = BNXT_ULP_ACT_HID_4480, - .act_pattern_id = 53, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_VXLAN_DECAP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [55] = { - .act_hid = BNXT_ULP_ACT_HID_8480, - .act_pattern_id = 54, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_VXLAN_DECAP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [56] = { - .act_hid = BNXT_ULP_ACT_HID_c480, - .act_pattern_id = 55, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_VXLAN_DECAP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [57] = { - .act_hid = BNXT_ULP_ACT_HID_1d782, - .act_pattern_id = 56, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DROP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [58] = { - .act_hid = BNXT_ULP_ACT_HID_21782, - .act_pattern_id = 57, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DROP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [59] = { - .act_hid = BNXT_ULP_ACT_HID_25782, - .act_pattern_id = 58, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DROP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [60] = { - .act_hid = BNXT_ULP_ACT_HID_1d802, - .act_pattern_id = 59, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_DROP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [61] = { - .act_hid = BNXT_ULP_ACT_HID_21802, - .act_pattern_id = 60, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_DROP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [62] = { - .act_hid = BNXT_ULP_ACT_HID_25802, - .act_pattern_id = 61, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_DROP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [63] = { - .act_hid = BNXT_ULP_ACT_HID_1db42, - .act_pattern_id = 62, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_VXLAN_DECAP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [64] = { - .act_hid = BNXT_ULP_ACT_HID_21b42, - .act_pattern_id = 63, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_VXLAN_DECAP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [65] = { - .act_hid = BNXT_ULP_ACT_HID_25b42, - .act_pattern_id = 64, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_VXLAN_DECAP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [66] = { - .act_hid = BNXT_ULP_ACT_HID_1dbc2, - .act_pattern_id = 65, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_VXLAN_DECAP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [67] = { - .act_hid = BNXT_ULP_ACT_HID_21bc2, - .act_pattern_id = 66, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_VXLAN_DECAP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [68] = { - .act_hid = BNXT_ULP_ACT_HID_25bc2, - .act_pattern_id = 67, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_VXLAN_DECAP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [69] = { - .act_hid = BNXT_ULP_ACT_HID_fce0, - .act_pattern_id = 68, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DROP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [70] = { - .act_hid = BNXT_ULP_ACT_HID_13ce0, - .act_pattern_id = 69, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DROP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [71] = { - .act_hid = BNXT_ULP_ACT_HID_17ce0, - .act_pattern_id = 70, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DROP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [72] = { - .act_hid = BNXT_ULP_ACT_HID_fd60, - .act_pattern_id = 71, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_DROP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [73] = { - .act_hid = BNXT_ULP_ACT_HID_13d60, - .act_pattern_id = 72, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_DROP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [74] = { - .act_hid = BNXT_ULP_ACT_HID_17d60, - .act_pattern_id = 73, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_DROP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [75] = { - .act_hid = BNXT_ULP_ACT_HID_e0a0, - .act_pattern_id = 74, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_VXLAN_DECAP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [76] = { - .act_hid = BNXT_ULP_ACT_HID_120a0, - .act_pattern_id = 75, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_VXLAN_DECAP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [77] = { - .act_hid = BNXT_ULP_ACT_HID_160a0, - .act_pattern_id = 76, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_VXLAN_DECAP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [78] = { - .act_hid = BNXT_ULP_ACT_HID_e120, - .act_pattern_id = 77, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_VXLAN_DECAP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [79] = { - .act_hid = BNXT_ULP_ACT_HID_12120, - .act_pattern_id = 78, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_VXLAN_DECAP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [80] = { - .act_hid = BNXT_ULP_ACT_HID_16120, - .act_pattern_id = 79, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_VXLAN_DECAP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 - }, - [81] = { - .act_hid = BNXT_ULP_ACT_HID_32061, - .act_pattern_id = 0, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED | - BNXT_ULP_ACT_BIT_SAMPLE | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 2 - }, - [82] = { - .act_hid = BNXT_ULP_ACT_HID_320e1, - .act_pattern_id = 1, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED | - BNXT_ULP_ACT_BIT_SAMPLE | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 2 - }, - [83] = { - .act_hid = BNXT_ULP_ACT_HID_388a, - .act_pattern_id = 2, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_DELETE | - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 2 - }, - [84] = { - .act_hid = BNXT_ULP_ACT_HID_4000, - .act_pattern_id = 0, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [85] = { - .act_hid = BNXT_ULP_ACT_HID_8000, - .act_pattern_id = 1, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [86] = { - .act_hid = BNXT_ULP_ACT_HID_c000, - .act_pattern_id = 2, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [87] = { - .act_hid = BNXT_ULP_ACT_HID_4080, - .act_pattern_id = 3, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [88] = { - .act_hid = BNXT_ULP_ACT_HID_8080, - .act_pattern_id = 4, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [89] = { - .act_hid = BNXT_ULP_ACT_HID_c080, - .act_pattern_id = 5, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [90] = { - .act_hid = BNXT_ULP_ACT_HID_8880, - .act_pattern_id = 6, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [91] = { - .act_hid = BNXT_ULP_ACT_HID_22100, - .act_pattern_id = 7, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [92] = { - .act_hid = BNXT_ULP_ACT_HID_11100, - .act_pattern_id = 8, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [93] = { - .act_hid = BNXT_ULP_ACT_HID_6420, - .act_pattern_id = 9, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [94] = { - .act_hid = BNXT_ULP_ACT_HID_1fca0, - .act_pattern_id = 10, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [95] = { - .act_hid = BNXT_ULP_ACT_HID_19980, - .act_pattern_id = 11, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [96] = { - .act_hid = BNXT_ULP_ACT_HID_28520, - .act_pattern_id = 12, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [97] = { - .act_hid = BNXT_ULP_ACT_HID_c880, - .act_pattern_id = 13, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [98] = { - .act_hid = BNXT_ULP_ACT_HID_26100, - .act_pattern_id = 14, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [99] = { - .act_hid = BNXT_ULP_ACT_HID_15100, - .act_pattern_id = 15, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [100] = { - .act_hid = BNXT_ULP_ACT_HID_a420, - .act_pattern_id = 16, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [101] = { - .act_hid = BNXT_ULP_ACT_HID_23ca0, - .act_pattern_id = 17, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [102] = { - .act_hid = BNXT_ULP_ACT_HID_1d980, - .act_pattern_id = 18, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [103] = { - .act_hid = BNXT_ULP_ACT_HID_2c520, - .act_pattern_id = 19, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [104] = { - .act_hid = BNXT_ULP_ACT_HID_10880, - .act_pattern_id = 20, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [105] = { - .act_hid = BNXT_ULP_ACT_HID_2a100, - .act_pattern_id = 21, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [106] = { - .act_hid = BNXT_ULP_ACT_HID_19100, - .act_pattern_id = 22, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [107] = { - .act_hid = BNXT_ULP_ACT_HID_e420, - .act_pattern_id = 23, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [108] = { - .act_hid = BNXT_ULP_ACT_HID_27ca0, - .act_pattern_id = 24, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [109] = { - .act_hid = BNXT_ULP_ACT_HID_21980, - .act_pattern_id = 25, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [110] = { - .act_hid = BNXT_ULP_ACT_HID_30520, - .act_pattern_id = 26, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [111] = { - .act_hid = BNXT_ULP_ACT_HID_14880, - .act_pattern_id = 27, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [112] = { - .act_hid = BNXT_ULP_ACT_HID_2e100, - .act_pattern_id = 28, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [113] = { - .act_hid = BNXT_ULP_ACT_HID_1d100, - .act_pattern_id = 29, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [114] = { - .act_hid = BNXT_ULP_ACT_HID_12420, - .act_pattern_id = 30, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [115] = { - .act_hid = BNXT_ULP_ACT_HID_2bca0, - .act_pattern_id = 31, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [116] = { - .act_hid = BNXT_ULP_ACT_HID_25980, - .act_pattern_id = 32, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [117] = { - .act_hid = BNXT_ULP_ACT_HID_34520, - .act_pattern_id = 33, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [118] = { - .act_hid = BNXT_ULP_ACT_HID_8900, - .act_pattern_id = 34, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [119] = { - .act_hid = BNXT_ULP_ACT_HID_22180, - .act_pattern_id = 35, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [120] = { - .act_hid = BNXT_ULP_ACT_HID_11180, - .act_pattern_id = 36, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [121] = { - .act_hid = BNXT_ULP_ACT_HID_64a0, - .act_pattern_id = 37, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [122] = { - .act_hid = BNXT_ULP_ACT_HID_1fd20, - .act_pattern_id = 38, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [123] = { - .act_hid = BNXT_ULP_ACT_HID_19a00, - .act_pattern_id = 39, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [124] = { - .act_hid = BNXT_ULP_ACT_HID_285a0, - .act_pattern_id = 40, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [125] = { - .act_hid = BNXT_ULP_ACT_HID_c900, - .act_pattern_id = 41, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [126] = { - .act_hid = BNXT_ULP_ACT_HID_26180, - .act_pattern_id = 42, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [127] = { - .act_hid = BNXT_ULP_ACT_HID_15180, - .act_pattern_id = 43, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [128] = { - .act_hid = BNXT_ULP_ACT_HID_a4a0, - .act_pattern_id = 44, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [129] = { - .act_hid = BNXT_ULP_ACT_HID_23d20, - .act_pattern_id = 45, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [130] = { - .act_hid = BNXT_ULP_ACT_HID_1da00, - .act_pattern_id = 46, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [131] = { - .act_hid = BNXT_ULP_ACT_HID_2c5a0, - .act_pattern_id = 47, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [132] = { - .act_hid = BNXT_ULP_ACT_HID_10900, - .act_pattern_id = 48, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [133] = { - .act_hid = BNXT_ULP_ACT_HID_2a180, - .act_pattern_id = 49, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [134] = { - .act_hid = BNXT_ULP_ACT_HID_19180, - .act_pattern_id = 50, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [135] = { - .act_hid = BNXT_ULP_ACT_HID_e4a0, - .act_pattern_id = 51, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [136] = { - .act_hid = BNXT_ULP_ACT_HID_27d20, - .act_pattern_id = 52, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [137] = { - .act_hid = BNXT_ULP_ACT_HID_21a00, - .act_pattern_id = 53, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [138] = { - .act_hid = BNXT_ULP_ACT_HID_305a0, - .act_pattern_id = 54, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [139] = { - .act_hid = BNXT_ULP_ACT_HID_14900, - .act_pattern_id = 55, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [140] = { - .act_hid = BNXT_ULP_ACT_HID_2e180, - .act_pattern_id = 56, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [141] = { - .act_hid = BNXT_ULP_ACT_HID_1d180, - .act_pattern_id = 57, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [142] = { - .act_hid = BNXT_ULP_ACT_HID_124a0, - .act_pattern_id = 58, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [143] = { - .act_hid = BNXT_ULP_ACT_HID_2bd20, - .act_pattern_id = 59, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [144] = { - .act_hid = BNXT_ULP_ACT_HID_25a00, - .act_pattern_id = 60, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [145] = { - .act_hid = BNXT_ULP_ACT_HID_345a0, - .act_pattern_id = 61, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [146] = { - .act_hid = BNXT_ULP_ACT_HID_154c0, - .act_pattern_id = 62, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [147] = { - .act_hid = BNXT_ULP_ACT_HID_2ed40, - .act_pattern_id = 63, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [148] = { - .act_hid = BNXT_ULP_ACT_HID_1dd40, - .act_pattern_id = 64, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [149] = { - .act_hid = BNXT_ULP_ACT_HID_13060, - .act_pattern_id = 65, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [150] = { - .act_hid = BNXT_ULP_ACT_HID_2c8e0, - .act_pattern_id = 66, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [151] = { - .act_hid = BNXT_ULP_ACT_HID_35160, - .act_pattern_id = 67, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [152] = { - .act_hid = BNXT_ULP_ACT_HID_15540, - .act_pattern_id = 68, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [153] = { - .act_hid = BNXT_ULP_ACT_HID_2edc0, - .act_pattern_id = 69, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [154] = { - .act_hid = BNXT_ULP_ACT_HID_1ddc0, - .act_pattern_id = 70, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [155] = { - .act_hid = BNXT_ULP_ACT_HID_130e0, - .act_pattern_id = 71, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [156] = { - .act_hid = BNXT_ULP_ACT_HID_2c960, - .act_pattern_id = 72, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [157] = { - .act_hid = BNXT_ULP_ACT_HID_351e0, - .act_pattern_id = 73, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [158] = { - .act_hid = BNXT_ULP_ACT_HID_194c0, - .act_pattern_id = 74, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [159] = { - .act_hid = BNXT_ULP_ACT_HID_32d40, - .act_pattern_id = 75, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [160] = { - .act_hid = BNXT_ULP_ACT_HID_21d40, - .act_pattern_id = 76, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [161] = { - .act_hid = BNXT_ULP_ACT_HID_17060, - .act_pattern_id = 77, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [162] = { - .act_hid = BNXT_ULP_ACT_HID_308e0, - .act_pattern_id = 78, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [163] = { - .act_hid = BNXT_ULP_ACT_HID_39160, - .act_pattern_id = 79, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [164] = { - .act_hid = BNXT_ULP_ACT_HID_19540, - .act_pattern_id = 80, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [165] = { - .act_hid = BNXT_ULP_ACT_HID_32dc0, - .act_pattern_id = 81, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [166] = { - .act_hid = BNXT_ULP_ACT_HID_21dc0, - .act_pattern_id = 82, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [167] = { - .act_hid = BNXT_ULP_ACT_HID_170e0, - .act_pattern_id = 83, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [168] = { - .act_hid = BNXT_ULP_ACT_HID_30960, - .act_pattern_id = 84, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [169] = { - .act_hid = BNXT_ULP_ACT_HID_391e0, - .act_pattern_id = 85, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [170] = { - .act_hid = BNXT_ULP_ACT_HID_1d4c0, - .act_pattern_id = 86, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [171] = { - .act_hid = BNXT_ULP_ACT_HID_36d40, - .act_pattern_id = 87, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [172] = { - .act_hid = BNXT_ULP_ACT_HID_25d40, - .act_pattern_id = 88, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [173] = { - .act_hid = BNXT_ULP_ACT_HID_1b060, - .act_pattern_id = 89, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [174] = { - .act_hid = BNXT_ULP_ACT_HID_348e0, - .act_pattern_id = 90, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [175] = { - .act_hid = BNXT_ULP_ACT_HID_3d160, - .act_pattern_id = 91, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [176] = { - .act_hid = BNXT_ULP_ACT_HID_1d540, - .act_pattern_id = 92, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [177] = { - .act_hid = BNXT_ULP_ACT_HID_36dc0, - .act_pattern_id = 93, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [178] = { - .act_hid = BNXT_ULP_ACT_HID_25dc0, - .act_pattern_id = 94, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [179] = { - .act_hid = BNXT_ULP_ACT_HID_1b0e0, - .act_pattern_id = 95, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [180] = { - .act_hid = BNXT_ULP_ACT_HID_34960, - .act_pattern_id = 96, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [181] = { - .act_hid = BNXT_ULP_ACT_HID_3d1e0, - .act_pattern_id = 97, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [182] = { - .act_hid = BNXT_ULP_ACT_HID_214c0, - .act_pattern_id = 98, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [183] = { - .act_hid = BNXT_ULP_ACT_HID_3ad40, - .act_pattern_id = 99, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [184] = { - .act_hid = BNXT_ULP_ACT_HID_29d40, - .act_pattern_id = 100, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [185] = { - .act_hid = BNXT_ULP_ACT_HID_1f060, - .act_pattern_id = 101, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [186] = { - .act_hid = BNXT_ULP_ACT_HID_388e0, - .act_pattern_id = 102, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [187] = { - .act_hid = BNXT_ULP_ACT_HID_3380, - .act_pattern_id = 103, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [188] = { - .act_hid = BNXT_ULP_ACT_HID_21540, - .act_pattern_id = 104, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [189] = { - .act_hid = BNXT_ULP_ACT_HID_3adc0, - .act_pattern_id = 105, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [190] = { - .act_hid = BNXT_ULP_ACT_HID_29dc0, - .act_pattern_id = 106, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [191] = { - .act_hid = BNXT_ULP_ACT_HID_1f0e0, - .act_pattern_id = 107, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [192] = { - .act_hid = BNXT_ULP_ACT_HID_38960, - .act_pattern_id = 108, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [193] = { - .act_hid = BNXT_ULP_ACT_HID_3400, - .act_pattern_id = 109, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [194] = { - .act_hid = BNXT_ULP_ACT_HID_1d742, - .act_pattern_id = 110, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [195] = { - .act_hid = BNXT_ULP_ACT_HID_21742, - .act_pattern_id = 111, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [196] = { - .act_hid = BNXT_ULP_ACT_HID_25742, - .act_pattern_id = 112, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [197] = { - .act_hid = BNXT_ULP_ACT_HID_1d7c2, - .act_pattern_id = 113, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [198] = { - .act_hid = BNXT_ULP_ACT_HID_217c2, - .act_pattern_id = 114, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [199] = { - .act_hid = BNXT_ULP_ACT_HID_257c2, - .act_pattern_id = 115, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [200] = { - .act_hid = BNXT_ULP_ACT_HID_21fc2, - .act_pattern_id = 116, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [201] = { - .act_hid = BNXT_ULP_ACT_HID_3b842, - .act_pattern_id = 117, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [202] = { - .act_hid = BNXT_ULP_ACT_HID_2a842, - .act_pattern_id = 118, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [203] = { - .act_hid = BNXT_ULP_ACT_HID_1fb62, - .act_pattern_id = 119, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [204] = { - .act_hid = BNXT_ULP_ACT_HID_393e2, - .act_pattern_id = 120, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [205] = { - .act_hid = BNXT_ULP_ACT_HID_330c2, - .act_pattern_id = 121, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [206] = { - .act_hid = BNXT_ULP_ACT_HID_3e82, - .act_pattern_id = 122, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [207] = { - .act_hid = BNXT_ULP_ACT_HID_25fc2, - .act_pattern_id = 123, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [208] = { - .act_hid = BNXT_ULP_ACT_HID_1a62, - .act_pattern_id = 124, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [209] = { - .act_hid = BNXT_ULP_ACT_HID_2e842, - .act_pattern_id = 125, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [210] = { - .act_hid = BNXT_ULP_ACT_HID_23b62, - .act_pattern_id = 126, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [211] = { - .act_hid = BNXT_ULP_ACT_HID_3d3e2, - .act_pattern_id = 127, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [212] = { - .act_hid = BNXT_ULP_ACT_HID_370c2, - .act_pattern_id = 128, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [213] = { - .act_hid = BNXT_ULP_ACT_HID_7e82, - .act_pattern_id = 129, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [214] = { - .act_hid = BNXT_ULP_ACT_HID_29fc2, - .act_pattern_id = 130, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [215] = { - .act_hid = BNXT_ULP_ACT_HID_5a62, - .act_pattern_id = 131, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [216] = { - .act_hid = BNXT_ULP_ACT_HID_32842, - .act_pattern_id = 132, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [217] = { - .act_hid = BNXT_ULP_ACT_HID_27b62, - .act_pattern_id = 133, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [218] = { - .act_hid = BNXT_ULP_ACT_HID_3602, - .act_pattern_id = 134, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [219] = { - .act_hid = BNXT_ULP_ACT_HID_3b0c2, - .act_pattern_id = 135, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [220] = { - .act_hid = BNXT_ULP_ACT_HID_be82, - .act_pattern_id = 136, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [221] = { - .act_hid = BNXT_ULP_ACT_HID_2dfc2, - .act_pattern_id = 137, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [222] = { - .act_hid = BNXT_ULP_ACT_HID_9a62, - .act_pattern_id = 138, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [223] = { - .act_hid = BNXT_ULP_ACT_HID_36842, - .act_pattern_id = 139, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [224] = { - .act_hid = BNXT_ULP_ACT_HID_2bb62, - .act_pattern_id = 140, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [225] = { - .act_hid = BNXT_ULP_ACT_HID_7602, - .act_pattern_id = 141, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [226] = { - .act_hid = BNXT_ULP_ACT_HID_12e2, - .act_pattern_id = 142, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [227] = { - .act_hid = BNXT_ULP_ACT_HID_fe82, - .act_pattern_id = 143, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [228] = { - .act_hid = BNXT_ULP_ACT_HID_22042, - .act_pattern_id = 144, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [229] = { - .act_hid = BNXT_ULP_ACT_HID_3b8c2, - .act_pattern_id = 145, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [230] = { - .act_hid = BNXT_ULP_ACT_HID_2a8c2, - .act_pattern_id = 146, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [231] = { - .act_hid = BNXT_ULP_ACT_HID_1fbe2, - .act_pattern_id = 147, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [232] = { - .act_hid = BNXT_ULP_ACT_HID_39462, - .act_pattern_id = 148, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [233] = { - .act_hid = BNXT_ULP_ACT_HID_33142, - .act_pattern_id = 149, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [234] = { - .act_hid = BNXT_ULP_ACT_HID_3f02, - .act_pattern_id = 150, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [235] = { - .act_hid = BNXT_ULP_ACT_HID_26042, - .act_pattern_id = 151, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [236] = { - .act_hid = BNXT_ULP_ACT_HID_1ae2, - .act_pattern_id = 152, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [237] = { - .act_hid = BNXT_ULP_ACT_HID_2e8c2, - .act_pattern_id = 153, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [238] = { - .act_hid = BNXT_ULP_ACT_HID_23be2, - .act_pattern_id = 154, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [239] = { - .act_hid = BNXT_ULP_ACT_HID_3d462, - .act_pattern_id = 155, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [240] = { - .act_hid = BNXT_ULP_ACT_HID_37142, - .act_pattern_id = 156, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [241] = { - .act_hid = BNXT_ULP_ACT_HID_7f02, - .act_pattern_id = 157, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [242] = { - .act_hid = BNXT_ULP_ACT_HID_2a042, - .act_pattern_id = 158, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [243] = { - .act_hid = BNXT_ULP_ACT_HID_5ae2, - .act_pattern_id = 159, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [244] = { - .act_hid = BNXT_ULP_ACT_HID_328c2, - .act_pattern_id = 160, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [245] = { - .act_hid = BNXT_ULP_ACT_HID_27be2, - .act_pattern_id = 161, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [246] = { - .act_hid = BNXT_ULP_ACT_HID_3682, - .act_pattern_id = 162, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [247] = { - .act_hid = BNXT_ULP_ACT_HID_3b142, - .act_pattern_id = 163, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [248] = { - .act_hid = BNXT_ULP_ACT_HID_bf02, - .act_pattern_id = 164, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [249] = { - .act_hid = BNXT_ULP_ACT_HID_2e042, - .act_pattern_id = 165, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [250] = { - .act_hid = BNXT_ULP_ACT_HID_9ae2, - .act_pattern_id = 166, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [251] = { - .act_hid = BNXT_ULP_ACT_HID_368c2, - .act_pattern_id = 167, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [252] = { - .act_hid = BNXT_ULP_ACT_HID_2bbe2, - .act_pattern_id = 168, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [253] = { - .act_hid = BNXT_ULP_ACT_HID_7682, - .act_pattern_id = 169, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [254] = { - .act_hid = BNXT_ULP_ACT_HID_1362, - .act_pattern_id = 170, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [255] = { - .act_hid = BNXT_ULP_ACT_HID_ff02, - .act_pattern_id = 171, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [256] = { - .act_hid = BNXT_ULP_ACT_HID_2ec02, - .act_pattern_id = 172, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [257] = { - .act_hid = BNXT_ULP_ACT_HID_a6a2, - .act_pattern_id = 173, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [258] = { - .act_hid = BNXT_ULP_ACT_HID_37482, - .act_pattern_id = 174, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [259] = { - .act_hid = BNXT_ULP_ACT_HID_2c7a2, - .act_pattern_id = 175, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [260] = { - .act_hid = BNXT_ULP_ACT_HID_8242, - .act_pattern_id = 176, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [261] = { - .act_hid = BNXT_ULP_ACT_HID_10ac2, - .act_pattern_id = 177, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [262] = { - .act_hid = BNXT_ULP_ACT_HID_2ec82, - .act_pattern_id = 178, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [263] = { - .act_hid = BNXT_ULP_ACT_HID_a722, - .act_pattern_id = 179, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [264] = { - .act_hid = BNXT_ULP_ACT_HID_37502, - .act_pattern_id = 180, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [265] = { - .act_hid = BNXT_ULP_ACT_HID_2c822, - .act_pattern_id = 181, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [266] = { - .act_hid = BNXT_ULP_ACT_HID_82c2, - .act_pattern_id = 182, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [267] = { - .act_hid = BNXT_ULP_ACT_HID_10b42, - .act_pattern_id = 183, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [268] = { - .act_hid = BNXT_ULP_ACT_HID_32c02, - .act_pattern_id = 184, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [269] = { - .act_hid = BNXT_ULP_ACT_HID_e6a2, - .act_pattern_id = 185, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [270] = { - .act_hid = BNXT_ULP_ACT_HID_3b482, - .act_pattern_id = 186, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [271] = { - .act_hid = BNXT_ULP_ACT_HID_307a2, - .act_pattern_id = 187, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [272] = { - .act_hid = BNXT_ULP_ACT_HID_c242, - .act_pattern_id = 188, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [273] = { - .act_hid = BNXT_ULP_ACT_HID_14ac2, - .act_pattern_id = 189, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [274] = { - .act_hid = BNXT_ULP_ACT_HID_32c82, - .act_pattern_id = 190, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [275] = { - .act_hid = BNXT_ULP_ACT_HID_e722, - .act_pattern_id = 191, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [276] = { - .act_hid = BNXT_ULP_ACT_HID_3b502, - .act_pattern_id = 192, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [277] = { - .act_hid = BNXT_ULP_ACT_HID_30822, - .act_pattern_id = 193, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [278] = { - .act_hid = BNXT_ULP_ACT_HID_c2c2, - .act_pattern_id = 194, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [279] = { - .act_hid = BNXT_ULP_ACT_HID_14b42, - .act_pattern_id = 195, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [280] = { - .act_hid = BNXT_ULP_ACT_HID_36c02, - .act_pattern_id = 196, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [281] = { - .act_hid = BNXT_ULP_ACT_HID_126a2, - .act_pattern_id = 197, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [282] = { - .act_hid = BNXT_ULP_ACT_HID_16a2, - .act_pattern_id = 198, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [283] = { - .act_hid = BNXT_ULP_ACT_HID_347a2, - .act_pattern_id = 199, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [284] = { - .act_hid = BNXT_ULP_ACT_HID_10242, - .act_pattern_id = 200, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [285] = { - .act_hid = BNXT_ULP_ACT_HID_18ac2, - .act_pattern_id = 201, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [286] = { - .act_hid = BNXT_ULP_ACT_HID_36c82, - .act_pattern_id = 202, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [287] = { - .act_hid = BNXT_ULP_ACT_HID_12722, - .act_pattern_id = 203, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [288] = { - .act_hid = BNXT_ULP_ACT_HID_1722, - .act_pattern_id = 204, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [289] = { - .act_hid = BNXT_ULP_ACT_HID_34822, - .act_pattern_id = 205, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [290] = { - .act_hid = BNXT_ULP_ACT_HID_102c2, - .act_pattern_id = 206, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [291] = { - .act_hid = BNXT_ULP_ACT_HID_18b42, - .act_pattern_id = 207, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [292] = { - .act_hid = BNXT_ULP_ACT_HID_3ac02, - .act_pattern_id = 208, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [293] = { - .act_hid = BNXT_ULP_ACT_HID_166a2, - .act_pattern_id = 209, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [294] = { - .act_hid = BNXT_ULP_ACT_HID_56a2, - .act_pattern_id = 210, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [295] = { - .act_hid = BNXT_ULP_ACT_HID_387a2, - .act_pattern_id = 211, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [296] = { - .act_hid = BNXT_ULP_ACT_HID_14242, - .act_pattern_id = 212, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [297] = { - .act_hid = BNXT_ULP_ACT_HID_1cac2, - .act_pattern_id = 213, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [298] = { - .act_hid = BNXT_ULP_ACT_HID_3ac82, - .act_pattern_id = 214, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [299] = { - .act_hid = BNXT_ULP_ACT_HID_16722, - .act_pattern_id = 215, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [300] = { - .act_hid = BNXT_ULP_ACT_HID_5722, - .act_pattern_id = 216, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [301] = { - .act_hid = BNXT_ULP_ACT_HID_38822, - .act_pattern_id = 217, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [302] = { - .act_hid = BNXT_ULP_ACT_HID_142c2, - .act_pattern_id = 218, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [303] = { - .act_hid = BNXT_ULP_ACT_HID_1cb42, - .act_pattern_id = 219, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [304] = { - .act_hid = BNXT_ULP_ACT_HID_12520, - .act_pattern_id = 220, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [305] = { - .act_hid = BNXT_ULP_ACT_HID_2bda0, - .act_pattern_id = 221, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [306] = { - .act_hid = BNXT_ULP_ACT_HID_1ada0, - .act_pattern_id = 222, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [307] = { - .act_hid = BNXT_ULP_ACT_HID_120c0, - .act_pattern_id = 223, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [308] = { - .act_hid = BNXT_ULP_ACT_HID_2b940, - .act_pattern_id = 224, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [309] = { - .act_hid = BNXT_ULP_ACT_HID_23620, - .act_pattern_id = 225, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [310] = { - .act_hid = BNXT_ULP_ACT_HID_321c0, - .act_pattern_id = 226, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [311] = { - .act_hid = BNXT_ULP_ACT_HID_125a0, - .act_pattern_id = 227, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [312] = { - .act_hid = BNXT_ULP_ACT_HID_2be20, - .act_pattern_id = 228, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [313] = { - .act_hid = BNXT_ULP_ACT_HID_1ae20, - .act_pattern_id = 229, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [314] = { - .act_hid = BNXT_ULP_ACT_HID_12140, - .act_pattern_id = 230, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [315] = { - .act_hid = BNXT_ULP_ACT_HID_2b9c0, - .act_pattern_id = 231, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [316] = { - .act_hid = BNXT_ULP_ACT_HID_236a0, - .act_pattern_id = 232, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [317] = { - .act_hid = BNXT_ULP_ACT_HID_32240, - .act_pattern_id = 233, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [318] = { - .act_hid = BNXT_ULP_ACT_HID_1f160, - .act_pattern_id = 234, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [319] = { - .act_hid = BNXT_ULP_ACT_HID_3a9e0, - .act_pattern_id = 235, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [320] = { - .act_hid = BNXT_ULP_ACT_HID_279e0, - .act_pattern_id = 236, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [321] = { - .act_hid = BNXT_ULP_ACT_HID_1ed00, - .act_pattern_id = 237, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [322] = { - .act_hid = BNXT_ULP_ACT_HID_36580, - .act_pattern_id = 238, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [323] = { - .act_hid = BNXT_ULP_ACT_HID_3020, - .act_pattern_id = 239, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [324] = { - .act_hid = BNXT_ULP_ACT_HID_1f1e0, - .act_pattern_id = 240, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [325] = { - .act_hid = BNXT_ULP_ACT_HID_3aa60, - .act_pattern_id = 241, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [326] = { - .act_hid = BNXT_ULP_ACT_HID_27a60, - .act_pattern_id = 242, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [327] = { - .act_hid = BNXT_ULP_ACT_HID_1ed80, - .act_pattern_id = 243, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [328] = { - .act_hid = BNXT_ULP_ACT_HID_36600, - .act_pattern_id = 244, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [329] = { - .act_hid = BNXT_ULP_ACT_HID_30a0, - .act_pattern_id = 245, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 3 - }, - [330] = { - .act_hid = BNXT_ULP_ACT_HID_0100, - .act_pattern_id = 0, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_RSS | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 4 - }, - [331] = { - .act_hid = BNXT_ULP_ACT_HID_0180, - .act_pattern_id = 1, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_RSS | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 4 - }, - [332] = { - .act_hid = BNXT_ULP_ACT_HID_32e84, - .act_pattern_id = 2, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_QUEUE | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 4 - }, - [333] = { - .act_hid = BNXT_ULP_ACT_HID_32f04, - .act_pattern_id = 3, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_QUEUE | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 4 - }, - [334] = { - .act_hid = BNXT_ULP_ACT_HID_19842, - .act_pattern_id = 4, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_RSS | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 4 - }, - [335] = { - .act_hid = BNXT_ULP_ACT_HID_198c2, - .act_pattern_id = 5, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_RSS | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 4 - }, - [336] = { - .act_hid = BNXT_ULP_ACT_HID_e7e6, - .act_pattern_id = 6, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_QUEUE | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 4 - }, - [337] = { - .act_hid = BNXT_ULP_ACT_HID_e866, - .act_pattern_id = 7, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_QUEUE | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 4 - }, - [338] = { - .act_hid = BNXT_ULP_ACT_HID_a3e0, - .act_pattern_id = 0, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_METER_PROFILE | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 5 - }, - [339] = { - .act_hid = BNXT_ULP_ACT_HID_240e0, - .act_pattern_id = 1, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_METER | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 5 - }, - [340] = { - .act_hid = BNXT_ULP_ACT_HID_322c8, - .act_pattern_id = 2, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_DELETE | - BNXT_ULP_ACT_BIT_METER_PROFILE | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 5 - }, - [341] = { - .act_hid = BNXT_ULP_ACT_HID_e228, - .act_pattern_id = 3, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_DELETE | - BNXT_ULP_ACT_BIT_SHARED_METER | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 5 - }, - [342] = { - .act_hid = BNXT_ULP_ACT_HID_36130, - .act_pattern_id = 4, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_UPDATE | - BNXT_ULP_ACT_BIT_SHARED_METER | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 5 - }, - [343] = { - .act_hid = BNXT_ULP_ACT_HID_2e840, - .act_pattern_id = 0, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 6 - }, - [344] = { - .act_hid = BNXT_ULP_ACT_HID_2e880, - .act_pattern_id = 1, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_DROP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 6 - }, - [345] = { - .act_hid = BNXT_ULP_ACT_HID_2e900, - .act_pattern_id = 2, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_DROP | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 6 - }, - [346] = { - .act_hid = BNXT_ULP_ACT_HID_170c0, - .act_pattern_id = 3, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_VLAN_PCP | - BNXT_ULP_ACT_BIT_SET_VLAN_VID | - BNXT_ULP_ACT_BIT_PUSH_VLAN | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 6 - }, - [347] = { - .act_hid = BNXT_ULP_ACT_HID_14ea0, - .act_pattern_id = 4, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_VLAN_VID | - BNXT_ULP_ACT_BIT_PUSH_VLAN | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 6 - }, - [348] = { - .act_hid = BNXT_ULP_ACT_HID_3b480, - .act_pattern_id = 5, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 6 - }, - [349] = { - .act_hid = BNXT_ULP_ACT_HID_23d00, - .act_pattern_id = 6, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_VLAN_PCP | - BNXT_ULP_ACT_BIT_SET_VLAN_VID | - BNXT_ULP_ACT_BIT_PUSH_VLAN | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 6 - }, - [350] = { - .act_hid = BNXT_ULP_ACT_HID_21ae0, - .act_pattern_id = 7, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_VLAN_VID | - BNXT_ULP_ACT_BIT_PUSH_VLAN | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 6 - }, - [351] = { - .act_hid = BNXT_ULP_ACT_HID_2e8c0, - .act_pattern_id = 8, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 6 - }, - [352] = { - .act_hid = BNXT_ULP_ACT_HID_17140, - .act_pattern_id = 9, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_VLAN_PCP | - BNXT_ULP_ACT_BIT_SET_VLAN_VID | - BNXT_ULP_ACT_BIT_PUSH_VLAN | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 6 - }, - [353] = { - .act_hid = BNXT_ULP_ACT_HID_14f20, - .act_pattern_id = 10, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_VLAN_VID | - BNXT_ULP_ACT_BIT_PUSH_VLAN | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 6 - }, - [354] = { - .act_hid = BNXT_ULP_ACT_HID_3b500, - .act_pattern_id = 11, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 6 - }, - [355] = { - .act_hid = BNXT_ULP_ACT_HID_23d80, - .act_pattern_id = 12, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_VLAN_PCP | - BNXT_ULP_ACT_BIT_SET_VLAN_VID | - BNXT_ULP_ACT_BIT_PUSH_VLAN | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 6 - }, - [356] = { - .act_hid = BNXT_ULP_ACT_HID_21b60, - .act_pattern_id = 13, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_VLAN_VID | - BNXT_ULP_ACT_BIT_PUSH_VLAN | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 6 - }, - [357] = { - .act_hid = BNXT_ULP_ACT_HID_a1a2, - .act_pattern_id = 14, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 6 - }, - [358] = { - .act_hid = BNXT_ULP_ACT_HID_a1e2, - .act_pattern_id = 15, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_DROP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 6 - }, - [359] = { - .act_hid = BNXT_ULP_ACT_HID_a262, - .act_pattern_id = 16, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_DROP | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 6 - }, - [360] = { - .act_hid = BNXT_ULP_ACT_HID_30802, - .act_pattern_id = 17, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_VLAN_PCP | - BNXT_ULP_ACT_BIT_SET_VLAN_VID | - BNXT_ULP_ACT_BIT_PUSH_VLAN | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 6 - }, - [361] = { - .act_hid = BNXT_ULP_ACT_HID_2e5e2, - .act_pattern_id = 18, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_VLAN_VID | - BNXT_ULP_ACT_BIT_PUSH_VLAN | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 6 - }, - [362] = { - .act_hid = BNXT_ULP_ACT_HID_16de2, - .act_pattern_id = 19, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 6 - }, - [363] = { - .act_hid = BNXT_ULP_ACT_HID_3d442, - .act_pattern_id = 20, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_VLAN_PCP | - BNXT_ULP_ACT_BIT_SET_VLAN_VID | - BNXT_ULP_ACT_BIT_PUSH_VLAN | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 6 - }, - [364] = { - .act_hid = BNXT_ULP_ACT_HID_3b222, - .act_pattern_id = 21, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_VLAN_VID | - BNXT_ULP_ACT_BIT_PUSH_VLAN | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 6 - }, - [365] = { - .act_hid = BNXT_ULP_ACT_HID_a222, - .act_pattern_id = 22, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 6 - }, - [366] = { - .act_hid = BNXT_ULP_ACT_HID_30882, - .act_pattern_id = 23, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_VLAN_PCP | - BNXT_ULP_ACT_BIT_SET_VLAN_VID | - BNXT_ULP_ACT_BIT_PUSH_VLAN | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 6 - }, - [367] = { - .act_hid = BNXT_ULP_ACT_HID_2e662, - .act_pattern_id = 24, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_VLAN_VID | - BNXT_ULP_ACT_BIT_PUSH_VLAN | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 6 - }, - [368] = { - .act_hid = BNXT_ULP_ACT_HID_16e62, - .act_pattern_id = 25, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 6 - }, - [369] = { - .act_hid = BNXT_ULP_ACT_HID_3d4c2, - .act_pattern_id = 26, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_VLAN_PCP | - BNXT_ULP_ACT_BIT_SET_VLAN_VID | - BNXT_ULP_ACT_BIT_PUSH_VLAN | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 6 - }, - [370] = { - .act_hid = BNXT_ULP_ACT_HID_3b2a2, - .act_pattern_id = 27, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_VLAN_VID | - BNXT_ULP_ACT_BIT_PUSH_VLAN | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 6 - }, - [371] = { - .act_hid = BNXT_ULP_ACT_HID_3a4e0, - .act_pattern_id = 28, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 6 - }, - [372] = { - .act_hid = BNXT_ULP_ACT_HID_3a520, - .act_pattern_id = 29, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_DROP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 6 - }, - [373] = { - .act_hid = BNXT_ULP_ACT_HID_3a5a0, - .act_pattern_id = 30, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_DROP | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 6 - }, - [374] = { - .act_hid = BNXT_ULP_ACT_HID_22d60, - .act_pattern_id = 31, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_VLAN_PCP | - BNXT_ULP_ACT_BIT_SET_VLAN_VID | - BNXT_ULP_ACT_BIT_PUSH_VLAN | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 6 - }, - [375] = { - .act_hid = BNXT_ULP_ACT_HID_1eb40, - .act_pattern_id = 32, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_VLAN_VID | - BNXT_ULP_ACT_BIT_PUSH_VLAN | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 6 - }, - [376] = { - .act_hid = BNXT_ULP_ACT_HID_7340, - .act_pattern_id = 33, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 6 - }, - [377] = { - .act_hid = BNXT_ULP_ACT_HID_2f9a0, - .act_pattern_id = 34, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_VLAN_PCP | - BNXT_ULP_ACT_BIT_SET_VLAN_VID | - BNXT_ULP_ACT_BIT_PUSH_VLAN | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 6 - }, - [378] = { - .act_hid = BNXT_ULP_ACT_HID_2b780, - .act_pattern_id = 35, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_VLAN_VID | - BNXT_ULP_ACT_BIT_PUSH_VLAN | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 6 - }, - [379] = { - .act_hid = BNXT_ULP_ACT_HID_3a560, - .act_pattern_id = 36, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 6 - }, - [380] = { - .act_hid = BNXT_ULP_ACT_HID_22de0, - .act_pattern_id = 37, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_VLAN_PCP | - BNXT_ULP_ACT_BIT_SET_VLAN_VID | - BNXT_ULP_ACT_BIT_PUSH_VLAN | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 6 - }, - [381] = { - .act_hid = BNXT_ULP_ACT_HID_1ebc0, - .act_pattern_id = 38, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_VLAN_VID | - BNXT_ULP_ACT_BIT_PUSH_VLAN | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 6 - }, - [382] = { - .act_hid = BNXT_ULP_ACT_HID_73c0, - .act_pattern_id = 39, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 6 - }, - [383] = { - .act_hid = BNXT_ULP_ACT_HID_2fa20, - .act_pattern_id = 40, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_VLAN_PCP | - BNXT_ULP_ACT_BIT_SET_VLAN_VID | - BNXT_ULP_ACT_BIT_PUSH_VLAN | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 6 - }, - [384] = { - .act_hid = BNXT_ULP_ACT_HID_2b800, - .act_pattern_id = 41, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_VLAN_VID | - BNXT_ULP_ACT_BIT_PUSH_VLAN | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 6 - }, - [385] = { - .act_hid = BNXT_ULP_ACT_HID_32840, - .act_pattern_id = 0, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [386] = { - .act_hid = BNXT_ULP_ACT_HID_36840, - .act_pattern_id = 1, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [387] = { - .act_hid = BNXT_ULP_ACT_HID_3a840, - .act_pattern_id = 2, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [388] = { - .act_hid = BNXT_ULP_ACT_HID_328c0, - .act_pattern_id = 3, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [389] = { - .act_hid = BNXT_ULP_ACT_HID_368c0, - .act_pattern_id = 4, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [390] = { - .act_hid = BNXT_ULP_ACT_HID_3a8c0, - .act_pattern_id = 5, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [391] = { - .act_hid = BNXT_ULP_ACT_HID_370c0, - .act_pattern_id = 6, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [392] = { - .act_hid = BNXT_ULP_ACT_HID_12b60, - .act_pattern_id = 7, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [393] = { - .act_hid = BNXT_ULP_ACT_HID_1b60, - .act_pattern_id = 8, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [394] = { - .act_hid = BNXT_ULP_ACT_HID_34c60, - .act_pattern_id = 9, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [395] = { - .act_hid = BNXT_ULP_ACT_HID_10700, - .act_pattern_id = 10, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [396] = { - .act_hid = BNXT_ULP_ACT_HID_18f80, - .act_pattern_id = 11, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [397] = { - .act_hid = BNXT_ULP_ACT_HID_3b0c0, - .act_pattern_id = 12, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [398] = { - .act_hid = BNXT_ULP_ACT_HID_16b60, - .act_pattern_id = 13, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [399] = { - .act_hid = BNXT_ULP_ACT_HID_5b60, - .act_pattern_id = 14, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [400] = { - .act_hid = BNXT_ULP_ACT_HID_38c60, - .act_pattern_id = 15, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [401] = { - .act_hid = BNXT_ULP_ACT_HID_14700, - .act_pattern_id = 16, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [402] = { - .act_hid = BNXT_ULP_ACT_HID_1cf80, - .act_pattern_id = 17, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [403] = { - .act_hid = BNXT_ULP_ACT_HID_12e0, - .act_pattern_id = 18, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [404] = { - .act_hid = BNXT_ULP_ACT_HID_1ab60, - .act_pattern_id = 19, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [405] = { - .act_hid = BNXT_ULP_ACT_HID_9b60, - .act_pattern_id = 20, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [406] = { - .act_hid = BNXT_ULP_ACT_HID_3cc60, - .act_pattern_id = 21, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [407] = { - .act_hid = BNXT_ULP_ACT_HID_18700, - .act_pattern_id = 22, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [408] = { - .act_hid = BNXT_ULP_ACT_HID_20f80, - .act_pattern_id = 23, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [409] = { - .act_hid = BNXT_ULP_ACT_HID_52e0, - .act_pattern_id = 24, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [410] = { - .act_hid = BNXT_ULP_ACT_HID_1eb60, - .act_pattern_id = 25, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [411] = { - .act_hid = BNXT_ULP_ACT_HID_db60, - .act_pattern_id = 26, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [412] = { - .act_hid = BNXT_ULP_ACT_HID_2e80, - .act_pattern_id = 27, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [413] = { - .act_hid = BNXT_ULP_ACT_HID_1c700, - .act_pattern_id = 28, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [414] = { - .act_hid = BNXT_ULP_ACT_HID_24f80, - .act_pattern_id = 29, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [415] = { - .act_hid = BNXT_ULP_ACT_HID_37140, - .act_pattern_id = 30, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [416] = { - .act_hid = BNXT_ULP_ACT_HID_12be0, - .act_pattern_id = 31, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [417] = { - .act_hid = BNXT_ULP_ACT_HID_1be0, - .act_pattern_id = 32, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [418] = { - .act_hid = BNXT_ULP_ACT_HID_34ce0, - .act_pattern_id = 33, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [419] = { - .act_hid = BNXT_ULP_ACT_HID_10780, - .act_pattern_id = 34, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [420] = { - .act_hid = BNXT_ULP_ACT_HID_19000, - .act_pattern_id = 35, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [421] = { - .act_hid = BNXT_ULP_ACT_HID_3b140, - .act_pattern_id = 36, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [422] = { - .act_hid = BNXT_ULP_ACT_HID_16be0, - .act_pattern_id = 37, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [423] = { - .act_hid = BNXT_ULP_ACT_HID_5be0, - .act_pattern_id = 38, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [424] = { - .act_hid = BNXT_ULP_ACT_HID_38ce0, - .act_pattern_id = 39, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [425] = { - .act_hid = BNXT_ULP_ACT_HID_14780, - .act_pattern_id = 40, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [426] = { - .act_hid = BNXT_ULP_ACT_HID_1d000, - .act_pattern_id = 41, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [427] = { - .act_hid = BNXT_ULP_ACT_HID_1360, - .act_pattern_id = 42, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [428] = { - .act_hid = BNXT_ULP_ACT_HID_1abe0, - .act_pattern_id = 43, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [429] = { - .act_hid = BNXT_ULP_ACT_HID_9be0, - .act_pattern_id = 44, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [430] = { - .act_hid = BNXT_ULP_ACT_HID_3cce0, - .act_pattern_id = 45, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [431] = { - .act_hid = BNXT_ULP_ACT_HID_18780, - .act_pattern_id = 46, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [432] = { - .act_hid = BNXT_ULP_ACT_HID_21000, - .act_pattern_id = 47, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [433] = { - .act_hid = BNXT_ULP_ACT_HID_5360, - .act_pattern_id = 48, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [434] = { - .act_hid = BNXT_ULP_ACT_HID_1ebe0, - .act_pattern_id = 49, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [435] = { - .act_hid = BNXT_ULP_ACT_HID_dbe0, - .act_pattern_id = 50, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [436] = { - .act_hid = BNXT_ULP_ACT_HID_2f00, - .act_pattern_id = 51, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [437] = { - .act_hid = BNXT_ULP_ACT_HID_1c780, - .act_pattern_id = 52, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [438] = { - .act_hid = BNXT_ULP_ACT_HID_25000, - .act_pattern_id = 53, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [439] = { - .act_hid = BNXT_ULP_ACT_HID_5f20, - .act_pattern_id = 54, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [440] = { - .act_hid = BNXT_ULP_ACT_HID_1f7a0, - .act_pattern_id = 55, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [441] = { - .act_hid = BNXT_ULP_ACT_HID_e7a0, - .act_pattern_id = 56, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [442] = { - .act_hid = BNXT_ULP_ACT_HID_3ac0, - .act_pattern_id = 57, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [443] = { - .act_hid = BNXT_ULP_ACT_HID_1d340, - .act_pattern_id = 58, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [444] = { - .act_hid = BNXT_ULP_ACT_HID_25bc0, - .act_pattern_id = 59, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [445] = { - .act_hid = BNXT_ULP_ACT_HID_5fa0, - .act_pattern_id = 60, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [446] = { - .act_hid = BNXT_ULP_ACT_HID_1f820, - .act_pattern_id = 61, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [447] = { - .act_hid = BNXT_ULP_ACT_HID_e820, - .act_pattern_id = 62, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [448] = { - .act_hid = BNXT_ULP_ACT_HID_3b40, - .act_pattern_id = 63, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [449] = { - .act_hid = BNXT_ULP_ACT_HID_1d3c0, - .act_pattern_id = 64, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [450] = { - .act_hid = BNXT_ULP_ACT_HID_25c40, - .act_pattern_id = 65, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [451] = { - .act_hid = BNXT_ULP_ACT_HID_237a0, - .act_pattern_id = 66, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [452] = { - .act_hid = BNXT_ULP_ACT_HID_127a0, - .act_pattern_id = 67, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [453] = { - .act_hid = BNXT_ULP_ACT_HID_7ac0, - .act_pattern_id = 68, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [454] = { - .act_hid = BNXT_ULP_ACT_HID_9f20, - .act_pattern_id = 69, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [455] = { - .act_hid = BNXT_ULP_ACT_HID_21340, - .act_pattern_id = 70, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [456] = { - .act_hid = BNXT_ULP_ACT_HID_29bc0, - .act_pattern_id = 71, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [457] = { - .act_hid = BNXT_ULP_ACT_HID_9fa0, - .act_pattern_id = 72, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [458] = { - .act_hid = BNXT_ULP_ACT_HID_23820, - .act_pattern_id = 73, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [459] = { - .act_hid = BNXT_ULP_ACT_HID_12820, - .act_pattern_id = 74, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [460] = { - .act_hid = BNXT_ULP_ACT_HID_7b40, - .act_pattern_id = 75, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [461] = { - .act_hid = BNXT_ULP_ACT_HID_213c0, - .act_pattern_id = 76, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [462] = { - .act_hid = BNXT_ULP_ACT_HID_29c40, - .act_pattern_id = 77, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [463] = { - .act_hid = BNXT_ULP_ACT_HID_df20, - .act_pattern_id = 78, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [464] = { - .act_hid = BNXT_ULP_ACT_HID_277a0, - .act_pattern_id = 79, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [465] = { - .act_hid = BNXT_ULP_ACT_HID_167a0, - .act_pattern_id = 80, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [466] = { - .act_hid = BNXT_ULP_ACT_HID_bac0, - .act_pattern_id = 81, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [467] = { - .act_hid = BNXT_ULP_ACT_HID_25340, - .act_pattern_id = 82, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [468] = { - .act_hid = BNXT_ULP_ACT_HID_2dbc0, - .act_pattern_id = 83, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [469] = { - .act_hid = BNXT_ULP_ACT_HID_dfa0, - .act_pattern_id = 84, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [470] = { - .act_hid = BNXT_ULP_ACT_HID_27820, - .act_pattern_id = 85, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [471] = { - .act_hid = BNXT_ULP_ACT_HID_16820, - .act_pattern_id = 86, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [472] = { - .act_hid = BNXT_ULP_ACT_HID_bb40, - .act_pattern_id = 87, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [473] = { - .act_hid = BNXT_ULP_ACT_HID_253c0, - .act_pattern_id = 88, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [474] = { - .act_hid = BNXT_ULP_ACT_HID_2dc40, - .act_pattern_id = 89, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [475] = { - .act_hid = BNXT_ULP_ACT_HID_11f20, - .act_pattern_id = 90, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [476] = { - .act_hid = BNXT_ULP_ACT_HID_2b7a0, - .act_pattern_id = 91, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [477] = { - .act_hid = BNXT_ULP_ACT_HID_1a7a0, - .act_pattern_id = 92, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [478] = { - .act_hid = BNXT_ULP_ACT_HID_fac0, - .act_pattern_id = 93, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [479] = { - .act_hid = BNXT_ULP_ACT_HID_29340, - .act_pattern_id = 94, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [480] = { - .act_hid = BNXT_ULP_ACT_HID_31bc0, - .act_pattern_id = 95, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [481] = { - .act_hid = BNXT_ULP_ACT_HID_11fa0, - .act_pattern_id = 96, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [482] = { - .act_hid = BNXT_ULP_ACT_HID_2b820, - .act_pattern_id = 97, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [483] = { - .act_hid = BNXT_ULP_ACT_HID_1a820, - .act_pattern_id = 98, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [484] = { - .act_hid = BNXT_ULP_ACT_HID_fb40, - .act_pattern_id = 99, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [485] = { - .act_hid = BNXT_ULP_ACT_HID_293c0, - .act_pattern_id = 100, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [486] = { - .act_hid = BNXT_ULP_ACT_HID_31c40, - .act_pattern_id = 101, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [487] = { - .act_hid = BNXT_ULP_ACT_HID_e1a2, - .act_pattern_id = 102, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [488] = { - .act_hid = BNXT_ULP_ACT_HID_121a2, - .act_pattern_id = 103, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [489] = { - .act_hid = BNXT_ULP_ACT_HID_161a2, - .act_pattern_id = 104, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [490] = { - .act_hid = BNXT_ULP_ACT_HID_e222, - .act_pattern_id = 105, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [491] = { - .act_hid = BNXT_ULP_ACT_HID_12222, - .act_pattern_id = 106, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [492] = { - .act_hid = BNXT_ULP_ACT_HID_16222, - .act_pattern_id = 107, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [493] = { - .act_hid = BNXT_ULP_ACT_HID_12a22, - .act_pattern_id = 108, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [494] = { - .act_hid = BNXT_ULP_ACT_HID_2c2a2, - .act_pattern_id = 109, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [495] = { - .act_hid = BNXT_ULP_ACT_HID_1b2a2, - .act_pattern_id = 110, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [496] = { - .act_hid = BNXT_ULP_ACT_HID_105c2, - .act_pattern_id = 111, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [497] = { - .act_hid = BNXT_ULP_ACT_HID_29e42, - .act_pattern_id = 112, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [498] = { - .act_hid = BNXT_ULP_ACT_HID_326c2, - .act_pattern_id = 113, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [499] = { - .act_hid = BNXT_ULP_ACT_HID_16a22, - .act_pattern_id = 114, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [500] = { - .act_hid = BNXT_ULP_ACT_HID_302a2, - .act_pattern_id = 115, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [501] = { - .act_hid = BNXT_ULP_ACT_HID_1f2a2, - .act_pattern_id = 116, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [502] = { - .act_hid = BNXT_ULP_ACT_HID_145c2, - .act_pattern_id = 117, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [503] = { - .act_hid = BNXT_ULP_ACT_HID_2de42, - .act_pattern_id = 118, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [504] = { - .act_hid = BNXT_ULP_ACT_HID_366c2, - .act_pattern_id = 119, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [505] = { - .act_hid = BNXT_ULP_ACT_HID_1aa22, - .act_pattern_id = 120, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [506] = { - .act_hid = BNXT_ULP_ACT_HID_342a2, - .act_pattern_id = 121, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [507] = { - .act_hid = BNXT_ULP_ACT_HID_232a2, - .act_pattern_id = 122, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [508] = { - .act_hid = BNXT_ULP_ACT_HID_185c2, - .act_pattern_id = 123, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [509] = { - .act_hid = BNXT_ULP_ACT_HID_31e42, - .act_pattern_id = 124, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [510] = { - .act_hid = BNXT_ULP_ACT_HID_3a6c2, - .act_pattern_id = 125, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [511] = { - .act_hid = BNXT_ULP_ACT_HID_1ea22, - .act_pattern_id = 126, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [512] = { - .act_hid = BNXT_ULP_ACT_HID_382a2, - .act_pattern_id = 127, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [513] = { - .act_hid = BNXT_ULP_ACT_HID_272a2, - .act_pattern_id = 128, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [514] = { - .act_hid = BNXT_ULP_ACT_HID_1c5c2, - .act_pattern_id = 129, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [515] = { - .act_hid = BNXT_ULP_ACT_HID_35e42, - .act_pattern_id = 130, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [516] = { - .act_hid = BNXT_ULP_ACT_HID_08e2, - .act_pattern_id = 131, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [517] = { - .act_hid = BNXT_ULP_ACT_HID_12aa2, - .act_pattern_id = 132, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [518] = { - .act_hid = BNXT_ULP_ACT_HID_2c322, - .act_pattern_id = 133, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [519] = { - .act_hid = BNXT_ULP_ACT_HID_1b322, - .act_pattern_id = 134, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [520] = { - .act_hid = BNXT_ULP_ACT_HID_10642, - .act_pattern_id = 135, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [521] = { - .act_hid = BNXT_ULP_ACT_HID_29ec2, - .act_pattern_id = 136, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [522] = { - .act_hid = BNXT_ULP_ACT_HID_32742, - .act_pattern_id = 137, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [523] = { - .act_hid = BNXT_ULP_ACT_HID_16aa2, - .act_pattern_id = 138, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [524] = { - .act_hid = BNXT_ULP_ACT_HID_30322, - .act_pattern_id = 139, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [525] = { - .act_hid = BNXT_ULP_ACT_HID_1f322, - .act_pattern_id = 140, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [526] = { - .act_hid = BNXT_ULP_ACT_HID_14642, - .act_pattern_id = 141, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [527] = { - .act_hid = BNXT_ULP_ACT_HID_2dec2, - .act_pattern_id = 142, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [528] = { - .act_hid = BNXT_ULP_ACT_HID_36742, - .act_pattern_id = 143, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [529] = { - .act_hid = BNXT_ULP_ACT_HID_1aaa2, - .act_pattern_id = 144, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [530] = { - .act_hid = BNXT_ULP_ACT_HID_34322, - .act_pattern_id = 145, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [531] = { - .act_hid = BNXT_ULP_ACT_HID_23322, - .act_pattern_id = 146, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [532] = { - .act_hid = BNXT_ULP_ACT_HID_18642, - .act_pattern_id = 147, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [533] = { - .act_hid = BNXT_ULP_ACT_HID_31ec2, - .act_pattern_id = 148, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [534] = { - .act_hid = BNXT_ULP_ACT_HID_3a742, - .act_pattern_id = 149, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [535] = { - .act_hid = BNXT_ULP_ACT_HID_1eaa2, - .act_pattern_id = 150, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [536] = { - .act_hid = BNXT_ULP_ACT_HID_38322, - .act_pattern_id = 151, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [537] = { - .act_hid = BNXT_ULP_ACT_HID_27322, - .act_pattern_id = 152, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [538] = { - .act_hid = BNXT_ULP_ACT_HID_1c642, - .act_pattern_id = 153, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [539] = { - .act_hid = BNXT_ULP_ACT_HID_35ec2, - .act_pattern_id = 154, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [540] = { - .act_hid = BNXT_ULP_ACT_HID_0962, - .act_pattern_id = 155, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [541] = { - .act_hid = BNXT_ULP_ACT_HID_1f662, - .act_pattern_id = 156, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [542] = { - .act_hid = BNXT_ULP_ACT_HID_38ee2, - .act_pattern_id = 157, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [543] = { - .act_hid = BNXT_ULP_ACT_HID_27ee2, - .act_pattern_id = 158, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [544] = { - .act_hid = BNXT_ULP_ACT_HID_1d202, - .act_pattern_id = 159, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [545] = { - .act_hid = BNXT_ULP_ACT_HID_36a82, - .act_pattern_id = 160, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [546] = { - .act_hid = BNXT_ULP_ACT_HID_1522, - .act_pattern_id = 161, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [547] = { - .act_hid = BNXT_ULP_ACT_HID_1f6e2, - .act_pattern_id = 162, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [548] = { - .act_hid = BNXT_ULP_ACT_HID_38f62, - .act_pattern_id = 163, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [549] = { - .act_hid = BNXT_ULP_ACT_HID_27f62, - .act_pattern_id = 164, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [550] = { - .act_hid = BNXT_ULP_ACT_HID_1d282, - .act_pattern_id = 165, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [551] = { - .act_hid = BNXT_ULP_ACT_HID_36b02, - .act_pattern_id = 166, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [552] = { - .act_hid = BNXT_ULP_ACT_HID_15a2, - .act_pattern_id = 167, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [553] = { - .act_hid = BNXT_ULP_ACT_HID_3cee2, - .act_pattern_id = 168, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [554] = { - .act_hid = BNXT_ULP_ACT_HID_2bee2, - .act_pattern_id = 169, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [555] = { - .act_hid = BNXT_ULP_ACT_HID_21202, - .act_pattern_id = 170, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [556] = { - .act_hid = BNXT_ULP_ACT_HID_23662, - .act_pattern_id = 171, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [557] = { - .act_hid = BNXT_ULP_ACT_HID_3aa82, - .act_pattern_id = 172, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [558] = { - .act_hid = BNXT_ULP_ACT_HID_5522, - .act_pattern_id = 173, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [559] = { - .act_hid = BNXT_ULP_ACT_HID_236e2, - .act_pattern_id = 174, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [560] = { - .act_hid = BNXT_ULP_ACT_HID_3cf62, - .act_pattern_id = 175, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [561] = { - .act_hid = BNXT_ULP_ACT_HID_2bf62, - .act_pattern_id = 176, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [562] = { - .act_hid = BNXT_ULP_ACT_HID_21282, - .act_pattern_id = 177, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [563] = { - .act_hid = BNXT_ULP_ACT_HID_3ab02, - .act_pattern_id = 178, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [564] = { - .act_hid = BNXT_ULP_ACT_HID_55a2, - .act_pattern_id = 179, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [565] = { - .act_hid = BNXT_ULP_ACT_HID_27662, - .act_pattern_id = 180, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [566] = { - .act_hid = BNXT_ULP_ACT_HID_3102, - .act_pattern_id = 181, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [567] = { - .act_hid = BNXT_ULP_ACT_HID_2fee2, - .act_pattern_id = 182, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [568] = { - .act_hid = BNXT_ULP_ACT_HID_25202, - .act_pattern_id = 183, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [569] = { - .act_hid = BNXT_ULP_ACT_HID_0ca2, - .act_pattern_id = 184, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [570] = { - .act_hid = BNXT_ULP_ACT_HID_9522, - .act_pattern_id = 185, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [571] = { - .act_hid = BNXT_ULP_ACT_HID_276e2, - .act_pattern_id = 186, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [572] = { - .act_hid = BNXT_ULP_ACT_HID_3182, - .act_pattern_id = 187, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [573] = { - .act_hid = BNXT_ULP_ACT_HID_2ff62, - .act_pattern_id = 188, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [574] = { - .act_hid = BNXT_ULP_ACT_HID_25282, - .act_pattern_id = 189, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [575] = { - .act_hid = BNXT_ULP_ACT_HID_0d22, - .act_pattern_id = 190, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [576] = { - .act_hid = BNXT_ULP_ACT_HID_95a2, - .act_pattern_id = 191, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [577] = { - .act_hid = BNXT_ULP_ACT_HID_2b662, - .act_pattern_id = 192, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [578] = { - .act_hid = BNXT_ULP_ACT_HID_7102, - .act_pattern_id = 193, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [579] = { - .act_hid = BNXT_ULP_ACT_HID_33ee2, - .act_pattern_id = 194, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [580] = { - .act_hid = BNXT_ULP_ACT_HID_29202, - .act_pattern_id = 195, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [581] = { - .act_hid = BNXT_ULP_ACT_HID_4ca2, - .act_pattern_id = 196, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [582] = { - .act_hid = BNXT_ULP_ACT_HID_d522, - .act_pattern_id = 197, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [583] = { - .act_hid = BNXT_ULP_ACT_HID_2b6e2, - .act_pattern_id = 198, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [584] = { - .act_hid = BNXT_ULP_ACT_HID_7182, - .act_pattern_id = 199, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [585] = { - .act_hid = BNXT_ULP_ACT_HID_33f62, - .act_pattern_id = 200, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [586] = { - .act_hid = BNXT_ULP_ACT_HID_29282, - .act_pattern_id = 201, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [587] = { - .act_hid = BNXT_ULP_ACT_HID_4d22, - .act_pattern_id = 202, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [588] = { - .act_hid = BNXT_ULP_ACT_HID_d5a2, - .act_pattern_id = 203, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [589] = { - .act_hid = BNXT_ULP_ACT_HID_3e4e0, - .act_pattern_id = 204, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [590] = { - .act_hid = BNXT_ULP_ACT_HID_2700, - .act_pattern_id = 205, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [591] = { - .act_hid = BNXT_ULP_ACT_HID_6700, - .act_pattern_id = 206, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [592] = { - .act_hid = BNXT_ULP_ACT_HID_3e560, - .act_pattern_id = 207, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [593] = { - .act_hid = BNXT_ULP_ACT_HID_2780, - .act_pattern_id = 208, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [594] = { - .act_hid = BNXT_ULP_ACT_HID_6780, - .act_pattern_id = 209, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [595] = { - .act_hid = BNXT_ULP_ACT_HID_2f80, - .act_pattern_id = 210, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [596] = { - .act_hid = BNXT_ULP_ACT_HID_1e800, - .act_pattern_id = 211, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [597] = { - .act_hid = BNXT_ULP_ACT_HID_b800, - .act_pattern_id = 212, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [598] = { - .act_hid = BNXT_ULP_ACT_HID_2b20, - .act_pattern_id = 213, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [599] = { - .act_hid = BNXT_ULP_ACT_HID_1a3a0, - .act_pattern_id = 214, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [600] = { - .act_hid = BNXT_ULP_ACT_HID_22c20, - .act_pattern_id = 215, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [601] = { - .act_hid = BNXT_ULP_ACT_HID_6f80, - .act_pattern_id = 216, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [602] = { - .act_hid = BNXT_ULP_ACT_HID_22800, - .act_pattern_id = 217, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [603] = { - .act_hid = BNXT_ULP_ACT_HID_f800, - .act_pattern_id = 218, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [604] = { - .act_hid = BNXT_ULP_ACT_HID_6b20, - .act_pattern_id = 219, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [605] = { - .act_hid = BNXT_ULP_ACT_HID_1e3a0, - .act_pattern_id = 220, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [606] = { - .act_hid = BNXT_ULP_ACT_HID_26c20, - .act_pattern_id = 221, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [607] = { - .act_hid = BNXT_ULP_ACT_HID_af80, - .act_pattern_id = 222, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [608] = { - .act_hid = BNXT_ULP_ACT_HID_26800, - .act_pattern_id = 223, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [609] = { - .act_hid = BNXT_ULP_ACT_HID_13800, - .act_pattern_id = 224, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [610] = { - .act_hid = BNXT_ULP_ACT_HID_ab20, - .act_pattern_id = 225, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [611] = { - .act_hid = BNXT_ULP_ACT_HID_223a0, - .act_pattern_id = 226, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [612] = { - .act_hid = BNXT_ULP_ACT_HID_2ac20, - .act_pattern_id = 227, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [613] = { - .act_hid = BNXT_ULP_ACT_HID_ef80, - .act_pattern_id = 228, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [614] = { - .act_hid = BNXT_ULP_ACT_HID_2a800, - .act_pattern_id = 229, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [615] = { - .act_hid = BNXT_ULP_ACT_HID_17800, - .act_pattern_id = 230, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [616] = { - .act_hid = BNXT_ULP_ACT_HID_eb20, - .act_pattern_id = 231, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [617] = { - .act_hid = BNXT_ULP_ACT_HID_263a0, - .act_pattern_id = 232, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [618] = { - .act_hid = BNXT_ULP_ACT_HID_2ec20, - .act_pattern_id = 233, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [619] = { - .act_hid = BNXT_ULP_ACT_HID_3000, - .act_pattern_id = 234, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [620] = { - .act_hid = BNXT_ULP_ACT_HID_1e880, - .act_pattern_id = 235, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [621] = { - .act_hid = BNXT_ULP_ACT_HID_b880, - .act_pattern_id = 236, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [622] = { - .act_hid = BNXT_ULP_ACT_HID_2ba0, - .act_pattern_id = 237, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [623] = { - .act_hid = BNXT_ULP_ACT_HID_1a420, - .act_pattern_id = 238, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [624] = { - .act_hid = BNXT_ULP_ACT_HID_22ca0, - .act_pattern_id = 239, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [625] = { - .act_hid = BNXT_ULP_ACT_HID_7000, - .act_pattern_id = 240, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [626] = { - .act_hid = BNXT_ULP_ACT_HID_22880, - .act_pattern_id = 241, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [627] = { - .act_hid = BNXT_ULP_ACT_HID_f880, - .act_pattern_id = 242, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [628] = { - .act_hid = BNXT_ULP_ACT_HID_6ba0, - .act_pattern_id = 243, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [629] = { - .act_hid = BNXT_ULP_ACT_HID_1e420, - .act_pattern_id = 244, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [630] = { - .act_hid = BNXT_ULP_ACT_HID_26ca0, - .act_pattern_id = 245, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [631] = { - .act_hid = BNXT_ULP_ACT_HID_b000, - .act_pattern_id = 246, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [632] = { - .act_hid = BNXT_ULP_ACT_HID_26880, - .act_pattern_id = 247, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [633] = { - .act_hid = BNXT_ULP_ACT_HID_13880, - .act_pattern_id = 248, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [634] = { - .act_hid = BNXT_ULP_ACT_HID_aba0, - .act_pattern_id = 249, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [635] = { - .act_hid = BNXT_ULP_ACT_HID_22420, - .act_pattern_id = 250, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [636] = { - .act_hid = BNXT_ULP_ACT_HID_2aca0, - .act_pattern_id = 251, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [637] = { - .act_hid = BNXT_ULP_ACT_HID_f000, - .act_pattern_id = 252, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [638] = { - .act_hid = BNXT_ULP_ACT_HID_2a880, - .act_pattern_id = 253, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [639] = { - .act_hid = BNXT_ULP_ACT_HID_17880, - .act_pattern_id = 254, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [640] = { - .act_hid = BNXT_ULP_ACT_HID_eba0, - .act_pattern_id = 255, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [641] = { - .act_hid = BNXT_ULP_ACT_HID_26420, - .act_pattern_id = 256, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [642] = { - .act_hid = BNXT_ULP_ACT_HID_2eca0, - .act_pattern_id = 257, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [643] = { - .act_hid = BNXT_ULP_ACT_HID_fbc0, - .act_pattern_id = 258, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [644] = { - .act_hid = BNXT_ULP_ACT_HID_2b440, - .act_pattern_id = 259, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [645] = { - .act_hid = BNXT_ULP_ACT_HID_1a440, - .act_pattern_id = 260, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [646] = { - .act_hid = BNXT_ULP_ACT_HID_f760, - .act_pattern_id = 261, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [647] = { - .act_hid = BNXT_ULP_ACT_HID_26fe0, - .act_pattern_id = 262, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [648] = { - .act_hid = BNXT_ULP_ACT_HID_2f860, - .act_pattern_id = 263, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [649] = { - .act_hid = BNXT_ULP_ACT_HID_fc40, - .act_pattern_id = 264, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [650] = { - .act_hid = BNXT_ULP_ACT_HID_2b4c0, - .act_pattern_id = 265, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [651] = { - .act_hid = BNXT_ULP_ACT_HID_1a4c0, - .act_pattern_id = 266, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [652] = { - .act_hid = BNXT_ULP_ACT_HID_f7e0, - .act_pattern_id = 267, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [653] = { - .act_hid = BNXT_ULP_ACT_HID_27060, - .act_pattern_id = 268, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [654] = { - .act_hid = BNXT_ULP_ACT_HID_2f8e0, - .act_pattern_id = 269, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [655] = { - .act_hid = BNXT_ULP_ACT_HID_2f440, - .act_pattern_id = 270, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [656] = { - .act_hid = BNXT_ULP_ACT_HID_1e440, - .act_pattern_id = 271, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [657] = { - .act_hid = BNXT_ULP_ACT_HID_13760, - .act_pattern_id = 272, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [658] = { - .act_hid = BNXT_ULP_ACT_HID_13bc0, - .act_pattern_id = 273, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [659] = { - .act_hid = BNXT_ULP_ACT_HID_2afe0, - .act_pattern_id = 274, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [660] = { - .act_hid = BNXT_ULP_ACT_HID_33860, - .act_pattern_id = 275, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [661] = { - .act_hid = BNXT_ULP_ACT_HID_13c40, - .act_pattern_id = 276, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [662] = { - .act_hid = BNXT_ULP_ACT_HID_2f4c0, - .act_pattern_id = 277, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [663] = { - .act_hid = BNXT_ULP_ACT_HID_1e4c0, - .act_pattern_id = 278, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [664] = { - .act_hid = BNXT_ULP_ACT_HID_137e0, - .act_pattern_id = 279, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [665] = { - .act_hid = BNXT_ULP_ACT_HID_2b060, - .act_pattern_id = 280, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [666] = { - .act_hid = BNXT_ULP_ACT_HID_338e0, - .act_pattern_id = 281, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [667] = { - .act_hid = BNXT_ULP_ACT_HID_17bc0, - .act_pattern_id = 282, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [668] = { - .act_hid = BNXT_ULP_ACT_HID_33440, - .act_pattern_id = 283, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [669] = { - .act_hid = BNXT_ULP_ACT_HID_22440, - .act_pattern_id = 284, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [670] = { - .act_hid = BNXT_ULP_ACT_HID_17760, - .act_pattern_id = 285, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [671] = { - .act_hid = BNXT_ULP_ACT_HID_2efe0, - .act_pattern_id = 286, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [672] = { - .act_hid = BNXT_ULP_ACT_HID_37860, - .act_pattern_id = 287, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [673] = { - .act_hid = BNXT_ULP_ACT_HID_17c40, - .act_pattern_id = 288, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [674] = { - .act_hid = BNXT_ULP_ACT_HID_334c0, - .act_pattern_id = 289, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [675] = { - .act_hid = BNXT_ULP_ACT_HID_224c0, - .act_pattern_id = 290, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [676] = { - .act_hid = BNXT_ULP_ACT_HID_177e0, - .act_pattern_id = 291, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [677] = { - .act_hid = BNXT_ULP_ACT_HID_2f060, - .act_pattern_id = 292, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [678] = { - .act_hid = BNXT_ULP_ACT_HID_378e0, - .act_pattern_id = 293, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [679] = { - .act_hid = BNXT_ULP_ACT_HID_1bbc0, - .act_pattern_id = 294, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [680] = { - .act_hid = BNXT_ULP_ACT_HID_37440, - .act_pattern_id = 295, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [681] = { - .act_hid = BNXT_ULP_ACT_HID_26440, - .act_pattern_id = 296, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [682] = { - .act_hid = BNXT_ULP_ACT_HID_1b760, - .act_pattern_id = 297, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [683] = { - .act_hid = BNXT_ULP_ACT_HID_32fe0, - .act_pattern_id = 298, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [684] = { - .act_hid = BNXT_ULP_ACT_HID_3b860, - .act_pattern_id = 299, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [685] = { - .act_hid = BNXT_ULP_ACT_HID_1bc40, - .act_pattern_id = 300, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [686] = { - .act_hid = BNXT_ULP_ACT_HID_374c0, - .act_pattern_id = 301, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_VXLAN_DECAP | + BNXT_ULP_ACT_BIT_GENEVE_DECAP | BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_SRC | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [687] = { - .act_hid = BNXT_ULP_ACT_HID_264c0, - .act_pattern_id = 302, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | + BNXT_ULP_ACT_BIT_METER | + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | BNXT_ULP_ACT_BIT_SET_MAC_SRC | BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [688] = { - .act_hid = BNXT_ULP_ACT_HID_1b7e0, - .act_pattern_id = 303, - .app_sig = 0, - .act_sig = { .bits = BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 1 }, - [689] = { - .act_hid = BNXT_ULP_ACT_HID_33060, - .act_pattern_id = 304, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | + [2] = { + .act_bitmap = { .bits = + BNXT_ULP_ACT_BIT_SHARED | + BNXT_ULP_ACT_BIT_SAMPLE | BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_ACT_BIT_SET_IPV4_DST | - BNXT_ULP_ACT_BIT_SET_TP_SRC | - BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 2 + }, + [3] = { + .act_bitmap = { .bits = + BNXT_ULP_ACT_BIT_DELETE | + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 2 }, - [690] = { - .act_hid = BNXT_ULP_ACT_HID_3b8e0, - .act_pattern_id = 305, - .app_sig = 0, - .act_sig = { .bits = + [4] = { + .act_bitmap = { .bits = + BNXT_ULP_ACT_BIT_COUNT | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | BNXT_ULP_ACT_BIT_MULTIPLE_PORT | BNXT_ULP_ACT_BIT_SET_MAC_SRC | BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_DEC_TTL | - BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_ACT_BIT_SET_IPV4_SRC | BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_IPV6_SRC | + BNXT_ULP_ACT_BIT_SET_IPV6_DST | BNXT_ULP_ACT_BIT_SET_TP_SRC | BNXT_ULP_ACT_BIT_SET_TP_DST | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 7 - }, - [691] = { - .act_hid = BNXT_ULP_ACT_HID_18e80, - .act_pattern_id = 0, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_VXLAN_ENCAP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 8 - }, - [692] = { - .act_hid = BNXT_ULP_ACT_HID_18f00, - .act_pattern_id = 1, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_VXLAN_ENCAP | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 8 - }, - [693] = { - .act_hid = BNXT_ULP_ACT_HID_1ce80, - .act_pattern_id = 2, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_VXLAN_ENCAP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 8 - }, - [694] = { - .act_hid = BNXT_ULP_ACT_HID_1cf00, - .act_pattern_id = 3, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_VXLAN_ENCAP | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 8 - }, - [695] = { - .act_hid = BNXT_ULP_ACT_HID_20e80, - .act_pattern_id = 4, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_VXLAN_ENCAP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 8 - }, - [696] = { - .act_hid = BNXT_ULP_ACT_HID_20f00, - .act_pattern_id = 5, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_VXLAN_ENCAP | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 8 - }, - [697] = { - .act_hid = BNXT_ULP_ACT_HID_24e80, - .act_pattern_id = 6, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_VXLAN_ENCAP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 8 - }, - [698] = { - .act_hid = BNXT_ULP_ACT_HID_24f00, - .act_pattern_id = 7, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_VXLAN_ENCAP | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 8 - }, - [699] = { - .act_hid = BNXT_ULP_ACT_HID_325c2, - .act_pattern_id = 8, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_VXLAN_ENCAP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 8 + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 }, - [700] = { - .act_hid = BNXT_ULP_ACT_HID_32642, - .act_pattern_id = 9, - .app_sig = 0, - .act_sig = { .bits = + [5] = { + .act_bitmap = { .bits = BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_VXLAN_ENCAP | + BNXT_ULP_ACT_BIT_RSS | + BNXT_ULP_ACT_BIT_QUEUE | BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 8 + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 4 }, - [701] = { - .act_hid = BNXT_ULP_ACT_HID_365c2, - .act_pattern_id = 10, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_VXLAN_ENCAP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 8 + [6] = { + .act_bitmap = { .bits = + BNXT_ULP_ACT_BIT_METER_PROFILE | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 5 }, - [702] = { - .act_hid = BNXT_ULP_ACT_HID_36642, - .act_pattern_id = 11, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_VXLAN_ENCAP | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 8 + [7] = { + .act_bitmap = { .bits = + BNXT_ULP_ACT_BIT_SHARED_METER | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 5 }, - [703] = { - .act_hid = BNXT_ULP_ACT_HID_3a5c2, - .act_pattern_id = 12, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_VXLAN_ENCAP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 8 + [8] = { + .act_bitmap = { .bits = + BNXT_ULP_ACT_BIT_DELETE | + BNXT_ULP_ACT_BIT_METER_PROFILE | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 5 }, - [704] = { - .act_hid = BNXT_ULP_ACT_HID_3a642, - .act_pattern_id = 13, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_VXLAN_ENCAP | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 8 + [9] = { + .act_bitmap = { .bits = + BNXT_ULP_ACT_BIT_DELETE | + BNXT_ULP_ACT_BIT_SHARED_METER | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 5 }, - [705] = { - .act_hid = BNXT_ULP_ACT_HID_07e2, - .act_pattern_id = 14, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_VXLAN_ENCAP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 8 + [10] = { + .act_bitmap = { .bits = + BNXT_ULP_ACT_BIT_UPDATE | + BNXT_ULP_ACT_BIT_SHARED_METER | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 5 }, - [706] = { - .act_hid = BNXT_ULP_ACT_HID_0862, - .act_pattern_id = 15, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_VXLAN_ENCAP | + [11] = { + .act_bitmap = { .bits = + BNXT_ULP_ACT_BIT_DROP | + BNXT_ULP_ACT_BIT_SET_VLAN_PCP | + BNXT_ULP_ACT_BIT_SET_VLAN_VID | + BNXT_ULP_ACT_BIT_PUSH_VLAN | BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 8 - }, - [707] = { - .act_hid = BNXT_ULP_ACT_HID_22b20, - .act_pattern_id = 16, - .app_sig = 0, - .act_sig = { .bits = + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_VXLAN_ENCAP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 8 + .act_tid = 6 }, - [708] = { - .act_hid = BNXT_ULP_ACT_HID_22ba0, - .act_pattern_id = 17, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_VXLAN_ENCAP | + [12] = { + .act_bitmap = { .bits = BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 8 - }, - [709] = { - .act_hid = BNXT_ULP_ACT_HID_26b20, - .act_pattern_id = 18, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_VXLAN_ENCAP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 8 - }, - [710] = { - .act_hid = BNXT_ULP_ACT_HID_26ba0, - .act_pattern_id = 19, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_VXLAN_ENCAP | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 8 - }, - [711] = { - .act_hid = BNXT_ULP_ACT_HID_2ab20, - .act_pattern_id = 20, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_VXLAN_ENCAP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 8 - }, - [712] = { - .act_hid = BNXT_ULP_ACT_HID_2aba0, - .act_pattern_id = 21, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_VXLAN_ENCAP | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 8 - }, - [713] = { - .act_hid = BNXT_ULP_ACT_HID_2eb20, - .act_pattern_id = 22, - .app_sig = 0, - .act_sig = { .bits = + BNXT_ULP_ACT_BIT_SET_IPV4_SRC | + BNXT_ULP_ACT_BIT_SET_IPV4_DST | + BNXT_ULP_ACT_BIT_SET_IPV6_SRC | + BNXT_ULP_ACT_BIT_SET_IPV6_DST | + BNXT_ULP_ACT_BIT_SET_TP_SRC | + BNXT_ULP_ACT_BIT_SET_TP_DST | + BNXT_ULP_ACT_BIT_DEC_TTL | + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_SET_MAC_SRC | - BNXT_ULP_ACT_BIT_SET_MAC_DST | - BNXT_ULP_ACT_BIT_VXLAN_ENCAP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 8 + .act_tid = 7 }, - [714] = { - .act_hid = BNXT_ULP_ACT_HID_2eba0, - .act_pattern_id = 23, - .app_sig = 0, - .act_sig = { .bits = + [13] = { + .act_bitmap = { .bits = + BNXT_ULP_ACT_BIT_SHARED_SAMPLE | BNXT_ULP_ACT_BIT_MULTIPLE_PORT | BNXT_ULP_ACT_BIT_SET_MAC_SRC | BNXT_ULP_ACT_BIT_SET_MAC_DST | BNXT_ULP_ACT_BIT_VXLAN_ENCAP | + BNXT_ULP_ACT_BIT_GENEVE_ENCAP | BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 8 }, - [715] = { - .act_hid = BNXT_ULP_ACT_HID_199e0, - .act_pattern_id = 0, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_VF_TO_VF | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 9 - }, - [716] = { - .act_hid = BNXT_ULP_ACT_HID_19960, - .act_pattern_id = 1, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_VF_TO_VF | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 9 - }, - [717] = { - .act_hid = BNXT_ULP_ACT_HID_33122, - .act_pattern_id = 2, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_VF_TO_VF | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 9 - }, - [718] = { - .act_hid = BNXT_ULP_ACT_HID_331a2, - .act_pattern_id = 3, - .app_sig = 0, - .act_sig = { .bits = + [14] = { + .act_bitmap = { .bits = BNXT_ULP_ACT_BIT_SHARED_SAMPLE | - BNXT_ULP_ACT_BIT_VF_TO_VF | - BNXT_ULP_ACT_BIT_COUNT | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 9 - }, - [719] = { - .act_hid = BNXT_ULP_ACT_HID_23580, - .act_pattern_id = 4, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_MULTIPLE_PORT | - BNXT_ULP_ACT_BIT_VF_TO_VF | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 9 - }, - [720] = { - .act_hid = BNXT_ULP_ACT_HID_23700, - .act_pattern_id = 5, - .app_sig = 0, - .act_sig = { .bits = BNXT_ULP_ACT_BIT_MULTIPLE_PORT | BNXT_ULP_ACT_BIT_VF_TO_VF | BNXT_ULP_ACT_BIT_COUNT | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 9 }, - [721] = { - .act_hid = BNXT_ULP_ACT_HID_db61, - .act_pattern_id = 0, - .app_sig = 0, - .act_sig = { .bits = - BNXT_ULP_ACT_BIT_SHARED | - BNXT_ULP_ACT_BIT_SAMPLE | - BNXT_ULP_ACT_BIT_VF_TO_VF | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 10 - }, - [722] = { - .act_hid = BNXT_ULP_ACT_HID_dbe1, - .act_pattern_id = 1, - .app_sig = 0, - .act_sig = { .bits = + [15] = { + .act_bitmap = { .bits = BNXT_ULP_ACT_BIT_SHARED | BNXT_ULP_ACT_BIT_SAMPLE | BNXT_ULP_ACT_BIT_VF_TO_VF | @@ -9534,11 +160,8 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = { BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .act_tid = 10 }, - [723] = { - .act_hid = BNXT_ULP_ACT_HID_320ca, - .act_pattern_id = 2, - .app_sig = 0, - .act_sig = { .bits = + [16] = { + .act_bitmap = { .bits = BNXT_ULP_ACT_BIT_DELETE | BNXT_ULP_ACT_BIT_SHARED_SAMPLE | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c index e6ea114f1b..6ef1016d9f 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c @@ -8,42734 +8,7186 @@ #include "ulp_template_struct.h" #include "ulp_template_db_tbl.h" -/* Define the template structures */ +/* Define the template match patterns */ /* - * Classification signature table: - * maps hash id to ulp_class_match_list[] index + * List of protocol matches */ -uint16_t ulp_class_sig_tbl[BNXT_ULP_CLASS_SIG_TBL_MAX_SZ] = { - [BNXT_ULP_CLASS_HID_00b8] = 1, - [BNXT_ULP_CLASS_HID_0cc2] = 2, - [BNXT_ULP_CLASS_HID_10e4] = 3, - [BNXT_ULP_CLASS_HID_1d0e] = 4, - [BNXT_ULP_CLASS_HID_0286] = 5, - [BNXT_ULP_CLASS_HID_0e98] = 6, - [BNXT_ULP_CLASS_HID_1666] = 7, - [BNXT_ULP_CLASS_HID_02de] = 8, - [BNXT_ULP_CLASS_HID_81d25] = 9, - [BNXT_ULP_CLASS_HID_809ad] = 10, - [BNXT_ULP_CLASS_HID_80ae3] = 11, - [BNXT_ULP_CLASS_HID_8170d] = 12, - [BNXT_ULP_CLASS_HID_80773] = 13, - [BNXT_ULP_CLASS_HID_8139d] = 14, - [BNXT_ULP_CLASS_HID_814d3] = 15, - [BNXT_ULP_CLASS_HID_8015b] = 16, - [BNXT_ULP_CLASS_HID_21977] = 17, - [BNXT_ULP_CLASS_HID_205ef] = 18, - [BNXT_ULP_CLASS_HID_20735] = 19, - [BNXT_ULP_CLASS_HID_2134f] = 20, - [BNXT_ULP_CLASS_HID_61beb] = 21, - [BNXT_ULP_CLASS_HID_60863] = 22, - [BNXT_ULP_CLASS_HID_609a9] = 23, - [BNXT_ULP_CLASS_HID_615c3] = 24, - [BNXT_ULP_CLASS_HID_00a8] = 25, - [BNXT_ULP_CLASS_HID_0cd2] = 26, - [BNXT_ULP_CLASS_HID_10f4] = 27, - [BNXT_ULP_CLASS_HID_1d1e] = 28, - [BNXT_ULP_CLASS_HID_1488] = 29, - [BNXT_ULP_CLASS_HID_0110] = 30, - [BNXT_ULP_CLASS_HID_0532] = 31, - [BNXT_ULP_CLASS_HID_115c] = 32, - [BNXT_ULP_CLASS_HID_0ab8] = 33, - [BNXT_ULP_CLASS_HID_16a2] = 34, - [BNXT_ULP_CLASS_HID_1ac4] = 35, - [BNXT_ULP_CLASS_HID_074c] = 36, - [BNXT_ULP_CLASS_HID_1e98] = 37, - [BNXT_ULP_CLASS_HID_0ae0] = 38, - [BNXT_ULP_CLASS_HID_0f02] = 39, - [BNXT_ULP_CLASS_HID_1b2c] = 40, - [BNXT_ULP_CLASS_HID_0296] = 41, - [BNXT_ULP_CLASS_HID_0e88] = 42, - [BNXT_ULP_CLASS_HID_1676] = 43, - [BNXT_ULP_CLASS_HID_02ce] = 44, - [BNXT_ULP_CLASS_HID_8076e] = 45, - [BNXT_ULP_CLASS_HID_81380] = 46, - [BNXT_ULP_CLASS_HID_81b4e] = 47, - [BNXT_ULP_CLASS_HID_807c6] = 48, - [BNXT_ULP_CLASS_HID_404ea] = 49, - [BNXT_ULP_CLASS_HID_4110c] = 50, - [BNXT_ULP_CLASS_HID_418ca] = 51, - [BNXT_ULP_CLASS_HID_40542] = 52, - [BNXT_ULP_CLASS_HID_c09e2] = 53, - [BNXT_ULP_CLASS_HID_c1604] = 54, - [BNXT_ULP_CLASS_HID_c1dc2] = 55, - [BNXT_ULP_CLASS_HID_c0a5a] = 56, - [BNXT_ULP_CLASS_HID_0098] = 57, - [BNXT_ULP_CLASS_HID_0ce2] = 58, - [BNXT_ULP_CLASS_HID_10c4] = 59, - [BNXT_ULP_CLASS_HID_1d2e] = 60, - [BNXT_ULP_CLASS_HID_14b8] = 61, - [BNXT_ULP_CLASS_HID_0120] = 62, - [BNXT_ULP_CLASS_HID_0502] = 63, - [BNXT_ULP_CLASS_HID_116c] = 64, - [BNXT_ULP_CLASS_HID_0a88] = 65, - [BNXT_ULP_CLASS_HID_1692] = 66, - [BNXT_ULP_CLASS_HID_1af4] = 67, - [BNXT_ULP_CLASS_HID_077c] = 68, - [BNXT_ULP_CLASS_HID_1ea8] = 69, - [BNXT_ULP_CLASS_HID_0ad0] = 70, - [BNXT_ULP_CLASS_HID_0f32] = 71, - [BNXT_ULP_CLASS_HID_1b1c] = 72, - [BNXT_ULP_CLASS_HID_02a6] = 73, - [BNXT_ULP_CLASS_HID_0eb8] = 74, - [BNXT_ULP_CLASS_HID_1646] = 75, - [BNXT_ULP_CLASS_HID_02fe] = 76, - [BNXT_ULP_CLASS_HID_8075e] = 77, - [BNXT_ULP_CLASS_HID_813b0] = 78, - [BNXT_ULP_CLASS_HID_81b7e] = 79, - [BNXT_ULP_CLASS_HID_807f6] = 80, - [BNXT_ULP_CLASS_HID_404da] = 81, - [BNXT_ULP_CLASS_HID_4113c] = 82, - [BNXT_ULP_CLASS_HID_418fa] = 83, - [BNXT_ULP_CLASS_HID_40572] = 84, - [BNXT_ULP_CLASS_HID_c09d2] = 85, - [BNXT_ULP_CLASS_HID_c1634] = 86, - [BNXT_ULP_CLASS_HID_c1df2] = 87, - [BNXT_ULP_CLASS_HID_c0a6a] = 88, - [BNXT_ULP_CLASS_HID_81d35] = 89, - [BNXT_ULP_CLASS_HID_809bd] = 90, - [BNXT_ULP_CLASS_HID_80af3] = 91, - [BNXT_ULP_CLASS_HID_8171d] = 92, - [BNXT_ULP_CLASS_HID_80763] = 93, - [BNXT_ULP_CLASS_HID_8138d] = 94, - [BNXT_ULP_CLASS_HID_814c3] = 95, - [BNXT_ULP_CLASS_HID_8014b] = 96, - [BNXT_ULP_CLASS_HID_c001f] = 97, - [BNXT_ULP_CLASS_HID_c0c39] = 98, - [BNXT_ULP_CLASS_HID_c0d7f] = 99, - [BNXT_ULP_CLASS_HID_c1999] = 100, - [BNXT_ULP_CLASS_HID_c09ef] = 101, - [BNXT_ULP_CLASS_HID_c1609] = 102, - [BNXT_ULP_CLASS_HID_c174f] = 103, - [BNXT_ULP_CLASS_HID_c03d7] = 104, - [BNXT_ULP_CLASS_HID_a1e73] = 105, - [BNXT_ULP_CLASS_HID_a0afb] = 106, - [BNXT_ULP_CLASS_HID_a0c31] = 107, - [BNXT_ULP_CLASS_HID_a185b] = 108, - [BNXT_ULP_CLASS_HID_a08a1] = 109, - [BNXT_ULP_CLASS_HID_a14cb] = 110, - [BNXT_ULP_CLASS_HID_a1601] = 111, - [BNXT_ULP_CLASS_HID_a0289] = 112, - [BNXT_ULP_CLASS_HID_e015d] = 113, - [BNXT_ULP_CLASS_HID_e0d47] = 114, - [BNXT_ULP_CLASS_HID_e0ebd] = 115, - [BNXT_ULP_CLASS_HID_e1aa7] = 116, - [BNXT_ULP_CLASS_HID_e0b2d] = 117, - [BNXT_ULP_CLASS_HID_e1757] = 118, - [BNXT_ULP_CLASS_HID_e188d] = 119, - [BNXT_ULP_CLASS_HID_e0515] = 120, - [BNXT_ULP_CLASS_HID_21967] = 121, - [BNXT_ULP_CLASS_HID_205ff] = 122, - [BNXT_ULP_CLASS_HID_20725] = 123, - [BNXT_ULP_CLASS_HID_2135f] = 124, - [BNXT_ULP_CLASS_HID_61bfb] = 125, - [BNXT_ULP_CLASS_HID_60873] = 126, - [BNXT_ULP_CLASS_HID_609b9] = 127, - [BNXT_ULP_CLASS_HID_615d3] = 128, - [BNXT_ULP_CLASS_HID_30a55] = 129, - [BNXT_ULP_CLASS_HID_3164f] = 130, - [BNXT_ULP_CLASS_HID_317b5] = 131, - [BNXT_ULP_CLASS_HID_3040d] = 132, - [BNXT_ULP_CLASS_HID_70ca9] = 133, - [BNXT_ULP_CLASS_HID_718c3] = 134, - [BNXT_ULP_CLASS_HID_71a09] = 135, - [BNXT_ULP_CLASS_HID_70681] = 136, - [BNXT_ULP_CLASS_HID_2821d] = 137, - [BNXT_ULP_CLASS_HID_28e37] = 138, - [BNXT_ULP_CLASS_HID_28f7d] = 139, - [BNXT_ULP_CLASS_HID_29b97] = 140, - [BNXT_ULP_CLASS_HID_68491] = 141, - [BNXT_ULP_CLASS_HID_6908b] = 142, - [BNXT_ULP_CLASS_HID_691f1] = 143, - [BNXT_ULP_CLASS_HID_69deb] = 144, - [BNXT_ULP_CLASS_HID_3926d] = 145, - [BNXT_ULP_CLASS_HID_39e87] = 146, - [BNXT_ULP_CLASS_HID_38023] = 147, - [BNXT_ULP_CLASS_HID_38c45] = 148, - [BNXT_ULP_CLASS_HID_794e1] = 149, - [BNXT_ULP_CLASS_HID_78179] = 150, - [BNXT_ULP_CLASS_HID_782a7] = 151, - [BNXT_ULP_CLASS_HID_78ed9] = 152, - [BNXT_ULP_CLASS_HID_81d05] = 153, - [BNXT_ULP_CLASS_HID_8098d] = 154, - [BNXT_ULP_CLASS_HID_80ac3] = 155, - [BNXT_ULP_CLASS_HID_8172d] = 156, - [BNXT_ULP_CLASS_HID_80753] = 157, - [BNXT_ULP_CLASS_HID_813bd] = 158, - [BNXT_ULP_CLASS_HID_814f3] = 159, - [BNXT_ULP_CLASS_HID_8017b] = 160, - [BNXT_ULP_CLASS_HID_c002f] = 161, - [BNXT_ULP_CLASS_HID_c0c09] = 162, - [BNXT_ULP_CLASS_HID_c0d4f] = 163, - [BNXT_ULP_CLASS_HID_c19a9] = 164, - [BNXT_ULP_CLASS_HID_c09df] = 165, - [BNXT_ULP_CLASS_HID_c1639] = 166, - [BNXT_ULP_CLASS_HID_c177f] = 167, - [BNXT_ULP_CLASS_HID_c03e7] = 168, - [BNXT_ULP_CLASS_HID_a1e43] = 169, - [BNXT_ULP_CLASS_HID_a0acb] = 170, - [BNXT_ULP_CLASS_HID_a0c01] = 171, - [BNXT_ULP_CLASS_HID_a186b] = 172, - [BNXT_ULP_CLASS_HID_a0891] = 173, - [BNXT_ULP_CLASS_HID_a14fb] = 174, - [BNXT_ULP_CLASS_HID_a1631] = 175, - [BNXT_ULP_CLASS_HID_a02b9] = 176, - [BNXT_ULP_CLASS_HID_e016d] = 177, - [BNXT_ULP_CLASS_HID_e0d77] = 178, - [BNXT_ULP_CLASS_HID_e0e8d] = 179, - [BNXT_ULP_CLASS_HID_e1a97] = 180, - [BNXT_ULP_CLASS_HID_e0b1d] = 181, - [BNXT_ULP_CLASS_HID_e1767] = 182, - [BNXT_ULP_CLASS_HID_e18bd] = 183, - [BNXT_ULP_CLASS_HID_e0525] = 184, - [BNXT_ULP_CLASS_HID_21957] = 185, - [BNXT_ULP_CLASS_HID_205cf] = 186, - [BNXT_ULP_CLASS_HID_20715] = 187, - [BNXT_ULP_CLASS_HID_2136f] = 188, - [BNXT_ULP_CLASS_HID_61bcb] = 189, - [BNXT_ULP_CLASS_HID_60843] = 190, - [BNXT_ULP_CLASS_HID_60989] = 191, - [BNXT_ULP_CLASS_HID_615e3] = 192, - [BNXT_ULP_CLASS_HID_30a65] = 193, - [BNXT_ULP_CLASS_HID_3167f] = 194, - [BNXT_ULP_CLASS_HID_31785] = 195, - [BNXT_ULP_CLASS_HID_3043d] = 196, - [BNXT_ULP_CLASS_HID_70c99] = 197, - [BNXT_ULP_CLASS_HID_718f3] = 198, - [BNXT_ULP_CLASS_HID_71a39] = 199, - [BNXT_ULP_CLASS_HID_706b1] = 200, - [BNXT_ULP_CLASS_HID_2822d] = 201, - [BNXT_ULP_CLASS_HID_28e07] = 202, - [BNXT_ULP_CLASS_HID_28f4d] = 203, - [BNXT_ULP_CLASS_HID_29ba7] = 204, - [BNXT_ULP_CLASS_HID_684a1] = 205, - [BNXT_ULP_CLASS_HID_690bb] = 206, - [BNXT_ULP_CLASS_HID_691c1] = 207, - [BNXT_ULP_CLASS_HID_69ddb] = 208, - [BNXT_ULP_CLASS_HID_3925d] = 209, - [BNXT_ULP_CLASS_HID_39eb7] = 210, - [BNXT_ULP_CLASS_HID_38013] = 211, - [BNXT_ULP_CLASS_HID_38c75] = 212, - [BNXT_ULP_CLASS_HID_794d1] = 213, - [BNXT_ULP_CLASS_HID_78149] = 214, - [BNXT_ULP_CLASS_HID_78297] = 215, - [BNXT_ULP_CLASS_HID_78ee9] = 216, - [BNXT_ULP_CLASS_HID_0816] = 217, - [BNXT_ULP_CLASS_HID_1852] = 218, - [BNXT_ULP_CLASS_HID_09f4] = 219, - [BNXT_ULP_CLASS_HID_1dd4] = 220, - [BNXT_ULP_CLASS_HID_804f1] = 221, - [BNXT_ULP_CLASS_HID_81251] = 222, - [BNXT_ULP_CLASS_HID_80ee1] = 223, - [BNXT_ULP_CLASS_HID_81c41] = 224, - [BNXT_ULP_CLASS_HID_2013b] = 225, - [BNXT_ULP_CLASS_HID_20e9b] = 226, - [BNXT_ULP_CLASS_HID_603bf] = 227, - [BNXT_ULP_CLASS_HID_6111f] = 228, - [BNXT_ULP_CLASS_HID_0806] = 229, - [BNXT_ULP_CLASS_HID_1842] = 230, - [BNXT_ULP_CLASS_HID_1be6] = 231, - [BNXT_ULP_CLASS_HID_0c80] = 232, - [BNXT_ULP_CLASS_HID_1216] = 233, - [BNXT_ULP_CLASS_HID_02b0] = 234, - [BNXT_ULP_CLASS_HID_0654] = 235, - [BNXT_ULP_CLASS_HID_1690] = 236, - [BNXT_ULP_CLASS_HID_09e4] = 237, - [BNXT_ULP_CLASS_HID_1dc4] = 238, - [BNXT_ULP_CLASS_HID_80efc] = 239, - [BNXT_ULP_CLASS_HID_80332] = 240, - [BNXT_ULP_CLASS_HID_40c78] = 241, - [BNXT_ULP_CLASS_HID_400be] = 242, - [BNXT_ULP_CLASS_HID_c1170] = 243, - [BNXT_ULP_CLASS_HID_c05b6] = 244, - [BNXT_ULP_CLASS_HID_0836] = 245, - [BNXT_ULP_CLASS_HID_1872] = 246, - [BNXT_ULP_CLASS_HID_1bd6] = 247, - [BNXT_ULP_CLASS_HID_0cb0] = 248, - [BNXT_ULP_CLASS_HID_1226] = 249, - [BNXT_ULP_CLASS_HID_0280] = 250, - [BNXT_ULP_CLASS_HID_0664] = 251, - [BNXT_ULP_CLASS_HID_16a0] = 252, - [BNXT_ULP_CLASS_HID_09d4] = 253, - [BNXT_ULP_CLASS_HID_1df4] = 254, - [BNXT_ULP_CLASS_HID_80ecc] = 255, - [BNXT_ULP_CLASS_HID_80302] = 256, - [BNXT_ULP_CLASS_HID_40c48] = 257, - [BNXT_ULP_CLASS_HID_4008e] = 258, - [BNXT_ULP_CLASS_HID_c1140] = 259, - [BNXT_ULP_CLASS_HID_c0586] = 260, - [BNXT_ULP_CLASS_HID_804e1] = 261, - [BNXT_ULP_CLASS_HID_81241] = 262, - [BNXT_ULP_CLASS_HID_80ef1] = 263, - [BNXT_ULP_CLASS_HID_81c51] = 264, - [BNXT_ULP_CLASS_HID_c076d] = 265, - [BNXT_ULP_CLASS_HID_c14cd] = 266, - [BNXT_ULP_CLASS_HID_c117d] = 267, - [BNXT_ULP_CLASS_HID_c1edd] = 268, - [BNXT_ULP_CLASS_HID_a062f] = 269, - [BNXT_ULP_CLASS_HID_a138f] = 270, - [BNXT_ULP_CLASS_HID_a103f] = 271, - [BNXT_ULP_CLASS_HID_a1d9f] = 272, - [BNXT_ULP_CLASS_HID_e08ab] = 273, - [BNXT_ULP_CLASS_HID_e160b] = 274, - [BNXT_ULP_CLASS_HID_e12bb] = 275, - [BNXT_ULP_CLASS_HID_e0079] = 276, - [BNXT_ULP_CLASS_HID_2012b] = 277, - [BNXT_ULP_CLASS_HID_20e8b] = 278, - [BNXT_ULP_CLASS_HID_603af] = 279, - [BNXT_ULP_CLASS_HID_6110f] = 280, - [BNXT_ULP_CLASS_HID_311bb] = 281, - [BNXT_ULP_CLASS_HID_31f1b] = 282, - [BNXT_ULP_CLASS_HID_7143f] = 283, - [BNXT_ULP_CLASS_HID_701fd] = 284, - [BNXT_ULP_CLASS_HID_28963] = 285, - [BNXT_ULP_CLASS_HID_296c3] = 286, - [BNXT_ULP_CLASS_HID_68be7] = 287, - [BNXT_ULP_CLASS_HID_69947] = 288, - [BNXT_ULP_CLASS_HID_399f3] = 289, - [BNXT_ULP_CLASS_HID_387b1] = 290, - [BNXT_ULP_CLASS_HID_79c77] = 291, - [BNXT_ULP_CLASS_HID_78a35] = 292, - [BNXT_ULP_CLASS_HID_804d1] = 293, - [BNXT_ULP_CLASS_HID_81271] = 294, - [BNXT_ULP_CLASS_HID_80ec1] = 295, - [BNXT_ULP_CLASS_HID_81c61] = 296, - [BNXT_ULP_CLASS_HID_c075d] = 297, - [BNXT_ULP_CLASS_HID_c14fd] = 298, - [BNXT_ULP_CLASS_HID_c114d] = 299, - [BNXT_ULP_CLASS_HID_c1eed] = 300, - [BNXT_ULP_CLASS_HID_a061f] = 301, - [BNXT_ULP_CLASS_HID_a13bf] = 302, - [BNXT_ULP_CLASS_HID_a100f] = 303, - [BNXT_ULP_CLASS_HID_a1daf] = 304, - [BNXT_ULP_CLASS_HID_e089b] = 305, - [BNXT_ULP_CLASS_HID_e163b] = 306, - [BNXT_ULP_CLASS_HID_e128b] = 307, - [BNXT_ULP_CLASS_HID_e0049] = 308, - [BNXT_ULP_CLASS_HID_2011b] = 309, - [BNXT_ULP_CLASS_HID_20ebb] = 310, - [BNXT_ULP_CLASS_HID_6039f] = 311, - [BNXT_ULP_CLASS_HID_6113f] = 312, - [BNXT_ULP_CLASS_HID_3118b] = 313, - [BNXT_ULP_CLASS_HID_31f2b] = 314, - [BNXT_ULP_CLASS_HID_7140f] = 315, - [BNXT_ULP_CLASS_HID_701cd] = 316, - [BNXT_ULP_CLASS_HID_28953] = 317, - [BNXT_ULP_CLASS_HID_296f3] = 318, - [BNXT_ULP_CLASS_HID_68bd7] = 319, - [BNXT_ULP_CLASS_HID_69977] = 320, - [BNXT_ULP_CLASS_HID_399c3] = 321, - [BNXT_ULP_CLASS_HID_38781] = 322, - [BNXT_ULP_CLASS_HID_79c47] = 323, - [BNXT_ULP_CLASS_HID_78a05] = 324, - [BNXT_ULP_CLASS_HID_04a4] = 325, - [BNXT_ULP_CLASS_HID_04a8] = 326, - [BNXT_ULP_CLASS_HID_04a5] = 327, - [BNXT_ULP_CLASS_HID_1205] = 328, - [BNXT_ULP_CLASS_HID_04a9] = 329, - [BNXT_ULP_CLASS_HID_1209] = 330, - [BNXT_ULP_CLASS_HID_04b4] = 331, - [BNXT_ULP_CLASS_HID_04b8] = 332, - [BNXT_ULP_CLASS_HID_0484] = 333, - [BNXT_ULP_CLASS_HID_0488] = 334, - [BNXT_ULP_CLASS_HID_04b5] = 335, - [BNXT_ULP_CLASS_HID_1215] = 336, - [BNXT_ULP_CLASS_HID_04b9] = 337, - [BNXT_ULP_CLASS_HID_1219] = 338, - [BNXT_ULP_CLASS_HID_0485] = 339, - [BNXT_ULP_CLASS_HID_1225] = 340, - [BNXT_ULP_CLASS_HID_0489] = 341, - [BNXT_ULP_CLASS_HID_1229] = 342, - [BNXT_ULP_CLASS_HID_0226] = 343, - [BNXT_ULP_CLASS_HID_4045a] = 344, - [BNXT_ULP_CLASS_HID_0daa] = 345, - [BNXT_ULP_CLASS_HID_11b0] = 346, - [BNXT_ULP_CLASS_HID_403f8] = 347, - [BNXT_ULP_CLASS_HID_4161e] = 348, - [BNXT_ULP_CLASS_HID_40439] = 349, - [BNXT_ULP_CLASS_HID_41405] = 350, - [BNXT_ULP_CLASS_HID_51449] = 351, - [BNXT_ULP_CLASS_HID_50b33] = 352, - [BNXT_ULP_CLASS_HID_48c01] = 353, - [BNXT_ULP_CLASS_HID_483eb] = 354, - [BNXT_ULP_CLASS_HID_5833f] = 355, - [BNXT_ULP_CLASS_HID_5937b] = 356, - [BNXT_ULP_CLASS_HID_41875] = 357, - [BNXT_ULP_CLASS_HID_40f5f] = 358, - [BNXT_ULP_CLASS_HID_50f23] = 359, - [BNXT_ULP_CLASS_HID_51f6f] = 360, - [BNXT_ULP_CLASS_HID_4875b] = 361, - [BNXT_ULP_CLASS_HID_49727] = 362, - [BNXT_ULP_CLASS_HID_5976b] = 363, - [BNXT_ULP_CLASS_HID_58655] = 364, - [BNXT_ULP_CLASS_HID_4125f] = 365, - [BNXT_ULP_CLASS_HID_401f9] = 366, - [BNXT_ULP_CLASS_HID_501cd] = 367, - [BNXT_ULP_CLASS_HID_51149] = 368, - [BNXT_ULP_CLASS_HID_49a67] = 369, - [BNXT_ULP_CLASS_HID_489c1] = 370, - [BNXT_ULP_CLASS_HID_58955] = 371, - [BNXT_ULP_CLASS_HID_59951] = 372, - [BNXT_ULP_CLASS_HID_40569] = 373, - [BNXT_ULP_CLASS_HID_41575] = 374, - [BNXT_ULP_CLASS_HID_51579] = 375, - [BNXT_ULP_CLASS_HID_50463] = 376, - [BNXT_ULP_CLASS_HID_48d71] = 377, - [BNXT_ULP_CLASS_HID_49d7d] = 378, - [BNXT_ULP_CLASS_HID_59d41] = 379, - [BNXT_ULP_CLASS_HID_58c6b] = 380, - [BNXT_ULP_CLASS_HID_10255] = 381, - [BNXT_ULP_CLASS_HID_11675] = 382, - [BNXT_ULP_CLASS_HID_14649] = 383, - [BNXT_ULP_CLASS_HID_15a69] = 384, - [BNXT_ULP_CLASS_HID_1205b] = 385, - [BNXT_ULP_CLASS_HID_1347b] = 386, - [BNXT_ULP_CLASS_HID_16bbf] = 387, - [BNXT_ULP_CLASS_HID_1785f] = 388, - [BNXT_ULP_CLASS_HID_11551] = 389, - [BNXT_ULP_CLASS_HID_10897] = 390, - [BNXT_ULP_CLASS_HID_15955] = 391, - [BNXT_ULP_CLASS_HID_14c8b] = 392, - [BNXT_ULP_CLASS_HID_13b47] = 393, - [BNXT_ULP_CLASS_HID_12e85] = 394, - [BNXT_ULP_CLASS_HID_17f5b] = 395, - [BNXT_ULP_CLASS_HID_17299] = 396, - [BNXT_ULP_CLASS_HID_10fe7] = 397, - [BNXT_ULP_CLASS_HID_10325] = 398, - [BNXT_ULP_CLASS_HID_153cb] = 399, - [BNXT_ULP_CLASS_HID_14709] = 400, - [BNXT_ULP_CLASS_HID_12dc5] = 401, - [BNXT_ULP_CLASS_HID_1212b] = 402, - [BNXT_ULP_CLASS_HID_171c9] = 403, - [BNXT_ULP_CLASS_HID_1650f] = 404, - [BNXT_ULP_CLASS_HID_10201] = 405, - [BNXT_ULP_CLASS_HID_116c1] = 406, - [BNXT_ULP_CLASS_HID_14605] = 407, - [BNXT_ULP_CLASS_HID_15a05] = 408, - [BNXT_ULP_CLASS_HID_12007] = 409, - [BNXT_ULP_CLASS_HID_13407] = 410, - [BNXT_ULP_CLASS_HID_1640b] = 411, - [BNXT_ULP_CLASS_HID_1780b] = 412, - [BNXT_ULP_CLASS_HID_404b0] = 413, - [BNXT_ULP_CLASS_HID_4148c] = 414, - [BNXT_ULP_CLASS_HID_514c0] = 415, - [BNXT_ULP_CLASS_HID_50bba] = 416, - [BNXT_ULP_CLASS_HID_48c88] = 417, - [BNXT_ULP_CLASS_HID_48362] = 418, - [BNXT_ULP_CLASS_HID_583b6] = 419, - [BNXT_ULP_CLASS_HID_593f2] = 420, - [BNXT_ULP_CLASS_HID_41f54] = 421, - [BNXT_ULP_CLASS_HID_40fce] = 422, - [BNXT_ULP_CLASS_HID_50e02] = 423, - [BNXT_ULP_CLASS_HID_51e5e] = 424, - [BNXT_ULP_CLASS_HID_487ca] = 425, - [BNXT_ULP_CLASS_HID_49606] = 426, - [BNXT_ULP_CLASS_HID_5965a] = 427, - [BNXT_ULP_CLASS_HID_58514] = 428, - [BNXT_ULP_CLASS_HID_412c2] = 429, - [BNXT_ULP_CLASS_HID_401ac] = 430, - [BNXT_ULP_CLASS_HID_501e0] = 431, - [BNXT_ULP_CLASS_HID_511cc] = 432, - [BNXT_ULP_CLASS_HID_4990a] = 433, - [BNXT_ULP_CLASS_HID_489e4] = 434, - [BNXT_ULP_CLASS_HID_589c8] = 435, - [BNXT_ULP_CLASS_HID_59804] = 436, - [BNXT_ULP_CLASS_HID_40404] = 437, - [BNXT_ULP_CLASS_HID_41440] = 438, - [BNXT_ULP_CLASS_HID_51484] = 439, - [BNXT_ULP_CLASS_HID_50b0e] = 440, - [BNXT_ULP_CLASS_HID_48c4c] = 441, - [BNXT_ULP_CLASS_HID_48306] = 442, - [BNXT_ULP_CLASS_HID_5830a] = 443, - [BNXT_ULP_CLASS_HID_59346] = 444, - [BNXT_ULP_CLASS_HID_102cc] = 445, - [BNXT_ULP_CLASS_HID_116ec] = 446, - [BNXT_ULP_CLASS_HID_146d0] = 447, - [BNXT_ULP_CLASS_HID_15af0] = 448, - [BNXT_ULP_CLASS_HID_120c2] = 449, - [BNXT_ULP_CLASS_HID_134e2] = 450, - [BNXT_ULP_CLASS_HID_16b26] = 451, - [BNXT_ULP_CLASS_HID_178c6] = 452, - [BNXT_ULP_CLASS_HID_115c6] = 453, - [BNXT_ULP_CLASS_HID_10804] = 454, - [BNXT_ULP_CLASS_HID_15822] = 455, - [BNXT_ULP_CLASS_HID_14c60] = 456, - [BNXT_ULP_CLASS_HID_13bd4] = 457, - [BNXT_ULP_CLASS_HID_12e12] = 458, - [BNXT_ULP_CLASS_HID_17e30] = 459, - [BNXT_ULP_CLASS_HID_17276] = 460, - [BNXT_ULP_CLASS_HID_11f1a] = 461, - [BNXT_ULP_CLASS_HID_11358] = 462, - [BNXT_ULP_CLASS_HID_14398] = 463, - [BNXT_ULP_CLASS_HID_157b8] = 464, - [BNXT_ULP_CLASS_HID_13d68] = 465, - [BNXT_ULP_CLASS_HID_131aa] = 466, - [BNXT_ULP_CLASS_HID_16192] = 467, - [BNXT_ULP_CLASS_HID_175b2] = 468, - [BNXT_ULP_CLASS_HID_112b2] = 469, - [BNXT_ULP_CLASS_HID_106f0] = 470, - [BNXT_ULP_CLASS_HID_15692] = 471, - [BNXT_ULP_CLASS_HID_14ad0] = 472, - [BNXT_ULP_CLASS_HID_13080] = 473, - [BNXT_ULP_CLASS_HID_124c2] = 474, - [BNXT_ULP_CLASS_HID_174e0] = 475, - [BNXT_ULP_CLASS_HID_16f22] = 476, - [BNXT_ULP_CLASS_HID_4025b] = 477, - [BNXT_ULP_CLASS_HID_41267] = 478, - [BNXT_ULP_CLASS_HID_5122b] = 479, - [BNXT_ULP_CLASS_HID_50d51] = 480, - [BNXT_ULP_CLASS_HID_48a63] = 481, - [BNXT_ULP_CLASS_HID_48589] = 482, - [BNXT_ULP_CLASS_HID_5855d] = 483, - [BNXT_ULP_CLASS_HID_59519] = 484, - [BNXT_ULP_CLASS_HID_41e17] = 485, - [BNXT_ULP_CLASS_HID_4093d] = 486, - [BNXT_ULP_CLASS_HID_50941] = 487, - [BNXT_ULP_CLASS_HID_5190d] = 488, - [BNXT_ULP_CLASS_HID_48139] = 489, - [BNXT_ULP_CLASS_HID_49145] = 490, - [BNXT_ULP_CLASS_HID_59109] = 491, - [BNXT_ULP_CLASS_HID_58037] = 492, - [BNXT_ULP_CLASS_HID_4143d] = 493, - [BNXT_ULP_CLASS_HID_4079b] = 494, - [BNXT_ULP_CLASS_HID_507af] = 495, - [BNXT_ULP_CLASS_HID_5172b] = 496, - [BNXT_ULP_CLASS_HID_49c05] = 497, - [BNXT_ULP_CLASS_HID_48fa3] = 498, - [BNXT_ULP_CLASS_HID_58f37] = 499, - [BNXT_ULP_CLASS_HID_59f33] = 500, - [BNXT_ULP_CLASS_HID_4030b] = 501, - [BNXT_ULP_CLASS_HID_41317] = 502, - [BNXT_ULP_CLASS_HID_5131b] = 503, - [BNXT_ULP_CLASS_HID_50201] = 504, - [BNXT_ULP_CLASS_HID_48b13] = 505, - [BNXT_ULP_CLASS_HID_49b1f] = 506, - [BNXT_ULP_CLASS_HID_59b23] = 507, - [BNXT_ULP_CLASS_HID_58a09] = 508, - [BNXT_ULP_CLASS_HID_419bf] = 509, - [BNXT_ULP_CLASS_HID_40925] = 510, - [BNXT_ULP_CLASS_HID_508e9] = 511, - [BNXT_ULP_CLASS_HID_518b5] = 512, - [BNXT_ULP_CLASS_HID_48121] = 513, - [BNXT_ULP_CLASS_HID_490ed] = 514, - [BNXT_ULP_CLASS_HID_590b1] = 515, - [BNXT_ULP_CLASS_HID_583ff] = 516, - [BNXT_ULP_CLASS_HID_41475] = 517, - [BNXT_ULP_CLASS_HID_40473] = 518, - [BNXT_ULP_CLASS_HID_50427] = 519, - [BNXT_ULP_CLASS_HID_51763] = 520, - [BNXT_ULP_CLASS_HID_49c3d] = 521, - [BNXT_ULP_CLASS_HID_48c3b] = 522, - [BNXT_ULP_CLASS_HID_58f6f] = 523, - [BNXT_ULP_CLASS_HID_59f2b] = 524, - [BNXT_ULP_CLASS_HID_40333] = 525, - [BNXT_ULP_CLASS_HID_412bf] = 526, - [BNXT_ULP_CLASS_HID_512a3] = 527, - [BNXT_ULP_CLASS_HID_50229] = 528, - [BNXT_ULP_CLASS_HID_48abb] = 529, - [BNXT_ULP_CLASS_HID_49aa7] = 530, - [BNXT_ULP_CLASS_HID_59a2b] = 531, - [BNXT_ULP_CLASS_HID_595b1] = 532, - [BNXT_ULP_CLASS_HID_41e2f] = 533, - [BNXT_ULP_CLASS_HID_40e35] = 534, - [BNXT_ULP_CLASS_HID_50939] = 535, - [BNXT_ULP_CLASS_HID_51925] = 536, - [BNXT_ULP_CLASS_HID_48631] = 537, - [BNXT_ULP_CLASS_HID_4913d] = 538, - [BNXT_ULP_CLASS_HID_59121] = 539, - [BNXT_ULP_CLASS_HID_5812f] = 540, - [BNXT_ULP_CLASS_HID_41429] = 541, - [BNXT_ULP_CLASS_HID_40747] = 542, - [BNXT_ULP_CLASS_HID_5070b] = 543, - [BNXT_ULP_CLASS_HID_51727] = 544, - [BNXT_ULP_CLASS_HID_49fe1] = 545, - [BNXT_ULP_CLASS_HID_48f0f] = 546, - [BNXT_ULP_CLASS_HID_58f23] = 547, - [BNXT_ULP_CLASS_HID_59eef] = 548, - [BNXT_ULP_CLASS_HID_40347] = 549, - [BNXT_ULP_CLASS_HID_41303] = 550, - [BNXT_ULP_CLASS_HID_51247] = 551, - [BNXT_ULP_CLASS_HID_5026d] = 552, - [BNXT_ULP_CLASS_HID_48b0f] = 553, - [BNXT_ULP_CLASS_HID_49a4b] = 554, - [BNXT_ULP_CLASS_HID_59a0f] = 555, - [BNXT_ULP_CLASS_HID_58a05] = 556, - [BNXT_ULP_CLASS_HID_41983] = 557, - [BNXT_ULP_CLASS_HID_40929] = 558, - [BNXT_ULP_CLASS_HID_5092d] = 559, - [BNXT_ULP_CLASS_HID_518a9] = 560, - [BNXT_ULP_CLASS_HID_48125] = 561, - [BNXT_ULP_CLASS_HID_49121] = 562, - [BNXT_ULP_CLASS_HID_59085] = 563, - [BNXT_ULP_CLASS_HID_58023] = 564, - [BNXT_ULP_CLASS_HID_41509] = 565, - [BNXT_ULP_CLASS_HID_40407] = 566, - [BNXT_ULP_CLASS_HID_5040b] = 567, - [BNXT_ULP_CLASS_HID_51407] = 568, - [BNXT_ULP_CLASS_HID_49d21] = 569, - [BNXT_ULP_CLASS_HID_48c0f] = 570, - [BNXT_ULP_CLASS_HID_58c03] = 571, - [BNXT_ULP_CLASS_HID_59f0f] = 572, - [BNXT_ULP_CLASS_HID_402ef] = 573, - [BNXT_ULP_CLASS_HID_412ab] = 574, - [BNXT_ULP_CLASS_HID_5126f] = 575, - [BNXT_ULP_CLASS_HID_50de5] = 576, - [BNXT_ULP_CLASS_HID_48aa7] = 577, - [BNXT_ULP_CLASS_HID_485ed] = 578, - [BNXT_ULP_CLASS_HID_585e1] = 579, - [BNXT_ULP_CLASS_HID_595ad] = 580, - [BNXT_ULP_CLASS_HID_41e6b] = 581, - [BNXT_ULP_CLASS_HID_40961] = 582, - [BNXT_ULP_CLASS_HID_50925] = 583, - [BNXT_ULP_CLASS_HID_51961] = 584, - [BNXT_ULP_CLASS_HID_4816d] = 585, - [BNXT_ULP_CLASS_HID_49129] = 586, - [BNXT_ULP_CLASS_HID_5916d] = 587, - [BNXT_ULP_CLASS_HID_5806b] = 588, - [BNXT_ULP_CLASS_HID_414a1] = 589, - [BNXT_ULP_CLASS_HID_4042f] = 590, - [BNXT_ULP_CLASS_HID_507a3] = 591, - [BNXT_ULP_CLASS_HID_517af] = 592, - [BNXT_ULP_CLASS_HID_49c29] = 593, - [BNXT_ULP_CLASS_HID_48fa7] = 594, - [BNXT_ULP_CLASS_HID_58fab] = 595, - [BNXT_ULP_CLASS_HID_59f27] = 596, - [BNXT_ULP_CLASS_HID_4032f] = 597, - [BNXT_ULP_CLASS_HID_4132b] = 598, - [BNXT_ULP_CLASS_HID_5132f] = 599, - [BNXT_ULP_CLASS_HID_50225] = 600, - [BNXT_ULP_CLASS_HID_48b27] = 601, - [BNXT_ULP_CLASS_HID_49b23] = 602, - [BNXT_ULP_CLASS_HID_59b27] = 603, - [BNXT_ULP_CLASS_HID_58a2d] = 604, - [BNXT_ULP_CLASS_HID_10437] = 605, - [BNXT_ULP_CLASS_HID_11017] = 606, - [BNXT_ULP_CLASS_HID_1402b] = 607, - [BNXT_ULP_CLASS_HID_15c0b] = 608, - [BNXT_ULP_CLASS_HID_12639] = 609, - [BNXT_ULP_CLASS_HID_13219] = 610, - [BNXT_ULP_CLASS_HID_16ddd] = 611, - [BNXT_ULP_CLASS_HID_17e3d] = 612, - [BNXT_ULP_CLASS_HID_11333] = 613, - [BNXT_ULP_CLASS_HID_10ef5] = 614, - [BNXT_ULP_CLASS_HID_15f37] = 615, - [BNXT_ULP_CLASS_HID_14ae9] = 616, - [BNXT_ULP_CLASS_HID_13d25] = 617, - [BNXT_ULP_CLASS_HID_128e7] = 618, - [BNXT_ULP_CLASS_HID_17939] = 619, - [BNXT_ULP_CLASS_HID_174fb] = 620, - [BNXT_ULP_CLASS_HID_10985] = 621, - [BNXT_ULP_CLASS_HID_10547] = 622, - [BNXT_ULP_CLASS_HID_155a9] = 623, - [BNXT_ULP_CLASS_HID_1416b] = 624, - [BNXT_ULP_CLASS_HID_12ba7] = 625, - [BNXT_ULP_CLASS_HID_12749] = 626, - [BNXT_ULP_CLASS_HID_177ab] = 627, - [BNXT_ULP_CLASS_HID_1636d] = 628, - [BNXT_ULP_CLASS_HID_10463] = 629, - [BNXT_ULP_CLASS_HID_110a3] = 630, - [BNXT_ULP_CLASS_HID_14067] = 631, - [BNXT_ULP_CLASS_HID_15c67] = 632, - [BNXT_ULP_CLASS_HID_12665] = 633, - [BNXT_ULP_CLASS_HID_13265] = 634, - [BNXT_ULP_CLASS_HID_16269] = 635, - [BNXT_ULP_CLASS_HID_17e69] = 636, - [BNXT_ULP_CLASS_HID_1133d] = 637, - [BNXT_ULP_CLASS_HID_10eff] = 638, - [BNXT_ULP_CLASS_HID_15ed9] = 639, - [BNXT_ULP_CLASS_HID_14a9b] = 640, - [BNXT_ULP_CLASS_HID_13d2f] = 641, - [BNXT_ULP_CLASS_HID_128e9] = 642, - [BNXT_ULP_CLASS_HID_178cb] = 643, - [BNXT_ULP_CLASS_HID_1748d] = 644, - [BNXT_ULP_CLASS_HID_109fb] = 645, - [BNXT_ULP_CLASS_HID_105bd] = 646, - [BNXT_ULP_CLASS_HID_155bf] = 647, - [BNXT_ULP_CLASS_HID_14179] = 648, - [BNXT_ULP_CLASS_HID_12bed] = 649, - [BNXT_ULP_CLASS_HID_127af] = 650, - [BNXT_ULP_CLASS_HID_177a9] = 651, - [BNXT_ULP_CLASS_HID_1636b] = 652, - [BNXT_ULP_CLASS_HID_1046d] = 653, - [BNXT_ULP_CLASS_HID_1104d] = 654, - [BNXT_ULP_CLASS_HID_14009] = 655, - [BNXT_ULP_CLASS_HID_15c69] = 656, - [BNXT_ULP_CLASS_HID_1260f] = 657, - [BNXT_ULP_CLASS_HID_1326f] = 658, - [BNXT_ULP_CLASS_HID_1622b] = 659, - [BNXT_ULP_CLASS_HID_17e0b] = 660, - [BNXT_ULP_CLASS_HID_11369] = 661, - [BNXT_ULP_CLASS_HID_10f2b] = 662, - [BNXT_ULP_CLASS_HID_15f6d] = 663, - [BNXT_ULP_CLASS_HID_14b2f] = 664, - [BNXT_ULP_CLASS_HID_13d6b] = 665, - [BNXT_ULP_CLASS_HID_1292d] = 666, - [BNXT_ULP_CLASS_HID_1792f] = 667, - [BNXT_ULP_CLASS_HID_174e9] = 668, - [BNXT_ULP_CLASS_HID_119e1] = 669, - [BNXT_ULP_CLASS_HID_115a3] = 670, - [BNXT_ULP_CLASS_HID_14563] = 671, - [BNXT_ULP_CLASS_HID_15143] = 672, - [BNXT_ULP_CLASS_HID_13b93] = 673, - [BNXT_ULP_CLASS_HID_13751] = 674, - [BNXT_ULP_CLASS_HID_16769] = 675, - [BNXT_ULP_CLASS_HID_17349] = 676, - [BNXT_ULP_CLASS_HID_114ab] = 677, - [BNXT_ULP_CLASS_HID_10061] = 678, - [BNXT_ULP_CLASS_HID_15063] = 679, - [BNXT_ULP_CLASS_HID_14c21] = 680, - [BNXT_ULP_CLASS_HID_13671] = 681, - [BNXT_ULP_CLASS_HID_12233] = 682, - [BNXT_ULP_CLASS_HID_17271] = 683, - [BNXT_ULP_CLASS_HID_16e33] = 684, - [BNXT_ULP_CLASS_HID_102c1] = 685, - [BNXT_ULP_CLASS_HID_11f21] = 686, - [BNXT_ULP_CLASS_HID_14ee1] = 687, - [BNXT_ULP_CLASS_HID_15ac1] = 688, - [BNXT_ULP_CLASS_HID_12cc3] = 689, - [BNXT_ULP_CLASS_HID_13923] = 690, - [BNXT_ULP_CLASS_HID_168e3] = 691, - [BNXT_ULP_CLASS_HID_164a9] = 692, - [BNXT_ULP_CLASS_HID_11e29] = 693, - [BNXT_ULP_CLASS_HID_115eb] = 694, - [BNXT_ULP_CLASS_HID_145a3] = 695, - [BNXT_ULP_CLASS_HID_151a3] = 696, - [BNXT_ULP_CLASS_HID_1382b] = 697, - [BNXT_ULP_CLASS_HID_137e1] = 698, - [BNXT_ULP_CLASS_HID_167a1] = 699, - [BNXT_ULP_CLASS_HID_173a1] = 700, - [BNXT_ULP_CLASS_HID_11449] = 701, - [BNXT_ULP_CLASS_HID_1000b] = 702, - [BNXT_ULP_CLASS_HID_15069] = 703, - [BNXT_ULP_CLASS_HID_14c2b] = 704, - [BNXT_ULP_CLASS_HID_1367b] = 705, - [BNXT_ULP_CLASS_HID_12239] = 706, - [BNXT_ULP_CLASS_HID_1721b] = 707, - [BNXT_ULP_CLASS_HID_169d9] = 708, - [BNXT_ULP_CLASS_HID_1033b] = 709, - [BNXT_ULP_CLASS_HID_11f3b] = 710, - [BNXT_ULP_CLASS_HID_14f2b] = 711, - [BNXT_ULP_CLASS_HID_15b2b] = 712, - [BNXT_ULP_CLASS_HID_12d39] = 713, - [BNXT_ULP_CLASS_HID_13939] = 714, - [BNXT_ULP_CLASS_HID_168f9] = 715, - [BNXT_ULP_CLASS_HID_164bb] = 716, - [BNXT_ULP_CLASS_HID_119cb] = 717, - [BNXT_ULP_CLASS_HID_11589] = 718, - [BNXT_ULP_CLASS_HID_14549] = 719, - [BNXT_ULP_CLASS_HID_151a9] = 720, - [BNXT_ULP_CLASS_HID_13bc9] = 721, - [BNXT_ULP_CLASS_HID_1378b] = 722, - [BNXT_ULP_CLASS_HID_1674b] = 723, - [BNXT_ULP_CLASS_HID_173ab] = 724, - [BNXT_ULP_CLASS_HID_114a9] = 725, - [BNXT_ULP_CLASS_HID_1006b] = 726, - [BNXT_ULP_CLASS_HID_150a9] = 727, - [BNXT_ULP_CLASS_HID_14c6b] = 728, - [BNXT_ULP_CLASS_HID_136ab] = 729, - [BNXT_ULP_CLASS_HID_12269] = 730, - [BNXT_ULP_CLASS_HID_172ab] = 731, - [BNXT_ULP_CLASS_HID_16e69] = 732, - [BNXT_ULP_CLASS_HID_402d2] = 733, - [BNXT_ULP_CLASS_HID_412ee] = 734, - [BNXT_ULP_CLASS_HID_512a2] = 735, - [BNXT_ULP_CLASS_HID_50dd8] = 736, - [BNXT_ULP_CLASS_HID_48aea] = 737, - [BNXT_ULP_CLASS_HID_48500] = 738, - [BNXT_ULP_CLASS_HID_585d4] = 739, - [BNXT_ULP_CLASS_HID_59590] = 740, - [BNXT_ULP_CLASS_HID_41936] = 741, - [BNXT_ULP_CLASS_HID_409ac] = 742, - [BNXT_ULP_CLASS_HID_50860] = 743, - [BNXT_ULP_CLASS_HID_5183c] = 744, - [BNXT_ULP_CLASS_HID_481a8] = 745, - [BNXT_ULP_CLASS_HID_49064] = 746, - [BNXT_ULP_CLASS_HID_59038] = 747, - [BNXT_ULP_CLASS_HID_58376] = 748, - [BNXT_ULP_CLASS_HID_414a0] = 749, - [BNXT_ULP_CLASS_HID_407ce] = 750, - [BNXT_ULP_CLASS_HID_50782] = 751, - [BNXT_ULP_CLASS_HID_517ae] = 752, - [BNXT_ULP_CLASS_HID_49f68] = 753, - [BNXT_ULP_CLASS_HID_48f86] = 754, - [BNXT_ULP_CLASS_HID_58faa] = 755, - [BNXT_ULP_CLASS_HID_59e66] = 756, - [BNXT_ULP_CLASS_HID_40266] = 757, - [BNXT_ULP_CLASS_HID_41222] = 758, - [BNXT_ULP_CLASS_HID_512e6] = 759, - [BNXT_ULP_CLASS_HID_50d6c] = 760, - [BNXT_ULP_CLASS_HID_48a2e] = 761, - [BNXT_ULP_CLASS_HID_48564] = 762, - [BNXT_ULP_CLASS_HID_58568] = 763, - [BNXT_ULP_CLASS_HID_59524] = 764, - [BNXT_ULP_CLASS_HID_419d8] = 765, - [BNXT_ULP_CLASS_HID_4087e] = 766, - [BNXT_ULP_CLASS_HID_5080a] = 767, - [BNXT_ULP_CLASS_HID_518ce] = 768, - [BNXT_ULP_CLASS_HID_4807a] = 769, - [BNXT_ULP_CLASS_HID_4900e] = 770, - [BNXT_ULP_CLASS_HID_590ca] = 771, - [BNXT_ULP_CLASS_HID_58378] = 772, - [BNXT_ULP_CLASS_HID_414be] = 773, - [BNXT_ULP_CLASS_HID_4073c] = 774, - [BNXT_ULP_CLASS_HID_507e8] = 775, - [BNXT_ULP_CLASS_HID_517ac] = 776, - [BNXT_ULP_CLASS_HID_49f7e] = 777, - [BNXT_ULP_CLASS_HID_48fec] = 778, - [BNXT_ULP_CLASS_HID_58fa8] = 779, - [BNXT_ULP_CLASS_HID_59e7c] = 780, - [BNXT_ULP_CLASS_HID_40208] = 781, - [BNXT_ULP_CLASS_HID_412cc] = 782, - [BNXT_ULP_CLASS_HID_51288] = 783, - [BNXT_ULP_CLASS_HID_50d2e] = 784, - [BNXT_ULP_CLASS_HID_48ac8] = 785, - [BNXT_ULP_CLASS_HID_4856e] = 786, - [BNXT_ULP_CLASS_HID_5852a] = 787, - [BNXT_ULP_CLASS_HID_595ce] = 788, - [BNXT_ULP_CLASS_HID_4196c] = 789, - [BNXT_ULP_CLASS_HID_409aa] = 790, - [BNXT_ULP_CLASS_HID_5086e] = 791, - [BNXT_ULP_CLASS_HID_5182a] = 792, - [BNXT_ULP_CLASS_HID_481ae] = 793, - [BNXT_ULP_CLASS_HID_4906a] = 794, - [BNXT_ULP_CLASS_HID_5902e] = 795, - [BNXT_ULP_CLASS_HID_580ac] = 796, - [BNXT_ULP_CLASS_HID_40766] = 797, - [BNXT_ULP_CLASS_HID_41726] = 798, - [BNXT_ULP_CLASS_HID_517f6] = 799, - [BNXT_ULP_CLASS_HID_5066c] = 800, - [BNXT_ULP_CLASS_HID_48f3e] = 801, - [BNXT_ULP_CLASS_HID_49ffe] = 802, - [BNXT_ULP_CLASS_HID_59f8e] = 803, - [BNXT_ULP_CLASS_HID_58e24] = 804, - [BNXT_ULP_CLASS_HID_4126e] = 805, - [BNXT_ULP_CLASS_HID_402e4] = 806, - [BNXT_ULP_CLASS_HID_502b4] = 807, - [BNXT_ULP_CLASS_HID_51d74] = 808, - [BNXT_ULP_CLASS_HID_49a26] = 809, - [BNXT_ULP_CLASS_HID_48abc] = 810, - [BNXT_ULP_CLASS_HID_5956c] = 811, - [BNXT_ULP_CLASS_HID_585ee] = 812, - [BNXT_ULP_CLASS_HID_409e4] = 813, - [BNXT_ULP_CLASS_HID_419a4] = 814, - [BNXT_ULP_CLASS_HID_51844] = 815, - [BNXT_ULP_CLASS_HID_508e6] = 816, - [BNXT_ULP_CLASS_HID_4918c] = 817, - [BNXT_ULP_CLASS_HID_4802e] = 818, - [BNXT_ULP_CLASS_HID_580ee] = 819, - [BNXT_ULP_CLASS_HID_590ae] = 820, - [BNXT_ULP_CLASS_HID_404ae] = 821, - [BNXT_ULP_CLASS_HID_41766] = 822, - [BNXT_ULP_CLASS_HID_5172e] = 823, - [BNXT_ULP_CLASS_HID_507a4] = 824, - [BNXT_ULP_CLASS_HID_48f66] = 825, - [BNXT_ULP_CLASS_HID_49f2e] = 826, - [BNXT_ULP_CLASS_HID_59fe6] = 827, - [BNXT_ULP_CLASS_HID_58e6c] = 828, - [BNXT_ULP_CLASS_HID_4126c] = 829, - [BNXT_ULP_CLASS_HID_4028e] = 830, - [BNXT_ULP_CLASS_HID_50d5e] = 831, - [BNXT_ULP_CLASS_HID_51d1e] = 832, - [BNXT_ULP_CLASS_HID_49a2c] = 833, - [BNXT_ULP_CLASS_HID_4954e] = 834, - [BNXT_ULP_CLASS_HID_5951e] = 835, - [BNXT_ULP_CLASS_HID_5858c] = 836, - [BNXT_ULP_CLASS_HID_409fe] = 837, - [BNXT_ULP_CLASS_HID_419ee] = 838, - [BNXT_ULP_CLASS_HID_519ae] = 839, - [BNXT_ULP_CLASS_HID_508fc] = 840, - [BNXT_ULP_CLASS_HID_491ee] = 841, - [BNXT_ULP_CLASS_HID_4802c] = 842, - [BNXT_ULP_CLASS_HID_580fc] = 843, - [BNXT_ULP_CLASS_HID_590bc] = 844, - [BNXT_ULP_CLASS_HID_4074c] = 845, - [BNXT_ULP_CLASS_HID_4170c] = 846, - [BNXT_ULP_CLASS_HID_5172c] = 847, - [BNXT_ULP_CLASS_HID_5064e] = 848, - [BNXT_ULP_CLASS_HID_48f0c] = 849, - [BNXT_ULP_CLASS_HID_49fcc] = 850, - [BNXT_ULP_CLASS_HID_59fec] = 851, - [BNXT_ULP_CLASS_HID_58e0e] = 852, - [BNXT_ULP_CLASS_HID_413ac] = 853, - [BNXT_ULP_CLASS_HID_402ee] = 854, - [BNXT_ULP_CLASS_HID_502ae] = 855, - [BNXT_ULP_CLASS_HID_512ae] = 856, - [BNXT_ULP_CLASS_HID_49a6c] = 857, - [BNXT_ULP_CLASS_HID_48aae] = 858, - [BNXT_ULP_CLASS_HID_58aae] = 859, - [BNXT_ULP_CLASS_HID_585ec] = 860, - [BNXT_ULP_CLASS_HID_104ae] = 861, - [BNXT_ULP_CLASS_HID_1108e] = 862, - [BNXT_ULP_CLASS_HID_140b2] = 863, - [BNXT_ULP_CLASS_HID_15c92] = 864, - [BNXT_ULP_CLASS_HID_126a0] = 865, - [BNXT_ULP_CLASS_HID_13280] = 866, - [BNXT_ULP_CLASS_HID_16d44] = 867, - [BNXT_ULP_CLASS_HID_17ea4] = 868, - [BNXT_ULP_CLASS_HID_113a4] = 869, - [BNXT_ULP_CLASS_HID_10e66] = 870, - [BNXT_ULP_CLASS_HID_15e40] = 871, - [BNXT_ULP_CLASS_HID_14a02] = 872, - [BNXT_ULP_CLASS_HID_13db6] = 873, - [BNXT_ULP_CLASS_HID_12870] = 874, - [BNXT_ULP_CLASS_HID_17852] = 875, - [BNXT_ULP_CLASS_HID_17414] = 876, - [BNXT_ULP_CLASS_HID_11978] = 877, - [BNXT_ULP_CLASS_HID_1153a] = 878, - [BNXT_ULP_CLASS_HID_145fa] = 879, - [BNXT_ULP_CLASS_HID_151da] = 880, - [BNXT_ULP_CLASS_HID_13b0a] = 881, - [BNXT_ULP_CLASS_HID_137c8] = 882, - [BNXT_ULP_CLASS_HID_167f0] = 883, - [BNXT_ULP_CLASS_HID_173d0] = 884, - [BNXT_ULP_CLASS_HID_114d0] = 885, - [BNXT_ULP_CLASS_HID_10092] = 886, - [BNXT_ULP_CLASS_HID_150f0] = 887, - [BNXT_ULP_CLASS_HID_14cb2] = 888, - [BNXT_ULP_CLASS_HID_136e2] = 889, - [BNXT_ULP_CLASS_HID_122a0] = 890, - [BNXT_ULP_CLASS_HID_17282] = 891, - [BNXT_ULP_CLASS_HID_16940] = 892, - [BNXT_ULP_CLASS_HID_11b90] = 893, - [BNXT_ULP_CLASS_HID_11654] = 894, - [BNXT_ULP_CLASS_HID_14618] = 895, - [BNXT_ULP_CLASS_HID_15278] = 896, - [BNXT_ULP_CLASS_HID_12404] = 897, - [BNXT_ULP_CLASS_HID_13064] = 898, - [BNXT_ULP_CLASS_HID_16028] = 899, - [BNXT_ULP_CLASS_HID_17c08] = 900, - [BNXT_ULP_CLASS_HID_11100] = 901, - [BNXT_ULP_CLASS_HID_10dc4] = 902, - [BNXT_ULP_CLASS_HID_15d24] = 903, - [BNXT_ULP_CLASS_HID_149d0] = 904, - [BNXT_ULP_CLASS_HID_13314] = 905, - [BNXT_ULP_CLASS_HID_12fd4] = 906, - [BNXT_ULP_CLASS_HID_17f20] = 907, - [BNXT_ULP_CLASS_HID_16be0] = 908, - [BNXT_ULP_CLASS_HID_11cd8] = 909, - [BNXT_ULP_CLASS_HID_10880] = 910, - [BNXT_ULP_CLASS_HID_158e0] = 911, - [BNXT_ULP_CLASS_HID_154a0] = 912, - [BNXT_ULP_CLASS_HID_13ed0] = 913, - [BNXT_ULP_CLASS_HID_12a90] = 914, - [BNXT_ULP_CLASS_HID_16550] = 915, - [BNXT_ULP_CLASS_HID_176b0] = 916, - [BNXT_ULP_CLASS_HID_10bb0] = 917, - [BNXT_ULP_CLASS_HID_10670] = 918, - [BNXT_ULP_CLASS_HID_15650] = 919, - [BNXT_ULP_CLASS_HID_14210] = 920, - [BNXT_ULP_CLASS_HID_13440] = 921, - [BNXT_ULP_CLASS_HID_12000] = 922, - [BNXT_ULP_CLASS_HID_17060] = 923, - [BNXT_ULP_CLASS_HID_16c20] = 924, - [BNXT_ULP_CLASS_HID_11511] = 925, - [BNXT_ULP_CLASS_HID_101d3] = 926, - [BNXT_ULP_CLASS_HID_15135] = 927, - [BNXT_ULP_CLASS_HID_14df7] = 928, - [BNXT_ULP_CLASS_HID_13723] = 929, - [BNXT_ULP_CLASS_HID_123e5] = 930, - [BNXT_ULP_CLASS_HID_173c7] = 931, - [BNXT_ULP_CLASS_HID_16f89] = 932, - [BNXT_ULP_CLASS_HID_10081] = 933, - [BNXT_ULP_CLASS_HID_11ce1] = 934, - [BNXT_ULP_CLASS_HID_14ca5] = 935, - [BNXT_ULP_CLASS_HID_15885] = 936, - [BNXT_ULP_CLASS_HID_12293] = 937, - [BNXT_ULP_CLASS_HID_13ef3] = 938, - [BNXT_ULP_CLASS_HID_16eb7] = 939, - [BNXT_ULP_CLASS_HID_16561] = 940, - [BNXT_ULP_CLASS_HID_10e59] = 941, - [BNXT_ULP_CLASS_HID_11bb9] = 942, - [BNXT_ULP_CLASS_HID_14a61] = 943, - [BNXT_ULP_CLASS_HID_14623] = 944, - [BNXT_ULP_CLASS_HID_1286b] = 945, - [BNXT_ULP_CLASS_HID_12411] = 946, - [BNXT_ULP_CLASS_HID_17473] = 947, - [BNXT_ULP_CLASS_HID_16031] = 948, - [BNXT_ULP_CLASS_HID_10531] = 949, - [BNXT_ULP_CLASS_HID_11111] = 950, - [BNXT_ULP_CLASS_HID_141d1] = 951, - [BNXT_ULP_CLASS_HID_15d31] = 952, - [BNXT_ULP_CLASS_HID_127c3] = 953, - [BNXT_ULP_CLASS_HID_13323] = 954, - [BNXT_ULP_CLASS_HID_163e3] = 955, - [BNXT_ULP_CLASS_HID_17fc3] = 956, - [BNXT_ULP_CLASS_HID_108f5] = 957, - [BNXT_ULP_CLASS_HID_104b9] = 958, - [BNXT_ULP_CLASS_HID_15499] = 959, - [BNXT_ULP_CLASS_HID_1435d] = 960, - [BNXT_ULP_CLASS_HID_12a89] = 961, - [BNXT_ULP_CLASS_HID_12149] = 962, - [BNXT_ULP_CLASS_HID_176ad] = 963, - [BNXT_ULP_CLASS_HID_16d6d] = 964, - [BNXT_ULP_CLASS_HID_10665] = 965, - [BNXT_ULP_CLASS_HID_11245] = 966, - [BNXT_ULP_CLASS_HID_14271] = 967, - [BNXT_ULP_CLASS_HID_15e51] = 968, - [BNXT_ULP_CLASS_HID_12061] = 969, - [BNXT_ULP_CLASS_HID_13c41] = 970, - [BNXT_ULP_CLASS_HID_16c05] = 971, - [BNXT_ULP_CLASS_HID_17865] = 972, - [BNXT_ULP_CLASS_HID_10d21] = 973, - [BNXT_ULP_CLASS_HID_11901] = 974, - [BNXT_ULP_CLASS_HID_149c1] = 975, - [BNXT_ULP_CLASS_HID_14589] = 976, - [BNXT_ULP_CLASS_HID_12f31] = 977, - [BNXT_ULP_CLASS_HID_13b11] = 978, - [BNXT_ULP_CLASS_HID_16bd9] = 979, - [BNXT_ULP_CLASS_HID_16799] = 980, - [BNXT_ULP_CLASS_HID_11831] = 981, - [BNXT_ULP_CLASS_HID_114f1] = 982, - [BNXT_ULP_CLASS_HID_144b1] = 983, - [BNXT_ULP_CLASS_HID_15091] = 984, - [BNXT_ULP_CLASS_HID_13ac1] = 985, - [BNXT_ULP_CLASS_HID_13681] = 986, - [BNXT_ULP_CLASS_HID_166b1] = 987, - [BNXT_ULP_CLASS_HID_17291] = 988, - [BNXT_ULP_CLASS_HID_4007d] = 989, - [BNXT_ULP_CLASS_HID_41041] = 990, - [BNXT_ULP_CLASS_HID_5100d] = 991, - [BNXT_ULP_CLASS_HID_50f77] = 992, - [BNXT_ULP_CLASS_HID_48845] = 993, - [BNXT_ULP_CLASS_HID_487af] = 994, - [BNXT_ULP_CLASS_HID_5877b] = 995, - [BNXT_ULP_CLASS_HID_5973f] = 996, - [BNXT_ULP_CLASS_HID_41c31] = 997, - [BNXT_ULP_CLASS_HID_40b1b] = 998, - [BNXT_ULP_CLASS_HID_50b67] = 999, - [BNXT_ULP_CLASS_HID_51b2b] = 1000, - [BNXT_ULP_CLASS_HID_4831f] = 1001, - [BNXT_ULP_CLASS_HID_49363] = 1002, - [BNXT_ULP_CLASS_HID_5932f] = 1003, - [BNXT_ULP_CLASS_HID_58211] = 1004, - [BNXT_ULP_CLASS_HID_4161b] = 1005, - [BNXT_ULP_CLASS_HID_405bd] = 1006, - [BNXT_ULP_CLASS_HID_50589] = 1007, - [BNXT_ULP_CLASS_HID_5150d] = 1008, - [BNXT_ULP_CLASS_HID_49e23] = 1009, - [BNXT_ULP_CLASS_HID_48d85] = 1010, - [BNXT_ULP_CLASS_HID_58d11] = 1011, - [BNXT_ULP_CLASS_HID_59d15] = 1012, - [BNXT_ULP_CLASS_HID_4012d] = 1013, - [BNXT_ULP_CLASS_HID_41131] = 1014, - [BNXT_ULP_CLASS_HID_5113d] = 1015, - [BNXT_ULP_CLASS_HID_50027] = 1016, - [BNXT_ULP_CLASS_HID_48935] = 1017, - [BNXT_ULP_CLASS_HID_49939] = 1018, - [BNXT_ULP_CLASS_HID_59905] = 1019, - [BNXT_ULP_CLASS_HID_5882f] = 1020, - [BNXT_ULP_CLASS_HID_41b99] = 1021, - [BNXT_ULP_CLASS_HID_40b03] = 1022, - [BNXT_ULP_CLASS_HID_50acf] = 1023, - [BNXT_ULP_CLASS_HID_51a93] = 1024, - [BNXT_ULP_CLASS_HID_48307] = 1025, - [BNXT_ULP_CLASS_HID_492cb] = 1026, - [BNXT_ULP_CLASS_HID_59297] = 1027, - [BNXT_ULP_CLASS_HID_581d9] = 1028, - [BNXT_ULP_CLASS_HID_41653] = 1029, - [BNXT_ULP_CLASS_HID_40655] = 1030, - [BNXT_ULP_CLASS_HID_50601] = 1031, - [BNXT_ULP_CLASS_HID_51545] = 1032, - [BNXT_ULP_CLASS_HID_49e1b] = 1033, - [BNXT_ULP_CLASS_HID_48e1d] = 1034, - [BNXT_ULP_CLASS_HID_58d49] = 1035, - [BNXT_ULP_CLASS_HID_59d0d] = 1036, - [BNXT_ULP_CLASS_HID_40115] = 1037, - [BNXT_ULP_CLASS_HID_41099] = 1038, - [BNXT_ULP_CLASS_HID_51085] = 1039, - [BNXT_ULP_CLASS_HID_5000f] = 1040, - [BNXT_ULP_CLASS_HID_4889d] = 1041, - [BNXT_ULP_CLASS_HID_49881] = 1042, - [BNXT_ULP_CLASS_HID_5980d] = 1043, - [BNXT_ULP_CLASS_HID_59797] = 1044, - [BNXT_ULP_CLASS_HID_41c09] = 1045, - [BNXT_ULP_CLASS_HID_40c13] = 1046, - [BNXT_ULP_CLASS_HID_50b1f] = 1047, - [BNXT_ULP_CLASS_HID_51b03] = 1048, - [BNXT_ULP_CLASS_HID_48417] = 1049, - [BNXT_ULP_CLASS_HID_4931b] = 1050, - [BNXT_ULP_CLASS_HID_59307] = 1051, - [BNXT_ULP_CLASS_HID_58309] = 1052, - [BNXT_ULP_CLASS_HID_4160f] = 1053, - [BNXT_ULP_CLASS_HID_40561] = 1054, - [BNXT_ULP_CLASS_HID_5052d] = 1055, - [BNXT_ULP_CLASS_HID_51501] = 1056, - [BNXT_ULP_CLASS_HID_49dc7] = 1057, - [BNXT_ULP_CLASS_HID_48d29] = 1058, - [BNXT_ULP_CLASS_HID_58d05] = 1059, - [BNXT_ULP_CLASS_HID_59cc9] = 1060, - [BNXT_ULP_CLASS_HID_40161] = 1061, - [BNXT_ULP_CLASS_HID_41125] = 1062, - [BNXT_ULP_CLASS_HID_51061] = 1063, - [BNXT_ULP_CLASS_HID_5004b] = 1064, - [BNXT_ULP_CLASS_HID_48929] = 1065, - [BNXT_ULP_CLASS_HID_4986d] = 1066, - [BNXT_ULP_CLASS_HID_59829] = 1067, - [BNXT_ULP_CLASS_HID_58823] = 1068, - [BNXT_ULP_CLASS_HID_41ba5] = 1069, - [BNXT_ULP_CLASS_HID_40b0f] = 1070, - [BNXT_ULP_CLASS_HID_50b0b] = 1071, - [BNXT_ULP_CLASS_HID_51a8f] = 1072, - [BNXT_ULP_CLASS_HID_48303] = 1073, - [BNXT_ULP_CLASS_HID_49307] = 1074, - [BNXT_ULP_CLASS_HID_592a3] = 1075, - [BNXT_ULP_CLASS_HID_58205] = 1076, - [BNXT_ULP_CLASS_HID_4172f] = 1077, - [BNXT_ULP_CLASS_HID_40621] = 1078, - [BNXT_ULP_CLASS_HID_5062d] = 1079, - [BNXT_ULP_CLASS_HID_51621] = 1080, - [BNXT_ULP_CLASS_HID_49f07] = 1081, - [BNXT_ULP_CLASS_HID_48e29] = 1082, - [BNXT_ULP_CLASS_HID_58e25] = 1083, - [BNXT_ULP_CLASS_HID_59d29] = 1084, - [BNXT_ULP_CLASS_HID_400c9] = 1085, - [BNXT_ULP_CLASS_HID_4108d] = 1086, - [BNXT_ULP_CLASS_HID_51049] = 1087, - [BNXT_ULP_CLASS_HID_50fc3] = 1088, - [BNXT_ULP_CLASS_HID_48881] = 1089, - [BNXT_ULP_CLASS_HID_487cb] = 1090, - [BNXT_ULP_CLASS_HID_587c7] = 1091, - [BNXT_ULP_CLASS_HID_5978b] = 1092, - [BNXT_ULP_CLASS_HID_41c4d] = 1093, - [BNXT_ULP_CLASS_HID_40b47] = 1094, - [BNXT_ULP_CLASS_HID_50b03] = 1095, - [BNXT_ULP_CLASS_HID_51b47] = 1096, - [BNXT_ULP_CLASS_HID_4834b] = 1097, - [BNXT_ULP_CLASS_HID_4930f] = 1098, - [BNXT_ULP_CLASS_HID_5934b] = 1099, - [BNXT_ULP_CLASS_HID_5824d] = 1100, - [BNXT_ULP_CLASS_HID_41687] = 1101, - [BNXT_ULP_CLASS_HID_40609] = 1102, - [BNXT_ULP_CLASS_HID_50585] = 1103, - [BNXT_ULP_CLASS_HID_51589] = 1104, - [BNXT_ULP_CLASS_HID_49e0f] = 1105, - [BNXT_ULP_CLASS_HID_48d81] = 1106, - [BNXT_ULP_CLASS_HID_58d8d] = 1107, - [BNXT_ULP_CLASS_HID_59d01] = 1108, - [BNXT_ULP_CLASS_HID_40109] = 1109, - [BNXT_ULP_CLASS_HID_4110d] = 1110, - [BNXT_ULP_CLASS_HID_51109] = 1111, - [BNXT_ULP_CLASS_HID_50003] = 1112, - [BNXT_ULP_CLASS_HID_48901] = 1113, - [BNXT_ULP_CLASS_HID_49905] = 1114, - [BNXT_ULP_CLASS_HID_59901] = 1115, - [BNXT_ULP_CLASS_HID_5880b] = 1116, - [BNXT_ULP_CLASS_HID_10619] = 1117, - [BNXT_ULP_CLASS_HID_11239] = 1118, - [BNXT_ULP_CLASS_HID_14205] = 1119, - [BNXT_ULP_CLASS_HID_15e25] = 1120, - [BNXT_ULP_CLASS_HID_12417] = 1121, - [BNXT_ULP_CLASS_HID_13037] = 1122, - [BNXT_ULP_CLASS_HID_16ff3] = 1123, - [BNXT_ULP_CLASS_HID_17c13] = 1124, - [BNXT_ULP_CLASS_HID_1111d] = 1125, - [BNXT_ULP_CLASS_HID_10cdb] = 1126, - [BNXT_ULP_CLASS_HID_15d19] = 1127, - [BNXT_ULP_CLASS_HID_148c7] = 1128, - [BNXT_ULP_CLASS_HID_13f0b] = 1129, - [BNXT_ULP_CLASS_HID_12ac9] = 1130, - [BNXT_ULP_CLASS_HID_17b17] = 1131, - [BNXT_ULP_CLASS_HID_176d5] = 1132, - [BNXT_ULP_CLASS_HID_10bab] = 1133, - [BNXT_ULP_CLASS_HID_10769] = 1134, - [BNXT_ULP_CLASS_HID_15787] = 1135, - [BNXT_ULP_CLASS_HID_14345] = 1136, - [BNXT_ULP_CLASS_HID_12989] = 1137, - [BNXT_ULP_CLASS_HID_12567] = 1138, - [BNXT_ULP_CLASS_HID_17585] = 1139, - [BNXT_ULP_CLASS_HID_16143] = 1140, - [BNXT_ULP_CLASS_HID_1064d] = 1141, - [BNXT_ULP_CLASS_HID_1128d] = 1142, - [BNXT_ULP_CLASS_HID_14249] = 1143, - [BNXT_ULP_CLASS_HID_15e49] = 1144, - [BNXT_ULP_CLASS_HID_1244b] = 1145, - [BNXT_ULP_CLASS_HID_1304b] = 1146, - [BNXT_ULP_CLASS_HID_16047] = 1147, - [BNXT_ULP_CLASS_HID_17c47] = 1148, - [BNXT_ULP_CLASS_HID_11113] = 1149, - [BNXT_ULP_CLASS_HID_10cd1] = 1150, - [BNXT_ULP_CLASS_HID_15cf7] = 1151, - [BNXT_ULP_CLASS_HID_148b5] = 1152, - [BNXT_ULP_CLASS_HID_13f01] = 1153, - [BNXT_ULP_CLASS_HID_12ac7] = 1154, - [BNXT_ULP_CLASS_HID_17ae5] = 1155, - [BNXT_ULP_CLASS_HID_176a3] = 1156, - [BNXT_ULP_CLASS_HID_10bd5] = 1157, - [BNXT_ULP_CLASS_HID_10793] = 1158, - [BNXT_ULP_CLASS_HID_15791] = 1159, - [BNXT_ULP_CLASS_HID_14357] = 1160, - [BNXT_ULP_CLASS_HID_129c3] = 1161, - [BNXT_ULP_CLASS_HID_12581] = 1162, - [BNXT_ULP_CLASS_HID_17587] = 1163, - [BNXT_ULP_CLASS_HID_16145] = 1164, - [BNXT_ULP_CLASS_HID_10643] = 1165, - [BNXT_ULP_CLASS_HID_11263] = 1166, - [BNXT_ULP_CLASS_HID_14227] = 1167, - [BNXT_ULP_CLASS_HID_15e47] = 1168, - [BNXT_ULP_CLASS_HID_12421] = 1169, - [BNXT_ULP_CLASS_HID_13041] = 1170, - [BNXT_ULP_CLASS_HID_16005] = 1171, - [BNXT_ULP_CLASS_HID_17c25] = 1172, - [BNXT_ULP_CLASS_HID_11147] = 1173, - [BNXT_ULP_CLASS_HID_10d05] = 1174, - [BNXT_ULP_CLASS_HID_15d43] = 1175, - [BNXT_ULP_CLASS_HID_14901] = 1176, - [BNXT_ULP_CLASS_HID_13f45] = 1177, - [BNXT_ULP_CLASS_HID_12b03] = 1178, - [BNXT_ULP_CLASS_HID_17b01] = 1179, - [BNXT_ULP_CLASS_HID_176c7] = 1180, - [BNXT_ULP_CLASS_HID_11bcf] = 1181, - [BNXT_ULP_CLASS_HID_1178d] = 1182, - [BNXT_ULP_CLASS_HID_1474d] = 1183, - [BNXT_ULP_CLASS_HID_1536d] = 1184, - [BNXT_ULP_CLASS_HID_139bd] = 1185, - [BNXT_ULP_CLASS_HID_1357f] = 1186, - [BNXT_ULP_CLASS_HID_16547] = 1187, - [BNXT_ULP_CLASS_HID_17167] = 1188, - [BNXT_ULP_CLASS_HID_11685] = 1189, - [BNXT_ULP_CLASS_HID_1024f] = 1190, - [BNXT_ULP_CLASS_HID_1524d] = 1191, - [BNXT_ULP_CLASS_HID_14e0f] = 1192, - [BNXT_ULP_CLASS_HID_1345f] = 1193, - [BNXT_ULP_CLASS_HID_1201d] = 1194, - [BNXT_ULP_CLASS_HID_1705f] = 1195, - [BNXT_ULP_CLASS_HID_16c1d] = 1196, - [BNXT_ULP_CLASS_HID_100ef] = 1197, - [BNXT_ULP_CLASS_HID_11d0f] = 1198, - [BNXT_ULP_CLASS_HID_14ccf] = 1199, - [BNXT_ULP_CLASS_HID_158ef] = 1200, - [BNXT_ULP_CLASS_HID_12eed] = 1201, - [BNXT_ULP_CLASS_HID_13b0d] = 1202, - [BNXT_ULP_CLASS_HID_16acd] = 1203, - [BNXT_ULP_CLASS_HID_16687] = 1204, - [BNXT_ULP_CLASS_HID_11c07] = 1205, - [BNXT_ULP_CLASS_HID_117c5] = 1206, - [BNXT_ULP_CLASS_HID_1478d] = 1207, - [BNXT_ULP_CLASS_HID_1538d] = 1208, - [BNXT_ULP_CLASS_HID_13a05] = 1209, - [BNXT_ULP_CLASS_HID_135cf] = 1210, - [BNXT_ULP_CLASS_HID_1658f] = 1211, - [BNXT_ULP_CLASS_HID_1718f] = 1212, - [BNXT_ULP_CLASS_HID_11667] = 1213, - [BNXT_ULP_CLASS_HID_10225] = 1214, - [BNXT_ULP_CLASS_HID_15247] = 1215, - [BNXT_ULP_CLASS_HID_14e05] = 1216, - [BNXT_ULP_CLASS_HID_13455] = 1217, - [BNXT_ULP_CLASS_HID_12017] = 1218, - [BNXT_ULP_CLASS_HID_17035] = 1219, - [BNXT_ULP_CLASS_HID_16bf7] = 1220, - [BNXT_ULP_CLASS_HID_10115] = 1221, - [BNXT_ULP_CLASS_HID_11d15] = 1222, - [BNXT_ULP_CLASS_HID_14d05] = 1223, - [BNXT_ULP_CLASS_HID_15905] = 1224, - [BNXT_ULP_CLASS_HID_12f17] = 1225, - [BNXT_ULP_CLASS_HID_13b17] = 1226, - [BNXT_ULP_CLASS_HID_16ad7] = 1227, - [BNXT_ULP_CLASS_HID_16695] = 1228, - [BNXT_ULP_CLASS_HID_11be5] = 1229, - [BNXT_ULP_CLASS_HID_117a7] = 1230, - [BNXT_ULP_CLASS_HID_14767] = 1231, - [BNXT_ULP_CLASS_HID_15387] = 1232, - [BNXT_ULP_CLASS_HID_139e7] = 1233, - [BNXT_ULP_CLASS_HID_135a5] = 1234, - [BNXT_ULP_CLASS_HID_16565] = 1235, - [BNXT_ULP_CLASS_HID_17185] = 1236, - [BNXT_ULP_CLASS_HID_11687] = 1237, - [BNXT_ULP_CLASS_HID_10245] = 1238, - [BNXT_ULP_CLASS_HID_15287] = 1239, - [BNXT_ULP_CLASS_HID_14e45] = 1240, - [BNXT_ULP_CLASS_HID_13485] = 1241, - [BNXT_ULP_CLASS_HID_12047] = 1242, - [BNXT_ULP_CLASS_HID_17085] = 1243, - [BNXT_ULP_CLASS_HID_16c47] = 1244, - [BNXT_ULP_CLASS_HID_400f4] = 1245, - [BNXT_ULP_CLASS_HID_410c8] = 1246, - [BNXT_ULP_CLASS_HID_51084] = 1247, - [BNXT_ULP_CLASS_HID_50ffe] = 1248, - [BNXT_ULP_CLASS_HID_488cc] = 1249, - [BNXT_ULP_CLASS_HID_48726] = 1250, - [BNXT_ULP_CLASS_HID_587f2] = 1251, - [BNXT_ULP_CLASS_HID_597b6] = 1252, - [BNXT_ULP_CLASS_HID_41b10] = 1253, - [BNXT_ULP_CLASS_HID_40b8a] = 1254, - [BNXT_ULP_CLASS_HID_50a46] = 1255, - [BNXT_ULP_CLASS_HID_51a1a] = 1256, - [BNXT_ULP_CLASS_HID_4838e] = 1257, - [BNXT_ULP_CLASS_HID_49242] = 1258, - [BNXT_ULP_CLASS_HID_5921e] = 1259, - [BNXT_ULP_CLASS_HID_58150] = 1260, - [BNXT_ULP_CLASS_HID_41686] = 1261, - [BNXT_ULP_CLASS_HID_405e8] = 1262, - [BNXT_ULP_CLASS_HID_505a4] = 1263, - [BNXT_ULP_CLASS_HID_51588] = 1264, - [BNXT_ULP_CLASS_HID_49d4e] = 1265, - [BNXT_ULP_CLASS_HID_48da0] = 1266, - [BNXT_ULP_CLASS_HID_58d8c] = 1267, - [BNXT_ULP_CLASS_HID_59c40] = 1268, - [BNXT_ULP_CLASS_HID_40040] = 1269, - [BNXT_ULP_CLASS_HID_41004] = 1270, - [BNXT_ULP_CLASS_HID_510c0] = 1271, - [BNXT_ULP_CLASS_HID_50f4a] = 1272, - [BNXT_ULP_CLASS_HID_48808] = 1273, - [BNXT_ULP_CLASS_HID_48742] = 1274, - [BNXT_ULP_CLASS_HID_5874e] = 1275, - [BNXT_ULP_CLASS_HID_59702] = 1276, - [BNXT_ULP_CLASS_HID_41bfe] = 1277, - [BNXT_ULP_CLASS_HID_40a58] = 1278, - [BNXT_ULP_CLASS_HID_50a2c] = 1279, - [BNXT_ULP_CLASS_HID_51ae8] = 1280, - [BNXT_ULP_CLASS_HID_4825c] = 1281, - [BNXT_ULP_CLASS_HID_49228] = 1282, - [BNXT_ULP_CLASS_HID_592ec] = 1283, - [BNXT_ULP_CLASS_HID_5815e] = 1284, - [BNXT_ULP_CLASS_HID_41698] = 1285, - [BNXT_ULP_CLASS_HID_4051a] = 1286, - [BNXT_ULP_CLASS_HID_505ce] = 1287, - [BNXT_ULP_CLASS_HID_5158a] = 1288, - [BNXT_ULP_CLASS_HID_49d58] = 1289, - [BNXT_ULP_CLASS_HID_48dca] = 1290, - [BNXT_ULP_CLASS_HID_58d8e] = 1291, - [BNXT_ULP_CLASS_HID_59c5a] = 1292, - [BNXT_ULP_CLASS_HID_4002e] = 1293, - [BNXT_ULP_CLASS_HID_410ea] = 1294, - [BNXT_ULP_CLASS_HID_510ae] = 1295, - [BNXT_ULP_CLASS_HID_50f08] = 1296, - [BNXT_ULP_CLASS_HID_488ee] = 1297, - [BNXT_ULP_CLASS_HID_48748] = 1298, - [BNXT_ULP_CLASS_HID_5870c] = 1299, - [BNXT_ULP_CLASS_HID_597e8] = 1300, - [BNXT_ULP_CLASS_HID_41b4a] = 1301, - [BNXT_ULP_CLASS_HID_40b8c] = 1302, - [BNXT_ULP_CLASS_HID_50a48] = 1303, - [BNXT_ULP_CLASS_HID_51a0c] = 1304, - [BNXT_ULP_CLASS_HID_48388] = 1305, - [BNXT_ULP_CLASS_HID_4924c] = 1306, - [BNXT_ULP_CLASS_HID_59208] = 1307, - [BNXT_ULP_CLASS_HID_5828a] = 1308, - [BNXT_ULP_CLASS_HID_40540] = 1309, - [BNXT_ULP_CLASS_HID_41500] = 1310, - [BNXT_ULP_CLASS_HID_515d0] = 1311, - [BNXT_ULP_CLASS_HID_5044a] = 1312, - [BNXT_ULP_CLASS_HID_48d18] = 1313, - [BNXT_ULP_CLASS_HID_49dd8] = 1314, - [BNXT_ULP_CLASS_HID_59da8] = 1315, - [BNXT_ULP_CLASS_HID_58c02] = 1316, - [BNXT_ULP_CLASS_HID_41048] = 1317, - [BNXT_ULP_CLASS_HID_400c2] = 1318, - [BNXT_ULP_CLASS_HID_50092] = 1319, - [BNXT_ULP_CLASS_HID_51f52] = 1320, - [BNXT_ULP_CLASS_HID_49800] = 1321, - [BNXT_ULP_CLASS_HID_4889a] = 1322, - [BNXT_ULP_CLASS_HID_5974a] = 1323, - [BNXT_ULP_CLASS_HID_587c8] = 1324, - [BNXT_ULP_CLASS_HID_40bc2] = 1325, - [BNXT_ULP_CLASS_HID_41b82] = 1326, - [BNXT_ULP_CLASS_HID_51a62] = 1327, - [BNXT_ULP_CLASS_HID_50ac0] = 1328, - [BNXT_ULP_CLASS_HID_493aa] = 1329, - [BNXT_ULP_CLASS_HID_48208] = 1330, - [BNXT_ULP_CLASS_HID_582c8] = 1331, - [BNXT_ULP_CLASS_HID_59288] = 1332, - [BNXT_ULP_CLASS_HID_40688] = 1333, - [BNXT_ULP_CLASS_HID_41540] = 1334, - [BNXT_ULP_CLASS_HID_51508] = 1335, - [BNXT_ULP_CLASS_HID_50582] = 1336, - [BNXT_ULP_CLASS_HID_48d40] = 1337, - [BNXT_ULP_CLASS_HID_49d08] = 1338, - [BNXT_ULP_CLASS_HID_59dc0] = 1339, - [BNXT_ULP_CLASS_HID_58c4a] = 1340, - [BNXT_ULP_CLASS_HID_4104a] = 1341, - [BNXT_ULP_CLASS_HID_400a8] = 1342, - [BNXT_ULP_CLASS_HID_50f78] = 1343, - [BNXT_ULP_CLASS_HID_51f38] = 1344, - [BNXT_ULP_CLASS_HID_4980a] = 1345, - [BNXT_ULP_CLASS_HID_49768] = 1346, - [BNXT_ULP_CLASS_HID_59738] = 1347, - [BNXT_ULP_CLASS_HID_587aa] = 1348, - [BNXT_ULP_CLASS_HID_40bd8] = 1349, - [BNXT_ULP_CLASS_HID_41bc8] = 1350, - [BNXT_ULP_CLASS_HID_51b88] = 1351, - [BNXT_ULP_CLASS_HID_50ada] = 1352, - [BNXT_ULP_CLASS_HID_493c8] = 1353, - [BNXT_ULP_CLASS_HID_4820a] = 1354, - [BNXT_ULP_CLASS_HID_582da] = 1355, - [BNXT_ULP_CLASS_HID_5929a] = 1356, - [BNXT_ULP_CLASS_HID_4056a] = 1357, - [BNXT_ULP_CLASS_HID_4152a] = 1358, - [BNXT_ULP_CLASS_HID_5150a] = 1359, - [BNXT_ULP_CLASS_HID_50468] = 1360, - [BNXT_ULP_CLASS_HID_48d2a] = 1361, - [BNXT_ULP_CLASS_HID_49dea] = 1362, - [BNXT_ULP_CLASS_HID_59dca] = 1363, - [BNXT_ULP_CLASS_HID_58c28] = 1364, - [BNXT_ULP_CLASS_HID_4118a] = 1365, - [BNXT_ULP_CLASS_HID_400c8] = 1366, - [BNXT_ULP_CLASS_HID_50088] = 1367, - [BNXT_ULP_CLASS_HID_51088] = 1368, - [BNXT_ULP_CLASS_HID_4984a] = 1369, - [BNXT_ULP_CLASS_HID_48888] = 1370, - [BNXT_ULP_CLASS_HID_58888] = 1371, - [BNXT_ULP_CLASS_HID_587ca] = 1372, - [BNXT_ULP_CLASS_HID_10690] = 1373, - [BNXT_ULP_CLASS_HID_112b0] = 1374, - [BNXT_ULP_CLASS_HID_1428c] = 1375, - [BNXT_ULP_CLASS_HID_15eac] = 1376, - [BNXT_ULP_CLASS_HID_1249e] = 1377, - [BNXT_ULP_CLASS_HID_130be] = 1378, - [BNXT_ULP_CLASS_HID_16f7a] = 1379, - [BNXT_ULP_CLASS_HID_17c9a] = 1380, - [BNXT_ULP_CLASS_HID_1119a] = 1381, - [BNXT_ULP_CLASS_HID_10c58] = 1382, - [BNXT_ULP_CLASS_HID_15c7e] = 1383, - [BNXT_ULP_CLASS_HID_1483c] = 1384, - [BNXT_ULP_CLASS_HID_13f88] = 1385, - [BNXT_ULP_CLASS_HID_12a4e] = 1386, - [BNXT_ULP_CLASS_HID_17a6c] = 1387, - [BNXT_ULP_CLASS_HID_1762a] = 1388, - [BNXT_ULP_CLASS_HID_11b46] = 1389, - [BNXT_ULP_CLASS_HID_11704] = 1390, - [BNXT_ULP_CLASS_HID_147c4] = 1391, - [BNXT_ULP_CLASS_HID_153e4] = 1392, - [BNXT_ULP_CLASS_HID_13934] = 1393, - [BNXT_ULP_CLASS_HID_135f6] = 1394, - [BNXT_ULP_CLASS_HID_165ce] = 1395, - [BNXT_ULP_CLASS_HID_171ee] = 1396, - [BNXT_ULP_CLASS_HID_116ee] = 1397, - [BNXT_ULP_CLASS_HID_102ac] = 1398, - [BNXT_ULP_CLASS_HID_152ce] = 1399, - [BNXT_ULP_CLASS_HID_14e8c] = 1400, - [BNXT_ULP_CLASS_HID_134dc] = 1401, - [BNXT_ULP_CLASS_HID_1209e] = 1402, - [BNXT_ULP_CLASS_HID_170bc] = 1403, - [BNXT_ULP_CLASS_HID_16b7e] = 1404, - [BNXT_ULP_CLASS_HID_119ae] = 1405, - [BNXT_ULP_CLASS_HID_1146a] = 1406, - [BNXT_ULP_CLASS_HID_14426] = 1407, - [BNXT_ULP_CLASS_HID_15046] = 1408, - [BNXT_ULP_CLASS_HID_1263a] = 1409, - [BNXT_ULP_CLASS_HID_1325a] = 1410, - [BNXT_ULP_CLASS_HID_16216] = 1411, - [BNXT_ULP_CLASS_HID_17e36] = 1412, - [BNXT_ULP_CLASS_HID_1133e] = 1413, - [BNXT_ULP_CLASS_HID_10ffa] = 1414, - [BNXT_ULP_CLASS_HID_15f1a] = 1415, - [BNXT_ULP_CLASS_HID_14bee] = 1416, - [BNXT_ULP_CLASS_HID_1312a] = 1417, - [BNXT_ULP_CLASS_HID_12dea] = 1418, - [BNXT_ULP_CLASS_HID_17d1e] = 1419, - [BNXT_ULP_CLASS_HID_169de] = 1420, - [BNXT_ULP_CLASS_HID_11ee6] = 1421, - [BNXT_ULP_CLASS_HID_10abe] = 1422, - [BNXT_ULP_CLASS_HID_15ade] = 1423, - [BNXT_ULP_CLASS_HID_1569e] = 1424, - [BNXT_ULP_CLASS_HID_13cee] = 1425, - [BNXT_ULP_CLASS_HID_128ae] = 1426, - [BNXT_ULP_CLASS_HID_1676e] = 1427, - [BNXT_ULP_CLASS_HID_1748e] = 1428, - [BNXT_ULP_CLASS_HID_1098e] = 1429, - [BNXT_ULP_CLASS_HID_1044e] = 1430, - [BNXT_ULP_CLASS_HID_1546e] = 1431, - [BNXT_ULP_CLASS_HID_1402e] = 1432, - [BNXT_ULP_CLASS_HID_1367e] = 1433, - [BNXT_ULP_CLASS_HID_1223e] = 1434, - [BNXT_ULP_CLASS_HID_1725e] = 1435, - [BNXT_ULP_CLASS_HID_16e1e] = 1436, - [BNXT_ULP_CLASS_HID_1172f] = 1437, - [BNXT_ULP_CLASS_HID_103ed] = 1438, - [BNXT_ULP_CLASS_HID_1530b] = 1439, - [BNXT_ULP_CLASS_HID_14fc9] = 1440, - [BNXT_ULP_CLASS_HID_1351d] = 1441, - [BNXT_ULP_CLASS_HID_121db] = 1442, - [BNXT_ULP_CLASS_HID_171f9] = 1443, - [BNXT_ULP_CLASS_HID_16db7] = 1444, - [BNXT_ULP_CLASS_HID_102bf] = 1445, - [BNXT_ULP_CLASS_HID_11edf] = 1446, - [BNXT_ULP_CLASS_HID_14e9b] = 1447, - [BNXT_ULP_CLASS_HID_15abb] = 1448, - [BNXT_ULP_CLASS_HID_120ad] = 1449, - [BNXT_ULP_CLASS_HID_13ccd] = 1450, - [BNXT_ULP_CLASS_HID_16c89] = 1451, - [BNXT_ULP_CLASS_HID_1675f] = 1452, - [BNXT_ULP_CLASS_HID_10c67] = 1453, - [BNXT_ULP_CLASS_HID_11987] = 1454, - [BNXT_ULP_CLASS_HID_1485f] = 1455, - [BNXT_ULP_CLASS_HID_1441d] = 1456, - [BNXT_ULP_CLASS_HID_12a55] = 1457, - [BNXT_ULP_CLASS_HID_1262f] = 1458, - [BNXT_ULP_CLASS_HID_1764d] = 1459, - [BNXT_ULP_CLASS_HID_1620f] = 1460, - [BNXT_ULP_CLASS_HID_1070f] = 1461, - [BNXT_ULP_CLASS_HID_1132f] = 1462, - [BNXT_ULP_CLASS_HID_143ef] = 1463, - [BNXT_ULP_CLASS_HID_15f0f] = 1464, - [BNXT_ULP_CLASS_HID_125fd] = 1465, - [BNXT_ULP_CLASS_HID_1311d] = 1466, - [BNXT_ULP_CLASS_HID_161dd] = 1467, - [BNXT_ULP_CLASS_HID_17dfd] = 1468, - [BNXT_ULP_CLASS_HID_10acb] = 1469, - [BNXT_ULP_CLASS_HID_10687] = 1470, - [BNXT_ULP_CLASS_HID_156a7] = 1471, - [BNXT_ULP_CLASS_HID_14163] = 1472, - [BNXT_ULP_CLASS_HID_128b7] = 1473, - [BNXT_ULP_CLASS_HID_12377] = 1474, - [BNXT_ULP_CLASS_HID_17493] = 1475, - [BNXT_ULP_CLASS_HID_16f53] = 1476, - [BNXT_ULP_CLASS_HID_1045b] = 1477, - [BNXT_ULP_CLASS_HID_1107b] = 1478, - [BNXT_ULP_CLASS_HID_1404f] = 1479, - [BNXT_ULP_CLASS_HID_15c6f] = 1480, - [BNXT_ULP_CLASS_HID_1225f] = 1481, - [BNXT_ULP_CLASS_HID_13e7f] = 1482, - [BNXT_ULP_CLASS_HID_16e3b] = 1483, - [BNXT_ULP_CLASS_HID_17a5b] = 1484, - [BNXT_ULP_CLASS_HID_10f1f] = 1485, - [BNXT_ULP_CLASS_HID_11b3f] = 1486, - [BNXT_ULP_CLASS_HID_14bff] = 1487, - [BNXT_ULP_CLASS_HID_147b7] = 1488, - [BNXT_ULP_CLASS_HID_12d0f] = 1489, - [BNXT_ULP_CLASS_HID_1392f] = 1490, - [BNXT_ULP_CLASS_HID_169e7] = 1491, - [BNXT_ULP_CLASS_HID_165a7] = 1492, - [BNXT_ULP_CLASS_HID_11a0f] = 1493, - [BNXT_ULP_CLASS_HID_116cf] = 1494, - [BNXT_ULP_CLASS_HID_1468f] = 1495, - [BNXT_ULP_CLASS_HID_152af] = 1496, - [BNXT_ULP_CLASS_HID_138ff] = 1497, - [BNXT_ULP_CLASS_HID_134bf] = 1498, - [BNXT_ULP_CLASS_HID_1648f] = 1499, - [BNXT_ULP_CLASS_HID_170af] = 1500, - [BNXT_ULP_CLASS_HID_40c38] = 1501, - [BNXT_ULP_CLASS_HID_41c04] = 1502, - [BNXT_ULP_CLASS_HID_51c48] = 1503, - [BNXT_ULP_CLASS_HID_50332] = 1504, - [BNXT_ULP_CLASS_HID_48400] = 1505, - [BNXT_ULP_CLASS_HID_48bea] = 1506, - [BNXT_ULP_CLASS_HID_58b3e] = 1507, - [BNXT_ULP_CLASS_HID_59b7a] = 1508, - [BNXT_ULP_CLASS_HID_417dc] = 1509, - [BNXT_ULP_CLASS_HID_40746] = 1510, - [BNXT_ULP_CLASS_HID_5068a] = 1511, - [BNXT_ULP_CLASS_HID_516d6] = 1512, - [BNXT_ULP_CLASS_HID_48f42] = 1513, - [BNXT_ULP_CLASS_HID_49e8e] = 1514, - [BNXT_ULP_CLASS_HID_59ed2] = 1515, - [BNXT_ULP_CLASS_HID_58d9c] = 1516, - [BNXT_ULP_CLASS_HID_41a4a] = 1517, - [BNXT_ULP_CLASS_HID_40924] = 1518, - [BNXT_ULP_CLASS_HID_50968] = 1519, - [BNXT_ULP_CLASS_HID_51944] = 1520, - [BNXT_ULP_CLASS_HID_49182] = 1521, - [BNXT_ULP_CLASS_HID_4816c] = 1522, - [BNXT_ULP_CLASS_HID_58140] = 1523, - [BNXT_ULP_CLASS_HID_5908c] = 1524, - [BNXT_ULP_CLASS_HID_40c8c] = 1525, - [BNXT_ULP_CLASS_HID_41cc8] = 1526, - [BNXT_ULP_CLASS_HID_51c0c] = 1527, - [BNXT_ULP_CLASS_HID_50386] = 1528, - [BNXT_ULP_CLASS_HID_484c4] = 1529, - [BNXT_ULP_CLASS_HID_48b8e] = 1530, - [BNXT_ULP_CLASS_HID_58b82] = 1531, - [BNXT_ULP_CLASS_HID_59bce] = 1532, - [BNXT_ULP_CLASS_HID_10a54] = 1533, - [BNXT_ULP_CLASS_HID_11e74] = 1534, - [BNXT_ULP_CLASS_HID_14e48] = 1535, - [BNXT_ULP_CLASS_HID_15268] = 1536, - [BNXT_ULP_CLASS_HID_1285a] = 1537, - [BNXT_ULP_CLASS_HID_13c7a] = 1538, - [BNXT_ULP_CLASS_HID_163be] = 1539, - [BNXT_ULP_CLASS_HID_1705e] = 1540, - [BNXT_ULP_CLASS_HID_11d5e] = 1541, - [BNXT_ULP_CLASS_HID_1009c] = 1542, - [BNXT_ULP_CLASS_HID_150ba] = 1543, - [BNXT_ULP_CLASS_HID_144f8] = 1544, - [BNXT_ULP_CLASS_HID_1334c] = 1545, - [BNXT_ULP_CLASS_HID_1268a] = 1546, - [BNXT_ULP_CLASS_HID_176a8] = 1547, - [BNXT_ULP_CLASS_HID_17aee] = 1548, - [BNXT_ULP_CLASS_HID_11782] = 1549, - [BNXT_ULP_CLASS_HID_11bc0] = 1550, - [BNXT_ULP_CLASS_HID_14b00] = 1551, - [BNXT_ULP_CLASS_HID_15f20] = 1552, - [BNXT_ULP_CLASS_HID_135f0] = 1553, - [BNXT_ULP_CLASS_HID_13932] = 1554, - [BNXT_ULP_CLASS_HID_1690a] = 1555, - [BNXT_ULP_CLASS_HID_17d2a] = 1556, - [BNXT_ULP_CLASS_HID_11a2a] = 1557, - [BNXT_ULP_CLASS_HID_10e68] = 1558, - [BNXT_ULP_CLASS_HID_15e0a] = 1559, - [BNXT_ULP_CLASS_HID_14248] = 1560, - [BNXT_ULP_CLASS_HID_13818] = 1561, - [BNXT_ULP_CLASS_HID_12c5a] = 1562, - [BNXT_ULP_CLASS_HID_17c78] = 1563, - [BNXT_ULP_CLASS_HID_167ba] = 1564, - [BNXT_ULP_CLASS_HID_1f91] = 1565, - [BNXT_ULP_CLASS_HID_0763] = 1566, - [BNXT_ULP_CLASS_HID_0f7b] = 1567, - [BNXT_ULP_CLASS_HID_16af] = 1568, - [BNXT_ULP_CLASS_HID_1daf] = 1569, - [BNXT_ULP_CLASS_HID_0539] = 1570, - [BNXT_ULP_CLASS_HID_01ed] = 1571, - [BNXT_ULP_CLASS_HID_097f] = 1572, - [BNXT_ULP_CLASS_HID_81ab8] = 1573, - [BNXT_ULP_CLASS_HID_8020e] = 1574, - [BNXT_ULP_CLASS_HID_815d8] = 1575, - [BNXT_ULP_CLASS_HID_81cae] = 1576, - [BNXT_ULP_CLASS_HID_810a8] = 1577, - [BNXT_ULP_CLASS_HID_8183e] = 1578, - [BNXT_ULP_CLASS_HID_8036a] = 1579, - [BNXT_ULP_CLASS_HID_80af8] = 1580, - [BNXT_ULP_CLASS_HID_206fe] = 1581, - [BNXT_ULP_CLASS_HID_20e4c] = 1582, - [BNXT_ULP_CLASS_HID_2111e] = 1583, - [BNXT_ULP_CLASS_HID_218ec] = 1584, - [BNXT_ULP_CLASS_HID_60472] = 1585, - [BNXT_ULP_CLASS_HID_603c0] = 1586, - [BNXT_ULP_CLASS_HID_61692] = 1587, - [BNXT_ULP_CLASS_HID_61e60] = 1588, - [BNXT_ULP_CLASS_HID_1f81] = 1589, - [BNXT_ULP_CLASS_HID_0773] = 1590, - [BNXT_ULP_CLASS_HID_0f6b] = 1591, - [BNXT_ULP_CLASS_HID_16bf] = 1592, - [BNXT_ULP_CLASS_HID_03cf] = 1593, - [BNXT_ULP_CLASS_HID_0ab1] = 1594, - [BNXT_ULP_CLASS_HID_130b] = 1595, - [BNXT_ULP_CLASS_HID_1afd] = 1596, - [BNXT_ULP_CLASS_HID_1591] = 1597, - [BNXT_ULP_CLASS_HID_1d03] = 1598, - [BNXT_ULP_CLASS_HID_057b] = 1599, - [BNXT_ULP_CLASS_HID_0ced] = 1600, - [BNXT_ULP_CLASS_HID_19df] = 1601, - [BNXT_ULP_CLASS_HID_0141] = 1602, - [BNXT_ULP_CLASS_HID_08b9] = 1603, - [BNXT_ULP_CLASS_HID_108d] = 1604, - [BNXT_ULP_CLASS_HID_1dbf] = 1605, - [BNXT_ULP_CLASS_HID_0529] = 1606, - [BNXT_ULP_CLASS_HID_01fd] = 1607, - [BNXT_ULP_CLASS_HID_096f] = 1608, - [BNXT_ULP_CLASS_HID_810b7] = 1609, - [BNXT_ULP_CLASS_HID_81821] = 1610, - [BNXT_ULP_CLASS_HID_804f5] = 1611, - [BNXT_ULP_CLASS_HID_80c67] = 1612, - [BNXT_ULP_CLASS_HID_41333] = 1613, - [BNXT_ULP_CLASS_HID_41aad] = 1614, - [BNXT_ULP_CLASS_HID_40771] = 1615, - [BNXT_ULP_CLASS_HID_40ee3] = 1616, - [BNXT_ULP_CLASS_HID_c16cb] = 1617, - [BNXT_ULP_CLASS_HID_c1da5] = 1618, - [BNXT_ULP_CLASS_HID_c1a09] = 1619, - [BNXT_ULP_CLASS_HID_c01fb] = 1620, - [BNXT_ULP_CLASS_HID_1ff1] = 1621, - [BNXT_ULP_CLASS_HID_0703] = 1622, - [BNXT_ULP_CLASS_HID_0f1b] = 1623, - [BNXT_ULP_CLASS_HID_16cf] = 1624, - [BNXT_ULP_CLASS_HID_03bf] = 1625, - [BNXT_ULP_CLASS_HID_0ac1] = 1626, - [BNXT_ULP_CLASS_HID_137b] = 1627, - [BNXT_ULP_CLASS_HID_1a8d] = 1628, - [BNXT_ULP_CLASS_HID_15e1] = 1629, - [BNXT_ULP_CLASS_HID_1d73] = 1630, - [BNXT_ULP_CLASS_HID_050b] = 1631, - [BNXT_ULP_CLASS_HID_0c9d] = 1632, - [BNXT_ULP_CLASS_HID_19af] = 1633, - [BNXT_ULP_CLASS_HID_0131] = 1634, - [BNXT_ULP_CLASS_HID_08c9] = 1635, - [BNXT_ULP_CLASS_HID_10fd] = 1636, - [BNXT_ULP_CLASS_HID_1dcf] = 1637, - [BNXT_ULP_CLASS_HID_0559] = 1638, - [BNXT_ULP_CLASS_HID_018d] = 1639, - [BNXT_ULP_CLASS_HID_091f] = 1640, - [BNXT_ULP_CLASS_HID_810c7] = 1641, - [BNXT_ULP_CLASS_HID_81851] = 1642, - [BNXT_ULP_CLASS_HID_80485] = 1643, - [BNXT_ULP_CLASS_HID_80c17] = 1644, - [BNXT_ULP_CLASS_HID_41343] = 1645, - [BNXT_ULP_CLASS_HID_41add] = 1646, - [BNXT_ULP_CLASS_HID_40701] = 1647, - [BNXT_ULP_CLASS_HID_40e93] = 1648, - [BNXT_ULP_CLASS_HID_c16bb] = 1649, - [BNXT_ULP_CLASS_HID_c1dd5] = 1650, - [BNXT_ULP_CLASS_HID_c1a79] = 1651, - [BNXT_ULP_CLASS_HID_c018b] = 1652, - [BNXT_ULP_CLASS_HID_81aa8] = 1653, - [BNXT_ULP_CLASS_HID_8021e] = 1654, - [BNXT_ULP_CLASS_HID_815c8] = 1655, - [BNXT_ULP_CLASS_HID_81cbe] = 1656, - [BNXT_ULP_CLASS_HID_810b8] = 1657, - [BNXT_ULP_CLASS_HID_8182e] = 1658, - [BNXT_ULP_CLASS_HID_8037a] = 1659, - [BNXT_ULP_CLASS_HID_80ae8] = 1660, - [BNXT_ULP_CLASS_HID_c1834] = 1661, - [BNXT_ULP_CLASS_HID_c079a] = 1662, - [BNXT_ULP_CLASS_HID_c0af6] = 1663, - [BNXT_ULP_CLASS_HID_c123a] = 1664, - [BNXT_ULP_CLASS_HID_c16c4] = 1665, - [BNXT_ULP_CLASS_HID_c1daa] = 1666, - [BNXT_ULP_CLASS_HID_c0086] = 1667, - [BNXT_ULP_CLASS_HID_c0874] = 1668, - [BNXT_ULP_CLASS_HID_a19ea] = 1669, - [BNXT_ULP_CLASS_HID_a0158] = 1670, - [BNXT_ULP_CLASS_HID_a0bb4] = 1671, - [BNXT_ULP_CLASS_HID_a13f8] = 1672, - [BNXT_ULP_CLASS_HID_a17fa] = 1673, - [BNXT_ULP_CLASS_HID_a1f68] = 1674, - [BNXT_ULP_CLASS_HID_a0244] = 1675, - [BNXT_ULP_CLASS_HID_a092a] = 1676, - [BNXT_ULP_CLASS_HID_e1f76] = 1677, - [BNXT_ULP_CLASS_HID_e06e4] = 1678, - [BNXT_ULP_CLASS_HID_e0930] = 1679, - [BNXT_ULP_CLASS_HID_e1104] = 1680, - [BNXT_ULP_CLASS_HID_e1506] = 1681, - [BNXT_ULP_CLASS_HID_e1cf4] = 1682, - [BNXT_ULP_CLASS_HID_e07c0] = 1683, - [BNXT_ULP_CLASS_HID_e0eb6] = 1684, - [BNXT_ULP_CLASS_HID_206ee] = 1685, - [BNXT_ULP_CLASS_HID_20e5c] = 1686, - [BNXT_ULP_CLASS_HID_2110e] = 1687, - [BNXT_ULP_CLASS_HID_218fc] = 1688, - [BNXT_ULP_CLASS_HID_60462] = 1689, - [BNXT_ULP_CLASS_HID_603d0] = 1690, - [BNXT_ULP_CLASS_HID_61682] = 1691, - [BNXT_ULP_CLASS_HID_61e70] = 1692, - [BNXT_ULP_CLASS_HID_3167e] = 1693, - [BNXT_ULP_CLASS_HID_31dec] = 1694, - [BNXT_ULP_CLASS_HID_30030] = 1695, - [BNXT_ULP_CLASS_HID_30fae] = 1696, - [BNXT_ULP_CLASS_HID_70b14] = 1697, - [BNXT_ULP_CLASS_HID_71360] = 1698, - [BNXT_ULP_CLASS_HID_705b4] = 1699, - [BNXT_ULP_CLASS_HID_70d22] = 1700, - [BNXT_ULP_CLASS_HID_29e26] = 1701, - [BNXT_ULP_CLASS_HID_28594] = 1702, - [BNXT_ULP_CLASS_HID_288f8] = 1703, - [BNXT_ULP_CLASS_HID_29034] = 1704, - [BNXT_ULP_CLASS_HID_693ba] = 1705, - [BNXT_ULP_CLASS_HID_69b28] = 1706, - [BNXT_ULP_CLASS_HID_68e7c] = 1707, - [BNXT_ULP_CLASS_HID_69648] = 1708, - [BNXT_ULP_CLASS_HID_38de8] = 1709, - [BNXT_ULP_CLASS_HID_39524] = 1710, - [BNXT_ULP_CLASS_HID_39808] = 1711, - [BNXT_ULP_CLASS_HID_387e6] = 1712, - [BNXT_ULP_CLASS_HID_7836c] = 1713, - [BNXT_ULP_CLASS_HID_78ada] = 1714, - [BNXT_ULP_CLASS_HID_79d8c] = 1715, - [BNXT_ULP_CLASS_HID_7857a] = 1716, - [BNXT_ULP_CLASS_HID_81ad8] = 1717, - [BNXT_ULP_CLASS_HID_8026e] = 1718, - [BNXT_ULP_CLASS_HID_815b8] = 1719, - [BNXT_ULP_CLASS_HID_81cce] = 1720, - [BNXT_ULP_CLASS_HID_810c8] = 1721, - [BNXT_ULP_CLASS_HID_8185e] = 1722, - [BNXT_ULP_CLASS_HID_8030a] = 1723, - [BNXT_ULP_CLASS_HID_80a98] = 1724, - [BNXT_ULP_CLASS_HID_c1844] = 1725, - [BNXT_ULP_CLASS_HID_c07ea] = 1726, - [BNXT_ULP_CLASS_HID_c0a86] = 1727, - [BNXT_ULP_CLASS_HID_c124a] = 1728, - [BNXT_ULP_CLASS_HID_c16b4] = 1729, - [BNXT_ULP_CLASS_HID_c1dda] = 1730, - [BNXT_ULP_CLASS_HID_c00f6] = 1731, - [BNXT_ULP_CLASS_HID_c0804] = 1732, - [BNXT_ULP_CLASS_HID_a199a] = 1733, - [BNXT_ULP_CLASS_HID_a0128] = 1734, - [BNXT_ULP_CLASS_HID_a0bc4] = 1735, - [BNXT_ULP_CLASS_HID_a1388] = 1736, - [BNXT_ULP_CLASS_HID_a178a] = 1737, - [BNXT_ULP_CLASS_HID_a1f18] = 1738, - [BNXT_ULP_CLASS_HID_a0234] = 1739, - [BNXT_ULP_CLASS_HID_a095a] = 1740, - [BNXT_ULP_CLASS_HID_e1f06] = 1741, - [BNXT_ULP_CLASS_HID_e0694] = 1742, - [BNXT_ULP_CLASS_HID_e0940] = 1743, - [BNXT_ULP_CLASS_HID_e1174] = 1744, - [BNXT_ULP_CLASS_HID_e1576] = 1745, - [BNXT_ULP_CLASS_HID_e1c84] = 1746, - [BNXT_ULP_CLASS_HID_e07b0] = 1747, - [BNXT_ULP_CLASS_HID_e0ec6] = 1748, - [BNXT_ULP_CLASS_HID_2069e] = 1749, - [BNXT_ULP_CLASS_HID_20e2c] = 1750, - [BNXT_ULP_CLASS_HID_2117e] = 1751, - [BNXT_ULP_CLASS_HID_2188c] = 1752, - [BNXT_ULP_CLASS_HID_60412] = 1753, - [BNXT_ULP_CLASS_HID_603a0] = 1754, - [BNXT_ULP_CLASS_HID_616f2] = 1755, - [BNXT_ULP_CLASS_HID_61e00] = 1756, - [BNXT_ULP_CLASS_HID_3160e] = 1757, - [BNXT_ULP_CLASS_HID_31d9c] = 1758, - [BNXT_ULP_CLASS_HID_30040] = 1759, - [BNXT_ULP_CLASS_HID_30fde] = 1760, - [BNXT_ULP_CLASS_HID_70b64] = 1761, - [BNXT_ULP_CLASS_HID_71310] = 1762, - [BNXT_ULP_CLASS_HID_705c4] = 1763, - [BNXT_ULP_CLASS_HID_70d52] = 1764, - [BNXT_ULP_CLASS_HID_29e56] = 1765, - [BNXT_ULP_CLASS_HID_285e4] = 1766, - [BNXT_ULP_CLASS_HID_28888] = 1767, - [BNXT_ULP_CLASS_HID_29044] = 1768, - [BNXT_ULP_CLASS_HID_693ca] = 1769, - [BNXT_ULP_CLASS_HID_69b58] = 1770, - [BNXT_ULP_CLASS_HID_68e0c] = 1771, - [BNXT_ULP_CLASS_HID_69638] = 1772, - [BNXT_ULP_CLASS_HID_38d98] = 1773, - [BNXT_ULP_CLASS_HID_39554] = 1774, - [BNXT_ULP_CLASS_HID_39878] = 1775, - [BNXT_ULP_CLASS_HID_38796] = 1776, - [BNXT_ULP_CLASS_HID_7831c] = 1777, - [BNXT_ULP_CLASS_HID_78aaa] = 1778, - [BNXT_ULP_CLASS_HID_79dfc] = 1779, - [BNXT_ULP_CLASS_HID_7850a] = 1780, - [BNXT_ULP_CLASS_HID_03b7] = 1781, - [BNXT_ULP_CLASS_HID_13f3] = 1782, - [BNXT_ULP_CLASS_HID_0255] = 1783, - [BNXT_ULP_CLASS_HID_1675] = 1784, - [BNXT_ULP_CLASS_HID_80f52] = 1785, - [BNXT_ULP_CLASS_HID_819f2] = 1786, - [BNXT_ULP_CLASS_HID_80542] = 1787, - [BNXT_ULP_CLASS_HID_817e2] = 1788, - [BNXT_ULP_CLASS_HID_20a98] = 1789, - [BNXT_ULP_CLASS_HID_20538] = 1790, - [BNXT_ULP_CLASS_HID_6081c] = 1791, - [BNXT_ULP_CLASS_HID_61abc] = 1792, - [BNXT_ULP_CLASS_HID_03a7] = 1793, - [BNXT_ULP_CLASS_HID_13e3] = 1794, - [BNXT_ULP_CLASS_HID_1047] = 1795, - [BNXT_ULP_CLASS_HID_0721] = 1796, - [BNXT_ULP_CLASS_HID_19b7] = 1797, - [BNXT_ULP_CLASS_HID_0911] = 1798, - [BNXT_ULP_CLASS_HID_0df5] = 1799, - [BNXT_ULP_CLASS_HID_1d31] = 1800, - [BNXT_ULP_CLASS_HID_0245] = 1801, - [BNXT_ULP_CLASS_HID_1665] = 1802, - [BNXT_ULP_CLASS_HID_8055d] = 1803, - [BNXT_ULP_CLASS_HID_80893] = 1804, - [BNXT_ULP_CLASS_HID_407d9] = 1805, - [BNXT_ULP_CLASS_HID_40b1f] = 1806, - [BNXT_ULP_CLASS_HID_c1ad1] = 1807, - [BNXT_ULP_CLASS_HID_c0e17] = 1808, - [BNXT_ULP_CLASS_HID_03d7] = 1809, - [BNXT_ULP_CLASS_HID_1393] = 1810, - [BNXT_ULP_CLASS_HID_1037] = 1811, - [BNXT_ULP_CLASS_HID_0751] = 1812, - [BNXT_ULP_CLASS_HID_19c7] = 1813, - [BNXT_ULP_CLASS_HID_0961] = 1814, - [BNXT_ULP_CLASS_HID_0d85] = 1815, - [BNXT_ULP_CLASS_HID_1d41] = 1816, - [BNXT_ULP_CLASS_HID_0235] = 1817, - [BNXT_ULP_CLASS_HID_1615] = 1818, - [BNXT_ULP_CLASS_HID_8052d] = 1819, - [BNXT_ULP_CLASS_HID_808e3] = 1820, - [BNXT_ULP_CLASS_HID_407a9] = 1821, - [BNXT_ULP_CLASS_HID_40b6f] = 1822, - [BNXT_ULP_CLASS_HID_c1aa1] = 1823, - [BNXT_ULP_CLASS_HID_c0e67] = 1824, - [BNXT_ULP_CLASS_HID_80f42] = 1825, - [BNXT_ULP_CLASS_HID_819e2] = 1826, - [BNXT_ULP_CLASS_HID_80552] = 1827, - [BNXT_ULP_CLASS_HID_817f2] = 1828, - [BNXT_ULP_CLASS_HID_c0cce] = 1829, - [BNXT_ULP_CLASS_HID_c1f6e] = 1830, - [BNXT_ULP_CLASS_HID_c1ade] = 1831, - [BNXT_ULP_CLASS_HID_c157e] = 1832, - [BNXT_ULP_CLASS_HID_a0d8c] = 1833, - [BNXT_ULP_CLASS_HID_a182c] = 1834, - [BNXT_ULP_CLASS_HID_a1b9c] = 1835, - [BNXT_ULP_CLASS_HID_a163c] = 1836, - [BNXT_ULP_CLASS_HID_e0308] = 1837, - [BNXT_ULP_CLASS_HID_e1da8] = 1838, - [BNXT_ULP_CLASS_HID_e1918] = 1839, - [BNXT_ULP_CLASS_HID_e0bda] = 1840, - [BNXT_ULP_CLASS_HID_20a88] = 1841, - [BNXT_ULP_CLASS_HID_20528] = 1842, - [BNXT_ULP_CLASS_HID_6080c] = 1843, - [BNXT_ULP_CLASS_HID_61aac] = 1844, - [BNXT_ULP_CLASS_HID_31a18] = 1845, - [BNXT_ULP_CLASS_HID_314b8] = 1846, - [BNXT_ULP_CLASS_HID_71f9c] = 1847, - [BNXT_ULP_CLASS_HID_70a5e] = 1848, - [BNXT_ULP_CLASS_HID_282c0] = 1849, - [BNXT_ULP_CLASS_HID_29d60] = 1850, - [BNXT_ULP_CLASS_HID_68044] = 1851, - [BNXT_ULP_CLASS_HID_692e4] = 1852, - [BNXT_ULP_CLASS_HID_39250] = 1853, - [BNXT_ULP_CLASS_HID_38c12] = 1854, - [BNXT_ULP_CLASS_HID_797d4] = 1855, - [BNXT_ULP_CLASS_HID_78196] = 1856, - [BNXT_ULP_CLASS_HID_80f32] = 1857, - [BNXT_ULP_CLASS_HID_81992] = 1858, - [BNXT_ULP_CLASS_HID_80522] = 1859, - [BNXT_ULP_CLASS_HID_81782] = 1860, - [BNXT_ULP_CLASS_HID_c0cbe] = 1861, - [BNXT_ULP_CLASS_HID_c1f1e] = 1862, - [BNXT_ULP_CLASS_HID_c1aae] = 1863, - [BNXT_ULP_CLASS_HID_c150e] = 1864, - [BNXT_ULP_CLASS_HID_a0dfc] = 1865, - [BNXT_ULP_CLASS_HID_a185c] = 1866, - [BNXT_ULP_CLASS_HID_a1bec] = 1867, - [BNXT_ULP_CLASS_HID_a164c] = 1868, - [BNXT_ULP_CLASS_HID_e0378] = 1869, - [BNXT_ULP_CLASS_HID_e1dd8] = 1870, - [BNXT_ULP_CLASS_HID_e1968] = 1871, - [BNXT_ULP_CLASS_HID_e0baa] = 1872, - [BNXT_ULP_CLASS_HID_20af8] = 1873, - [BNXT_ULP_CLASS_HID_20558] = 1874, - [BNXT_ULP_CLASS_HID_6087c] = 1875, - [BNXT_ULP_CLASS_HID_61adc] = 1876, - [BNXT_ULP_CLASS_HID_31a68] = 1877, - [BNXT_ULP_CLASS_HID_314c8] = 1878, - [BNXT_ULP_CLASS_HID_71fec] = 1879, - [BNXT_ULP_CLASS_HID_70a2e] = 1880, - [BNXT_ULP_CLASS_HID_282b0] = 1881, - [BNXT_ULP_CLASS_HID_29d10] = 1882, - [BNXT_ULP_CLASS_HID_68034] = 1883, - [BNXT_ULP_CLASS_HID_69294] = 1884, - [BNXT_ULP_CLASS_HID_39220] = 1885, - [BNXT_ULP_CLASS_HID_38c62] = 1886, - [BNXT_ULP_CLASS_HID_797a4] = 1887, - [BNXT_ULP_CLASS_HID_781e6] = 1888, - [BNXT_ULP_CLASS_HID_0f05] = 1889, - [BNXT_ULP_CLASS_HID_0f09] = 1890, - [BNXT_ULP_CLASS_HID_0f06] = 1891, - [BNXT_ULP_CLASS_HID_19a6] = 1892, - [BNXT_ULP_CLASS_HID_0f0a] = 1893, - [BNXT_ULP_CLASS_HID_19aa] = 1894, - [BNXT_ULP_CLASS_HID_0f15] = 1895, - [BNXT_ULP_CLASS_HID_0f19] = 1896, - [BNXT_ULP_CLASS_HID_0f65] = 1897, - [BNXT_ULP_CLASS_HID_0f69] = 1898, - [BNXT_ULP_CLASS_HID_0f16] = 1899, - [BNXT_ULP_CLASS_HID_19b6] = 1900, - [BNXT_ULP_CLASS_HID_0f1a] = 1901, - [BNXT_ULP_CLASS_HID_19ba] = 1902, - [BNXT_ULP_CLASS_HID_0f66] = 1903, - [BNXT_ULP_CLASS_HID_19c6] = 1904, - [BNXT_ULP_CLASS_HID_0f6a] = 1905, - [BNXT_ULP_CLASS_HID_19ca] = 1906 -}; - -/* Array for the proto matcher list */ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { [1] = { - .class_hid = BNXT_ULP_CLASS_HID_00b8, - .class_tid = 1, - .hdr_sig_id = 0, - .flow_sig_id = 4096UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = + .app_id = 0, + .hdr_bitmap = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_0_BITMASK_O_IPV6_DST_ADDR } + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xB800000000000000, + .field_exclude_bitmap = 0x2000000000000000, + .class_tid = 1, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + }, }, [2] = { - .class_hid = BNXT_ULP_CLASS_HID_0cc2, + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x9000000000000000, + .field_exclude_bitmap = 0x0, .class_tid = 1, - .hdr_sig_id = 0, - .flow_sig_id = 4104UL, .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_0_BITMASK_O_IPV6_DST_ADDR } + .field_list = { + [1] = 1, + [108] = 2, + [112] = 3, + [116] = 4, + }, }, [3] = { - .class_hid = BNXT_ULP_CLASS_HID_10e4, - .class_tid = 1, - .hdr_sig_id = 0, - .flow_sig_id = 6144UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = + .app_id = 0, + .hdr_bitmap = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_0_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_0_BITMASK_O_IPV6_DST_ADDR } + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBA00000000000000, + .field_exclude_bitmap = 0x2000000000000000, + .class_tid = 1, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [108] = 5, + [112] = 6, + [116] = 7, + }, }, [4] = { - .class_hid = BNXT_ULP_CLASS_HID_1d0e, + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x9000000000000000, + .field_exclude_bitmap = 0x0, .class_tid = 1, - .hdr_sig_id = 0, - .flow_sig_id = 6152UL, .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_0_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_0_BITMASK_O_IPV6_DST_ADDR } + .field_list = { + [1] = 1, + [109] = 2, + [113] = 3, + [117] = 4, + }, }, [5] = { - .class_hid = BNXT_ULP_CLASS_HID_0286, - .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 16384UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = + .app_id = 0, + .hdr_bitmap = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_OI_VLAN | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_1_BITMASK_O_IPV4_DST_ADDR } + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBA00000000000000, + .field_exclude_bitmap = 0x2000000000000000, + .class_tid = 1, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [109] = 5, + [113] = 6, + [117] = 7, + }, }, [6] = { - .class_hid = BNXT_ULP_CLASS_HID_0e98, + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x9200000000000000, + .field_exclude_bitmap = 0x0, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 16392UL, .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_1_BITMASK_O_IPV4_DST_ADDR } + .field_list = { + [1] = 1, + [108] = 2, + [109] = 5, + [112] = 3, + [113] = 6, + [116] = 4, + [117] = 7, + }, }, [7] = { - .class_hid = BNXT_ULP_CLASS_HID_1666, - .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 24576UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = + .app_id = 0, + .hdr_bitmap = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_OI_VLAN | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_1_BITMASK_O_IPV4_DST_ADDR } + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBA40000000000000, + .field_exclude_bitmap = 0x2000000000000000, + .class_tid = 1, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [108] = 5, + [109] = 8, + [112] = 6, + [113] = 9, + [116] = 7, + [117] = 10, + }, }, [8] = { - .class_hid = BNXT_ULP_CLASS_HID_02de, + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x93C0000000000000, + .field_exclude_bitmap = 0x0, .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 24584UL, .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_1_BITMASK_O_IPV4_DST_ADDR } + .field_list = { + [1] = 1, + [52] = 2, + [54] = 3, + [56] = 4, + [58] = 5, + [60] = 6, + [62] = 7, + [64] = 8, + [66] = 9, + }, }, [9] = { - .class_hid = BNXT_ULP_CLASS_HID_81d25, + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x91B0000000000000, + .field_exclude_bitmap = 0x0, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 32768UL, .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_DST_ADDR } + .field_list = { + [1] = 1, + [32] = 2, + [34] = 3, + [36] = 4, + [38] = 5, + [40] = 6, + [42] = 7, + [44] = 8, + [46] = 9, + [48] = 10, + [50] = 11, + }, }, [10] = { - .class_hid = BNXT_ULP_CLASS_HID_809ad, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 32776UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = + .app_id = 0, + .hdr_bitmap = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_DST_ADDR } - }, - [11] = { - .class_hid = BNXT_ULP_CLASS_HID_80ae3, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBA78000000000000, + .field_exclude_bitmap = 0x2000000000000000, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 32832UL, .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [52] = 5, + [54] = 6, + [56] = 7, + [58] = 8, + [60] = 9, + [62] = 10, + [64] = 11, + [66] = 12, + }, + }, + [11] = { + .app_id = 0, + .hdr_bitmap = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_DST_ADDR } - }, - [12] = { - .class_hid = BNXT_ULP_CLASS_HID_8170d, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBA36000000000000, + .field_exclude_bitmap = 0x2000000000000000, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 32840UL, .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [32] = 5, + [34] = 6, + [36] = 7, + [38] = 8, + [40] = 9, + [42] = 10, + [44] = 11, + [46] = 12, + [48] = 13, + [50] = 14, + }, + }, + [12] = { + .app_id = 0, + .hdr_bitmap = { .bits = BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_DST_ADDR } - }, - [13] = { - .class_hid = BNXT_ULP_CLASS_HID_80773, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x9278000000000000, + .field_exclude_bitmap = 0x0, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 49152UL, .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | + .field_list = { + [1] = 1, + [52] = 5, + [54] = 6, + [56] = 7, + [58] = 8, + [60] = 9, + [62] = 10, + [64] = 11, + [66] = 12, + [108] = 2, + [112] = 3, + [116] = 4, + }, + }, + [13] = { + .app_id = 0, + .hdr_bitmap = { .bits = BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_DST_ADDR } - }, - [14] = { - .class_hid = BNXT_ULP_CLASS_HID_8139d, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x9236000000000000, + .field_exclude_bitmap = 0x0, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 49160UL, .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = + .field_list = { + [1] = 1, + [32] = 5, + [34] = 6, + [36] = 7, + [38] = 8, + [40] = 9, + [42] = 10, + [44] = 11, + [46] = 12, + [48] = 13, + [50] = 14, + [108] = 2, + [112] = 3, + [116] = 4, + }, + }, + [14] = { + .app_id = 0, + .hdr_bitmap = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_DST_ADDR } - }, - [15] = { - .class_hid = BNXT_ULP_CLASS_HID_814d3, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBA4F000000000000, + .field_exclude_bitmap = 0x2000000000000000, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 49216UL, .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [52] = 8, + [54] = 9, + [56] = 10, + [58] = 11, + [60] = 12, + [62] = 13, + [64] = 14, + [66] = 15, + [108] = 5, + [112] = 6, + [116] = 7, + }, + }, + [15] = { + .app_id = 0, + .hdr_bitmap = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_DST_ADDR } - }, - [16] = { - .class_hid = BNXT_ULP_CLASS_HID_8015b, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBA46C00000000000, + .field_exclude_bitmap = 0x2000000000000000, .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 49224UL, .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_DST_ADDR } + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [32] = 8, + [34] = 9, + [36] = 10, + [38] = 11, + [40] = 12, + [42] = 13, + [44] = 14, + [46] = 15, + [48] = 16, + [50] = 17, + [108] = 5, + [112] = 6, + [116] = 7, + }, + }, + [16] = { + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x9278000000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 1, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [52] = 5, + [54] = 6, + [56] = 7, + [58] = 8, + [60] = 9, + [62] = 10, + [64] = 11, + [66] = 12, + [109] = 2, + [113] = 3, + [117] = 4, + }, }, [17] = { - .class_hid = BNXT_ULP_CLASS_HID_21977, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 131072UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_DST_ADDR } + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x9236000000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 1, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [32] = 5, + [34] = 6, + [36] = 7, + [38] = 8, + [40] = 9, + [42] = 10, + [44] = 11, + [46] = 12, + [48] = 13, + [50] = 14, + [109] = 2, + [113] = 3, + [117] = 4, + }, }, [18] = { - .class_hid = BNXT_ULP_CLASS_HID_205ef, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 131080UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_DST_ADDR } + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBA4F000000000000, + .field_exclude_bitmap = 0x2000000000000000, + .class_tid = 1, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [52] = 8, + [54] = 9, + [56] = 10, + [58] = 11, + [60] = 12, + [62] = 13, + [64] = 14, + [66] = 15, + [109] = 5, + [113] = 6, + [117] = 7, + }, }, [19] = { - .class_hid = BNXT_ULP_CLASS_HID_20735, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 131136UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_DST_ADDR } + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBA46C00000000000, + .field_exclude_bitmap = 0x2000000000000000, + .class_tid = 1, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [32] = 8, + [34] = 9, + [36] = 10, + [38] = 11, + [40] = 12, + [42] = 13, + [44] = 14, + [46] = 15, + [48] = 16, + [50] = 17, + [109] = 5, + [113] = 6, + [117] = 7, + }, }, [20] = { - .class_hid = BNXT_ULP_CLASS_HID_2134f, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 131144UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_DST_ADDR } + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x924F000000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 1, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [52] = 8, + [54] = 9, + [56] = 10, + [58] = 11, + [60] = 12, + [62] = 13, + [64] = 14, + [66] = 15, + [108] = 2, + [109] = 5, + [112] = 3, + [113] = 6, + [116] = 4, + [117] = 7, + }, }, [21] = { - .class_hid = BNXT_ULP_CLASS_HID_61beb, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 196608UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_DST_ADDR } + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x9246C00000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 1, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [32] = 8, + [34] = 9, + [36] = 10, + [38] = 11, + [40] = 12, + [42] = 13, + [44] = 14, + [46] = 15, + [48] = 16, + [50] = 17, + [108] = 2, + [109] = 5, + [112] = 3, + [113] = 6, + [116] = 4, + [117] = 7, + }, }, [22] = { - .class_hid = BNXT_ULP_CLASS_HID_60863, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 196616UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_DST_ADDR } + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBA49E00000000000, + .field_exclude_bitmap = 0x2000000000000000, + .class_tid = 1, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [52] = 11, + [54] = 12, + [56] = 13, + [58] = 14, + [60] = 15, + [62] = 16, + [64] = 17, + [66] = 18, + [108] = 5, + [109] = 8, + [112] = 6, + [113] = 9, + [116] = 7, + [117] = 10, + }, }, [23] = { - .class_hid = BNXT_ULP_CLASS_HID_609a9, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 196672UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_DST_ADDR } + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBA48D80000000000, + .field_exclude_bitmap = 0x2000000000000000, + .class_tid = 1, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [32] = 11, + [34] = 12, + [36] = 13, + [38] = 14, + [40] = 15, + [42] = 16, + [44] = 17, + [46] = 18, + [48] = 19, + [50] = 20, + [108] = 5, + [109] = 8, + [112] = 6, + [113] = 9, + [116] = 7, + [117] = 10, + }, }, [24] = { - .class_hid = BNXT_ULP_CLASS_HID_615c3, + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xB000000000000000, + .field_exclude_bitmap = 0x0, .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 196680UL, .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_DST_ADDR } + .field_list = { + [1] = 1, + [82] = 2, + [84] = 3, + [86] = 4, + [88] = 5, + [90] = 6, + [92] = 7, + [94] = 8, + [96] = 9, + [98] = 10, + }, }, [25] = { - .class_hid = BNXT_ULP_CLASS_HID_00a8, + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xB000000000000000, + .field_exclude_bitmap = 0x0, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 4096UL, .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR } + .field_list = { + [1] = 1, + [100] = 2, + [102] = 3, + [104] = 4, + [106] = 5, + }, }, [26] = { - .class_hid = BNXT_ULP_CLASS_HID_0cd2, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 4104UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = + .app_id = 0, + .hdr_bitmap = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR } - }, - [27] = { - .class_hid = BNXT_ULP_CLASS_HID_10f4, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBE00000000000000, + .field_exclude_bitmap = 0x2000000000000000, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 6144UL, .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [82] = 5, + [84] = 6, + [86] = 7, + [88] = 8, + [90] = 9, + [92] = 10, + [94] = 11, + [96] = 12, + [98] = 13, + }, + }, + [27] = { + .app_id = 0, + .hdr_bitmap = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR } - }, - [28] = { - .class_hid = BNXT_ULP_CLASS_HID_1d1e, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBE00000000000000, + .field_exclude_bitmap = 0x2000000000000000, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 6152UL, .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [100] = 5, + [102] = 6, + [104] = 7, + [106] = 8, + }, + }, + [28] = { + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR } + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x9600000000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 1, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [82] = 5, + [84] = 6, + [86] = 7, + [88] = 8, + [90] = 9, + [92] = 10, + [94] = 11, + [96] = 12, + [98] = 13, + [108] = 2, + [112] = 3, + [116] = 4, + }, }, [29] = { - .class_hid = BNXT_ULP_CLASS_HID_1488, + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x9600000000000000, + .field_exclude_bitmap = 0x0, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 12288UL, .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_SRC_PORT } + .field_list = { + [1] = 1, + [100] = 5, + [102] = 6, + [104] = 7, + [106] = 8, + [108] = 2, + [112] = 3, + [116] = 4, + }, }, [30] = { - .class_hid = BNXT_ULP_CLASS_HID_0110, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 12296UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = + .app_id = 0, + .hdr_bitmap = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_SRC_PORT } - }, - [31] = { - .class_hid = BNXT_ULP_CLASS_HID_0532, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBAC0000000000000, + .field_exclude_bitmap = 0x2000000000000000, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 14336UL, .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [82] = 8, + [84] = 9, + [86] = 10, + [88] = 11, + [90] = 12, + [92] = 13, + [94] = 14, + [96] = 15, + [98] = 16, + [108] = 5, + [112] = 6, + [116] = 7, + }, + }, + [31] = { + .app_id = 0, + .hdr_bitmap = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_SRC_PORT } - }, - [32] = { - .class_hid = BNXT_ULP_CLASS_HID_115c, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBAC0000000000000, + .field_exclude_bitmap = 0x2000000000000000, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 14344UL, .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_SRC_PORT } + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [100] = 8, + [102] = 9, + [104] = 10, + [106] = 11, + [108] = 5, + [112] = 6, + [116] = 7, + }, + }, + [32] = { + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x9600000000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 1, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [82] = 5, + [84] = 6, + [86] = 7, + [88] = 8, + [90] = 9, + [92] = 10, + [94] = 11, + [96] = 12, + [98] = 13, + [109] = 2, + [113] = 3, + [117] = 4, + }, }, [33] = { - .class_hid = BNXT_ULP_CLASS_HID_0ab8, + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x9600000000000000, + .field_exclude_bitmap = 0x0, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 20480UL, .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DST_PORT } + .field_list = { + [1] = 1, + [100] = 5, + [102] = 6, + [104] = 7, + [106] = 8, + [109] = 2, + [113] = 3, + [117] = 4, + }, }, [34] = { - .class_hid = BNXT_ULP_CLASS_HID_16a2, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 20488UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DST_PORT } + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBAC0000000000000, + .field_exclude_bitmap = 0x2000000000000000, + .class_tid = 1, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [82] = 8, + [84] = 9, + [86] = 10, + [88] = 11, + [90] = 12, + [92] = 13, + [94] = 14, + [96] = 15, + [98] = 16, + [109] = 5, + [113] = 6, + [117] = 7, + }, }, [35] = { - .class_hid = BNXT_ULP_CLASS_HID_1ac4, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 22528UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = + .app_id = 0, + .hdr_bitmap = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DST_PORT } - }, - [36] = { - .class_hid = BNXT_ULP_CLASS_HID_074c, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBAC0000000000000, + .field_exclude_bitmap = 0x2000000000000000, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 22536UL, .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DST_PORT } + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [100] = 8, + [102] = 9, + [104] = 10, + [106] = 11, + [109] = 5, + [113] = 6, + [117] = 7, + }, + }, + [36] = { + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x92C0000000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 1, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [82] = 8, + [84] = 9, + [86] = 10, + [88] = 11, + [90] = 12, + [92] = 13, + [94] = 14, + [96] = 15, + [98] = 16, + [108] = 2, + [109] = 5, + [112] = 3, + [113] = 6, + [116] = 4, + [117] = 7, + }, }, [37] = { - .class_hid = BNXT_ULP_CLASS_HID_1e98, + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x92C0000000000000, + .field_exclude_bitmap = 0x0, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 28672UL, .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DST_PORT } + .field_list = { + [1] = 1, + [100] = 8, + [102] = 9, + [104] = 10, + [106] = 11, + [108] = 2, + [109] = 5, + [112] = 3, + [113] = 6, + [116] = 4, + [117] = 7, + }, }, [38] = { - .class_hid = BNXT_ULP_CLASS_HID_0ae0, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 28680UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DST_PORT } + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBA58000000000000, + .field_exclude_bitmap = 0x2000000000000000, + .class_tid = 1, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [82] = 11, + [84] = 12, + [86] = 13, + [88] = 14, + [90] = 15, + [92] = 16, + [94] = 17, + [96] = 18, + [98] = 19, + [108] = 5, + [109] = 8, + [112] = 6, + [113] = 9, + [116] = 7, + [117] = 10, + }, }, [39] = { - .class_hid = BNXT_ULP_CLASS_HID_0f02, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 30720UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = + .app_id = 0, + .hdr_bitmap = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DST_PORT } - }, - [40] = { - .class_hid = BNXT_ULP_CLASS_HID_1b2c, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBA58000000000000, + .field_exclude_bitmap = 0x2000000000000000, .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 30728UL, .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DST_PORT } + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [100] = 11, + [102] = 12, + [104] = 13, + [106] = 14, + [108] = 5, + [109] = 8, + [112] = 6, + [113] = 9, + [116] = 7, + [117] = 10, + }, + }, + [40] = { + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x93F0000000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 1, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [52] = 2, + [54] = 3, + [56] = 4, + [58] = 5, + [60] = 6, + [62] = 7, + [64] = 8, + [66] = 9, + [82] = 10, + [84] = 11, + [86] = 12, + [88] = 13, + [90] = 14, + [92] = 15, + [94] = 16, + [96] = 17, + [98] = 18, + }, }, [41] = { - .class_hid = BNXT_ULP_CLASS_HID_0296, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 16384UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR } + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x91BC000000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 1, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [32] = 2, + [34] = 3, + [36] = 4, + [38] = 5, + [40] = 6, + [42] = 7, + [44] = 8, + [46] = 9, + [48] = 10, + [50] = 11, + [82] = 12, + [84] = 13, + [86] = 14, + [88] = 15, + [90] = 16, + [92] = 17, + [94] = 18, + [96] = 19, + [98] = 20, + }, }, [42] = { - .class_hid = BNXT_ULP_CLASS_HID_0e88, + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x93F0000000000000, + .field_exclude_bitmap = 0x0, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 16392UL, .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR } + .field_list = { + [1] = 1, + [52] = 2, + [54] = 3, + [56] = 4, + [58] = 5, + [60] = 6, + [62] = 7, + [64] = 8, + [66] = 9, + [100] = 10, + [102] = 11, + [104] = 12, + [106] = 13, + }, }, [43] = { - .class_hid = BNXT_ULP_CLASS_HID_1676, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 24576UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR } + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x91BC000000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 1, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [32] = 2, + [34] = 3, + [36] = 4, + [38] = 5, + [40] = 6, + [42] = 7, + [44] = 8, + [46] = 9, + [48] = 10, + [50] = 11, + [100] = 12, + [102] = 13, + [104] = 14, + [106] = 15, + }, }, [44] = { - .class_hid = BNXT_ULP_CLASS_HID_02ce, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 24584UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR } + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBA7E000000000000, + .field_exclude_bitmap = 0x2000000000000000, + .class_tid = 1, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [52] = 5, + [54] = 6, + [56] = 7, + [58] = 8, + [60] = 9, + [62] = 10, + [64] = 11, + [66] = 12, + [82] = 13, + [84] = 14, + [86] = 15, + [88] = 16, + [90] = 17, + [92] = 18, + [94] = 19, + [96] = 20, + [98] = 21, + }, }, [45] = { - .class_hid = BNXT_ULP_CLASS_HID_8076e, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 49152UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_SRC_PORT } + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBA37800000000000, + .field_exclude_bitmap = 0x2000000000000000, + .class_tid = 1, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [32] = 5, + [34] = 6, + [36] = 7, + [38] = 8, + [40] = 9, + [42] = 10, + [44] = 11, + [46] = 12, + [48] = 13, + [50] = 14, + [82] = 15, + [84] = 16, + [86] = 17, + [88] = 18, + [90] = 19, + [92] = 20, + [94] = 21, + [96] = 22, + [98] = 23, + }, }, [46] = { - .class_hid = BNXT_ULP_CLASS_HID_81380, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 49160UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = + .app_id = 0, + .hdr_bitmap = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_SRC_PORT } - }, - [47] = { - .class_hid = BNXT_ULP_CLASS_HID_81b4e, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBA7E000000000000, + .field_exclude_bitmap = 0x2000000000000000, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 57344UL, .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_SRC_PORT } + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [52] = 5, + [54] = 6, + [56] = 7, + [58] = 8, + [60] = 9, + [62] = 10, + [64] = 11, + [66] = 12, + [100] = 13, + [102] = 14, + [104] = 15, + [106] = 16, + }, + }, + [47] = { + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBA37800000000000, + .field_exclude_bitmap = 0x2000000000000000, + .class_tid = 1, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [32] = 5, + [34] = 6, + [36] = 7, + [38] = 8, + [40] = 9, + [42] = 10, + [44] = 11, + [46] = 12, + [48] = 13, + [50] = 14, + [100] = 15, + [102] = 16, + [104] = 17, + [106] = 18, + }, }, [48] = { - .class_hid = BNXT_ULP_CLASS_HID_807c6, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 57352UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_SRC_PORT } + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x927E000000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 1, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [52] = 5, + [54] = 6, + [56] = 7, + [58] = 8, + [60] = 9, + [62] = 10, + [64] = 11, + [66] = 12, + [82] = 13, + [84] = 14, + [86] = 15, + [88] = 16, + [90] = 17, + [92] = 18, + [94] = 19, + [96] = 20, + [98] = 21, + [108] = 2, + [112] = 3, + [116] = 4, + }, }, [49] = { - .class_hid = BNXT_ULP_CLASS_HID_404ea, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 81920UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DST_PORT } + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x9237800000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 1, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [32] = 5, + [34] = 6, + [36] = 7, + [38] = 8, + [40] = 9, + [42] = 10, + [44] = 11, + [46] = 12, + [48] = 13, + [50] = 14, + [82] = 15, + [84] = 16, + [86] = 17, + [88] = 18, + [90] = 19, + [92] = 20, + [94] = 21, + [96] = 22, + [98] = 23, + [108] = 2, + [112] = 3, + [116] = 4, + }, }, [50] = { - .class_hid = BNXT_ULP_CLASS_HID_4110c, + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x927E000000000000, + .field_exclude_bitmap = 0x0, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 81928UL, .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DST_PORT } + .field_list = { + [1] = 1, + [52] = 5, + [54] = 6, + [56] = 7, + [58] = 8, + [60] = 9, + [62] = 10, + [64] = 11, + [66] = 12, + [100] = 13, + [102] = 14, + [104] = 15, + [106] = 16, + [108] = 2, + [112] = 3, + [116] = 4, + }, }, [51] = { - .class_hid = BNXT_ULP_CLASS_HID_418ca, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 90112UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DST_PORT } + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x9237800000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 1, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [32] = 5, + [34] = 6, + [36] = 7, + [38] = 8, + [40] = 9, + [42] = 10, + [44] = 11, + [46] = 12, + [48] = 13, + [50] = 14, + [100] = 15, + [102] = 16, + [104] = 17, + [106] = 18, + [108] = 2, + [112] = 3, + [116] = 4, + }, }, [52] = { - .class_hid = BNXT_ULP_CLASS_HID_40542, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 90120UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DST_PORT } + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBA4FC00000000000, + .field_exclude_bitmap = 0x2000000000000000, + .class_tid = 1, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [52] = 8, + [54] = 9, + [56] = 10, + [58] = 11, + [60] = 12, + [62] = 13, + [64] = 14, + [66] = 15, + [82] = 16, + [84] = 17, + [86] = 18, + [88] = 19, + [90] = 20, + [92] = 21, + [94] = 22, + [96] = 23, + [98] = 24, + [108] = 5, + [112] = 6, + [116] = 7, + }, }, [53] = { - .class_hid = BNXT_ULP_CLASS_HID_c09e2, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 114688UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DST_PORT } + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBA46F00000000000, + .field_exclude_bitmap = 0x2000000000000000, + .class_tid = 1, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [32] = 8, + [34] = 9, + [36] = 10, + [38] = 11, + [40] = 12, + [42] = 13, + [44] = 14, + [46] = 15, + [48] = 16, + [50] = 17, + [82] = 18, + [84] = 19, + [86] = 20, + [88] = 21, + [90] = 22, + [92] = 23, + [94] = 24, + [96] = 25, + [98] = 26, + [108] = 5, + [112] = 6, + [116] = 7, + }, }, [54] = { - .class_hid = BNXT_ULP_CLASS_HID_c1604, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 114696UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = + .app_id = 0, + .hdr_bitmap = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DST_PORT } - }, - [55] = { - .class_hid = BNXT_ULP_CLASS_HID_c1dc2, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBA4FC00000000000, + .field_exclude_bitmap = 0x2000000000000000, .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 122880UL, .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DST_PORT } + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [52] = 8, + [54] = 9, + [56] = 10, + [58] = 11, + [60] = 12, + [62] = 13, + [64] = 14, + [66] = 15, + [100] = 16, + [102] = 17, + [104] = 18, + [106] = 19, + [108] = 5, + [112] = 6, + [116] = 7, + }, + }, + [55] = { + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBA46F00000000000, + .field_exclude_bitmap = 0x2000000000000000, + .class_tid = 1, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [32] = 8, + [34] = 9, + [36] = 10, + [38] = 11, + [40] = 12, + [42] = 13, + [44] = 14, + [46] = 15, + [48] = 16, + [50] = 17, + [100] = 18, + [102] = 19, + [104] = 20, + [106] = 21, + [108] = 5, + [112] = 6, + [116] = 7, + }, }, [56] = { - .class_hid = BNXT_ULP_CLASS_HID_c0a5a, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 122888UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DST_PORT } + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x927E000000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 1, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [52] = 5, + [54] = 6, + [56] = 7, + [58] = 8, + [60] = 9, + [62] = 10, + [64] = 11, + [66] = 12, + [82] = 13, + [84] = 14, + [86] = 15, + [88] = 16, + [90] = 17, + [92] = 18, + [94] = 19, + [96] = 20, + [98] = 21, + [109] = 2, + [113] = 3, + [117] = 4, + }, }, [57] = { - .class_hid = BNXT_ULP_CLASS_HID_0098, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 4096UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR } + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x9237800000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 1, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [32] = 5, + [34] = 6, + [36] = 7, + [38] = 8, + [40] = 9, + [42] = 10, + [44] = 11, + [46] = 12, + [48] = 13, + [50] = 14, + [82] = 15, + [84] = 16, + [86] = 17, + [88] = 18, + [90] = 19, + [92] = 20, + [94] = 21, + [96] = 22, + [98] = 23, + [109] = 2, + [113] = 3, + [117] = 4, + }, }, [58] = { - .class_hid = BNXT_ULP_CLASS_HID_0ce2, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 4104UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR } + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x927E000000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 1, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [52] = 5, + [54] = 6, + [56] = 7, + [58] = 8, + [60] = 9, + [62] = 10, + [64] = 11, + [66] = 12, + [100] = 13, + [102] = 14, + [104] = 15, + [106] = 16, + [109] = 2, + [113] = 3, + [117] = 4, + }, }, [59] = { - .class_hid = BNXT_ULP_CLASS_HID_10c4, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 6144UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR } + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x9237800000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 1, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [32] = 5, + [34] = 6, + [36] = 7, + [38] = 8, + [40] = 9, + [42] = 10, + [44] = 11, + [46] = 12, + [48] = 13, + [50] = 14, + [100] = 15, + [102] = 16, + [104] = 17, + [106] = 18, + [109] = 2, + [113] = 3, + [117] = 4, + }, }, [60] = { - .class_hid = BNXT_ULP_CLASS_HID_1d2e, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 6152UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR } + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBA4FC00000000000, + .field_exclude_bitmap = 0x2000000000000000, + .class_tid = 1, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [52] = 8, + [54] = 9, + [56] = 10, + [58] = 11, + [60] = 12, + [62] = 13, + [64] = 14, + [66] = 15, + [82] = 16, + [84] = 17, + [86] = 18, + [88] = 19, + [90] = 20, + [92] = 21, + [94] = 22, + [96] = 23, + [98] = 24, + [109] = 5, + [113] = 6, + [117] = 7, + }, }, [61] = { - .class_hid = BNXT_ULP_CLASS_HID_14b8, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 12288UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_SRC_PORT } + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBA46F00000000000, + .field_exclude_bitmap = 0x2000000000000000, + .class_tid = 1, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [32] = 8, + [34] = 9, + [36] = 10, + [38] = 11, + [40] = 12, + [42] = 13, + [44] = 14, + [46] = 15, + [48] = 16, + [50] = 17, + [82] = 18, + [84] = 19, + [86] = 20, + [88] = 21, + [90] = 22, + [92] = 23, + [94] = 24, + [96] = 25, + [98] = 26, + [109] = 5, + [113] = 6, + [117] = 7, + }, }, [62] = { - .class_hid = BNXT_ULP_CLASS_HID_0120, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 12296UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_SRC_PORT } + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBA4FC00000000000, + .field_exclude_bitmap = 0x2000000000000000, + .class_tid = 1, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [52] = 8, + [54] = 9, + [56] = 10, + [58] = 11, + [60] = 12, + [62] = 13, + [64] = 14, + [66] = 15, + [100] = 16, + [102] = 17, + [104] = 18, + [106] = 19, + [109] = 5, + [113] = 6, + [117] = 7, + }, }, [63] = { - .class_hid = BNXT_ULP_CLASS_HID_0502, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 14336UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_SRC_PORT } + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBA46F00000000000, + .field_exclude_bitmap = 0x2000000000000000, + .class_tid = 1, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [32] = 8, + [34] = 9, + [36] = 10, + [38] = 11, + [40] = 12, + [42] = 13, + [44] = 14, + [46] = 15, + [48] = 16, + [50] = 17, + [100] = 18, + [102] = 19, + [104] = 20, + [106] = 21, + [109] = 5, + [113] = 6, + [117] = 7, + }, }, [64] = { - .class_hid = BNXT_ULP_CLASS_HID_116c, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 14344UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_SRC_PORT } + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x924FC00000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 1, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [52] = 8, + [54] = 9, + [56] = 10, + [58] = 11, + [60] = 12, + [62] = 13, + [64] = 14, + [66] = 15, + [82] = 16, + [84] = 17, + [86] = 18, + [88] = 19, + [90] = 20, + [92] = 21, + [94] = 22, + [96] = 23, + [98] = 24, + [108] = 2, + [109] = 5, + [112] = 3, + [113] = 6, + [116] = 4, + [117] = 7, + }, }, [65] = { - .class_hid = BNXT_ULP_CLASS_HID_0a88, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 20480UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_DST_PORT } + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x9246F00000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 1, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [32] = 8, + [34] = 9, + [36] = 10, + [38] = 11, + [40] = 12, + [42] = 13, + [44] = 14, + [46] = 15, + [48] = 16, + [50] = 17, + [82] = 18, + [84] = 19, + [86] = 20, + [88] = 21, + [90] = 22, + [92] = 23, + [94] = 24, + [96] = 25, + [98] = 26, + [108] = 2, + [109] = 5, + [112] = 3, + [113] = 6, + [116] = 4, + [117] = 7, + }, }, [66] = { - .class_hid = BNXT_ULP_CLASS_HID_1692, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 20488UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_DST_PORT } + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x924FC00000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 1, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [52] = 8, + [54] = 9, + [56] = 10, + [58] = 11, + [60] = 12, + [62] = 13, + [64] = 14, + [66] = 15, + [100] = 16, + [102] = 17, + [104] = 18, + [106] = 19, + [108] = 2, + [109] = 5, + [112] = 3, + [113] = 6, + [116] = 4, + [117] = 7, + }, }, [67] = { - .class_hid = BNXT_ULP_CLASS_HID_1af4, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 22528UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_DST_PORT } + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x9246F00000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 1, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [32] = 8, + [34] = 9, + [36] = 10, + [38] = 11, + [40] = 12, + [42] = 13, + [44] = 14, + [46] = 15, + [48] = 16, + [50] = 17, + [100] = 18, + [102] = 19, + [104] = 20, + [106] = 21, + [108] = 2, + [109] = 5, + [112] = 3, + [113] = 6, + [116] = 4, + [117] = 7, + }, }, [68] = { - .class_hid = BNXT_ULP_CLASS_HID_077c, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 22536UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_DST_PORT } + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBA49F80000000000, + .field_exclude_bitmap = 0x2000000000000000, + .class_tid = 1, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [52] = 11, + [54] = 12, + [56] = 13, + [58] = 14, + [60] = 15, + [62] = 16, + [64] = 17, + [66] = 18, + [82] = 19, + [84] = 20, + [86] = 21, + [88] = 22, + [90] = 23, + [92] = 24, + [94] = 25, + [96] = 26, + [98] = 27, + [108] = 5, + [109] = 8, + [112] = 6, + [113] = 9, + [116] = 7, + [117] = 10, + }, }, [69] = { - .class_hid = BNXT_ULP_CLASS_HID_1ea8, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 28672UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_DST_PORT } + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBA48DE0000000000, + .field_exclude_bitmap = 0x2000000000000000, + .class_tid = 1, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [32] = 11, + [34] = 12, + [36] = 13, + [38] = 14, + [40] = 15, + [42] = 16, + [44] = 17, + [46] = 18, + [48] = 19, + [50] = 20, + [82] = 21, + [84] = 22, + [86] = 23, + [88] = 24, + [90] = 25, + [92] = 26, + [94] = 27, + [96] = 28, + [98] = 29, + [108] = 5, + [109] = 8, + [112] = 6, + [113] = 9, + [116] = 7, + [117] = 10, + }, }, [70] = { - .class_hid = BNXT_ULP_CLASS_HID_0ad0, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 28680UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_DST_PORT } + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBA49F80000000000, + .field_exclude_bitmap = 0x2000000000000000, + .class_tid = 1, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [52] = 11, + [54] = 12, + [56] = 13, + [58] = 14, + [60] = 15, + [62] = 16, + [64] = 17, + [66] = 18, + [100] = 19, + [102] = 20, + [104] = 21, + [106] = 22, + [108] = 5, + [109] = 8, + [112] = 6, + [113] = 9, + [116] = 7, + [117] = 10, + }, }, [71] = { - .class_hid = BNXT_ULP_CLASS_HID_0f32, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 30720UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_DST_PORT } + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBA48DE0000000000, + .field_exclude_bitmap = 0x2000000000000000, + .class_tid = 1, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [32] = 11, + [34] = 12, + [36] = 13, + [38] = 14, + [40] = 15, + [42] = 16, + [44] = 17, + [46] = 18, + [48] = 19, + [50] = 20, + [100] = 21, + [102] = 22, + [104] = 23, + [106] = 24, + [108] = 5, + [109] = 8, + [112] = 6, + [113] = 9, + [116] = 7, + [117] = 10, + }, }, [72] = { - .class_hid = BNXT_ULP_CLASS_HID_1b1c, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 30728UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = + .app_id = 0, + .hdr_bitmap = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_DST_PORT } + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xB01A160000000000, + .field_exclude_bitmap = 0x2000000000000000, + .class_tid = 1, + .flow_pattern_id = 1, + .field_list = { + [1] = 1, + [6] = 2, + [7] = 21, + [8] = 3, + [9] = 22, + [10] = 4, + [11] = 23, + [52] = 5, + [54] = 6, + [56] = 7, + [58] = 8, + [60] = 9, + [62] = 10, + [64] = 11, + [66] = 12, + [100] = 13, + [102] = 14, + [104] = 15, + [106] = 16, + [120] = 17, + [121] = 18, + [122] = 19, + [123] = 20, + }, }, [73] = { - .class_hid = BNXT_ULP_CLASS_HID_02a6, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 16384UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR } + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xB006858000000000, + .field_exclude_bitmap = 0x2000000000000000, + .class_tid = 1, + .flow_pattern_id = 1, + .field_list = { + [1] = 1, + [6] = 2, + [7] = 23, + [8] = 3, + [9] = 24, + [10] = 4, + [11] = 25, + [32] = 5, + [34] = 6, + [36] = 7, + [38] = 8, + [40] = 9, + [42] = 10, + [44] = 11, + [46] = 12, + [48] = 13, + [50] = 14, + [100] = 15, + [102] = 16, + [104] = 17, + [106] = 18, + [120] = 19, + [121] = 20, + [122] = 21, + [123] = 22, + }, }, [74] = { - .class_hid = BNXT_ULP_CLASS_HID_0eb8, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 16392UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR } + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xB01A160300000000, + .field_exclude_bitmap = 0x2000000000000000, + .class_tid = 1, + .flow_pattern_id = 1, + .field_list = { + [1] = 1, + [6] = 2, + [7] = 21, + [8] = 3, + [9] = 22, + [10] = 4, + [11] = 23, + [52] = 5, + [53] = 24, + [54] = 6, + [55] = 25, + [56] = 7, + [57] = 26, + [58] = 8, + [59] = 27, + [60] = 9, + [61] = 28, + [62] = 10, + [63] = 29, + [64] = 11, + [65] = 30, + [66] = 12, + [67] = 31, + [100] = 13, + [102] = 14, + [104] = 15, + [106] = 16, + [120] = 17, + [121] = 18, + [122] = 19, + [123] = 20, + }, }, [75] = { - .class_hid = BNXT_ULP_CLASS_HID_1646, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 24576UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR } + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xB0068580C0000000, + .field_exclude_bitmap = 0x2000000000000000, + .class_tid = 1, + .flow_pattern_id = 1, + .field_list = { + [1] = 1, + [6] = 2, + [7] = 23, + [8] = 3, + [9] = 24, + [10] = 4, + [11] = 25, + [32] = 5, + [34] = 6, + [36] = 7, + [38] = 8, + [40] = 9, + [42] = 10, + [44] = 11, + [46] = 12, + [48] = 13, + [50] = 14, + [53] = 26, + [55] = 27, + [57] = 28, + [59] = 29, + [61] = 30, + [63] = 31, + [65] = 32, + [67] = 33, + [100] = 15, + [102] = 16, + [104] = 17, + [106] = 18, + [120] = 19, + [121] = 20, + [122] = 21, + [123] = 22, + }, }, [76] = { - .class_hid = BNXT_ULP_CLASS_HID_02fe, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 24584UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR } + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xB01A1600C0000000, + .field_exclude_bitmap = 0x2000000000000000, + .class_tid = 1, + .flow_pattern_id = 1, + .field_list = { + [1] = 1, + [6] = 2, + [7] = 21, + [8] = 3, + [9] = 22, + [10] = 4, + [11] = 23, + [33] = 24, + [35] = 25, + [37] = 26, + [39] = 27, + [41] = 28, + [43] = 29, + [45] = 30, + [47] = 31, + [49] = 32, + [51] = 33, + [52] = 5, + [54] = 6, + [56] = 7, + [58] = 8, + [60] = 9, + [62] = 10, + [64] = 11, + [66] = 12, + [100] = 13, + [102] = 14, + [104] = 15, + [106] = 16, + [120] = 17, + [121] = 18, + [122] = 19, + [123] = 20, + }, }, [77] = { - .class_hid = BNXT_ULP_CLASS_HID_8075e, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 49152UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_SRC_PORT } + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xB006858030000000, + .field_exclude_bitmap = 0x2000000000000000, + .class_tid = 1, + .flow_pattern_id = 1, + .field_list = { + [1] = 1, + [6] = 2, + [7] = 23, + [8] = 3, + [9] = 24, + [10] = 4, + [11] = 25, + [32] = 5, + [33] = 26, + [34] = 6, + [35] = 27, + [36] = 7, + [37] = 28, + [38] = 8, + [39] = 29, + [40] = 9, + [41] = 30, + [42] = 10, + [43] = 31, + [44] = 11, + [45] = 32, + [46] = 12, + [47] = 33, + [48] = 13, + [49] = 34, + [50] = 14, + [51] = 35, + [100] = 15, + [102] = 16, + [104] = 17, + [106] = 18, + [120] = 19, + [121] = 20, + [122] = 21, + [123] = 22, + }, }, [78] = { - .class_hid = BNXT_ULP_CLASS_HID_813b0, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 49160UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_SRC_PORT } + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xB01A16C000000000, + .field_exclude_bitmap = 0x2000000000000000, + .class_tid = 1, + .flow_pattern_id = 1, + .field_list = { + [1] = 1, + [6] = 2, + [7] = 21, + [8] = 3, + [9] = 22, + [10] = 4, + [11] = 23, + [52] = 5, + [54] = 6, + [56] = 7, + [58] = 8, + [60] = 9, + [62] = 10, + [64] = 11, + [66] = 12, + [83] = 24, + [85] = 25, + [87] = 26, + [89] = 27, + [91] = 28, + [93] = 29, + [95] = 30, + [97] = 31, + [99] = 32, + [100] = 13, + [102] = 14, + [104] = 15, + [106] = 16, + [120] = 17, + [121] = 18, + [122] = 19, + [123] = 20, + }, }, [79] = { - .class_hid = BNXT_ULP_CLASS_HID_81b7e, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 57344UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_SRC_PORT } + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xB00685B000000000, + .field_exclude_bitmap = 0x2000000000000000, + .class_tid = 1, + .flow_pattern_id = 1, + .field_list = { + [1] = 1, + [6] = 2, + [7] = 23, + [8] = 3, + [9] = 24, + [10] = 4, + [11] = 25, + [32] = 5, + [34] = 6, + [36] = 7, + [38] = 8, + [40] = 9, + [42] = 10, + [44] = 11, + [46] = 12, + [48] = 13, + [50] = 14, + [83] = 26, + [85] = 27, + [87] = 28, + [89] = 29, + [91] = 30, + [93] = 31, + [95] = 32, + [97] = 33, + [99] = 34, + [100] = 15, + [102] = 16, + [104] = 17, + [106] = 18, + [120] = 19, + [121] = 20, + [122] = 21, + [123] = 22, + }, }, [80] = { - .class_hid = BNXT_ULP_CLASS_HID_807f6, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 57352UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_SRC_PORT } + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xB01A16C000000000, + .field_exclude_bitmap = 0x2000000000000000, + .class_tid = 1, + .flow_pattern_id = 1, + .field_list = { + [1] = 1, + [6] = 2, + [7] = 21, + [8] = 3, + [9] = 22, + [10] = 4, + [11] = 23, + [52] = 5, + [54] = 6, + [56] = 7, + [58] = 8, + [60] = 9, + [62] = 10, + [64] = 11, + [66] = 12, + [100] = 13, + [101] = 24, + [102] = 14, + [103] = 25, + [104] = 15, + [105] = 26, + [106] = 16, + [107] = 27, + [120] = 17, + [121] = 18, + [122] = 19, + [123] = 20, + }, }, [81] = { - .class_hid = BNXT_ULP_CLASS_HID_404da, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 81920UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_DST_PORT } + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xB00685B000000000, + .field_exclude_bitmap = 0x2000000000000000, + .class_tid = 1, + .flow_pattern_id = 1, + .field_list = { + [1] = 1, + [6] = 2, + [7] = 23, + [8] = 3, + [9] = 24, + [10] = 4, + [11] = 25, + [32] = 5, + [34] = 6, + [36] = 7, + [38] = 8, + [40] = 9, + [42] = 10, + [44] = 11, + [46] = 12, + [48] = 13, + [50] = 14, + [100] = 15, + [101] = 26, + [102] = 16, + [103] = 27, + [104] = 17, + [105] = 28, + [106] = 18, + [107] = 29, + [120] = 19, + [121] = 20, + [122] = 21, + [123] = 22, + }, }, [82] = { - .class_hid = BNXT_ULP_CLASS_HID_4113c, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 81928UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_DST_PORT } + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV6 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xB01A1603C0000000, + .field_exclude_bitmap = 0x2000000000000000, + .class_tid = 1, + .flow_pattern_id = 1, + .field_list = { + [1] = 1, + [6] = 2, + [7] = 21, + [8] = 3, + [9] = 22, + [10] = 4, + [11] = 23, + [52] = 5, + [53] = 24, + [54] = 6, + [55] = 25, + [56] = 7, + [57] = 26, + [58] = 8, + [59] = 27, + [60] = 9, + [61] = 28, + [62] = 10, + [63] = 29, + [64] = 11, + [65] = 30, + [66] = 12, + [67] = 31, + [83] = 32, + [85] = 33, + [87] = 34, + [89] = 35, + [91] = 36, + [93] = 37, + [95] = 38, + [97] = 39, + [99] = 40, + [100] = 13, + [102] = 14, + [104] = 15, + [106] = 16, + [120] = 17, + [121] = 18, + [122] = 19, + [123] = 20, + }, }, [83] = { - .class_hid = BNXT_ULP_CLASS_HID_418fa, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 90112UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_DST_PORT } + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV6 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xB0068580F0000000, + .field_exclude_bitmap = 0x2000000000000000, + .class_tid = 1, + .flow_pattern_id = 1, + .field_list = { + [1] = 1, + [6] = 2, + [7] = 23, + [8] = 3, + [9] = 24, + [10] = 4, + [11] = 25, + [32] = 5, + [34] = 6, + [36] = 7, + [38] = 8, + [40] = 9, + [42] = 10, + [44] = 11, + [46] = 12, + [48] = 13, + [50] = 14, + [53] = 26, + [55] = 27, + [57] = 28, + [59] = 29, + [61] = 30, + [63] = 31, + [65] = 32, + [67] = 33, + [83] = 34, + [85] = 35, + [87] = 36, + [89] = 37, + [91] = 38, + [93] = 39, + [95] = 40, + [97] = 41, + [99] = 42, + [100] = 15, + [102] = 16, + [104] = 17, + [106] = 18, + [120] = 19, + [121] = 20, + [122] = 21, + [123] = 22, + }, }, [84] = { - .class_hid = BNXT_ULP_CLASS_HID_40572, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 90120UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_DST_PORT } + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xB01A1600F0000000, + .field_exclude_bitmap = 0x2000000000000000, + .class_tid = 1, + .flow_pattern_id = 1, + .field_list = { + [1] = 1, + [6] = 2, + [7] = 21, + [8] = 3, + [9] = 22, + [10] = 4, + [11] = 23, + [33] = 24, + [35] = 25, + [37] = 26, + [39] = 27, + [41] = 28, + [43] = 29, + [45] = 30, + [47] = 31, + [49] = 32, + [51] = 33, + [52] = 5, + [54] = 6, + [56] = 7, + [58] = 8, + [60] = 9, + [62] = 10, + [64] = 11, + [66] = 12, + [83] = 34, + [85] = 35, + [87] = 36, + [89] = 37, + [91] = 38, + [93] = 39, + [95] = 40, + [97] = 41, + [99] = 42, + [100] = 13, + [102] = 14, + [104] = 15, + [106] = 16, + [120] = 17, + [121] = 18, + [122] = 19, + [123] = 20, + }, }, [85] = { - .class_hid = BNXT_ULP_CLASS_HID_c09d2, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 114688UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_DST_PORT } + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xB00685803C000000, + .field_exclude_bitmap = 0x2000000000000000, + .class_tid = 1, + .flow_pattern_id = 1, + .field_list = { + [1] = 1, + [6] = 2, + [7] = 23, + [8] = 3, + [9] = 24, + [10] = 4, + [11] = 25, + [32] = 5, + [33] = 26, + [34] = 6, + [35] = 27, + [36] = 7, + [37] = 28, + [38] = 8, + [39] = 29, + [40] = 9, + [41] = 30, + [42] = 10, + [43] = 31, + [44] = 11, + [45] = 32, + [46] = 12, + [47] = 33, + [48] = 13, + [49] = 34, + [50] = 14, + [51] = 35, + [83] = 36, + [85] = 37, + [87] = 38, + [89] = 39, + [91] = 40, + [93] = 41, + [95] = 42, + [97] = 43, + [99] = 44, + [100] = 15, + [102] = 16, + [104] = 17, + [106] = 18, + [120] = 19, + [121] = 20, + [122] = 21, + [123] = 22, + }, }, [86] = { - .class_hid = BNXT_ULP_CLASS_HID_c1634, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 114696UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_DST_PORT } + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV6 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xB01A1603C0000000, + .field_exclude_bitmap = 0x2000000000000000, + .class_tid = 1, + .flow_pattern_id = 1, + .field_list = { + [1] = 1, + [6] = 2, + [7] = 21, + [8] = 3, + [9] = 22, + [10] = 4, + [11] = 23, + [52] = 5, + [53] = 24, + [54] = 6, + [55] = 25, + [56] = 7, + [57] = 26, + [58] = 8, + [59] = 27, + [60] = 9, + [61] = 28, + [62] = 10, + [63] = 29, + [64] = 11, + [65] = 30, + [66] = 12, + [67] = 31, + [100] = 13, + [101] = 32, + [102] = 14, + [103] = 33, + [104] = 15, + [105] = 34, + [106] = 16, + [107] = 35, + [120] = 17, + [121] = 18, + [122] = 19, + [123] = 20, + }, }, [87] = { - .class_hid = BNXT_ULP_CLASS_HID_c1df2, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 122880UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_DST_PORT } + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV6 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xB0068580F0000000, + .field_exclude_bitmap = 0x2000000000000000, + .class_tid = 1, + .flow_pattern_id = 1, + .field_list = { + [1] = 1, + [6] = 2, + [7] = 23, + [8] = 3, + [9] = 24, + [10] = 4, + [11] = 25, + [32] = 5, + [34] = 6, + [36] = 7, + [38] = 8, + [40] = 9, + [42] = 10, + [44] = 11, + [46] = 12, + [48] = 13, + [50] = 14, + [53] = 26, + [55] = 27, + [57] = 28, + [59] = 29, + [61] = 30, + [63] = 31, + [65] = 32, + [67] = 33, + [100] = 15, + [101] = 34, + [102] = 16, + [103] = 35, + [104] = 17, + [105] = 36, + [106] = 18, + [107] = 37, + [120] = 19, + [121] = 20, + [122] = 21, + [123] = 22, + }, }, [88] = { - .class_hid = BNXT_ULP_CLASS_HID_c0a6a, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 122888UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_DST_PORT } + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xB01A1600F0000000, + .field_exclude_bitmap = 0x2000000000000000, + .class_tid = 1, + .flow_pattern_id = 1, + .field_list = { + [1] = 1, + [6] = 2, + [7] = 21, + [8] = 3, + [9] = 22, + [10] = 4, + [11] = 23, + [33] = 24, + [35] = 25, + [37] = 26, + [39] = 27, + [41] = 28, + [43] = 29, + [45] = 30, + [47] = 31, + [49] = 32, + [51] = 33, + [52] = 5, + [54] = 6, + [56] = 7, + [58] = 8, + [60] = 9, + [62] = 10, + [64] = 11, + [66] = 12, + [100] = 13, + [101] = 34, + [102] = 14, + [103] = 35, + [104] = 15, + [105] = 36, + [106] = 16, + [107] = 37, + [120] = 17, + [121] = 18, + [122] = 19, + [123] = 20, + }, }, [89] = { - .class_hid = BNXT_ULP_CLASS_HID_81d35, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 32768UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR } + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xB00685803C000000, + .field_exclude_bitmap = 0x2000000000000000, + .class_tid = 1, + .flow_pattern_id = 1, + .field_list = { + [1] = 1, + [6] = 2, + [7] = 23, + [8] = 3, + [9] = 24, + [10] = 4, + [11] = 25, + [32] = 5, + [33] = 26, + [34] = 6, + [35] = 27, + [36] = 7, + [37] = 28, + [38] = 8, + [39] = 29, + [40] = 9, + [41] = 30, + [42] = 10, + [43] = 31, + [44] = 11, + [45] = 32, + [46] = 12, + [47] = 33, + [48] = 13, + [49] = 34, + [50] = 14, + [51] = 35, + [100] = 15, + [101] = 36, + [102] = 16, + [103] = 37, + [104] = 17, + [105] = 38, + [106] = 18, + [107] = 39, + [120] = 19, + [121] = 20, + [122] = 21, + [123] = 22, + }, }, [90] = { - .class_hid = BNXT_ULP_CLASS_HID_809bd, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 32776UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_F1 | BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR } + .field_man_bitmap = 0x200A000000000000, + .field_opt_bitmap = 0x9000000000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 1, + .flow_pattern_id = 2, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [52] = 5, + [54] = 6, + [56] = 7, + [58] = 8, + [60] = 9, + [62] = 10, + [64] = 11, + [66] = 12, + [100] = 13, + [102] = 14, + [104] = 15, + [106] = 16, + [120] = 17, + [121] = 18, + [122] = 19, + [123] = 20, + }, }, [91] = { - .class_hid = BNXT_ULP_CLASS_HID_80af3, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 32832UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_F1 | BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR } + .field_man_bitmap = 0x2002800000000000, + .field_opt_bitmap = 0x9000000000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 1, + .flow_pattern_id = 2, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [32] = 5, + [34] = 6, + [36] = 7, + [38] = 8, + [40] = 9, + [42] = 10, + [44] = 11, + [46] = 12, + [48] = 13, + [50] = 14, + [100] = 15, + [102] = 16, + [104] = 17, + [106] = 18, + [120] = 19, + [121] = 20, + [122] = 21, + [123] = 22, + }, }, [92] = { - .class_hid = BNXT_ULP_CLASS_HID_8171d, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 32840UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_F2 | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR } + .field_man_bitmap = 0xC0800000000000, + .field_opt_bitmap = 0x8010301800000000, + .field_exclude_bitmap = 0x0, + .class_tid = 1, + .flow_pattern_id = 3, + .field_list = { + [1] = 1, + [7] = 18, + [9] = 19, + [11] = 20, + [52] = 2, + [53] = 21, + [54] = 3, + [55] = 22, + [56] = 4, + [57] = 23, + [58] = 5, + [59] = 24, + [60] = 6, + [61] = 25, + [62] = 7, + [63] = 26, + [64] = 8, + [65] = 27, + [66] = 9, + [67] = 28, + [100] = 10, + [102] = 11, + [104] = 12, + [106] = 13, + [120] = 14, + [121] = 15, + [122] = 16, + [123] = 17, + }, }, [93] = { - .class_hid = BNXT_ULP_CLASS_HID_80763, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 49152UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_F2 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR } + .field_man_bitmap = 0x30200000000000, + .field_opt_bitmap = 0x80040C0600000000, + .field_exclude_bitmap = 0x0, + .class_tid = 1, + .flow_pattern_id = 3, + .field_list = { + [1] = 1, + [7] = 20, + [9] = 21, + [11] = 22, + [32] = 2, + [34] = 3, + [36] = 4, + [38] = 5, + [40] = 6, + [42] = 7, + [44] = 8, + [46] = 9, + [48] = 10, + [50] = 11, + [53] = 23, + [55] = 24, + [57] = 25, + [59] = 26, + [61] = 27, + [63] = 28, + [65] = 29, + [67] = 30, + [100] = 12, + [102] = 13, + [104] = 14, + [106] = 15, + [120] = 16, + [121] = 17, + [122] = 18, + [123] = 19, + }, }, [94] = { - .class_hid = BNXT_ULP_CLASS_HID_8138d, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 49160UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_F2 | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR } + .field_man_bitmap = 0xC0800000000000, + .field_opt_bitmap = 0x8010300600000000, + .field_exclude_bitmap = 0x0, + .class_tid = 1, + .flow_pattern_id = 3, + .field_list = { + [1] = 1, + [7] = 18, + [9] = 19, + [11] = 20, + [33] = 21, + [35] = 22, + [37] = 23, + [39] = 24, + [41] = 25, + [43] = 26, + [45] = 27, + [47] = 28, + [49] = 29, + [51] = 30, + [52] = 2, + [54] = 3, + [56] = 4, + [58] = 5, + [60] = 6, + [62] = 7, + [64] = 8, + [66] = 9, + [100] = 10, + [102] = 11, + [104] = 12, + [106] = 13, + [120] = 14, + [121] = 15, + [122] = 16, + [123] = 17, + }, }, [95] = { - .class_hid = BNXT_ULP_CLASS_HID_814c3, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 49216UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_F2 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR } + .field_man_bitmap = 0x30200000000000, + .field_opt_bitmap = 0x80040C0180000000, + .field_exclude_bitmap = 0x0, + .class_tid = 1, + .flow_pattern_id = 3, + .field_list = { + [1] = 1, + [7] = 20, + [9] = 21, + [11] = 22, + [32] = 2, + [33] = 23, + [34] = 3, + [35] = 24, + [36] = 4, + [37] = 25, + [38] = 5, + [39] = 26, + [40] = 6, + [41] = 27, + [42] = 7, + [43] = 28, + [44] = 8, + [45] = 29, + [46] = 9, + [47] = 30, + [48] = 10, + [49] = 31, + [50] = 11, + [51] = 32, + [100] = 12, + [102] = 13, + [104] = 14, + [106] = 15, + [120] = 16, + [121] = 17, + [122] = 18, + [123] = 19, + }, }, [96] = { - .class_hid = BNXT_ULP_CLASS_HID_8014b, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 49224UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_F2 | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV6 | + BNXT_ULP_HDR_BIT_I_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR } + .field_man_bitmap = 0xC0800000000000, + .field_opt_bitmap = 0x8010301E00000000, + .field_exclude_bitmap = 0x0, + .class_tid = 1, + .flow_pattern_id = 3, + .field_list = { + [1] = 1, + [7] = 18, + [9] = 19, + [11] = 20, + [52] = 2, + [53] = 21, + [54] = 3, + [55] = 22, + [56] = 4, + [57] = 23, + [58] = 5, + [59] = 24, + [60] = 6, + [61] = 25, + [62] = 7, + [63] = 26, + [64] = 8, + [65] = 27, + [66] = 9, + [67] = 28, + [83] = 29, + [85] = 30, + [87] = 31, + [89] = 32, + [91] = 33, + [93] = 34, + [95] = 35, + [97] = 36, + [99] = 37, + [100] = 10, + [102] = 11, + [104] = 12, + [106] = 13, + [120] = 14, + [121] = 15, + [122] = 16, + [123] = 17, + }, }, [97] = { - .class_hid = BNXT_ULP_CLASS_HID_c001f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 98304UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_F2 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV6 | + BNXT_ULP_HDR_BIT_I_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT } + .field_man_bitmap = 0x30200000000000, + .field_opt_bitmap = 0x80040C0780000000, + .field_exclude_bitmap = 0x0, + .class_tid = 1, + .flow_pattern_id = 3, + .field_list = { + [1] = 1, + [7] = 20, + [9] = 21, + [11] = 22, + [32] = 2, + [34] = 3, + [36] = 4, + [38] = 5, + [40] = 6, + [42] = 7, + [44] = 8, + [46] = 9, + [48] = 10, + [50] = 11, + [53] = 23, + [55] = 24, + [57] = 25, + [59] = 26, + [61] = 27, + [63] = 28, + [65] = 29, + [67] = 30, + [83] = 31, + [85] = 32, + [87] = 33, + [89] = 34, + [91] = 35, + [93] = 36, + [95] = 37, + [97] = 38, + [99] = 39, + [100] = 12, + [102] = 13, + [104] = 14, + [106] = 15, + [120] = 16, + [121] = 17, + [122] = 18, + [123] = 19, + }, }, [98] = { - .class_hid = BNXT_ULP_CLASS_HID_c0c39, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 98312UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_F2 | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT } + .field_man_bitmap = 0xC0800000000000, + .field_opt_bitmap = 0x8010300780000000, + .field_exclude_bitmap = 0x0, + .class_tid = 1, + .flow_pattern_id = 3, + .field_list = { + [1] = 1, + [7] = 18, + [9] = 19, + [11] = 20, + [33] = 21, + [35] = 22, + [37] = 23, + [39] = 24, + [41] = 25, + [43] = 26, + [45] = 27, + [47] = 28, + [49] = 29, + [51] = 30, + [52] = 2, + [54] = 3, + [56] = 4, + [58] = 5, + [60] = 6, + [62] = 7, + [64] = 8, + [66] = 9, + [83] = 31, + [85] = 32, + [87] = 33, + [89] = 34, + [91] = 35, + [93] = 36, + [95] = 37, + [97] = 38, + [99] = 39, + [100] = 10, + [102] = 11, + [104] = 12, + [106] = 13, + [120] = 14, + [121] = 15, + [122] = 16, + [123] = 17, + }, }, [99] = { - .class_hid = BNXT_ULP_CLASS_HID_c0d7f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 98368UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_F2 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT } + .field_man_bitmap = 0x30200000000000, + .field_opt_bitmap = 0x80040C01E0000000, + .field_exclude_bitmap = 0x0, + .class_tid = 1, + .flow_pattern_id = 3, + .field_list = { + [1] = 1, + [7] = 20, + [9] = 21, + [11] = 22, + [32] = 2, + [33] = 23, + [34] = 3, + [35] = 24, + [36] = 4, + [37] = 25, + [38] = 5, + [39] = 26, + [40] = 6, + [41] = 27, + [42] = 7, + [43] = 28, + [44] = 8, + [45] = 29, + [46] = 9, + [47] = 30, + [48] = 10, + [49] = 31, + [50] = 11, + [51] = 32, + [83] = 33, + [85] = 34, + [87] = 35, + [89] = 36, + [91] = 37, + [93] = 38, + [95] = 39, + [97] = 40, + [99] = 41, + [100] = 12, + [102] = 13, + [104] = 14, + [106] = 15, + [120] = 16, + [121] = 17, + [122] = 18, + [123] = 19, + }, }, [100] = { - .class_hid = BNXT_ULP_CLASS_HID_c1999, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 98376UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_F2 | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV6 | + BNXT_ULP_HDR_BIT_I_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT } + .field_man_bitmap = 0xC0800000000000, + .field_opt_bitmap = 0x8010301E00000000, + .field_exclude_bitmap = 0x0, + .class_tid = 1, + .flow_pattern_id = 3, + .field_list = { + [1] = 1, + [7] = 18, + [9] = 19, + [11] = 20, + [52] = 2, + [53] = 21, + [54] = 3, + [55] = 22, + [56] = 4, + [57] = 23, + [58] = 5, + [59] = 24, + [60] = 6, + [61] = 25, + [62] = 7, + [63] = 26, + [64] = 8, + [65] = 27, + [66] = 9, + [67] = 28, + [100] = 10, + [101] = 29, + [102] = 11, + [103] = 30, + [104] = 12, + [105] = 31, + [106] = 13, + [107] = 32, + [120] = 14, + [121] = 15, + [122] = 16, + [123] = 17, + }, }, [101] = { - .class_hid = BNXT_ULP_CLASS_HID_c09ef, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114688UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_F2 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV6 | + BNXT_ULP_HDR_BIT_I_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT } + .field_man_bitmap = 0x30200000000000, + .field_opt_bitmap = 0x80040C0780000000, + .field_exclude_bitmap = 0x0, + .class_tid = 1, + .flow_pattern_id = 3, + .field_list = { + [1] = 1, + [7] = 20, + [9] = 21, + [11] = 22, + [32] = 2, + [34] = 3, + [36] = 4, + [38] = 5, + [40] = 6, + [42] = 7, + [44] = 8, + [46] = 9, + [48] = 10, + [50] = 11, + [53] = 23, + [55] = 24, + [57] = 25, + [59] = 26, + [61] = 27, + [63] = 28, + [65] = 29, + [67] = 30, + [100] = 12, + [101] = 31, + [102] = 13, + [103] = 32, + [104] = 14, + [105] = 33, + [106] = 15, + [107] = 34, + [120] = 16, + [121] = 17, + [122] = 18, + [123] = 19, + }, }, [102] = { - .class_hid = BNXT_ULP_CLASS_HID_c1609, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114696UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_F2 | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT } + .field_man_bitmap = 0xC0800000000000, + .field_opt_bitmap = 0x8010300780000000, + .field_exclude_bitmap = 0x0, + .class_tid = 1, + .flow_pattern_id = 3, + .field_list = { + [1] = 1, + [7] = 18, + [9] = 19, + [11] = 20, + [33] = 21, + [35] = 22, + [37] = 23, + [39] = 24, + [41] = 25, + [43] = 26, + [45] = 27, + [47] = 28, + [49] = 29, + [51] = 30, + [52] = 2, + [54] = 3, + [56] = 4, + [58] = 5, + [60] = 6, + [62] = 7, + [64] = 8, + [66] = 9, + [100] = 10, + [101] = 31, + [102] = 11, + [103] = 32, + [104] = 12, + [105] = 33, + [106] = 13, + [107] = 34, + [120] = 14, + [121] = 15, + [122] = 16, + [123] = 17, + }, }, [103] = { - .class_hid = BNXT_ULP_CLASS_HID_c174f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114752UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_F2 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT } + .field_man_bitmap = 0x30200000000000, + .field_opt_bitmap = 0x80040C01E0000000, + .field_exclude_bitmap = 0x0, + .class_tid = 1, + .flow_pattern_id = 3, + .field_list = { + [1] = 1, + [7] = 20, + [9] = 21, + [11] = 22, + [32] = 2, + [33] = 23, + [34] = 3, + [35] = 24, + [36] = 4, + [37] = 25, + [38] = 5, + [39] = 26, + [40] = 6, + [41] = 27, + [42] = 7, + [43] = 28, + [44] = 8, + [45] = 29, + [46] = 9, + [47] = 30, + [48] = 10, + [49] = 31, + [50] = 11, + [51] = 32, + [100] = 12, + [101] = 33, + [102] = 13, + [103] = 34, + [104] = 14, + [105] = 35, + [106] = 15, + [107] = 36, + [120] = 16, + [121] = 17, + [122] = 18, + [123] = 19, + }, }, [104] = { - .class_hid = BNXT_ULP_CLASS_HID_c03d7, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114760UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_F2 | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_ICMP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT } + .field_man_bitmap = 0xC0800000000000, + .field_opt_bitmap = 0x8010300600000000, + .field_exclude_bitmap = 0x0, + .class_tid = 1, + .flow_pattern_id = 4, + .field_list = { + [1] = 1, + [7] = 18, + [9] = 19, + [11] = 20, + [23] = 31, + [25] = 32, + [27] = 33, + [29] = 34, + [31] = 35, + [33] = 21, + [35] = 22, + [37] = 23, + [39] = 24, + [41] = 25, + [43] = 26, + [45] = 27, + [47] = 28, + [49] = 29, + [51] = 30, + [52] = 2, + [54] = 3, + [56] = 4, + [58] = 5, + [60] = 6, + [62] = 7, + [64] = 8, + [66] = 9, + [100] = 10, + [102] = 11, + [104] = 12, + [106] = 13, + [120] = 14, + [121] = 15, + [122] = 16, + [123] = 17, + }, }, [105] = { - .class_hid = BNXT_ULP_CLASS_HID_a1e73, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 163840UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_F2 | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_ICMP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT } + .field_man_bitmap = 0x30200000000000, + .field_opt_bitmap = 0x80040C0180000000, + .field_exclude_bitmap = 0x0, + .class_tid = 1, + .flow_pattern_id = 4, + .field_list = { + [1] = 1, + [7] = 20, + [9] = 21, + [11] = 22, + [23] = 33, + [25] = 34, + [27] = 35, + [29] = 36, + [31] = 37, + [32] = 2, + [33] = 23, + [34] = 3, + [35] = 24, + [36] = 4, + [37] = 25, + [38] = 5, + [39] = 26, + [40] = 6, + [41] = 27, + [42] = 7, + [43] = 28, + [44] = 8, + [45] = 29, + [46] = 9, + [47] = 30, + [48] = 10, + [49] = 31, + [50] = 11, + [51] = 32, + [100] = 12, + [102] = 13, + [104] = 14, + [106] = 15, + [120] = 16, + [121] = 17, + [122] = 18, + [123] = 19, + }, }, [106] = { - .class_hid = BNXT_ULP_CLASS_HID_a0afb, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 163848UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT } + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_GENEVE | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xA002800000000000, + .field_exclude_bitmap = 0x2000000000000000, + .class_tid = 1, + .flow_pattern_id = 5, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [32] = 5, + [34] = 6, + [36] = 7, + [38] = 8, + [40] = 9, + [42] = 10, + [44] = 11, + [46] = 12, + [48] = 13, + [50] = 14, + [100] = 15, + [102] = 16, + [104] = 17, + [106] = 18, + }, }, [107] = { - .class_hid = BNXT_ULP_CLASS_HID_a0c31, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 163904UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = + .app_id = 0, + .hdr_bitmap = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xB800000000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + }, }, [108] = { - .class_hid = BNXT_ULP_CLASS_HID_a185b, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 163912UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | + .app_id = 0, + .hdr_bitmap = { .bits = BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x9000000000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [108] = 2, + [112] = 3, + [116] = 4, + }, }, [109] = { - .class_hid = BNXT_ULP_CLASS_HID_a08a1, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 180224UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = + .app_id = 0, + .hdr_bitmap = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBA00000000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [108] = 5, + [112] = 6, + [116] = 7, + }, }, [110] = { - .class_hid = BNXT_ULP_CLASS_HID_a14cb, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 180232UL, + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x9000000000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT } + .field_list = { + [1] = 1, + [109] = 2, + [113] = 3, + [117] = 4, + }, }, [111] = { - .class_hid = BNXT_ULP_CLASS_HID_a1601, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 180288UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = + .app_id = 0, + .hdr_bitmap = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBA00000000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [109] = 5, + [113] = 6, + [117] = 7, + }, }, [112] = { - .class_hid = BNXT_ULP_CLASS_HID_a0289, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 180296UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | + .app_id = 0, + .hdr_bitmap = { .bits = BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x9200000000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [108] = 2, + [109] = 5, + [112] = 3, + [113] = 6, + [116] = 4, + [117] = 7, + }, }, [113] = { - .class_hid = BNXT_ULP_CLASS_HID_e015d, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 229376UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = + .app_id = 0, + .hdr_bitmap = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBA40000000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [108] = 5, + [109] = 8, + [112] = 6, + [113] = 9, + [116] = 7, + [117] = 10, + }, }, [114] = { - .class_hid = BNXT_ULP_CLASS_HID_e0d47, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 229384UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | + .app_id = 0, + .hdr_bitmap = { .bits = BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x93C0000000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [52] = 2, + [54] = 3, + [56] = 4, + [58] = 5, + [60] = 6, + [62] = 7, + [64] = 8, + [66] = 9, + }, }, [115] = { - .class_hid = BNXT_ULP_CLASS_HID_e0ebd, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 229440UL, + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x91B0000000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT } + .field_list = { + [1] = 1, + [32] = 2, + [34] = 3, + [36] = 4, + [38] = 5, + [40] = 6, + [42] = 7, + [44] = 8, + [46] = 9, + [48] = 10, + [50] = 11, + }, }, [116] = { - .class_hid = BNXT_ULP_CLASS_HID_e1aa7, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 229448UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = + .app_id = 0, + .hdr_bitmap = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBA78000000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [52] = 5, + [54] = 6, + [56] = 7, + [58] = 8, + [60] = 9, + [62] = 10, + [64] = 11, + [66] = 12, + }, }, [117] = { - .class_hid = BNXT_ULP_CLASS_HID_e0b2d, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 245760UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = + .app_id = 0, + .hdr_bitmap = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBA36000000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [32] = 5, + [34] = 6, + [36] = 7, + [38] = 8, + [40] = 9, + [42] = 10, + [44] = 11, + [46] = 12, + [48] = 13, + [50] = 14, + }, }, [118] = { - .class_hid = BNXT_ULP_CLASS_HID_e1757, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 245768UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | + .app_id = 0, + .hdr_bitmap = { .bits = BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x9278000000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [52] = 5, + [54] = 6, + [56] = 7, + [58] = 8, + [60] = 9, + [62] = 10, + [64] = 11, + [66] = 12, + [108] = 2, + [112] = 3, + [116] = 4, + }, }, [119] = { - .class_hid = BNXT_ULP_CLASS_HID_e188d, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 245824UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | + .app_id = 0, + .hdr_bitmap = { .bits = BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x9236000000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [32] = 5, + [34] = 6, + [36] = 7, + [38] = 8, + [40] = 9, + [42] = 10, + [44] = 11, + [46] = 12, + [48] = 13, + [50] = 14, + [108] = 2, + [112] = 3, + [116] = 4, + }, }, [120] = { - .class_hid = BNXT_ULP_CLASS_HID_e0515, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 245832UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = + .app_id = 0, + .hdr_bitmap = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBA4F000000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [52] = 8, + [54] = 9, + [56] = 10, + [58] = 11, + [60] = 12, + [62] = 13, + [64] = 14, + [66] = 15, + [108] = 5, + [112] = 6, + [116] = 7, + }, }, [121] = { - .class_hid = BNXT_ULP_CLASS_HID_21967, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 131072UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = + .app_id = 0, + .hdr_bitmap = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBA46C00000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [32] = 8, + [34] = 9, + [36] = 10, + [38] = 11, + [40] = 12, + [42] = 13, + [44] = 14, + [46] = 15, + [48] = 16, + [50] = 17, + [108] = 5, + [112] = 6, + [116] = 7, + }, }, [122] = { - .class_hid = BNXT_ULP_CLASS_HID_205ff, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 131080UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR } + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x9278000000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [52] = 5, + [54] = 6, + [56] = 7, + [58] = 8, + [60] = 9, + [62] = 10, + [64] = 11, + [66] = 12, + [109] = 2, + [113] = 3, + [117] = 4, + }, }, [123] = { - .class_hid = BNXT_ULP_CLASS_HID_20725, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 131136UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR } + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x9236000000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [32] = 5, + [34] = 6, + [36] = 7, + [38] = 8, + [40] = 9, + [42] = 10, + [44] = 11, + [46] = 12, + [48] = 13, + [50] = 14, + [109] = 2, + [113] = 3, + [117] = 4, + }, }, [124] = { - .class_hid = BNXT_ULP_CLASS_HID_2135f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 131144UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR } + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBA4F000000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [52] = 8, + [54] = 9, + [56] = 10, + [58] = 11, + [60] = 12, + [62] = 13, + [64] = 14, + [66] = 15, + [109] = 5, + [113] = 6, + [117] = 7, + }, }, [125] = { - .class_hid = BNXT_ULP_CLASS_HID_61bfb, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 196608UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR } + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBA46C00000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [32] = 8, + [34] = 9, + [36] = 10, + [38] = 11, + [40] = 12, + [42] = 13, + [44] = 14, + [46] = 15, + [48] = 16, + [50] = 17, + [109] = 5, + [113] = 6, + [117] = 7, + }, }, [126] = { - .class_hid = BNXT_ULP_CLASS_HID_60873, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 196616UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR } + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x924F000000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [52] = 8, + [54] = 9, + [56] = 10, + [58] = 11, + [60] = 12, + [62] = 13, + [64] = 14, + [66] = 15, + [108] = 2, + [109] = 5, + [112] = 3, + [113] = 6, + [116] = 4, + [117] = 7, + }, }, [127] = { - .class_hid = BNXT_ULP_CLASS_HID_609b9, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 196672UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR } + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x9246C00000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [32] = 8, + [34] = 9, + [36] = 10, + [38] = 11, + [40] = 12, + [42] = 13, + [44] = 14, + [46] = 15, + [48] = 16, + [50] = 17, + [108] = 2, + [109] = 5, + [112] = 3, + [113] = 6, + [116] = 4, + [117] = 7, + }, }, [128] = { - .class_hid = BNXT_ULP_CLASS_HID_615d3, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 196680UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR } + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBA49E00000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [52] = 11, + [54] = 12, + [56] = 13, + [58] = 14, + [60] = 15, + [62] = 16, + [64] = 17, + [66] = 18, + [108] = 5, + [109] = 8, + [112] = 6, + [113] = 9, + [116] = 7, + [117] = 10, + }, }, [129] = { - .class_hid = BNXT_ULP_CLASS_HID_30a55, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 393216UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT } + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBA48D80000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [32] = 11, + [34] = 12, + [36] = 13, + [38] = 14, + [40] = 15, + [42] = 16, + [44] = 17, + [46] = 18, + [48] = 19, + [50] = 20, + [108] = 5, + [109] = 8, + [112] = 6, + [113] = 9, + [116] = 7, + [117] = 10, + }, }, [130] = { - .class_hid = BNXT_ULP_CLASS_HID_3164f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 393224UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT } - }, - [131] = { - .class_hid = BNXT_ULP_CLASS_HID_317b5, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 393280UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT } - }, - [132] = { - .class_hid = BNXT_ULP_CLASS_HID_3040d, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 393288UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT } - }, - [133] = { - .class_hid = BNXT_ULP_CLASS_HID_70ca9, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 458752UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT } - }, - [134] = { - .class_hid = BNXT_ULP_CLASS_HID_718c3, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 458760UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT } - }, - [135] = { - .class_hid = BNXT_ULP_CLASS_HID_71a09, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 458816UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT } - }, - [136] = { - .class_hid = BNXT_ULP_CLASS_HID_70681, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 458824UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT } - }, - [137] = { - .class_hid = BNXT_ULP_CLASS_HID_2821d, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 655360UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT } - }, - [138] = { - .class_hid = BNXT_ULP_CLASS_HID_28e37, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 655368UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT } - }, - [139] = { - .class_hid = BNXT_ULP_CLASS_HID_28f7d, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 655424UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT } - }, - [140] = { - .class_hid = BNXT_ULP_CLASS_HID_29b97, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 655432UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + .app_id = 0, + .hdr_bitmap = { .bits = BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT } - }, - [141] = { - .class_hid = BNXT_ULP_CLASS_HID_68491, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 720896UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT } - }, - [142] = { - .class_hid = BNXT_ULP_CLASS_HID_6908b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 720904UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT } - }, - [143] = { - .class_hid = BNXT_ULP_CLASS_HID_691f1, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 720960UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT } - }, - [144] = { - .class_hid = BNXT_ULP_CLASS_HID_69deb, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 720968UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT } - }, - [145] = { - .class_hid = BNXT_ULP_CLASS_HID_3926d, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 917504UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT } - }, - [146] = { - .class_hid = BNXT_ULP_CLASS_HID_39e87, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 917512UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT } - }, - [147] = { - .class_hid = BNXT_ULP_CLASS_HID_38023, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 917568UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT } - }, - [148] = { - .class_hid = BNXT_ULP_CLASS_HID_38c45, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 917576UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT } - }, - [149] = { - .class_hid = BNXT_ULP_CLASS_HID_794e1, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 983040UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT } - }, - [150] = { - .class_hid = BNXT_ULP_CLASS_HID_78179, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 983048UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT } - }, - [151] = { - .class_hid = BNXT_ULP_CLASS_HID_782a7, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 983104UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT } - }, - [152] = { - .class_hid = BNXT_ULP_CLASS_HID_78ed9, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 983112UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT } - }, - [153] = { - .class_hid = BNXT_ULP_CLASS_HID_81d05, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 32768UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR } - }, - [154] = { - .class_hid = BNXT_ULP_CLASS_HID_8098d, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 32776UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR } - }, - [155] = { - .class_hid = BNXT_ULP_CLASS_HID_80ac3, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 32832UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR } - }, - [156] = { - .class_hid = BNXT_ULP_CLASS_HID_8172d, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 32840UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR } - }, - [157] = { - .class_hid = BNXT_ULP_CLASS_HID_80753, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 49152UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR } - }, - [158] = { - .class_hid = BNXT_ULP_CLASS_HID_813bd, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 49160UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR } - }, - [159] = { - .class_hid = BNXT_ULP_CLASS_HID_814f3, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 49216UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR } - }, - [160] = { - .class_hid = BNXT_ULP_CLASS_HID_8017b, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 49224UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR } - }, - [161] = { - .class_hid = BNXT_ULP_CLASS_HID_c002f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 98304UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT } - }, - [162] = { - .class_hid = BNXT_ULP_CLASS_HID_c0c09, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 98312UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT } - }, - [163] = { - .class_hid = BNXT_ULP_CLASS_HID_c0d4f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 98368UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT } - }, - [164] = { - .class_hid = BNXT_ULP_CLASS_HID_c19a9, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 98376UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT } - }, - [165] = { - .class_hid = BNXT_ULP_CLASS_HID_c09df, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 114688UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT } - }, - [166] = { - .class_hid = BNXT_ULP_CLASS_HID_c1639, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 114696UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT } - }, - [167] = { - .class_hid = BNXT_ULP_CLASS_HID_c177f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 114752UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT } - }, - [168] = { - .class_hid = BNXT_ULP_CLASS_HID_c03e7, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 114760UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT } - }, - [169] = { - .class_hid = BNXT_ULP_CLASS_HID_a1e43, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 163840UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT } - }, - [170] = { - .class_hid = BNXT_ULP_CLASS_HID_a0acb, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 163848UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT } - }, - [171] = { - .class_hid = BNXT_ULP_CLASS_HID_a0c01, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 163904UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT } - }, - [172] = { - .class_hid = BNXT_ULP_CLASS_HID_a186b, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 163912UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT } - }, - [173] = { - .class_hid = BNXT_ULP_CLASS_HID_a0891, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 180224UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT } - }, - [174] = { - .class_hid = BNXT_ULP_CLASS_HID_a14fb, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 180232UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT } - }, - [175] = { - .class_hid = BNXT_ULP_CLASS_HID_a1631, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 180288UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT } - }, - [176] = { - .class_hid = BNXT_ULP_CLASS_HID_a02b9, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 180296UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT } - }, - [177] = { - .class_hid = BNXT_ULP_CLASS_HID_e016d, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 229376UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT } - }, - [178] = { - .class_hid = BNXT_ULP_CLASS_HID_e0d77, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 229384UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT } - }, - [179] = { - .class_hid = BNXT_ULP_CLASS_HID_e0e8d, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 229440UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT } - }, - [180] = { - .class_hid = BNXT_ULP_CLASS_HID_e1a97, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 229448UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT } - }, - [181] = { - .class_hid = BNXT_ULP_CLASS_HID_e0b1d, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 245760UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT } - }, - [182] = { - .class_hid = BNXT_ULP_CLASS_HID_e1767, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 245768UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT } - }, - [183] = { - .class_hid = BNXT_ULP_CLASS_HID_e18bd, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 245824UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT } - }, - [184] = { - .class_hid = BNXT_ULP_CLASS_HID_e0525, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 245832UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT } - }, - [185] = { - .class_hid = BNXT_ULP_CLASS_HID_21957, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 131072UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR } - }, - [186] = { - .class_hid = BNXT_ULP_CLASS_HID_205cf, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 131080UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR } - }, - [187] = { - .class_hid = BNXT_ULP_CLASS_HID_20715, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 131136UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR } - }, - [188] = { - .class_hid = BNXT_ULP_CLASS_HID_2136f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 131144UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR } - }, - [189] = { - .class_hid = BNXT_ULP_CLASS_HID_61bcb, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 196608UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR } - }, - [190] = { - .class_hid = BNXT_ULP_CLASS_HID_60843, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 196616UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR } - }, - [191] = { - .class_hid = BNXT_ULP_CLASS_HID_60989, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 196672UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR } - }, - [192] = { - .class_hid = BNXT_ULP_CLASS_HID_615e3, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 196680UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR } - }, - [193] = { - .class_hid = BNXT_ULP_CLASS_HID_30a65, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 393216UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT } - }, - [194] = { - .class_hid = BNXT_ULP_CLASS_HID_3167f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 393224UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT } - }, - [195] = { - .class_hid = BNXT_ULP_CLASS_HID_31785, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 393280UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT } - }, - [196] = { - .class_hid = BNXT_ULP_CLASS_HID_3043d, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 393288UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT } - }, - [197] = { - .class_hid = BNXT_ULP_CLASS_HID_70c99, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 458752UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT } - }, - [198] = { - .class_hid = BNXT_ULP_CLASS_HID_718f3, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 458760UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT } - }, - [199] = { - .class_hid = BNXT_ULP_CLASS_HID_71a39, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 458816UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT } - }, - [200] = { - .class_hid = BNXT_ULP_CLASS_HID_706b1, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 458824UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT } - }, - [201] = { - .class_hid = BNXT_ULP_CLASS_HID_2822d, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 655360UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT } - }, - [202] = { - .class_hid = BNXT_ULP_CLASS_HID_28e07, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 655368UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT } - }, - [203] = { - .class_hid = BNXT_ULP_CLASS_HID_28f4d, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 655424UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT } - }, - [204] = { - .class_hid = BNXT_ULP_CLASS_HID_29ba7, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 655432UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT } - }, - [205] = { - .class_hid = BNXT_ULP_CLASS_HID_684a1, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 720896UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT } - }, - [206] = { - .class_hid = BNXT_ULP_CLASS_HID_690bb, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 720904UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT } - }, - [207] = { - .class_hid = BNXT_ULP_CLASS_HID_691c1, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 720960UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT } - }, - [208] = { - .class_hid = BNXT_ULP_CLASS_HID_69ddb, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 720968UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT } - }, - [209] = { - .class_hid = BNXT_ULP_CLASS_HID_3925d, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 917504UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT } - }, - [210] = { - .class_hid = BNXT_ULP_CLASS_HID_39eb7, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 917512UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT } - }, - [211] = { - .class_hid = BNXT_ULP_CLASS_HID_38013, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 917568UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT } - }, - [212] = { - .class_hid = BNXT_ULP_CLASS_HID_38c75, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 917576UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT } - }, - [213] = { - .class_hid = BNXT_ULP_CLASS_HID_794d1, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 983040UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT } - }, - [214] = { - .class_hid = BNXT_ULP_CLASS_HID_78149, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 983048UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT } - }, - [215] = { - .class_hid = BNXT_ULP_CLASS_HID_78297, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 983104UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT } - }, - [216] = { - .class_hid = BNXT_ULP_CLASS_HID_78ee9, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 983112UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT } - }, - [217] = { - .class_hid = BNXT_ULP_CLASS_HID_0816, - .class_tid = 1, - .hdr_sig_id = 0, - .flow_sig_id = 4096UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_0_BITMASK_O_IPV6_DST_ADDR } - }, - [218] = { - .class_hid = BNXT_ULP_CLASS_HID_1852, - .class_tid = 1, - .hdr_sig_id = 0, - .flow_sig_id = 6144UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_0_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_0_BITMASK_O_IPV6_DST_ADDR } - }, - [219] = { - .class_hid = BNXT_ULP_CLASS_HID_09f4, - .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 16384UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_1_BITMASK_O_IPV4_DST_ADDR } - }, - [220] = { - .class_hid = BNXT_ULP_CLASS_HID_1dd4, - .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 24576UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_1_BITMASK_O_IPV4_DST_ADDR } - }, - [221] = { - .class_hid = BNXT_ULP_CLASS_HID_804f1, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 32768UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_DST_ADDR } - }, - [222] = { - .class_hid = BNXT_ULP_CLASS_HID_81251, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 32832UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_DST_ADDR } - }, - [223] = { - .class_hid = BNXT_ULP_CLASS_HID_80ee1, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 49152UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_DST_ADDR } - }, - [224] = { - .class_hid = BNXT_ULP_CLASS_HID_81c41, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 49216UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_DST_ADDR } - }, - [225] = { - .class_hid = BNXT_ULP_CLASS_HID_2013b, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 131072UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_DST_ADDR } - }, - [226] = { - .class_hid = BNXT_ULP_CLASS_HID_20e9b, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 131136UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_DST_ADDR } - }, - [227] = { - .class_hid = BNXT_ULP_CLASS_HID_603bf, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 196608UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_DST_ADDR } - }, - [228] = { - .class_hid = BNXT_ULP_CLASS_HID_6111f, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 196672UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_DST_ADDR } - }, - [229] = { - .class_hid = BNXT_ULP_CLASS_HID_0806, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 4096UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR } - }, - [230] = { - .class_hid = BNXT_ULP_CLASS_HID_1842, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 6144UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR } - }, - [231] = { - .class_hid = BNXT_ULP_CLASS_HID_1be6, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 12288UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_SRC_PORT } - }, - [232] = { - .class_hid = BNXT_ULP_CLASS_HID_0c80, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 14336UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_SRC_PORT } - }, - [233] = { - .class_hid = BNXT_ULP_CLASS_HID_1216, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 20480UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DST_PORT } - }, - [234] = { - .class_hid = BNXT_ULP_CLASS_HID_02b0, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 22528UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DST_PORT } - }, - [235] = { - .class_hid = BNXT_ULP_CLASS_HID_0654, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 28672UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DST_PORT } - }, - [236] = { - .class_hid = BNXT_ULP_CLASS_HID_1690, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 30720UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DST_PORT } - }, - [237] = { - .class_hid = BNXT_ULP_CLASS_HID_09e4, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 16384UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR } - }, - [238] = { - .class_hid = BNXT_ULP_CLASS_HID_1dc4, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 24576UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR } - }, - [239] = { - .class_hid = BNXT_ULP_CLASS_HID_80efc, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 49152UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_SRC_PORT } - }, - [240] = { - .class_hid = BNXT_ULP_CLASS_HID_80332, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 57344UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_SRC_PORT } - }, - [241] = { - .class_hid = BNXT_ULP_CLASS_HID_40c78, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 81920UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DST_PORT } - }, - [242] = { - .class_hid = BNXT_ULP_CLASS_HID_400be, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 90112UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DST_PORT } - }, - [243] = { - .class_hid = BNXT_ULP_CLASS_HID_c1170, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 114688UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DST_PORT } - }, - [244] = { - .class_hid = BNXT_ULP_CLASS_HID_c05b6, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 122880UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DST_PORT } - }, - [245] = { - .class_hid = BNXT_ULP_CLASS_HID_0836, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 4096UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR } - }, - [246] = { - .class_hid = BNXT_ULP_CLASS_HID_1872, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 6144UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR } - }, - [247] = { - .class_hid = BNXT_ULP_CLASS_HID_1bd6, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 12288UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_SRC_PORT } - }, - [248] = { - .class_hid = BNXT_ULP_CLASS_HID_0cb0, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 14336UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_SRC_PORT } - }, - [249] = { - .class_hid = BNXT_ULP_CLASS_HID_1226, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 20480UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_DST_PORT } - }, - [250] = { - .class_hid = BNXT_ULP_CLASS_HID_0280, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 22528UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_DST_PORT } - }, - [251] = { - .class_hid = BNXT_ULP_CLASS_HID_0664, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 28672UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_DST_PORT } - }, - [252] = { - .class_hid = BNXT_ULP_CLASS_HID_16a0, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 30720UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_DST_PORT } - }, - [253] = { - .class_hid = BNXT_ULP_CLASS_HID_09d4, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 16384UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR } - }, - [254] = { - .class_hid = BNXT_ULP_CLASS_HID_1df4, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 24576UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR } - }, - [255] = { - .class_hid = BNXT_ULP_CLASS_HID_80ecc, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 49152UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_SRC_PORT } - }, - [256] = { - .class_hid = BNXT_ULP_CLASS_HID_80302, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 57344UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_SRC_PORT } - }, - [257] = { - .class_hid = BNXT_ULP_CLASS_HID_40c48, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 81920UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_DST_PORT } - }, - [258] = { - .class_hid = BNXT_ULP_CLASS_HID_4008e, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 90112UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_DST_PORT } - }, - [259] = { - .class_hid = BNXT_ULP_CLASS_HID_c1140, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 114688UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_DST_PORT } - }, - [260] = { - .class_hid = BNXT_ULP_CLASS_HID_c0586, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 122880UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_DST_PORT } - }, - [261] = { - .class_hid = BNXT_ULP_CLASS_HID_804e1, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 32768UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR } - }, - [262] = { - .class_hid = BNXT_ULP_CLASS_HID_81241, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 32832UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR } - }, - [263] = { - .class_hid = BNXT_ULP_CLASS_HID_80ef1, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 49152UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR } - }, - [264] = { - .class_hid = BNXT_ULP_CLASS_HID_81c51, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 49216UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR } - }, - [265] = { - .class_hid = BNXT_ULP_CLASS_HID_c076d, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 98304UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT } - }, - [266] = { - .class_hid = BNXT_ULP_CLASS_HID_c14cd, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 98368UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT } - }, - [267] = { - .class_hid = BNXT_ULP_CLASS_HID_c117d, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114688UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT } - }, - [268] = { - .class_hid = BNXT_ULP_CLASS_HID_c1edd, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 114752UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT } - }, - [269] = { - .class_hid = BNXT_ULP_CLASS_HID_a062f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 163840UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT } - }, - [270] = { - .class_hid = BNXT_ULP_CLASS_HID_a138f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 163904UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT } - }, - [271] = { - .class_hid = BNXT_ULP_CLASS_HID_a103f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 180224UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT } - }, - [272] = { - .class_hid = BNXT_ULP_CLASS_HID_a1d9f, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 180288UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT } - }, - [273] = { - .class_hid = BNXT_ULP_CLASS_HID_e08ab, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 229376UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT } - }, - [274] = { - .class_hid = BNXT_ULP_CLASS_HID_e160b, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 229440UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT } - }, - [275] = { - .class_hid = BNXT_ULP_CLASS_HID_e12bb, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 245760UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT } - }, - [276] = { - .class_hid = BNXT_ULP_CLASS_HID_e0079, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 245824UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT } - }, - [277] = { - .class_hid = BNXT_ULP_CLASS_HID_2012b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 131072UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR } - }, - [278] = { - .class_hid = BNXT_ULP_CLASS_HID_20e8b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 131136UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR } - }, - [279] = { - .class_hid = BNXT_ULP_CLASS_HID_603af, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 196608UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR } - }, - [280] = { - .class_hid = BNXT_ULP_CLASS_HID_6110f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 196672UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR } - }, - [281] = { - .class_hid = BNXT_ULP_CLASS_HID_311bb, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 393216UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT } - }, - [282] = { - .class_hid = BNXT_ULP_CLASS_HID_31f1b, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 393280UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT } - }, - [283] = { - .class_hid = BNXT_ULP_CLASS_HID_7143f, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 458752UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT } - }, - [284] = { - .class_hid = BNXT_ULP_CLASS_HID_701fd, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 458816UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT } - }, - [285] = { - .class_hid = BNXT_ULP_CLASS_HID_28963, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 655360UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT } - }, - [286] = { - .class_hid = BNXT_ULP_CLASS_HID_296c3, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 655424UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT } - }, - [287] = { - .class_hid = BNXT_ULP_CLASS_HID_68be7, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 720896UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT } - }, - [288] = { - .class_hid = BNXT_ULP_CLASS_HID_69947, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 720960UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT } - }, - [289] = { - .class_hid = BNXT_ULP_CLASS_HID_399f3, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 917504UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT } - }, - [290] = { - .class_hid = BNXT_ULP_CLASS_HID_387b1, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 917568UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT } - }, - [291] = { - .class_hid = BNXT_ULP_CLASS_HID_79c77, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 983040UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT } - }, - [292] = { - .class_hid = BNXT_ULP_CLASS_HID_78a35, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 983104UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT } - }, - [293] = { - .class_hid = BNXT_ULP_CLASS_HID_804d1, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 32768UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR } - }, - [294] = { - .class_hid = BNXT_ULP_CLASS_HID_81271, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 32832UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR } - }, - [295] = { - .class_hid = BNXT_ULP_CLASS_HID_80ec1, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 49152UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR } - }, - [296] = { - .class_hid = BNXT_ULP_CLASS_HID_81c61, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 49216UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR } - }, - [297] = { - .class_hid = BNXT_ULP_CLASS_HID_c075d, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 98304UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT } - }, - [298] = { - .class_hid = BNXT_ULP_CLASS_HID_c14fd, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 98368UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT } - }, - [299] = { - .class_hid = BNXT_ULP_CLASS_HID_c114d, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 114688UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT } - }, - [300] = { - .class_hid = BNXT_ULP_CLASS_HID_c1eed, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 114752UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT } - }, - [301] = { - .class_hid = BNXT_ULP_CLASS_HID_a061f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 163840UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT } - }, - [302] = { - .class_hid = BNXT_ULP_CLASS_HID_a13bf, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 163904UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT } - }, - [303] = { - .class_hid = BNXT_ULP_CLASS_HID_a100f, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 180224UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT } - }, - [304] = { - .class_hid = BNXT_ULP_CLASS_HID_a1daf, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 180288UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT } - }, - [305] = { - .class_hid = BNXT_ULP_CLASS_HID_e089b, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 229376UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT } - }, - [306] = { - .class_hid = BNXT_ULP_CLASS_HID_e163b, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 229440UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT } - }, - [307] = { - .class_hid = BNXT_ULP_CLASS_HID_e128b, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 245760UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT } - }, - [308] = { - .class_hid = BNXT_ULP_CLASS_HID_e0049, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 245824UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT } - }, - [309] = { - .class_hid = BNXT_ULP_CLASS_HID_2011b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 131072UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR } - }, - [310] = { - .class_hid = BNXT_ULP_CLASS_HID_20ebb, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 131136UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR } - }, - [311] = { - .class_hid = BNXT_ULP_CLASS_HID_6039f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 196608UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR } - }, - [312] = { - .class_hid = BNXT_ULP_CLASS_HID_6113f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 196672UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR } - }, - [313] = { - .class_hid = BNXT_ULP_CLASS_HID_3118b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 393216UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT } - }, - [314] = { - .class_hid = BNXT_ULP_CLASS_HID_31f2b, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 393280UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT } - }, - [315] = { - .class_hid = BNXT_ULP_CLASS_HID_7140f, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 458752UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT } - }, - [316] = { - .class_hid = BNXT_ULP_CLASS_HID_701cd, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 458816UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT } - }, - [317] = { - .class_hid = BNXT_ULP_CLASS_HID_28953, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 655360UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT } - }, - [318] = { - .class_hid = BNXT_ULP_CLASS_HID_296f3, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 655424UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT } - }, - [319] = { - .class_hid = BNXT_ULP_CLASS_HID_68bd7, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 720896UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT } - }, - [320] = { - .class_hid = BNXT_ULP_CLASS_HID_69977, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 720960UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT } - }, - [321] = { - .class_hid = BNXT_ULP_CLASS_HID_399c3, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 917504UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT } - }, - [322] = { - .class_hid = BNXT_ULP_CLASS_HID_38781, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 917568UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT } - }, - [323] = { - .class_hid = BNXT_ULP_CLASS_HID_79c47, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 983040UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT } - }, - [324] = { - .class_hid = BNXT_ULP_CLASS_HID_78a05, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 983104UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT } - }, - [325] = { - .class_hid = BNXT_ULP_CLASS_HID_04a4, - .class_tid = 1, - .hdr_sig_id = 0, - .flow_sig_id = 8UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_0_BITMASK_O_ETH_SMAC } - }, - [326] = { - .class_hid = BNXT_ULP_CLASS_HID_04a8, - .class_tid = 1, - .hdr_sig_id = 1, - .flow_sig_id = 8UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_1_BITMASK_O_ETH_SMAC } - }, - [327] = { - .class_hid = BNXT_ULP_CLASS_HID_04a5, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 8UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_2_BITMASK_O_ETH_SMAC } - }, - [328] = { - .class_hid = BNXT_ULP_CLASS_HID_1205, - .class_tid = 1, - .hdr_sig_id = 2, - .flow_sig_id = 72UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_2_BITMASK_OO_VLAN_VID } - }, - [329] = { - .class_hid = BNXT_ULP_CLASS_HID_04a9, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 8UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_3_BITMASK_O_ETH_SMAC } - }, - [330] = { - .class_hid = BNXT_ULP_CLASS_HID_1209, - .class_tid = 1, - .hdr_sig_id = 3, - .flow_sig_id = 72UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_3_BITMASK_OO_VLAN_VID } - }, - [331] = { - .class_hid = BNXT_ULP_CLASS_HID_04b4, - .class_tid = 1, - .hdr_sig_id = 4, - .flow_sig_id = 8UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_4_BITMASK_O_ETH_SMAC } - }, - [332] = { - .class_hid = BNXT_ULP_CLASS_HID_04b8, - .class_tid = 1, - .hdr_sig_id = 5, - .flow_sig_id = 8UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_5_BITMASK_O_ETH_SMAC } - }, - [333] = { - .class_hid = BNXT_ULP_CLASS_HID_0484, - .class_tid = 1, - .hdr_sig_id = 6, - .flow_sig_id = 8UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_6_BITMASK_O_ETH_SMAC } - }, - [334] = { - .class_hid = BNXT_ULP_CLASS_HID_0488, - .class_tid = 1, - .hdr_sig_id = 7, - .flow_sig_id = 8UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_7_BITMASK_O_ETH_SMAC } - }, - [335] = { - .class_hid = BNXT_ULP_CLASS_HID_04b5, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 8UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_SMAC } - }, - [336] = { - .class_hid = BNXT_ULP_CLASS_HID_1215, - .class_tid = 1, - .hdr_sig_id = 8, - .flow_sig_id = 72UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_8_BITMASK_OO_VLAN_VID } - }, - [337] = { - .class_hid = BNXT_ULP_CLASS_HID_04b9, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 8UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_SMAC } - }, - [338] = { - .class_hid = BNXT_ULP_CLASS_HID_1219, - .class_tid = 1, - .hdr_sig_id = 9, - .flow_sig_id = 72UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_9_BITMASK_OO_VLAN_VID } - }, - [339] = { - .class_hid = BNXT_ULP_CLASS_HID_0485, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 8UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_SMAC } - }, - [340] = { - .class_hid = BNXT_ULP_CLASS_HID_1225, - .class_tid = 1, - .hdr_sig_id = 10, - .flow_sig_id = 72UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_10_BITMASK_OO_VLAN_VID } - }, - [341] = { - .class_hid = BNXT_ULP_CLASS_HID_0489, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 8UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_SMAC } - }, - [342] = { - .class_hid = BNXT_ULP_CLASS_HID_1229, - .class_tid = 1, - .hdr_sig_id = 11, - .flow_sig_id = 72UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_1_11_BITMASK_OO_VLAN_VID } - }, - [343] = { - .class_hid = BNXT_ULP_CLASS_HID_0226, - .class_tid = 1, - .hdr_sig_id = 12, - .flow_sig_id = 16384UL, - .flow_pattern_id = 3, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_12_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_12_BITMASK_O_IPV4_DST_ADDR } - }, - [344] = { - .class_hid = BNXT_ULP_CLASS_HID_4045a, - .class_tid = 1, - .hdr_sig_id = 12, - .flow_sig_id = 81920UL, - .flow_pattern_id = 3, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_1_12_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_1_12_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_1_12_BITMASK_O_UDP_DST_PORT } - }, - [345] = { - .class_hid = BNXT_ULP_CLASS_HID_0daa, - .class_tid = 2, - .hdr_sig_id = 13, - .flow_sig_id = 20480UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_F1 | - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_13_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_13_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT } - }, - [346] = { - .class_hid = BNXT_ULP_CLASS_HID_11b0, - .class_tid = 2, - .hdr_sig_id = 13, - .flow_sig_id = 20488UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_F1 | - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_13_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_13_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_13_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT } - }, - [347] = { - .class_hid = BNXT_ULP_CLASS_HID_403f8, - .class_tid = 2, - .hdr_sig_id = 14, - .flow_sig_id = 81920UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_F1 | - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_14_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_14_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_14_BITMASK_O_UDP_DST_PORT } - }, - [348] = { - .class_hid = BNXT_ULP_CLASS_HID_4161e, - .class_tid = 2, - .hdr_sig_id = 14, - .flow_sig_id = 81928UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_F1 | - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_14_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_14_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_14_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_14_BITMASK_O_UDP_DST_PORT } - }, - [349] = { - .class_hid = BNXT_ULP_CLASS_HID_40439, - .class_tid = 2, - .hdr_sig_id = 15, - .flow_sig_id = 66304UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI } - }, - [350] = { - .class_hid = BNXT_ULP_CLASS_HID_41405, - .class_tid = 2, - .hdr_sig_id = 15, - .flow_sig_id = 68352UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI } - }, - [351] = { - .class_hid = BNXT_ULP_CLASS_HID_51449, - .class_tid = 2, - .hdr_sig_id = 15, - .flow_sig_id = 328448UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_DMAC } - }, - [352] = { - .class_hid = BNXT_ULP_CLASS_HID_50b33, - .class_tid = 2, - .hdr_sig_id = 15, - .flow_sig_id = 330496UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_DMAC } - }, - [353] = { - .class_hid = BNXT_ULP_CLASS_HID_48c01, - .class_tid = 2, - .hdr_sig_id = 15, - .flow_sig_id = 590592UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_SMAC } - }, - [354] = { - .class_hid = BNXT_ULP_CLASS_HID_483eb, - .class_tid = 2, - .hdr_sig_id = 15, - .flow_sig_id = 592640UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_SMAC } - }, - [355] = { - .class_hid = BNXT_ULP_CLASS_HID_5833f, - .class_tid = 2, - .hdr_sig_id = 15, - .flow_sig_id = 852736UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_SMAC } - }, - [356] = { - .class_hid = BNXT_ULP_CLASS_HID_5937b, - .class_tid = 2, - .hdr_sig_id = 15, - .flow_sig_id = 854784UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_SMAC } - }, - [357] = { - .class_hid = BNXT_ULP_CLASS_HID_41875, - .class_tid = 2, - .hdr_sig_id = 15, - .flow_sig_id = 134284032UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_15_BITMASK_I_IPV6_SRC_ADDR } - }, - [358] = { - .class_hid = BNXT_ULP_CLASS_HID_40f5f, - .class_tid = 2, - .hdr_sig_id = 15, - .flow_sig_id = 134286080UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_15_BITMASK_I_IPV6_SRC_ADDR } - }, - [359] = { - .class_hid = BNXT_ULP_CLASS_HID_50f23, - .class_tid = 2, - .hdr_sig_id = 15, - .flow_sig_id = 134546176UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_15_BITMASK_I_IPV6_SRC_ADDR } - }, - [360] = { - .class_hid = BNXT_ULP_CLASS_HID_51f6f, - .class_tid = 2, - .hdr_sig_id = 15, - .flow_sig_id = 134548224UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_15_BITMASK_I_IPV6_SRC_ADDR } - }, - [361] = { - .class_hid = BNXT_ULP_CLASS_HID_4875b, - .class_tid = 2, - .hdr_sig_id = 15, - .flow_sig_id = 134808320UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_15_BITMASK_I_IPV6_SRC_ADDR } - }, - [362] = { - .class_hid = BNXT_ULP_CLASS_HID_49727, - .class_tid = 2, - .hdr_sig_id = 15, - .flow_sig_id = 134810368UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_15_BITMASK_I_IPV6_SRC_ADDR } - }, - [363] = { - .class_hid = BNXT_ULP_CLASS_HID_5976b, - .class_tid = 2, - .hdr_sig_id = 15, - .flow_sig_id = 135070464UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_15_BITMASK_I_IPV6_SRC_ADDR } - }, - [364] = { - .class_hid = BNXT_ULP_CLASS_HID_58655, - .class_tid = 2, - .hdr_sig_id = 15, - .flow_sig_id = 135072512UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_15_BITMASK_I_IPV6_SRC_ADDR } - }, - [365] = { - .class_hid = BNXT_ULP_CLASS_HID_4125f, - .class_tid = 2, - .hdr_sig_id = 15, - .flow_sig_id = 268501760UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_15_BITMASK_I_IPV6_DST_ADDR } - }, - [366] = { - .class_hid = BNXT_ULP_CLASS_HID_401f9, - .class_tid = 2, - .hdr_sig_id = 15, - .flow_sig_id = 268503808UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_15_BITMASK_I_IPV6_DST_ADDR } - }, - [367] = { - .class_hid = BNXT_ULP_CLASS_HID_501cd, - .class_tid = 2, - .hdr_sig_id = 15, - .flow_sig_id = 268763904UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_15_BITMASK_I_IPV6_DST_ADDR } - }, - [368] = { - .class_hid = BNXT_ULP_CLASS_HID_51149, - .class_tid = 2, - .hdr_sig_id = 15, - .flow_sig_id = 268765952UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_15_BITMASK_I_IPV6_DST_ADDR } - }, - [369] = { - .class_hid = BNXT_ULP_CLASS_HID_49a67, - .class_tid = 2, - .hdr_sig_id = 15, - .flow_sig_id = 269026048UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_15_BITMASK_I_IPV6_DST_ADDR } - }, - [370] = { - .class_hid = BNXT_ULP_CLASS_HID_489c1, - .class_tid = 2, - .hdr_sig_id = 15, - .flow_sig_id = 269028096UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_15_BITMASK_I_IPV6_DST_ADDR } - }, - [371] = { - .class_hid = BNXT_ULP_CLASS_HID_58955, - .class_tid = 2, - .hdr_sig_id = 15, - .flow_sig_id = 269288192UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_15_BITMASK_I_IPV6_DST_ADDR } - }, - [372] = { - .class_hid = BNXT_ULP_CLASS_HID_59951, - .class_tid = 2, - .hdr_sig_id = 15, - .flow_sig_id = 269290240UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_15_BITMASK_I_IPV6_DST_ADDR } - }, - [373] = { - .class_hid = BNXT_ULP_CLASS_HID_40569, - .class_tid = 2, - .hdr_sig_id = 15, - .flow_sig_id = 402719488UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_15_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_I_IPV6_DST_ADDR } - }, - [374] = { - .class_hid = BNXT_ULP_CLASS_HID_41575, - .class_tid = 2, - .hdr_sig_id = 15, - .flow_sig_id = 402721536UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_15_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_I_IPV6_DST_ADDR } - }, - [375] = { - .class_hid = BNXT_ULP_CLASS_HID_51579, - .class_tid = 2, - .hdr_sig_id = 15, - .flow_sig_id = 402981632UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_15_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_I_IPV6_DST_ADDR } - }, - [376] = { - .class_hid = BNXT_ULP_CLASS_HID_50463, - .class_tid = 2, - .hdr_sig_id = 15, - .flow_sig_id = 402983680UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_15_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_I_IPV6_DST_ADDR } - }, - [377] = { - .class_hid = BNXT_ULP_CLASS_HID_48d71, - .class_tid = 2, - .hdr_sig_id = 15, - .flow_sig_id = 403243776UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_15_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_I_IPV6_DST_ADDR } - }, - [378] = { - .class_hid = BNXT_ULP_CLASS_HID_49d7d, - .class_tid = 2, - .hdr_sig_id = 15, - .flow_sig_id = 403245824UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_15_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_I_IPV6_DST_ADDR } - }, - [379] = { - .class_hid = BNXT_ULP_CLASS_HID_59d41, - .class_tid = 2, - .hdr_sig_id = 15, - .flow_sig_id = 403505920UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_15_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_I_IPV6_DST_ADDR } - }, - [380] = { - .class_hid = BNXT_ULP_CLASS_HID_58c6b, - .class_tid = 2, - .hdr_sig_id = 15, - .flow_sig_id = 403507968UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_15_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_15_BITMASK_I_IPV6_DST_ADDR } - }, - [381] = { - .class_hid = BNXT_ULP_CLASS_HID_10255, - .class_tid = 2, - .hdr_sig_id = 16, - .flow_sig_id = 265216UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_T_VXLAN_VNI } - }, - [382] = { - .class_hid = BNXT_ULP_CLASS_HID_11675, - .class_tid = 2, - .hdr_sig_id = 16, - .flow_sig_id = 273408UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_16_BITMASK_T_VXLAN_VNI } - }, - [383] = { - .class_hid = BNXT_ULP_CLASS_HID_14649, - .class_tid = 2, - .hdr_sig_id = 16, - .flow_sig_id = 1313792UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_16_BITMASK_I_ETH_DMAC } - }, - [384] = { - .class_hid = BNXT_ULP_CLASS_HID_15a69, - .class_tid = 2, - .hdr_sig_id = 16, - .flow_sig_id = 1321984UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_16_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_16_BITMASK_I_ETH_DMAC } - }, - [385] = { - .class_hid = BNXT_ULP_CLASS_HID_1205b, - .class_tid = 2, - .hdr_sig_id = 16, - .flow_sig_id = 2362368UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_16_BITMASK_I_ETH_SMAC } - }, - [386] = { - .class_hid = BNXT_ULP_CLASS_HID_1347b, - .class_tid = 2, - .hdr_sig_id = 16, - .flow_sig_id = 2370560UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_16_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_16_BITMASK_I_ETH_SMAC } - }, - [387] = { - .class_hid = BNXT_ULP_CLASS_HID_16bbf, - .class_tid = 2, - .hdr_sig_id = 16, - .flow_sig_id = 3410944UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_16_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_16_BITMASK_I_ETH_SMAC } - }, - [388] = { - .class_hid = BNXT_ULP_CLASS_HID_1785f, - .class_tid = 2, - .hdr_sig_id = 16, - .flow_sig_id = 3419136UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_16_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_16_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_16_BITMASK_I_ETH_SMAC } - }, - [389] = { - .class_hid = BNXT_ULP_CLASS_HID_11551, - .class_tid = 2, - .hdr_sig_id = 16, - .flow_sig_id = 537136128UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_16_BITMASK_I_IPV6_SRC_ADDR } - }, - [390] = { - .class_hid = BNXT_ULP_CLASS_HID_10897, - .class_tid = 2, - .hdr_sig_id = 16, - .flow_sig_id = 537144320UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_16_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_16_BITMASK_I_IPV6_SRC_ADDR } - }, - [391] = { - .class_hid = BNXT_ULP_CLASS_HID_15955, - .class_tid = 2, - .hdr_sig_id = 16, - .flow_sig_id = 538184704UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_16_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_16_BITMASK_I_IPV6_SRC_ADDR } - }, - [392] = { - .class_hid = BNXT_ULP_CLASS_HID_14c8b, - .class_tid = 2, - .hdr_sig_id = 16, - .flow_sig_id = 538192896UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_16_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_16_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_16_BITMASK_I_IPV6_SRC_ADDR } - }, - [393] = { - .class_hid = BNXT_ULP_CLASS_HID_13b47, - .class_tid = 2, - .hdr_sig_id = 16, - .flow_sig_id = 539233280UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_16_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_16_BITMASK_I_IPV6_SRC_ADDR } - }, - [394] = { - .class_hid = BNXT_ULP_CLASS_HID_12e85, - .class_tid = 2, - .hdr_sig_id = 16, - .flow_sig_id = 539241472UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_16_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_16_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_16_BITMASK_I_IPV6_SRC_ADDR } - }, - [395] = { - .class_hid = BNXT_ULP_CLASS_HID_17f5b, - .class_tid = 2, - .hdr_sig_id = 16, - .flow_sig_id = 540281856UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_16_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_16_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_16_BITMASK_I_IPV6_SRC_ADDR } - }, - [396] = { - .class_hid = BNXT_ULP_CLASS_HID_17299, - .class_tid = 2, - .hdr_sig_id = 16, - .flow_sig_id = 540290048UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_16_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_16_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_16_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_16_BITMASK_I_IPV6_SRC_ADDR } - }, - [397] = { - .class_hid = BNXT_ULP_CLASS_HID_10fe7, - .class_tid = 2, - .hdr_sig_id = 16, - .flow_sig_id = 1074007040UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_16_BITMASK_I_IPV6_DST_ADDR } - }, - [398] = { - .class_hid = BNXT_ULP_CLASS_HID_10325, - .class_tid = 2, - .hdr_sig_id = 16, - .flow_sig_id = 1074015232UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_16_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_16_BITMASK_I_IPV6_DST_ADDR } - }, - [399] = { - .class_hid = BNXT_ULP_CLASS_HID_153cb, - .class_tid = 2, - .hdr_sig_id = 16, - .flow_sig_id = 1075055616UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_16_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_16_BITMASK_I_IPV6_DST_ADDR } - }, - [400] = { - .class_hid = BNXT_ULP_CLASS_HID_14709, - .class_tid = 2, - .hdr_sig_id = 16, - .flow_sig_id = 1075063808UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_16_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_16_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_16_BITMASK_I_IPV6_DST_ADDR } - }, - [401] = { - .class_hid = BNXT_ULP_CLASS_HID_12dc5, - .class_tid = 2, - .hdr_sig_id = 16, - .flow_sig_id = 1076104192UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_16_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_16_BITMASK_I_IPV6_DST_ADDR } - }, - [402] = { - .class_hid = BNXT_ULP_CLASS_HID_1212b, - .class_tid = 2, - .hdr_sig_id = 16, - .flow_sig_id = 1076112384UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_16_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_16_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_16_BITMASK_I_IPV6_DST_ADDR } - }, - [403] = { - .class_hid = BNXT_ULP_CLASS_HID_171c9, - .class_tid = 2, - .hdr_sig_id = 16, - .flow_sig_id = 1077152768UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_16_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_16_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_16_BITMASK_I_IPV6_DST_ADDR } - }, - [404] = { - .class_hid = BNXT_ULP_CLASS_HID_1650f, - .class_tid = 2, - .hdr_sig_id = 16, - .flow_sig_id = 1077160960UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_16_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_16_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_16_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_16_BITMASK_I_IPV6_DST_ADDR } - }, - [405] = { - .class_hid = BNXT_ULP_CLASS_HID_10201, - .class_tid = 2, - .hdr_sig_id = 16, - .flow_sig_id = 1610877952UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_16_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_I_IPV6_DST_ADDR } - }, - [406] = { - .class_hid = BNXT_ULP_CLASS_HID_116c1, - .class_tid = 2, - .hdr_sig_id = 16, - .flow_sig_id = 1610886144UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_16_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_16_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_I_IPV6_DST_ADDR } - }, - [407] = { - .class_hid = BNXT_ULP_CLASS_HID_14605, - .class_tid = 2, - .hdr_sig_id = 16, - .flow_sig_id = 1611926528UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_16_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_16_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_I_IPV6_DST_ADDR } - }, - [408] = { - .class_hid = BNXT_ULP_CLASS_HID_15a05, - .class_tid = 2, - .hdr_sig_id = 16, - .flow_sig_id = 1611934720UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_16_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_16_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_16_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_I_IPV6_DST_ADDR } - }, - [409] = { - .class_hid = BNXT_ULP_CLASS_HID_12007, - .class_tid = 2, - .hdr_sig_id = 16, - .flow_sig_id = 1612975104UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_16_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_16_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_I_IPV6_DST_ADDR } - }, - [410] = { - .class_hid = BNXT_ULP_CLASS_HID_13407, - .class_tid = 2, - .hdr_sig_id = 16, - .flow_sig_id = 1612983296UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_16_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_16_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_16_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_I_IPV6_DST_ADDR } - }, - [411] = { - .class_hid = BNXT_ULP_CLASS_HID_1640b, - .class_tid = 2, - .hdr_sig_id = 16, - .flow_sig_id = 1614023680UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_16_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_16_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_16_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_I_IPV6_DST_ADDR } - }, - [412] = { - .class_hid = BNXT_ULP_CLASS_HID_1780b, - .class_tid = 2, - .hdr_sig_id = 16, - .flow_sig_id = 1614031872UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_16_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_16_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_16_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_16_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_16_BITMASK_I_IPV6_DST_ADDR } - }, - [413] = { - .class_hid = BNXT_ULP_CLASS_HID_404b0, - .class_tid = 2, - .hdr_sig_id = 17, - .flow_sig_id = 66304UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_T_VXLAN_VNI } - }, - [414] = { - .class_hid = BNXT_ULP_CLASS_HID_4148c, - .class_tid = 2, - .hdr_sig_id = 17, - .flow_sig_id = 68352UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_17_BITMASK_T_VXLAN_VNI } - }, - [415] = { - .class_hid = BNXT_ULP_CLASS_HID_514c0, - .class_tid = 2, - .hdr_sig_id = 17, - .flow_sig_id = 328448UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_17_BITMASK_I_ETH_DMAC } - }, - [416] = { - .class_hid = BNXT_ULP_CLASS_HID_50bba, - .class_tid = 2, - .hdr_sig_id = 17, - .flow_sig_id = 330496UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_17_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_17_BITMASK_I_ETH_DMAC } - }, - [417] = { - .class_hid = BNXT_ULP_CLASS_HID_48c88, - .class_tid = 2, - .hdr_sig_id = 17, - .flow_sig_id = 590592UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_17_BITMASK_I_ETH_SMAC } - }, - [418] = { - .class_hid = BNXT_ULP_CLASS_HID_48362, - .class_tid = 2, - .hdr_sig_id = 17, - .flow_sig_id = 592640UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_17_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_17_BITMASK_I_ETH_SMAC } - }, - [419] = { - .class_hid = BNXT_ULP_CLASS_HID_583b6, - .class_tid = 2, - .hdr_sig_id = 17, - .flow_sig_id = 852736UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_17_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_17_BITMASK_I_ETH_SMAC } - }, - [420] = { - .class_hid = BNXT_ULP_CLASS_HID_593f2, - .class_tid = 2, - .hdr_sig_id = 17, - .flow_sig_id = 854784UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_17_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_17_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_17_BITMASK_I_ETH_SMAC } - }, - [421] = { - .class_hid = BNXT_ULP_CLASS_HID_41f54, - .class_tid = 2, - .hdr_sig_id = 17, - .flow_sig_id = 536937216UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_17_BITMASK_I_IPV4_SRC_ADDR } - }, - [422] = { - .class_hid = BNXT_ULP_CLASS_HID_40fce, - .class_tid = 2, - .hdr_sig_id = 17, - .flow_sig_id = 536939264UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_17_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_17_BITMASK_I_IPV4_SRC_ADDR } - }, - [423] = { - .class_hid = BNXT_ULP_CLASS_HID_50e02, - .class_tid = 2, - .hdr_sig_id = 17, - .flow_sig_id = 537199360UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_17_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_17_BITMASK_I_IPV4_SRC_ADDR } - }, - [424] = { - .class_hid = BNXT_ULP_CLASS_HID_51e5e, - .class_tid = 2, - .hdr_sig_id = 17, - .flow_sig_id = 537201408UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_17_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_17_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_17_BITMASK_I_IPV4_SRC_ADDR } - }, - [425] = { - .class_hid = BNXT_ULP_CLASS_HID_487ca, - .class_tid = 2, - .hdr_sig_id = 17, - .flow_sig_id = 537461504UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_17_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_17_BITMASK_I_IPV4_SRC_ADDR } - }, - [426] = { - .class_hid = BNXT_ULP_CLASS_HID_49606, - .class_tid = 2, - .hdr_sig_id = 17, - .flow_sig_id = 537463552UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_17_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_17_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_17_BITMASK_I_IPV4_SRC_ADDR } - }, - [427] = { - .class_hid = BNXT_ULP_CLASS_HID_5965a, - .class_tid = 2, - .hdr_sig_id = 17, - .flow_sig_id = 537723648UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_17_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_17_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_17_BITMASK_I_IPV4_SRC_ADDR } - }, - [428] = { - .class_hid = BNXT_ULP_CLASS_HID_58514, - .class_tid = 2, - .hdr_sig_id = 17, - .flow_sig_id = 537725696UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_17_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_17_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_17_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_17_BITMASK_I_IPV4_SRC_ADDR } - }, - [429] = { - .class_hid = BNXT_ULP_CLASS_HID_412c2, - .class_tid = 2, - .hdr_sig_id = 17, - .flow_sig_id = 1073808128UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_17_BITMASK_I_IPV4_DST_ADDR } - }, - [430] = { - .class_hid = BNXT_ULP_CLASS_HID_401ac, - .class_tid = 2, - .hdr_sig_id = 17, - .flow_sig_id = 1073810176UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_17_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_17_BITMASK_I_IPV4_DST_ADDR } - }, - [431] = { - .class_hid = BNXT_ULP_CLASS_HID_501e0, - .class_tid = 2, - .hdr_sig_id = 17, - .flow_sig_id = 1074070272UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_17_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_17_BITMASK_I_IPV4_DST_ADDR } - }, - [432] = { - .class_hid = BNXT_ULP_CLASS_HID_511cc, - .class_tid = 2, - .hdr_sig_id = 17, - .flow_sig_id = 1074072320UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_17_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_17_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_17_BITMASK_I_IPV4_DST_ADDR } - }, - [433] = { - .class_hid = BNXT_ULP_CLASS_HID_4990a, - .class_tid = 2, - .hdr_sig_id = 17, - .flow_sig_id = 1074332416UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_17_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_17_BITMASK_I_IPV4_DST_ADDR } - }, - [434] = { - .class_hid = BNXT_ULP_CLASS_HID_489e4, - .class_tid = 2, - .hdr_sig_id = 17, - .flow_sig_id = 1074334464UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_17_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_17_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_17_BITMASK_I_IPV4_DST_ADDR } - }, - [435] = { - .class_hid = BNXT_ULP_CLASS_HID_589c8, - .class_tid = 2, - .hdr_sig_id = 17, - .flow_sig_id = 1074594560UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_17_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_17_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_17_BITMASK_I_IPV4_DST_ADDR } - }, - [436] = { - .class_hid = BNXT_ULP_CLASS_HID_59804, - .class_tid = 2, - .hdr_sig_id = 17, - .flow_sig_id = 1074596608UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_17_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_17_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_17_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_17_BITMASK_I_IPV4_DST_ADDR } - }, - [437] = { - .class_hid = BNXT_ULP_CLASS_HID_40404, - .class_tid = 2, - .hdr_sig_id = 17, - .flow_sig_id = 1610679040UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_17_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_I_IPV4_DST_ADDR } - }, - [438] = { - .class_hid = BNXT_ULP_CLASS_HID_41440, - .class_tid = 2, - .hdr_sig_id = 17, - .flow_sig_id = 1610681088UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_17_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_17_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_I_IPV4_DST_ADDR } - }, - [439] = { - .class_hid = BNXT_ULP_CLASS_HID_51484, - .class_tid = 2, - .hdr_sig_id = 17, - .flow_sig_id = 1610941184UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_17_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_17_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_I_IPV4_DST_ADDR } - }, - [440] = { - .class_hid = BNXT_ULP_CLASS_HID_50b0e, - .class_tid = 2, - .hdr_sig_id = 17, - .flow_sig_id = 1610943232UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_17_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_17_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_17_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_I_IPV4_DST_ADDR } - }, - [441] = { - .class_hid = BNXT_ULP_CLASS_HID_48c4c, - .class_tid = 2, - .hdr_sig_id = 17, - .flow_sig_id = 1611203328UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_17_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_17_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_I_IPV4_DST_ADDR } - }, - [442] = { - .class_hid = BNXT_ULP_CLASS_HID_48306, - .class_tid = 2, - .hdr_sig_id = 17, - .flow_sig_id = 1611205376UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_17_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_17_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_17_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_I_IPV4_DST_ADDR } - }, - [443] = { - .class_hid = BNXT_ULP_CLASS_HID_5830a, - .class_tid = 2, - .hdr_sig_id = 17, - .flow_sig_id = 1611465472UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_17_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_17_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_17_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_I_IPV4_DST_ADDR } - }, - [444] = { - .class_hid = BNXT_ULP_CLASS_HID_59346, - .class_tid = 2, - .hdr_sig_id = 17, - .flow_sig_id = 1611467520UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_17_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_17_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_17_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_17_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_17_BITMASK_I_IPV4_DST_ADDR } - }, - [445] = { - .class_hid = BNXT_ULP_CLASS_HID_102cc, - .class_tid = 2, - .hdr_sig_id = 18, - .flow_sig_id = 265216UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_T_VXLAN_VNI } - }, - [446] = { - .class_hid = BNXT_ULP_CLASS_HID_116ec, - .class_tid = 2, - .hdr_sig_id = 18, - .flow_sig_id = 273408UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_18_BITMASK_T_VXLAN_VNI } - }, - [447] = { - .class_hid = BNXT_ULP_CLASS_HID_146d0, - .class_tid = 2, - .hdr_sig_id = 18, - .flow_sig_id = 1313792UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_18_BITMASK_I_ETH_DMAC } - }, - [448] = { - .class_hid = BNXT_ULP_CLASS_HID_15af0, - .class_tid = 2, - .hdr_sig_id = 18, - .flow_sig_id = 1321984UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_18_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_18_BITMASK_I_ETH_DMAC } - }, - [449] = { - .class_hid = BNXT_ULP_CLASS_HID_120c2, - .class_tid = 2, - .hdr_sig_id = 18, - .flow_sig_id = 2362368UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_18_BITMASK_I_ETH_SMAC } - }, - [450] = { - .class_hid = BNXT_ULP_CLASS_HID_134e2, - .class_tid = 2, - .hdr_sig_id = 18, - .flow_sig_id = 2370560UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_18_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_18_BITMASK_I_ETH_SMAC } - }, - [451] = { - .class_hid = BNXT_ULP_CLASS_HID_16b26, - .class_tid = 2, - .hdr_sig_id = 18, - .flow_sig_id = 3410944UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_18_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_18_BITMASK_I_ETH_SMAC } - }, - [452] = { - .class_hid = BNXT_ULP_CLASS_HID_178c6, - .class_tid = 2, - .hdr_sig_id = 18, - .flow_sig_id = 3419136UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_18_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_18_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_18_BITMASK_I_ETH_SMAC } - }, - [453] = { - .class_hid = BNXT_ULP_CLASS_HID_115c6, - .class_tid = 2, - .hdr_sig_id = 18, - .flow_sig_id = 2147748864UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_18_BITMASK_I_IPV4_SRC_ADDR } - }, - [454] = { - .class_hid = BNXT_ULP_CLASS_HID_10804, - .class_tid = 2, - .hdr_sig_id = 18, - .flow_sig_id = 2147757056UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_18_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_18_BITMASK_I_IPV4_SRC_ADDR } - }, - [455] = { - .class_hid = BNXT_ULP_CLASS_HID_15822, - .class_tid = 2, - .hdr_sig_id = 18, - .flow_sig_id = 2148797440UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_18_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_18_BITMASK_I_IPV4_SRC_ADDR } - }, - [456] = { - .class_hid = BNXT_ULP_CLASS_HID_14c60, - .class_tid = 2, - .hdr_sig_id = 18, - .flow_sig_id = 2148805632UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_18_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_18_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_18_BITMASK_I_IPV4_SRC_ADDR } - }, - [457] = { - .class_hid = BNXT_ULP_CLASS_HID_13bd4, - .class_tid = 2, - .hdr_sig_id = 18, - .flow_sig_id = 2149846016UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_18_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_18_BITMASK_I_IPV4_SRC_ADDR } - }, - [458] = { - .class_hid = BNXT_ULP_CLASS_HID_12e12, - .class_tid = 2, - .hdr_sig_id = 18, - .flow_sig_id = 2149854208UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_18_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_18_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_18_BITMASK_I_IPV4_SRC_ADDR } - }, - [459] = { - .class_hid = BNXT_ULP_CLASS_HID_17e30, - .class_tid = 2, - .hdr_sig_id = 18, - .flow_sig_id = 2150894592UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_18_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_18_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_18_BITMASK_I_IPV4_SRC_ADDR } - }, - [460] = { - .class_hid = BNXT_ULP_CLASS_HID_17276, - .class_tid = 2, - .hdr_sig_id = 18, - .flow_sig_id = 2150902784UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_18_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_18_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_18_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_18_BITMASK_I_IPV4_SRC_ADDR } - }, - [461] = { - .class_hid = BNXT_ULP_CLASS_HID_11f1a, - .class_tid = 2, - .hdr_sig_id = 18, - .flow_sig_id = 4295232512UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_18_BITMASK_I_IPV4_DST_ADDR } - }, - [462] = { - .class_hid = BNXT_ULP_CLASS_HID_11358, - .class_tid = 2, - .hdr_sig_id = 18, - .flow_sig_id = 4295240704UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_18_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_18_BITMASK_I_IPV4_DST_ADDR } - }, - [463] = { - .class_hid = BNXT_ULP_CLASS_HID_14398, - .class_tid = 2, - .hdr_sig_id = 18, - .flow_sig_id = 4296281088UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_18_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_18_BITMASK_I_IPV4_DST_ADDR } - }, - [464] = { - .class_hid = BNXT_ULP_CLASS_HID_157b8, - .class_tid = 2, - .hdr_sig_id = 18, - .flow_sig_id = 4296289280UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_18_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_18_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_18_BITMASK_I_IPV4_DST_ADDR } - }, - [465] = { - .class_hid = BNXT_ULP_CLASS_HID_13d68, - .class_tid = 2, - .hdr_sig_id = 18, - .flow_sig_id = 4297329664UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_18_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_18_BITMASK_I_IPV4_DST_ADDR } - }, - [466] = { - .class_hid = BNXT_ULP_CLASS_HID_131aa, - .class_tid = 2, - .hdr_sig_id = 18, - .flow_sig_id = 4297337856UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_18_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_18_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_18_BITMASK_I_IPV4_DST_ADDR } - }, - [467] = { - .class_hid = BNXT_ULP_CLASS_HID_16192, - .class_tid = 2, - .hdr_sig_id = 18, - .flow_sig_id = 4298378240UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_18_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_18_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_18_BITMASK_I_IPV4_DST_ADDR } - }, - [468] = { - .class_hid = BNXT_ULP_CLASS_HID_175b2, - .class_tid = 2, - .hdr_sig_id = 18, - .flow_sig_id = 4298386432UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_18_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_18_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_18_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_18_BITMASK_I_IPV4_DST_ADDR } - }, - [469] = { - .class_hid = BNXT_ULP_CLASS_HID_112b2, - .class_tid = 2, - .hdr_sig_id = 18, - .flow_sig_id = 6442716160UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_18_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_I_IPV4_DST_ADDR } - }, - [470] = { - .class_hid = BNXT_ULP_CLASS_HID_106f0, - .class_tid = 2, - .hdr_sig_id = 18, - .flow_sig_id = 6442724352UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_18_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_18_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_I_IPV4_DST_ADDR } - }, - [471] = { - .class_hid = BNXT_ULP_CLASS_HID_15692, - .class_tid = 2, - .hdr_sig_id = 18, - .flow_sig_id = 6443764736UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_18_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_18_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_I_IPV4_DST_ADDR } - }, - [472] = { - .class_hid = BNXT_ULP_CLASS_HID_14ad0, - .class_tid = 2, - .hdr_sig_id = 18, - .flow_sig_id = 6443772928UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_18_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_18_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_18_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_I_IPV4_DST_ADDR } - }, - [473] = { - .class_hid = BNXT_ULP_CLASS_HID_13080, - .class_tid = 2, - .hdr_sig_id = 18, - .flow_sig_id = 6444813312UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_18_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_18_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_I_IPV4_DST_ADDR } - }, - [474] = { - .class_hid = BNXT_ULP_CLASS_HID_124c2, - .class_tid = 2, - .hdr_sig_id = 18, - .flow_sig_id = 6444821504UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_18_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_18_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_18_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_I_IPV4_DST_ADDR } - }, - [475] = { - .class_hid = BNXT_ULP_CLASS_HID_174e0, - .class_tid = 2, - .hdr_sig_id = 18, - .flow_sig_id = 6445861888UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_18_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_18_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_18_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_I_IPV4_DST_ADDR } - }, - [476] = { - .class_hid = BNXT_ULP_CLASS_HID_16f22, - .class_tid = 2, - .hdr_sig_id = 18, - .flow_sig_id = 6445870080UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_18_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_18_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_18_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_18_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_18_BITMASK_I_IPV4_DST_ADDR } - }, - [477] = { - .class_hid = BNXT_ULP_CLASS_HID_4025b, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 66304UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI } - }, - [478] = { - .class_hid = BNXT_ULP_CLASS_HID_41267, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 68352UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI } - }, - [479] = { - .class_hid = BNXT_ULP_CLASS_HID_5122b, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 328448UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC } - }, - [480] = { - .class_hid = BNXT_ULP_CLASS_HID_50d51, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 330496UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC } - }, - [481] = { - .class_hid = BNXT_ULP_CLASS_HID_48a63, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 590592UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC } - }, - [482] = { - .class_hid = BNXT_ULP_CLASS_HID_48589, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 592640UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC } - }, - [483] = { - .class_hid = BNXT_ULP_CLASS_HID_5855d, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 852736UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC } - }, - [484] = { - .class_hid = BNXT_ULP_CLASS_HID_59519, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 854784UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC } - }, - [485] = { - .class_hid = BNXT_ULP_CLASS_HID_41e17, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 134284032UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR } - }, - [486] = { - .class_hid = BNXT_ULP_CLASS_HID_4093d, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 134286080UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR } - }, - [487] = { - .class_hid = BNXT_ULP_CLASS_HID_50941, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 134546176UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR } - }, - [488] = { - .class_hid = BNXT_ULP_CLASS_HID_5190d, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 134548224UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR } - }, - [489] = { - .class_hid = BNXT_ULP_CLASS_HID_48139, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 134808320UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR } - }, - [490] = { - .class_hid = BNXT_ULP_CLASS_HID_49145, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 134810368UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR } - }, - [491] = { - .class_hid = BNXT_ULP_CLASS_HID_59109, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 135070464UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR } - }, - [492] = { - .class_hid = BNXT_ULP_CLASS_HID_58037, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 135072512UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR } - }, - [493] = { - .class_hid = BNXT_ULP_CLASS_HID_4143d, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 268501760UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR } - }, - [494] = { - .class_hid = BNXT_ULP_CLASS_HID_4079b, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 268503808UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR } - }, - [495] = { - .class_hid = BNXT_ULP_CLASS_HID_507af, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 268763904UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR } - }, - [496] = { - .class_hid = BNXT_ULP_CLASS_HID_5172b, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 268765952UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR } - }, - [497] = { - .class_hid = BNXT_ULP_CLASS_HID_49c05, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 269026048UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR } - }, - [498] = { - .class_hid = BNXT_ULP_CLASS_HID_48fa3, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 269028096UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR } - }, - [499] = { - .class_hid = BNXT_ULP_CLASS_HID_58f37, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 269288192UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR } - }, - [500] = { - .class_hid = BNXT_ULP_CLASS_HID_59f33, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 269290240UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR } - }, - [501] = { - .class_hid = BNXT_ULP_CLASS_HID_4030b, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 402719488UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR } - }, - [502] = { - .class_hid = BNXT_ULP_CLASS_HID_41317, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 402721536UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR } - }, - [503] = { - .class_hid = BNXT_ULP_CLASS_HID_5131b, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 402981632UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR } - }, - [504] = { - .class_hid = BNXT_ULP_CLASS_HID_50201, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 402983680UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR } - }, - [505] = { - .class_hid = BNXT_ULP_CLASS_HID_48b13, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 403243776UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR } - }, - [506] = { - .class_hid = BNXT_ULP_CLASS_HID_49b1f, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 403245824UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR } - }, - [507] = { - .class_hid = BNXT_ULP_CLASS_HID_59b23, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 403505920UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR } - }, - [508] = { - .class_hid = BNXT_ULP_CLASS_HID_58a09, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 403507968UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR } - }, - [509] = { - .class_hid = BNXT_ULP_CLASS_HID_419bf, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 536937216UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT } - }, - [510] = { - .class_hid = BNXT_ULP_CLASS_HID_40925, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 536939264UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT } - }, - [511] = { - .class_hid = BNXT_ULP_CLASS_HID_508e9, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 537199360UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT } - }, - [512] = { - .class_hid = BNXT_ULP_CLASS_HID_518b5, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 537201408UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT } - }, - [513] = { - .class_hid = BNXT_ULP_CLASS_HID_48121, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 537461504UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT } - }, - [514] = { - .class_hid = BNXT_ULP_CLASS_HID_490ed, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 537463552UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT } - }, - [515] = { - .class_hid = BNXT_ULP_CLASS_HID_590b1, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 537723648UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT } - }, - [516] = { - .class_hid = BNXT_ULP_CLASS_HID_583ff, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 537725696UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT } - }, - [517] = { - .class_hid = BNXT_ULP_CLASS_HID_41475, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 671154944UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT } - }, - [518] = { - .class_hid = BNXT_ULP_CLASS_HID_40473, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 671156992UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT } - }, - [519] = { - .class_hid = BNXT_ULP_CLASS_HID_50427, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 671417088UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT } - }, - [520] = { - .class_hid = BNXT_ULP_CLASS_HID_51763, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 671419136UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT } - }, - [521] = { - .class_hid = BNXT_ULP_CLASS_HID_49c3d, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 671679232UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT } - }, - [522] = { - .class_hid = BNXT_ULP_CLASS_HID_48c3b, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 671681280UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT } - }, - [523] = { - .class_hid = BNXT_ULP_CLASS_HID_58f6f, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 671941376UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT } - }, - [524] = { - .class_hid = BNXT_ULP_CLASS_HID_59f2b, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 671943424UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT } - }, - [525] = { - .class_hid = BNXT_ULP_CLASS_HID_40333, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 805372672UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT } - }, - [526] = { - .class_hid = BNXT_ULP_CLASS_HID_412bf, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 805374720UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT } - }, - [527] = { - .class_hid = BNXT_ULP_CLASS_HID_512a3, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 805634816UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT } - }, - [528] = { - .class_hid = BNXT_ULP_CLASS_HID_50229, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 805636864UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT } - }, - [529] = { - .class_hid = BNXT_ULP_CLASS_HID_48abb, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 805896960UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT } - }, - [530] = { - .class_hid = BNXT_ULP_CLASS_HID_49aa7, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 805899008UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT } - }, - [531] = { - .class_hid = BNXT_ULP_CLASS_HID_59a2b, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 806159104UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT } - }, - [532] = { - .class_hid = BNXT_ULP_CLASS_HID_595b1, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 806161152UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT } - }, - [533] = { - .class_hid = BNXT_ULP_CLASS_HID_41e2f, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 939590400UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT } - }, - [534] = { - .class_hid = BNXT_ULP_CLASS_HID_40e35, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 939592448UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT } - }, - [535] = { - .class_hid = BNXT_ULP_CLASS_HID_50939, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 939852544UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT } - }, - [536] = { - .class_hid = BNXT_ULP_CLASS_HID_51925, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 939854592UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT } - }, - [537] = { - .class_hid = BNXT_ULP_CLASS_HID_48631, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 940114688UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT } - }, - [538] = { - .class_hid = BNXT_ULP_CLASS_HID_4913d, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 940116736UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT } - }, - [539] = { - .class_hid = BNXT_ULP_CLASS_HID_59121, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 940376832UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT } - }, - [540] = { - .class_hid = BNXT_ULP_CLASS_HID_5812f, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 940378880UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT } - }, - [541] = { - .class_hid = BNXT_ULP_CLASS_HID_41429, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 1073808128UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [542] = { - .class_hid = BNXT_ULP_CLASS_HID_40747, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 1073810176UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [543] = { - .class_hid = BNXT_ULP_CLASS_HID_5070b, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 1074070272UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [544] = { - .class_hid = BNXT_ULP_CLASS_HID_51727, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 1074072320UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [545] = { - .class_hid = BNXT_ULP_CLASS_HID_49fe1, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 1074332416UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [546] = { - .class_hid = BNXT_ULP_CLASS_HID_48f0f, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 1074334464UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [547] = { - .class_hid = BNXT_ULP_CLASS_HID_58f23, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 1074594560UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [548] = { - .class_hid = BNXT_ULP_CLASS_HID_59eef, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 1074596608UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [549] = { - .class_hid = BNXT_ULP_CLASS_HID_40347, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 1208025856UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [550] = { - .class_hid = BNXT_ULP_CLASS_HID_41303, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 1208027904UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [551] = { - .class_hid = BNXT_ULP_CLASS_HID_51247, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 1208288000UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [552] = { - .class_hid = BNXT_ULP_CLASS_HID_5026d, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 1208290048UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [553] = { - .class_hid = BNXT_ULP_CLASS_HID_48b0f, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 1208550144UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [554] = { - .class_hid = BNXT_ULP_CLASS_HID_49a4b, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 1208552192UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [555] = { - .class_hid = BNXT_ULP_CLASS_HID_59a0f, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 1208812288UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [556] = { - .class_hid = BNXT_ULP_CLASS_HID_58a05, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 1208814336UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [557] = { - .class_hid = BNXT_ULP_CLASS_HID_41983, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 1342243584UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [558] = { - .class_hid = BNXT_ULP_CLASS_HID_40929, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 1342245632UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [559] = { - .class_hid = BNXT_ULP_CLASS_HID_5092d, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 1342505728UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [560] = { - .class_hid = BNXT_ULP_CLASS_HID_518a9, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 1342507776UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [561] = { - .class_hid = BNXT_ULP_CLASS_HID_48125, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 1342767872UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [562] = { - .class_hid = BNXT_ULP_CLASS_HID_49121, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 1342769920UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [563] = { - .class_hid = BNXT_ULP_CLASS_HID_59085, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 1343030016UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [564] = { - .class_hid = BNXT_ULP_CLASS_HID_58023, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 1343032064UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [565] = { - .class_hid = BNXT_ULP_CLASS_HID_41509, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 1476461312UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [566] = { - .class_hid = BNXT_ULP_CLASS_HID_40407, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 1476463360UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [567] = { - .class_hid = BNXT_ULP_CLASS_HID_5040b, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 1476723456UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [568] = { - .class_hid = BNXT_ULP_CLASS_HID_51407, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 1476725504UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [569] = { - .class_hid = BNXT_ULP_CLASS_HID_49d21, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 1476985600UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [570] = { - .class_hid = BNXT_ULP_CLASS_HID_48c0f, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 1476987648UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [571] = { - .class_hid = BNXT_ULP_CLASS_HID_58c03, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 1477247744UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [572] = { - .class_hid = BNXT_ULP_CLASS_HID_59f0f, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 1477249792UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [573] = { - .class_hid = BNXT_ULP_CLASS_HID_402ef, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 1610679040UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [574] = { - .class_hid = BNXT_ULP_CLASS_HID_412ab, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 1610681088UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [575] = { - .class_hid = BNXT_ULP_CLASS_HID_5126f, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 1610941184UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [576] = { - .class_hid = BNXT_ULP_CLASS_HID_50de5, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 1610943232UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [577] = { - .class_hid = BNXT_ULP_CLASS_HID_48aa7, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 1611203328UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [578] = { - .class_hid = BNXT_ULP_CLASS_HID_485ed, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 1611205376UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [579] = { - .class_hid = BNXT_ULP_CLASS_HID_585e1, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 1611465472UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [580] = { - .class_hid = BNXT_ULP_CLASS_HID_595ad, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 1611467520UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [581] = { - .class_hid = BNXT_ULP_CLASS_HID_41e6b, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 1744896768UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [582] = { - .class_hid = BNXT_ULP_CLASS_HID_40961, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 1744898816UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [583] = { - .class_hid = BNXT_ULP_CLASS_HID_50925, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 1745158912UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [584] = { - .class_hid = BNXT_ULP_CLASS_HID_51961, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 1745160960UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [585] = { - .class_hid = BNXT_ULP_CLASS_HID_4816d, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 1745421056UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [586] = { - .class_hid = BNXT_ULP_CLASS_HID_49129, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 1745423104UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [587] = { - .class_hid = BNXT_ULP_CLASS_HID_5916d, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 1745683200UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [588] = { - .class_hid = BNXT_ULP_CLASS_HID_5806b, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 1745685248UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [589] = { - .class_hid = BNXT_ULP_CLASS_HID_414a1, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 1879114496UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [590] = { - .class_hid = BNXT_ULP_CLASS_HID_4042f, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 1879116544UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [591] = { - .class_hid = BNXT_ULP_CLASS_HID_507a3, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 1879376640UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [592] = { - .class_hid = BNXT_ULP_CLASS_HID_517af, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 1879378688UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [593] = { - .class_hid = BNXT_ULP_CLASS_HID_49c29, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 1879638784UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [594] = { - .class_hid = BNXT_ULP_CLASS_HID_48fa7, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 1879640832UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [595] = { - .class_hid = BNXT_ULP_CLASS_HID_58fab, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 1879900928UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [596] = { - .class_hid = BNXT_ULP_CLASS_HID_59f27, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 1879902976UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [597] = { - .class_hid = BNXT_ULP_CLASS_HID_4032f, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 2013332224UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [598] = { - .class_hid = BNXT_ULP_CLASS_HID_4132b, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 2013334272UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [599] = { - .class_hid = BNXT_ULP_CLASS_HID_5132f, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 2013594368UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [600] = { - .class_hid = BNXT_ULP_CLASS_HID_50225, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 2013596416UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [601] = { - .class_hid = BNXT_ULP_CLASS_HID_48b27, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 2013856512UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [602] = { - .class_hid = BNXT_ULP_CLASS_HID_49b23, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 2013858560UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [603] = { - .class_hid = BNXT_ULP_CLASS_HID_59b27, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 2014118656UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [604] = { - .class_hid = BNXT_ULP_CLASS_HID_58a2d, - .class_tid = 2, - .hdr_sig_id = 19, - .flow_sig_id = 2014120704UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT } - }, - [605] = { - .class_hid = BNXT_ULP_CLASS_HID_10437, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 265216UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI } - }, - [606] = { - .class_hid = BNXT_ULP_CLASS_HID_11017, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 273408UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI } - }, - [607] = { - .class_hid = BNXT_ULP_CLASS_HID_1402b, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 1313792UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC } - }, - [608] = { - .class_hid = BNXT_ULP_CLASS_HID_15c0b, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 1321984UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC } - }, - [609] = { - .class_hid = BNXT_ULP_CLASS_HID_12639, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 2362368UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC } - }, - [610] = { - .class_hid = BNXT_ULP_CLASS_HID_13219, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 2370560UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC } - }, - [611] = { - .class_hid = BNXT_ULP_CLASS_HID_16ddd, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 3410944UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC } - }, - [612] = { - .class_hid = BNXT_ULP_CLASS_HID_17e3d, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 3419136UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC } - }, - [613] = { - .class_hid = BNXT_ULP_CLASS_HID_11333, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 537136128UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR } - }, - [614] = { - .class_hid = BNXT_ULP_CLASS_HID_10ef5, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 537144320UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR } - }, - [615] = { - .class_hid = BNXT_ULP_CLASS_HID_15f37, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 538184704UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR } - }, - [616] = { - .class_hid = BNXT_ULP_CLASS_HID_14ae9, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 538192896UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR } - }, - [617] = { - .class_hid = BNXT_ULP_CLASS_HID_13d25, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 539233280UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR } - }, - [618] = { - .class_hid = BNXT_ULP_CLASS_HID_128e7, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 539241472UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR } - }, - [619] = { - .class_hid = BNXT_ULP_CLASS_HID_17939, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 540281856UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR } - }, - [620] = { - .class_hid = BNXT_ULP_CLASS_HID_174fb, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 540290048UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR } - }, - [621] = { - .class_hid = BNXT_ULP_CLASS_HID_10985, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 1074007040UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR } - }, - [622] = { - .class_hid = BNXT_ULP_CLASS_HID_10547, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 1074015232UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR } - }, - [623] = { - .class_hid = BNXT_ULP_CLASS_HID_155a9, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 1075055616UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR } - }, - [624] = { - .class_hid = BNXT_ULP_CLASS_HID_1416b, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 1075063808UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR } - }, - [625] = { - .class_hid = BNXT_ULP_CLASS_HID_12ba7, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 1076104192UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR } - }, - [626] = { - .class_hid = BNXT_ULP_CLASS_HID_12749, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 1076112384UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR } - }, - [627] = { - .class_hid = BNXT_ULP_CLASS_HID_177ab, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 1077152768UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR } - }, - [628] = { - .class_hid = BNXT_ULP_CLASS_HID_1636d, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 1077160960UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR } - }, - [629] = { - .class_hid = BNXT_ULP_CLASS_HID_10463, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 1610877952UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR } - }, - [630] = { - .class_hid = BNXT_ULP_CLASS_HID_110a3, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 1610886144UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR } - }, - [631] = { - .class_hid = BNXT_ULP_CLASS_HID_14067, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 1611926528UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR } - }, - [632] = { - .class_hid = BNXT_ULP_CLASS_HID_15c67, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 1611934720UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR } - }, - [633] = { - .class_hid = BNXT_ULP_CLASS_HID_12665, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 1612975104UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR } - }, - [634] = { - .class_hid = BNXT_ULP_CLASS_HID_13265, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 1612983296UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR } - }, - [635] = { - .class_hid = BNXT_ULP_CLASS_HID_16269, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 1614023680UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR } - }, - [636] = { - .class_hid = BNXT_ULP_CLASS_HID_17e69, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 1614031872UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR } - }, - [637] = { - .class_hid = BNXT_ULP_CLASS_HID_1133d, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 2147748864UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT } - }, - [638] = { - .class_hid = BNXT_ULP_CLASS_HID_10eff, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 2147757056UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT } - }, - [639] = { - .class_hid = BNXT_ULP_CLASS_HID_15ed9, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 2148797440UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT } - }, - [640] = { - .class_hid = BNXT_ULP_CLASS_HID_14a9b, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 2148805632UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT } - }, - [641] = { - .class_hid = BNXT_ULP_CLASS_HID_13d2f, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 2149846016UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT } - }, - [642] = { - .class_hid = BNXT_ULP_CLASS_HID_128e9, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 2149854208UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT } - }, - [643] = { - .class_hid = BNXT_ULP_CLASS_HID_178cb, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 2150894592UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT } - }, - [644] = { - .class_hid = BNXT_ULP_CLASS_HID_1748d, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 2150902784UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT } - }, - [645] = { - .class_hid = BNXT_ULP_CLASS_HID_109fb, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 2684619776UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT } - }, - [646] = { - .class_hid = BNXT_ULP_CLASS_HID_105bd, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 2684627968UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT } - }, - [647] = { - .class_hid = BNXT_ULP_CLASS_HID_155bf, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 2685668352UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT } - }, - [648] = { - .class_hid = BNXT_ULP_CLASS_HID_14179, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 2685676544UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT } - }, - [649] = { - .class_hid = BNXT_ULP_CLASS_HID_12bed, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 2686716928UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT } - }, - [650] = { - .class_hid = BNXT_ULP_CLASS_HID_127af, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 2686725120UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT } - }, - [651] = { - .class_hid = BNXT_ULP_CLASS_HID_177a9, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 2687765504UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT } - }, - [652] = { - .class_hid = BNXT_ULP_CLASS_HID_1636b, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 2687773696UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT } - }, - [653] = { - .class_hid = BNXT_ULP_CLASS_HID_1046d, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 3221490688UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT } - }, - [654] = { - .class_hid = BNXT_ULP_CLASS_HID_1104d, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 3221498880UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT } - }, - [655] = { - .class_hid = BNXT_ULP_CLASS_HID_14009, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 3222539264UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT } - }, - [656] = { - .class_hid = BNXT_ULP_CLASS_HID_15c69, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 3222547456UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT } - }, - [657] = { - .class_hid = BNXT_ULP_CLASS_HID_1260f, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 3223587840UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT } - }, - [658] = { - .class_hid = BNXT_ULP_CLASS_HID_1326f, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 3223596032UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT } - }, - [659] = { - .class_hid = BNXT_ULP_CLASS_HID_1622b, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 3224636416UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT } - }, - [660] = { - .class_hid = BNXT_ULP_CLASS_HID_17e0b, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 3224644608UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT } - }, - [661] = { - .class_hid = BNXT_ULP_CLASS_HID_11369, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 3758361600UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT } - }, - [662] = { - .class_hid = BNXT_ULP_CLASS_HID_10f2b, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 3758369792UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT } - }, - [663] = { - .class_hid = BNXT_ULP_CLASS_HID_15f6d, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 3759410176UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT } - }, - [664] = { - .class_hid = BNXT_ULP_CLASS_HID_14b2f, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 3759418368UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT } - }, - [665] = { - .class_hid = BNXT_ULP_CLASS_HID_13d6b, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 3760458752UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT } - }, - [666] = { - .class_hid = BNXT_ULP_CLASS_HID_1292d, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 3760466944UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT } - }, - [667] = { - .class_hid = BNXT_ULP_CLASS_HID_1792f, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 3761507328UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT } - }, - [668] = { - .class_hid = BNXT_ULP_CLASS_HID_174e9, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 3761515520UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT } - }, - [669] = { - .class_hid = BNXT_ULP_CLASS_HID_119e1, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 4295232512UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [670] = { - .class_hid = BNXT_ULP_CLASS_HID_115a3, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 4295240704UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [671] = { - .class_hid = BNXT_ULP_CLASS_HID_14563, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 4296281088UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [672] = { - .class_hid = BNXT_ULP_CLASS_HID_15143, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 4296289280UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [673] = { - .class_hid = BNXT_ULP_CLASS_HID_13b93, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 4297329664UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [674] = { - .class_hid = BNXT_ULP_CLASS_HID_13751, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 4297337856UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [675] = { - .class_hid = BNXT_ULP_CLASS_HID_16769, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 4298378240UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [676] = { - .class_hid = BNXT_ULP_CLASS_HID_17349, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 4298386432UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [677] = { - .class_hid = BNXT_ULP_CLASS_HID_114ab, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 4832103424UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [678] = { - .class_hid = BNXT_ULP_CLASS_HID_10061, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 4832111616UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [679] = { - .class_hid = BNXT_ULP_CLASS_HID_15063, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 4833152000UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [680] = { - .class_hid = BNXT_ULP_CLASS_HID_14c21, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 4833160192UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [681] = { - .class_hid = BNXT_ULP_CLASS_HID_13671, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 4834200576UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [682] = { - .class_hid = BNXT_ULP_CLASS_HID_12233, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 4834208768UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [683] = { - .class_hid = BNXT_ULP_CLASS_HID_17271, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 4835249152UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [684] = { - .class_hid = BNXT_ULP_CLASS_HID_16e33, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 4835257344UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [685] = { - .class_hid = BNXT_ULP_CLASS_HID_102c1, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 5368974336UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [686] = { - .class_hid = BNXT_ULP_CLASS_HID_11f21, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 5368982528UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [687] = { - .class_hid = BNXT_ULP_CLASS_HID_14ee1, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 5370022912UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [688] = { - .class_hid = BNXT_ULP_CLASS_HID_15ac1, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 5370031104UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [689] = { - .class_hid = BNXT_ULP_CLASS_HID_12cc3, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 5371071488UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [690] = { - .class_hid = BNXT_ULP_CLASS_HID_13923, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 5371079680UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [691] = { - .class_hid = BNXT_ULP_CLASS_HID_168e3, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 5372120064UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [692] = { - .class_hid = BNXT_ULP_CLASS_HID_164a9, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 5372128256UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [693] = { - .class_hid = BNXT_ULP_CLASS_HID_11e29, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 5905845248UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [694] = { - .class_hid = BNXT_ULP_CLASS_HID_115eb, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 5905853440UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [695] = { - .class_hid = BNXT_ULP_CLASS_HID_145a3, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 5906893824UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [696] = { - .class_hid = BNXT_ULP_CLASS_HID_151a3, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 5906902016UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [697] = { - .class_hid = BNXT_ULP_CLASS_HID_1382b, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 5907942400UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [698] = { - .class_hid = BNXT_ULP_CLASS_HID_137e1, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 5907950592UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [699] = { - .class_hid = BNXT_ULP_CLASS_HID_167a1, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 5908990976UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [700] = { - .class_hid = BNXT_ULP_CLASS_HID_173a1, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 5908999168UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [701] = { - .class_hid = BNXT_ULP_CLASS_HID_11449, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 6442716160UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [702] = { - .class_hid = BNXT_ULP_CLASS_HID_1000b, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 6442724352UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [703] = { - .class_hid = BNXT_ULP_CLASS_HID_15069, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 6443764736UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [704] = { - .class_hid = BNXT_ULP_CLASS_HID_14c2b, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 6443772928UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [705] = { - .class_hid = BNXT_ULP_CLASS_HID_1367b, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 6444813312UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [706] = { - .class_hid = BNXT_ULP_CLASS_HID_12239, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 6444821504UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [707] = { - .class_hid = BNXT_ULP_CLASS_HID_1721b, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 6445861888UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [708] = { - .class_hid = BNXT_ULP_CLASS_HID_169d9, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 6445870080UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [709] = { - .class_hid = BNXT_ULP_CLASS_HID_1033b, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 6979587072UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [710] = { - .class_hid = BNXT_ULP_CLASS_HID_11f3b, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 6979595264UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [711] = { - .class_hid = BNXT_ULP_CLASS_HID_14f2b, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 6980635648UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [712] = { - .class_hid = BNXT_ULP_CLASS_HID_15b2b, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 6980643840UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [713] = { - .class_hid = BNXT_ULP_CLASS_HID_12d39, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 6981684224UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [714] = { - .class_hid = BNXT_ULP_CLASS_HID_13939, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 6981692416UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [715] = { - .class_hid = BNXT_ULP_CLASS_HID_168f9, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 6982732800UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [716] = { - .class_hid = BNXT_ULP_CLASS_HID_164bb, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 6982740992UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [717] = { - .class_hid = BNXT_ULP_CLASS_HID_119cb, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 7516457984UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [718] = { - .class_hid = BNXT_ULP_CLASS_HID_11589, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 7516466176UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [719] = { - .class_hid = BNXT_ULP_CLASS_HID_14549, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 7517506560UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [720] = { - .class_hid = BNXT_ULP_CLASS_HID_151a9, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 7517514752UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [721] = { - .class_hid = BNXT_ULP_CLASS_HID_13bc9, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 7518555136UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [722] = { - .class_hid = BNXT_ULP_CLASS_HID_1378b, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 7518563328UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [723] = { - .class_hid = BNXT_ULP_CLASS_HID_1674b, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 7519603712UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [724] = { - .class_hid = BNXT_ULP_CLASS_HID_173ab, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 7519611904UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [725] = { - .class_hid = BNXT_ULP_CLASS_HID_114a9, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 8053328896UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [726] = { - .class_hid = BNXT_ULP_CLASS_HID_1006b, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 8053337088UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [727] = { - .class_hid = BNXT_ULP_CLASS_HID_150a9, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 8054377472UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [728] = { - .class_hid = BNXT_ULP_CLASS_HID_14c6b, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 8054385664UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [729] = { - .class_hid = BNXT_ULP_CLASS_HID_136ab, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 8055426048UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [730] = { - .class_hid = BNXT_ULP_CLASS_HID_12269, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 8055434240UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [731] = { - .class_hid = BNXT_ULP_CLASS_HID_172ab, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 8056474624UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [732] = { - .class_hid = BNXT_ULP_CLASS_HID_16e69, - .class_tid = 2, - .hdr_sig_id = 20, - .flow_sig_id = 8056482816UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT } - }, - [733] = { - .class_hid = BNXT_ULP_CLASS_HID_402d2, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 66304UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI } - }, - [734] = { - .class_hid = BNXT_ULP_CLASS_HID_412ee, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 68352UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI } - }, - [735] = { - .class_hid = BNXT_ULP_CLASS_HID_512a2, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 328448UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC } - }, - [736] = { - .class_hid = BNXT_ULP_CLASS_HID_50dd8, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 330496UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC } - }, - [737] = { - .class_hid = BNXT_ULP_CLASS_HID_48aea, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 590592UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC } - }, - [738] = { - .class_hid = BNXT_ULP_CLASS_HID_48500, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 592640UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC } - }, - [739] = { - .class_hid = BNXT_ULP_CLASS_HID_585d4, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 852736UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC } - }, - [740] = { - .class_hid = BNXT_ULP_CLASS_HID_59590, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 854784UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC } - }, - [741] = { - .class_hid = BNXT_ULP_CLASS_HID_41936, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 536937216UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR } - }, - [742] = { - .class_hid = BNXT_ULP_CLASS_HID_409ac, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 536939264UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR } - }, - [743] = { - .class_hid = BNXT_ULP_CLASS_HID_50860, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 537199360UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR } - }, - [744] = { - .class_hid = BNXT_ULP_CLASS_HID_5183c, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 537201408UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR } - }, - [745] = { - .class_hid = BNXT_ULP_CLASS_HID_481a8, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 537461504UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR } - }, - [746] = { - .class_hid = BNXT_ULP_CLASS_HID_49064, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 537463552UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR } - }, - [747] = { - .class_hid = BNXT_ULP_CLASS_HID_59038, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 537723648UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR } - }, - [748] = { - .class_hid = BNXT_ULP_CLASS_HID_58376, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 537725696UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR } - }, - [749] = { - .class_hid = BNXT_ULP_CLASS_HID_414a0, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 1073808128UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR } - }, - [750] = { - .class_hid = BNXT_ULP_CLASS_HID_407ce, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 1073810176UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR } - }, - [751] = { - .class_hid = BNXT_ULP_CLASS_HID_50782, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 1074070272UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR } - }, - [752] = { - .class_hid = BNXT_ULP_CLASS_HID_517ae, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 1074072320UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR } - }, - [753] = { - .class_hid = BNXT_ULP_CLASS_HID_49f68, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 1074332416UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR } - }, - [754] = { - .class_hid = BNXT_ULP_CLASS_HID_48f86, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 1074334464UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR } - }, - [755] = { - .class_hid = BNXT_ULP_CLASS_HID_58faa, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 1074594560UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR } - }, - [756] = { - .class_hid = BNXT_ULP_CLASS_HID_59e66, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 1074596608UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR } - }, - [757] = { - .class_hid = BNXT_ULP_CLASS_HID_40266, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 1610679040UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR } - }, - [758] = { - .class_hid = BNXT_ULP_CLASS_HID_41222, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 1610681088UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR } - }, - [759] = { - .class_hid = BNXT_ULP_CLASS_HID_512e6, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 1610941184UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR } - }, - [760] = { - .class_hid = BNXT_ULP_CLASS_HID_50d6c, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 1610943232UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR } - }, - [761] = { - .class_hid = BNXT_ULP_CLASS_HID_48a2e, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 1611203328UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR } - }, - [762] = { - .class_hid = BNXT_ULP_CLASS_HID_48564, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 1611205376UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR } - }, - [763] = { - .class_hid = BNXT_ULP_CLASS_HID_58568, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 1611465472UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR } - }, - [764] = { - .class_hid = BNXT_ULP_CLASS_HID_59524, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 1611467520UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR } - }, - [765] = { - .class_hid = BNXT_ULP_CLASS_HID_419d8, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 2147549952UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT } - }, - [766] = { - .class_hid = BNXT_ULP_CLASS_HID_4087e, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 2147552000UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT } - }, - [767] = { - .class_hid = BNXT_ULP_CLASS_HID_5080a, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 2147812096UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT } - }, - [768] = { - .class_hid = BNXT_ULP_CLASS_HID_518ce, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 2147814144UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT } - }, - [769] = { - .class_hid = BNXT_ULP_CLASS_HID_4807a, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 2148074240UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT } - }, - [770] = { - .class_hid = BNXT_ULP_CLASS_HID_4900e, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 2148076288UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT } - }, - [771] = { - .class_hid = BNXT_ULP_CLASS_HID_590ca, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 2148336384UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT } - }, - [772] = { - .class_hid = BNXT_ULP_CLASS_HID_58378, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 2148338432UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT } - }, - [773] = { - .class_hid = BNXT_ULP_CLASS_HID_414be, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 2684420864UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT } - }, - [774] = { - .class_hid = BNXT_ULP_CLASS_HID_4073c, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 2684422912UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT } - }, - [775] = { - .class_hid = BNXT_ULP_CLASS_HID_507e8, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 2684683008UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT } - }, - [776] = { - .class_hid = BNXT_ULP_CLASS_HID_517ac, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 2684685056UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT } - }, - [777] = { - .class_hid = BNXT_ULP_CLASS_HID_49f7e, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 2684945152UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT } - }, - [778] = { - .class_hid = BNXT_ULP_CLASS_HID_48fec, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 2684947200UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT } - }, - [779] = { - .class_hid = BNXT_ULP_CLASS_HID_58fa8, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 2685207296UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT } - }, - [780] = { - .class_hid = BNXT_ULP_CLASS_HID_59e7c, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 2685209344UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT } - }, - [781] = { - .class_hid = BNXT_ULP_CLASS_HID_40208, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 3221291776UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT } - }, - [782] = { - .class_hid = BNXT_ULP_CLASS_HID_412cc, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 3221293824UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT } - }, - [783] = { - .class_hid = BNXT_ULP_CLASS_HID_51288, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 3221553920UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT } - }, - [784] = { - .class_hid = BNXT_ULP_CLASS_HID_50d2e, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 3221555968UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT } - }, - [785] = { - .class_hid = BNXT_ULP_CLASS_HID_48ac8, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 3221816064UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT } - }, - [786] = { - .class_hid = BNXT_ULP_CLASS_HID_4856e, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 3221818112UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT } - }, - [787] = { - .class_hid = BNXT_ULP_CLASS_HID_5852a, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 3222078208UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT } - }, - [788] = { - .class_hid = BNXT_ULP_CLASS_HID_595ce, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 3222080256UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT } - }, - [789] = { - .class_hid = BNXT_ULP_CLASS_HID_4196c, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 3758162688UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT } - }, - [790] = { - .class_hid = BNXT_ULP_CLASS_HID_409aa, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 3758164736UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT } - }, - [791] = { - .class_hid = BNXT_ULP_CLASS_HID_5086e, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 3758424832UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT } - }, - [792] = { - .class_hid = BNXT_ULP_CLASS_HID_5182a, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 3758426880UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT } - }, - [793] = { - .class_hid = BNXT_ULP_CLASS_HID_481ae, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 3758686976UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT } - }, - [794] = { - .class_hid = BNXT_ULP_CLASS_HID_4906a, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 3758689024UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT } - }, - [795] = { - .class_hid = BNXT_ULP_CLASS_HID_5902e, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 3758949120UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT } - }, - [796] = { - .class_hid = BNXT_ULP_CLASS_HID_580ac, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 3758951168UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT } - }, - [797] = { - .class_hid = BNXT_ULP_CLASS_HID_40766, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 4295033600UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [798] = { - .class_hid = BNXT_ULP_CLASS_HID_41726, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 4295035648UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [799] = { - .class_hid = BNXT_ULP_CLASS_HID_517f6, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 4295295744UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [800] = { - .class_hid = BNXT_ULP_CLASS_HID_5066c, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 4295297792UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [801] = { - .class_hid = BNXT_ULP_CLASS_HID_48f3e, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 4295557888UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [802] = { - .class_hid = BNXT_ULP_CLASS_HID_49ffe, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 4295559936UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [803] = { - .class_hid = BNXT_ULP_CLASS_HID_59f8e, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 4295820032UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [804] = { - .class_hid = BNXT_ULP_CLASS_HID_58e24, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 4295822080UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [805] = { - .class_hid = BNXT_ULP_CLASS_HID_4126e, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 4831904512UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [806] = { - .class_hid = BNXT_ULP_CLASS_HID_402e4, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 4831906560UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [807] = { - .class_hid = BNXT_ULP_CLASS_HID_502b4, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 4832166656UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [808] = { - .class_hid = BNXT_ULP_CLASS_HID_51d74, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 4832168704UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [809] = { - .class_hid = BNXT_ULP_CLASS_HID_49a26, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 4832428800UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [810] = { - .class_hid = BNXT_ULP_CLASS_HID_48abc, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 4832430848UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [811] = { - .class_hid = BNXT_ULP_CLASS_HID_5956c, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 4832690944UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [812] = { - .class_hid = BNXT_ULP_CLASS_HID_585ee, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 4832692992UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [813] = { - .class_hid = BNXT_ULP_CLASS_HID_409e4, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 5368775424UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [814] = { - .class_hid = BNXT_ULP_CLASS_HID_419a4, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 5368777472UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [815] = { - .class_hid = BNXT_ULP_CLASS_HID_51844, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 5369037568UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [816] = { - .class_hid = BNXT_ULP_CLASS_HID_508e6, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 5369039616UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [817] = { - .class_hid = BNXT_ULP_CLASS_HID_4918c, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 5369299712UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [818] = { - .class_hid = BNXT_ULP_CLASS_HID_4802e, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 5369301760UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [819] = { - .class_hid = BNXT_ULP_CLASS_HID_580ee, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 5369561856UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [820] = { - .class_hid = BNXT_ULP_CLASS_HID_590ae, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 5369563904UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [821] = { - .class_hid = BNXT_ULP_CLASS_HID_404ae, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 5905646336UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [822] = { - .class_hid = BNXT_ULP_CLASS_HID_41766, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 5905648384UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [823] = { - .class_hid = BNXT_ULP_CLASS_HID_5172e, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 5905908480UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [824] = { - .class_hid = BNXT_ULP_CLASS_HID_507a4, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 5905910528UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [825] = { - .class_hid = BNXT_ULP_CLASS_HID_48f66, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 5906170624UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [826] = { - .class_hid = BNXT_ULP_CLASS_HID_49f2e, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 5906172672UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [827] = { - .class_hid = BNXT_ULP_CLASS_HID_59fe6, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 5906432768UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [828] = { - .class_hid = BNXT_ULP_CLASS_HID_58e6c, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 5906434816UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [829] = { - .class_hid = BNXT_ULP_CLASS_HID_4126c, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 6442517248UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [830] = { - .class_hid = BNXT_ULP_CLASS_HID_4028e, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 6442519296UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [831] = { - .class_hid = BNXT_ULP_CLASS_HID_50d5e, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 6442779392UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [832] = { - .class_hid = BNXT_ULP_CLASS_HID_51d1e, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 6442781440UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [833] = { - .class_hid = BNXT_ULP_CLASS_HID_49a2c, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 6443041536UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [834] = { - .class_hid = BNXT_ULP_CLASS_HID_4954e, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 6443043584UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [835] = { - .class_hid = BNXT_ULP_CLASS_HID_5951e, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 6443303680UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [836] = { - .class_hid = BNXT_ULP_CLASS_HID_5858c, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 6443305728UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [837] = { - .class_hid = BNXT_ULP_CLASS_HID_409fe, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 6979388160UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [838] = { - .class_hid = BNXT_ULP_CLASS_HID_419ee, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 6979390208UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [839] = { - .class_hid = BNXT_ULP_CLASS_HID_519ae, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 6979650304UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [840] = { - .class_hid = BNXT_ULP_CLASS_HID_508fc, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 6979652352UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [841] = { - .class_hid = BNXT_ULP_CLASS_HID_491ee, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 6979912448UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [842] = { - .class_hid = BNXT_ULP_CLASS_HID_4802c, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 6979914496UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [843] = { - .class_hid = BNXT_ULP_CLASS_HID_580fc, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 6980174592UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [844] = { - .class_hid = BNXT_ULP_CLASS_HID_590bc, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 6980176640UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [845] = { - .class_hid = BNXT_ULP_CLASS_HID_4074c, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 7516259072UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [846] = { - .class_hid = BNXT_ULP_CLASS_HID_4170c, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 7516261120UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [847] = { - .class_hid = BNXT_ULP_CLASS_HID_5172c, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 7516521216UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [848] = { - .class_hid = BNXT_ULP_CLASS_HID_5064e, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 7516523264UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [849] = { - .class_hid = BNXT_ULP_CLASS_HID_48f0c, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 7516783360UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [850] = { - .class_hid = BNXT_ULP_CLASS_HID_49fcc, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 7516785408UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [851] = { - .class_hid = BNXT_ULP_CLASS_HID_59fec, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 7517045504UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [852] = { - .class_hid = BNXT_ULP_CLASS_HID_58e0e, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 7517047552UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [853] = { - .class_hid = BNXT_ULP_CLASS_HID_413ac, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 8053129984UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [854] = { - .class_hid = BNXT_ULP_CLASS_HID_402ee, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 8053132032UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [855] = { - .class_hid = BNXT_ULP_CLASS_HID_502ae, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 8053392128UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [856] = { - .class_hid = BNXT_ULP_CLASS_HID_512ae, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 8053394176UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [857] = { - .class_hid = BNXT_ULP_CLASS_HID_49a6c, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 8053654272UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [858] = { - .class_hid = BNXT_ULP_CLASS_HID_48aae, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 8053656320UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [859] = { - .class_hid = BNXT_ULP_CLASS_HID_58aae, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 8053916416UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [860] = { - .class_hid = BNXT_ULP_CLASS_HID_585ec, - .class_tid = 2, - .hdr_sig_id = 21, - .flow_sig_id = 8053918464UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT } - }, - [861] = { - .class_hid = BNXT_ULP_CLASS_HID_104ae, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 265216UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI } - }, - [862] = { - .class_hid = BNXT_ULP_CLASS_HID_1108e, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 273408UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI } - }, - [863] = { - .class_hid = BNXT_ULP_CLASS_HID_140b2, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 1313792UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC } - }, - [864] = { - .class_hid = BNXT_ULP_CLASS_HID_15c92, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 1321984UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC } - }, - [865] = { - .class_hid = BNXT_ULP_CLASS_HID_126a0, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 2362368UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC } - }, - [866] = { - .class_hid = BNXT_ULP_CLASS_HID_13280, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 2370560UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC } - }, - [867] = { - .class_hid = BNXT_ULP_CLASS_HID_16d44, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 3410944UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC } - }, - [868] = { - .class_hid = BNXT_ULP_CLASS_HID_17ea4, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 3419136UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC } - }, - [869] = { - .class_hid = BNXT_ULP_CLASS_HID_113a4, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 2147748864UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR } - }, - [870] = { - .class_hid = BNXT_ULP_CLASS_HID_10e66, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 2147757056UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR } - }, - [871] = { - .class_hid = BNXT_ULP_CLASS_HID_15e40, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 2148797440UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR } - }, - [872] = { - .class_hid = BNXT_ULP_CLASS_HID_14a02, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 2148805632UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR } - }, - [873] = { - .class_hid = BNXT_ULP_CLASS_HID_13db6, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 2149846016UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR } - }, - [874] = { - .class_hid = BNXT_ULP_CLASS_HID_12870, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 2149854208UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR } - }, - [875] = { - .class_hid = BNXT_ULP_CLASS_HID_17852, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 2150894592UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR } - }, - [876] = { - .class_hid = BNXT_ULP_CLASS_HID_17414, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 2150902784UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR } - }, - [877] = { - .class_hid = BNXT_ULP_CLASS_HID_11978, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 4295232512UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR } - }, - [878] = { - .class_hid = BNXT_ULP_CLASS_HID_1153a, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 4295240704UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR } - }, - [879] = { - .class_hid = BNXT_ULP_CLASS_HID_145fa, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 4296281088UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR } - }, - [880] = { - .class_hid = BNXT_ULP_CLASS_HID_151da, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 4296289280UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR } - }, - [881] = { - .class_hid = BNXT_ULP_CLASS_HID_13b0a, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 4297329664UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR } - }, - [882] = { - .class_hid = BNXT_ULP_CLASS_HID_137c8, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 4297337856UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR } - }, - [883] = { - .class_hid = BNXT_ULP_CLASS_HID_167f0, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 4298378240UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR } - }, - [884] = { - .class_hid = BNXT_ULP_CLASS_HID_173d0, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 4298386432UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR } - }, - [885] = { - .class_hid = BNXT_ULP_CLASS_HID_114d0, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 6442716160UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR } - }, - [886] = { - .class_hid = BNXT_ULP_CLASS_HID_10092, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 6442724352UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR } - }, - [887] = { - .class_hid = BNXT_ULP_CLASS_HID_150f0, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 6443764736UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR } - }, - [888] = { - .class_hid = BNXT_ULP_CLASS_HID_14cb2, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 6443772928UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR } - }, - [889] = { - .class_hid = BNXT_ULP_CLASS_HID_136e2, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 6444813312UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR } - }, - [890] = { - .class_hid = BNXT_ULP_CLASS_HID_122a0, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 6444821504UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR } - }, - [891] = { - .class_hid = BNXT_ULP_CLASS_HID_17282, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 6445861888UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR } - }, - [892] = { - .class_hid = BNXT_ULP_CLASS_HID_16940, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 6445870080UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR } - }, - [893] = { - .class_hid = BNXT_ULP_CLASS_HID_11b90, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 8590199808UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT } - }, - [894] = { - .class_hid = BNXT_ULP_CLASS_HID_11654, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 8590208000UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT } - }, - [895] = { - .class_hid = BNXT_ULP_CLASS_HID_14618, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 8591248384UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT } - }, - [896] = { - .class_hid = BNXT_ULP_CLASS_HID_15278, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 8591256576UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT } - }, - [897] = { - .class_hid = BNXT_ULP_CLASS_HID_12404, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 8592296960UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT } - }, - [898] = { - .class_hid = BNXT_ULP_CLASS_HID_13064, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 8592305152UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT } - }, - [899] = { - .class_hid = BNXT_ULP_CLASS_HID_16028, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 8593345536UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT } - }, - [900] = { - .class_hid = BNXT_ULP_CLASS_HID_17c08, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 8593353728UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT } - }, - [901] = { - .class_hid = BNXT_ULP_CLASS_HID_11100, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 10737683456UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT } - }, - [902] = { - .class_hid = BNXT_ULP_CLASS_HID_10dc4, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 10737691648UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT } - }, - [903] = { - .class_hid = BNXT_ULP_CLASS_HID_15d24, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 10738732032UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT } - }, - [904] = { - .class_hid = BNXT_ULP_CLASS_HID_149d0, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 10738740224UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT } - }, - [905] = { - .class_hid = BNXT_ULP_CLASS_HID_13314, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 10739780608UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT } - }, - [906] = { - .class_hid = BNXT_ULP_CLASS_HID_12fd4, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 10739788800UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT } - }, - [907] = { - .class_hid = BNXT_ULP_CLASS_HID_17f20, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 10740829184UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT } - }, - [908] = { - .class_hid = BNXT_ULP_CLASS_HID_16be0, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 10740837376UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT } - }, - [909] = { - .class_hid = BNXT_ULP_CLASS_HID_11cd8, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 12885167104UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT } - }, - [910] = { - .class_hid = BNXT_ULP_CLASS_HID_10880, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 12885175296UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT } - }, - [911] = { - .class_hid = BNXT_ULP_CLASS_HID_158e0, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 12886215680UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT } - }, - [912] = { - .class_hid = BNXT_ULP_CLASS_HID_154a0, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 12886223872UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT } - }, - [913] = { - .class_hid = BNXT_ULP_CLASS_HID_13ed0, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 12887264256UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT } - }, - [914] = { - .class_hid = BNXT_ULP_CLASS_HID_12a90, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 12887272448UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT } - }, - [915] = { - .class_hid = BNXT_ULP_CLASS_HID_16550, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 12888312832UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT } - }, - [916] = { - .class_hid = BNXT_ULP_CLASS_HID_176b0, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 12888321024UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT } - }, - [917] = { - .class_hid = BNXT_ULP_CLASS_HID_10bb0, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 15032650752UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT } - }, - [918] = { - .class_hid = BNXT_ULP_CLASS_HID_10670, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 15032658944UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT } - }, - [919] = { - .class_hid = BNXT_ULP_CLASS_HID_15650, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 15033699328UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT } - }, - [920] = { - .class_hid = BNXT_ULP_CLASS_HID_14210, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 15033707520UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT } - }, - [921] = { - .class_hid = BNXT_ULP_CLASS_HID_13440, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 15034747904UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT } - }, - [922] = { - .class_hid = BNXT_ULP_CLASS_HID_12000, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 15034756096UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT } - }, - [923] = { - .class_hid = BNXT_ULP_CLASS_HID_17060, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 15035796480UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT } - }, - [924] = { - .class_hid = BNXT_ULP_CLASS_HID_16c20, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 15035804672UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT } - }, - [925] = { - .class_hid = BNXT_ULP_CLASS_HID_11511, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 17180134400UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [926] = { - .class_hid = BNXT_ULP_CLASS_HID_101d3, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 17180142592UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [927] = { - .class_hid = BNXT_ULP_CLASS_HID_15135, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 17181182976UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [928] = { - .class_hid = BNXT_ULP_CLASS_HID_14df7, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 17181191168UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [929] = { - .class_hid = BNXT_ULP_CLASS_HID_13723, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 17182231552UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [930] = { - .class_hid = BNXT_ULP_CLASS_HID_123e5, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 17182239744UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [931] = { - .class_hid = BNXT_ULP_CLASS_HID_173c7, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 17183280128UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [932] = { - .class_hid = BNXT_ULP_CLASS_HID_16f89, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 17183288320UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [933] = { - .class_hid = BNXT_ULP_CLASS_HID_10081, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 19327618048UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [934] = { - .class_hid = BNXT_ULP_CLASS_HID_11ce1, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 19327626240UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [935] = { - .class_hid = BNXT_ULP_CLASS_HID_14ca5, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 19328666624UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [936] = { - .class_hid = BNXT_ULP_CLASS_HID_15885, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 19328674816UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [937] = { - .class_hid = BNXT_ULP_CLASS_HID_12293, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 19329715200UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [938] = { - .class_hid = BNXT_ULP_CLASS_HID_13ef3, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 19329723392UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [939] = { - .class_hid = BNXT_ULP_CLASS_HID_16eb7, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 19330763776UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [940] = { - .class_hid = BNXT_ULP_CLASS_HID_16561, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 19330771968UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [941] = { - .class_hid = BNXT_ULP_CLASS_HID_10e59, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 21475101696UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [942] = { - .class_hid = BNXT_ULP_CLASS_HID_11bb9, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 21475109888UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [943] = { - .class_hid = BNXT_ULP_CLASS_HID_14a61, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 21476150272UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [944] = { - .class_hid = BNXT_ULP_CLASS_HID_14623, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 21476158464UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [945] = { - .class_hid = BNXT_ULP_CLASS_HID_1286b, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 21477198848UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [946] = { - .class_hid = BNXT_ULP_CLASS_HID_12411, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 21477207040UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [947] = { - .class_hid = BNXT_ULP_CLASS_HID_17473, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 21478247424UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [948] = { - .class_hid = BNXT_ULP_CLASS_HID_16031, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 21478255616UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [949] = { - .class_hid = BNXT_ULP_CLASS_HID_10531, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 23622585344UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [950] = { - .class_hid = BNXT_ULP_CLASS_HID_11111, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 23622593536UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [951] = { - .class_hid = BNXT_ULP_CLASS_HID_141d1, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 23623633920UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [952] = { - .class_hid = BNXT_ULP_CLASS_HID_15d31, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 23623642112UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [953] = { - .class_hid = BNXT_ULP_CLASS_HID_127c3, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 23624682496UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [954] = { - .class_hid = BNXT_ULP_CLASS_HID_13323, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 23624690688UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [955] = { - .class_hid = BNXT_ULP_CLASS_HID_163e3, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 23625731072UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [956] = { - .class_hid = BNXT_ULP_CLASS_HID_17fc3, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 23625739264UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [957] = { - .class_hid = BNXT_ULP_CLASS_HID_108f5, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 25770068992UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [958] = { - .class_hid = BNXT_ULP_CLASS_HID_104b9, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 25770077184UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [959] = { - .class_hid = BNXT_ULP_CLASS_HID_15499, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 25771117568UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [960] = { - .class_hid = BNXT_ULP_CLASS_HID_1435d, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 25771125760UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [961] = { - .class_hid = BNXT_ULP_CLASS_HID_12a89, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 25772166144UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [962] = { - .class_hid = BNXT_ULP_CLASS_HID_12149, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 25772174336UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [963] = { - .class_hid = BNXT_ULP_CLASS_HID_176ad, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 25773214720UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [964] = { - .class_hid = BNXT_ULP_CLASS_HID_16d6d, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 25773222912UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [965] = { - .class_hid = BNXT_ULP_CLASS_HID_10665, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 27917552640UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [966] = { - .class_hid = BNXT_ULP_CLASS_HID_11245, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 27917560832UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [967] = { - .class_hid = BNXT_ULP_CLASS_HID_14271, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 27918601216UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [968] = { - .class_hid = BNXT_ULP_CLASS_HID_15e51, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 27918609408UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [969] = { - .class_hid = BNXT_ULP_CLASS_HID_12061, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 27919649792UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [970] = { - .class_hid = BNXT_ULP_CLASS_HID_13c41, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 27919657984UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [971] = { - .class_hid = BNXT_ULP_CLASS_HID_16c05, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 27920698368UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [972] = { - .class_hid = BNXT_ULP_CLASS_HID_17865, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 27920706560UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [973] = { - .class_hid = BNXT_ULP_CLASS_HID_10d21, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 30065036288UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [974] = { - .class_hid = BNXT_ULP_CLASS_HID_11901, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 30065044480UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [975] = { - .class_hid = BNXT_ULP_CLASS_HID_149c1, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 30066084864UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [976] = { - .class_hid = BNXT_ULP_CLASS_HID_14589, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 30066093056UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [977] = { - .class_hid = BNXT_ULP_CLASS_HID_12f31, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 30067133440UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [978] = { - .class_hid = BNXT_ULP_CLASS_HID_13b11, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 30067141632UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [979] = { - .class_hid = BNXT_ULP_CLASS_HID_16bd9, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 30068182016UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [980] = { - .class_hid = BNXT_ULP_CLASS_HID_16799, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 30068190208UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [981] = { - .class_hid = BNXT_ULP_CLASS_HID_11831, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 32212519936UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [982] = { - .class_hid = BNXT_ULP_CLASS_HID_114f1, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 32212528128UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [983] = { - .class_hid = BNXT_ULP_CLASS_HID_144b1, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 32213568512UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [984] = { - .class_hid = BNXT_ULP_CLASS_HID_15091, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 32213576704UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [985] = { - .class_hid = BNXT_ULP_CLASS_HID_13ac1, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 32214617088UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [986] = { - .class_hid = BNXT_ULP_CLASS_HID_13681, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 32214625280UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [987] = { - .class_hid = BNXT_ULP_CLASS_HID_166b1, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 32215665664UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [988] = { - .class_hid = BNXT_ULP_CLASS_HID_17291, - .class_tid = 2, - .hdr_sig_id = 22, - .flow_sig_id = 32215673856UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT } - }, - [989] = { - .class_hid = BNXT_ULP_CLASS_HID_4007d, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 66304UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI } - }, - [990] = { - .class_hid = BNXT_ULP_CLASS_HID_41041, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 68352UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI } - }, - [991] = { - .class_hid = BNXT_ULP_CLASS_HID_5100d, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 328448UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC } - }, - [992] = { - .class_hid = BNXT_ULP_CLASS_HID_50f77, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 330496UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC } - }, - [993] = { - .class_hid = BNXT_ULP_CLASS_HID_48845, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 590592UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC } - }, - [994] = { - .class_hid = BNXT_ULP_CLASS_HID_487af, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 592640UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC } - }, - [995] = { - .class_hid = BNXT_ULP_CLASS_HID_5877b, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 852736UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC } - }, - [996] = { - .class_hid = BNXT_ULP_CLASS_HID_5973f, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 854784UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC } - }, - [997] = { - .class_hid = BNXT_ULP_CLASS_HID_41c31, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 134284032UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR } - }, - [998] = { - .class_hid = BNXT_ULP_CLASS_HID_40b1b, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 134286080UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR } - }, - [999] = { - .class_hid = BNXT_ULP_CLASS_HID_50b67, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 134546176UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR } - }, - [1000] = { - .class_hid = BNXT_ULP_CLASS_HID_51b2b, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 134548224UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR } - }, - [1001] = { - .class_hid = BNXT_ULP_CLASS_HID_4831f, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 134808320UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR } - }, - [1002] = { - .class_hid = BNXT_ULP_CLASS_HID_49363, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 134810368UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR } - }, - [1003] = { - .class_hid = BNXT_ULP_CLASS_HID_5932f, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 135070464UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR } - }, - [1004] = { - .class_hid = BNXT_ULP_CLASS_HID_58211, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 135072512UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR } - }, - [1005] = { - .class_hid = BNXT_ULP_CLASS_HID_4161b, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 268501760UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR } - }, - [1006] = { - .class_hid = BNXT_ULP_CLASS_HID_405bd, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 268503808UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR } - }, - [1007] = { - .class_hid = BNXT_ULP_CLASS_HID_50589, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 268763904UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR } - }, - [1008] = { - .class_hid = BNXT_ULP_CLASS_HID_5150d, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 268765952UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR } - }, - [1009] = { - .class_hid = BNXT_ULP_CLASS_HID_49e23, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 269026048UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR } - }, - [1010] = { - .class_hid = BNXT_ULP_CLASS_HID_48d85, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 269028096UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR } - }, - [1011] = { - .class_hid = BNXT_ULP_CLASS_HID_58d11, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 269288192UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR } - }, - [1012] = { - .class_hid = BNXT_ULP_CLASS_HID_59d15, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 269290240UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR } - }, - [1013] = { - .class_hid = BNXT_ULP_CLASS_HID_4012d, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 402719488UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR } - }, - [1014] = { - .class_hid = BNXT_ULP_CLASS_HID_41131, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 402721536UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR } - }, - [1015] = { - .class_hid = BNXT_ULP_CLASS_HID_5113d, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 402981632UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR } - }, - [1016] = { - .class_hid = BNXT_ULP_CLASS_HID_50027, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 402983680UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR } - }, - [1017] = { - .class_hid = BNXT_ULP_CLASS_HID_48935, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 403243776UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR } - }, - [1018] = { - .class_hid = BNXT_ULP_CLASS_HID_49939, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 403245824UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR } - }, - [1019] = { - .class_hid = BNXT_ULP_CLASS_HID_59905, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 403505920UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR } - }, - [1020] = { - .class_hid = BNXT_ULP_CLASS_HID_5882f, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 403507968UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR } - }, - [1021] = { - .class_hid = BNXT_ULP_CLASS_HID_41b99, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 536937216UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT } - }, - [1022] = { - .class_hid = BNXT_ULP_CLASS_HID_40b03, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 536939264UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT } - }, - [1023] = { - .class_hid = BNXT_ULP_CLASS_HID_50acf, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 537199360UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT } - }, - [1024] = { - .class_hid = BNXT_ULP_CLASS_HID_51a93, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 537201408UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT } - }, - [1025] = { - .class_hid = BNXT_ULP_CLASS_HID_48307, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 537461504UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT } - }, - [1026] = { - .class_hid = BNXT_ULP_CLASS_HID_492cb, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 537463552UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT } - }, - [1027] = { - .class_hid = BNXT_ULP_CLASS_HID_59297, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 537723648UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT } - }, - [1028] = { - .class_hid = BNXT_ULP_CLASS_HID_581d9, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 537725696UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT } - }, - [1029] = { - .class_hid = BNXT_ULP_CLASS_HID_41653, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 671154944UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT } - }, - [1030] = { - .class_hid = BNXT_ULP_CLASS_HID_40655, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 671156992UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT } - }, - [1031] = { - .class_hid = BNXT_ULP_CLASS_HID_50601, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 671417088UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT } - }, - [1032] = { - .class_hid = BNXT_ULP_CLASS_HID_51545, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 671419136UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT } - }, - [1033] = { - .class_hid = BNXT_ULP_CLASS_HID_49e1b, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 671679232UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT } - }, - [1034] = { - .class_hid = BNXT_ULP_CLASS_HID_48e1d, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 671681280UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT } - }, - [1035] = { - .class_hid = BNXT_ULP_CLASS_HID_58d49, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 671941376UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT } - }, - [1036] = { - .class_hid = BNXT_ULP_CLASS_HID_59d0d, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 671943424UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT } - }, - [1037] = { - .class_hid = BNXT_ULP_CLASS_HID_40115, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 805372672UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT } - }, - [1038] = { - .class_hid = BNXT_ULP_CLASS_HID_41099, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 805374720UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT } - }, - [1039] = { - .class_hid = BNXT_ULP_CLASS_HID_51085, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 805634816UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT } - }, - [1040] = { - .class_hid = BNXT_ULP_CLASS_HID_5000f, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 805636864UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT } - }, - [1041] = { - .class_hid = BNXT_ULP_CLASS_HID_4889d, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 805896960UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT } - }, - [1042] = { - .class_hid = BNXT_ULP_CLASS_HID_49881, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 805899008UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT } - }, - [1043] = { - .class_hid = BNXT_ULP_CLASS_HID_5980d, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 806159104UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT } - }, - [1044] = { - .class_hid = BNXT_ULP_CLASS_HID_59797, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 806161152UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT } - }, - [1045] = { - .class_hid = BNXT_ULP_CLASS_HID_41c09, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 939590400UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT } - }, - [1046] = { - .class_hid = BNXT_ULP_CLASS_HID_40c13, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 939592448UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT } - }, - [1047] = { - .class_hid = BNXT_ULP_CLASS_HID_50b1f, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 939852544UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT } - }, - [1048] = { - .class_hid = BNXT_ULP_CLASS_HID_51b03, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 939854592UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT } - }, - [1049] = { - .class_hid = BNXT_ULP_CLASS_HID_48417, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 940114688UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT } - }, - [1050] = { - .class_hid = BNXT_ULP_CLASS_HID_4931b, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 940116736UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT } - }, - [1051] = { - .class_hid = BNXT_ULP_CLASS_HID_59307, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 940376832UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT } - }, - [1052] = { - .class_hid = BNXT_ULP_CLASS_HID_58309, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 940378880UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT } - }, - [1053] = { - .class_hid = BNXT_ULP_CLASS_HID_4160f, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 1073808128UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1054] = { - .class_hid = BNXT_ULP_CLASS_HID_40561, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 1073810176UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1055] = { - .class_hid = BNXT_ULP_CLASS_HID_5052d, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 1074070272UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1056] = { - .class_hid = BNXT_ULP_CLASS_HID_51501, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 1074072320UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1057] = { - .class_hid = BNXT_ULP_CLASS_HID_49dc7, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 1074332416UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1058] = { - .class_hid = BNXT_ULP_CLASS_HID_48d29, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 1074334464UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1059] = { - .class_hid = BNXT_ULP_CLASS_HID_58d05, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 1074594560UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1060] = { - .class_hid = BNXT_ULP_CLASS_HID_59cc9, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 1074596608UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1061] = { - .class_hid = BNXT_ULP_CLASS_HID_40161, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 1208025856UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1062] = { - .class_hid = BNXT_ULP_CLASS_HID_41125, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 1208027904UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1063] = { - .class_hid = BNXT_ULP_CLASS_HID_51061, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 1208288000UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1064] = { - .class_hid = BNXT_ULP_CLASS_HID_5004b, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 1208290048UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1065] = { - .class_hid = BNXT_ULP_CLASS_HID_48929, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 1208550144UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1066] = { - .class_hid = BNXT_ULP_CLASS_HID_4986d, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 1208552192UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1067] = { - .class_hid = BNXT_ULP_CLASS_HID_59829, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 1208812288UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1068] = { - .class_hid = BNXT_ULP_CLASS_HID_58823, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 1208814336UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1069] = { - .class_hid = BNXT_ULP_CLASS_HID_41ba5, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 1342243584UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1070] = { - .class_hid = BNXT_ULP_CLASS_HID_40b0f, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 1342245632UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1071] = { - .class_hid = BNXT_ULP_CLASS_HID_50b0b, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 1342505728UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1072] = { - .class_hid = BNXT_ULP_CLASS_HID_51a8f, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 1342507776UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1073] = { - .class_hid = BNXT_ULP_CLASS_HID_48303, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 1342767872UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1074] = { - .class_hid = BNXT_ULP_CLASS_HID_49307, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 1342769920UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1075] = { - .class_hid = BNXT_ULP_CLASS_HID_592a3, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 1343030016UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1076] = { - .class_hid = BNXT_ULP_CLASS_HID_58205, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 1343032064UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1077] = { - .class_hid = BNXT_ULP_CLASS_HID_4172f, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 1476461312UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1078] = { - .class_hid = BNXT_ULP_CLASS_HID_40621, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 1476463360UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1079] = { - .class_hid = BNXT_ULP_CLASS_HID_5062d, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 1476723456UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1080] = { - .class_hid = BNXT_ULP_CLASS_HID_51621, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 1476725504UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1081] = { - .class_hid = BNXT_ULP_CLASS_HID_49f07, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 1476985600UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1082] = { - .class_hid = BNXT_ULP_CLASS_HID_48e29, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 1476987648UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1083] = { - .class_hid = BNXT_ULP_CLASS_HID_58e25, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 1477247744UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1084] = { - .class_hid = BNXT_ULP_CLASS_HID_59d29, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 1477249792UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1085] = { - .class_hid = BNXT_ULP_CLASS_HID_400c9, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 1610679040UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1086] = { - .class_hid = BNXT_ULP_CLASS_HID_4108d, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 1610681088UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1087] = { - .class_hid = BNXT_ULP_CLASS_HID_51049, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 1610941184UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1088] = { - .class_hid = BNXT_ULP_CLASS_HID_50fc3, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 1610943232UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1089] = { - .class_hid = BNXT_ULP_CLASS_HID_48881, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 1611203328UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1090] = { - .class_hid = BNXT_ULP_CLASS_HID_487cb, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 1611205376UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1091] = { - .class_hid = BNXT_ULP_CLASS_HID_587c7, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 1611465472UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1092] = { - .class_hid = BNXT_ULP_CLASS_HID_5978b, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 1611467520UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1093] = { - .class_hid = BNXT_ULP_CLASS_HID_41c4d, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 1744896768UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1094] = { - .class_hid = BNXT_ULP_CLASS_HID_40b47, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 1744898816UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1095] = { - .class_hid = BNXT_ULP_CLASS_HID_50b03, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 1745158912UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1096] = { - .class_hid = BNXT_ULP_CLASS_HID_51b47, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 1745160960UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1097] = { - .class_hid = BNXT_ULP_CLASS_HID_4834b, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 1745421056UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1098] = { - .class_hid = BNXT_ULP_CLASS_HID_4930f, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 1745423104UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1099] = { - .class_hid = BNXT_ULP_CLASS_HID_5934b, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 1745683200UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1100] = { - .class_hid = BNXT_ULP_CLASS_HID_5824d, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 1745685248UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1101] = { - .class_hid = BNXT_ULP_CLASS_HID_41687, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 1879114496UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1102] = { - .class_hid = BNXT_ULP_CLASS_HID_40609, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 1879116544UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1103] = { - .class_hid = BNXT_ULP_CLASS_HID_50585, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 1879376640UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1104] = { - .class_hid = BNXT_ULP_CLASS_HID_51589, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 1879378688UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1105] = { - .class_hid = BNXT_ULP_CLASS_HID_49e0f, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 1879638784UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1106] = { - .class_hid = BNXT_ULP_CLASS_HID_48d81, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 1879640832UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1107] = { - .class_hid = BNXT_ULP_CLASS_HID_58d8d, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 1879900928UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1108] = { - .class_hid = BNXT_ULP_CLASS_HID_59d01, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 1879902976UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1109] = { - .class_hid = BNXT_ULP_CLASS_HID_40109, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 2013332224UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1110] = { - .class_hid = BNXT_ULP_CLASS_HID_4110d, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 2013334272UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1111] = { - .class_hid = BNXT_ULP_CLASS_HID_51109, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 2013594368UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1112] = { - .class_hid = BNXT_ULP_CLASS_HID_50003, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 2013596416UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1113] = { - .class_hid = BNXT_ULP_CLASS_HID_48901, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 2013856512UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1114] = { - .class_hid = BNXT_ULP_CLASS_HID_49905, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 2013858560UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1115] = { - .class_hid = BNXT_ULP_CLASS_HID_59901, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 2014118656UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1116] = { - .class_hid = BNXT_ULP_CLASS_HID_5880b, - .class_tid = 2, - .hdr_sig_id = 23, - .flow_sig_id = 2014120704UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT } - }, - [1117] = { - .class_hid = BNXT_ULP_CLASS_HID_10619, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 265216UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI } - }, - [1118] = { - .class_hid = BNXT_ULP_CLASS_HID_11239, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 273408UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI } - }, - [1119] = { - .class_hid = BNXT_ULP_CLASS_HID_14205, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 1313792UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC } - }, - [1120] = { - .class_hid = BNXT_ULP_CLASS_HID_15e25, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 1321984UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC } - }, - [1121] = { - .class_hid = BNXT_ULP_CLASS_HID_12417, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 2362368UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC } - }, - [1122] = { - .class_hid = BNXT_ULP_CLASS_HID_13037, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 2370560UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC } - }, - [1123] = { - .class_hid = BNXT_ULP_CLASS_HID_16ff3, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 3410944UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC } - }, - [1124] = { - .class_hid = BNXT_ULP_CLASS_HID_17c13, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 3419136UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC } - }, - [1125] = { - .class_hid = BNXT_ULP_CLASS_HID_1111d, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 537136128UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR } - }, - [1126] = { - .class_hid = BNXT_ULP_CLASS_HID_10cdb, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 537144320UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR } - }, - [1127] = { - .class_hid = BNXT_ULP_CLASS_HID_15d19, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 538184704UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR } - }, - [1128] = { - .class_hid = BNXT_ULP_CLASS_HID_148c7, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 538192896UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR } - }, - [1129] = { - .class_hid = BNXT_ULP_CLASS_HID_13f0b, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 539233280UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR } - }, - [1130] = { - .class_hid = BNXT_ULP_CLASS_HID_12ac9, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 539241472UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR } - }, - [1131] = { - .class_hid = BNXT_ULP_CLASS_HID_17b17, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 540281856UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR } - }, - [1132] = { - .class_hid = BNXT_ULP_CLASS_HID_176d5, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 540290048UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR } - }, - [1133] = { - .class_hid = BNXT_ULP_CLASS_HID_10bab, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 1074007040UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR } - }, - [1134] = { - .class_hid = BNXT_ULP_CLASS_HID_10769, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 1074015232UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR } - }, - [1135] = { - .class_hid = BNXT_ULP_CLASS_HID_15787, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 1075055616UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR } - }, - [1136] = { - .class_hid = BNXT_ULP_CLASS_HID_14345, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 1075063808UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR } - }, - [1137] = { - .class_hid = BNXT_ULP_CLASS_HID_12989, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 1076104192UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR } - }, - [1138] = { - .class_hid = BNXT_ULP_CLASS_HID_12567, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 1076112384UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR } - }, - [1139] = { - .class_hid = BNXT_ULP_CLASS_HID_17585, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 1077152768UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR } - }, - [1140] = { - .class_hid = BNXT_ULP_CLASS_HID_16143, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 1077160960UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR } - }, - [1141] = { - .class_hid = BNXT_ULP_CLASS_HID_1064d, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 1610877952UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR } - }, - [1142] = { - .class_hid = BNXT_ULP_CLASS_HID_1128d, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 1610886144UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR } - }, - [1143] = { - .class_hid = BNXT_ULP_CLASS_HID_14249, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 1611926528UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR } - }, - [1144] = { - .class_hid = BNXT_ULP_CLASS_HID_15e49, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 1611934720UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR } - }, - [1145] = { - .class_hid = BNXT_ULP_CLASS_HID_1244b, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 1612975104UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR } - }, - [1146] = { - .class_hid = BNXT_ULP_CLASS_HID_1304b, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 1612983296UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR } - }, - [1147] = { - .class_hid = BNXT_ULP_CLASS_HID_16047, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 1614023680UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR } - }, - [1148] = { - .class_hid = BNXT_ULP_CLASS_HID_17c47, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 1614031872UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR } - }, - [1149] = { - .class_hid = BNXT_ULP_CLASS_HID_11113, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 2147748864UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT } - }, - [1150] = { - .class_hid = BNXT_ULP_CLASS_HID_10cd1, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 2147757056UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT } - }, - [1151] = { - .class_hid = BNXT_ULP_CLASS_HID_15cf7, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 2148797440UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT } - }, - [1152] = { - .class_hid = BNXT_ULP_CLASS_HID_148b5, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 2148805632UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT } - }, - [1153] = { - .class_hid = BNXT_ULP_CLASS_HID_13f01, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 2149846016UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT } - }, - [1154] = { - .class_hid = BNXT_ULP_CLASS_HID_12ac7, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 2149854208UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT } - }, - [1155] = { - .class_hid = BNXT_ULP_CLASS_HID_17ae5, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 2150894592UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT } - }, - [1156] = { - .class_hid = BNXT_ULP_CLASS_HID_176a3, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 2150902784UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT } - }, - [1157] = { - .class_hid = BNXT_ULP_CLASS_HID_10bd5, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 2684619776UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT } - }, - [1158] = { - .class_hid = BNXT_ULP_CLASS_HID_10793, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 2684627968UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT } - }, - [1159] = { - .class_hid = BNXT_ULP_CLASS_HID_15791, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 2685668352UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT } - }, - [1160] = { - .class_hid = BNXT_ULP_CLASS_HID_14357, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 2685676544UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT } - }, - [1161] = { - .class_hid = BNXT_ULP_CLASS_HID_129c3, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 2686716928UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT } - }, - [1162] = { - .class_hid = BNXT_ULP_CLASS_HID_12581, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 2686725120UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT } - }, - [1163] = { - .class_hid = BNXT_ULP_CLASS_HID_17587, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 2687765504UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT } - }, - [1164] = { - .class_hid = BNXT_ULP_CLASS_HID_16145, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 2687773696UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT } - }, - [1165] = { - .class_hid = BNXT_ULP_CLASS_HID_10643, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 3221490688UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT } - }, - [1166] = { - .class_hid = BNXT_ULP_CLASS_HID_11263, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 3221498880UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT } - }, - [1167] = { - .class_hid = BNXT_ULP_CLASS_HID_14227, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 3222539264UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT } - }, - [1168] = { - .class_hid = BNXT_ULP_CLASS_HID_15e47, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 3222547456UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT } - }, - [1169] = { - .class_hid = BNXT_ULP_CLASS_HID_12421, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 3223587840UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT } - }, - [1170] = { - .class_hid = BNXT_ULP_CLASS_HID_13041, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 3223596032UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT } - }, - [1171] = { - .class_hid = BNXT_ULP_CLASS_HID_16005, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 3224636416UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT } - }, - [1172] = { - .class_hid = BNXT_ULP_CLASS_HID_17c25, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 3224644608UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT } - }, - [1173] = { - .class_hid = BNXT_ULP_CLASS_HID_11147, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 3758361600UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT } - }, - [1174] = { - .class_hid = BNXT_ULP_CLASS_HID_10d05, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 3758369792UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT } - }, - [1175] = { - .class_hid = BNXT_ULP_CLASS_HID_15d43, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 3759410176UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT } - }, - [1176] = { - .class_hid = BNXT_ULP_CLASS_HID_14901, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 3759418368UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT } - }, - [1177] = { - .class_hid = BNXT_ULP_CLASS_HID_13f45, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 3760458752UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT } - }, - [1178] = { - .class_hid = BNXT_ULP_CLASS_HID_12b03, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 3760466944UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT } - }, - [1179] = { - .class_hid = BNXT_ULP_CLASS_HID_17b01, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 3761507328UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT } - }, - [1180] = { - .class_hid = BNXT_ULP_CLASS_HID_176c7, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 3761515520UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT } - }, - [1181] = { - .class_hid = BNXT_ULP_CLASS_HID_11bcf, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 4295232512UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1182] = { - .class_hid = BNXT_ULP_CLASS_HID_1178d, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 4295240704UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1183] = { - .class_hid = BNXT_ULP_CLASS_HID_1474d, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 4296281088UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1184] = { - .class_hid = BNXT_ULP_CLASS_HID_1536d, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 4296289280UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1185] = { - .class_hid = BNXT_ULP_CLASS_HID_139bd, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 4297329664UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1186] = { - .class_hid = BNXT_ULP_CLASS_HID_1357f, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 4297337856UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1187] = { - .class_hid = BNXT_ULP_CLASS_HID_16547, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 4298378240UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1188] = { - .class_hid = BNXT_ULP_CLASS_HID_17167, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 4298386432UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1189] = { - .class_hid = BNXT_ULP_CLASS_HID_11685, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 4832103424UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1190] = { - .class_hid = BNXT_ULP_CLASS_HID_1024f, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 4832111616UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1191] = { - .class_hid = BNXT_ULP_CLASS_HID_1524d, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 4833152000UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1192] = { - .class_hid = BNXT_ULP_CLASS_HID_14e0f, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 4833160192UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1193] = { - .class_hid = BNXT_ULP_CLASS_HID_1345f, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 4834200576UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1194] = { - .class_hid = BNXT_ULP_CLASS_HID_1201d, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 4834208768UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1195] = { - .class_hid = BNXT_ULP_CLASS_HID_1705f, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 4835249152UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1196] = { - .class_hid = BNXT_ULP_CLASS_HID_16c1d, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 4835257344UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1197] = { - .class_hid = BNXT_ULP_CLASS_HID_100ef, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 5368974336UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1198] = { - .class_hid = BNXT_ULP_CLASS_HID_11d0f, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 5368982528UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1199] = { - .class_hid = BNXT_ULP_CLASS_HID_14ccf, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 5370022912UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1200] = { - .class_hid = BNXT_ULP_CLASS_HID_158ef, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 5370031104UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1201] = { - .class_hid = BNXT_ULP_CLASS_HID_12eed, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 5371071488UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1202] = { - .class_hid = BNXT_ULP_CLASS_HID_13b0d, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 5371079680UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1203] = { - .class_hid = BNXT_ULP_CLASS_HID_16acd, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 5372120064UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1204] = { - .class_hid = BNXT_ULP_CLASS_HID_16687, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 5372128256UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1205] = { - .class_hid = BNXT_ULP_CLASS_HID_11c07, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 5905845248UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1206] = { - .class_hid = BNXT_ULP_CLASS_HID_117c5, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 5905853440UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1207] = { - .class_hid = BNXT_ULP_CLASS_HID_1478d, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 5906893824UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1208] = { - .class_hid = BNXT_ULP_CLASS_HID_1538d, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 5906902016UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1209] = { - .class_hid = BNXT_ULP_CLASS_HID_13a05, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 5907942400UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1210] = { - .class_hid = BNXT_ULP_CLASS_HID_135cf, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 5907950592UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1211] = { - .class_hid = BNXT_ULP_CLASS_HID_1658f, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 5908990976UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1212] = { - .class_hid = BNXT_ULP_CLASS_HID_1718f, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 5908999168UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1213] = { - .class_hid = BNXT_ULP_CLASS_HID_11667, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 6442716160UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1214] = { - .class_hid = BNXT_ULP_CLASS_HID_10225, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 6442724352UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1215] = { - .class_hid = BNXT_ULP_CLASS_HID_15247, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 6443764736UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1216] = { - .class_hid = BNXT_ULP_CLASS_HID_14e05, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 6443772928UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1217] = { - .class_hid = BNXT_ULP_CLASS_HID_13455, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 6444813312UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1218] = { - .class_hid = BNXT_ULP_CLASS_HID_12017, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 6444821504UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1219] = { - .class_hid = BNXT_ULP_CLASS_HID_17035, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 6445861888UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1220] = { - .class_hid = BNXT_ULP_CLASS_HID_16bf7, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 6445870080UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1221] = { - .class_hid = BNXT_ULP_CLASS_HID_10115, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 6979587072UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1222] = { - .class_hid = BNXT_ULP_CLASS_HID_11d15, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 6979595264UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1223] = { - .class_hid = BNXT_ULP_CLASS_HID_14d05, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 6980635648UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1224] = { - .class_hid = BNXT_ULP_CLASS_HID_15905, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 6980643840UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1225] = { - .class_hid = BNXT_ULP_CLASS_HID_12f17, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 6981684224UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1226] = { - .class_hid = BNXT_ULP_CLASS_HID_13b17, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 6981692416UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1227] = { - .class_hid = BNXT_ULP_CLASS_HID_16ad7, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 6982732800UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1228] = { - .class_hid = BNXT_ULP_CLASS_HID_16695, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 6982740992UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1229] = { - .class_hid = BNXT_ULP_CLASS_HID_11be5, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 7516457984UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1230] = { - .class_hid = BNXT_ULP_CLASS_HID_117a7, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 7516466176UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1231] = { - .class_hid = BNXT_ULP_CLASS_HID_14767, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 7517506560UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1232] = { - .class_hid = BNXT_ULP_CLASS_HID_15387, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 7517514752UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1233] = { - .class_hid = BNXT_ULP_CLASS_HID_139e7, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 7518555136UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1234] = { - .class_hid = BNXT_ULP_CLASS_HID_135a5, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 7518563328UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1235] = { - .class_hid = BNXT_ULP_CLASS_HID_16565, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 7519603712UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1236] = { - .class_hid = BNXT_ULP_CLASS_HID_17185, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 7519611904UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1237] = { - .class_hid = BNXT_ULP_CLASS_HID_11687, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 8053328896UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1238] = { - .class_hid = BNXT_ULP_CLASS_HID_10245, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 8053337088UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1239] = { - .class_hid = BNXT_ULP_CLASS_HID_15287, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 8054377472UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1240] = { - .class_hid = BNXT_ULP_CLASS_HID_14e45, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 8054385664UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1241] = { - .class_hid = BNXT_ULP_CLASS_HID_13485, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 8055426048UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1242] = { - .class_hid = BNXT_ULP_CLASS_HID_12047, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 8055434240UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1243] = { - .class_hid = BNXT_ULP_CLASS_HID_17085, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 8056474624UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1244] = { - .class_hid = BNXT_ULP_CLASS_HID_16c47, - .class_tid = 2, - .hdr_sig_id = 24, - .flow_sig_id = 8056482816UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV6 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT } - }, - [1245] = { - .class_hid = BNXT_ULP_CLASS_HID_400f4, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 66304UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI } - }, - [1246] = { - .class_hid = BNXT_ULP_CLASS_HID_410c8, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 68352UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI } - }, - [1247] = { - .class_hid = BNXT_ULP_CLASS_HID_51084, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 328448UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC } - }, - [1248] = { - .class_hid = BNXT_ULP_CLASS_HID_50ffe, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 330496UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC } - }, - [1249] = { - .class_hid = BNXT_ULP_CLASS_HID_488cc, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 590592UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC } - }, - [1250] = { - .class_hid = BNXT_ULP_CLASS_HID_48726, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 592640UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC } - }, - [1251] = { - .class_hid = BNXT_ULP_CLASS_HID_587f2, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 852736UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC } - }, - [1252] = { - .class_hid = BNXT_ULP_CLASS_HID_597b6, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 854784UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC } - }, - [1253] = { - .class_hid = BNXT_ULP_CLASS_HID_41b10, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 536937216UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR } - }, - [1254] = { - .class_hid = BNXT_ULP_CLASS_HID_40b8a, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 536939264UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR } - }, - [1255] = { - .class_hid = BNXT_ULP_CLASS_HID_50a46, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 537199360UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR } - }, - [1256] = { - .class_hid = BNXT_ULP_CLASS_HID_51a1a, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 537201408UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR } - }, - [1257] = { - .class_hid = BNXT_ULP_CLASS_HID_4838e, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 537461504UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR } - }, - [1258] = { - .class_hid = BNXT_ULP_CLASS_HID_49242, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 537463552UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR } - }, - [1259] = { - .class_hid = BNXT_ULP_CLASS_HID_5921e, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 537723648UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR } - }, - [1260] = { - .class_hid = BNXT_ULP_CLASS_HID_58150, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 537725696UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR } - }, - [1261] = { - .class_hid = BNXT_ULP_CLASS_HID_41686, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 1073808128UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR } - }, - [1262] = { - .class_hid = BNXT_ULP_CLASS_HID_405e8, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 1073810176UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR } - }, - [1263] = { - .class_hid = BNXT_ULP_CLASS_HID_505a4, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 1074070272UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR } - }, - [1264] = { - .class_hid = BNXT_ULP_CLASS_HID_51588, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 1074072320UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR } - }, - [1265] = { - .class_hid = BNXT_ULP_CLASS_HID_49d4e, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 1074332416UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR } - }, - [1266] = { - .class_hid = BNXT_ULP_CLASS_HID_48da0, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 1074334464UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR } - }, - [1267] = { - .class_hid = BNXT_ULP_CLASS_HID_58d8c, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 1074594560UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR } - }, - [1268] = { - .class_hid = BNXT_ULP_CLASS_HID_59c40, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 1074596608UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR } - }, - [1269] = { - .class_hid = BNXT_ULP_CLASS_HID_40040, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 1610679040UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR } - }, - [1270] = { - .class_hid = BNXT_ULP_CLASS_HID_41004, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 1610681088UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR } - }, - [1271] = { - .class_hid = BNXT_ULP_CLASS_HID_510c0, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 1610941184UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR } - }, - [1272] = { - .class_hid = BNXT_ULP_CLASS_HID_50f4a, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 1610943232UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR } - }, - [1273] = { - .class_hid = BNXT_ULP_CLASS_HID_48808, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 1611203328UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR } - }, - [1274] = { - .class_hid = BNXT_ULP_CLASS_HID_48742, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 1611205376UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR } - }, - [1275] = { - .class_hid = BNXT_ULP_CLASS_HID_5874e, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 1611465472UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR } - }, - [1276] = { - .class_hid = BNXT_ULP_CLASS_HID_59702, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 1611467520UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR } - }, - [1277] = { - .class_hid = BNXT_ULP_CLASS_HID_41bfe, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 2147549952UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT } - }, - [1278] = { - .class_hid = BNXT_ULP_CLASS_HID_40a58, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 2147552000UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT } - }, - [1279] = { - .class_hid = BNXT_ULP_CLASS_HID_50a2c, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 2147812096UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT } - }, - [1280] = { - .class_hid = BNXT_ULP_CLASS_HID_51ae8, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 2147814144UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT } - }, - [1281] = { - .class_hid = BNXT_ULP_CLASS_HID_4825c, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 2148074240UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT } - }, - [1282] = { - .class_hid = BNXT_ULP_CLASS_HID_49228, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 2148076288UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT } - }, - [1283] = { - .class_hid = BNXT_ULP_CLASS_HID_592ec, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 2148336384UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT } - }, - [1284] = { - .class_hid = BNXT_ULP_CLASS_HID_5815e, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 2148338432UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT } - }, - [1285] = { - .class_hid = BNXT_ULP_CLASS_HID_41698, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 2684420864UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT } - }, - [1286] = { - .class_hid = BNXT_ULP_CLASS_HID_4051a, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 2684422912UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT } - }, - [1287] = { - .class_hid = BNXT_ULP_CLASS_HID_505ce, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 2684683008UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT } - }, - [1288] = { - .class_hid = BNXT_ULP_CLASS_HID_5158a, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 2684685056UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT } - }, - [1289] = { - .class_hid = BNXT_ULP_CLASS_HID_49d58, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 2684945152UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT } - }, - [1290] = { - .class_hid = BNXT_ULP_CLASS_HID_48dca, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 2684947200UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT } - }, - [1291] = { - .class_hid = BNXT_ULP_CLASS_HID_58d8e, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 2685207296UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT } - }, - [1292] = { - .class_hid = BNXT_ULP_CLASS_HID_59c5a, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 2685209344UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT } - }, - [1293] = { - .class_hid = BNXT_ULP_CLASS_HID_4002e, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 3221291776UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT } - }, - [1294] = { - .class_hid = BNXT_ULP_CLASS_HID_410ea, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 3221293824UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT } - }, - [1295] = { - .class_hid = BNXT_ULP_CLASS_HID_510ae, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 3221553920UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT } - }, - [1296] = { - .class_hid = BNXT_ULP_CLASS_HID_50f08, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 3221555968UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT } - }, - [1297] = { - .class_hid = BNXT_ULP_CLASS_HID_488ee, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 3221816064UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT } - }, - [1298] = { - .class_hid = BNXT_ULP_CLASS_HID_48748, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 3221818112UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT } - }, - [1299] = { - .class_hid = BNXT_ULP_CLASS_HID_5870c, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 3222078208UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT } - }, - [1300] = { - .class_hid = BNXT_ULP_CLASS_HID_597e8, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 3222080256UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT } - }, - [1301] = { - .class_hid = BNXT_ULP_CLASS_HID_41b4a, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 3758162688UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT } - }, - [1302] = { - .class_hid = BNXT_ULP_CLASS_HID_40b8c, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 3758164736UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT } - }, - [1303] = { - .class_hid = BNXT_ULP_CLASS_HID_50a48, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 3758424832UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT } - }, - [1304] = { - .class_hid = BNXT_ULP_CLASS_HID_51a0c, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 3758426880UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT } - }, - [1305] = { - .class_hid = BNXT_ULP_CLASS_HID_48388, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 3758686976UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT } - }, - [1306] = { - .class_hid = BNXT_ULP_CLASS_HID_4924c, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 3758689024UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT } - }, - [1307] = { - .class_hid = BNXT_ULP_CLASS_HID_59208, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 3758949120UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT } - }, - [1308] = { - .class_hid = BNXT_ULP_CLASS_HID_5828a, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 3758951168UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT } - }, - [1309] = { - .class_hid = BNXT_ULP_CLASS_HID_40540, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 4295033600UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1310] = { - .class_hid = BNXT_ULP_CLASS_HID_41500, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 4295035648UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1311] = { - .class_hid = BNXT_ULP_CLASS_HID_515d0, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 4295295744UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1312] = { - .class_hid = BNXT_ULP_CLASS_HID_5044a, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 4295297792UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1313] = { - .class_hid = BNXT_ULP_CLASS_HID_48d18, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 4295557888UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1314] = { - .class_hid = BNXT_ULP_CLASS_HID_49dd8, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 4295559936UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1315] = { - .class_hid = BNXT_ULP_CLASS_HID_59da8, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 4295820032UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1316] = { - .class_hid = BNXT_ULP_CLASS_HID_58c02, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 4295822080UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1317] = { - .class_hid = BNXT_ULP_CLASS_HID_41048, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 4831904512UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1318] = { - .class_hid = BNXT_ULP_CLASS_HID_400c2, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 4831906560UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1319] = { - .class_hid = BNXT_ULP_CLASS_HID_50092, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 4832166656UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1320] = { - .class_hid = BNXT_ULP_CLASS_HID_51f52, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 4832168704UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1321] = { - .class_hid = BNXT_ULP_CLASS_HID_49800, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 4832428800UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1322] = { - .class_hid = BNXT_ULP_CLASS_HID_4889a, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 4832430848UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1323] = { - .class_hid = BNXT_ULP_CLASS_HID_5974a, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 4832690944UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1324] = { - .class_hid = BNXT_ULP_CLASS_HID_587c8, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 4832692992UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1325] = { - .class_hid = BNXT_ULP_CLASS_HID_40bc2, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 5368775424UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1326] = { - .class_hid = BNXT_ULP_CLASS_HID_41b82, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 5368777472UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1327] = { - .class_hid = BNXT_ULP_CLASS_HID_51a62, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 5369037568UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1328] = { - .class_hid = BNXT_ULP_CLASS_HID_50ac0, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 5369039616UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1329] = { - .class_hid = BNXT_ULP_CLASS_HID_493aa, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 5369299712UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1330] = { - .class_hid = BNXT_ULP_CLASS_HID_48208, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 5369301760UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1331] = { - .class_hid = BNXT_ULP_CLASS_HID_582c8, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 5369561856UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1332] = { - .class_hid = BNXT_ULP_CLASS_HID_59288, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 5369563904UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1333] = { - .class_hid = BNXT_ULP_CLASS_HID_40688, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 5905646336UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1334] = { - .class_hid = BNXT_ULP_CLASS_HID_41540, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 5905648384UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1335] = { - .class_hid = BNXT_ULP_CLASS_HID_51508, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 5905908480UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1336] = { - .class_hid = BNXT_ULP_CLASS_HID_50582, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 5905910528UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1337] = { - .class_hid = BNXT_ULP_CLASS_HID_48d40, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 5906170624UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1338] = { - .class_hid = BNXT_ULP_CLASS_HID_49d08, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 5906172672UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1339] = { - .class_hid = BNXT_ULP_CLASS_HID_59dc0, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 5906432768UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1340] = { - .class_hid = BNXT_ULP_CLASS_HID_58c4a, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 5906434816UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1341] = { - .class_hid = BNXT_ULP_CLASS_HID_4104a, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 6442517248UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1342] = { - .class_hid = BNXT_ULP_CLASS_HID_400a8, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 6442519296UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1343] = { - .class_hid = BNXT_ULP_CLASS_HID_50f78, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 6442779392UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1344] = { - .class_hid = BNXT_ULP_CLASS_HID_51f38, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 6442781440UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1345] = { - .class_hid = BNXT_ULP_CLASS_HID_4980a, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 6443041536UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1346] = { - .class_hid = BNXT_ULP_CLASS_HID_49768, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 6443043584UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1347] = { - .class_hid = BNXT_ULP_CLASS_HID_59738, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 6443303680UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1348] = { - .class_hid = BNXT_ULP_CLASS_HID_587aa, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 6443305728UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1349] = { - .class_hid = BNXT_ULP_CLASS_HID_40bd8, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 6979388160UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1350] = { - .class_hid = BNXT_ULP_CLASS_HID_41bc8, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 6979390208UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1351] = { - .class_hid = BNXT_ULP_CLASS_HID_51b88, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 6979650304UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1352] = { - .class_hid = BNXT_ULP_CLASS_HID_50ada, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 6979652352UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1353] = { - .class_hid = BNXT_ULP_CLASS_HID_493c8, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 6979912448UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1354] = { - .class_hid = BNXT_ULP_CLASS_HID_4820a, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 6979914496UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1355] = { - .class_hid = BNXT_ULP_CLASS_HID_582da, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 6980174592UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1356] = { - .class_hid = BNXT_ULP_CLASS_HID_5929a, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 6980176640UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1357] = { - .class_hid = BNXT_ULP_CLASS_HID_4056a, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 7516259072UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1358] = { - .class_hid = BNXT_ULP_CLASS_HID_4152a, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 7516261120UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1359] = { - .class_hid = BNXT_ULP_CLASS_HID_5150a, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 7516521216UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1360] = { - .class_hid = BNXT_ULP_CLASS_HID_50468, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 7516523264UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1361] = { - .class_hid = BNXT_ULP_CLASS_HID_48d2a, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 7516783360UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1362] = { - .class_hid = BNXT_ULP_CLASS_HID_49dea, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 7516785408UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1363] = { - .class_hid = BNXT_ULP_CLASS_HID_59dca, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 7517045504UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1364] = { - .class_hid = BNXT_ULP_CLASS_HID_58c28, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 7517047552UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1365] = { - .class_hid = BNXT_ULP_CLASS_HID_4118a, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 8053129984UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1366] = { - .class_hid = BNXT_ULP_CLASS_HID_400c8, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 8053132032UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1367] = { - .class_hid = BNXT_ULP_CLASS_HID_50088, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 8053392128UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1368] = { - .class_hid = BNXT_ULP_CLASS_HID_51088, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 8053394176UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1369] = { - .class_hid = BNXT_ULP_CLASS_HID_4984a, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 8053654272UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1370] = { - .class_hid = BNXT_ULP_CLASS_HID_48888, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 8053656320UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1371] = { - .class_hid = BNXT_ULP_CLASS_HID_58888, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 8053916416UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1372] = { - .class_hid = BNXT_ULP_CLASS_HID_587ca, - .class_tid = 2, - .hdr_sig_id = 25, - .flow_sig_id = 8053918464UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT } - }, - [1373] = { - .class_hid = BNXT_ULP_CLASS_HID_10690, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 265216UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI } - }, - [1374] = { - .class_hid = BNXT_ULP_CLASS_HID_112b0, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 273408UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI } - }, - [1375] = { - .class_hid = BNXT_ULP_CLASS_HID_1428c, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 1313792UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC } - }, - [1376] = { - .class_hid = BNXT_ULP_CLASS_HID_15eac, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 1321984UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC } - }, - [1377] = { - .class_hid = BNXT_ULP_CLASS_HID_1249e, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 2362368UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC } - }, - [1378] = { - .class_hid = BNXT_ULP_CLASS_HID_130be, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 2370560UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC } - }, - [1379] = { - .class_hid = BNXT_ULP_CLASS_HID_16f7a, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 3410944UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC } - }, - [1380] = { - .class_hid = BNXT_ULP_CLASS_HID_17c9a, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 3419136UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC } - }, - [1381] = { - .class_hid = BNXT_ULP_CLASS_HID_1119a, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 2147748864UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR } - }, - [1382] = { - .class_hid = BNXT_ULP_CLASS_HID_10c58, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 2147757056UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR } - }, - [1383] = { - .class_hid = BNXT_ULP_CLASS_HID_15c7e, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 2148797440UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR } - }, - [1384] = { - .class_hid = BNXT_ULP_CLASS_HID_1483c, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 2148805632UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR } - }, - [1385] = { - .class_hid = BNXT_ULP_CLASS_HID_13f88, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 2149846016UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR } - }, - [1386] = { - .class_hid = BNXT_ULP_CLASS_HID_12a4e, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 2149854208UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR } - }, - [1387] = { - .class_hid = BNXT_ULP_CLASS_HID_17a6c, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 2150894592UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR } - }, - [1388] = { - .class_hid = BNXT_ULP_CLASS_HID_1762a, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 2150902784UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR } - }, - [1389] = { - .class_hid = BNXT_ULP_CLASS_HID_11b46, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 4295232512UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR } - }, - [1390] = { - .class_hid = BNXT_ULP_CLASS_HID_11704, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 4295240704UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR } - }, - [1391] = { - .class_hid = BNXT_ULP_CLASS_HID_147c4, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 4296281088UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR } - }, - [1392] = { - .class_hid = BNXT_ULP_CLASS_HID_153e4, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 4296289280UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR } - }, - [1393] = { - .class_hid = BNXT_ULP_CLASS_HID_13934, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 4297329664UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR } - }, - [1394] = { - .class_hid = BNXT_ULP_CLASS_HID_135f6, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 4297337856UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR } - }, - [1395] = { - .class_hid = BNXT_ULP_CLASS_HID_165ce, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 4298378240UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR } - }, - [1396] = { - .class_hid = BNXT_ULP_CLASS_HID_171ee, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 4298386432UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR } - }, - [1397] = { - .class_hid = BNXT_ULP_CLASS_HID_116ee, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 6442716160UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR } - }, - [1398] = { - .class_hid = BNXT_ULP_CLASS_HID_102ac, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 6442724352UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR } - }, - [1399] = { - .class_hid = BNXT_ULP_CLASS_HID_152ce, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 6443764736UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR } - }, - [1400] = { - .class_hid = BNXT_ULP_CLASS_HID_14e8c, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 6443772928UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR } - }, - [1401] = { - .class_hid = BNXT_ULP_CLASS_HID_134dc, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 6444813312UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR } - }, - [1402] = { - .class_hid = BNXT_ULP_CLASS_HID_1209e, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 6444821504UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR } - }, - [1403] = { - .class_hid = BNXT_ULP_CLASS_HID_170bc, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 6445861888UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR } - }, - [1404] = { - .class_hid = BNXT_ULP_CLASS_HID_16b7e, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 6445870080UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR } - }, - [1405] = { - .class_hid = BNXT_ULP_CLASS_HID_119ae, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 8590199808UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT } - }, - [1406] = { - .class_hid = BNXT_ULP_CLASS_HID_1146a, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 8590208000UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT } - }, - [1407] = { - .class_hid = BNXT_ULP_CLASS_HID_14426, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 8591248384UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT } - }, - [1408] = { - .class_hid = BNXT_ULP_CLASS_HID_15046, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 8591256576UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT } - }, - [1409] = { - .class_hid = BNXT_ULP_CLASS_HID_1263a, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 8592296960UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT } - }, - [1410] = { - .class_hid = BNXT_ULP_CLASS_HID_1325a, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 8592305152UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT } - }, - [1411] = { - .class_hid = BNXT_ULP_CLASS_HID_16216, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 8593345536UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT } - }, - [1412] = { - .class_hid = BNXT_ULP_CLASS_HID_17e36, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 8593353728UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT } - }, - [1413] = { - .class_hid = BNXT_ULP_CLASS_HID_1133e, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 10737683456UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT } - }, - [1414] = { - .class_hid = BNXT_ULP_CLASS_HID_10ffa, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 10737691648UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT } - }, - [1415] = { - .class_hid = BNXT_ULP_CLASS_HID_15f1a, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 10738732032UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT } - }, - [1416] = { - .class_hid = BNXT_ULP_CLASS_HID_14bee, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 10738740224UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT } - }, - [1417] = { - .class_hid = BNXT_ULP_CLASS_HID_1312a, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 10739780608UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT } - }, - [1418] = { - .class_hid = BNXT_ULP_CLASS_HID_12dea, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 10739788800UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT } - }, - [1419] = { - .class_hid = BNXT_ULP_CLASS_HID_17d1e, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 10740829184UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT } - }, - [1420] = { - .class_hid = BNXT_ULP_CLASS_HID_169de, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 10740837376UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT } - }, - [1421] = { - .class_hid = BNXT_ULP_CLASS_HID_11ee6, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 12885167104UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT } - }, - [1422] = { - .class_hid = BNXT_ULP_CLASS_HID_10abe, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 12885175296UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT } - }, - [1423] = { - .class_hid = BNXT_ULP_CLASS_HID_15ade, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 12886215680UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT } - }, - [1424] = { - .class_hid = BNXT_ULP_CLASS_HID_1569e, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 12886223872UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT } - }, - [1425] = { - .class_hid = BNXT_ULP_CLASS_HID_13cee, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 12887264256UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT } - }, - [1426] = { - .class_hid = BNXT_ULP_CLASS_HID_128ae, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 12887272448UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT } - }, - [1427] = { - .class_hid = BNXT_ULP_CLASS_HID_1676e, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 12888312832UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT } - }, - [1428] = { - .class_hid = BNXT_ULP_CLASS_HID_1748e, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 12888321024UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT } - }, - [1429] = { - .class_hid = BNXT_ULP_CLASS_HID_1098e, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 15032650752UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT } - }, - [1430] = { - .class_hid = BNXT_ULP_CLASS_HID_1044e, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 15032658944UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT } - }, - [1431] = { - .class_hid = BNXT_ULP_CLASS_HID_1546e, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 15033699328UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT } - }, - [1432] = { - .class_hid = BNXT_ULP_CLASS_HID_1402e, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 15033707520UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT } - }, - [1433] = { - .class_hid = BNXT_ULP_CLASS_HID_1367e, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 15034747904UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT } - }, - [1434] = { - .class_hid = BNXT_ULP_CLASS_HID_1223e, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 15034756096UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT } - }, - [1435] = { - .class_hid = BNXT_ULP_CLASS_HID_1725e, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 15035796480UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT } - }, - [1436] = { - .class_hid = BNXT_ULP_CLASS_HID_16e1e, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 15035804672UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT } - }, - [1437] = { - .class_hid = BNXT_ULP_CLASS_HID_1172f, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 17180134400UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1438] = { - .class_hid = BNXT_ULP_CLASS_HID_103ed, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 17180142592UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1439] = { - .class_hid = BNXT_ULP_CLASS_HID_1530b, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 17181182976UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1440] = { - .class_hid = BNXT_ULP_CLASS_HID_14fc9, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 17181191168UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1441] = { - .class_hid = BNXT_ULP_CLASS_HID_1351d, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 17182231552UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1442] = { - .class_hid = BNXT_ULP_CLASS_HID_121db, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 17182239744UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1443] = { - .class_hid = BNXT_ULP_CLASS_HID_171f9, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 17183280128UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1444] = { - .class_hid = BNXT_ULP_CLASS_HID_16db7, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 17183288320UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1445] = { - .class_hid = BNXT_ULP_CLASS_HID_102bf, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 19327618048UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1446] = { - .class_hid = BNXT_ULP_CLASS_HID_11edf, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 19327626240UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1447] = { - .class_hid = BNXT_ULP_CLASS_HID_14e9b, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 19328666624UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1448] = { - .class_hid = BNXT_ULP_CLASS_HID_15abb, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 19328674816UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1449] = { - .class_hid = BNXT_ULP_CLASS_HID_120ad, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 19329715200UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1450] = { - .class_hid = BNXT_ULP_CLASS_HID_13ccd, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 19329723392UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1451] = { - .class_hid = BNXT_ULP_CLASS_HID_16c89, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 19330763776UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1452] = { - .class_hid = BNXT_ULP_CLASS_HID_1675f, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 19330771968UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1453] = { - .class_hid = BNXT_ULP_CLASS_HID_10c67, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 21475101696UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1454] = { - .class_hid = BNXT_ULP_CLASS_HID_11987, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 21475109888UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1455] = { - .class_hid = BNXT_ULP_CLASS_HID_1485f, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 21476150272UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1456] = { - .class_hid = BNXT_ULP_CLASS_HID_1441d, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 21476158464UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1457] = { - .class_hid = BNXT_ULP_CLASS_HID_12a55, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 21477198848UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1458] = { - .class_hid = BNXT_ULP_CLASS_HID_1262f, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 21477207040UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1459] = { - .class_hid = BNXT_ULP_CLASS_HID_1764d, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 21478247424UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1460] = { - .class_hid = BNXT_ULP_CLASS_HID_1620f, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 21478255616UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1461] = { - .class_hid = BNXT_ULP_CLASS_HID_1070f, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 23622585344UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1462] = { - .class_hid = BNXT_ULP_CLASS_HID_1132f, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 23622593536UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1463] = { - .class_hid = BNXT_ULP_CLASS_HID_143ef, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 23623633920UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1464] = { - .class_hid = BNXT_ULP_CLASS_HID_15f0f, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 23623642112UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1465] = { - .class_hid = BNXT_ULP_CLASS_HID_125fd, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 23624682496UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1466] = { - .class_hid = BNXT_ULP_CLASS_HID_1311d, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 23624690688UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1467] = { - .class_hid = BNXT_ULP_CLASS_HID_161dd, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 23625731072UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1468] = { - .class_hid = BNXT_ULP_CLASS_HID_17dfd, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 23625739264UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1469] = { - .class_hid = BNXT_ULP_CLASS_HID_10acb, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 25770068992UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1470] = { - .class_hid = BNXT_ULP_CLASS_HID_10687, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 25770077184UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1471] = { - .class_hid = BNXT_ULP_CLASS_HID_156a7, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 25771117568UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1472] = { - .class_hid = BNXT_ULP_CLASS_HID_14163, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 25771125760UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1473] = { - .class_hid = BNXT_ULP_CLASS_HID_128b7, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 25772166144UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1474] = { - .class_hid = BNXT_ULP_CLASS_HID_12377, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 25772174336UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1475] = { - .class_hid = BNXT_ULP_CLASS_HID_17493, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 25773214720UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1476] = { - .class_hid = BNXT_ULP_CLASS_HID_16f53, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 25773222912UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1477] = { - .class_hid = BNXT_ULP_CLASS_HID_1045b, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 27917552640UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1478] = { - .class_hid = BNXT_ULP_CLASS_HID_1107b, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 27917560832UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1479] = { - .class_hid = BNXT_ULP_CLASS_HID_1404f, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 27918601216UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1480] = { - .class_hid = BNXT_ULP_CLASS_HID_15c6f, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 27918609408UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1481] = { - .class_hid = BNXT_ULP_CLASS_HID_1225f, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 27919649792UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1482] = { - .class_hid = BNXT_ULP_CLASS_HID_13e7f, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 27919657984UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1483] = { - .class_hid = BNXT_ULP_CLASS_HID_16e3b, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 27920698368UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1484] = { - .class_hid = BNXT_ULP_CLASS_HID_17a5b, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 27920706560UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1485] = { - .class_hid = BNXT_ULP_CLASS_HID_10f1f, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 30065036288UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1486] = { - .class_hid = BNXT_ULP_CLASS_HID_11b3f, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 30065044480UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1487] = { - .class_hid = BNXT_ULP_CLASS_HID_14bff, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 30066084864UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1488] = { - .class_hid = BNXT_ULP_CLASS_HID_147b7, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 30066093056UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1489] = { - .class_hid = BNXT_ULP_CLASS_HID_12d0f, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 30067133440UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1490] = { - .class_hid = BNXT_ULP_CLASS_HID_1392f, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 30067141632UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1491] = { - .class_hid = BNXT_ULP_CLASS_HID_169e7, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 30068182016UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1492] = { - .class_hid = BNXT_ULP_CLASS_HID_165a7, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 30068190208UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1493] = { - .class_hid = BNXT_ULP_CLASS_HID_11a0f, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 32212519936UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1494] = { - .class_hid = BNXT_ULP_CLASS_HID_116cf, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 32212528128UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1495] = { - .class_hid = BNXT_ULP_CLASS_HID_1468f, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 32213568512UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1496] = { - .class_hid = BNXT_ULP_CLASS_HID_152af, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 32213576704UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1497] = { - .class_hid = BNXT_ULP_CLASS_HID_138ff, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 32214617088UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1498] = { - .class_hid = BNXT_ULP_CLASS_HID_134bf, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 32214625280UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1499] = { - .class_hid = BNXT_ULP_CLASS_HID_1648f, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 32215665664UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1500] = { - .class_hid = BNXT_ULP_CLASS_HID_170af, - .class_tid = 2, - .hdr_sig_id = 26, - .flow_sig_id = 32215673856UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT } - }, - [1501] = { - .class_hid = BNXT_ULP_CLASS_HID_40c38, - .class_tid = 2, - .hdr_sig_id = 27, - .flow_sig_id = 66304UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_T_VXLAN_VNI } - }, - [1502] = { - .class_hid = BNXT_ULP_CLASS_HID_41c04, - .class_tid = 2, - .hdr_sig_id = 27, - .flow_sig_id = 68352UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_27_BITMASK_T_VXLAN_VNI } - }, - [1503] = { - .class_hid = BNXT_ULP_CLASS_HID_51c48, - .class_tid = 2, - .hdr_sig_id = 27, - .flow_sig_id = 328448UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_27_BITMASK_I_ETH_DMAC } - }, - [1504] = { - .class_hid = BNXT_ULP_CLASS_HID_50332, - .class_tid = 2, - .hdr_sig_id = 27, - .flow_sig_id = 330496UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_27_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_27_BITMASK_I_ETH_DMAC } - }, - [1505] = { - .class_hid = BNXT_ULP_CLASS_HID_48400, - .class_tid = 2, - .hdr_sig_id = 27, - .flow_sig_id = 590592UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_27_BITMASK_I_ETH_SMAC } - }, - [1506] = { - .class_hid = BNXT_ULP_CLASS_HID_48bea, - .class_tid = 2, - .hdr_sig_id = 27, - .flow_sig_id = 592640UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_27_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_27_BITMASK_I_ETH_SMAC } - }, - [1507] = { - .class_hid = BNXT_ULP_CLASS_HID_58b3e, - .class_tid = 2, - .hdr_sig_id = 27, - .flow_sig_id = 852736UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_27_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_27_BITMASK_I_ETH_SMAC } - }, - [1508] = { - .class_hid = BNXT_ULP_CLASS_HID_59b7a, - .class_tid = 2, - .hdr_sig_id = 27, - .flow_sig_id = 854784UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_27_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_27_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_27_BITMASK_I_ETH_SMAC } - }, - [1509] = { - .class_hid = BNXT_ULP_CLASS_HID_417dc, - .class_tid = 2, - .hdr_sig_id = 27, - .flow_sig_id = 536937216UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_27_BITMASK_I_IPV4_SRC_ADDR } - }, - [1510] = { - .class_hid = BNXT_ULP_CLASS_HID_40746, - .class_tid = 2, - .hdr_sig_id = 27, - .flow_sig_id = 536939264UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_27_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_27_BITMASK_I_IPV4_SRC_ADDR } - }, - [1511] = { - .class_hid = BNXT_ULP_CLASS_HID_5068a, - .class_tid = 2, - .hdr_sig_id = 27, - .flow_sig_id = 537199360UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_27_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_27_BITMASK_I_IPV4_SRC_ADDR } - }, - [1512] = { - .class_hid = BNXT_ULP_CLASS_HID_516d6, - .class_tid = 2, - .hdr_sig_id = 27, - .flow_sig_id = 537201408UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_27_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_27_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_27_BITMASK_I_IPV4_SRC_ADDR } - }, - [1513] = { - .class_hid = BNXT_ULP_CLASS_HID_48f42, - .class_tid = 2, - .hdr_sig_id = 27, - .flow_sig_id = 537461504UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_27_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_27_BITMASK_I_IPV4_SRC_ADDR } - }, - [1514] = { - .class_hid = BNXT_ULP_CLASS_HID_49e8e, - .class_tid = 2, - .hdr_sig_id = 27, - .flow_sig_id = 537463552UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_27_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_27_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_27_BITMASK_I_IPV4_SRC_ADDR } - }, - [1515] = { - .class_hid = BNXT_ULP_CLASS_HID_59ed2, - .class_tid = 2, - .hdr_sig_id = 27, - .flow_sig_id = 537723648UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_27_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_27_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_27_BITMASK_I_IPV4_SRC_ADDR } - }, - [1516] = { - .class_hid = BNXT_ULP_CLASS_HID_58d9c, - .class_tid = 2, - .hdr_sig_id = 27, - .flow_sig_id = 537725696UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_27_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_27_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_27_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_27_BITMASK_I_IPV4_SRC_ADDR } - }, - [1517] = { - .class_hid = BNXT_ULP_CLASS_HID_41a4a, - .class_tid = 2, - .hdr_sig_id = 27, - .flow_sig_id = 1073808128UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_27_BITMASK_I_IPV4_DST_ADDR } - }, - [1518] = { - .class_hid = BNXT_ULP_CLASS_HID_40924, - .class_tid = 2, - .hdr_sig_id = 27, - .flow_sig_id = 1073810176UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_27_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_27_BITMASK_I_IPV4_DST_ADDR } - }, - [1519] = { - .class_hid = BNXT_ULP_CLASS_HID_50968, - .class_tid = 2, - .hdr_sig_id = 27, - .flow_sig_id = 1074070272UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_27_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_27_BITMASK_I_IPV4_DST_ADDR } - }, - [1520] = { - .class_hid = BNXT_ULP_CLASS_HID_51944, - .class_tid = 2, - .hdr_sig_id = 27, - .flow_sig_id = 1074072320UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_27_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_27_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_27_BITMASK_I_IPV4_DST_ADDR } - }, - [1521] = { - .class_hid = BNXT_ULP_CLASS_HID_49182, - .class_tid = 2, - .hdr_sig_id = 27, - .flow_sig_id = 1074332416UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_27_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_27_BITMASK_I_IPV4_DST_ADDR } - }, - [1522] = { - .class_hid = BNXT_ULP_CLASS_HID_4816c, - .class_tid = 2, - .hdr_sig_id = 27, - .flow_sig_id = 1074334464UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_27_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_27_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_27_BITMASK_I_IPV4_DST_ADDR } - }, - [1523] = { - .class_hid = BNXT_ULP_CLASS_HID_58140, - .class_tid = 2, - .hdr_sig_id = 27, - .flow_sig_id = 1074594560UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_27_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_27_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_27_BITMASK_I_IPV4_DST_ADDR } - }, - [1524] = { - .class_hid = BNXT_ULP_CLASS_HID_5908c, - .class_tid = 2, - .hdr_sig_id = 27, - .flow_sig_id = 1074596608UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_27_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_27_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_27_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_27_BITMASK_I_IPV4_DST_ADDR } - }, - [1525] = { - .class_hid = BNXT_ULP_CLASS_HID_40c8c, - .class_tid = 2, - .hdr_sig_id = 27, - .flow_sig_id = 1610679040UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_27_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_I_IPV4_DST_ADDR } - }, - [1526] = { - .class_hid = BNXT_ULP_CLASS_HID_41cc8, - .class_tid = 2, - .hdr_sig_id = 27, - .flow_sig_id = 1610681088UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_27_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_27_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_I_IPV4_DST_ADDR } - }, - [1527] = { - .class_hid = BNXT_ULP_CLASS_HID_51c0c, - .class_tid = 2, - .hdr_sig_id = 27, - .flow_sig_id = 1610941184UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_27_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_27_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_I_IPV4_DST_ADDR } - }, - [1528] = { - .class_hid = BNXT_ULP_CLASS_HID_50386, - .class_tid = 2, - .hdr_sig_id = 27, - .flow_sig_id = 1610943232UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_27_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_27_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_27_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_I_IPV4_DST_ADDR } - }, - [1529] = { - .class_hid = BNXT_ULP_CLASS_HID_484c4, - .class_tid = 2, - .hdr_sig_id = 27, - .flow_sig_id = 1611203328UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_27_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_27_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_I_IPV4_DST_ADDR } - }, - [1530] = { - .class_hid = BNXT_ULP_CLASS_HID_48b8e, - .class_tid = 2, - .hdr_sig_id = 27, - .flow_sig_id = 1611205376UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_27_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_27_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_27_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_I_IPV4_DST_ADDR } - }, - [1531] = { - .class_hid = BNXT_ULP_CLASS_HID_58b82, - .class_tid = 2, - .hdr_sig_id = 27, - .flow_sig_id = 1611465472UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_27_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_27_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_27_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_I_IPV4_DST_ADDR } - }, - [1532] = { - .class_hid = BNXT_ULP_CLASS_HID_59bce, - .class_tid = 2, - .hdr_sig_id = 27, - .flow_sig_id = 1611467520UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_27_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_27_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_27_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_27_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_27_BITMASK_I_IPV4_DST_ADDR } - }, - [1533] = { - .class_hid = BNXT_ULP_CLASS_HID_10a54, - .class_tid = 2, - .hdr_sig_id = 28, - .flow_sig_id = 265216UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_T_VXLAN_VNI } - }, - [1534] = { - .class_hid = BNXT_ULP_CLASS_HID_11e74, - .class_tid = 2, - .hdr_sig_id = 28, - .flow_sig_id = 273408UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_28_BITMASK_T_VXLAN_VNI } - }, - [1535] = { - .class_hid = BNXT_ULP_CLASS_HID_14e48, - .class_tid = 2, - .hdr_sig_id = 28, - .flow_sig_id = 1313792UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_28_BITMASK_I_ETH_DMAC } - }, - [1536] = { - .class_hid = BNXT_ULP_CLASS_HID_15268, - .class_tid = 2, - .hdr_sig_id = 28, - .flow_sig_id = 1321984UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_28_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_28_BITMASK_I_ETH_DMAC } - }, - [1537] = { - .class_hid = BNXT_ULP_CLASS_HID_1285a, - .class_tid = 2, - .hdr_sig_id = 28, - .flow_sig_id = 2362368UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_28_BITMASK_I_ETH_SMAC } - }, - [1538] = { - .class_hid = BNXT_ULP_CLASS_HID_13c7a, - .class_tid = 2, - .hdr_sig_id = 28, - .flow_sig_id = 2370560UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_28_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_28_BITMASK_I_ETH_SMAC } - }, - [1539] = { - .class_hid = BNXT_ULP_CLASS_HID_163be, - .class_tid = 2, - .hdr_sig_id = 28, - .flow_sig_id = 3410944UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_28_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_28_BITMASK_I_ETH_SMAC } - }, - [1540] = { - .class_hid = BNXT_ULP_CLASS_HID_1705e, - .class_tid = 2, - .hdr_sig_id = 28, - .flow_sig_id = 3419136UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_28_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_28_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_28_BITMASK_I_ETH_SMAC } - }, - [1541] = { - .class_hid = BNXT_ULP_CLASS_HID_11d5e, - .class_tid = 2, - .hdr_sig_id = 28, - .flow_sig_id = 2147748864UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_28_BITMASK_I_IPV4_SRC_ADDR } - }, - [1542] = { - .class_hid = BNXT_ULP_CLASS_HID_1009c, - .class_tid = 2, - .hdr_sig_id = 28, - .flow_sig_id = 2147757056UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_28_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_28_BITMASK_I_IPV4_SRC_ADDR } - }, - [1543] = { - .class_hid = BNXT_ULP_CLASS_HID_150ba, - .class_tid = 2, - .hdr_sig_id = 28, - .flow_sig_id = 2148797440UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_28_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_28_BITMASK_I_IPV4_SRC_ADDR } - }, - [1544] = { - .class_hid = BNXT_ULP_CLASS_HID_144f8, - .class_tid = 2, - .hdr_sig_id = 28, - .flow_sig_id = 2148805632UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_28_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_28_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_28_BITMASK_I_IPV4_SRC_ADDR } - }, - [1545] = { - .class_hid = BNXT_ULP_CLASS_HID_1334c, - .class_tid = 2, - .hdr_sig_id = 28, - .flow_sig_id = 2149846016UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_28_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_28_BITMASK_I_IPV4_SRC_ADDR } - }, - [1546] = { - .class_hid = BNXT_ULP_CLASS_HID_1268a, - .class_tid = 2, - .hdr_sig_id = 28, - .flow_sig_id = 2149854208UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_28_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_28_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_28_BITMASK_I_IPV4_SRC_ADDR } - }, - [1547] = { - .class_hid = BNXT_ULP_CLASS_HID_176a8, - .class_tid = 2, - .hdr_sig_id = 28, - .flow_sig_id = 2150894592UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_28_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_28_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_28_BITMASK_I_IPV4_SRC_ADDR } - }, - [1548] = { - .class_hid = BNXT_ULP_CLASS_HID_17aee, - .class_tid = 2, - .hdr_sig_id = 28, - .flow_sig_id = 2150902784UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_28_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_28_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_28_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_28_BITMASK_I_IPV4_SRC_ADDR } - }, - [1549] = { - .class_hid = BNXT_ULP_CLASS_HID_11782, - .class_tid = 2, - .hdr_sig_id = 28, - .flow_sig_id = 4295232512UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_28_BITMASK_I_IPV4_DST_ADDR } - }, - [1550] = { - .class_hid = BNXT_ULP_CLASS_HID_11bc0, - .class_tid = 2, - .hdr_sig_id = 28, - .flow_sig_id = 4295240704UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_28_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_28_BITMASK_I_IPV4_DST_ADDR } - }, - [1551] = { - .class_hid = BNXT_ULP_CLASS_HID_14b00, - .class_tid = 2, - .hdr_sig_id = 28, - .flow_sig_id = 4296281088UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_28_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_28_BITMASK_I_IPV4_DST_ADDR } - }, - [1552] = { - .class_hid = BNXT_ULP_CLASS_HID_15f20, - .class_tid = 2, - .hdr_sig_id = 28, - .flow_sig_id = 4296289280UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_28_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_28_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_28_BITMASK_I_IPV4_DST_ADDR } - }, - [1553] = { - .class_hid = BNXT_ULP_CLASS_HID_135f0, - .class_tid = 2, - .hdr_sig_id = 28, - .flow_sig_id = 4297329664UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_28_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_28_BITMASK_I_IPV4_DST_ADDR } - }, - [1554] = { - .class_hid = BNXT_ULP_CLASS_HID_13932, - .class_tid = 2, - .hdr_sig_id = 28, - .flow_sig_id = 4297337856UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_28_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_28_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_28_BITMASK_I_IPV4_DST_ADDR } - }, - [1555] = { - .class_hid = BNXT_ULP_CLASS_HID_1690a, - .class_tid = 2, - .hdr_sig_id = 28, - .flow_sig_id = 4298378240UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_28_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_28_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_28_BITMASK_I_IPV4_DST_ADDR } - }, - [1556] = { - .class_hid = BNXT_ULP_CLASS_HID_17d2a, - .class_tid = 2, - .hdr_sig_id = 28, - .flow_sig_id = 4298386432UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_28_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_28_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_28_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_28_BITMASK_I_IPV4_DST_ADDR } - }, - [1557] = { - .class_hid = BNXT_ULP_CLASS_HID_11a2a, - .class_tid = 2, - .hdr_sig_id = 28, - .flow_sig_id = 6442716160UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_28_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_I_IPV4_DST_ADDR } - }, - [1558] = { - .class_hid = BNXT_ULP_CLASS_HID_10e68, - .class_tid = 2, - .hdr_sig_id = 28, - .flow_sig_id = 6442724352UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_28_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_28_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_I_IPV4_DST_ADDR } - }, - [1559] = { - .class_hid = BNXT_ULP_CLASS_HID_15e0a, - .class_tid = 2, - .hdr_sig_id = 28, - .flow_sig_id = 6443764736UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_28_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_28_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_I_IPV4_DST_ADDR } - }, - [1560] = { - .class_hid = BNXT_ULP_CLASS_HID_14248, - .class_tid = 2, - .hdr_sig_id = 28, - .flow_sig_id = 6443772928UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_28_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_28_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_28_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_I_IPV4_DST_ADDR } - }, - [1561] = { - .class_hid = BNXT_ULP_CLASS_HID_13818, - .class_tid = 2, - .hdr_sig_id = 28, - .flow_sig_id = 6444813312UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_28_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_28_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_I_IPV4_DST_ADDR } - }, - [1562] = { - .class_hid = BNXT_ULP_CLASS_HID_12c5a, - .class_tid = 2, - .hdr_sig_id = 28, - .flow_sig_id = 6444821504UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_28_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_28_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_28_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_I_IPV4_DST_ADDR } - }, - [1563] = { - .class_hid = BNXT_ULP_CLASS_HID_17c78, - .class_tid = 2, - .hdr_sig_id = 28, - .flow_sig_id = 6445861888UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_28_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_28_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_28_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_I_IPV4_DST_ADDR } - }, - [1564] = { - .class_hid = BNXT_ULP_CLASS_HID_167ba, - .class_tid = 2, - .hdr_sig_id = 28, - .flow_sig_id = 6445870080UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_ICMP | - BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .field_sig = { .bits = - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_O_UDP_DST_PORT | - BNXT_ULP_HF_0_2_28_BITMASK_T_VXLAN_VNI | - BNXT_ULP_HF_0_2_28_BITMASK_I_ETH_DMAC | - BNXT_ULP_HF_0_2_28_BITMASK_I_ETH_SMAC | - BNXT_ULP_HF_0_2_28_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_28_BITMASK_I_IPV4_DST_ADDR } - }, - [1565] = { - .class_hid = BNXT_ULP_CLASS_HID_1f91, - .class_tid = 3, - .hdr_sig_id = 29, - .flow_sig_id = 4096UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_29_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_29_BITMASK_O_IPV6_DST_ADDR } - }, - [1566] = { - .class_hid = BNXT_ULP_CLASS_HID_0763, - .class_tid = 3, - .hdr_sig_id = 29, - .flow_sig_id = 4100UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_29_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_29_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_29_BITMASK_O_IPV6_DST_ADDR } - }, - [1567] = { - .class_hid = BNXT_ULP_CLASS_HID_0f7b, - .class_tid = 3, - .hdr_sig_id = 29, - .flow_sig_id = 6144UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_29_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_29_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_29_BITMASK_O_IPV6_DST_ADDR } - }, - [1568] = { - .class_hid = BNXT_ULP_CLASS_HID_16af, - .class_tid = 3, - .hdr_sig_id = 29, - .flow_sig_id = 6148UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_29_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_29_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_29_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_29_BITMASK_O_IPV6_DST_ADDR } - }, - [1569] = { - .class_hid = BNXT_ULP_CLASS_HID_1daf, - .class_tid = 3, - .hdr_sig_id = 30, - .flow_sig_id = 16384UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_30_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_30_BITMASK_O_IPV4_DST_ADDR } - }, - [1570] = { - .class_hid = BNXT_ULP_CLASS_HID_0539, - .class_tid = 3, - .hdr_sig_id = 30, - .flow_sig_id = 16388UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_30_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_30_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_30_BITMASK_O_IPV4_DST_ADDR } - }, - [1571] = { - .class_hid = BNXT_ULP_CLASS_HID_01ed, - .class_tid = 3, - .hdr_sig_id = 30, - .flow_sig_id = 24576UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_30_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_30_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_30_BITMASK_O_IPV4_DST_ADDR } - }, - [1572] = { - .class_hid = BNXT_ULP_CLASS_HID_097f, - .class_tid = 3, - .hdr_sig_id = 30, - .flow_sig_id = 24580UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_30_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_30_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_30_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_30_BITMASK_O_IPV4_DST_ADDR } - }, - [1573] = { - .class_hid = BNXT_ULP_CLASS_HID_81ab8, - .class_tid = 3, - .hdr_sig_id = 31, - .flow_sig_id = 32768UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_31_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_31_BITMASK_O_IPV6_DST_ADDR } - }, - [1574] = { - .class_hid = BNXT_ULP_CLASS_HID_8020e, - .class_tid = 3, - .hdr_sig_id = 31, - .flow_sig_id = 32772UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_31_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_31_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_31_BITMASK_O_IPV6_DST_ADDR } - }, - [1575] = { - .class_hid = BNXT_ULP_CLASS_HID_815d8, - .class_tid = 3, - .hdr_sig_id = 31, - .flow_sig_id = 32832UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_31_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_31_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_31_BITMASK_O_IPV6_DST_ADDR } - }, - [1576] = { - .class_hid = BNXT_ULP_CLASS_HID_81cae, - .class_tid = 3, - .hdr_sig_id = 31, - .flow_sig_id = 32836UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_31_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_31_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_31_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_31_BITMASK_O_IPV6_DST_ADDR } - }, - [1577] = { - .class_hid = BNXT_ULP_CLASS_HID_810a8, - .class_tid = 3, - .hdr_sig_id = 31, - .flow_sig_id = 49152UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_31_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_31_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_31_BITMASK_O_IPV6_DST_ADDR } - }, - [1578] = { - .class_hid = BNXT_ULP_CLASS_HID_8183e, - .class_tid = 3, - .hdr_sig_id = 31, - .flow_sig_id = 49156UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_31_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_31_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_31_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_31_BITMASK_O_IPV6_DST_ADDR } - }, - [1579] = { - .class_hid = BNXT_ULP_CLASS_HID_8036a, - .class_tid = 3, - .hdr_sig_id = 31, - .flow_sig_id = 49216UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_31_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_31_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_31_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_31_BITMASK_O_IPV6_DST_ADDR } - }, - [1580] = { - .class_hid = BNXT_ULP_CLASS_HID_80af8, - .class_tid = 3, - .hdr_sig_id = 31, - .flow_sig_id = 49220UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_31_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_31_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_31_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_31_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_31_BITMASK_O_IPV6_DST_ADDR } - }, - [1581] = { - .class_hid = BNXT_ULP_CLASS_HID_206fe, - .class_tid = 3, - .hdr_sig_id = 32, - .flow_sig_id = 131072UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_32_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_32_BITMASK_O_IPV4_DST_ADDR } - }, - [1582] = { - .class_hid = BNXT_ULP_CLASS_HID_20e4c, - .class_tid = 3, - .hdr_sig_id = 32, - .flow_sig_id = 131076UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_32_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_32_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_32_BITMASK_O_IPV4_DST_ADDR } - }, - [1583] = { - .class_hid = BNXT_ULP_CLASS_HID_2111e, - .class_tid = 3, - .hdr_sig_id = 32, - .flow_sig_id = 131136UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_32_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_32_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_32_BITMASK_O_IPV4_DST_ADDR } - }, - [1584] = { - .class_hid = BNXT_ULP_CLASS_HID_218ec, - .class_tid = 3, - .hdr_sig_id = 32, - .flow_sig_id = 131140UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_32_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_32_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_32_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_32_BITMASK_O_IPV4_DST_ADDR } - }, - [1585] = { - .class_hid = BNXT_ULP_CLASS_HID_60472, - .class_tid = 3, - .hdr_sig_id = 32, - .flow_sig_id = 196608UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_32_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_32_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_32_BITMASK_O_IPV4_DST_ADDR } - }, - [1586] = { - .class_hid = BNXT_ULP_CLASS_HID_603c0, - .class_tid = 3, - .hdr_sig_id = 32, - .flow_sig_id = 196612UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_32_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_32_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_32_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_32_BITMASK_O_IPV4_DST_ADDR } - }, - [1587] = { - .class_hid = BNXT_ULP_CLASS_HID_61692, - .class_tid = 3, - .hdr_sig_id = 32, - .flow_sig_id = 196672UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_32_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_32_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_32_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_32_BITMASK_O_IPV4_DST_ADDR } - }, - [1588] = { - .class_hid = BNXT_ULP_CLASS_HID_61e60, - .class_tid = 3, - .hdr_sig_id = 32, - .flow_sig_id = 196676UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_32_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_32_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_32_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_32_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_32_BITMASK_O_IPV4_DST_ADDR } - }, - [1589] = { - .class_hid = BNXT_ULP_CLASS_HID_1f81, - .class_tid = 3, - .hdr_sig_id = 33, - .flow_sig_id = 4096UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_33_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_33_BITMASK_O_IPV6_DST_ADDR } - }, - [1590] = { - .class_hid = BNXT_ULP_CLASS_HID_0773, - .class_tid = 3, - .hdr_sig_id = 33, - .flow_sig_id = 4100UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_33_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_33_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_33_BITMASK_O_IPV6_DST_ADDR } - }, - [1591] = { - .class_hid = BNXT_ULP_CLASS_HID_0f6b, - .class_tid = 3, - .hdr_sig_id = 33, - .flow_sig_id = 6144UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_33_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_33_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_33_BITMASK_O_IPV6_DST_ADDR } - }, - [1592] = { - .class_hid = BNXT_ULP_CLASS_HID_16bf, - .class_tid = 3, - .hdr_sig_id = 33, - .flow_sig_id = 6148UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_33_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_33_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_33_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_33_BITMASK_O_IPV6_DST_ADDR } - }, - [1593] = { - .class_hid = BNXT_ULP_CLASS_HID_03cf, - .class_tid = 3, - .hdr_sig_id = 33, - .flow_sig_id = 12288UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_33_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_33_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_33_BITMASK_O_TCP_SRC_PORT } - }, - [1594] = { - .class_hid = BNXT_ULP_CLASS_HID_0ab1, - .class_tid = 3, - .hdr_sig_id = 33, - .flow_sig_id = 12292UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_33_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_33_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_33_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_33_BITMASK_O_TCP_SRC_PORT } - }, - [1595] = { - .class_hid = BNXT_ULP_CLASS_HID_130b, - .class_tid = 3, - .hdr_sig_id = 33, - .flow_sig_id = 14336UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_33_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_33_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_33_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_33_BITMASK_O_TCP_SRC_PORT } - }, - [1596] = { - .class_hid = BNXT_ULP_CLASS_HID_1afd, - .class_tid = 3, - .hdr_sig_id = 33, - .flow_sig_id = 14340UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_33_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_33_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_33_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_33_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_33_BITMASK_O_TCP_SRC_PORT } - }, - [1597] = { - .class_hid = BNXT_ULP_CLASS_HID_1591, - .class_tid = 3, - .hdr_sig_id = 33, - .flow_sig_id = 20480UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_33_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_33_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_33_BITMASK_O_TCP_DST_PORT } - }, - [1598] = { - .class_hid = BNXT_ULP_CLASS_HID_1d03, - .class_tid = 3, - .hdr_sig_id = 33, - .flow_sig_id = 20484UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_33_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_33_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_33_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_33_BITMASK_O_TCP_DST_PORT } - }, - [1599] = { - .class_hid = BNXT_ULP_CLASS_HID_057b, - .class_tid = 3, - .hdr_sig_id = 33, - .flow_sig_id = 22528UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_33_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_33_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_33_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_33_BITMASK_O_TCP_DST_PORT } - }, - [1600] = { - .class_hid = BNXT_ULP_CLASS_HID_0ced, - .class_tid = 3, - .hdr_sig_id = 33, - .flow_sig_id = 22532UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_33_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_33_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_33_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_33_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_33_BITMASK_O_TCP_DST_PORT } - }, - [1601] = { - .class_hid = BNXT_ULP_CLASS_HID_19df, - .class_tid = 3, - .hdr_sig_id = 33, - .flow_sig_id = 28672UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_33_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_33_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_33_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_3_33_BITMASK_O_TCP_DST_PORT } - }, - [1602] = { - .class_hid = BNXT_ULP_CLASS_HID_0141, - .class_tid = 3, - .hdr_sig_id = 33, - .flow_sig_id = 28676UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_33_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_33_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_33_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_33_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_3_33_BITMASK_O_TCP_DST_PORT } - }, - [1603] = { - .class_hid = BNXT_ULP_CLASS_HID_08b9, - .class_tid = 3, - .hdr_sig_id = 33, - .flow_sig_id = 30720UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_33_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_33_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_33_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_33_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_3_33_BITMASK_O_TCP_DST_PORT } - }, - [1604] = { - .class_hid = BNXT_ULP_CLASS_HID_108d, - .class_tid = 3, - .hdr_sig_id = 33, - .flow_sig_id = 30724UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_33_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_33_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_33_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_33_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_33_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_3_33_BITMASK_O_TCP_DST_PORT } - }, - [1605] = { - .class_hid = BNXT_ULP_CLASS_HID_1dbf, - .class_tid = 3, - .hdr_sig_id = 34, - .flow_sig_id = 16384UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_34_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_34_BITMASK_O_IPV4_DST_ADDR } - }, - [1606] = { - .class_hid = BNXT_ULP_CLASS_HID_0529, - .class_tid = 3, - .hdr_sig_id = 34, - .flow_sig_id = 16388UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_34_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_34_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_34_BITMASK_O_IPV4_DST_ADDR } - }, - [1607] = { - .class_hid = BNXT_ULP_CLASS_HID_01fd, - .class_tid = 3, - .hdr_sig_id = 34, - .flow_sig_id = 24576UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_34_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_34_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_34_BITMASK_O_IPV4_DST_ADDR } - }, - [1608] = { - .class_hid = BNXT_ULP_CLASS_HID_096f, - .class_tid = 3, - .hdr_sig_id = 34, - .flow_sig_id = 24580UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_34_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_34_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_34_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_34_BITMASK_O_IPV4_DST_ADDR } - }, - [1609] = { - .class_hid = BNXT_ULP_CLASS_HID_810b7, - .class_tid = 3, - .hdr_sig_id = 34, - .flow_sig_id = 49152UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_34_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_34_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_34_BITMASK_O_TCP_SRC_PORT } - }, - [1610] = { - .class_hid = BNXT_ULP_CLASS_HID_81821, - .class_tid = 3, - .hdr_sig_id = 34, - .flow_sig_id = 49156UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_34_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_34_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_34_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_34_BITMASK_O_TCP_SRC_PORT } - }, - [1611] = { - .class_hid = BNXT_ULP_CLASS_HID_804f5, - .class_tid = 3, - .hdr_sig_id = 34, - .flow_sig_id = 57344UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_34_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_34_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_34_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_34_BITMASK_O_TCP_SRC_PORT } - }, - [1612] = { - .class_hid = BNXT_ULP_CLASS_HID_80c67, - .class_tid = 3, - .hdr_sig_id = 34, - .flow_sig_id = 57348UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_34_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_34_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_34_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_34_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_34_BITMASK_O_TCP_SRC_PORT } - }, - [1613] = { - .class_hid = BNXT_ULP_CLASS_HID_41333, - .class_tid = 3, - .hdr_sig_id = 34, - .flow_sig_id = 81920UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_34_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_34_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_34_BITMASK_O_TCP_DST_PORT } - }, - [1614] = { - .class_hid = BNXT_ULP_CLASS_HID_41aad, - .class_tid = 3, - .hdr_sig_id = 34, - .flow_sig_id = 81924UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_34_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_34_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_34_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_34_BITMASK_O_TCP_DST_PORT } - }, - [1615] = { - .class_hid = BNXT_ULP_CLASS_HID_40771, - .class_tid = 3, - .hdr_sig_id = 34, - .flow_sig_id = 90112UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_34_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_34_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_34_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_34_BITMASK_O_TCP_DST_PORT } - }, - [1616] = { - .class_hid = BNXT_ULP_CLASS_HID_40ee3, - .class_tid = 3, - .hdr_sig_id = 34, - .flow_sig_id = 90116UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_34_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_34_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_34_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_34_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_34_BITMASK_O_TCP_DST_PORT } - }, - [1617] = { - .class_hid = BNXT_ULP_CLASS_HID_c16cb, - .class_tid = 3, - .hdr_sig_id = 34, - .flow_sig_id = 114688UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_34_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_34_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_34_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_3_34_BITMASK_O_TCP_DST_PORT } - }, - [1618] = { - .class_hid = BNXT_ULP_CLASS_HID_c1da5, - .class_tid = 3, - .hdr_sig_id = 34, - .flow_sig_id = 114692UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_34_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_34_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_34_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_34_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_3_34_BITMASK_O_TCP_DST_PORT } - }, - [1619] = { - .class_hid = BNXT_ULP_CLASS_HID_c1a09, - .class_tid = 3, - .hdr_sig_id = 34, - .flow_sig_id = 122880UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_34_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_34_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_34_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_34_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_3_34_BITMASK_O_TCP_DST_PORT } - }, - [1620] = { - .class_hid = BNXT_ULP_CLASS_HID_c01fb, - .class_tid = 3, - .hdr_sig_id = 34, - .flow_sig_id = 122884UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_34_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_34_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_34_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_34_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_34_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_3_34_BITMASK_O_TCP_DST_PORT } - }, - [1621] = { - .class_hid = BNXT_ULP_CLASS_HID_1ff1, - .class_tid = 3, - .hdr_sig_id = 35, - .flow_sig_id = 4096UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_35_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_35_BITMASK_O_IPV6_DST_ADDR } - }, - [1622] = { - .class_hid = BNXT_ULP_CLASS_HID_0703, - .class_tid = 3, - .hdr_sig_id = 35, - .flow_sig_id = 4100UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_35_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_35_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_35_BITMASK_O_IPV6_DST_ADDR } - }, - [1623] = { - .class_hid = BNXT_ULP_CLASS_HID_0f1b, - .class_tid = 3, - .hdr_sig_id = 35, - .flow_sig_id = 6144UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_35_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_35_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_35_BITMASK_O_IPV6_DST_ADDR } - }, - [1624] = { - .class_hid = BNXT_ULP_CLASS_HID_16cf, - .class_tid = 3, - .hdr_sig_id = 35, - .flow_sig_id = 6148UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_35_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_35_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_35_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_35_BITMASK_O_IPV6_DST_ADDR } - }, - [1625] = { - .class_hid = BNXT_ULP_CLASS_HID_03bf, - .class_tid = 3, - .hdr_sig_id = 35, - .flow_sig_id = 12288UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_35_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_35_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_35_BITMASK_O_UDP_SRC_PORT } - }, - [1626] = { - .class_hid = BNXT_ULP_CLASS_HID_0ac1, - .class_tid = 3, - .hdr_sig_id = 35, - .flow_sig_id = 12292UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_35_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_35_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_35_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_35_BITMASK_O_UDP_SRC_PORT } - }, - [1627] = { - .class_hid = BNXT_ULP_CLASS_HID_137b, - .class_tid = 3, - .hdr_sig_id = 35, - .flow_sig_id = 14336UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_35_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_35_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_35_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_35_BITMASK_O_UDP_SRC_PORT } - }, - [1628] = { - .class_hid = BNXT_ULP_CLASS_HID_1a8d, - .class_tid = 3, - .hdr_sig_id = 35, - .flow_sig_id = 14340UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_35_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_35_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_35_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_35_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_35_BITMASK_O_UDP_SRC_PORT } - }, - [1629] = { - .class_hid = BNXT_ULP_CLASS_HID_15e1, - .class_tid = 3, - .hdr_sig_id = 35, - .flow_sig_id = 20480UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_35_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_35_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_35_BITMASK_O_UDP_DST_PORT } - }, - [1630] = { - .class_hid = BNXT_ULP_CLASS_HID_1d73, - .class_tid = 3, - .hdr_sig_id = 35, - .flow_sig_id = 20484UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_35_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_35_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_35_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_35_BITMASK_O_UDP_DST_PORT } - }, - [1631] = { - .class_hid = BNXT_ULP_CLASS_HID_050b, - .class_tid = 3, - .hdr_sig_id = 35, - .flow_sig_id = 22528UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_35_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_35_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_35_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_35_BITMASK_O_UDP_DST_PORT } - }, - [1632] = { - .class_hid = BNXT_ULP_CLASS_HID_0c9d, - .class_tid = 3, - .hdr_sig_id = 35, - .flow_sig_id = 22532UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_35_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_35_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_35_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_35_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_35_BITMASK_O_UDP_DST_PORT } - }, - [1633] = { - .class_hid = BNXT_ULP_CLASS_HID_19af, - .class_tid = 3, - .hdr_sig_id = 35, - .flow_sig_id = 28672UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_35_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_35_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_35_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_3_35_BITMASK_O_UDP_DST_PORT } - }, - [1634] = { - .class_hid = BNXT_ULP_CLASS_HID_0131, - .class_tid = 3, - .hdr_sig_id = 35, - .flow_sig_id = 28676UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_35_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_35_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_35_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_35_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_3_35_BITMASK_O_UDP_DST_PORT } - }, - [1635] = { - .class_hid = BNXT_ULP_CLASS_HID_08c9, - .class_tid = 3, - .hdr_sig_id = 35, - .flow_sig_id = 30720UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_35_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_35_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_35_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_35_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_3_35_BITMASK_O_UDP_DST_PORT } - }, - [1636] = { - .class_hid = BNXT_ULP_CLASS_HID_10fd, - .class_tid = 3, - .hdr_sig_id = 35, - .flow_sig_id = 30724UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_35_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_35_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_35_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_35_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_35_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_3_35_BITMASK_O_UDP_DST_PORT } - }, - [1637] = { - .class_hid = BNXT_ULP_CLASS_HID_1dcf, - .class_tid = 3, - .hdr_sig_id = 36, - .flow_sig_id = 16384UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_36_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_36_BITMASK_O_IPV4_DST_ADDR } - }, - [1638] = { - .class_hid = BNXT_ULP_CLASS_HID_0559, - .class_tid = 3, - .hdr_sig_id = 36, - .flow_sig_id = 16388UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_36_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_36_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_36_BITMASK_O_IPV4_DST_ADDR } - }, - [1639] = { - .class_hid = BNXT_ULP_CLASS_HID_018d, - .class_tid = 3, - .hdr_sig_id = 36, - .flow_sig_id = 24576UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_36_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_36_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_36_BITMASK_O_IPV4_DST_ADDR } - }, - [1640] = { - .class_hid = BNXT_ULP_CLASS_HID_091f, - .class_tid = 3, - .hdr_sig_id = 36, - .flow_sig_id = 24580UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_36_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_36_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_36_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_36_BITMASK_O_IPV4_DST_ADDR } - }, - [1641] = { - .class_hid = BNXT_ULP_CLASS_HID_810c7, - .class_tid = 3, - .hdr_sig_id = 36, - .flow_sig_id = 49152UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_36_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_36_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_36_BITMASK_O_UDP_SRC_PORT } - }, - [1642] = { - .class_hid = BNXT_ULP_CLASS_HID_81851, - .class_tid = 3, - .hdr_sig_id = 36, - .flow_sig_id = 49156UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_36_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_36_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_36_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_36_BITMASK_O_UDP_SRC_PORT } - }, - [1643] = { - .class_hid = BNXT_ULP_CLASS_HID_80485, - .class_tid = 3, - .hdr_sig_id = 36, - .flow_sig_id = 57344UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_36_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_36_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_36_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_36_BITMASK_O_UDP_SRC_PORT } - }, - [1644] = { - .class_hid = BNXT_ULP_CLASS_HID_80c17, - .class_tid = 3, - .hdr_sig_id = 36, - .flow_sig_id = 57348UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_36_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_36_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_36_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_36_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_36_BITMASK_O_UDP_SRC_PORT } - }, - [1645] = { - .class_hid = BNXT_ULP_CLASS_HID_41343, - .class_tid = 3, - .hdr_sig_id = 36, - .flow_sig_id = 81920UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_36_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_36_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_36_BITMASK_O_UDP_DST_PORT } - }, - [1646] = { - .class_hid = BNXT_ULP_CLASS_HID_41add, - .class_tid = 3, - .hdr_sig_id = 36, - .flow_sig_id = 81924UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_36_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_36_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_36_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_36_BITMASK_O_UDP_DST_PORT } - }, - [1647] = { - .class_hid = BNXT_ULP_CLASS_HID_40701, - .class_tid = 3, - .hdr_sig_id = 36, - .flow_sig_id = 90112UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_36_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_36_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_36_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_36_BITMASK_O_UDP_DST_PORT } - }, - [1648] = { - .class_hid = BNXT_ULP_CLASS_HID_40e93, - .class_tid = 3, - .hdr_sig_id = 36, - .flow_sig_id = 90116UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_36_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_36_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_36_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_36_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_36_BITMASK_O_UDP_DST_PORT } - }, - [1649] = { - .class_hid = BNXT_ULP_CLASS_HID_c16bb, - .class_tid = 3, - .hdr_sig_id = 36, - .flow_sig_id = 114688UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_36_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_36_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_36_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_3_36_BITMASK_O_UDP_DST_PORT } - }, - [1650] = { - .class_hid = BNXT_ULP_CLASS_HID_c1dd5, - .class_tid = 3, - .hdr_sig_id = 36, - .flow_sig_id = 114692UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_36_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_36_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_36_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_36_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_3_36_BITMASK_O_UDP_DST_PORT } - }, - [1651] = { - .class_hid = BNXT_ULP_CLASS_HID_c1a79, - .class_tid = 3, - .hdr_sig_id = 36, - .flow_sig_id = 122880UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_36_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_36_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_36_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_36_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_3_36_BITMASK_O_UDP_DST_PORT } - }, - [1652] = { - .class_hid = BNXT_ULP_CLASS_HID_c018b, - .class_tid = 3, - .hdr_sig_id = 36, - .flow_sig_id = 122884UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_36_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_36_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_36_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_36_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_36_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_3_36_BITMASK_O_UDP_DST_PORT } - }, - [1653] = { - .class_hid = BNXT_ULP_CLASS_HID_81aa8, - .class_tid = 3, - .hdr_sig_id = 37, - .flow_sig_id = 32768UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_37_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_DST_ADDR } - }, - [1654] = { - .class_hid = BNXT_ULP_CLASS_HID_8021e, - .class_tid = 3, - .hdr_sig_id = 37, - .flow_sig_id = 32772UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_37_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_37_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_DST_ADDR } - }, - [1655] = { - .class_hid = BNXT_ULP_CLASS_HID_815c8, - .class_tid = 3, - .hdr_sig_id = 37, - .flow_sig_id = 32832UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_37_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_37_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_DST_ADDR } - }, - [1656] = { - .class_hid = BNXT_ULP_CLASS_HID_81cbe, - .class_tid = 3, - .hdr_sig_id = 37, - .flow_sig_id = 32836UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_37_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_37_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_37_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_DST_ADDR } - }, - [1657] = { - .class_hid = BNXT_ULP_CLASS_HID_810b8, - .class_tid = 3, - .hdr_sig_id = 37, - .flow_sig_id = 49152UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_37_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_DST_ADDR } - }, - [1658] = { - .class_hid = BNXT_ULP_CLASS_HID_8182e, - .class_tid = 3, - .hdr_sig_id = 37, - .flow_sig_id = 49156UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_37_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_37_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_DST_ADDR } - }, - [1659] = { - .class_hid = BNXT_ULP_CLASS_HID_8037a, - .class_tid = 3, - .hdr_sig_id = 37, - .flow_sig_id = 49216UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_37_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_37_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_DST_ADDR } - }, - [1660] = { - .class_hid = BNXT_ULP_CLASS_HID_80ae8, - .class_tid = 3, - .hdr_sig_id = 37, - .flow_sig_id = 49220UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_37_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_37_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_37_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_DST_ADDR } - }, - [1661] = { - .class_hid = BNXT_ULP_CLASS_HID_c1834, - .class_tid = 3, - .hdr_sig_id = 37, - .flow_sig_id = 98304UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_37_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_37_BITMASK_O_TCP_SRC_PORT } - }, - [1662] = { - .class_hid = BNXT_ULP_CLASS_HID_c079a, - .class_tid = 3, - .hdr_sig_id = 37, - .flow_sig_id = 98308UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_37_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_37_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_37_BITMASK_O_TCP_SRC_PORT } - }, - [1663] = { - .class_hid = BNXT_ULP_CLASS_HID_c0af6, - .class_tid = 3, - .hdr_sig_id = 37, - .flow_sig_id = 98368UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_37_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_37_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_37_BITMASK_O_TCP_SRC_PORT } - }, - [1664] = { - .class_hid = BNXT_ULP_CLASS_HID_c123a, - .class_tid = 3, - .hdr_sig_id = 37, - .flow_sig_id = 98372UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_37_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_37_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_37_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_37_BITMASK_O_TCP_SRC_PORT } - }, - [1665] = { - .class_hid = BNXT_ULP_CLASS_HID_c16c4, - .class_tid = 3, - .hdr_sig_id = 37, - .flow_sig_id = 114688UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_37_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_37_BITMASK_O_TCP_SRC_PORT } - }, - [1666] = { - .class_hid = BNXT_ULP_CLASS_HID_c1daa, - .class_tid = 3, - .hdr_sig_id = 37, - .flow_sig_id = 114692UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_37_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_37_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_37_BITMASK_O_TCP_SRC_PORT } - }, - [1667] = { - .class_hid = BNXT_ULP_CLASS_HID_c0086, - .class_tid = 3, - .hdr_sig_id = 37, - .flow_sig_id = 114752UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_37_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_37_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_37_BITMASK_O_TCP_SRC_PORT } - }, - [1668] = { - .class_hid = BNXT_ULP_CLASS_HID_c0874, - .class_tid = 3, - .hdr_sig_id = 37, - .flow_sig_id = 114756UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_37_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_37_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_37_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_37_BITMASK_O_TCP_SRC_PORT } - }, - [1669] = { - .class_hid = BNXT_ULP_CLASS_HID_a19ea, - .class_tid = 3, - .hdr_sig_id = 37, - .flow_sig_id = 163840UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_37_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_37_BITMASK_O_TCP_DST_PORT } - }, - [1670] = { - .class_hid = BNXT_ULP_CLASS_HID_a0158, - .class_tid = 3, - .hdr_sig_id = 37, - .flow_sig_id = 163844UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_37_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_37_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_37_BITMASK_O_TCP_DST_PORT } - }, - [1671] = { - .class_hid = BNXT_ULP_CLASS_HID_a0bb4, - .class_tid = 3, - .hdr_sig_id = 37, - .flow_sig_id = 163904UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_37_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_37_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_37_BITMASK_O_TCP_DST_PORT } - }, - [1672] = { - .class_hid = BNXT_ULP_CLASS_HID_a13f8, - .class_tid = 3, - .hdr_sig_id = 37, - .flow_sig_id = 163908UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_37_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_37_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_37_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_37_BITMASK_O_TCP_DST_PORT } - }, - [1673] = { - .class_hid = BNXT_ULP_CLASS_HID_a17fa, - .class_tid = 3, - .hdr_sig_id = 37, - .flow_sig_id = 180224UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_37_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_37_BITMASK_O_TCP_DST_PORT } - }, - [1674] = { - .class_hid = BNXT_ULP_CLASS_HID_a1f68, - .class_tid = 3, - .hdr_sig_id = 37, - .flow_sig_id = 180228UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_37_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_37_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_37_BITMASK_O_TCP_DST_PORT } - }, - [1675] = { - .class_hid = BNXT_ULP_CLASS_HID_a0244, - .class_tid = 3, - .hdr_sig_id = 37, - .flow_sig_id = 180288UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_37_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_37_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_37_BITMASK_O_TCP_DST_PORT } - }, - [1676] = { - .class_hid = BNXT_ULP_CLASS_HID_a092a, - .class_tid = 3, - .hdr_sig_id = 37, - .flow_sig_id = 180292UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_37_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_37_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_37_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_37_BITMASK_O_TCP_DST_PORT } - }, - [1677] = { - .class_hid = BNXT_ULP_CLASS_HID_e1f76, - .class_tid = 3, - .hdr_sig_id = 37, - .flow_sig_id = 229376UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_37_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_37_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_3_37_BITMASK_O_TCP_DST_PORT } - }, - [1678] = { - .class_hid = BNXT_ULP_CLASS_HID_e06e4, - .class_tid = 3, - .hdr_sig_id = 37, - .flow_sig_id = 229380UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_37_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_37_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_37_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_3_37_BITMASK_O_TCP_DST_PORT } - }, - [1679] = { - .class_hid = BNXT_ULP_CLASS_HID_e0930, - .class_tid = 3, - .hdr_sig_id = 37, - .flow_sig_id = 229440UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_37_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_37_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_37_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_3_37_BITMASK_O_TCP_DST_PORT } - }, - [1680] = { - .class_hid = BNXT_ULP_CLASS_HID_e1104, - .class_tid = 3, - .hdr_sig_id = 37, - .flow_sig_id = 229444UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_37_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_37_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_37_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_37_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_3_37_BITMASK_O_TCP_DST_PORT } - }, - [1681] = { - .class_hid = BNXT_ULP_CLASS_HID_e1506, - .class_tid = 3, - .hdr_sig_id = 37, - .flow_sig_id = 245760UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_37_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_37_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_3_37_BITMASK_O_TCP_DST_PORT } - }, - [1682] = { - .class_hid = BNXT_ULP_CLASS_HID_e1cf4, - .class_tid = 3, - .hdr_sig_id = 37, - .flow_sig_id = 245764UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_37_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_37_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_37_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_3_37_BITMASK_O_TCP_DST_PORT } - }, - [1683] = { - .class_hid = BNXT_ULP_CLASS_HID_e07c0, - .class_tid = 3, - .hdr_sig_id = 37, - .flow_sig_id = 245824UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_37_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_37_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_37_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_3_37_BITMASK_O_TCP_DST_PORT } - }, - [1684] = { - .class_hid = BNXT_ULP_CLASS_HID_e0eb6, - .class_tid = 3, - .hdr_sig_id = 37, - .flow_sig_id = 245828UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_37_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_37_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_37_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_37_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_3_37_BITMASK_O_TCP_DST_PORT } - }, - [1685] = { - .class_hid = BNXT_ULP_CLASS_HID_206ee, - .class_tid = 3, - .hdr_sig_id = 38, - .flow_sig_id = 131072UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_38_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_DST_ADDR } - }, - [1686] = { - .class_hid = BNXT_ULP_CLASS_HID_20e5c, - .class_tid = 3, - .hdr_sig_id = 38, - .flow_sig_id = 131076UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_38_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_38_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_DST_ADDR } - }, - [1687] = { - .class_hid = BNXT_ULP_CLASS_HID_2110e, - .class_tid = 3, - .hdr_sig_id = 38, - .flow_sig_id = 131136UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_38_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_38_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_DST_ADDR } - }, - [1688] = { - .class_hid = BNXT_ULP_CLASS_HID_218fc, - .class_tid = 3, - .hdr_sig_id = 38, - .flow_sig_id = 131140UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_38_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_38_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_38_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_DST_ADDR } - }, - [1689] = { - .class_hid = BNXT_ULP_CLASS_HID_60462, - .class_tid = 3, - .hdr_sig_id = 38, - .flow_sig_id = 196608UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_38_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_DST_ADDR } - }, - [1690] = { - .class_hid = BNXT_ULP_CLASS_HID_603d0, - .class_tid = 3, - .hdr_sig_id = 38, - .flow_sig_id = 196612UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_38_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_38_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_DST_ADDR } - }, - [1691] = { - .class_hid = BNXT_ULP_CLASS_HID_61682, - .class_tid = 3, - .hdr_sig_id = 38, - .flow_sig_id = 196672UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_38_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_38_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_DST_ADDR } - }, - [1692] = { - .class_hid = BNXT_ULP_CLASS_HID_61e70, - .class_tid = 3, - .hdr_sig_id = 38, - .flow_sig_id = 196676UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_38_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_38_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_38_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_DST_ADDR } - }, - [1693] = { - .class_hid = BNXT_ULP_CLASS_HID_3167e, - .class_tid = 3, - .hdr_sig_id = 38, - .flow_sig_id = 393216UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_38_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_38_BITMASK_O_TCP_SRC_PORT } - }, - [1694] = { - .class_hid = BNXT_ULP_CLASS_HID_31dec, - .class_tid = 3, - .hdr_sig_id = 38, - .flow_sig_id = 393220UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_38_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_38_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_38_BITMASK_O_TCP_SRC_PORT } - }, - [1695] = { - .class_hid = BNXT_ULP_CLASS_HID_30030, - .class_tid = 3, - .hdr_sig_id = 38, - .flow_sig_id = 393280UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_38_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_38_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_38_BITMASK_O_TCP_SRC_PORT } - }, - [1696] = { - .class_hid = BNXT_ULP_CLASS_HID_30fae, - .class_tid = 3, - .hdr_sig_id = 38, - .flow_sig_id = 393284UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_38_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_38_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_38_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_38_BITMASK_O_TCP_SRC_PORT } - }, - [1697] = { - .class_hid = BNXT_ULP_CLASS_HID_70b14, - .class_tid = 3, - .hdr_sig_id = 38, - .flow_sig_id = 458752UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_38_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_38_BITMASK_O_TCP_SRC_PORT } - }, - [1698] = { - .class_hid = BNXT_ULP_CLASS_HID_71360, - .class_tid = 3, - .hdr_sig_id = 38, - .flow_sig_id = 458756UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_38_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_38_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_38_BITMASK_O_TCP_SRC_PORT } - }, - [1699] = { - .class_hid = BNXT_ULP_CLASS_HID_705b4, - .class_tid = 3, - .hdr_sig_id = 38, - .flow_sig_id = 458816UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_38_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_38_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_38_BITMASK_O_TCP_SRC_PORT } - }, - [1700] = { - .class_hid = BNXT_ULP_CLASS_HID_70d22, - .class_tid = 3, - .hdr_sig_id = 38, - .flow_sig_id = 458820UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_38_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_38_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_38_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_38_BITMASK_O_TCP_SRC_PORT } - }, - [1701] = { - .class_hid = BNXT_ULP_CLASS_HID_29e26, - .class_tid = 3, - .hdr_sig_id = 38, - .flow_sig_id = 655360UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_38_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_38_BITMASK_O_TCP_DST_PORT } - }, - [1702] = { - .class_hid = BNXT_ULP_CLASS_HID_28594, - .class_tid = 3, - .hdr_sig_id = 38, - .flow_sig_id = 655364UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_38_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_38_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_38_BITMASK_O_TCP_DST_PORT } - }, - [1703] = { - .class_hid = BNXT_ULP_CLASS_HID_288f8, - .class_tid = 3, - .hdr_sig_id = 38, - .flow_sig_id = 655424UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_38_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_38_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_38_BITMASK_O_TCP_DST_PORT } - }, - [1704] = { - .class_hid = BNXT_ULP_CLASS_HID_29034, - .class_tid = 3, - .hdr_sig_id = 38, - .flow_sig_id = 655428UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_38_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_38_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_38_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_38_BITMASK_O_TCP_DST_PORT } - }, - [1705] = { - .class_hid = BNXT_ULP_CLASS_HID_693ba, - .class_tid = 3, - .hdr_sig_id = 38, - .flow_sig_id = 720896UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_38_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_38_BITMASK_O_TCP_DST_PORT } - }, - [1706] = { - .class_hid = BNXT_ULP_CLASS_HID_69b28, - .class_tid = 3, - .hdr_sig_id = 38, - .flow_sig_id = 720900UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_38_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_38_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_38_BITMASK_O_TCP_DST_PORT } - }, - [1707] = { - .class_hid = BNXT_ULP_CLASS_HID_68e7c, - .class_tid = 3, - .hdr_sig_id = 38, - .flow_sig_id = 720960UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_38_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_38_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_38_BITMASK_O_TCP_DST_PORT } - }, - [1708] = { - .class_hid = BNXT_ULP_CLASS_HID_69648, - .class_tid = 3, - .hdr_sig_id = 38, - .flow_sig_id = 720964UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_38_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_38_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_38_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_38_BITMASK_O_TCP_DST_PORT } - }, - [1709] = { - .class_hid = BNXT_ULP_CLASS_HID_38de8, - .class_tid = 3, - .hdr_sig_id = 38, - .flow_sig_id = 917504UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_38_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_38_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_3_38_BITMASK_O_TCP_DST_PORT } - }, - [1710] = { - .class_hid = BNXT_ULP_CLASS_HID_39524, - .class_tid = 3, - .hdr_sig_id = 38, - .flow_sig_id = 917508UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_38_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_38_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_38_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_3_38_BITMASK_O_TCP_DST_PORT } - }, - [1711] = { - .class_hid = BNXT_ULP_CLASS_HID_39808, - .class_tid = 3, - .hdr_sig_id = 38, - .flow_sig_id = 917568UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_38_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_38_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_38_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_3_38_BITMASK_O_TCP_DST_PORT } - }, - [1712] = { - .class_hid = BNXT_ULP_CLASS_HID_387e6, - .class_tid = 3, - .hdr_sig_id = 38, - .flow_sig_id = 917572UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_38_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_38_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_38_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_38_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_3_38_BITMASK_O_TCP_DST_PORT } - }, - [1713] = { - .class_hid = BNXT_ULP_CLASS_HID_7836c, - .class_tid = 3, - .hdr_sig_id = 38, - .flow_sig_id = 983040UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_38_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_38_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_3_38_BITMASK_O_TCP_DST_PORT } - }, - [1714] = { - .class_hid = BNXT_ULP_CLASS_HID_78ada, - .class_tid = 3, - .hdr_sig_id = 38, - .flow_sig_id = 983044UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_38_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_38_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_38_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_3_38_BITMASK_O_TCP_DST_PORT } - }, - [1715] = { - .class_hid = BNXT_ULP_CLASS_HID_79d8c, - .class_tid = 3, - .hdr_sig_id = 38, - .flow_sig_id = 983104UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_38_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_38_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_38_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_3_38_BITMASK_O_TCP_DST_PORT } - }, - [1716] = { - .class_hid = BNXT_ULP_CLASS_HID_7857a, - .class_tid = 3, - .hdr_sig_id = 38, - .flow_sig_id = 983108UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_38_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_38_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_38_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_38_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_3_38_BITMASK_O_TCP_DST_PORT } - }, - [1717] = { - .class_hid = BNXT_ULP_CLASS_HID_81ad8, - .class_tid = 3, - .hdr_sig_id = 39, - .flow_sig_id = 32768UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_39_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_DST_ADDR } - }, - [1718] = { - .class_hid = BNXT_ULP_CLASS_HID_8026e, - .class_tid = 3, - .hdr_sig_id = 39, - .flow_sig_id = 32772UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_39_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_39_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_DST_ADDR } - }, - [1719] = { - .class_hid = BNXT_ULP_CLASS_HID_815b8, - .class_tid = 3, - .hdr_sig_id = 39, - .flow_sig_id = 32832UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_39_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_39_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_DST_ADDR } - }, - [1720] = { - .class_hid = BNXT_ULP_CLASS_HID_81cce, - .class_tid = 3, - .hdr_sig_id = 39, - .flow_sig_id = 32836UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_39_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_39_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_39_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_DST_ADDR } - }, - [1721] = { - .class_hid = BNXT_ULP_CLASS_HID_810c8, - .class_tid = 3, - .hdr_sig_id = 39, - .flow_sig_id = 49152UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_39_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_DST_ADDR } - }, - [1722] = { - .class_hid = BNXT_ULP_CLASS_HID_8185e, - .class_tid = 3, - .hdr_sig_id = 39, - .flow_sig_id = 49156UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_39_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_39_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_DST_ADDR } - }, - [1723] = { - .class_hid = BNXT_ULP_CLASS_HID_8030a, - .class_tid = 3, - .hdr_sig_id = 39, - .flow_sig_id = 49216UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_39_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_39_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_DST_ADDR } - }, - [1724] = { - .class_hid = BNXT_ULP_CLASS_HID_80a98, - .class_tid = 3, - .hdr_sig_id = 39, - .flow_sig_id = 49220UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_39_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_39_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_39_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_DST_ADDR } - }, - [1725] = { - .class_hid = BNXT_ULP_CLASS_HID_c1844, - .class_tid = 3, - .hdr_sig_id = 39, - .flow_sig_id = 98304UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_39_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_39_BITMASK_O_UDP_SRC_PORT } - }, - [1726] = { - .class_hid = BNXT_ULP_CLASS_HID_c07ea, - .class_tid = 3, - .hdr_sig_id = 39, - .flow_sig_id = 98308UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_39_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_39_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_39_BITMASK_O_UDP_SRC_PORT } - }, - [1727] = { - .class_hid = BNXT_ULP_CLASS_HID_c0a86, - .class_tid = 3, - .hdr_sig_id = 39, - .flow_sig_id = 98368UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_39_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_39_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_39_BITMASK_O_UDP_SRC_PORT } - }, - [1728] = { - .class_hid = BNXT_ULP_CLASS_HID_c124a, - .class_tid = 3, - .hdr_sig_id = 39, - .flow_sig_id = 98372UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_39_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_39_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_39_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_39_BITMASK_O_UDP_SRC_PORT } - }, - [1729] = { - .class_hid = BNXT_ULP_CLASS_HID_c16b4, - .class_tid = 3, - .hdr_sig_id = 39, - .flow_sig_id = 114688UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_39_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_39_BITMASK_O_UDP_SRC_PORT } - }, - [1730] = { - .class_hid = BNXT_ULP_CLASS_HID_c1dda, - .class_tid = 3, - .hdr_sig_id = 39, - .flow_sig_id = 114692UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_39_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_39_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_39_BITMASK_O_UDP_SRC_PORT } - }, - [1731] = { - .class_hid = BNXT_ULP_CLASS_HID_c00f6, - .class_tid = 3, - .hdr_sig_id = 39, - .flow_sig_id = 114752UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_39_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_39_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_39_BITMASK_O_UDP_SRC_PORT } - }, - [1732] = { - .class_hid = BNXT_ULP_CLASS_HID_c0804, - .class_tid = 3, - .hdr_sig_id = 39, - .flow_sig_id = 114756UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_39_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_39_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_39_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_39_BITMASK_O_UDP_SRC_PORT } - }, - [1733] = { - .class_hid = BNXT_ULP_CLASS_HID_a199a, - .class_tid = 3, - .hdr_sig_id = 39, - .flow_sig_id = 163840UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_39_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_39_BITMASK_O_UDP_DST_PORT } - }, - [1734] = { - .class_hid = BNXT_ULP_CLASS_HID_a0128, - .class_tid = 3, - .hdr_sig_id = 39, - .flow_sig_id = 163844UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_39_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_39_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_39_BITMASK_O_UDP_DST_PORT } - }, - [1735] = { - .class_hid = BNXT_ULP_CLASS_HID_a0bc4, - .class_tid = 3, - .hdr_sig_id = 39, - .flow_sig_id = 163904UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_39_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_39_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_39_BITMASK_O_UDP_DST_PORT } - }, - [1736] = { - .class_hid = BNXT_ULP_CLASS_HID_a1388, - .class_tid = 3, - .hdr_sig_id = 39, - .flow_sig_id = 163908UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_39_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_39_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_39_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_39_BITMASK_O_UDP_DST_PORT } - }, - [1737] = { - .class_hid = BNXT_ULP_CLASS_HID_a178a, - .class_tid = 3, - .hdr_sig_id = 39, - .flow_sig_id = 180224UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_39_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_39_BITMASK_O_UDP_DST_PORT } - }, - [1738] = { - .class_hid = BNXT_ULP_CLASS_HID_a1f18, - .class_tid = 3, - .hdr_sig_id = 39, - .flow_sig_id = 180228UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_39_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_39_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_39_BITMASK_O_UDP_DST_PORT } - }, - [1739] = { - .class_hid = BNXT_ULP_CLASS_HID_a0234, - .class_tid = 3, - .hdr_sig_id = 39, - .flow_sig_id = 180288UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_39_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_39_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_39_BITMASK_O_UDP_DST_PORT } - }, - [1740] = { - .class_hid = BNXT_ULP_CLASS_HID_a095a, - .class_tid = 3, - .hdr_sig_id = 39, - .flow_sig_id = 180292UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_39_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_39_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_39_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_39_BITMASK_O_UDP_DST_PORT } - }, - [1741] = { - .class_hid = BNXT_ULP_CLASS_HID_e1f06, - .class_tid = 3, - .hdr_sig_id = 39, - .flow_sig_id = 229376UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_39_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_39_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_3_39_BITMASK_O_UDP_DST_PORT } - }, - [1742] = { - .class_hid = BNXT_ULP_CLASS_HID_e0694, - .class_tid = 3, - .hdr_sig_id = 39, - .flow_sig_id = 229380UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_39_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_39_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_39_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_3_39_BITMASK_O_UDP_DST_PORT } - }, - [1743] = { - .class_hid = BNXT_ULP_CLASS_HID_e0940, - .class_tid = 3, - .hdr_sig_id = 39, - .flow_sig_id = 229440UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_39_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_39_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_39_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_3_39_BITMASK_O_UDP_DST_PORT } - }, - [1744] = { - .class_hid = BNXT_ULP_CLASS_HID_e1174, - .class_tid = 3, - .hdr_sig_id = 39, - .flow_sig_id = 229444UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_39_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_39_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_39_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_39_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_3_39_BITMASK_O_UDP_DST_PORT } - }, - [1745] = { - .class_hid = BNXT_ULP_CLASS_HID_e1576, - .class_tid = 3, - .hdr_sig_id = 39, - .flow_sig_id = 245760UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_39_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_39_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_3_39_BITMASK_O_UDP_DST_PORT } - }, - [1746] = { - .class_hid = BNXT_ULP_CLASS_HID_e1c84, - .class_tid = 3, - .hdr_sig_id = 39, - .flow_sig_id = 245764UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_39_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_39_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_39_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_3_39_BITMASK_O_UDP_DST_PORT } - }, - [1747] = { - .class_hid = BNXT_ULP_CLASS_HID_e07b0, - .class_tid = 3, - .hdr_sig_id = 39, - .flow_sig_id = 245824UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_39_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_39_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_39_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_3_39_BITMASK_O_UDP_DST_PORT } - }, - [1748] = { - .class_hid = BNXT_ULP_CLASS_HID_e0ec6, - .class_tid = 3, - .hdr_sig_id = 39, - .flow_sig_id = 245828UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_39_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_39_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_39_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_39_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_3_39_BITMASK_O_UDP_DST_PORT } - }, - [1749] = { - .class_hid = BNXT_ULP_CLASS_HID_2069e, - .class_tid = 3, - .hdr_sig_id = 40, - .flow_sig_id = 131072UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_40_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_DST_ADDR } - }, - [1750] = { - .class_hid = BNXT_ULP_CLASS_HID_20e2c, - .class_tid = 3, - .hdr_sig_id = 40, - .flow_sig_id = 131076UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_40_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_40_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_DST_ADDR } - }, - [1751] = { - .class_hid = BNXT_ULP_CLASS_HID_2117e, - .class_tid = 3, - .hdr_sig_id = 40, - .flow_sig_id = 131136UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_40_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_40_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_DST_ADDR } - }, - [1752] = { - .class_hid = BNXT_ULP_CLASS_HID_2188c, - .class_tid = 3, - .hdr_sig_id = 40, - .flow_sig_id = 131140UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_40_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_40_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_40_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_DST_ADDR } - }, - [1753] = { - .class_hid = BNXT_ULP_CLASS_HID_60412, - .class_tid = 3, - .hdr_sig_id = 40, - .flow_sig_id = 196608UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_40_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_DST_ADDR } - }, - [1754] = { - .class_hid = BNXT_ULP_CLASS_HID_603a0, - .class_tid = 3, - .hdr_sig_id = 40, - .flow_sig_id = 196612UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_40_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_40_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_DST_ADDR } - }, - [1755] = { - .class_hid = BNXT_ULP_CLASS_HID_616f2, - .class_tid = 3, - .hdr_sig_id = 40, - .flow_sig_id = 196672UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_40_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_40_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_DST_ADDR } - }, - [1756] = { - .class_hid = BNXT_ULP_CLASS_HID_61e00, - .class_tid = 3, - .hdr_sig_id = 40, - .flow_sig_id = 196676UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_40_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_40_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_40_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_DST_ADDR } - }, - [1757] = { - .class_hid = BNXT_ULP_CLASS_HID_3160e, - .class_tid = 3, - .hdr_sig_id = 40, - .flow_sig_id = 393216UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_40_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_40_BITMASK_O_UDP_SRC_PORT } - }, - [1758] = { - .class_hid = BNXT_ULP_CLASS_HID_31d9c, - .class_tid = 3, - .hdr_sig_id = 40, - .flow_sig_id = 393220UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_40_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_40_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_40_BITMASK_O_UDP_SRC_PORT } - }, - [1759] = { - .class_hid = BNXT_ULP_CLASS_HID_30040, - .class_tid = 3, - .hdr_sig_id = 40, - .flow_sig_id = 393280UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_40_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_40_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_40_BITMASK_O_UDP_SRC_PORT } - }, - [1760] = { - .class_hid = BNXT_ULP_CLASS_HID_30fde, - .class_tid = 3, - .hdr_sig_id = 40, - .flow_sig_id = 393284UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_40_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_40_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_40_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_40_BITMASK_O_UDP_SRC_PORT } - }, - [1761] = { - .class_hid = BNXT_ULP_CLASS_HID_70b64, - .class_tid = 3, - .hdr_sig_id = 40, - .flow_sig_id = 458752UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_40_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_40_BITMASK_O_UDP_SRC_PORT } - }, - [1762] = { - .class_hid = BNXT_ULP_CLASS_HID_71310, - .class_tid = 3, - .hdr_sig_id = 40, - .flow_sig_id = 458756UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_40_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_40_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_40_BITMASK_O_UDP_SRC_PORT } - }, - [1763] = { - .class_hid = BNXT_ULP_CLASS_HID_705c4, - .class_tid = 3, - .hdr_sig_id = 40, - .flow_sig_id = 458816UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_40_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_40_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_40_BITMASK_O_UDP_SRC_PORT } - }, - [1764] = { - .class_hid = BNXT_ULP_CLASS_HID_70d52, - .class_tid = 3, - .hdr_sig_id = 40, - .flow_sig_id = 458820UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_40_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_40_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_40_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_40_BITMASK_O_UDP_SRC_PORT } - }, - [1765] = { - .class_hid = BNXT_ULP_CLASS_HID_29e56, - .class_tid = 3, - .hdr_sig_id = 40, - .flow_sig_id = 655360UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_40_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_40_BITMASK_O_UDP_DST_PORT } - }, - [1766] = { - .class_hid = BNXT_ULP_CLASS_HID_285e4, - .class_tid = 3, - .hdr_sig_id = 40, - .flow_sig_id = 655364UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_40_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_40_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_40_BITMASK_O_UDP_DST_PORT } - }, - [1767] = { - .class_hid = BNXT_ULP_CLASS_HID_28888, - .class_tid = 3, - .hdr_sig_id = 40, - .flow_sig_id = 655424UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_40_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_40_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_40_BITMASK_O_UDP_DST_PORT } - }, - [1768] = { - .class_hid = BNXT_ULP_CLASS_HID_29044, - .class_tid = 3, - .hdr_sig_id = 40, - .flow_sig_id = 655428UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_40_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_40_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_40_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_40_BITMASK_O_UDP_DST_PORT } - }, - [1769] = { - .class_hid = BNXT_ULP_CLASS_HID_693ca, - .class_tid = 3, - .hdr_sig_id = 40, - .flow_sig_id = 720896UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_40_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_40_BITMASK_O_UDP_DST_PORT } - }, - [1770] = { - .class_hid = BNXT_ULP_CLASS_HID_69b58, - .class_tid = 3, - .hdr_sig_id = 40, - .flow_sig_id = 720900UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_40_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_40_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_40_BITMASK_O_UDP_DST_PORT } - }, - [1771] = { - .class_hid = BNXT_ULP_CLASS_HID_68e0c, - .class_tid = 3, - .hdr_sig_id = 40, - .flow_sig_id = 720960UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_40_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_40_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_40_BITMASK_O_UDP_DST_PORT } - }, - [1772] = { - .class_hid = BNXT_ULP_CLASS_HID_69638, - .class_tid = 3, - .hdr_sig_id = 40, - .flow_sig_id = 720964UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_40_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_40_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_40_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_40_BITMASK_O_UDP_DST_PORT } - }, - [1773] = { - .class_hid = BNXT_ULP_CLASS_HID_38d98, - .class_tid = 3, - .hdr_sig_id = 40, - .flow_sig_id = 917504UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_40_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_40_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_3_40_BITMASK_O_UDP_DST_PORT } - }, - [1774] = { - .class_hid = BNXT_ULP_CLASS_HID_39554, - .class_tid = 3, - .hdr_sig_id = 40, - .flow_sig_id = 917508UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_40_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_40_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_40_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_3_40_BITMASK_O_UDP_DST_PORT } - }, - [1775] = { - .class_hid = BNXT_ULP_CLASS_HID_39878, - .class_tid = 3, - .hdr_sig_id = 40, - .flow_sig_id = 917568UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_40_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_40_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_40_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_3_40_BITMASK_O_UDP_DST_PORT } - }, - [1776] = { - .class_hid = BNXT_ULP_CLASS_HID_38796, - .class_tid = 3, - .hdr_sig_id = 40, - .flow_sig_id = 917572UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_40_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_40_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_40_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_40_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_3_40_BITMASK_O_UDP_DST_PORT } - }, - [1777] = { - .class_hid = BNXT_ULP_CLASS_HID_7831c, - .class_tid = 3, - .hdr_sig_id = 40, - .flow_sig_id = 983040UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_40_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_40_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_3_40_BITMASK_O_UDP_DST_PORT } - }, - [1778] = { - .class_hid = BNXT_ULP_CLASS_HID_78aaa, - .class_tid = 3, - .hdr_sig_id = 40, - .flow_sig_id = 983044UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_40_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_40_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_40_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_3_40_BITMASK_O_UDP_DST_PORT } - }, - [1779] = { - .class_hid = BNXT_ULP_CLASS_HID_79dfc, - .class_tid = 3, - .hdr_sig_id = 40, - .flow_sig_id = 983104UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_40_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_40_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_40_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_3_40_BITMASK_O_UDP_DST_PORT } - }, - [1780] = { - .class_hid = BNXT_ULP_CLASS_HID_7850a, - .class_tid = 3, - .hdr_sig_id = 40, - .flow_sig_id = 983108UL, - .flow_pattern_id = 0, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_40_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_40_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_40_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_40_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_3_40_BITMASK_O_UDP_DST_PORT } - }, - [1781] = { - .class_hid = BNXT_ULP_CLASS_HID_03b7, - .class_tid = 3, - .hdr_sig_id = 29, - .flow_sig_id = 4096UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_29_BITMASK_O_IPV6_DST_ADDR } - }, - [1782] = { - .class_hid = BNXT_ULP_CLASS_HID_13f3, - .class_tid = 3, - .hdr_sig_id = 29, - .flow_sig_id = 6144UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_29_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_29_BITMASK_O_IPV6_DST_ADDR } - }, - [1783] = { - .class_hid = BNXT_ULP_CLASS_HID_0255, - .class_tid = 3, - .hdr_sig_id = 30, - .flow_sig_id = 16384UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_30_BITMASK_O_IPV4_DST_ADDR } - }, - [1784] = { - .class_hid = BNXT_ULP_CLASS_HID_1675, - .class_tid = 3, - .hdr_sig_id = 30, - .flow_sig_id = 24576UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_30_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_30_BITMASK_O_IPV4_DST_ADDR } - }, - [1785] = { - .class_hid = BNXT_ULP_CLASS_HID_80f52, - .class_tid = 3, - .hdr_sig_id = 31, - .flow_sig_id = 32768UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_31_BITMASK_O_IPV6_DST_ADDR } - }, - [1786] = { - .class_hid = BNXT_ULP_CLASS_HID_819f2, - .class_tid = 3, - .hdr_sig_id = 31, - .flow_sig_id = 32832UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_31_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_31_BITMASK_O_IPV6_DST_ADDR } - }, - [1787] = { - .class_hid = BNXT_ULP_CLASS_HID_80542, - .class_tid = 3, - .hdr_sig_id = 31, - .flow_sig_id = 49152UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_31_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_31_BITMASK_O_IPV6_DST_ADDR } - }, - [1788] = { - .class_hid = BNXT_ULP_CLASS_HID_817e2, - .class_tid = 3, - .hdr_sig_id = 31, - .flow_sig_id = 49216UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_31_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_31_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_31_BITMASK_O_IPV6_DST_ADDR } - }, - [1789] = { - .class_hid = BNXT_ULP_CLASS_HID_20a98, - .class_tid = 3, - .hdr_sig_id = 32, - .flow_sig_id = 131072UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_32_BITMASK_O_IPV4_DST_ADDR } - }, - [1790] = { - .class_hid = BNXT_ULP_CLASS_HID_20538, - .class_tid = 3, - .hdr_sig_id = 32, - .flow_sig_id = 131136UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_32_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_32_BITMASK_O_IPV4_DST_ADDR } - }, - [1791] = { - .class_hid = BNXT_ULP_CLASS_HID_6081c, - .class_tid = 3, - .hdr_sig_id = 32, - .flow_sig_id = 196608UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_32_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_32_BITMASK_O_IPV4_DST_ADDR } - }, - [1792] = { - .class_hid = BNXT_ULP_CLASS_HID_61abc, - .class_tid = 3, - .hdr_sig_id = 32, - .flow_sig_id = 196672UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_32_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_32_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_32_BITMASK_O_IPV4_DST_ADDR } - }, - [1793] = { - .class_hid = BNXT_ULP_CLASS_HID_03a7, - .class_tid = 3, - .hdr_sig_id = 33, - .flow_sig_id = 4096UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_33_BITMASK_O_IPV6_DST_ADDR } - }, - [1794] = { - .class_hid = BNXT_ULP_CLASS_HID_13e3, - .class_tid = 3, - .hdr_sig_id = 33, - .flow_sig_id = 6144UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_33_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_33_BITMASK_O_IPV6_DST_ADDR } - }, - [1795] = { - .class_hid = BNXT_ULP_CLASS_HID_1047, - .class_tid = 3, - .hdr_sig_id = 33, - .flow_sig_id = 12288UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_33_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_33_BITMASK_O_TCP_SRC_PORT } - }, - [1796] = { - .class_hid = BNXT_ULP_CLASS_HID_0721, - .class_tid = 3, - .hdr_sig_id = 33, - .flow_sig_id = 14336UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_33_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_33_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_33_BITMASK_O_TCP_SRC_PORT } - }, - [1797] = { - .class_hid = BNXT_ULP_CLASS_HID_19b7, - .class_tid = 3, - .hdr_sig_id = 33, - .flow_sig_id = 20480UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_33_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_33_BITMASK_O_TCP_DST_PORT } - }, - [1798] = { - .class_hid = BNXT_ULP_CLASS_HID_0911, - .class_tid = 3, - .hdr_sig_id = 33, - .flow_sig_id = 22528UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_33_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_33_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_33_BITMASK_O_TCP_DST_PORT } - }, - [1799] = { - .class_hid = BNXT_ULP_CLASS_HID_0df5, - .class_tid = 3, - .hdr_sig_id = 33, - .flow_sig_id = 28672UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_33_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_33_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_3_33_BITMASK_O_TCP_DST_PORT } - }, - [1800] = { - .class_hid = BNXT_ULP_CLASS_HID_1d31, - .class_tid = 3, - .hdr_sig_id = 33, - .flow_sig_id = 30720UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_33_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_33_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_33_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_3_33_BITMASK_O_TCP_DST_PORT } - }, - [1801] = { - .class_hid = BNXT_ULP_CLASS_HID_0245, - .class_tid = 3, - .hdr_sig_id = 34, - .flow_sig_id = 16384UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_34_BITMASK_O_IPV4_DST_ADDR } - }, - [1802] = { - .class_hid = BNXT_ULP_CLASS_HID_1665, - .class_tid = 3, - .hdr_sig_id = 34, - .flow_sig_id = 24576UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_34_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_34_BITMASK_O_IPV4_DST_ADDR } - }, - [1803] = { - .class_hid = BNXT_ULP_CLASS_HID_8055d, - .class_tid = 3, - .hdr_sig_id = 34, - .flow_sig_id = 49152UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_34_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_34_BITMASK_O_TCP_SRC_PORT } - }, - [1804] = { - .class_hid = BNXT_ULP_CLASS_HID_80893, - .class_tid = 3, - .hdr_sig_id = 34, - .flow_sig_id = 57344UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_34_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_34_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_34_BITMASK_O_TCP_SRC_PORT } - }, - [1805] = { - .class_hid = BNXT_ULP_CLASS_HID_407d9, - .class_tid = 3, - .hdr_sig_id = 34, - .flow_sig_id = 81920UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_34_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_34_BITMASK_O_TCP_DST_PORT } - }, - [1806] = { - .class_hid = BNXT_ULP_CLASS_HID_40b1f, - .class_tid = 3, - .hdr_sig_id = 34, - .flow_sig_id = 90112UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_34_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_34_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_34_BITMASK_O_TCP_DST_PORT } - }, - [1807] = { - .class_hid = BNXT_ULP_CLASS_HID_c1ad1, - .class_tid = 3, - .hdr_sig_id = 34, - .flow_sig_id = 114688UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_34_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_34_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_3_34_BITMASK_O_TCP_DST_PORT } - }, - [1808] = { - .class_hid = BNXT_ULP_CLASS_HID_c0e17, - .class_tid = 3, - .hdr_sig_id = 34, - .flow_sig_id = 122880UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_34_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_34_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_34_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_3_34_BITMASK_O_TCP_DST_PORT } - }, - [1809] = { - .class_hid = BNXT_ULP_CLASS_HID_03d7, - .class_tid = 3, - .hdr_sig_id = 35, - .flow_sig_id = 4096UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_35_BITMASK_O_IPV6_DST_ADDR } - }, - [1810] = { - .class_hid = BNXT_ULP_CLASS_HID_1393, - .class_tid = 3, - .hdr_sig_id = 35, - .flow_sig_id = 6144UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_35_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_35_BITMASK_O_IPV6_DST_ADDR } - }, - [1811] = { - .class_hid = BNXT_ULP_CLASS_HID_1037, - .class_tid = 3, - .hdr_sig_id = 35, - .flow_sig_id = 12288UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_35_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_35_BITMASK_O_UDP_SRC_PORT } - }, - [1812] = { - .class_hid = BNXT_ULP_CLASS_HID_0751, - .class_tid = 3, - .hdr_sig_id = 35, - .flow_sig_id = 14336UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_35_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_35_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_35_BITMASK_O_UDP_SRC_PORT } - }, - [1813] = { - .class_hid = BNXT_ULP_CLASS_HID_19c7, - .class_tid = 3, - .hdr_sig_id = 35, - .flow_sig_id = 20480UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_35_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_35_BITMASK_O_UDP_DST_PORT } - }, - [1814] = { - .class_hid = BNXT_ULP_CLASS_HID_0961, - .class_tid = 3, - .hdr_sig_id = 35, - .flow_sig_id = 22528UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_35_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_35_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_35_BITMASK_O_UDP_DST_PORT } - }, - [1815] = { - .class_hid = BNXT_ULP_CLASS_HID_0d85, - .class_tid = 3, - .hdr_sig_id = 35, - .flow_sig_id = 28672UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_35_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_35_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_3_35_BITMASK_O_UDP_DST_PORT } - }, - [1816] = { - .class_hid = BNXT_ULP_CLASS_HID_1d41, - .class_tid = 3, - .hdr_sig_id = 35, - .flow_sig_id = 30720UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_35_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_35_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_35_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_3_35_BITMASK_O_UDP_DST_PORT } - }, - [1817] = { - .class_hid = BNXT_ULP_CLASS_HID_0235, - .class_tid = 3, - .hdr_sig_id = 36, - .flow_sig_id = 16384UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_36_BITMASK_O_IPV4_DST_ADDR } - }, - [1818] = { - .class_hid = BNXT_ULP_CLASS_HID_1615, - .class_tid = 3, - .hdr_sig_id = 36, - .flow_sig_id = 24576UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_36_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_36_BITMASK_O_IPV4_DST_ADDR } - }, - [1819] = { - .class_hid = BNXT_ULP_CLASS_HID_8052d, - .class_tid = 3, - .hdr_sig_id = 36, - .flow_sig_id = 49152UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_36_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_36_BITMASK_O_UDP_SRC_PORT } - }, - [1820] = { - .class_hid = BNXT_ULP_CLASS_HID_808e3, - .class_tid = 3, - .hdr_sig_id = 36, - .flow_sig_id = 57344UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_36_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_36_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_36_BITMASK_O_UDP_SRC_PORT } - }, - [1821] = { - .class_hid = BNXT_ULP_CLASS_HID_407a9, - .class_tid = 3, - .hdr_sig_id = 36, - .flow_sig_id = 81920UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_36_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_36_BITMASK_O_UDP_DST_PORT } - }, - [1822] = { - .class_hid = BNXT_ULP_CLASS_HID_40b6f, - .class_tid = 3, - .hdr_sig_id = 36, - .flow_sig_id = 90112UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_36_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_36_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_36_BITMASK_O_UDP_DST_PORT } - }, - [1823] = { - .class_hid = BNXT_ULP_CLASS_HID_c1aa1, - .class_tid = 3, - .hdr_sig_id = 36, - .flow_sig_id = 114688UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_36_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_36_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_3_36_BITMASK_O_UDP_DST_PORT } - }, - [1824] = { - .class_hid = BNXT_ULP_CLASS_HID_c0e67, - .class_tid = 3, - .hdr_sig_id = 36, - .flow_sig_id = 122880UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_36_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_36_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_36_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_3_36_BITMASK_O_UDP_DST_PORT } - }, - [1825] = { - .class_hid = BNXT_ULP_CLASS_HID_80f42, - .class_tid = 3, - .hdr_sig_id = 37, - .flow_sig_id = 32768UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_DST_ADDR } - }, - [1826] = { - .class_hid = BNXT_ULP_CLASS_HID_819e2, - .class_tid = 3, - .hdr_sig_id = 37, - .flow_sig_id = 32832UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_37_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_DST_ADDR } - }, - [1827] = { - .class_hid = BNXT_ULP_CLASS_HID_80552, - .class_tid = 3, - .hdr_sig_id = 37, - .flow_sig_id = 49152UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_DST_ADDR } - }, - [1828] = { - .class_hid = BNXT_ULP_CLASS_HID_817f2, - .class_tid = 3, - .hdr_sig_id = 37, - .flow_sig_id = 49216UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_37_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_DST_ADDR } - }, - [1829] = { - .class_hid = BNXT_ULP_CLASS_HID_c0cce, - .class_tid = 3, - .hdr_sig_id = 37, - .flow_sig_id = 98304UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_37_BITMASK_O_TCP_SRC_PORT } - }, - [1830] = { - .class_hid = BNXT_ULP_CLASS_HID_c1f6e, - .class_tid = 3, - .hdr_sig_id = 37, - .flow_sig_id = 98368UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_37_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_37_BITMASK_O_TCP_SRC_PORT } - }, - [1831] = { - .class_hid = BNXT_ULP_CLASS_HID_c1ade, - .class_tid = 3, - .hdr_sig_id = 37, - .flow_sig_id = 114688UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_37_BITMASK_O_TCP_SRC_PORT } - }, - [1832] = { - .class_hid = BNXT_ULP_CLASS_HID_c157e, - .class_tid = 3, - .hdr_sig_id = 37, - .flow_sig_id = 114752UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_37_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_37_BITMASK_O_TCP_SRC_PORT } - }, - [1833] = { - .class_hid = BNXT_ULP_CLASS_HID_a0d8c, - .class_tid = 3, - .hdr_sig_id = 37, - .flow_sig_id = 163840UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_37_BITMASK_O_TCP_DST_PORT } - }, - [1834] = { - .class_hid = BNXT_ULP_CLASS_HID_a182c, - .class_tid = 3, - .hdr_sig_id = 37, - .flow_sig_id = 163904UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_37_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_37_BITMASK_O_TCP_DST_PORT } - }, - [1835] = { - .class_hid = BNXT_ULP_CLASS_HID_a1b9c, - .class_tid = 3, - .hdr_sig_id = 37, - .flow_sig_id = 180224UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_37_BITMASK_O_TCP_DST_PORT } - }, - [1836] = { - .class_hid = BNXT_ULP_CLASS_HID_a163c, - .class_tid = 3, - .hdr_sig_id = 37, - .flow_sig_id = 180288UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_37_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_37_BITMASK_O_TCP_DST_PORT } - }, - [1837] = { - .class_hid = BNXT_ULP_CLASS_HID_e0308, - .class_tid = 3, - .hdr_sig_id = 37, - .flow_sig_id = 229376UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_37_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_3_37_BITMASK_O_TCP_DST_PORT } - }, - [1838] = { - .class_hid = BNXT_ULP_CLASS_HID_e1da8, - .class_tid = 3, - .hdr_sig_id = 37, - .flow_sig_id = 229440UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_37_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_37_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_3_37_BITMASK_O_TCP_DST_PORT } - }, - [1839] = { - .class_hid = BNXT_ULP_CLASS_HID_e1918, - .class_tid = 3, - .hdr_sig_id = 37, - .flow_sig_id = 245760UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_37_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_3_37_BITMASK_O_TCP_DST_PORT } - }, - [1840] = { - .class_hid = BNXT_ULP_CLASS_HID_e0bda, - .class_tid = 3, - .hdr_sig_id = 37, - .flow_sig_id = 245824UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_37_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_37_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_3_37_BITMASK_O_TCP_DST_PORT } - }, - [1841] = { - .class_hid = BNXT_ULP_CLASS_HID_20a88, - .class_tid = 3, - .hdr_sig_id = 38, - .flow_sig_id = 131072UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_DST_ADDR } - }, - [1842] = { - .class_hid = BNXT_ULP_CLASS_HID_20528, - .class_tid = 3, - .hdr_sig_id = 38, - .flow_sig_id = 131136UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_38_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_DST_ADDR } - }, - [1843] = { - .class_hid = BNXT_ULP_CLASS_HID_6080c, - .class_tid = 3, - .hdr_sig_id = 38, - .flow_sig_id = 196608UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_DST_ADDR } - }, - [1844] = { - .class_hid = BNXT_ULP_CLASS_HID_61aac, - .class_tid = 3, - .hdr_sig_id = 38, - .flow_sig_id = 196672UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_38_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_DST_ADDR } - }, - [1845] = { - .class_hid = BNXT_ULP_CLASS_HID_31a18, - .class_tid = 3, - .hdr_sig_id = 38, - .flow_sig_id = 393216UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_38_BITMASK_O_TCP_SRC_PORT } - }, - [1846] = { - .class_hid = BNXT_ULP_CLASS_HID_314b8, - .class_tid = 3, - .hdr_sig_id = 38, - .flow_sig_id = 393280UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_38_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_38_BITMASK_O_TCP_SRC_PORT } - }, - [1847] = { - .class_hid = BNXT_ULP_CLASS_HID_71f9c, - .class_tid = 3, - .hdr_sig_id = 38, - .flow_sig_id = 458752UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_38_BITMASK_O_TCP_SRC_PORT } - }, - [1848] = { - .class_hid = BNXT_ULP_CLASS_HID_70a5e, - .class_tid = 3, - .hdr_sig_id = 38, - .flow_sig_id = 458816UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_38_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_38_BITMASK_O_TCP_SRC_PORT } - }, - [1849] = { - .class_hid = BNXT_ULP_CLASS_HID_282c0, - .class_tid = 3, - .hdr_sig_id = 38, - .flow_sig_id = 655360UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_38_BITMASK_O_TCP_DST_PORT } - }, - [1850] = { - .class_hid = BNXT_ULP_CLASS_HID_29d60, - .class_tid = 3, - .hdr_sig_id = 38, - .flow_sig_id = 655424UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_38_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_38_BITMASK_O_TCP_DST_PORT } - }, - [1851] = { - .class_hid = BNXT_ULP_CLASS_HID_68044, - .class_tid = 3, - .hdr_sig_id = 38, - .flow_sig_id = 720896UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_38_BITMASK_O_TCP_DST_PORT } - }, - [1852] = { - .class_hid = BNXT_ULP_CLASS_HID_692e4, - .class_tid = 3, - .hdr_sig_id = 38, - .flow_sig_id = 720960UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_38_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_38_BITMASK_O_TCP_DST_PORT } - }, - [1853] = { - .class_hid = BNXT_ULP_CLASS_HID_39250, - .class_tid = 3, - .hdr_sig_id = 38, - .flow_sig_id = 917504UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_38_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_3_38_BITMASK_O_TCP_DST_PORT } - }, - [1854] = { - .class_hid = BNXT_ULP_CLASS_HID_38c12, - .class_tid = 3, - .hdr_sig_id = 38, - .flow_sig_id = 917568UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_38_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_38_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_3_38_BITMASK_O_TCP_DST_PORT } - }, - [1855] = { - .class_hid = BNXT_ULP_CLASS_HID_797d4, - .class_tid = 3, - .hdr_sig_id = 38, - .flow_sig_id = 983040UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_38_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_3_38_BITMASK_O_TCP_DST_PORT } - }, - [1856] = { - .class_hid = BNXT_ULP_CLASS_HID_78196, - .class_tid = 3, - .hdr_sig_id = 38, - .flow_sig_id = 983104UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_38_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_38_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_3_38_BITMASK_O_TCP_DST_PORT } - }, - [1857] = { - .class_hid = BNXT_ULP_CLASS_HID_80f32, - .class_tid = 3, - .hdr_sig_id = 39, - .flow_sig_id = 32768UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_DST_ADDR } - }, - [1858] = { - .class_hid = BNXT_ULP_CLASS_HID_81992, - .class_tid = 3, - .hdr_sig_id = 39, - .flow_sig_id = 32832UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_39_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_DST_ADDR } - }, - [1859] = { - .class_hid = BNXT_ULP_CLASS_HID_80522, - .class_tid = 3, - .hdr_sig_id = 39, - .flow_sig_id = 49152UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_DST_ADDR } - }, - [1860] = { - .class_hid = BNXT_ULP_CLASS_HID_81782, - .class_tid = 3, - .hdr_sig_id = 39, - .flow_sig_id = 49216UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_39_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_DST_ADDR } - }, - [1861] = { - .class_hid = BNXT_ULP_CLASS_HID_c0cbe, - .class_tid = 3, - .hdr_sig_id = 39, - .flow_sig_id = 98304UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_39_BITMASK_O_UDP_SRC_PORT } - }, - [1862] = { - .class_hid = BNXT_ULP_CLASS_HID_c1f1e, - .class_tid = 3, - .hdr_sig_id = 39, - .flow_sig_id = 98368UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_39_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_39_BITMASK_O_UDP_SRC_PORT } - }, - [1863] = { - .class_hid = BNXT_ULP_CLASS_HID_c1aae, - .class_tid = 3, - .hdr_sig_id = 39, - .flow_sig_id = 114688UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_39_BITMASK_O_UDP_SRC_PORT } - }, - [1864] = { - .class_hid = BNXT_ULP_CLASS_HID_c150e, - .class_tid = 3, - .hdr_sig_id = 39, - .flow_sig_id = 114752UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_39_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_39_BITMASK_O_UDP_SRC_PORT } - }, - [1865] = { - .class_hid = BNXT_ULP_CLASS_HID_a0dfc, - .class_tid = 3, - .hdr_sig_id = 39, - .flow_sig_id = 163840UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_39_BITMASK_O_UDP_DST_PORT } - }, - [1866] = { - .class_hid = BNXT_ULP_CLASS_HID_a185c, - .class_tid = 3, - .hdr_sig_id = 39, - .flow_sig_id = 163904UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_39_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_39_BITMASK_O_UDP_DST_PORT } - }, - [1867] = { - .class_hid = BNXT_ULP_CLASS_HID_a1bec, - .class_tid = 3, - .hdr_sig_id = 39, - .flow_sig_id = 180224UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_39_BITMASK_O_UDP_DST_PORT } - }, - [1868] = { - .class_hid = BNXT_ULP_CLASS_HID_a164c, - .class_tid = 3, - .hdr_sig_id = 39, - .flow_sig_id = 180288UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_39_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_39_BITMASK_O_UDP_DST_PORT } - }, - [1869] = { - .class_hid = BNXT_ULP_CLASS_HID_e0378, - .class_tid = 3, - .hdr_sig_id = 39, - .flow_sig_id = 229376UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_39_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_3_39_BITMASK_O_UDP_DST_PORT } - }, - [1870] = { - .class_hid = BNXT_ULP_CLASS_HID_e1dd8, - .class_tid = 3, - .hdr_sig_id = 39, - .flow_sig_id = 229440UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_39_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_39_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_3_39_BITMASK_O_UDP_DST_PORT } - }, - [1871] = { - .class_hid = BNXT_ULP_CLASS_HID_e1968, - .class_tid = 3, - .hdr_sig_id = 39, - .flow_sig_id = 245760UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_39_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_3_39_BITMASK_O_UDP_DST_PORT } - }, - [1872] = { - .class_hid = BNXT_ULP_CLASS_HID_e0baa, - .class_tid = 3, - .hdr_sig_id = 39, - .flow_sig_id = 245824UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_39_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_3_39_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_3_39_BITMASK_O_UDP_DST_PORT } - }, - [1873] = { - .class_hid = BNXT_ULP_CLASS_HID_20af8, - .class_tid = 3, - .hdr_sig_id = 40, - .flow_sig_id = 131072UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_DST_ADDR } - }, - [1874] = { - .class_hid = BNXT_ULP_CLASS_HID_20558, - .class_tid = 3, - .hdr_sig_id = 40, - .flow_sig_id = 131136UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_40_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_DST_ADDR } - }, - [1875] = { - .class_hid = BNXT_ULP_CLASS_HID_6087c, - .class_tid = 3, - .hdr_sig_id = 40, - .flow_sig_id = 196608UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_DST_ADDR } - }, - [1876] = { - .class_hid = BNXT_ULP_CLASS_HID_61adc, - .class_tid = 3, - .hdr_sig_id = 40, - .flow_sig_id = 196672UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_40_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_DST_ADDR } - }, - [1877] = { - .class_hid = BNXT_ULP_CLASS_HID_31a68, - .class_tid = 3, - .hdr_sig_id = 40, - .flow_sig_id = 393216UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_40_BITMASK_O_UDP_SRC_PORT } + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xB000000000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [82] = 2, + [84] = 3, + [86] = 4, + [88] = 5, + [90] = 6, + [92] = 7, + [94] = 8, + [96] = 9, + [98] = 10, + }, }, - [1878] = { - .class_hid = BNXT_ULP_CLASS_HID_314c8, - .class_tid = 3, - .hdr_sig_id = 40, - .flow_sig_id = 393280UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + [131] = { + .app_id = 0, + .hdr_bitmap = { .bits = BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_40_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_40_BITMASK_O_UDP_SRC_PORT } + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xB000000000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [100] = 2, + [102] = 3, + [104] = 4, + [106] = 5, + }, }, - [1879] = { - .class_hid = BNXT_ULP_CLASS_HID_71fec, - .class_tid = 3, - .hdr_sig_id = 40, - .flow_sig_id = 458752UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = + [132] = { + .app_id = 0, + .hdr_bitmap = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_40_BITMASK_O_UDP_SRC_PORT } + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBE00000000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [82] = 5, + [84] = 6, + [86] = 7, + [88] = 8, + [90] = 9, + [92] = 10, + [94] = 11, + [96] = 12, + [98] = 13, + }, }, - [1880] = { - .class_hid = BNXT_ULP_CLASS_HID_70a2e, - .class_tid = 3, - .hdr_sig_id = 40, - .flow_sig_id = 458816UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = + [133] = { + .app_id = 0, + .hdr_bitmap = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_40_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_40_BITMASK_O_UDP_SRC_PORT } + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBE00000000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [100] = 5, + [102] = 6, + [104] = 7, + [106] = 8, + }, }, - [1881] = { - .class_hid = BNXT_ULP_CLASS_HID_282b0, - .class_tid = 3, - .hdr_sig_id = 40, - .flow_sig_id = 655360UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | + [134] = { + .app_id = 0, + .hdr_bitmap = { .bits = BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_40_BITMASK_O_UDP_DST_PORT } + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x9600000000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [82] = 5, + [84] = 6, + [86] = 7, + [88] = 8, + [90] = 9, + [92] = 10, + [94] = 11, + [96] = 12, + [98] = 13, + [108] = 2, + [112] = 3, + [116] = 4, + }, }, - [1882] = { - .class_hid = BNXT_ULP_CLASS_HID_29d10, - .class_tid = 3, - .hdr_sig_id = 40, - .flow_sig_id = 655424UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | + [135] = { + .app_id = 0, + .hdr_bitmap = { .bits = BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_40_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_40_BITMASK_O_UDP_DST_PORT } + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x9600000000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [100] = 5, + [102] = 6, + [104] = 7, + [106] = 8, + [108] = 2, + [112] = 3, + [116] = 4, + }, }, - [1883] = { - .class_hid = BNXT_ULP_CLASS_HID_68034, - .class_tid = 3, - .hdr_sig_id = 40, - .flow_sig_id = 720896UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = + [136] = { + .app_id = 0, + .hdr_bitmap = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_40_BITMASK_O_UDP_DST_PORT } + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBAC0000000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [82] = 8, + [84] = 9, + [86] = 10, + [88] = 11, + [90] = 12, + [92] = 13, + [94] = 14, + [96] = 15, + [98] = 16, + [108] = 5, + [112] = 6, + [116] = 7, + }, }, - [1884] = { - .class_hid = BNXT_ULP_CLASS_HID_69294, - .class_tid = 3, - .hdr_sig_id = 40, - .flow_sig_id = 720960UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = + [137] = { + .app_id = 0, + .hdr_bitmap = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_40_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_40_BITMASK_O_UDP_DST_PORT } + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBAC0000000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [100] = 8, + [102] = 9, + [104] = 10, + [106] = 11, + [108] = 5, + [112] = 6, + [116] = 7, + }, }, - [1885] = { - .class_hid = BNXT_ULP_CLASS_HID_39220, - .class_tid = 3, - .hdr_sig_id = 40, - .flow_sig_id = 917504UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + [138] = { + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x9600000000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [82] = 5, + [84] = 6, + [86] = 7, + [88] = 8, + [90] = 9, + [92] = 10, + [94] = 11, + [96] = 12, + [98] = 13, + [109] = 2, + [113] = 3, + [117] = 4, + }, + }, + [139] = { + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_OI_VLAN | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_40_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_3_40_BITMASK_O_UDP_DST_PORT } + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x9600000000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [100] = 5, + [102] = 6, + [104] = 7, + [106] = 8, + [109] = 2, + [113] = 3, + [117] = 4, + }, }, - [1886] = { - .class_hid = BNXT_ULP_CLASS_HID_38c62, - .class_tid = 3, - .hdr_sig_id = 40, - .flow_sig_id = 917568UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = + [140] = { + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBAC0000000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [82] = 8, + [84] = 9, + [86] = 10, + [88] = 11, + [90] = 12, + [92] = 13, + [94] = 14, + [96] = 15, + [98] = 16, + [109] = 5, + [113] = 6, + [117] = 7, + }, + }, + [141] = { + .app_id = 0, + .hdr_bitmap = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_OI_VLAN | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_40_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_40_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_3_40_BITMASK_O_UDP_DST_PORT } + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBAC0000000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [100] = 8, + [102] = 9, + [104] = 10, + [106] = 11, + [109] = 5, + [113] = 6, + [117] = 7, + }, }, - [1887] = { - .class_hid = BNXT_ULP_CLASS_HID_797a4, - .class_tid = 3, - .hdr_sig_id = 40, - .flow_sig_id = 983040UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | + [142] = { + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x92C0000000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [82] = 8, + [84] = 9, + [86] = 10, + [88] = 11, + [90] = 12, + [92] = 13, + [94] = 14, + [96] = 15, + [98] = 16, + [108] = 2, + [109] = 5, + [112] = 3, + [113] = 6, + [116] = 4, + [117] = 7, + }, + }, + [143] = { + .app_id = 0, + .hdr_bitmap = { .bits = BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_OI_VLAN | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_40_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_3_40_BITMASK_O_UDP_DST_PORT } + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x92C0000000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [100] = 8, + [102] = 9, + [104] = 10, + [106] = 11, + [108] = 2, + [109] = 5, + [112] = 3, + [113] = 6, + [116] = 4, + [117] = 7, + }, }, - [1888] = { - .class_hid = BNXT_ULP_CLASS_HID_781e6, - .class_tid = 3, - .hdr_sig_id = 40, - .flow_sig_id = 983104UL, - .flow_pattern_id = 1, - .app_sig = 0, - .hdr_sig = { .bits = + [144] = { + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBA58000000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [82] = 11, + [84] = 12, + [86] = 13, + [88] = 14, + [90] = 15, + [92] = 16, + [94] = 17, + [96] = 18, + [98] = 19, + [108] = 5, + [109] = 8, + [112] = 6, + [113] = 9, + [116] = 7, + [117] = 10, + }, + }, + [145] = { + .app_id = 0, + .hdr_bitmap = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_OI_VLAN | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_40_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_3_40_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_3_40_BITMASK_O_UDP_DST_PORT } + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBA58000000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [100] = 11, + [102] = 12, + [104] = 13, + [106] = 14, + [108] = 5, + [109] = 8, + [112] = 6, + [113] = 9, + [116] = 7, + [117] = 10, + }, }, - [1889] = { - .class_hid = BNXT_ULP_CLASS_HID_0f05, - .class_tid = 3, - .hdr_sig_id = 29, - .flow_sig_id = 4UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_29_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_29_BITMASK_O_ETH_SMAC } + [146] = { + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x93F0000000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [52] = 2, + [54] = 3, + [56] = 4, + [58] = 5, + [60] = 6, + [62] = 7, + [64] = 8, + [66] = 9, + [82] = 10, + [84] = 11, + [86] = 12, + [88] = 13, + [90] = 14, + [92] = 15, + [94] = 16, + [96] = 17, + [98] = 18, + }, }, - [1890] = { - .class_hid = BNXT_ULP_CLASS_HID_0f09, - .class_tid = 3, - .hdr_sig_id = 30, - .flow_sig_id = 4UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_30_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_30_BITMASK_O_ETH_SMAC } + [147] = { + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x91BC000000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [32] = 2, + [34] = 3, + [36] = 4, + [38] = 5, + [40] = 6, + [42] = 7, + [44] = 8, + [46] = 9, + [48] = 10, + [50] = 11, + [82] = 12, + [84] = 13, + [86] = 14, + [88] = 15, + [90] = 16, + [92] = 17, + [94] = 18, + [96] = 19, + [98] = 20, + }, }, - [1891] = { - .class_hid = BNXT_ULP_CLASS_HID_0f06, - .class_tid = 3, - .hdr_sig_id = 31, - .flow_sig_id = 4UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | + [148] = { + .app_id = 0, + .hdr_bitmap = { .bits = BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_31_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_31_BITMASK_O_ETH_SMAC } + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x93F0000000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [52] = 2, + [54] = 3, + [56] = 4, + [58] = 5, + [60] = 6, + [62] = 7, + [64] = 8, + [66] = 9, + [100] = 10, + [102] = 11, + [104] = 12, + [106] = 13, + }, }, - [1892] = { - .class_hid = BNXT_ULP_CLASS_HID_19a6, - .class_tid = 3, - .hdr_sig_id = 31, - .flow_sig_id = 68UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_31_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_31_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_31_BITMASK_OO_VLAN_VID } + [149] = { + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x91BC000000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [32] = 2, + [34] = 3, + [36] = 4, + [38] = 5, + [40] = 6, + [42] = 7, + [44] = 8, + [46] = 9, + [48] = 10, + [50] = 11, + [100] = 12, + [102] = 13, + [104] = 14, + [106] = 15, + }, }, - [1893] = { - .class_hid = BNXT_ULP_CLASS_HID_0f0a, - .class_tid = 3, - .hdr_sig_id = 32, - .flow_sig_id = 4UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_32_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_32_BITMASK_O_ETH_SMAC } + [150] = { + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBA7E000000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [52] = 5, + [54] = 6, + [56] = 7, + [58] = 8, + [60] = 9, + [62] = 10, + [64] = 11, + [66] = 12, + [82] = 13, + [84] = 14, + [86] = 15, + [88] = 16, + [90] = 17, + [92] = 18, + [94] = 19, + [96] = 20, + [98] = 21, + }, }, - [1894] = { - .class_hid = BNXT_ULP_CLASS_HID_19aa, - .class_tid = 3, - .hdr_sig_id = 32, - .flow_sig_id = 68UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_32_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_32_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_32_BITMASK_OO_VLAN_VID } + [151] = { + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBA37800000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [32] = 5, + [34] = 6, + [36] = 7, + [38] = 8, + [40] = 9, + [42] = 10, + [44] = 11, + [46] = 12, + [48] = 13, + [50] = 14, + [82] = 15, + [84] = 16, + [86] = 17, + [88] = 18, + [90] = 19, + [92] = 20, + [94] = 21, + [96] = 22, + [98] = 23, + }, }, - [1895] = { - .class_hid = BNXT_ULP_CLASS_HID_0f15, - .class_tid = 3, - .hdr_sig_id = 33, - .flow_sig_id = 4UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = + [152] = { + .app_id = 0, + .hdr_bitmap = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_33_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_33_BITMASK_O_ETH_SMAC } + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBA7E000000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [52] = 5, + [54] = 6, + [56] = 7, + [58] = 8, + [60] = 9, + [62] = 10, + [64] = 11, + [66] = 12, + [100] = 13, + [102] = 14, + [104] = 15, + [106] = 16, + }, }, - [1896] = { - .class_hid = BNXT_ULP_CLASS_HID_0f19, - .class_tid = 3, - .hdr_sig_id = 34, - .flow_sig_id = 4UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_34_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_34_BITMASK_O_ETH_SMAC } + [153] = { + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBA37800000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [32] = 5, + [34] = 6, + [36] = 7, + [38] = 8, + [40] = 9, + [42] = 10, + [44] = 11, + [46] = 12, + [48] = 13, + [50] = 14, + [100] = 15, + [102] = 16, + [104] = 17, + [106] = 18, + }, }, - [1897] = { - .class_hid = BNXT_ULP_CLASS_HID_0f65, - .class_tid = 3, - .hdr_sig_id = 35, - .flow_sig_id = 4UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_35_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_35_BITMASK_O_ETH_SMAC } + [154] = { + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x927E000000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [52] = 5, + [54] = 6, + [56] = 7, + [58] = 8, + [60] = 9, + [62] = 10, + [64] = 11, + [66] = 12, + [82] = 13, + [84] = 14, + [86] = 15, + [88] = 16, + [90] = 17, + [92] = 18, + [94] = 19, + [96] = 20, + [98] = 21, + [108] = 2, + [112] = 3, + [116] = 4, + }, }, - [1898] = { - .class_hid = BNXT_ULP_CLASS_HID_0f69, - .class_tid = 3, - .hdr_sig_id = 36, - .flow_sig_id = 4UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_36_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_36_BITMASK_O_ETH_SMAC } + [155] = { + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x9237800000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [32] = 5, + [34] = 6, + [36] = 7, + [38] = 8, + [40] = 9, + [42] = 10, + [44] = 11, + [46] = 12, + [48] = 13, + [50] = 14, + [82] = 15, + [84] = 16, + [86] = 17, + [88] = 18, + [90] = 19, + [92] = 20, + [94] = 21, + [96] = 22, + [98] = 23, + [108] = 2, + [112] = 3, + [116] = 4, + }, }, - [1899] = { - .class_hid = BNXT_ULP_CLASS_HID_0f16, - .class_tid = 3, - .hdr_sig_id = 37, - .flow_sig_id = 4UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | + [156] = { + .app_id = 0, + .hdr_bitmap = { .bits = BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_37_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_37_BITMASK_O_ETH_SMAC } + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x927E000000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [52] = 5, + [54] = 6, + [56] = 7, + [58] = 8, + [60] = 9, + [62] = 10, + [64] = 11, + [66] = 12, + [100] = 13, + [102] = 14, + [104] = 15, + [106] = 16, + [108] = 2, + [112] = 3, + [116] = 4, + }, }, - [1900] = { - .class_hid = BNXT_ULP_CLASS_HID_19b6, - .class_tid = 3, - .hdr_sig_id = 37, - .flow_sig_id = 68UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV6 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_37_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_37_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_37_BITMASK_OO_VLAN_VID } + [157] = { + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x9237800000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [32] = 5, + [34] = 6, + [36] = 7, + [38] = 8, + [40] = 9, + [42] = 10, + [44] = 11, + [46] = 12, + [48] = 13, + [50] = 14, + [100] = 15, + [102] = 16, + [104] = 17, + [106] = 18, + [108] = 2, + [112] = 3, + [116] = 4, + }, }, - [1901] = { - .class_hid = BNXT_ULP_CLASS_HID_0f1a, - .class_tid = 3, - .hdr_sig_id = 38, - .flow_sig_id = 4UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_38_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_38_BITMASK_O_ETH_SMAC } + [158] = { + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBA4FC00000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [52] = 8, + [54] = 9, + [56] = 10, + [58] = 11, + [60] = 12, + [62] = 13, + [64] = 14, + [66] = 15, + [82] = 16, + [84] = 17, + [86] = 18, + [88] = 19, + [90] = 20, + [92] = 21, + [94] = 22, + [96] = 23, + [98] = 24, + [108] = 5, + [112] = 6, + [116] = 7, + }, }, - [1902] = { - .class_hid = BNXT_ULP_CLASS_HID_19ba, - .class_tid = 3, - .hdr_sig_id = 38, - .flow_sig_id = 68UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_TCP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_38_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_38_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_38_BITMASK_OO_VLAN_VID } + [159] = { + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBA46F00000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [32] = 8, + [34] = 9, + [36] = 10, + [38] = 11, + [40] = 12, + [42] = 13, + [44] = 14, + [46] = 15, + [48] = 16, + [50] = 17, + [82] = 18, + [84] = 19, + [86] = 20, + [88] = 21, + [90] = 22, + [92] = 23, + [94] = 24, + [96] = 25, + [98] = 26, + [108] = 5, + [112] = 6, + [116] = 7, + }, }, - [1903] = { - .class_hid = BNXT_ULP_CLASS_HID_0f66, - .class_tid = 3, - .hdr_sig_id = 39, - .flow_sig_id = 4UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = + [160] = { + .app_id = 0, + .hdr_bitmap = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_39_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_39_BITMASK_O_ETH_SMAC } + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBA4FC00000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [52] = 8, + [54] = 9, + [56] = 10, + [58] = 11, + [60] = 12, + [62] = 13, + [64] = 14, + [66] = 15, + [100] = 16, + [102] = 17, + [104] = 18, + [106] = 19, + [108] = 5, + [112] = 6, + [116] = 7, + }, }, - [1904] = { - .class_hid = BNXT_ULP_CLASS_HID_19c6, - .class_tid = 3, - .hdr_sig_id = 39, - .flow_sig_id = 68UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = + [161] = { + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBA46F00000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [32] = 8, + [34] = 9, + [36] = 10, + [38] = 11, + [40] = 12, + [42] = 13, + [44] = 14, + [46] = 15, + [48] = 16, + [50] = 17, + [100] = 18, + [102] = 19, + [104] = 20, + [106] = 21, + [108] = 5, + [112] = 6, + [116] = 7, + }, + }, + [162] = { + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x927E000000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [52] = 5, + [54] = 6, + [56] = 7, + [58] = 8, + [60] = 9, + [62] = 10, + [64] = 11, + [66] = 12, + [82] = 13, + [84] = 14, + [86] = 15, + [88] = 16, + [90] = 17, + [92] = 18, + [94] = 19, + [96] = 20, + [98] = 21, + [109] = 2, + [113] = 3, + [117] = 4, + }, + }, + [163] = { + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x9237800000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [32] = 5, + [34] = 6, + [36] = 7, + [38] = 8, + [40] = 9, + [42] = 10, + [44] = 11, + [46] = 12, + [48] = 13, + [50] = 14, + [82] = 15, + [84] = 16, + [86] = 17, + [88] = 18, + [90] = 19, + [92] = 20, + [94] = 21, + [96] = 22, + [98] = 23, + [109] = 2, + [113] = 3, + [117] = 4, + }, + }, + [164] = { + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x927E000000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [52] = 5, + [54] = 6, + [56] = 7, + [58] = 8, + [60] = 9, + [62] = 10, + [64] = 11, + [66] = 12, + [100] = 13, + [102] = 14, + [104] = 15, + [106] = 16, + [109] = 2, + [113] = 3, + [117] = 4, + }, + }, + [165] = { + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x9237800000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [32] = 5, + [34] = 6, + [36] = 7, + [38] = 8, + [40] = 9, + [42] = 10, + [44] = 11, + [46] = 12, + [48] = 13, + [50] = 14, + [100] = 15, + [102] = 16, + [104] = 17, + [106] = 18, + [109] = 2, + [113] = 3, + [117] = 4, + }, + }, + [166] = { + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBA4FC00000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [52] = 8, + [54] = 9, + [56] = 10, + [58] = 11, + [60] = 12, + [62] = 13, + [64] = 14, + [66] = 15, + [82] = 16, + [84] = 17, + [86] = 18, + [88] = 19, + [90] = 20, + [92] = 21, + [94] = 22, + [96] = 23, + [98] = 24, + [109] = 5, + [113] = 6, + [117] = 7, + }, + }, + [167] = { + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBA46F00000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [32] = 8, + [34] = 9, + [36] = 10, + [38] = 11, + [40] = 12, + [42] = 13, + [44] = 14, + [46] = 15, + [48] = 16, + [50] = 17, + [82] = 18, + [84] = 19, + [86] = 20, + [88] = 21, + [90] = 22, + [92] = 23, + [94] = 24, + [96] = 25, + [98] = 26, + [109] = 5, + [113] = 6, + [117] = 7, + }, + }, + [168] = { + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBA4FC00000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [52] = 8, + [54] = 9, + [56] = 10, + [58] = 11, + [60] = 12, + [62] = 13, + [64] = 14, + [66] = 15, + [100] = 16, + [102] = 17, + [104] = 18, + [106] = 19, + [109] = 5, + [113] = 6, + [117] = 7, + }, + }, + [169] = { + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBA46F00000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [32] = 8, + [34] = 9, + [36] = 10, + [38] = 11, + [40] = 12, + [42] = 13, + [44] = 14, + [46] = 15, + [48] = 16, + [50] = 17, + [100] = 18, + [102] = 19, + [104] = 20, + [106] = 21, + [109] = 5, + [113] = 6, + [117] = 7, + }, + }, + [170] = { + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x924FC00000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [52] = 8, + [54] = 9, + [56] = 10, + [58] = 11, + [60] = 12, + [62] = 13, + [64] = 14, + [66] = 15, + [82] = 16, + [84] = 17, + [86] = 18, + [88] = 19, + [90] = 20, + [92] = 21, + [94] = 22, + [96] = 23, + [98] = 24, + [108] = 2, + [109] = 5, + [112] = 3, + [113] = 6, + [116] = 4, + [117] = 7, + }, + }, + [171] = { + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x9246F00000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [32] = 8, + [34] = 9, + [36] = 10, + [38] = 11, + [40] = 12, + [42] = 13, + [44] = 14, + [46] = 15, + [48] = 16, + [50] = 17, + [82] = 18, + [84] = 19, + [86] = 20, + [88] = 21, + [90] = 22, + [92] = 23, + [94] = 24, + [96] = 25, + [98] = 26, + [108] = 2, + [109] = 5, + [112] = 3, + [113] = 6, + [116] = 4, + [117] = 7, + }, + }, + [172] = { + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x924FC00000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [52] = 8, + [54] = 9, + [56] = 10, + [58] = 11, + [60] = 12, + [62] = 13, + [64] = 14, + [66] = 15, + [100] = 16, + [102] = 17, + [104] = 18, + [106] = 19, + [108] = 2, + [109] = 5, + [112] = 3, + [113] = 6, + [116] = 4, + [117] = 7, + }, + }, + [173] = { + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0x9246F00000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [32] = 8, + [34] = 9, + [36] = 10, + [38] = 11, + [40] = 12, + [42] = 13, + [44] = 14, + [46] = 15, + [48] = 16, + [50] = 17, + [100] = 18, + [102] = 19, + [104] = 20, + [106] = 21, + [108] = 2, + [109] = 5, + [112] = 3, + [113] = 6, + [116] = 4, + [117] = 7, + }, + }, + [174] = { + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBA49F80000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [52] = 11, + [54] = 12, + [56] = 13, + [58] = 14, + [60] = 15, + [62] = 16, + [64] = 17, + [66] = 18, + [82] = 19, + [84] = 20, + [86] = 21, + [88] = 22, + [90] = 23, + [92] = 24, + [94] = 25, + [96] = 26, + [98] = 27, + [108] = 5, + [109] = 8, + [112] = 6, + [113] = 9, + [116] = 7, + [117] = 10, + }, + }, + [175] = { + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBA48DE0000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [32] = 11, + [34] = 12, + [36] = 13, + [38] = 14, + [40] = 15, + [42] = 16, + [44] = 17, + [46] = 18, + [48] = 19, + [50] = 20, + [82] = 21, + [84] = 22, + [86] = 23, + [88] = 24, + [90] = 25, + [92] = 26, + [94] = 27, + [96] = 28, + [98] = 29, + [108] = 5, + [109] = 8, + [112] = 6, + [113] = 9, + [116] = 7, + [117] = 10, + }, + }, + [176] = { + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBA49F80000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [52] = 11, + [54] = 12, + [56] = 13, + [58] = 14, + [60] = 15, + [62] = 16, + [64] = 17, + [66] = 18, + [100] = 19, + [102] = 20, + [104] = 21, + [106] = 22, + [108] = 5, + [109] = 8, + [112] = 6, + [113] = 9, + [116] = 7, + [117] = 10, + }, + }, + [177] = { + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_OI_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xBA48DE0000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 0, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [32] = 11, + [34] = 12, + [36] = 13, + [38] = 14, + [40] = 15, + [42] = 16, + [44] = 17, + [46] = 18, + [48] = 19, + [50] = 20, + [100] = 21, + [102] = 22, + [104] = 23, + [106] = 24, + [108] = 5, + [109] = 8, + [112] = 6, + [113] = 9, + [116] = 7, + [117] = 10, + }, + }, + [178] = { + .app_id = 0, + .hdr_bitmap = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_39_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_39_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_39_BITMASK_OO_VLAN_VID } + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xB01A160000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 1, + .field_list = { + [1] = 1, + [6] = 2, + [7] = 21, + [8] = 3, + [9] = 22, + [10] = 4, + [11] = 23, + [52] = 5, + [54] = 6, + [56] = 7, + [58] = 8, + [60] = 9, + [62] = 10, + [64] = 11, + [66] = 12, + [100] = 13, + [102] = 14, + [104] = 15, + [106] = 16, + [120] = 17, + [121] = 18, + [122] = 19, + [123] = 20, + }, }, - [1905] = { - .class_hid = BNXT_ULP_CLASS_HID_0f6a, - .class_tid = 3, - .hdr_sig_id = 40, - .flow_sig_id = 4UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = - BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_40_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_40_BITMASK_O_ETH_SMAC } + [179] = { + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xB006858000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 1, + .field_list = { + [1] = 1, + [6] = 2, + [7] = 23, + [8] = 3, + [9] = 24, + [10] = 4, + [11] = 25, + [32] = 5, + [34] = 6, + [36] = 7, + [38] = 8, + [40] = 9, + [42] = 10, + [44] = 11, + [46] = 12, + [48] = 13, + [50] = 14, + [100] = 15, + [102] = 16, + [104] = 17, + [106] = 18, + [120] = 19, + [121] = 20, + [122] = 21, + [123] = 22, + }, }, - [1906] = { - .class_hid = BNXT_ULP_CLASS_HID_19ca, - .class_tid = 3, - .hdr_sig_id = 40, - .flow_sig_id = 68UL, - .flow_pattern_id = 2, - .app_sig = 0, - .hdr_sig = { .bits = + [180] = { + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xB01A160300000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 1, + .field_list = { + [1] = 1, + [6] = 2, + [7] = 21, + [8] = 3, + [9] = 22, + [10] = 4, + [11] = 23, + [52] = 5, + [53] = 24, + [54] = 6, + [55] = 25, + [56] = 7, + [57] = 26, + [58] = 8, + [59] = 27, + [60] = 9, + [61] = 28, + [62] = 10, + [63] = 29, + [64] = 11, + [65] = 30, + [66] = 12, + [67] = 31, + [100] = 13, + [102] = 14, + [104] = 15, + [106] = 16, + [120] = 17, + [121] = 18, + [122] = 19, + [123] = 20, + }, + }, + [181] = { + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xB0068580C0000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 1, + .field_list = { + [1] = 1, + [6] = 2, + [7] = 23, + [8] = 3, + [9] = 24, + [10] = 4, + [11] = 25, + [32] = 5, + [34] = 6, + [36] = 7, + [38] = 8, + [40] = 9, + [42] = 10, + [44] = 11, + [46] = 12, + [48] = 13, + [50] = 14, + [53] = 26, + [55] = 27, + [57] = 28, + [59] = 29, + [61] = 30, + [63] = 31, + [65] = 32, + [67] = 33, + [100] = 15, + [102] = 16, + [104] = 17, + [106] = 18, + [120] = 19, + [121] = 20, + [122] = 21, + [123] = 22, + }, + }, + [182] = { + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xB01A1600C0000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 1, + .field_list = { + [1] = 1, + [6] = 2, + [7] = 21, + [8] = 3, + [9] = 22, + [10] = 4, + [11] = 23, + [33] = 24, + [35] = 25, + [37] = 26, + [39] = 27, + [41] = 28, + [43] = 29, + [45] = 30, + [47] = 31, + [49] = 32, + [51] = 33, + [52] = 5, + [54] = 6, + [56] = 7, + [58] = 8, + [60] = 9, + [62] = 10, + [64] = 11, + [66] = 12, + [100] = 13, + [102] = 14, + [104] = 15, + [106] = 16, + [120] = 17, + [121] = 18, + [122] = 19, + [123] = 20, + }, + }, + [183] = { + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xB006858030000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 1, + .field_list = { + [1] = 1, + [6] = 2, + [7] = 23, + [8] = 3, + [9] = 24, + [10] = 4, + [11] = 25, + [32] = 5, + [33] = 26, + [34] = 6, + [35] = 27, + [36] = 7, + [37] = 28, + [38] = 8, + [39] = 29, + [40] = 9, + [41] = 30, + [42] = 10, + [43] = 31, + [44] = 11, + [45] = 32, + [46] = 12, + [47] = 33, + [48] = 13, + [49] = 34, + [50] = 14, + [51] = 35, + [100] = 15, + [102] = 16, + [104] = 17, + [106] = 18, + [120] = 19, + [121] = 20, + [122] = 21, + [123] = 22, + }, + }, + [184] = { + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xB01A16C000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 1, + .field_list = { + [1] = 1, + [6] = 2, + [7] = 21, + [8] = 3, + [9] = 22, + [10] = 4, + [11] = 23, + [52] = 5, + [54] = 6, + [56] = 7, + [58] = 8, + [60] = 9, + [62] = 10, + [64] = 11, + [66] = 12, + [83] = 24, + [85] = 25, + [87] = 26, + [89] = 27, + [91] = 28, + [93] = 29, + [95] = 30, + [97] = 31, + [99] = 32, + [100] = 13, + [102] = 14, + [104] = 15, + [106] = 16, + [120] = 17, + [121] = 18, + [122] = 19, + [123] = 20, + }, + }, + [185] = { + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xB00685B000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 1, + .field_list = { + [1] = 1, + [6] = 2, + [7] = 23, + [8] = 3, + [9] = 24, + [10] = 4, + [11] = 25, + [32] = 5, + [34] = 6, + [36] = 7, + [38] = 8, + [40] = 9, + [42] = 10, + [44] = 11, + [46] = 12, + [48] = 13, + [50] = 14, + [83] = 26, + [85] = 27, + [87] = 28, + [89] = 29, + [91] = 30, + [93] = 31, + [95] = 32, + [97] = 33, + [99] = 34, + [100] = 15, + [102] = 16, + [104] = 17, + [106] = 18, + [120] = 19, + [121] = 20, + [122] = 21, + [123] = 22, + }, + }, + [186] = { + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xB01A16C000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 1, + .field_list = { + [1] = 1, + [6] = 2, + [7] = 21, + [8] = 3, + [9] = 22, + [10] = 4, + [11] = 23, + [52] = 5, + [54] = 6, + [56] = 7, + [58] = 8, + [60] = 9, + [62] = 10, + [64] = 11, + [66] = 12, + [100] = 13, + [101] = 24, + [102] = 14, + [103] = 25, + [104] = 15, + [105] = 26, + [106] = 16, + [107] = 27, + [120] = 17, + [121] = 18, + [122] = 19, + [123] = 20, + }, + }, + [187] = { + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xB00685B000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 1, + .field_list = { + [1] = 1, + [6] = 2, + [7] = 23, + [8] = 3, + [9] = 24, + [10] = 4, + [11] = 25, + [32] = 5, + [34] = 6, + [36] = 7, + [38] = 8, + [40] = 9, + [42] = 10, + [44] = 11, + [46] = 12, + [48] = 13, + [50] = 14, + [100] = 15, + [101] = 26, + [102] = 16, + [103] = 27, + [104] = 17, + [105] = 28, + [106] = 18, + [107] = 29, + [120] = 19, + [121] = 20, + [122] = 21, + [123] = 22, + }, + }, + [188] = { + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV6 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xB01A1603C0000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 1, + .field_list = { + [1] = 1, + [6] = 2, + [7] = 21, + [8] = 3, + [9] = 22, + [10] = 4, + [11] = 23, + [52] = 5, + [53] = 24, + [54] = 6, + [55] = 25, + [56] = 7, + [57] = 26, + [58] = 8, + [59] = 27, + [60] = 9, + [61] = 28, + [62] = 10, + [63] = 29, + [64] = 11, + [65] = 30, + [66] = 12, + [67] = 31, + [83] = 32, + [85] = 33, + [87] = 34, + [89] = 35, + [91] = 36, + [93] = 37, + [95] = 38, + [97] = 39, + [99] = 40, + [100] = 13, + [102] = 14, + [104] = 15, + [106] = 16, + [120] = 17, + [121] = 18, + [122] = 19, + [123] = 20, + }, + }, + [189] = { + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV6 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xB0068580F0000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 1, + .field_list = { + [1] = 1, + [6] = 2, + [7] = 23, + [8] = 3, + [9] = 24, + [10] = 4, + [11] = 25, + [32] = 5, + [34] = 6, + [36] = 7, + [38] = 8, + [40] = 9, + [42] = 10, + [44] = 11, + [46] = 12, + [48] = 13, + [50] = 14, + [53] = 26, + [55] = 27, + [57] = 28, + [59] = 29, + [61] = 30, + [63] = 31, + [65] = 32, + [67] = 33, + [83] = 34, + [85] = 35, + [87] = 36, + [89] = 37, + [91] = 38, + [93] = 39, + [95] = 40, + [97] = 41, + [99] = 42, + [100] = 15, + [102] = 16, + [104] = 17, + [106] = 18, + [120] = 19, + [121] = 20, + [122] = 21, + [123] = 22, + }, + }, + [190] = { + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xB01A1600F0000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 1, + .field_list = { + [1] = 1, + [6] = 2, + [7] = 21, + [8] = 3, + [9] = 22, + [10] = 4, + [11] = 23, + [33] = 24, + [35] = 25, + [37] = 26, + [39] = 27, + [41] = 28, + [43] = 29, + [45] = 30, + [47] = 31, + [49] = 32, + [51] = 33, + [52] = 5, + [54] = 6, + [56] = 7, + [58] = 8, + [60] = 9, + [62] = 10, + [64] = 11, + [66] = 12, + [83] = 34, + [85] = 35, + [87] = 36, + [89] = 37, + [91] = 38, + [93] = 39, + [95] = 40, + [97] = 41, + [99] = 42, + [100] = 13, + [102] = 14, + [104] = 15, + [106] = 16, + [120] = 17, + [121] = 18, + [122] = 19, + [123] = 20, + }, + }, + [191] = { + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xB00685803C000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 1, + .field_list = { + [1] = 1, + [6] = 2, + [7] = 23, + [8] = 3, + [9] = 24, + [10] = 4, + [11] = 25, + [32] = 5, + [33] = 26, + [34] = 6, + [35] = 27, + [36] = 7, + [37] = 28, + [38] = 8, + [39] = 29, + [40] = 9, + [41] = 30, + [42] = 10, + [43] = 31, + [44] = 11, + [45] = 32, + [46] = 12, + [47] = 33, + [48] = 13, + [49] = 34, + [50] = 14, + [51] = 35, + [83] = 36, + [85] = 37, + [87] = 38, + [89] = 39, + [91] = 40, + [93] = 41, + [95] = 42, + [97] = 43, + [99] = 44, + [100] = 15, + [102] = 16, + [104] = 17, + [106] = 18, + [120] = 19, + [121] = 20, + [122] = 21, + [123] = 22, + }, + }, + [192] = { + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV6 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xB01A1603C0000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 1, + .field_list = { + [1] = 1, + [6] = 2, + [7] = 21, + [8] = 3, + [9] = 22, + [10] = 4, + [11] = 23, + [52] = 5, + [53] = 24, + [54] = 6, + [55] = 25, + [56] = 7, + [57] = 26, + [58] = 8, + [59] = 27, + [60] = 9, + [61] = 28, + [62] = 10, + [63] = 29, + [64] = 11, + [65] = 30, + [66] = 12, + [67] = 31, + [100] = 13, + [101] = 32, + [102] = 14, + [103] = 33, + [104] = 15, + [105] = 34, + [106] = 16, + [107] = 35, + [120] = 17, + [121] = 18, + [122] = 19, + [123] = 20, + }, + }, + [193] = { + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV6 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xB0068580F0000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 1, + .field_list = { + [1] = 1, + [6] = 2, + [7] = 23, + [8] = 3, + [9] = 24, + [10] = 4, + [11] = 25, + [32] = 5, + [34] = 6, + [36] = 7, + [38] = 8, + [40] = 9, + [42] = 10, + [44] = 11, + [46] = 12, + [48] = 13, + [50] = 14, + [53] = 26, + [55] = 27, + [57] = 28, + [59] = 29, + [61] = 30, + [63] = 31, + [65] = 32, + [67] = 33, + [100] = 15, + [101] = 34, + [102] = 16, + [103] = 35, + [104] = 17, + [105] = 36, + [106] = 18, + [107] = 37, + [120] = 19, + [121] = 20, + [122] = 21, + [123] = 22, + }, + }, + [194] = { + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xB01A1600F0000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 1, + .field_list = { + [1] = 1, + [6] = 2, + [7] = 21, + [8] = 3, + [9] = 22, + [10] = 4, + [11] = 23, + [33] = 24, + [35] = 25, + [37] = 26, + [39] = 27, + [41] = 28, + [43] = 29, + [45] = 30, + [47] = 31, + [49] = 32, + [51] = 33, + [52] = 5, + [54] = 6, + [56] = 7, + [58] = 8, + [60] = 9, + [62] = 10, + [64] = 11, + [66] = 12, + [100] = 13, + [101] = 34, + [102] = 14, + [103] = 35, + [104] = 15, + [105] = 36, + [106] = 16, + [107] = 37, + [120] = 17, + [121] = 18, + [122] = 19, + [123] = 20, + }, + }, + [195] = { + .app_id = 0, + .hdr_bitmap = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xB00685803C000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 1, + .field_list = { + [1] = 1, + [6] = 2, + [7] = 23, + [8] = 3, + [9] = 24, + [10] = 4, + [11] = 25, + [32] = 5, + [33] = 26, + [34] = 6, + [35] = 27, + [36] = 7, + [37] = 28, + [38] = 8, + [39] = 29, + [40] = 9, + [41] = 30, + [42] = 10, + [43] = 31, + [44] = 11, + [45] = 32, + [46] = 12, + [47] = 33, + [48] = 13, + [49] = 34, + [50] = 14, + [51] = 35, + [100] = 15, + [101] = 36, + [102] = 16, + [103] = 37, + [104] = 17, + [105] = 38, + [106] = 18, + [107] = 39, + [120] = 19, + [121] = 20, + [122] = 21, + [123] = 22, + }, + }, + [196] = { + .app_id = 0, + .hdr_bitmap = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_OO_VLAN | BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_GENEVE | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .field_sig = { .bits = - BNXT_ULP_HF_0_3_40_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_3_40_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_3_40_BITMASK_OO_VLAN_VID } + .field_man_bitmap = 0x0, + .field_opt_bitmap = 0xB002800000000000, + .field_exclude_bitmap = 0x0, + .class_tid = 2, + .flow_pattern_id = 2, + .field_list = { + [1] = 1, + [6] = 2, + [8] = 3, + [10] = 4, + [32] = 5, + [34] = 6, + [36] = 7, + [38] = 8, + [40] = 9, + [42] = 10, + [44] = 11, + [46] = 12, + [48] = 13, + [50] = 14, + [100] = 15, + [102] = 16, + [104] = 17, + [106] = 18, + }, } }; diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h index ad42c12887..9944d93739 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h @@ -6,61 +6,70 @@ #ifndef ULP_TEMPLATE_DB_H_ #define ULP_TEMPLATE_DB_H_ -#define BNXT_ULP_REGFILE_MAX_SZ 67 -#define BNXT_ULP_MAX_NUM_DEVICES 4 -#define BNXT_ULP_LOG2_MAX_NUM_DEV 2 -#define BNXT_ULP_GEN_TBL_MAX_SZ 40 -#define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 1048576 -#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 1907 -#define BNXT_ULP_CLASS_HID_LOW_PRIME 4049 -#define BNXT_ULP_CLASS_HID_HIGH_PRIME 7919 -#define BNXT_ULP_CLASS_HID_SHFTR 29 -#define BNXT_ULP_CLASS_HID_SHFTL 28 -#define BNXT_ULP_CLASS_HID_MASK 1048575 -#define BNXT_ULP_ACT_SIG_TBL_MAX_SZ 262144 -#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 724 -#define BNXT_ULP_ACT_HID_LOW_PRIME 7919 -#define BNXT_ULP_ACT_HID_HIGH_PRIME 7919 -#define BNXT_ULP_ACT_HID_SHFTR 25 -#define BNXT_ULP_ACT_HID_SHFTL 30 -#define BNXT_ULP_ACT_HID_MASK 262143 +#define BNXT_ULP_REGFILE_MAX_SZ 74 +#define BNXT_ULP_MAX_NUM_DEVICES 5 +#define BNXT_ULP_LOG2_MAX_NUM_DEV 2.32192809488736 +#define BNXT_ULP_GEN_TBL_MAX_SZ 50 +#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 197 +#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 17 #define BNXT_ULP_APP_RESOURCE_RESV_LIST_MAX_SZ 0 -#define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 51 +#define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 57 #define BNXT_ULP_APP_GLB_RESOURCE_TBL_MAX_SZ 0 #define BNXT_ULP_RESOURCE_RESV_LIST_MAX_SZ 73 -#define BNXT_ULP_APP_CAP_TBL_MAX_SZ 2 +#define BNXT_ULP_APP_CAP_TBL_MAX_SZ 3 #define BNXT_ULP_COND_GOTO_REJECT 1023 #define BNXT_ULP_COND_GOTO_RF 0x10000 -#define BNXT_ULP_GLB_FIELD_TBL_SHIFT 7 -#define BNXT_ULP_HDR_SIG_ID_SHIFT 6 #define BNXT_ULP_APP_ID_CONFIG 0 -#define BNXT_ULP_APP_ID_SHIFT 4 -#define BNXT_ULP_GLB_FIELD_TBL_SIZE 29805 +#define BNXT_ULP_GLB_FIELD_TBL_SIZE 129 #define BNXT_ULP_GLB_SIG_TBL_SIZE 1 -#define ULP_WH_PLUS_CLASS_TMPL_LIST_SIZE 6 -#define ULP_WH_PLUS_CLASS_TBL_LIST_SIZE 94 -#define ULP_WH_PLUS_CLASS_KEY_INFO_LIST_SIZE 690 +#define ULP_WH_PLUS_CLASS_TMPL_LIST_SIZE 5 +#define ULP_WH_PLUS_CLASS_TBL_LIST_SIZE 95 +#define ULP_WH_PLUS_CLASS_KEY_INFO_LIST_SIZE 696 +#define ULP_WH_PLUS_CLASS_KEY_EXT_LIST_SIZE 0 #define ULP_WH_PLUS_CLASS_IDENT_LIST_SIZE 29 -#define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 664 -#define ULP_WH_PLUS_CLASS_COND_LIST_SIZE 49 -#define ULP_THOR_CLASS_TMPL_LIST_SIZE 6 -#define ULP_THOR_CLASS_TBL_LIST_SIZE 124 -#define ULP_THOR_CLASS_KEY_INFO_LIST_SIZE 2514 -#define ULP_THOR_CLASS_IDENT_LIST_SIZE 38 -#define ULP_THOR_CLASS_RESULT_FIELD_LIST_SIZE 1521 -#define ULP_THOR_CLASS_COND_LIST_SIZE 55 +#define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 670 +#define ULP_WH_PLUS_CLASS_COND_LIST_SIZE 50 +#define ULP_WH_PLUS_CLASS_COND_OPER_LIST_SIZE 0 +#define ULP_THOR_CLASS_TMPL_LIST_SIZE 5 +#define ULP_THOR_CLASS_TBL_LIST_SIZE 108 +#define ULP_THOR_CLASS_KEY_INFO_LIST_SIZE 578 +#define ULP_THOR_CLASS_KEY_EXT_LIST_SIZE 562 +#define ULP_THOR_CLASS_IDENT_LIST_SIZE 33 +#define ULP_THOR_CLASS_RESULT_FIELD_LIST_SIZE 1252 +#define ULP_THOR_CLASS_COND_LIST_SIZE 2963 +#define ULP_THOR_CLASS_COND_OPER_LIST_SIZE 0 +#define ULP_THOR2_CLASS_TMPL_LIST_SIZE 5 +#define ULP_THOR2_CLASS_TBL_LIST_SIZE 107 +#define ULP_THOR2_CLASS_KEY_INFO_LIST_SIZE 683 +#define ULP_THOR2_CLASS_KEY_EXT_LIST_SIZE 590 +#define ULP_THOR2_CLASS_IDENT_LIST_SIZE 43 +#define ULP_THOR2_CLASS_RESULT_FIELD_LIST_SIZE 1538 +#define ULP_THOR2_CLASS_COND_LIST_SIZE 3188 +#define ULP_THOR2_CLASS_COND_OPER_LIST_SIZE 0 #define ULP_WH_PLUS_ACT_TMPL_LIST_SIZE 11 #define ULP_WH_PLUS_ACT_TBL_LIST_SIZE 154 -#define ULP_WH_PLUS_ACT_KEY_INFO_LIST_SIZE 45 +#define ULP_WH_PLUS_ACT_KEY_INFO_LIST_SIZE 49 +#define ULP_WH_PLUS_ACT_KEY_EXT_LIST_SIZE 0 #define ULP_WH_PLUS_ACT_IDENT_LIST_SIZE 20 #define ULP_WH_PLUS_ACT_RESULT_FIELD_LIST_SIZE 995 -#define ULP_WH_PLUS_ACT_COND_LIST_SIZE 121 +#define ULP_WH_PLUS_ACT_COND_LIST_SIZE 134 +#define ULP_WH_PLUS_ACT_COND_OPER_LIST_SIZE 6 #define ULP_THOR_ACT_TMPL_LIST_SIZE 11 -#define ULP_THOR_ACT_TBL_LIST_SIZE 101 -#define ULP_THOR_ACT_KEY_INFO_LIST_SIZE 48 -#define ULP_THOR_ACT_IDENT_LIST_SIZE 21 -#define ULP_THOR_ACT_RESULT_FIELD_LIST_SIZE 798 -#define ULP_THOR_ACT_COND_LIST_SIZE 89 +#define ULP_THOR_ACT_TBL_LIST_SIZE 106 +#define ULP_THOR_ACT_KEY_INFO_LIST_SIZE 84 +#define ULP_THOR_ACT_KEY_EXT_LIST_SIZE 0 +#define ULP_THOR_ACT_IDENT_LIST_SIZE 22 +#define ULP_THOR_ACT_RESULT_FIELD_LIST_SIZE 612 +#define ULP_THOR_ACT_COND_LIST_SIZE 102 +#define ULP_THOR_ACT_COND_OPER_LIST_SIZE 2 +#define ULP_THOR2_ACT_TMPL_LIST_SIZE 11 +#define ULP_THOR2_ACT_TBL_LIST_SIZE 72 +#define ULP_THOR2_ACT_KEY_INFO_LIST_SIZE 53 +#define ULP_THOR2_ACT_KEY_EXT_LIST_SIZE 0 +#define ULP_THOR2_ACT_IDENT_LIST_SIZE 7 +#define ULP_THOR2_ACT_RESULT_FIELD_LIST_SIZE 458 +#define ULP_THOR2_ACT_COND_LIST_SIZE 57 +#define ULP_THOR2_ACT_COND_OPER_LIST_SIZE 0 enum bnxt_ulp_act_bit { BNXT_ULP_ACT_BIT_MARK = 0x0000000000000001, @@ -83,26 +92,41 @@ enum bnxt_ulp_act_bit { BNXT_ULP_ACT_BIT_SET_IPV6_SRC = 0x0000000000020000, BNXT_ULP_ACT_BIT_SET_IPV6_DST = 0x0000000000040000, BNXT_ULP_ACT_BIT_DEC_TTL = 0x0000000000080000, - BNXT_ULP_ACT_BIT_SET_TP_SRC = 0x0000000000100000, - BNXT_ULP_ACT_BIT_SET_TP_DST = 0x0000000000200000, - BNXT_ULP_ACT_BIT_VXLAN_ENCAP = 0x0000000000400000, - BNXT_ULP_ACT_BIT_JUMP = 0x0000000000800000, - BNXT_ULP_ACT_BIT_SHARED = 0x0000000001000000, - BNXT_ULP_ACT_BIT_SAMPLE = 0x0000000002000000, - BNXT_ULP_ACT_BIT_SHARED_SAMPLE = 0x0000000004000000, - BNXT_ULP_ACT_BIT_QUEUE = 0x0000000008000000, - BNXT_ULP_ACT_BIT_DELETE = 0x0000000010000000, - BNXT_ULP_ACT_BIT_UPDATE = 0x0000000020000000, - BNXT_ULP_ACT_BIT_SHARED_METER = 0x0000000040000000, - BNXT_ULP_ACT_BIT_METER_PROFILE = 0x0000000080000000, - BNXT_ULP_ACT_BIT_GOTO_CHAIN = 0x0000000100000000, - BNXT_ULP_ACT_BIT_VF_TO_VF = 0x0000000200000000, - BNXT_ULP_ACT_BIT_IP_ENCAP = 0x0000000400000000, - BNXT_ULP_ACT_BIT_IP_DECAP = 0x0000000800000000, - BNXT_ULP_ACT_BIT_L2_ENCAP = 0x0000001000000000, - BNXT_ULP_ACT_BIT_L2_DECAP = 0x0000002000000000, - BNXT_ULP_ACT_BIT_MULTIPLE_PORT = 0x0000004000000000, - BNXT_ULP_ACT_BIT_LAST = 0x0000008000000000 + BNXT_ULP_ACT_BIT_SET_TTL = 0x0000000000100000, + BNXT_ULP_ACT_BIT_SET_TP_SRC = 0x0000000000200000, + BNXT_ULP_ACT_BIT_SET_TP_DST = 0x0000000000400000, + BNXT_ULP_ACT_BIT_VXLAN_ENCAP = 0x0000000000800000, + BNXT_ULP_ACT_BIT_JUMP = 0x0000000001000000, + BNXT_ULP_ACT_BIT_SHARED = 0x0000000002000000, + BNXT_ULP_ACT_BIT_SAMPLE = 0x0000000004000000, + BNXT_ULP_ACT_BIT_SHARED_SAMPLE = 0x0000000008000000, + BNXT_ULP_ACT_BIT_QUEUE = 0x0000000010000000, + BNXT_ULP_ACT_BIT_DELETE = 0x0000000020000000, + BNXT_ULP_ACT_BIT_UPDATE = 0x0000000040000000, + BNXT_ULP_ACT_BIT_SHARED_METER = 0x0000000080000000, + BNXT_ULP_ACT_BIT_METER_PROFILE = 0x0000000100000000, + BNXT_ULP_ACT_BIT_GOTO_CHAIN = 0x0000000200000000, + BNXT_ULP_ACT_BIT_VF_TO_VF = 0x0000000400000000, + BNXT_ULP_ACT_BIT_IP_ENCAP = 0x0000000800000000, + BNXT_ULP_ACT_BIT_IP_DECAP = 0x0000001000000000, + BNXT_ULP_ACT_BIT_L2_ENCAP = 0x0000002000000000, + BNXT_ULP_ACT_BIT_L2_DECAP = 0x0000004000000000, + BNXT_ULP_ACT_BIT_GENEVE_DECAP = 0x0000008000000000, + BNXT_ULP_ACT_BIT_GENEVE_ENCAP = 0x0000010000000000, + BNXT_ULP_ACT_BIT_MULTIPLE_PORT = 0x0000020000000000, + BNXT_ULP_ACT_BIT_LAST = 0x0000040000000000 +}; + +enum bnxt_ulp_cf_bit { + BNXT_ULP_CF_BIT_IS_TUNNEL = 0x0000000000000001, + BNXT_ULP_CF_BIT_UPAR1 = 0x0000000000000002, + BNXT_ULP_CF_BIT_UPAR2 = 0x0000000000000004, + BNXT_ULP_CF_BIT_L2_CNTXT_ID = 0x0000000000000008, + BNXT_ULP_CF_BIT_RECYCLE_CNT = 0x0000000000000010, + BNXT_ULP_CF_BIT_METADATA = 0x0000000000000020, + BNXT_ULP_CF_BIT_L2_ONLY = 0x0000000000000040, + BNXT_ULP_CF_BIT_DIX_TRAFFIC = 0x0000000000000080, + BNXT_ULP_CF_BIT_LAST = 0x0000000000000100 }; enum bnxt_ulp_hdr_bit { @@ -131,7 +155,11 @@ enum bnxt_ulp_hdr_bit { BNXT_ULP_HDR_BIT_SVIF_IGNORE = 0x0000000000400000, BNXT_ULP_HDR_BIT_O_SRV6 = 0x0000000000800000, BNXT_ULP_HDR_BIT_T_VXLAN_GPE = 0x0000000001000000, - BNXT_ULP_HDR_BIT_LAST = 0x0000000002000000 + BNXT_ULP_HDR_BIT_T_GENEVE = 0x0000000002000000, + BNXT_ULP_HDR_BIT_O_UNTAGGED = 0x0000000004000000, + BNXT_ULP_HDR_BIT_I_UNTAGGED = 0x0000000008000000, + BNXT_ULP_HDR_BIT_NON_TUNNEL = 0x0000000010000000, + BNXT_ULP_HDR_BIT_LAST = 0x0000000020000000 }; enum bnxt_ulp_accept_opc { @@ -187,75 +215,79 @@ enum bnxt_ulp_cf_idx { BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID = 30, BNXT_ULP_CF_IDX_O_L3_PROTO_ID = 31, BNXT_ULP_CF_IDX_I_L3_PROTO_ID = 32, - BNXT_ULP_CF_IDX_DEV_PORT_ID = 33, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF = 34, - BNXT_ULP_CF_IDX_DRV_FUNC_SPIF = 35, - BNXT_ULP_CF_IDX_DRV_FUNC_PARIF = 36, - BNXT_ULP_CF_IDX_DRV_FUNC_VNIC = 37, - BNXT_ULP_CF_IDX_DRV_FUNC_PHY_PORT = 38, - BNXT_ULP_CF_IDX_VF_FUNC_SVIF = 39, - BNXT_ULP_CF_IDX_VF_FUNC_SPIF = 40, - BNXT_ULP_CF_IDX_VF_FUNC_PARIF = 41, - BNXT_ULP_CF_IDX_VF_FUNC_VNIC = 42, - BNXT_ULP_CF_IDX_PHY_PORT_SVIF = 43, - BNXT_ULP_CF_IDX_PHY_PORT_SPIF = 44, - BNXT_ULP_CF_IDX_PHY_PORT_PARIF = 45, - BNXT_ULP_CF_IDX_PHY_PORT_VPORT = 46, - BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG = 47, - BNXT_ULP_CF_IDX_ACT_ENCAP_IPV6_FLAG = 48, - BNXT_ULP_CF_IDX_ACT_DEC_TTL = 49, - BNXT_ULP_CF_IDX_ACT_T_DEC_TTL = 50, - BNXT_ULP_CF_IDX_ACT_PORT_IS_SET = 51, - BNXT_ULP_CF_IDX_ACT_PORT_TYPE = 52, - BNXT_ULP_CF_IDX_MATCH_PORT_TYPE = 53, - BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP = 54, - BNXT_ULP_CF_IDX_MATCH_PORT_IS_PF = 55, - BNXT_ULP_CF_IDX_VF_TO_VF = 56, - BNXT_ULP_CF_IDX_L3_HDR_CNT = 57, - BNXT_ULP_CF_IDX_L4_HDR_CNT = 58, - BNXT_ULP_CF_IDX_VFR_MODE = 59, - BNXT_ULP_CF_IDX_L3_TUN = 60, - BNXT_ULP_CF_IDX_L3_TUN_DECAP = 61, - BNXT_ULP_CF_IDX_FID = 62, - BNXT_ULP_CF_IDX_HDR_SIG_ID = 63, - BNXT_ULP_CF_IDX_FLOW_SIG_ID = 64, - BNXT_ULP_CF_IDX_WC_MATCH = 65, - BNXT_ULP_CF_IDX_WC_IS_HA_HIGH_REG = 66, - BNXT_ULP_CF_IDX_TUNNEL_ID = 67, - BNXT_ULP_CF_IDX_TUN_OFF_DIP_ID = 68, - BNXT_ULP_CF_IDX_TUN_OFF_DMAC_ID = 69, - BNXT_ULP_CF_IDX_OO_VLAN_FB_VID = 70, - BNXT_ULP_CF_IDX_OI_VLAN_FB_VID = 71, - BNXT_ULP_CF_IDX_IO_VLAN_FB_VID = 72, - BNXT_ULP_CF_IDX_II_VLAN_FB_VID = 73, - BNXT_ULP_CF_IDX_SOCKET_DIRECT = 74, - BNXT_ULP_CF_IDX_SOCKET_DIRECT_VPORT = 75, - BNXT_ULP_CF_IDX_TUNNEL_SPORT = 76, - BNXT_ULP_CF_IDX_VF_META_FID = 77, - BNXT_ULP_CF_IDX_DEV_ACT_PORT_ID = 78, - BNXT_ULP_CF_IDX_O_VLAN_NO_IGNORE = 79, - BNXT_ULP_CF_IDX_I_VLAN_NO_IGNORE = 80, - BNXT_ULP_CF_IDX_HA_SUPPORT_DISABLED = 81, - BNXT_ULP_CF_IDX_CHAIN_ID_METADATA = 82, - BNXT_ULP_CF_IDX_SRV6_UPAR_ID = 83, - BNXT_ULP_CF_IDX_SRV6_T_ID = 84, - BNXT_ULP_CF_IDX_GENERIC_SIZE = 85, - BNXT_ULP_CF_IDX_L2_CUSTOM_UPAR_ID = 86, - BNXT_ULP_CF_IDX_CUSTOM_GRE_EN = 87, - BNXT_ULP_CF_IDX_UPAR_HIGH_EN = 88, - BNXT_ULP_CF_IDX_MP_NPORTS = 89, - BNXT_ULP_CF_IDX_MP_PORT_A = 90, - BNXT_ULP_CF_IDX_MP_VNIC_A = 91, - BNXT_ULP_CF_IDX_MP_VPORT_A = 92, - BNXT_ULP_CF_IDX_MP_MDATA_A = 93, - BNXT_ULP_CF_IDX_MP_A_IS_VFREP = 94, - BNXT_ULP_CF_IDX_MP_PORT_B = 95, - BNXT_ULP_CF_IDX_MP_VNIC_B = 96, - BNXT_ULP_CF_IDX_MP_VPORT_B = 97, - BNXT_ULP_CF_IDX_MP_MDATA_B = 98, - BNXT_ULP_CF_IDX_MP_B_IS_VFREP = 99, - BNXT_ULP_CF_IDX_VXLAN_IP_UPAR_ID = 100, - BNXT_ULP_CF_IDX_LAST = 101 + BNXT_ULP_CF_IDX_O_L3_TTL = 33, + BNXT_ULP_CF_IDX_DEV_PORT_ID = 34, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF = 35, + BNXT_ULP_CF_IDX_DRV_FUNC_SPIF = 36, + BNXT_ULP_CF_IDX_DRV_FUNC_PARIF = 37, + BNXT_ULP_CF_IDX_DRV_FUNC_VNIC = 38, + BNXT_ULP_CF_IDX_DRV_FUNC_PHY_PORT = 39, + BNXT_ULP_CF_IDX_VF_FUNC_SVIF = 40, + BNXT_ULP_CF_IDX_VF_FUNC_SPIF = 41, + BNXT_ULP_CF_IDX_VF_FUNC_PARIF = 42, + BNXT_ULP_CF_IDX_VF_FUNC_VNIC = 43, + BNXT_ULP_CF_IDX_VNIC = 44, + BNXT_ULP_CF_IDX_PHY_PORT_SVIF = 45, + BNXT_ULP_CF_IDX_PHY_PORT_SPIF = 46, + BNXT_ULP_CF_IDX_PHY_PORT_PARIF = 47, + BNXT_ULP_CF_IDX_PHY_PORT_VPORT = 48, + BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG = 49, + BNXT_ULP_CF_IDX_ACT_ENCAP_IPV6_FLAG = 50, + BNXT_ULP_CF_IDX_ACT_DEC_TTL = 51, + BNXT_ULP_CF_IDX_ACT_T_DEC_TTL = 52, + BNXT_ULP_CF_IDX_ACT_PORT_IS_SET = 53, + BNXT_ULP_CF_IDX_ACT_PORT_TYPE = 54, + BNXT_ULP_CF_IDX_MATCH_PORT_TYPE = 55, + BNXT_ULP_CF_IDX_MATCH_PORT_IS_VFREP = 56, + BNXT_ULP_CF_IDX_MATCH_PORT_IS_PF = 57, + BNXT_ULP_CF_IDX_VF_TO_VF = 58, + BNXT_ULP_CF_IDX_L3_HDR_CNT = 59, + BNXT_ULP_CF_IDX_L4_HDR_CNT = 60, + BNXT_ULP_CF_IDX_VFR_MODE = 61, + BNXT_ULP_CF_IDX_L3_TUN_DECAP = 62, + BNXT_ULP_CF_IDX_FID = 63, + BNXT_ULP_CF_IDX_HDR_SIG_ID = 64, + BNXT_ULP_CF_IDX_FLOW_SIG_ID = 65, + BNXT_ULP_CF_IDX_WC_MATCH = 66, + BNXT_ULP_CF_IDX_WC_IS_HA_HIGH_REG = 67, + BNXT_ULP_CF_IDX_TUNNEL_ID = 68, + BNXT_ULP_CF_IDX_TUN_OFF_DIP_ID = 69, + BNXT_ULP_CF_IDX_TUN_OFF_DMAC_ID = 70, + BNXT_ULP_CF_IDX_OO_VLAN_FB_VID = 71, + BNXT_ULP_CF_IDX_OI_VLAN_FB_VID = 72, + BNXT_ULP_CF_IDX_IO_VLAN_FB_VID = 73, + BNXT_ULP_CF_IDX_II_VLAN_FB_VID = 74, + BNXT_ULP_CF_IDX_SOCKET_DIRECT = 75, + BNXT_ULP_CF_IDX_SOCKET_DIRECT_VPORT = 76, + BNXT_ULP_CF_IDX_TUNNEL_SPORT = 77, + BNXT_ULP_CF_IDX_VF_META_FID = 78, + BNXT_ULP_CF_IDX_DEV_ACT_PORT_ID = 79, + BNXT_ULP_CF_IDX_O_VLAN_NO_IGNORE = 80, + BNXT_ULP_CF_IDX_I_VLAN_NO_IGNORE = 81, + BNXT_ULP_CF_IDX_HA_SUPPORT_DISABLED = 82, + BNXT_ULP_CF_IDX_FUNCTION_ID = 83, + BNXT_ULP_CF_IDX_CHAIN_ID_METADATA = 84, + BNXT_ULP_CF_IDX_SRV6_UPAR_ID = 85, + BNXT_ULP_CF_IDX_SRV6_T_ID = 86, + BNXT_ULP_CF_IDX_GENERIC_SIZE = 87, + BNXT_ULP_CF_IDX_L2_CUSTOM_UPAR_ID = 88, + BNXT_ULP_CF_IDX_CUSTOM_GRE_EN = 89, + BNXT_ULP_CF_IDX_UPAR_HIGH_EN = 90, + BNXT_ULP_CF_IDX_MP_NPORTS = 91, + BNXT_ULP_CF_IDX_MP_PORT_A = 92, + BNXT_ULP_CF_IDX_MP_VNIC_A = 93, + BNXT_ULP_CF_IDX_MP_VPORT_A = 94, + BNXT_ULP_CF_IDX_MP_MDATA_A = 95, + BNXT_ULP_CF_IDX_MP_A_IS_VFREP = 96, + BNXT_ULP_CF_IDX_MP_PORT_B = 97, + BNXT_ULP_CF_IDX_MP_VNIC_B = 98, + BNXT_ULP_CF_IDX_MP_VPORT_B = 99, + BNXT_ULP_CF_IDX_MP_MDATA_B = 100, + BNXT_ULP_CF_IDX_MP_B_IS_VFREP = 101, + BNXT_ULP_CF_IDX_VXLAN_IP_UPAR_ID = 102, + BNXT_ULP_CF_IDX_ACT_REJ_COND_EN = 103, + BNXT_ULP_CF_IDX_HDR_BITMAP = 104, + BNXT_ULP_CF_IDX_LAST = 105 }; enum bnxt_ulp_cond_list_opc { @@ -263,7 +295,9 @@ enum bnxt_ulp_cond_list_opc { BNXT_ULP_COND_LIST_OPC_FALSE = 1, BNXT_ULP_COND_LIST_OPC_OR = 2, BNXT_ULP_COND_LIST_OPC_AND = 3, - BNXT_ULP_COND_LIST_OPC_LAST = 4 + BNXT_ULP_COND_LIST_OPC_LIST_OR = 4, + BNXT_ULP_COND_LIST_OPC_LIST_AND = 5, + BNXT_ULP_COND_LIST_OPC_LAST = 6 }; enum bnxt_ulp_cond_opc { @@ -285,7 +319,13 @@ enum bnxt_ulp_cond_opc { BNXT_ULP_COND_OPC_ENC_HDR_BIT_NOT_SET = 15, BNXT_ULP_COND_OPC_ACT_PROP_IS_SET = 16, BNXT_ULP_COND_OPC_ACT_PROP_NOT_SET = 17, - BNXT_ULP_COND_OPC_LAST = 18 + BNXT_ULP_COND_OPC_CF_BIT_IS_SET = 18, + BNXT_ULP_COND_OPC_CF_BIT_NOT_SET = 19, + BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET = 20, + BNXT_ULP_COND_OPC_WC_FIELD_BIT_NOT_SET = 21, + BNXT_ULP_COND_OPC_EXCLUDE_FIELD_BIT_IS_SET = 22, + BNXT_ULP_COND_OPC_EXCLUDE_FIELD_BIT_NOT_SET = 23, + BNXT_ULP_COND_OPC_LAST = 24 }; enum bnxt_ulp_critical_resource { @@ -299,7 +339,8 @@ enum bnxt_ulp_device_id { BNXT_ULP_DEVICE_ID_THOR = 1, BNXT_ULP_DEVICE_ID_STINGRAY = 2, BNXT_ULP_DEVICE_ID_STINGRAY2 = 3, - BNXT_ULP_DEVICE_ID_LAST = 4 + BNXT_ULP_DEVICE_ID_THOR2 = 4, + BNXT_ULP_DEVICE_ID_LAST = 5 }; enum bnxt_ulp_df_param_type { @@ -358,7 +399,17 @@ enum bnxt_ulp_enc_field { BNXT_ULP_ENC_FIELD_VXLAN_GPE_NEXT_PROTO = 41, BNXT_ULP_ENC_FIELD_VXLAN_GPE_VNI = 42, BNXT_ULP_ENC_FIELD_VXLAN_GPE_RSVD1 = 43, - BNXT_ULP_ENC_FIELD_LAST = 44 + BNXT_ULP_ENC_FIELD_GENEVE_VER_OPT_LEN_O_C_RSVD0 = 44, + BNXT_ULP_ENC_FIELD_GENEVE_PROTO_TYPE = 45, + BNXT_ULP_ENC_FIELD_GENEVE_VNI = 46, + BNXT_ULP_ENC_FIELD_GENEVE_RSVD1 = 47, + BNXT_ULP_ENC_FIELD_GENEVE_OPT_W0 = 48, + BNXT_ULP_ENC_FIELD_GENEVE_OPT_W1 = 49, + BNXT_ULP_ENC_FIELD_GENEVE_OPT_W2 = 50, + BNXT_ULP_ENC_FIELD_GENEVE_OPT_W3 = 51, + BNXT_ULP_ENC_FIELD_GENEVE_OPT_W4 = 52, + BNXT_ULP_ENC_FIELD_GENEVE_OPT_W5 = 53, + BNXT_ULP_ENC_FIELD_LAST = 54 }; enum bnxt_ulp_fdb_opc { @@ -390,7 +441,8 @@ enum bnxt_ulp_field_opc { BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2 = 8, BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3 = 9, BNXT_ULP_FIELD_OPC_SKIP = 10, - BNXT_ULP_FIELD_OPC_LAST = 11 + BNXT_ULP_FIELD_OPC_TERNARY_LIST = 11, + BNXT_ULP_FIELD_OPC_LAST = 12 }; enum bnxt_ulp_field_src { @@ -412,7 +464,10 @@ enum bnxt_ulp_field_src { BNXT_ULP_FIELD_SRC_PORT_TABLE = 15, BNXT_ULP_FIELD_SRC_ENC_HDR_BIT = 16, BNXT_ULP_FIELD_SRC_ENC_FIELD = 17, - BNXT_ULP_FIELD_SRC_LAST = 18 + BNXT_ULP_FIELD_SRC_LIST_AND = 18, + BNXT_ULP_FIELD_SRC_LIST_OR = 19, + BNXT_ULP_FIELD_SRC_NEXT = 20, + BNXT_ULP_FIELD_SRC_LAST = 21 }; enum bnxt_ulp_func_opc { @@ -429,9 +484,20 @@ enum bnxt_ulp_func_opc { BNXT_ULP_FUNC_OPC_ALLOC_L2_CTX_ID = 10, BNXT_ULP_FUNC_OPC_TUNNEL_DST_PORT_ALLOC = 11, BNXT_ULP_FUNC_OPC_TUNNEL_DST_PORT_FREE = 12, - BNXT_ULP_FUNC_OPC_ADD = 13, - BNXT_ULP_FUNC_OPC_SUB = 14, - BNXT_ULP_FUNC_OPC_LAST = 15 + BNXT_ULP_FUNC_OPC_HANDLE_TO_OFFSET = 13, + BNXT_ULP_FUNC_OPC_VFR_MARK_SET = 14, + BNXT_ULP_FUNC_OPC_BD_ACT_SET = 15, + BNXT_ULP_FUNC_OPC_LEFT_SHIFT = 16, + BNXT_ULP_FUNC_OPC_RIGHT_SHIFT = 17, + BNXT_ULP_FUNC_OPC_BIT_OR = 18, + BNXT_ULP_FUNC_OPC_BIT_AND = 19, + BNXT_ULP_FUNC_OPC_BIT_XOR = 20, + BNXT_ULP_FUNC_OPC_LOG_AND = 21, + BNXT_ULP_FUNC_OPC_LOG_OR = 22, + BNXT_ULP_FUNC_OPC_NOT_NOT = 23, + BNXT_ULP_FUNC_OPC_ADD = 24, + BNXT_ULP_FUNC_OPC_SUB = 25, + BNXT_ULP_FUNC_OPC_LAST = 26 }; enum bnxt_ulp_func_src { @@ -439,20 +505,32 @@ enum bnxt_ulp_func_src { BNXT_ULP_FUNC_SRC_GLB_REGFILE = 1, BNXT_ULP_FUNC_SRC_COMP_FIELD = 2, BNXT_ULP_FUNC_SRC_CONST = 3, - BNXT_ULP_FUNC_SRC_LAST = 4 + BNXT_ULP_FUNC_SRC_ACTION_BITMAP = 4, + BNXT_ULP_FUNC_SRC_HEADER_BITMAP = 5, + BNXT_ULP_FUNC_SRC_LAST = 6 +}; + +enum bnxt_ulp_gen_tbl_type { + BNXT_ULP_GEN_TBL_TYPE_KEY_LIST = 0, + BNXT_ULP_GEN_TBL_TYPE_HASH_LIST = 1, + BNXT_ULP_GEN_TBL_TYPE_SIMPLE_LIST = 2, + BNXT_ULP_GEN_TBL_TYPE_LAST = 3 }; enum bnxt_ulp_generic_tbl_lkup_type { BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX = 0, BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH = 1, - BNXT_ULP_GENERIC_TBL_LKUP_TYPE_LAST = 2 + BNXT_ULP_GENERIC_TBL_LKUP_TYPE_SEQ = 2, + BNXT_ULP_GENERIC_TBL_LKUP_TYPE_LAST = 3 }; enum bnxt_ulp_generic_tbl_opc { BNXT_ULP_GENERIC_TBL_OPC_NOT_USED = 0, BNXT_ULP_GENERIC_TBL_OPC_READ = 1, BNXT_ULP_GENERIC_TBL_OPC_WRITE = 2, - BNXT_ULP_GENERIC_TBL_OPC_LAST = 3 + BNXT_ULP_GENERIC_TBL_OPC_SEARCH_OVERLAP = 3, + BNXT_ULP_GENERIC_TBL_OPC_SIMPLE_WRITE = 4, + BNXT_ULP_GENERIC_TBL_OPC_LAST = 5 }; enum bnxt_ulp_glb_rf_idx { @@ -508,47 +586,53 @@ enum bnxt_ulp_glb_rf_idx { BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_5 = 49, BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0 = 50, BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_1 = 51, - BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0 = 52, - BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_1 = 53, - BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0 = 54, - BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_1 = 55, - BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 = 56, - BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1 = 57, - BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2 = 58, - BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3 = 59, - BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_4 = 60, - BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 = 61, - BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 = 62, - BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_2 = 63, - BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_3 = 64, - BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0 = 65, - BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_1 = 66, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 = 67, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1 = 68, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2 = 69, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_3 = 70, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_4 = 71, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_5 = 72, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_6 = 73, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_7 = 74, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_8 = 75, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_9 = 76, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_10 = 77, - BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0 = 78, - BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_1 = 79, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 = 80, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1 = 81, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_2 = 82, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_3 = 83, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_4 = 84, - BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_5 = 85, - BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0 = 86, - BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1 = 87, - BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID = 88, - BNXT_ULP_GLB_RF_IDX_RECYCLE_PROF_FUNC_ID = 89, - BNXT_ULP_GLB_RF_IDX_GLB_ECPRI_UPAR_ID = 90, - BNXT_ULP_GLB_RF_IDX_GLB_ECPRI_PROF_FUNC_ID = 91, - BNXT_ULP_GLB_RF_IDX_LAST = 92 + BNXT_ULP_GLB_RF_IDX_GLB_METADATA_RX_PROF_0 = 52, + BNXT_ULP_GLB_RF_IDX_GLB_METADATA_RX_ACT_0 = 53, + BNXT_ULP_GLB_RF_IDX_GLB_METADATA_RX_LKUP_0 = 54, + BNXT_ULP_GLB_RF_IDX_GLB_METADATA_TX_PROF_0 = 55, + BNXT_ULP_GLB_RF_IDX_GLB_METADATA_TX_ACT_0 = 56, + BNXT_ULP_GLB_RF_IDX_GLB_METADATA_TX_LKUP_0 = 57, + BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0 = 58, + BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_1 = 59, + BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0 = 60, + BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_1 = 61, + BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 = 62, + BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1 = 63, + BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2 = 64, + BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3 = 65, + BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_4 = 66, + BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 = 67, + BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 = 68, + BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_2 = 69, + BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_3 = 70, + BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0 = 71, + BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_1 = 72, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 = 73, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1 = 74, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2 = 75, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_3 = 76, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_4 = 77, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_5 = 78, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_6 = 79, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_7 = 80, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_8 = 81, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_9 = 82, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_10 = 83, + BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0 = 84, + BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_1 = 85, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 = 86, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1 = 87, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_2 = 88, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_3 = 89, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_4 = 90, + BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_5 = 91, + BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0 = 92, + BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1 = 93, + BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID = 94, + BNXT_ULP_GLB_RF_IDX_RECYCLE_PROF_FUNC_ID = 95, + BNXT_ULP_GLB_RF_IDX_GLB_ECPRI_UPAR_ID = 96, + BNXT_ULP_GLB_RF_IDX_GLB_ECPRI_PROF_FUNC_ID = 97, + BNXT_ULP_GLB_RF_IDX_LAST = 98 }; enum bnxt_ulp_global_register_tbl_opc { @@ -585,6 +669,18 @@ enum bnxt_ulp_index_tbl_opc { BNXT_ULP_INDEX_TBL_OPC_LAST = 8 }; +enum bnxt_ulp_key_recipe_opc { + BNXT_ULP_KEY_RECIPE_OPC_NOP = 0, + BNXT_ULP_KEY_RECIPE_OPC_DYN_KEY = 1, + BNXT_ULP_KEY_RECIPE_OPC_LAST = 2 +}; + +enum bnxt_ulp_key_recipe_tbl_opc { + BNXT_ULP_KEY_RECIPE_TBL_OPC_NOT_USED = 0, + BNXT_ULP_KEY_RECIPE_TBL_OPC_WR_REGFILE = 1, + BNXT_ULP_KEY_RECIPE_TBL_OPC_LAST = 2 +}; + enum bnxt_ulp_mark_db_opc { BNXT_ULP_MARK_DB_OPC_NOP = 0, BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION = 1, @@ -619,7 +715,8 @@ enum bnxt_ulp_port_table { BNXT_ULP_PORT_TABLE_PORT_IS_PF = 17, BNXT_ULP_PORT_TABLE_VF_FUNC_METADATA = 18, BNXT_ULP_PORT_TABLE_VF_FUNC_FID = 19, - BNXT_ULP_PORT_TABLE_LAST = 20 + BNXT_ULP_PORT_TABLE_TABLE_SCOPE = 20, + BNXT_ULP_PORT_TABLE_LAST = 21 }; enum bnxt_ulp_pri_opc { @@ -674,39 +771,46 @@ enum bnxt_ulp_rf_idx { BNXT_ULP_RF_IDX_HDR_SIG_ID = 32, BNXT_ULP_RF_IDX_FLOW_SIG_ID = 33, BNXT_ULP_RF_IDX_RID = 34, - BNXT_ULP_RF_IDX_WC_KEY_ID_0 = 35, - BNXT_ULP_RF_IDX_EM_KEY_ID_0 = 36, - BNXT_ULP_RF_IDX_DRV_FUNC_MAC = 37, - BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC = 38, - BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR = 39, - BNXT_ULP_RF_IDX_CC = 40, - BNXT_ULP_RF_IDX_CF_FLOW_SIG_ID = 41, - BNXT_ULP_RF_IDX_PHY_PORT = 42, - BNXT_ULP_RF_IDX_METADATA_PROF = 43, - BNXT_ULP_RF_IDX_MODIFY_PTR = 44, - BNXT_ULP_RF_IDX_SOCK_DIR_SVIF = 45, - BNXT_ULP_RF_IDX_SOCK_DIR_PARIF = 46, - BNXT_ULP_RF_IDX_SOCK_DIR_ACT_PTR = 47, - BNXT_ULP_RF_IDX_SOCK_DIR_PARENT_MAC = 48, - BNXT_ULP_RF_IDX_RSS_VNIC = 49, - BNXT_ULP_RF_IDX_PORT_IS_PF = 50, - BNXT_ULP_RF_IDX_METER_PROFILE_PTR_0 = 51, - BNXT_ULP_RF_IDX_METER_PTR_0 = 52, - BNXT_ULP_RF_IDX_REF_CNT = 53, - BNXT_ULP_RF_IDX_RF_0 = 54, - BNXT_ULP_RF_IDX_RF_1 = 55, - BNXT_ULP_RF_IDX_RF_2 = 56, - BNXT_ULP_RF_IDX_RF_3 = 57, - BNXT_ULP_RF_IDX_RF_4 = 58, - BNXT_ULP_RF_IDX_RF_5 = 59, - BNXT_ULP_RF_IDX_RF_6 = 60, - BNXT_ULP_RF_IDX_RF_7 = 61, - BNXT_ULP_RF_IDX_VF_FUNC_METADATA = 62, - BNXT_ULP_RF_IDX_CHAIN_ID_METADATA = 63, - BNXT_ULP_RF_IDX_DEST_VNIC = 64, - BNXT_ULP_RF_IDX_DEST_VPORT = 65, - BNXT_ULP_RF_IDX_DEST_METADATA = 66, - BNXT_ULP_RF_IDX_LAST = 67 + BNXT_ULP_RF_IDX_RID_1 = 35, + BNXT_ULP_RF_IDX_WC_KEY_ID_0 = 36, + BNXT_ULP_RF_IDX_EM_KEY_ID_0 = 37, + BNXT_ULP_RF_IDX_DRV_FUNC_MAC = 38, + BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC = 39, + BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR = 40, + BNXT_ULP_RF_IDX_CC = 41, + BNXT_ULP_RF_IDX_CF_FLOW_SIG_ID = 42, + BNXT_ULP_RF_IDX_PHY_PORT = 43, + BNXT_ULP_RF_IDX_METADATA_PROF = 44, + BNXT_ULP_RF_IDX_MODIFY_PTR = 45, + BNXT_ULP_RF_IDX_SOCK_DIR_SVIF = 46, + BNXT_ULP_RF_IDX_SOCK_DIR_PARIF = 47, + BNXT_ULP_RF_IDX_SOCK_DIR_ACT_PTR = 48, + BNXT_ULP_RF_IDX_SOCK_DIR_PARENT_MAC = 49, + BNXT_ULP_RF_IDX_RSS_VNIC = 50, + BNXT_ULP_RF_IDX_PORT_IS_PF = 51, + BNXT_ULP_RF_IDX_METER_PROFILE_PTR_0 = 52, + BNXT_ULP_RF_IDX_METER_PTR_0 = 53, + BNXT_ULP_RF_IDX_REF_CNT = 54, + BNXT_ULP_RF_IDX_RF_0 = 55, + BNXT_ULP_RF_IDX_RF_1 = 56, + BNXT_ULP_RF_IDX_RF_2 = 57, + BNXT_ULP_RF_IDX_RF_3 = 58, + BNXT_ULP_RF_IDX_RF_4 = 59, + BNXT_ULP_RF_IDX_RF_5 = 60, + BNXT_ULP_RF_IDX_RF_6 = 61, + BNXT_ULP_RF_IDX_RF_7 = 62, + BNXT_ULP_RF_IDX_CMM_ACT_HNDL = 63, + BNXT_ULP_RF_IDX_CMM_STAT_HNDL = 64, + BNXT_ULP_RF_IDX_CMM_MOD_HNDL = 65, + BNXT_ULP_RF_IDX_CMM_ENC_HNDL = 66, + BNXT_ULP_RF_IDX_CMM_SRP_HNDL = 67, + BNXT_ULP_RF_IDX_VF_FUNC_METADATA = 68, + BNXT_ULP_RF_IDX_CHAIN_ID_METADATA = 69, + BNXT_ULP_RF_IDX_RECYCLE_CNT = 70, + BNXT_ULP_RF_IDX_DEST_VNIC = 71, + BNXT_ULP_RF_IDX_DEST_VPORT = 72, + BNXT_ULP_RF_IDX_DEST_METADATA = 73, + BNXT_ULP_RF_IDX_LAST = 74 }; enum bnxt_ulp_tcam_tbl_opc { @@ -757,8 +861,8 @@ enum bnxt_ulp_flow_dir_bitmask { enum bnxt_ulp_resource_func { BNXT_ULP_RESOURCE_FUNC_INVALID = 0x00, BNXT_ULP_RESOURCE_FUNC_EM_TABLE = 0x20, - BNXT_ULP_RESOURCE_FUNC_RSVD1 = 0x40, - BNXT_ULP_RESOURCE_FUNC_RSVD2 = 0x60, + BNXT_ULP_RESOURCE_FUNC_CMM_TABLE = 0x40, + BNXT_ULP_RESOURCE_FUNC_CMM_STAT = 0x60, BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE = 0x80, BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE = 0x81, BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE = 0x82, @@ -769,7 +873,8 @@ enum bnxt_ulp_resource_func { BNXT_ULP_RESOURCE_FUNC_CHILD_FLOW = 0x87, BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE = 0x88, BNXT_ULP_RESOURCE_FUNC_VNIC_TABLE = 0x89, - BNXT_ULP_RESOURCE_FUNC_GLOBAL_REGISTER_TABLE = 0x8a + BNXT_ULP_RESOURCE_FUNC_GLOBAL_REGISTER_TABLE = 0x8a, + BNXT_ULP_RESOURCE_FUNC_KEY_RECIPE_TABLE = 0x8b }; enum bnxt_ulp_resource_sub_type { @@ -779,6 +884,7 @@ enum bnxt_ulp_resource_sub_type { BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT = 2, BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT_ACC = 3, BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_EXT_COUNT = 4, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_CFA_TBLS = 5, BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM = 0, BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM = 1, BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR = 2, @@ -798,13 +904,28 @@ enum bnxt_ulp_resource_sub_type { BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_ENCAP_REC_CACHE = 16, BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SRV6_ENCAP_REC_CACHE = 17, BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_RSS_PARAMS = 18, - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MULTI_SHARED_MIRROR = 19, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TABLE_SCOPE_CACHE = 19, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_GENEVE_ENCAP_REC_CACHE = 20, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROTO_HEADER = 21, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_EM_FLOW_CONFLICT = 22, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_HDR_OVERLAP = 23, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MULTI_SHARED_MIRROR = 24, BNXT_ULP_RESOURCE_SUB_TYPE_VNIC_TABLE_RSS = 0, BNXT_ULP_RESOURCE_SUB_TYPE_VNIC_TABLE_QUEUE = 1, BNXT_ULP_RESOURCE_SUB_TYPE_GLOBAL_REGISTER_CUST_VXLAN = 0, BNXT_ULP_RESOURCE_SUB_TYPE_GLOBAL_REGISTER_CUST_ECPRI = 1, BNXT_ULP_RESOURCE_SUB_TYPE_GLOBAL_REGISTER_CUST_VXLAN_GPE = 2, - BNXT_ULP_RESOURCE_SUB_TYPE_GLOBAL_REGISTER_CUST_VXLAN_GPE_V6 = 3 + BNXT_ULP_RESOURCE_SUB_TYPE_GLOBAL_REGISTER_CUST_VXLAN_GPE_V6 = 3, + BNXT_ULP_RESOURCE_SUB_TYPE_CMM_TABLE_ACT = 4, + BNXT_ULP_RESOURCE_SUB_TYPE_CMM_TABLE_LKUP = 5, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_STAT_64 = 6, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_CMM_MCG_ACT = 2, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_CMM_MODIFY_REC = 3, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_CMM_STAT_COUNTER = 4, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_CMM_SRC_PROP = 5, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_CMM_ENCAP_REC = 6, + BNXT_ULP_RESOURCE_SUB_TYPE_KEY_RECIPE_TABLE_EM = 0, + BNXT_ULP_RESOURCE_SUB_TYPE_KEY_RECIPE_TABLE_WM = 1 }; enum bnxt_ulp_session_type { @@ -859,6 +980,7 @@ enum bnxt_ulp_act_prop_sz { BNXT_ULP_ACT_PROP_SZ_ENCAP_TUN = 32, BNXT_ULP_ACT_PROP_SZ_JUMP = 4, BNXT_ULP_ACT_PROP_SZ_SHARED_HANDLE = 8, + BNXT_ULP_ACT_PROP_SZ_RSS_FUNC = 1, BNXT_ULP_ACT_PROP_SZ_RSS_TYPES = 8, BNXT_ULP_ACT_PROP_SZ_RSS_LEVEL = 4, BNXT_ULP_ACT_PROP_SZ_RSS_KEY_LEN = 4, @@ -885,6 +1007,7 @@ enum bnxt_ulp_act_prop_sz { BNXT_ULP_ACT_PROP_SZ_METER_INST_MTR_VAL_UPDATE = 1, BNXT_ULP_ACT_PROP_SZ_METER_INST_MTR_VAL = 1, BNXT_ULP_ACT_PROP_SZ_GOTO_CHAINID = 2, + BNXT_ULP_ACT_PROP_SZ_SET_TTL = 1, BNXT_ULP_ACT_PROP_SZ_LAST = 4 }; @@ -931,33 +1054,35 @@ enum bnxt_ulp_act_prop_idx { BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN = 221, BNXT_ULP_ACT_PROP_IDX_JUMP = 253, BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE = 257, - BNXT_ULP_ACT_PROP_IDX_RSS_TYPES = 265, - BNXT_ULP_ACT_PROP_IDX_RSS_LEVEL = 273, - BNXT_ULP_ACT_PROP_IDX_RSS_KEY_LEN = 277, - BNXT_ULP_ACT_PROP_IDX_RSS_KEY = 281, - BNXT_ULP_ACT_PROP_IDX_RSS_QUEUE_NUM = 321, - BNXT_ULP_ACT_PROP_IDX_RSS_QUEUE = 323, - BNXT_ULP_ACT_PROP_IDX_QUEUE_INDEX = 355, - BNXT_ULP_ACT_PROP_IDX_METER_PROF_ID_UPDATE = 357, - BNXT_ULP_ACT_PROP_IDX_METER_PROF_ID = 358, - BNXT_ULP_ACT_PROP_IDX_METER_PROF_CIR = 362, - BNXT_ULP_ACT_PROP_IDX_METER_PROF_EIR = 365, - BNXT_ULP_ACT_PROP_IDX_METER_PROF_CBS = 368, - BNXT_ULP_ACT_PROP_IDX_METER_PROF_EBS = 370, - BNXT_ULP_ACT_PROP_IDX_METER_PROF_RFC2698 = 372, - BNXT_ULP_ACT_PROP_IDX_METER_PROF_PM = 373, - BNXT_ULP_ACT_PROP_IDX_METER_PROF_EBND = 374, - BNXT_ULP_ACT_PROP_IDX_METER_PROF_CBND = 375, - BNXT_ULP_ACT_PROP_IDX_METER_PROF_EBSM = 376, - BNXT_ULP_ACT_PROP_IDX_METER_PROF_CBSM = 377, - BNXT_ULP_ACT_PROP_IDX_METER_PROF_CF = 378, - BNXT_ULP_ACT_PROP_IDX_METER_INST_ID = 379, - BNXT_ULP_ACT_PROP_IDX_METER_INST_ECN_RMP_EN_UPDATE = 383, - BNXT_ULP_ACT_PROP_IDX_METER_INST_ECN_RMP_EN = 384, - BNXT_ULP_ACT_PROP_IDX_METER_INST_MTR_VAL_UPDATE = 385, - BNXT_ULP_ACT_PROP_IDX_METER_INST_MTR_VAL = 386, - BNXT_ULP_ACT_PROP_IDX_GOTO_CHAINID = 387, - BNXT_ULP_ACT_PROP_IDX_LAST = 389 + BNXT_ULP_ACT_PROP_IDX_RSS_FUNC = 265, + BNXT_ULP_ACT_PROP_IDX_RSS_TYPES = 266, + BNXT_ULP_ACT_PROP_IDX_RSS_LEVEL = 274, + BNXT_ULP_ACT_PROP_IDX_RSS_KEY_LEN = 278, + BNXT_ULP_ACT_PROP_IDX_RSS_KEY = 282, + BNXT_ULP_ACT_PROP_IDX_RSS_QUEUE_NUM = 322, + BNXT_ULP_ACT_PROP_IDX_RSS_QUEUE = 324, + BNXT_ULP_ACT_PROP_IDX_QUEUE_INDEX = 356, + BNXT_ULP_ACT_PROP_IDX_METER_PROF_ID_UPDATE = 358, + BNXT_ULP_ACT_PROP_IDX_METER_PROF_ID = 359, + BNXT_ULP_ACT_PROP_IDX_METER_PROF_CIR = 363, + BNXT_ULP_ACT_PROP_IDX_METER_PROF_EIR = 366, + BNXT_ULP_ACT_PROP_IDX_METER_PROF_CBS = 369, + BNXT_ULP_ACT_PROP_IDX_METER_PROF_EBS = 371, + BNXT_ULP_ACT_PROP_IDX_METER_PROF_RFC2698 = 373, + BNXT_ULP_ACT_PROP_IDX_METER_PROF_PM = 374, + BNXT_ULP_ACT_PROP_IDX_METER_PROF_EBND = 375, + BNXT_ULP_ACT_PROP_IDX_METER_PROF_CBND = 376, + BNXT_ULP_ACT_PROP_IDX_METER_PROF_EBSM = 377, + BNXT_ULP_ACT_PROP_IDX_METER_PROF_CBSM = 378, + BNXT_ULP_ACT_PROP_IDX_METER_PROF_CF = 379, + BNXT_ULP_ACT_PROP_IDX_METER_INST_ID = 380, + BNXT_ULP_ACT_PROP_IDX_METER_INST_ECN_RMP_EN_UPDATE = 384, + BNXT_ULP_ACT_PROP_IDX_METER_INST_ECN_RMP_EN = 385, + BNXT_ULP_ACT_PROP_IDX_METER_INST_MTR_VAL_UPDATE = 386, + BNXT_ULP_ACT_PROP_IDX_METER_INST_MTR_VAL = 387, + BNXT_ULP_ACT_PROP_IDX_GOTO_CHAINID = 388, + BNXT_ULP_ACT_PROP_IDX_SET_TTL = 390, + BNXT_ULP_ACT_PROP_IDX_LAST = 391 }; enum ulp_wp_sym { @@ -968,11 +1093,18 @@ enum ulp_wp_sym { ULP_WP_SYM_FWD_OP_BYPASS_CFA_ROCE = 0, ULP_WP_SYM_FWD_OP_BYPASS_LKUP = 0, ULP_WP_SYM_FWD_OP_NORMAL_FLOW = 0, + ULP_WP_SYM_FWD_OP_DROP = 0, ULP_WP_SYM_CTXT_OPCODE_BYPASS_CFA = 0, ULP_WP_SYM_CTXT_OPCODE_BYPASS_LKUP = 0, ULP_WP_SYM_CTXT_OPCODE_META_UPDATE = 0, ULP_WP_SYM_CTXT_OPCODE_NORMAL_FLOW = 0, ULP_WP_SYM_CTXT_OPCODE_DROP = 0, + ULP_WP_SYM_L2_CTXT_PRI_CATCHALL = 0, + ULP_WP_SYM_L2_CTXT_PRI_MC_BC = 0, + ULP_WP_SYM_L2_CTXT_PRI_PORT = 0, + ULP_WP_SYM_L2_CTXT_PRI_APP = 0, + ULP_WP_SYM_PROF_TCAM_PRI_CATCHALL = 0, + ULP_WP_SYM_PROF_TCAM_PRI_APP = 0, ULP_WP_SYM_PKT_TYPE_IGNORE = 0, ULP_WP_SYM_PKT_TYPE_L2 = 0, ULP_WP_SYM_PKT_TYPE_0_IGNORE = 0, @@ -1056,6 +1188,19 @@ enum ulp_wp_sym { ULP_WP_SYM_TUN_HDR_TYPE_UPAR2 = 9, ULP_WP_SYM_TUN_HDR_TYPE_UPAR3 = 10, ULP_WP_SYM_TUN_HDR_TYPE_UPAR4 = 11, + ULP_WP_SYM_TUN_HDR_TYPE_UPAR5 = 0, + ULP_WP_SYM_TUN_HDR_TYPE_UPAR6 = 0, + ULP_WP_SYM_TUN_HDR_TYPE_UPAR7 = 0, + ULP_WP_SYM_TUN_HDR_TYPE_UPAR8 = 0, + ULP_WP_SYM_TUN_HDR_TYPE_ROE = 0, + ULP_WP_SYM_TUN_HDR_TYPE_ECPRI = 0, + ULP_WP_SYM_TUN_HDR_TYPE_GTP_V1_U = 0, + ULP_WP_SYM_TUN_HDR_TYPE_GTP_V2_C = 0, + ULP_WP_SYM_TUN_HDR_TYPE_PFCP_SESS = 0, + ULP_WP_SYM_TUN_HDR_TYPE_PFCP_NODE = 0, + ULP_WP_SYM_TUN_HDR_TYPE_NSH = 0, + ULP_WP_SYM_TUN_HDR_TYPE_VXLAN_IP = 0, + ULP_WP_SYM_TUN_HDR_TYPE_GRE_TEN = 0, ULP_WP_SYM_TUN_HDR_TYPE_NONE = 15, ULP_WP_SYM_TUN_HDR_TYPE_UPAR_MASK = 14, ULP_WP_SYM_TUN_HDR_TYPE_TID_MASK = 0, @@ -1080,6 +1225,18 @@ enum ulp_wp_sym { ULP_WP_SYM_L2_TWO_VTAGS_IGNORE = 0, ULP_WP_SYM_L2_TWO_VTAGS_NO = 0, ULP_WP_SYM_L2_TWO_VTAGS_YES = 1, + ULP_WP_SYM_L2_CNTX_VLAN_SELECT_INNER = 0, + ULP_WP_SYM_L2_CNTX_VLAN_SELECT_TUN = 0, + ULP_WP_SYM_L2_CNTX_VLAN_SELECT_O_TUN = 0, + ULP_WP_SYM_L2_CNTX_VLAN_SELECT_OM_TUN = 0, + ULP_WP_SYM_L2_CNTX_TUN_SELECT_TUN_ID = 0, + ULP_WP_SYM_L2_CNTX_TUN_SELECT_TUN_CNTX = 0, + ULP_WP_SYM_L2_CNTX_TUN_SELECT_O_TUN_ID = 0, + ULP_WP_SYM_L2_CNTX_TUN_SELECT_O_TUN_CNTX = 0, + ULP_WP_SYM_L2_CNTX_TUN_SELECT_I_L4_PORTS = 0, + ULP_WP_SYM_L2_CNTX_TUN_SELECT_O_L4_PORTS = 0, + ULP_WP_SYM_L2_CNTX_TUN_SELECT_OM_TUN_ID = 0, + ULP_WP_SYM_L2_CNTX_TUN_SELECT_OM_TUN_CNTX = 0, ULP_WP_SYM_L3_HDR_VALID_IGNORE = 0, ULP_WP_SYM_L3_HDR_VALID_NO = 0, ULP_WP_SYM_L3_HDR_VALID_YES = 1, @@ -1118,13 +1275,18 @@ enum ulp_wp_sym { ULP_WP_SYM_L4_HDR_TYPE_UPAR1 = 3, ULP_WP_SYM_L4_HDR_TYPE_UPAR2 = 4, ULP_WP_SYM_L4_HDR_TYPE_BTH_V1 = 5, + ULP_WP_SYM_L4_HDR_TYPE_IPSEC_AH = 0, + ULP_WP_SYM_L4_HDR_TYPE_IPSEC_ESP = 0, ULP_WP_SYM_L4_HDR_IS_UDP_TCP_IGNORE = 0, ULP_WP_SYM_L4_HDR_IS_UDP_TCP_NO = 0, ULP_WP_SYM_L4_HDR_IS_UDP_TCP_YES = 1, ULP_WP_SYM_EM_WM_OPCODE_OP_NORMAL = 0, + ULP_WP_SYM_EM_WM_OPCODE_OP_NORMAL_RFS = 0, ULP_WP_SYM_EM_WM_OPCODE_OP_RFS_FAST = 0, ULP_WP_SYM_EM_WM_OPCODE_OP_FAST = 0, ULP_WP_SYM_EM_WM_OPCODE_OP_RFS_ACT = 0, + ULP_WP_SYM_EM_WM_OPCODE_OP_CT_MISS_DEF = 0, + ULP_WP_SYM_EM_WM_OPCODE_OP_CT_HIT_DEF = 0, ULP_WP_SYM_EM_WM_OPCODE_OP_RECYCLE = 0, ULP_WP_SYM_POP_VLAN_NO = 0, ULP_WP_SYM_POP_VLAN_YES = 1, @@ -1220,11 +1382,18 @@ enum ulp_thor_sym { ULP_THOR_SYM_FWD_OP_BYPASS_CFA_ROCE = 1, ULP_THOR_SYM_FWD_OP_BYPASS_LKUP = 2, ULP_THOR_SYM_FWD_OP_NORMAL_FLOW = 3, + ULP_THOR_SYM_FWD_OP_DROP = 0, ULP_THOR_SYM_CTXT_OPCODE_BYPASS_CFA = 0, ULP_THOR_SYM_CTXT_OPCODE_BYPASS_LKUP = 1, ULP_THOR_SYM_CTXT_OPCODE_META_UPDATE = 2, ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW = 3, ULP_THOR_SYM_CTXT_OPCODE_DROP = 4, + ULP_THOR_SYM_L2_CTXT_PRI_CATCHALL = 0, + ULP_THOR_SYM_L2_CTXT_PRI_MC_BC = 0, + ULP_THOR_SYM_L2_CTXT_PRI_PORT = 0, + ULP_THOR_SYM_L2_CTXT_PRI_APP = 0, + ULP_THOR_SYM_PROF_TCAM_PRI_CATCHALL = 0, + ULP_THOR_SYM_PROF_TCAM_PRI_APP = 0, ULP_THOR_SYM_PKT_TYPE_IGNORE = 0, ULP_THOR_SYM_PKT_TYPE_L2 = 0, ULP_THOR_SYM_PKT_TYPE_0_IGNORE = 0, @@ -1308,6 +1477,19 @@ enum ulp_thor_sym { ULP_THOR_SYM_TUN_HDR_TYPE_UPAR2 = 9, ULP_THOR_SYM_TUN_HDR_TYPE_UPAR3 = 10, ULP_THOR_SYM_TUN_HDR_TYPE_UPAR4 = 11, + ULP_THOR_SYM_TUN_HDR_TYPE_UPAR5 = 0, + ULP_THOR_SYM_TUN_HDR_TYPE_UPAR6 = 0, + ULP_THOR_SYM_TUN_HDR_TYPE_UPAR7 = 0, + ULP_THOR_SYM_TUN_HDR_TYPE_UPAR8 = 0, + ULP_THOR_SYM_TUN_HDR_TYPE_ROE = 0, + ULP_THOR_SYM_TUN_HDR_TYPE_ECPRI = 0, + ULP_THOR_SYM_TUN_HDR_TYPE_GTP_V1_U = 0, + ULP_THOR_SYM_TUN_HDR_TYPE_GTP_V2_C = 0, + ULP_THOR_SYM_TUN_HDR_TYPE_PFCP_SESS = 0, + ULP_THOR_SYM_TUN_HDR_TYPE_PFCP_NODE = 0, + ULP_THOR_SYM_TUN_HDR_TYPE_NSH = 0, + ULP_THOR_SYM_TUN_HDR_TYPE_VXLAN_IP = 0, + ULP_THOR_SYM_TUN_HDR_TYPE_GRE_TEN = 0, ULP_THOR_SYM_TUN_HDR_TYPE_NONE = 15, ULP_THOR_SYM_TUN_HDR_TYPE_UPAR_MASK = 14, ULP_THOR_SYM_TUN_HDR_TYPE_TID_MASK = 3840, @@ -1332,6 +1514,18 @@ enum ulp_thor_sym { ULP_THOR_SYM_L2_TWO_VTAGS_IGNORE = 0, ULP_THOR_SYM_L2_TWO_VTAGS_NO = 0, ULP_THOR_SYM_L2_TWO_VTAGS_YES = 1, + ULP_THOR_SYM_L2_CNTX_VLAN_SELECT_INNER = 0, + ULP_THOR_SYM_L2_CNTX_VLAN_SELECT_TUN = 0, + ULP_THOR_SYM_L2_CNTX_VLAN_SELECT_O_TUN = 0, + ULP_THOR_SYM_L2_CNTX_VLAN_SELECT_OM_TUN = 0, + ULP_THOR_SYM_L2_CNTX_TUN_SELECT_TUN_ID = 0, + ULP_THOR_SYM_L2_CNTX_TUN_SELECT_TUN_CNTX = 0, + ULP_THOR_SYM_L2_CNTX_TUN_SELECT_O_TUN_ID = 0, + ULP_THOR_SYM_L2_CNTX_TUN_SELECT_O_TUN_CNTX = 0, + ULP_THOR_SYM_L2_CNTX_TUN_SELECT_I_L4_PORTS = 0, + ULP_THOR_SYM_L2_CNTX_TUN_SELECT_O_L4_PORTS = 0, + ULP_THOR_SYM_L2_CNTX_TUN_SELECT_OM_TUN_ID = 0, + ULP_THOR_SYM_L2_CNTX_TUN_SELECT_OM_TUN_CNTX = 0, ULP_THOR_SYM_L3_HDR_VALID_IGNORE = 0, ULP_THOR_SYM_L3_HDR_VALID_NO = 0, ULP_THOR_SYM_L3_HDR_VALID_YES = 1, @@ -1370,13 +1564,18 @@ enum ulp_thor_sym { ULP_THOR_SYM_L4_HDR_TYPE_UPAR1 = 3, ULP_THOR_SYM_L4_HDR_TYPE_UPAR2 = 4, ULP_THOR_SYM_L4_HDR_TYPE_BTH_V1 = 5, + ULP_THOR_SYM_L4_HDR_TYPE_IPSEC_AH = 0, + ULP_THOR_SYM_L4_HDR_TYPE_IPSEC_ESP = 0, ULP_THOR_SYM_L4_HDR_IS_UDP_TCP_IGNORE = 0, ULP_THOR_SYM_L4_HDR_IS_UDP_TCP_NO = 0, ULP_THOR_SYM_L4_HDR_IS_UDP_TCP_YES = 1, ULP_THOR_SYM_EM_WM_OPCODE_OP_NORMAL = 0, + ULP_THOR_SYM_EM_WM_OPCODE_OP_NORMAL_RFS = 0, ULP_THOR_SYM_EM_WM_OPCODE_OP_RFS_FAST = 1, ULP_THOR_SYM_EM_WM_OPCODE_OP_FAST = 2, ULP_THOR_SYM_EM_WM_OPCODE_OP_RFS_ACT = 3, + ULP_THOR_SYM_EM_WM_OPCODE_OP_CT_MISS_DEF = 0, + ULP_THOR_SYM_EM_WM_OPCODE_OP_CT_HIT_DEF = 0, ULP_THOR_SYM_EM_WM_OPCODE_OP_RECYCLE = 4, ULP_THOR_SYM_POP_VLAN_NO = 0, ULP_THOR_SYM_POP_VLAN_YES = 1, @@ -1464,2644 +1663,298 @@ enum ulp_thor_sym { ULP_THOR_SYM_L2_ROE_ETYPE = 64573 }; -enum bnxt_ulp_class_hid { - BNXT_ULP_CLASS_HID_00b8 = 0x00b8, - BNXT_ULP_CLASS_HID_0cc2 = 0x0cc2, - BNXT_ULP_CLASS_HID_10e4 = 0x10e4, - BNXT_ULP_CLASS_HID_1d0e = 0x1d0e, - BNXT_ULP_CLASS_HID_0286 = 0x0286, - BNXT_ULP_CLASS_HID_0e98 = 0x0e98, - BNXT_ULP_CLASS_HID_1666 = 0x1666, - BNXT_ULP_CLASS_HID_02de = 0x02de, - BNXT_ULP_CLASS_HID_81d25 = 0x81d25, - BNXT_ULP_CLASS_HID_809ad = 0x809ad, - BNXT_ULP_CLASS_HID_80ae3 = 0x80ae3, - BNXT_ULP_CLASS_HID_8170d = 0x8170d, - BNXT_ULP_CLASS_HID_80773 = 0x80773, - BNXT_ULP_CLASS_HID_8139d = 0x8139d, - BNXT_ULP_CLASS_HID_814d3 = 0x814d3, - BNXT_ULP_CLASS_HID_8015b = 0x8015b, - BNXT_ULP_CLASS_HID_21977 = 0x21977, - BNXT_ULP_CLASS_HID_205ef = 0x205ef, - BNXT_ULP_CLASS_HID_20735 = 0x20735, - BNXT_ULP_CLASS_HID_2134f = 0x2134f, - BNXT_ULP_CLASS_HID_61beb = 0x61beb, - BNXT_ULP_CLASS_HID_60863 = 0x60863, - BNXT_ULP_CLASS_HID_609a9 = 0x609a9, - BNXT_ULP_CLASS_HID_615c3 = 0x615c3, - BNXT_ULP_CLASS_HID_00a8 = 0x00a8, - BNXT_ULP_CLASS_HID_0cd2 = 0x0cd2, - BNXT_ULP_CLASS_HID_10f4 = 0x10f4, - BNXT_ULP_CLASS_HID_1d1e = 0x1d1e, - BNXT_ULP_CLASS_HID_1488 = 0x1488, - BNXT_ULP_CLASS_HID_0110 = 0x0110, - BNXT_ULP_CLASS_HID_0532 = 0x0532, - BNXT_ULP_CLASS_HID_115c = 0x115c, - BNXT_ULP_CLASS_HID_0ab8 = 0x0ab8, - BNXT_ULP_CLASS_HID_16a2 = 0x16a2, - BNXT_ULP_CLASS_HID_1ac4 = 0x1ac4, - BNXT_ULP_CLASS_HID_074c = 0x074c, - BNXT_ULP_CLASS_HID_1e98 = 0x1e98, - BNXT_ULP_CLASS_HID_0ae0 = 0x0ae0, - BNXT_ULP_CLASS_HID_0f02 = 0x0f02, - BNXT_ULP_CLASS_HID_1b2c = 0x1b2c, - BNXT_ULP_CLASS_HID_0296 = 0x0296, - BNXT_ULP_CLASS_HID_0e88 = 0x0e88, - BNXT_ULP_CLASS_HID_1676 = 0x1676, - BNXT_ULP_CLASS_HID_02ce = 0x02ce, - BNXT_ULP_CLASS_HID_8076e = 0x8076e, - BNXT_ULP_CLASS_HID_81380 = 0x81380, - BNXT_ULP_CLASS_HID_81b4e = 0x81b4e, - BNXT_ULP_CLASS_HID_807c6 = 0x807c6, - BNXT_ULP_CLASS_HID_404ea = 0x404ea, - BNXT_ULP_CLASS_HID_4110c = 0x4110c, - BNXT_ULP_CLASS_HID_418ca = 0x418ca, - BNXT_ULP_CLASS_HID_40542 = 0x40542, - BNXT_ULP_CLASS_HID_c09e2 = 0xc09e2, - BNXT_ULP_CLASS_HID_c1604 = 0xc1604, - BNXT_ULP_CLASS_HID_c1dc2 = 0xc1dc2, - BNXT_ULP_CLASS_HID_c0a5a = 0xc0a5a, - BNXT_ULP_CLASS_HID_0098 = 0x0098, - BNXT_ULP_CLASS_HID_0ce2 = 0x0ce2, - BNXT_ULP_CLASS_HID_10c4 = 0x10c4, - BNXT_ULP_CLASS_HID_1d2e = 0x1d2e, - BNXT_ULP_CLASS_HID_14b8 = 0x14b8, - BNXT_ULP_CLASS_HID_0120 = 0x0120, - BNXT_ULP_CLASS_HID_0502 = 0x0502, - BNXT_ULP_CLASS_HID_116c = 0x116c, - BNXT_ULP_CLASS_HID_0a88 = 0x0a88, - BNXT_ULP_CLASS_HID_1692 = 0x1692, - BNXT_ULP_CLASS_HID_1af4 = 0x1af4, - BNXT_ULP_CLASS_HID_077c = 0x077c, - BNXT_ULP_CLASS_HID_1ea8 = 0x1ea8, - BNXT_ULP_CLASS_HID_0ad0 = 0x0ad0, - BNXT_ULP_CLASS_HID_0f32 = 0x0f32, - BNXT_ULP_CLASS_HID_1b1c = 0x1b1c, - BNXT_ULP_CLASS_HID_02a6 = 0x02a6, - BNXT_ULP_CLASS_HID_0eb8 = 0x0eb8, - BNXT_ULP_CLASS_HID_1646 = 0x1646, - BNXT_ULP_CLASS_HID_02fe = 0x02fe, - BNXT_ULP_CLASS_HID_8075e = 0x8075e, - BNXT_ULP_CLASS_HID_813b0 = 0x813b0, - BNXT_ULP_CLASS_HID_81b7e = 0x81b7e, - BNXT_ULP_CLASS_HID_807f6 = 0x807f6, - BNXT_ULP_CLASS_HID_404da = 0x404da, - BNXT_ULP_CLASS_HID_4113c = 0x4113c, - BNXT_ULP_CLASS_HID_418fa = 0x418fa, - BNXT_ULP_CLASS_HID_40572 = 0x40572, - BNXT_ULP_CLASS_HID_c09d2 = 0xc09d2, - BNXT_ULP_CLASS_HID_c1634 = 0xc1634, - BNXT_ULP_CLASS_HID_c1df2 = 0xc1df2, - BNXT_ULP_CLASS_HID_c0a6a = 0xc0a6a, - BNXT_ULP_CLASS_HID_81d35 = 0x81d35, - BNXT_ULP_CLASS_HID_809bd = 0x809bd, - BNXT_ULP_CLASS_HID_80af3 = 0x80af3, - BNXT_ULP_CLASS_HID_8171d = 0x8171d, - BNXT_ULP_CLASS_HID_80763 = 0x80763, - BNXT_ULP_CLASS_HID_8138d = 0x8138d, - BNXT_ULP_CLASS_HID_814c3 = 0x814c3, - BNXT_ULP_CLASS_HID_8014b = 0x8014b, - BNXT_ULP_CLASS_HID_c001f = 0xc001f, - BNXT_ULP_CLASS_HID_c0c39 = 0xc0c39, - BNXT_ULP_CLASS_HID_c0d7f = 0xc0d7f, - BNXT_ULP_CLASS_HID_c1999 = 0xc1999, - BNXT_ULP_CLASS_HID_c09ef = 0xc09ef, - BNXT_ULP_CLASS_HID_c1609 = 0xc1609, - BNXT_ULP_CLASS_HID_c174f = 0xc174f, - BNXT_ULP_CLASS_HID_c03d7 = 0xc03d7, - BNXT_ULP_CLASS_HID_a1e73 = 0xa1e73, - BNXT_ULP_CLASS_HID_a0afb = 0xa0afb, - BNXT_ULP_CLASS_HID_a0c31 = 0xa0c31, - BNXT_ULP_CLASS_HID_a185b = 0xa185b, - BNXT_ULP_CLASS_HID_a08a1 = 0xa08a1, - BNXT_ULP_CLASS_HID_a14cb = 0xa14cb, - BNXT_ULP_CLASS_HID_a1601 = 0xa1601, - BNXT_ULP_CLASS_HID_a0289 = 0xa0289, - BNXT_ULP_CLASS_HID_e015d = 0xe015d, - BNXT_ULP_CLASS_HID_e0d47 = 0xe0d47, - BNXT_ULP_CLASS_HID_e0ebd = 0xe0ebd, - BNXT_ULP_CLASS_HID_e1aa7 = 0xe1aa7, - BNXT_ULP_CLASS_HID_e0b2d = 0xe0b2d, - BNXT_ULP_CLASS_HID_e1757 = 0xe1757, - BNXT_ULP_CLASS_HID_e188d = 0xe188d, - BNXT_ULP_CLASS_HID_e0515 = 0xe0515, - BNXT_ULP_CLASS_HID_21967 = 0x21967, - BNXT_ULP_CLASS_HID_205ff = 0x205ff, - BNXT_ULP_CLASS_HID_20725 = 0x20725, - BNXT_ULP_CLASS_HID_2135f = 0x2135f, - BNXT_ULP_CLASS_HID_61bfb = 0x61bfb, - BNXT_ULP_CLASS_HID_60873 = 0x60873, - BNXT_ULP_CLASS_HID_609b9 = 0x609b9, - BNXT_ULP_CLASS_HID_615d3 = 0x615d3, - BNXT_ULP_CLASS_HID_30a55 = 0x30a55, - BNXT_ULP_CLASS_HID_3164f = 0x3164f, - BNXT_ULP_CLASS_HID_317b5 = 0x317b5, - BNXT_ULP_CLASS_HID_3040d = 0x3040d, - BNXT_ULP_CLASS_HID_70ca9 = 0x70ca9, - BNXT_ULP_CLASS_HID_718c3 = 0x718c3, - BNXT_ULP_CLASS_HID_71a09 = 0x71a09, - BNXT_ULP_CLASS_HID_70681 = 0x70681, - BNXT_ULP_CLASS_HID_2821d = 0x2821d, - BNXT_ULP_CLASS_HID_28e37 = 0x28e37, - BNXT_ULP_CLASS_HID_28f7d = 0x28f7d, - BNXT_ULP_CLASS_HID_29b97 = 0x29b97, - BNXT_ULP_CLASS_HID_68491 = 0x68491, - BNXT_ULP_CLASS_HID_6908b = 0x6908b, - BNXT_ULP_CLASS_HID_691f1 = 0x691f1, - BNXT_ULP_CLASS_HID_69deb = 0x69deb, - BNXT_ULP_CLASS_HID_3926d = 0x3926d, - BNXT_ULP_CLASS_HID_39e87 = 0x39e87, - BNXT_ULP_CLASS_HID_38023 = 0x38023, - BNXT_ULP_CLASS_HID_38c45 = 0x38c45, - BNXT_ULP_CLASS_HID_794e1 = 0x794e1, - BNXT_ULP_CLASS_HID_78179 = 0x78179, - BNXT_ULP_CLASS_HID_782a7 = 0x782a7, - BNXT_ULP_CLASS_HID_78ed9 = 0x78ed9, - BNXT_ULP_CLASS_HID_81d05 = 0x81d05, - BNXT_ULP_CLASS_HID_8098d = 0x8098d, - BNXT_ULP_CLASS_HID_80ac3 = 0x80ac3, - BNXT_ULP_CLASS_HID_8172d = 0x8172d, - BNXT_ULP_CLASS_HID_80753 = 0x80753, - BNXT_ULP_CLASS_HID_813bd = 0x813bd, - BNXT_ULP_CLASS_HID_814f3 = 0x814f3, - BNXT_ULP_CLASS_HID_8017b = 0x8017b, - BNXT_ULP_CLASS_HID_c002f = 0xc002f, - BNXT_ULP_CLASS_HID_c0c09 = 0xc0c09, - BNXT_ULP_CLASS_HID_c0d4f = 0xc0d4f, - BNXT_ULP_CLASS_HID_c19a9 = 0xc19a9, - BNXT_ULP_CLASS_HID_c09df = 0xc09df, - BNXT_ULP_CLASS_HID_c1639 = 0xc1639, - BNXT_ULP_CLASS_HID_c177f = 0xc177f, - BNXT_ULP_CLASS_HID_c03e7 = 0xc03e7, - BNXT_ULP_CLASS_HID_a1e43 = 0xa1e43, - BNXT_ULP_CLASS_HID_a0acb = 0xa0acb, - BNXT_ULP_CLASS_HID_a0c01 = 0xa0c01, - BNXT_ULP_CLASS_HID_a186b = 0xa186b, - BNXT_ULP_CLASS_HID_a0891 = 0xa0891, - BNXT_ULP_CLASS_HID_a14fb = 0xa14fb, - BNXT_ULP_CLASS_HID_a1631 = 0xa1631, - BNXT_ULP_CLASS_HID_a02b9 = 0xa02b9, - BNXT_ULP_CLASS_HID_e016d = 0xe016d, - BNXT_ULP_CLASS_HID_e0d77 = 0xe0d77, - BNXT_ULP_CLASS_HID_e0e8d = 0xe0e8d, - BNXT_ULP_CLASS_HID_e1a97 = 0xe1a97, - BNXT_ULP_CLASS_HID_e0b1d = 0xe0b1d, - BNXT_ULP_CLASS_HID_e1767 = 0xe1767, - BNXT_ULP_CLASS_HID_e18bd = 0xe18bd, - BNXT_ULP_CLASS_HID_e0525 = 0xe0525, - BNXT_ULP_CLASS_HID_21957 = 0x21957, - BNXT_ULP_CLASS_HID_205cf = 0x205cf, - BNXT_ULP_CLASS_HID_20715 = 0x20715, - BNXT_ULP_CLASS_HID_2136f = 0x2136f, - BNXT_ULP_CLASS_HID_61bcb = 0x61bcb, - BNXT_ULP_CLASS_HID_60843 = 0x60843, - BNXT_ULP_CLASS_HID_60989 = 0x60989, - BNXT_ULP_CLASS_HID_615e3 = 0x615e3, - BNXT_ULP_CLASS_HID_30a65 = 0x30a65, - BNXT_ULP_CLASS_HID_3167f = 0x3167f, - BNXT_ULP_CLASS_HID_31785 = 0x31785, - BNXT_ULP_CLASS_HID_3043d = 0x3043d, - BNXT_ULP_CLASS_HID_70c99 = 0x70c99, - BNXT_ULP_CLASS_HID_718f3 = 0x718f3, - BNXT_ULP_CLASS_HID_71a39 = 0x71a39, - BNXT_ULP_CLASS_HID_706b1 = 0x706b1, - BNXT_ULP_CLASS_HID_2822d = 0x2822d, - BNXT_ULP_CLASS_HID_28e07 = 0x28e07, - BNXT_ULP_CLASS_HID_28f4d = 0x28f4d, - BNXT_ULP_CLASS_HID_29ba7 = 0x29ba7, - BNXT_ULP_CLASS_HID_684a1 = 0x684a1, - BNXT_ULP_CLASS_HID_690bb = 0x690bb, - BNXT_ULP_CLASS_HID_691c1 = 0x691c1, - BNXT_ULP_CLASS_HID_69ddb = 0x69ddb, - BNXT_ULP_CLASS_HID_3925d = 0x3925d, - BNXT_ULP_CLASS_HID_39eb7 = 0x39eb7, - BNXT_ULP_CLASS_HID_38013 = 0x38013, - BNXT_ULP_CLASS_HID_38c75 = 0x38c75, - BNXT_ULP_CLASS_HID_794d1 = 0x794d1, - BNXT_ULP_CLASS_HID_78149 = 0x78149, - BNXT_ULP_CLASS_HID_78297 = 0x78297, - BNXT_ULP_CLASS_HID_78ee9 = 0x78ee9, - BNXT_ULP_CLASS_HID_0816 = 0x0816, - BNXT_ULP_CLASS_HID_1852 = 0x1852, - BNXT_ULP_CLASS_HID_09f4 = 0x09f4, - BNXT_ULP_CLASS_HID_1dd4 = 0x1dd4, - BNXT_ULP_CLASS_HID_804f1 = 0x804f1, - BNXT_ULP_CLASS_HID_81251 = 0x81251, - BNXT_ULP_CLASS_HID_80ee1 = 0x80ee1, - BNXT_ULP_CLASS_HID_81c41 = 0x81c41, - BNXT_ULP_CLASS_HID_2013b = 0x2013b, - BNXT_ULP_CLASS_HID_20e9b = 0x20e9b, - BNXT_ULP_CLASS_HID_603bf = 0x603bf, - BNXT_ULP_CLASS_HID_6111f = 0x6111f, - BNXT_ULP_CLASS_HID_0806 = 0x0806, - BNXT_ULP_CLASS_HID_1842 = 0x1842, - BNXT_ULP_CLASS_HID_1be6 = 0x1be6, - BNXT_ULP_CLASS_HID_0c80 = 0x0c80, - BNXT_ULP_CLASS_HID_1216 = 0x1216, - BNXT_ULP_CLASS_HID_02b0 = 0x02b0, - BNXT_ULP_CLASS_HID_0654 = 0x0654, - BNXT_ULP_CLASS_HID_1690 = 0x1690, - BNXT_ULP_CLASS_HID_09e4 = 0x09e4, - BNXT_ULP_CLASS_HID_1dc4 = 0x1dc4, - BNXT_ULP_CLASS_HID_80efc = 0x80efc, - BNXT_ULP_CLASS_HID_80332 = 0x80332, - BNXT_ULP_CLASS_HID_40c78 = 0x40c78, - BNXT_ULP_CLASS_HID_400be = 0x400be, - BNXT_ULP_CLASS_HID_c1170 = 0xc1170, - BNXT_ULP_CLASS_HID_c05b6 = 0xc05b6, - BNXT_ULP_CLASS_HID_0836 = 0x0836, - BNXT_ULP_CLASS_HID_1872 = 0x1872, - BNXT_ULP_CLASS_HID_1bd6 = 0x1bd6, - BNXT_ULP_CLASS_HID_0cb0 = 0x0cb0, - BNXT_ULP_CLASS_HID_1226 = 0x1226, - BNXT_ULP_CLASS_HID_0280 = 0x0280, - BNXT_ULP_CLASS_HID_0664 = 0x0664, - BNXT_ULP_CLASS_HID_16a0 = 0x16a0, - BNXT_ULP_CLASS_HID_09d4 = 0x09d4, - BNXT_ULP_CLASS_HID_1df4 = 0x1df4, - BNXT_ULP_CLASS_HID_80ecc = 0x80ecc, - BNXT_ULP_CLASS_HID_80302 = 0x80302, - BNXT_ULP_CLASS_HID_40c48 = 0x40c48, - BNXT_ULP_CLASS_HID_4008e = 0x4008e, - BNXT_ULP_CLASS_HID_c1140 = 0xc1140, - BNXT_ULP_CLASS_HID_c0586 = 0xc0586, - BNXT_ULP_CLASS_HID_804e1 = 0x804e1, - BNXT_ULP_CLASS_HID_81241 = 0x81241, - BNXT_ULP_CLASS_HID_80ef1 = 0x80ef1, - BNXT_ULP_CLASS_HID_81c51 = 0x81c51, - BNXT_ULP_CLASS_HID_c076d = 0xc076d, - BNXT_ULP_CLASS_HID_c14cd = 0xc14cd, - BNXT_ULP_CLASS_HID_c117d = 0xc117d, - BNXT_ULP_CLASS_HID_c1edd = 0xc1edd, - BNXT_ULP_CLASS_HID_a062f = 0xa062f, - BNXT_ULP_CLASS_HID_a138f = 0xa138f, - BNXT_ULP_CLASS_HID_a103f = 0xa103f, - BNXT_ULP_CLASS_HID_a1d9f = 0xa1d9f, - BNXT_ULP_CLASS_HID_e08ab = 0xe08ab, - BNXT_ULP_CLASS_HID_e160b = 0xe160b, - BNXT_ULP_CLASS_HID_e12bb = 0xe12bb, - BNXT_ULP_CLASS_HID_e0079 = 0xe0079, - BNXT_ULP_CLASS_HID_2012b = 0x2012b, - BNXT_ULP_CLASS_HID_20e8b = 0x20e8b, - BNXT_ULP_CLASS_HID_603af = 0x603af, - BNXT_ULP_CLASS_HID_6110f = 0x6110f, - BNXT_ULP_CLASS_HID_311bb = 0x311bb, - BNXT_ULP_CLASS_HID_31f1b = 0x31f1b, - BNXT_ULP_CLASS_HID_7143f = 0x7143f, - BNXT_ULP_CLASS_HID_701fd = 0x701fd, - BNXT_ULP_CLASS_HID_28963 = 0x28963, - BNXT_ULP_CLASS_HID_296c3 = 0x296c3, - BNXT_ULP_CLASS_HID_68be7 = 0x68be7, - BNXT_ULP_CLASS_HID_69947 = 0x69947, - BNXT_ULP_CLASS_HID_399f3 = 0x399f3, - BNXT_ULP_CLASS_HID_387b1 = 0x387b1, - BNXT_ULP_CLASS_HID_79c77 = 0x79c77, - BNXT_ULP_CLASS_HID_78a35 = 0x78a35, - BNXT_ULP_CLASS_HID_804d1 = 0x804d1, - BNXT_ULP_CLASS_HID_81271 = 0x81271, - BNXT_ULP_CLASS_HID_80ec1 = 0x80ec1, - BNXT_ULP_CLASS_HID_81c61 = 0x81c61, - BNXT_ULP_CLASS_HID_c075d = 0xc075d, - BNXT_ULP_CLASS_HID_c14fd = 0xc14fd, - BNXT_ULP_CLASS_HID_c114d = 0xc114d, - BNXT_ULP_CLASS_HID_c1eed = 0xc1eed, - BNXT_ULP_CLASS_HID_a061f = 0xa061f, - BNXT_ULP_CLASS_HID_a13bf = 0xa13bf, - BNXT_ULP_CLASS_HID_a100f = 0xa100f, - BNXT_ULP_CLASS_HID_a1daf = 0xa1daf, - BNXT_ULP_CLASS_HID_e089b = 0xe089b, - BNXT_ULP_CLASS_HID_e163b = 0xe163b, - BNXT_ULP_CLASS_HID_e128b = 0xe128b, - BNXT_ULP_CLASS_HID_e0049 = 0xe0049, - BNXT_ULP_CLASS_HID_2011b = 0x2011b, - BNXT_ULP_CLASS_HID_20ebb = 0x20ebb, - BNXT_ULP_CLASS_HID_6039f = 0x6039f, - BNXT_ULP_CLASS_HID_6113f = 0x6113f, - BNXT_ULP_CLASS_HID_3118b = 0x3118b, - BNXT_ULP_CLASS_HID_31f2b = 0x31f2b, - BNXT_ULP_CLASS_HID_7140f = 0x7140f, - BNXT_ULP_CLASS_HID_701cd = 0x701cd, - BNXT_ULP_CLASS_HID_28953 = 0x28953, - BNXT_ULP_CLASS_HID_296f3 = 0x296f3, - BNXT_ULP_CLASS_HID_68bd7 = 0x68bd7, - BNXT_ULP_CLASS_HID_69977 = 0x69977, - BNXT_ULP_CLASS_HID_399c3 = 0x399c3, - BNXT_ULP_CLASS_HID_38781 = 0x38781, - BNXT_ULP_CLASS_HID_79c47 = 0x79c47, - BNXT_ULP_CLASS_HID_78a05 = 0x78a05, - BNXT_ULP_CLASS_HID_04a4 = 0x04a4, - BNXT_ULP_CLASS_HID_04a8 = 0x04a8, - BNXT_ULP_CLASS_HID_04a5 = 0x04a5, - BNXT_ULP_CLASS_HID_1205 = 0x1205, - BNXT_ULP_CLASS_HID_04a9 = 0x04a9, - BNXT_ULP_CLASS_HID_1209 = 0x1209, - BNXT_ULP_CLASS_HID_04b4 = 0x04b4, - BNXT_ULP_CLASS_HID_04b8 = 0x04b8, - BNXT_ULP_CLASS_HID_0484 = 0x0484, - BNXT_ULP_CLASS_HID_0488 = 0x0488, - BNXT_ULP_CLASS_HID_04b5 = 0x04b5, - BNXT_ULP_CLASS_HID_1215 = 0x1215, - BNXT_ULP_CLASS_HID_04b9 = 0x04b9, - BNXT_ULP_CLASS_HID_1219 = 0x1219, - BNXT_ULP_CLASS_HID_0485 = 0x0485, - BNXT_ULP_CLASS_HID_1225 = 0x1225, - BNXT_ULP_CLASS_HID_0489 = 0x0489, - BNXT_ULP_CLASS_HID_1229 = 0x1229, - BNXT_ULP_CLASS_HID_0226 = 0x0226, - BNXT_ULP_CLASS_HID_4045a = 0x4045a, - BNXT_ULP_CLASS_HID_0daa = 0x0daa, - BNXT_ULP_CLASS_HID_11b0 = 0x11b0, - BNXT_ULP_CLASS_HID_403f8 = 0x403f8, - BNXT_ULP_CLASS_HID_4161e = 0x4161e, - BNXT_ULP_CLASS_HID_40439 = 0x40439, - BNXT_ULP_CLASS_HID_41405 = 0x41405, - BNXT_ULP_CLASS_HID_51449 = 0x51449, - BNXT_ULP_CLASS_HID_50b33 = 0x50b33, - BNXT_ULP_CLASS_HID_48c01 = 0x48c01, - BNXT_ULP_CLASS_HID_483eb = 0x483eb, - BNXT_ULP_CLASS_HID_5833f = 0x5833f, - BNXT_ULP_CLASS_HID_5937b = 0x5937b, - BNXT_ULP_CLASS_HID_41875 = 0x41875, - BNXT_ULP_CLASS_HID_40f5f = 0x40f5f, - BNXT_ULP_CLASS_HID_50f23 = 0x50f23, - BNXT_ULP_CLASS_HID_51f6f = 0x51f6f, - BNXT_ULP_CLASS_HID_4875b = 0x4875b, - BNXT_ULP_CLASS_HID_49727 = 0x49727, - BNXT_ULP_CLASS_HID_5976b = 0x5976b, - BNXT_ULP_CLASS_HID_58655 = 0x58655, - BNXT_ULP_CLASS_HID_4125f = 0x4125f, - BNXT_ULP_CLASS_HID_401f9 = 0x401f9, - BNXT_ULP_CLASS_HID_501cd = 0x501cd, - BNXT_ULP_CLASS_HID_51149 = 0x51149, - BNXT_ULP_CLASS_HID_49a67 = 0x49a67, - BNXT_ULP_CLASS_HID_489c1 = 0x489c1, - BNXT_ULP_CLASS_HID_58955 = 0x58955, - BNXT_ULP_CLASS_HID_59951 = 0x59951, - BNXT_ULP_CLASS_HID_40569 = 0x40569, - BNXT_ULP_CLASS_HID_41575 = 0x41575, - BNXT_ULP_CLASS_HID_51579 = 0x51579, - BNXT_ULP_CLASS_HID_50463 = 0x50463, - BNXT_ULP_CLASS_HID_48d71 = 0x48d71, - BNXT_ULP_CLASS_HID_49d7d = 0x49d7d, - BNXT_ULP_CLASS_HID_59d41 = 0x59d41, - BNXT_ULP_CLASS_HID_58c6b = 0x58c6b, - BNXT_ULP_CLASS_HID_10255 = 0x10255, - BNXT_ULP_CLASS_HID_11675 = 0x11675, - BNXT_ULP_CLASS_HID_14649 = 0x14649, - BNXT_ULP_CLASS_HID_15a69 = 0x15a69, - BNXT_ULP_CLASS_HID_1205b = 0x1205b, - BNXT_ULP_CLASS_HID_1347b = 0x1347b, - BNXT_ULP_CLASS_HID_16bbf = 0x16bbf, - BNXT_ULP_CLASS_HID_1785f = 0x1785f, - BNXT_ULP_CLASS_HID_11551 = 0x11551, - BNXT_ULP_CLASS_HID_10897 = 0x10897, - BNXT_ULP_CLASS_HID_15955 = 0x15955, - BNXT_ULP_CLASS_HID_14c8b = 0x14c8b, - BNXT_ULP_CLASS_HID_13b47 = 0x13b47, - BNXT_ULP_CLASS_HID_12e85 = 0x12e85, - BNXT_ULP_CLASS_HID_17f5b = 0x17f5b, - BNXT_ULP_CLASS_HID_17299 = 0x17299, - BNXT_ULP_CLASS_HID_10fe7 = 0x10fe7, - BNXT_ULP_CLASS_HID_10325 = 0x10325, - BNXT_ULP_CLASS_HID_153cb = 0x153cb, - BNXT_ULP_CLASS_HID_14709 = 0x14709, - BNXT_ULP_CLASS_HID_12dc5 = 0x12dc5, - BNXT_ULP_CLASS_HID_1212b = 0x1212b, - BNXT_ULP_CLASS_HID_171c9 = 0x171c9, - BNXT_ULP_CLASS_HID_1650f = 0x1650f, - BNXT_ULP_CLASS_HID_10201 = 0x10201, - BNXT_ULP_CLASS_HID_116c1 = 0x116c1, - BNXT_ULP_CLASS_HID_14605 = 0x14605, - BNXT_ULP_CLASS_HID_15a05 = 0x15a05, - BNXT_ULP_CLASS_HID_12007 = 0x12007, - BNXT_ULP_CLASS_HID_13407 = 0x13407, - BNXT_ULP_CLASS_HID_1640b = 0x1640b, - BNXT_ULP_CLASS_HID_1780b = 0x1780b, - BNXT_ULP_CLASS_HID_404b0 = 0x404b0, - BNXT_ULP_CLASS_HID_4148c = 0x4148c, - BNXT_ULP_CLASS_HID_514c0 = 0x514c0, - BNXT_ULP_CLASS_HID_50bba = 0x50bba, - BNXT_ULP_CLASS_HID_48c88 = 0x48c88, - BNXT_ULP_CLASS_HID_48362 = 0x48362, - BNXT_ULP_CLASS_HID_583b6 = 0x583b6, - BNXT_ULP_CLASS_HID_593f2 = 0x593f2, - BNXT_ULP_CLASS_HID_41f54 = 0x41f54, - BNXT_ULP_CLASS_HID_40fce = 0x40fce, - BNXT_ULP_CLASS_HID_50e02 = 0x50e02, - BNXT_ULP_CLASS_HID_51e5e = 0x51e5e, - BNXT_ULP_CLASS_HID_487ca = 0x487ca, - BNXT_ULP_CLASS_HID_49606 = 0x49606, - BNXT_ULP_CLASS_HID_5965a = 0x5965a, - BNXT_ULP_CLASS_HID_58514 = 0x58514, - BNXT_ULP_CLASS_HID_412c2 = 0x412c2, - BNXT_ULP_CLASS_HID_401ac = 0x401ac, - BNXT_ULP_CLASS_HID_501e0 = 0x501e0, - BNXT_ULP_CLASS_HID_511cc = 0x511cc, - BNXT_ULP_CLASS_HID_4990a = 0x4990a, - BNXT_ULP_CLASS_HID_489e4 = 0x489e4, - BNXT_ULP_CLASS_HID_589c8 = 0x589c8, - BNXT_ULP_CLASS_HID_59804 = 0x59804, - BNXT_ULP_CLASS_HID_40404 = 0x40404, - BNXT_ULP_CLASS_HID_41440 = 0x41440, - BNXT_ULP_CLASS_HID_51484 = 0x51484, - BNXT_ULP_CLASS_HID_50b0e = 0x50b0e, - BNXT_ULP_CLASS_HID_48c4c = 0x48c4c, - BNXT_ULP_CLASS_HID_48306 = 0x48306, - BNXT_ULP_CLASS_HID_5830a = 0x5830a, - BNXT_ULP_CLASS_HID_59346 = 0x59346, - BNXT_ULP_CLASS_HID_102cc = 0x102cc, - BNXT_ULP_CLASS_HID_116ec = 0x116ec, - BNXT_ULP_CLASS_HID_146d0 = 0x146d0, - BNXT_ULP_CLASS_HID_15af0 = 0x15af0, - BNXT_ULP_CLASS_HID_120c2 = 0x120c2, - BNXT_ULP_CLASS_HID_134e2 = 0x134e2, - BNXT_ULP_CLASS_HID_16b26 = 0x16b26, - BNXT_ULP_CLASS_HID_178c6 = 0x178c6, - BNXT_ULP_CLASS_HID_115c6 = 0x115c6, - BNXT_ULP_CLASS_HID_10804 = 0x10804, - BNXT_ULP_CLASS_HID_15822 = 0x15822, - BNXT_ULP_CLASS_HID_14c60 = 0x14c60, - BNXT_ULP_CLASS_HID_13bd4 = 0x13bd4, - BNXT_ULP_CLASS_HID_12e12 = 0x12e12, - BNXT_ULP_CLASS_HID_17e30 = 0x17e30, - BNXT_ULP_CLASS_HID_17276 = 0x17276, - BNXT_ULP_CLASS_HID_11f1a = 0x11f1a, - BNXT_ULP_CLASS_HID_11358 = 0x11358, - BNXT_ULP_CLASS_HID_14398 = 0x14398, - BNXT_ULP_CLASS_HID_157b8 = 0x157b8, - BNXT_ULP_CLASS_HID_13d68 = 0x13d68, - BNXT_ULP_CLASS_HID_131aa = 0x131aa, - BNXT_ULP_CLASS_HID_16192 = 0x16192, - BNXT_ULP_CLASS_HID_175b2 = 0x175b2, - BNXT_ULP_CLASS_HID_112b2 = 0x112b2, - BNXT_ULP_CLASS_HID_106f0 = 0x106f0, - BNXT_ULP_CLASS_HID_15692 = 0x15692, - BNXT_ULP_CLASS_HID_14ad0 = 0x14ad0, - BNXT_ULP_CLASS_HID_13080 = 0x13080, - BNXT_ULP_CLASS_HID_124c2 = 0x124c2, - BNXT_ULP_CLASS_HID_174e0 = 0x174e0, - BNXT_ULP_CLASS_HID_16f22 = 0x16f22, - BNXT_ULP_CLASS_HID_4025b = 0x4025b, - BNXT_ULP_CLASS_HID_41267 = 0x41267, - BNXT_ULP_CLASS_HID_5122b = 0x5122b, - BNXT_ULP_CLASS_HID_50d51 = 0x50d51, - BNXT_ULP_CLASS_HID_48a63 = 0x48a63, - BNXT_ULP_CLASS_HID_48589 = 0x48589, - BNXT_ULP_CLASS_HID_5855d = 0x5855d, - BNXT_ULP_CLASS_HID_59519 = 0x59519, - BNXT_ULP_CLASS_HID_41e17 = 0x41e17, - BNXT_ULP_CLASS_HID_4093d = 0x4093d, - BNXT_ULP_CLASS_HID_50941 = 0x50941, - BNXT_ULP_CLASS_HID_5190d = 0x5190d, - BNXT_ULP_CLASS_HID_48139 = 0x48139, - BNXT_ULP_CLASS_HID_49145 = 0x49145, - BNXT_ULP_CLASS_HID_59109 = 0x59109, - BNXT_ULP_CLASS_HID_58037 = 0x58037, - BNXT_ULP_CLASS_HID_4143d = 0x4143d, - BNXT_ULP_CLASS_HID_4079b = 0x4079b, - BNXT_ULP_CLASS_HID_507af = 0x507af, - BNXT_ULP_CLASS_HID_5172b = 0x5172b, - BNXT_ULP_CLASS_HID_49c05 = 0x49c05, - BNXT_ULP_CLASS_HID_48fa3 = 0x48fa3, - BNXT_ULP_CLASS_HID_58f37 = 0x58f37, - BNXT_ULP_CLASS_HID_59f33 = 0x59f33, - BNXT_ULP_CLASS_HID_4030b = 0x4030b, - BNXT_ULP_CLASS_HID_41317 = 0x41317, - BNXT_ULP_CLASS_HID_5131b = 0x5131b, - BNXT_ULP_CLASS_HID_50201 = 0x50201, - BNXT_ULP_CLASS_HID_48b13 = 0x48b13, - BNXT_ULP_CLASS_HID_49b1f = 0x49b1f, - BNXT_ULP_CLASS_HID_59b23 = 0x59b23, - BNXT_ULP_CLASS_HID_58a09 = 0x58a09, - BNXT_ULP_CLASS_HID_419bf = 0x419bf, - BNXT_ULP_CLASS_HID_40925 = 0x40925, - BNXT_ULP_CLASS_HID_508e9 = 0x508e9, - BNXT_ULP_CLASS_HID_518b5 = 0x518b5, - BNXT_ULP_CLASS_HID_48121 = 0x48121, - BNXT_ULP_CLASS_HID_490ed = 0x490ed, - BNXT_ULP_CLASS_HID_590b1 = 0x590b1, - BNXT_ULP_CLASS_HID_583ff = 0x583ff, - BNXT_ULP_CLASS_HID_41475 = 0x41475, - BNXT_ULP_CLASS_HID_40473 = 0x40473, - BNXT_ULP_CLASS_HID_50427 = 0x50427, - BNXT_ULP_CLASS_HID_51763 = 0x51763, - BNXT_ULP_CLASS_HID_49c3d = 0x49c3d, - BNXT_ULP_CLASS_HID_48c3b = 0x48c3b, - BNXT_ULP_CLASS_HID_58f6f = 0x58f6f, - BNXT_ULP_CLASS_HID_59f2b = 0x59f2b, - BNXT_ULP_CLASS_HID_40333 = 0x40333, - BNXT_ULP_CLASS_HID_412bf = 0x412bf, - BNXT_ULP_CLASS_HID_512a3 = 0x512a3, - BNXT_ULP_CLASS_HID_50229 = 0x50229, - BNXT_ULP_CLASS_HID_48abb = 0x48abb, - BNXT_ULP_CLASS_HID_49aa7 = 0x49aa7, - BNXT_ULP_CLASS_HID_59a2b = 0x59a2b, - BNXT_ULP_CLASS_HID_595b1 = 0x595b1, - BNXT_ULP_CLASS_HID_41e2f = 0x41e2f, - BNXT_ULP_CLASS_HID_40e35 = 0x40e35, - BNXT_ULP_CLASS_HID_50939 = 0x50939, - BNXT_ULP_CLASS_HID_51925 = 0x51925, - BNXT_ULP_CLASS_HID_48631 = 0x48631, - BNXT_ULP_CLASS_HID_4913d = 0x4913d, - BNXT_ULP_CLASS_HID_59121 = 0x59121, - BNXT_ULP_CLASS_HID_5812f = 0x5812f, - BNXT_ULP_CLASS_HID_41429 = 0x41429, - BNXT_ULP_CLASS_HID_40747 = 0x40747, - BNXT_ULP_CLASS_HID_5070b = 0x5070b, - BNXT_ULP_CLASS_HID_51727 = 0x51727, - BNXT_ULP_CLASS_HID_49fe1 = 0x49fe1, - BNXT_ULP_CLASS_HID_48f0f = 0x48f0f, - BNXT_ULP_CLASS_HID_58f23 = 0x58f23, - BNXT_ULP_CLASS_HID_59eef = 0x59eef, - BNXT_ULP_CLASS_HID_40347 = 0x40347, - BNXT_ULP_CLASS_HID_41303 = 0x41303, - BNXT_ULP_CLASS_HID_51247 = 0x51247, - BNXT_ULP_CLASS_HID_5026d = 0x5026d, - BNXT_ULP_CLASS_HID_48b0f = 0x48b0f, - BNXT_ULP_CLASS_HID_49a4b = 0x49a4b, - BNXT_ULP_CLASS_HID_59a0f = 0x59a0f, - BNXT_ULP_CLASS_HID_58a05 = 0x58a05, - BNXT_ULP_CLASS_HID_41983 = 0x41983, - BNXT_ULP_CLASS_HID_40929 = 0x40929, - BNXT_ULP_CLASS_HID_5092d = 0x5092d, - BNXT_ULP_CLASS_HID_518a9 = 0x518a9, - BNXT_ULP_CLASS_HID_48125 = 0x48125, - BNXT_ULP_CLASS_HID_49121 = 0x49121, - BNXT_ULP_CLASS_HID_59085 = 0x59085, - BNXT_ULP_CLASS_HID_58023 = 0x58023, - BNXT_ULP_CLASS_HID_41509 = 0x41509, - BNXT_ULP_CLASS_HID_40407 = 0x40407, - BNXT_ULP_CLASS_HID_5040b = 0x5040b, - BNXT_ULP_CLASS_HID_51407 = 0x51407, - BNXT_ULP_CLASS_HID_49d21 = 0x49d21, - BNXT_ULP_CLASS_HID_48c0f = 0x48c0f, - BNXT_ULP_CLASS_HID_58c03 = 0x58c03, - BNXT_ULP_CLASS_HID_59f0f = 0x59f0f, - BNXT_ULP_CLASS_HID_402ef = 0x402ef, - BNXT_ULP_CLASS_HID_412ab = 0x412ab, - BNXT_ULP_CLASS_HID_5126f = 0x5126f, - BNXT_ULP_CLASS_HID_50de5 = 0x50de5, - BNXT_ULP_CLASS_HID_48aa7 = 0x48aa7, - BNXT_ULP_CLASS_HID_485ed = 0x485ed, - BNXT_ULP_CLASS_HID_585e1 = 0x585e1, - BNXT_ULP_CLASS_HID_595ad = 0x595ad, - BNXT_ULP_CLASS_HID_41e6b = 0x41e6b, - BNXT_ULP_CLASS_HID_40961 = 0x40961, - BNXT_ULP_CLASS_HID_50925 = 0x50925, - BNXT_ULP_CLASS_HID_51961 = 0x51961, - BNXT_ULP_CLASS_HID_4816d = 0x4816d, - BNXT_ULP_CLASS_HID_49129 = 0x49129, - BNXT_ULP_CLASS_HID_5916d = 0x5916d, - BNXT_ULP_CLASS_HID_5806b = 0x5806b, - BNXT_ULP_CLASS_HID_414a1 = 0x414a1, - BNXT_ULP_CLASS_HID_4042f = 0x4042f, - BNXT_ULP_CLASS_HID_507a3 = 0x507a3, - BNXT_ULP_CLASS_HID_517af = 0x517af, - BNXT_ULP_CLASS_HID_49c29 = 0x49c29, - BNXT_ULP_CLASS_HID_48fa7 = 0x48fa7, - BNXT_ULP_CLASS_HID_58fab = 0x58fab, - BNXT_ULP_CLASS_HID_59f27 = 0x59f27, - BNXT_ULP_CLASS_HID_4032f = 0x4032f, - BNXT_ULP_CLASS_HID_4132b = 0x4132b, - BNXT_ULP_CLASS_HID_5132f = 0x5132f, - BNXT_ULP_CLASS_HID_50225 = 0x50225, - BNXT_ULP_CLASS_HID_48b27 = 0x48b27, - BNXT_ULP_CLASS_HID_49b23 = 0x49b23, - BNXT_ULP_CLASS_HID_59b27 = 0x59b27, - BNXT_ULP_CLASS_HID_58a2d = 0x58a2d, - BNXT_ULP_CLASS_HID_10437 = 0x10437, - BNXT_ULP_CLASS_HID_11017 = 0x11017, - BNXT_ULP_CLASS_HID_1402b = 0x1402b, - BNXT_ULP_CLASS_HID_15c0b = 0x15c0b, - BNXT_ULP_CLASS_HID_12639 = 0x12639, - BNXT_ULP_CLASS_HID_13219 = 0x13219, - BNXT_ULP_CLASS_HID_16ddd = 0x16ddd, - BNXT_ULP_CLASS_HID_17e3d = 0x17e3d, - BNXT_ULP_CLASS_HID_11333 = 0x11333, - BNXT_ULP_CLASS_HID_10ef5 = 0x10ef5, - BNXT_ULP_CLASS_HID_15f37 = 0x15f37, - BNXT_ULP_CLASS_HID_14ae9 = 0x14ae9, - BNXT_ULP_CLASS_HID_13d25 = 0x13d25, - BNXT_ULP_CLASS_HID_128e7 = 0x128e7, - BNXT_ULP_CLASS_HID_17939 = 0x17939, - BNXT_ULP_CLASS_HID_174fb = 0x174fb, - BNXT_ULP_CLASS_HID_10985 = 0x10985, - BNXT_ULP_CLASS_HID_10547 = 0x10547, - BNXT_ULP_CLASS_HID_155a9 = 0x155a9, - BNXT_ULP_CLASS_HID_1416b = 0x1416b, - BNXT_ULP_CLASS_HID_12ba7 = 0x12ba7, - BNXT_ULP_CLASS_HID_12749 = 0x12749, - BNXT_ULP_CLASS_HID_177ab = 0x177ab, - BNXT_ULP_CLASS_HID_1636d = 0x1636d, - BNXT_ULP_CLASS_HID_10463 = 0x10463, - BNXT_ULP_CLASS_HID_110a3 = 0x110a3, - BNXT_ULP_CLASS_HID_14067 = 0x14067, - BNXT_ULP_CLASS_HID_15c67 = 0x15c67, - BNXT_ULP_CLASS_HID_12665 = 0x12665, - BNXT_ULP_CLASS_HID_13265 = 0x13265, - BNXT_ULP_CLASS_HID_16269 = 0x16269, - BNXT_ULP_CLASS_HID_17e69 = 0x17e69, - BNXT_ULP_CLASS_HID_1133d = 0x1133d, - BNXT_ULP_CLASS_HID_10eff = 0x10eff, - BNXT_ULP_CLASS_HID_15ed9 = 0x15ed9, - BNXT_ULP_CLASS_HID_14a9b = 0x14a9b, - BNXT_ULP_CLASS_HID_13d2f = 0x13d2f, - BNXT_ULP_CLASS_HID_128e9 = 0x128e9, - BNXT_ULP_CLASS_HID_178cb = 0x178cb, - BNXT_ULP_CLASS_HID_1748d = 0x1748d, - BNXT_ULP_CLASS_HID_109fb = 0x109fb, - BNXT_ULP_CLASS_HID_105bd = 0x105bd, - BNXT_ULP_CLASS_HID_155bf = 0x155bf, - BNXT_ULP_CLASS_HID_14179 = 0x14179, - BNXT_ULP_CLASS_HID_12bed = 0x12bed, - BNXT_ULP_CLASS_HID_127af = 0x127af, - BNXT_ULP_CLASS_HID_177a9 = 0x177a9, - BNXT_ULP_CLASS_HID_1636b = 0x1636b, - BNXT_ULP_CLASS_HID_1046d = 0x1046d, - BNXT_ULP_CLASS_HID_1104d = 0x1104d, - BNXT_ULP_CLASS_HID_14009 = 0x14009, - BNXT_ULP_CLASS_HID_15c69 = 0x15c69, - BNXT_ULP_CLASS_HID_1260f = 0x1260f, - BNXT_ULP_CLASS_HID_1326f = 0x1326f, - BNXT_ULP_CLASS_HID_1622b = 0x1622b, - BNXT_ULP_CLASS_HID_17e0b = 0x17e0b, - BNXT_ULP_CLASS_HID_11369 = 0x11369, - BNXT_ULP_CLASS_HID_10f2b = 0x10f2b, - BNXT_ULP_CLASS_HID_15f6d = 0x15f6d, - BNXT_ULP_CLASS_HID_14b2f = 0x14b2f, - BNXT_ULP_CLASS_HID_13d6b = 0x13d6b, - BNXT_ULP_CLASS_HID_1292d = 0x1292d, - BNXT_ULP_CLASS_HID_1792f = 0x1792f, - BNXT_ULP_CLASS_HID_174e9 = 0x174e9, - BNXT_ULP_CLASS_HID_119e1 = 0x119e1, - BNXT_ULP_CLASS_HID_115a3 = 0x115a3, - BNXT_ULP_CLASS_HID_14563 = 0x14563, - BNXT_ULP_CLASS_HID_15143 = 0x15143, - BNXT_ULP_CLASS_HID_13b93 = 0x13b93, - BNXT_ULP_CLASS_HID_13751 = 0x13751, - BNXT_ULP_CLASS_HID_16769 = 0x16769, - BNXT_ULP_CLASS_HID_17349 = 0x17349, - BNXT_ULP_CLASS_HID_114ab = 0x114ab, - BNXT_ULP_CLASS_HID_10061 = 0x10061, - BNXT_ULP_CLASS_HID_15063 = 0x15063, - BNXT_ULP_CLASS_HID_14c21 = 0x14c21, - BNXT_ULP_CLASS_HID_13671 = 0x13671, - BNXT_ULP_CLASS_HID_12233 = 0x12233, - BNXT_ULP_CLASS_HID_17271 = 0x17271, - BNXT_ULP_CLASS_HID_16e33 = 0x16e33, - BNXT_ULP_CLASS_HID_102c1 = 0x102c1, - BNXT_ULP_CLASS_HID_11f21 = 0x11f21, - BNXT_ULP_CLASS_HID_14ee1 = 0x14ee1, - BNXT_ULP_CLASS_HID_15ac1 = 0x15ac1, - BNXT_ULP_CLASS_HID_12cc3 = 0x12cc3, - BNXT_ULP_CLASS_HID_13923 = 0x13923, - BNXT_ULP_CLASS_HID_168e3 = 0x168e3, - BNXT_ULP_CLASS_HID_164a9 = 0x164a9, - BNXT_ULP_CLASS_HID_11e29 = 0x11e29, - BNXT_ULP_CLASS_HID_115eb = 0x115eb, - BNXT_ULP_CLASS_HID_145a3 = 0x145a3, - BNXT_ULP_CLASS_HID_151a3 = 0x151a3, - BNXT_ULP_CLASS_HID_1382b = 0x1382b, - BNXT_ULP_CLASS_HID_137e1 = 0x137e1, - BNXT_ULP_CLASS_HID_167a1 = 0x167a1, - BNXT_ULP_CLASS_HID_173a1 = 0x173a1, - BNXT_ULP_CLASS_HID_11449 = 0x11449, - BNXT_ULP_CLASS_HID_1000b = 0x1000b, - BNXT_ULP_CLASS_HID_15069 = 0x15069, - BNXT_ULP_CLASS_HID_14c2b = 0x14c2b, - BNXT_ULP_CLASS_HID_1367b = 0x1367b, - BNXT_ULP_CLASS_HID_12239 = 0x12239, - BNXT_ULP_CLASS_HID_1721b = 0x1721b, - BNXT_ULP_CLASS_HID_169d9 = 0x169d9, - BNXT_ULP_CLASS_HID_1033b = 0x1033b, - BNXT_ULP_CLASS_HID_11f3b = 0x11f3b, - BNXT_ULP_CLASS_HID_14f2b = 0x14f2b, - BNXT_ULP_CLASS_HID_15b2b = 0x15b2b, - BNXT_ULP_CLASS_HID_12d39 = 0x12d39, - BNXT_ULP_CLASS_HID_13939 = 0x13939, - BNXT_ULP_CLASS_HID_168f9 = 0x168f9, - BNXT_ULP_CLASS_HID_164bb = 0x164bb, - BNXT_ULP_CLASS_HID_119cb = 0x119cb, - BNXT_ULP_CLASS_HID_11589 = 0x11589, - BNXT_ULP_CLASS_HID_14549 = 0x14549, - BNXT_ULP_CLASS_HID_151a9 = 0x151a9, - BNXT_ULP_CLASS_HID_13bc9 = 0x13bc9, - BNXT_ULP_CLASS_HID_1378b = 0x1378b, - BNXT_ULP_CLASS_HID_1674b = 0x1674b, - BNXT_ULP_CLASS_HID_173ab = 0x173ab, - BNXT_ULP_CLASS_HID_114a9 = 0x114a9, - BNXT_ULP_CLASS_HID_1006b = 0x1006b, - BNXT_ULP_CLASS_HID_150a9 = 0x150a9, - BNXT_ULP_CLASS_HID_14c6b = 0x14c6b, - BNXT_ULP_CLASS_HID_136ab = 0x136ab, - BNXT_ULP_CLASS_HID_12269 = 0x12269, - BNXT_ULP_CLASS_HID_172ab = 0x172ab, - BNXT_ULP_CLASS_HID_16e69 = 0x16e69, - BNXT_ULP_CLASS_HID_402d2 = 0x402d2, - BNXT_ULP_CLASS_HID_412ee = 0x412ee, - BNXT_ULP_CLASS_HID_512a2 = 0x512a2, - BNXT_ULP_CLASS_HID_50dd8 = 0x50dd8, - BNXT_ULP_CLASS_HID_48aea = 0x48aea, - BNXT_ULP_CLASS_HID_48500 = 0x48500, - BNXT_ULP_CLASS_HID_585d4 = 0x585d4, - BNXT_ULP_CLASS_HID_59590 = 0x59590, - BNXT_ULP_CLASS_HID_41936 = 0x41936, - BNXT_ULP_CLASS_HID_409ac = 0x409ac, - BNXT_ULP_CLASS_HID_50860 = 0x50860, - BNXT_ULP_CLASS_HID_5183c = 0x5183c, - BNXT_ULP_CLASS_HID_481a8 = 0x481a8, - BNXT_ULP_CLASS_HID_49064 = 0x49064, - BNXT_ULP_CLASS_HID_59038 = 0x59038, - BNXT_ULP_CLASS_HID_58376 = 0x58376, - BNXT_ULP_CLASS_HID_414a0 = 0x414a0, - BNXT_ULP_CLASS_HID_407ce = 0x407ce, - BNXT_ULP_CLASS_HID_50782 = 0x50782, - BNXT_ULP_CLASS_HID_517ae = 0x517ae, - BNXT_ULP_CLASS_HID_49f68 = 0x49f68, - BNXT_ULP_CLASS_HID_48f86 = 0x48f86, - BNXT_ULP_CLASS_HID_58faa = 0x58faa, - BNXT_ULP_CLASS_HID_59e66 = 0x59e66, - BNXT_ULP_CLASS_HID_40266 = 0x40266, - BNXT_ULP_CLASS_HID_41222 = 0x41222, - BNXT_ULP_CLASS_HID_512e6 = 0x512e6, - BNXT_ULP_CLASS_HID_50d6c = 0x50d6c, - BNXT_ULP_CLASS_HID_48a2e = 0x48a2e, - BNXT_ULP_CLASS_HID_48564 = 0x48564, - BNXT_ULP_CLASS_HID_58568 = 0x58568, - BNXT_ULP_CLASS_HID_59524 = 0x59524, - BNXT_ULP_CLASS_HID_419d8 = 0x419d8, - BNXT_ULP_CLASS_HID_4087e = 0x4087e, - BNXT_ULP_CLASS_HID_5080a = 0x5080a, - BNXT_ULP_CLASS_HID_518ce = 0x518ce, - BNXT_ULP_CLASS_HID_4807a = 0x4807a, - BNXT_ULP_CLASS_HID_4900e = 0x4900e, - BNXT_ULP_CLASS_HID_590ca = 0x590ca, - BNXT_ULP_CLASS_HID_58378 = 0x58378, - BNXT_ULP_CLASS_HID_414be = 0x414be, - BNXT_ULP_CLASS_HID_4073c = 0x4073c, - BNXT_ULP_CLASS_HID_507e8 = 0x507e8, - BNXT_ULP_CLASS_HID_517ac = 0x517ac, - BNXT_ULP_CLASS_HID_49f7e = 0x49f7e, - BNXT_ULP_CLASS_HID_48fec = 0x48fec, - BNXT_ULP_CLASS_HID_58fa8 = 0x58fa8, - BNXT_ULP_CLASS_HID_59e7c = 0x59e7c, - BNXT_ULP_CLASS_HID_40208 = 0x40208, - BNXT_ULP_CLASS_HID_412cc = 0x412cc, - BNXT_ULP_CLASS_HID_51288 = 0x51288, - BNXT_ULP_CLASS_HID_50d2e = 0x50d2e, - BNXT_ULP_CLASS_HID_48ac8 = 0x48ac8, - BNXT_ULP_CLASS_HID_4856e = 0x4856e, - BNXT_ULP_CLASS_HID_5852a = 0x5852a, - BNXT_ULP_CLASS_HID_595ce = 0x595ce, - BNXT_ULP_CLASS_HID_4196c = 0x4196c, - BNXT_ULP_CLASS_HID_409aa = 0x409aa, - BNXT_ULP_CLASS_HID_5086e = 0x5086e, - BNXT_ULP_CLASS_HID_5182a = 0x5182a, - BNXT_ULP_CLASS_HID_481ae = 0x481ae, - BNXT_ULP_CLASS_HID_4906a = 0x4906a, - BNXT_ULP_CLASS_HID_5902e = 0x5902e, - BNXT_ULP_CLASS_HID_580ac = 0x580ac, - BNXT_ULP_CLASS_HID_40766 = 0x40766, - BNXT_ULP_CLASS_HID_41726 = 0x41726, - BNXT_ULP_CLASS_HID_517f6 = 0x517f6, - BNXT_ULP_CLASS_HID_5066c = 0x5066c, - BNXT_ULP_CLASS_HID_48f3e = 0x48f3e, - BNXT_ULP_CLASS_HID_49ffe = 0x49ffe, - BNXT_ULP_CLASS_HID_59f8e = 0x59f8e, - BNXT_ULP_CLASS_HID_58e24 = 0x58e24, - BNXT_ULP_CLASS_HID_4126e = 0x4126e, - BNXT_ULP_CLASS_HID_402e4 = 0x402e4, - BNXT_ULP_CLASS_HID_502b4 = 0x502b4, - BNXT_ULP_CLASS_HID_51d74 = 0x51d74, - BNXT_ULP_CLASS_HID_49a26 = 0x49a26, - BNXT_ULP_CLASS_HID_48abc = 0x48abc, - BNXT_ULP_CLASS_HID_5956c = 0x5956c, - BNXT_ULP_CLASS_HID_585ee = 0x585ee, - BNXT_ULP_CLASS_HID_409e4 = 0x409e4, - BNXT_ULP_CLASS_HID_419a4 = 0x419a4, - BNXT_ULP_CLASS_HID_51844 = 0x51844, - BNXT_ULP_CLASS_HID_508e6 = 0x508e6, - BNXT_ULP_CLASS_HID_4918c = 0x4918c, - BNXT_ULP_CLASS_HID_4802e = 0x4802e, - BNXT_ULP_CLASS_HID_580ee = 0x580ee, - BNXT_ULP_CLASS_HID_590ae = 0x590ae, - BNXT_ULP_CLASS_HID_404ae = 0x404ae, - BNXT_ULP_CLASS_HID_41766 = 0x41766, - BNXT_ULP_CLASS_HID_5172e = 0x5172e, - BNXT_ULP_CLASS_HID_507a4 = 0x507a4, - BNXT_ULP_CLASS_HID_48f66 = 0x48f66, - BNXT_ULP_CLASS_HID_49f2e = 0x49f2e, - BNXT_ULP_CLASS_HID_59fe6 = 0x59fe6, - BNXT_ULP_CLASS_HID_58e6c = 0x58e6c, - BNXT_ULP_CLASS_HID_4126c = 0x4126c, - BNXT_ULP_CLASS_HID_4028e = 0x4028e, - BNXT_ULP_CLASS_HID_50d5e = 0x50d5e, - BNXT_ULP_CLASS_HID_51d1e = 0x51d1e, - BNXT_ULP_CLASS_HID_49a2c = 0x49a2c, - BNXT_ULP_CLASS_HID_4954e = 0x4954e, - BNXT_ULP_CLASS_HID_5951e = 0x5951e, - BNXT_ULP_CLASS_HID_5858c = 0x5858c, - BNXT_ULP_CLASS_HID_409fe = 0x409fe, - BNXT_ULP_CLASS_HID_419ee = 0x419ee, - BNXT_ULP_CLASS_HID_519ae = 0x519ae, - BNXT_ULP_CLASS_HID_508fc = 0x508fc, - BNXT_ULP_CLASS_HID_491ee = 0x491ee, - BNXT_ULP_CLASS_HID_4802c = 0x4802c, - BNXT_ULP_CLASS_HID_580fc = 0x580fc, - BNXT_ULP_CLASS_HID_590bc = 0x590bc, - BNXT_ULP_CLASS_HID_4074c = 0x4074c, - BNXT_ULP_CLASS_HID_4170c = 0x4170c, - BNXT_ULP_CLASS_HID_5172c = 0x5172c, - BNXT_ULP_CLASS_HID_5064e = 0x5064e, - BNXT_ULP_CLASS_HID_48f0c = 0x48f0c, - BNXT_ULP_CLASS_HID_49fcc = 0x49fcc, - BNXT_ULP_CLASS_HID_59fec = 0x59fec, - BNXT_ULP_CLASS_HID_58e0e = 0x58e0e, - BNXT_ULP_CLASS_HID_413ac = 0x413ac, - BNXT_ULP_CLASS_HID_402ee = 0x402ee, - BNXT_ULP_CLASS_HID_502ae = 0x502ae, - BNXT_ULP_CLASS_HID_512ae = 0x512ae, - BNXT_ULP_CLASS_HID_49a6c = 0x49a6c, - BNXT_ULP_CLASS_HID_48aae = 0x48aae, - BNXT_ULP_CLASS_HID_58aae = 0x58aae, - BNXT_ULP_CLASS_HID_585ec = 0x585ec, - BNXT_ULP_CLASS_HID_104ae = 0x104ae, - BNXT_ULP_CLASS_HID_1108e = 0x1108e, - BNXT_ULP_CLASS_HID_140b2 = 0x140b2, - BNXT_ULP_CLASS_HID_15c92 = 0x15c92, - BNXT_ULP_CLASS_HID_126a0 = 0x126a0, - BNXT_ULP_CLASS_HID_13280 = 0x13280, - BNXT_ULP_CLASS_HID_16d44 = 0x16d44, - BNXT_ULP_CLASS_HID_17ea4 = 0x17ea4, - BNXT_ULP_CLASS_HID_113a4 = 0x113a4, - BNXT_ULP_CLASS_HID_10e66 = 0x10e66, - BNXT_ULP_CLASS_HID_15e40 = 0x15e40, - BNXT_ULP_CLASS_HID_14a02 = 0x14a02, - BNXT_ULP_CLASS_HID_13db6 = 0x13db6, - BNXT_ULP_CLASS_HID_12870 = 0x12870, - BNXT_ULP_CLASS_HID_17852 = 0x17852, - BNXT_ULP_CLASS_HID_17414 = 0x17414, - BNXT_ULP_CLASS_HID_11978 = 0x11978, - BNXT_ULP_CLASS_HID_1153a = 0x1153a, - BNXT_ULP_CLASS_HID_145fa = 0x145fa, - BNXT_ULP_CLASS_HID_151da = 0x151da, - BNXT_ULP_CLASS_HID_13b0a = 0x13b0a, - BNXT_ULP_CLASS_HID_137c8 = 0x137c8, - BNXT_ULP_CLASS_HID_167f0 = 0x167f0, - BNXT_ULP_CLASS_HID_173d0 = 0x173d0, - BNXT_ULP_CLASS_HID_114d0 = 0x114d0, - BNXT_ULP_CLASS_HID_10092 = 0x10092, - BNXT_ULP_CLASS_HID_150f0 = 0x150f0, - BNXT_ULP_CLASS_HID_14cb2 = 0x14cb2, - BNXT_ULP_CLASS_HID_136e2 = 0x136e2, - BNXT_ULP_CLASS_HID_122a0 = 0x122a0, - BNXT_ULP_CLASS_HID_17282 = 0x17282, - BNXT_ULP_CLASS_HID_16940 = 0x16940, - BNXT_ULP_CLASS_HID_11b90 = 0x11b90, - BNXT_ULP_CLASS_HID_11654 = 0x11654, - BNXT_ULP_CLASS_HID_14618 = 0x14618, - BNXT_ULP_CLASS_HID_15278 = 0x15278, - BNXT_ULP_CLASS_HID_12404 = 0x12404, - BNXT_ULP_CLASS_HID_13064 = 0x13064, - BNXT_ULP_CLASS_HID_16028 = 0x16028, - BNXT_ULP_CLASS_HID_17c08 = 0x17c08, - BNXT_ULP_CLASS_HID_11100 = 0x11100, - BNXT_ULP_CLASS_HID_10dc4 = 0x10dc4, - BNXT_ULP_CLASS_HID_15d24 = 0x15d24, - BNXT_ULP_CLASS_HID_149d0 = 0x149d0, - BNXT_ULP_CLASS_HID_13314 = 0x13314, - BNXT_ULP_CLASS_HID_12fd4 = 0x12fd4, - BNXT_ULP_CLASS_HID_17f20 = 0x17f20, - BNXT_ULP_CLASS_HID_16be0 = 0x16be0, - BNXT_ULP_CLASS_HID_11cd8 = 0x11cd8, - BNXT_ULP_CLASS_HID_10880 = 0x10880, - BNXT_ULP_CLASS_HID_158e0 = 0x158e0, - BNXT_ULP_CLASS_HID_154a0 = 0x154a0, - BNXT_ULP_CLASS_HID_13ed0 = 0x13ed0, - BNXT_ULP_CLASS_HID_12a90 = 0x12a90, - BNXT_ULP_CLASS_HID_16550 = 0x16550, - BNXT_ULP_CLASS_HID_176b0 = 0x176b0, - BNXT_ULP_CLASS_HID_10bb0 = 0x10bb0, - BNXT_ULP_CLASS_HID_10670 = 0x10670, - BNXT_ULP_CLASS_HID_15650 = 0x15650, - BNXT_ULP_CLASS_HID_14210 = 0x14210, - BNXT_ULP_CLASS_HID_13440 = 0x13440, - BNXT_ULP_CLASS_HID_12000 = 0x12000, - BNXT_ULP_CLASS_HID_17060 = 0x17060, - BNXT_ULP_CLASS_HID_16c20 = 0x16c20, - BNXT_ULP_CLASS_HID_11511 = 0x11511, - BNXT_ULP_CLASS_HID_101d3 = 0x101d3, - BNXT_ULP_CLASS_HID_15135 = 0x15135, - BNXT_ULP_CLASS_HID_14df7 = 0x14df7, - BNXT_ULP_CLASS_HID_13723 = 0x13723, - BNXT_ULP_CLASS_HID_123e5 = 0x123e5, - BNXT_ULP_CLASS_HID_173c7 = 0x173c7, - BNXT_ULP_CLASS_HID_16f89 = 0x16f89, - BNXT_ULP_CLASS_HID_10081 = 0x10081, - BNXT_ULP_CLASS_HID_11ce1 = 0x11ce1, - BNXT_ULP_CLASS_HID_14ca5 = 0x14ca5, - BNXT_ULP_CLASS_HID_15885 = 0x15885, - BNXT_ULP_CLASS_HID_12293 = 0x12293, - BNXT_ULP_CLASS_HID_13ef3 = 0x13ef3, - BNXT_ULP_CLASS_HID_16eb7 = 0x16eb7, - BNXT_ULP_CLASS_HID_16561 = 0x16561, - BNXT_ULP_CLASS_HID_10e59 = 0x10e59, - BNXT_ULP_CLASS_HID_11bb9 = 0x11bb9, - BNXT_ULP_CLASS_HID_14a61 = 0x14a61, - BNXT_ULP_CLASS_HID_14623 = 0x14623, - BNXT_ULP_CLASS_HID_1286b = 0x1286b, - BNXT_ULP_CLASS_HID_12411 = 0x12411, - BNXT_ULP_CLASS_HID_17473 = 0x17473, - BNXT_ULP_CLASS_HID_16031 = 0x16031, - BNXT_ULP_CLASS_HID_10531 = 0x10531, - BNXT_ULP_CLASS_HID_11111 = 0x11111, - BNXT_ULP_CLASS_HID_141d1 = 0x141d1, - BNXT_ULP_CLASS_HID_15d31 = 0x15d31, - BNXT_ULP_CLASS_HID_127c3 = 0x127c3, - BNXT_ULP_CLASS_HID_13323 = 0x13323, - BNXT_ULP_CLASS_HID_163e3 = 0x163e3, - BNXT_ULP_CLASS_HID_17fc3 = 0x17fc3, - BNXT_ULP_CLASS_HID_108f5 = 0x108f5, - BNXT_ULP_CLASS_HID_104b9 = 0x104b9, - BNXT_ULP_CLASS_HID_15499 = 0x15499, - BNXT_ULP_CLASS_HID_1435d = 0x1435d, - BNXT_ULP_CLASS_HID_12a89 = 0x12a89, - BNXT_ULP_CLASS_HID_12149 = 0x12149, - BNXT_ULP_CLASS_HID_176ad = 0x176ad, - BNXT_ULP_CLASS_HID_16d6d = 0x16d6d, - BNXT_ULP_CLASS_HID_10665 = 0x10665, - BNXT_ULP_CLASS_HID_11245 = 0x11245, - BNXT_ULP_CLASS_HID_14271 = 0x14271, - BNXT_ULP_CLASS_HID_15e51 = 0x15e51, - BNXT_ULP_CLASS_HID_12061 = 0x12061, - BNXT_ULP_CLASS_HID_13c41 = 0x13c41, - BNXT_ULP_CLASS_HID_16c05 = 0x16c05, - BNXT_ULP_CLASS_HID_17865 = 0x17865, - BNXT_ULP_CLASS_HID_10d21 = 0x10d21, - BNXT_ULP_CLASS_HID_11901 = 0x11901, - BNXT_ULP_CLASS_HID_149c1 = 0x149c1, - BNXT_ULP_CLASS_HID_14589 = 0x14589, - BNXT_ULP_CLASS_HID_12f31 = 0x12f31, - BNXT_ULP_CLASS_HID_13b11 = 0x13b11, - BNXT_ULP_CLASS_HID_16bd9 = 0x16bd9, - BNXT_ULP_CLASS_HID_16799 = 0x16799, - BNXT_ULP_CLASS_HID_11831 = 0x11831, - BNXT_ULP_CLASS_HID_114f1 = 0x114f1, - BNXT_ULP_CLASS_HID_144b1 = 0x144b1, - BNXT_ULP_CLASS_HID_15091 = 0x15091, - BNXT_ULP_CLASS_HID_13ac1 = 0x13ac1, - BNXT_ULP_CLASS_HID_13681 = 0x13681, - BNXT_ULP_CLASS_HID_166b1 = 0x166b1, - BNXT_ULP_CLASS_HID_17291 = 0x17291, - BNXT_ULP_CLASS_HID_4007d = 0x4007d, - BNXT_ULP_CLASS_HID_41041 = 0x41041, - BNXT_ULP_CLASS_HID_5100d = 0x5100d, - BNXT_ULP_CLASS_HID_50f77 = 0x50f77, - BNXT_ULP_CLASS_HID_48845 = 0x48845, - BNXT_ULP_CLASS_HID_487af = 0x487af, - BNXT_ULP_CLASS_HID_5877b = 0x5877b, - BNXT_ULP_CLASS_HID_5973f = 0x5973f, - BNXT_ULP_CLASS_HID_41c31 = 0x41c31, - BNXT_ULP_CLASS_HID_40b1b = 0x40b1b, - BNXT_ULP_CLASS_HID_50b67 = 0x50b67, - BNXT_ULP_CLASS_HID_51b2b = 0x51b2b, - BNXT_ULP_CLASS_HID_4831f = 0x4831f, - BNXT_ULP_CLASS_HID_49363 = 0x49363, - BNXT_ULP_CLASS_HID_5932f = 0x5932f, - BNXT_ULP_CLASS_HID_58211 = 0x58211, - BNXT_ULP_CLASS_HID_4161b = 0x4161b, - BNXT_ULP_CLASS_HID_405bd = 0x405bd, - BNXT_ULP_CLASS_HID_50589 = 0x50589, - BNXT_ULP_CLASS_HID_5150d = 0x5150d, - BNXT_ULP_CLASS_HID_49e23 = 0x49e23, - BNXT_ULP_CLASS_HID_48d85 = 0x48d85, - BNXT_ULP_CLASS_HID_58d11 = 0x58d11, - BNXT_ULP_CLASS_HID_59d15 = 0x59d15, - BNXT_ULP_CLASS_HID_4012d = 0x4012d, - BNXT_ULP_CLASS_HID_41131 = 0x41131, - BNXT_ULP_CLASS_HID_5113d = 0x5113d, - BNXT_ULP_CLASS_HID_50027 = 0x50027, - BNXT_ULP_CLASS_HID_48935 = 0x48935, - BNXT_ULP_CLASS_HID_49939 = 0x49939, - BNXT_ULP_CLASS_HID_59905 = 0x59905, - BNXT_ULP_CLASS_HID_5882f = 0x5882f, - BNXT_ULP_CLASS_HID_41b99 = 0x41b99, - BNXT_ULP_CLASS_HID_40b03 = 0x40b03, - BNXT_ULP_CLASS_HID_50acf = 0x50acf, - BNXT_ULP_CLASS_HID_51a93 = 0x51a93, - BNXT_ULP_CLASS_HID_48307 = 0x48307, - BNXT_ULP_CLASS_HID_492cb = 0x492cb, - BNXT_ULP_CLASS_HID_59297 = 0x59297, - BNXT_ULP_CLASS_HID_581d9 = 0x581d9, - BNXT_ULP_CLASS_HID_41653 = 0x41653, - BNXT_ULP_CLASS_HID_40655 = 0x40655, - BNXT_ULP_CLASS_HID_50601 = 0x50601, - BNXT_ULP_CLASS_HID_51545 = 0x51545, - BNXT_ULP_CLASS_HID_49e1b = 0x49e1b, - BNXT_ULP_CLASS_HID_48e1d = 0x48e1d, - BNXT_ULP_CLASS_HID_58d49 = 0x58d49, - BNXT_ULP_CLASS_HID_59d0d = 0x59d0d, - BNXT_ULP_CLASS_HID_40115 = 0x40115, - BNXT_ULP_CLASS_HID_41099 = 0x41099, - BNXT_ULP_CLASS_HID_51085 = 0x51085, - BNXT_ULP_CLASS_HID_5000f = 0x5000f, - BNXT_ULP_CLASS_HID_4889d = 0x4889d, - BNXT_ULP_CLASS_HID_49881 = 0x49881, - BNXT_ULP_CLASS_HID_5980d = 0x5980d, - BNXT_ULP_CLASS_HID_59797 = 0x59797, - BNXT_ULP_CLASS_HID_41c09 = 0x41c09, - BNXT_ULP_CLASS_HID_40c13 = 0x40c13, - BNXT_ULP_CLASS_HID_50b1f = 0x50b1f, - BNXT_ULP_CLASS_HID_51b03 = 0x51b03, - BNXT_ULP_CLASS_HID_48417 = 0x48417, - BNXT_ULP_CLASS_HID_4931b = 0x4931b, - BNXT_ULP_CLASS_HID_59307 = 0x59307, - BNXT_ULP_CLASS_HID_58309 = 0x58309, - BNXT_ULP_CLASS_HID_4160f = 0x4160f, - BNXT_ULP_CLASS_HID_40561 = 0x40561, - BNXT_ULP_CLASS_HID_5052d = 0x5052d, - BNXT_ULP_CLASS_HID_51501 = 0x51501, - BNXT_ULP_CLASS_HID_49dc7 = 0x49dc7, - BNXT_ULP_CLASS_HID_48d29 = 0x48d29, - BNXT_ULP_CLASS_HID_58d05 = 0x58d05, - BNXT_ULP_CLASS_HID_59cc9 = 0x59cc9, - BNXT_ULP_CLASS_HID_40161 = 0x40161, - BNXT_ULP_CLASS_HID_41125 = 0x41125, - BNXT_ULP_CLASS_HID_51061 = 0x51061, - BNXT_ULP_CLASS_HID_5004b = 0x5004b, - BNXT_ULP_CLASS_HID_48929 = 0x48929, - BNXT_ULP_CLASS_HID_4986d = 0x4986d, - BNXT_ULP_CLASS_HID_59829 = 0x59829, - BNXT_ULP_CLASS_HID_58823 = 0x58823, - BNXT_ULP_CLASS_HID_41ba5 = 0x41ba5, - BNXT_ULP_CLASS_HID_40b0f = 0x40b0f, - BNXT_ULP_CLASS_HID_50b0b = 0x50b0b, - BNXT_ULP_CLASS_HID_51a8f = 0x51a8f, - BNXT_ULP_CLASS_HID_48303 = 0x48303, - BNXT_ULP_CLASS_HID_49307 = 0x49307, - BNXT_ULP_CLASS_HID_592a3 = 0x592a3, - BNXT_ULP_CLASS_HID_58205 = 0x58205, - BNXT_ULP_CLASS_HID_4172f = 0x4172f, - BNXT_ULP_CLASS_HID_40621 = 0x40621, - BNXT_ULP_CLASS_HID_5062d = 0x5062d, - BNXT_ULP_CLASS_HID_51621 = 0x51621, - BNXT_ULP_CLASS_HID_49f07 = 0x49f07, - BNXT_ULP_CLASS_HID_48e29 = 0x48e29, - BNXT_ULP_CLASS_HID_58e25 = 0x58e25, - BNXT_ULP_CLASS_HID_59d29 = 0x59d29, - BNXT_ULP_CLASS_HID_400c9 = 0x400c9, - BNXT_ULP_CLASS_HID_4108d = 0x4108d, - BNXT_ULP_CLASS_HID_51049 = 0x51049, - BNXT_ULP_CLASS_HID_50fc3 = 0x50fc3, - BNXT_ULP_CLASS_HID_48881 = 0x48881, - BNXT_ULP_CLASS_HID_487cb = 0x487cb, - BNXT_ULP_CLASS_HID_587c7 = 0x587c7, - BNXT_ULP_CLASS_HID_5978b = 0x5978b, - BNXT_ULP_CLASS_HID_41c4d = 0x41c4d, - BNXT_ULP_CLASS_HID_40b47 = 0x40b47, - BNXT_ULP_CLASS_HID_50b03 = 0x50b03, - BNXT_ULP_CLASS_HID_51b47 = 0x51b47, - BNXT_ULP_CLASS_HID_4834b = 0x4834b, - BNXT_ULP_CLASS_HID_4930f = 0x4930f, - BNXT_ULP_CLASS_HID_5934b = 0x5934b, - BNXT_ULP_CLASS_HID_5824d = 0x5824d, - BNXT_ULP_CLASS_HID_41687 = 0x41687, - BNXT_ULP_CLASS_HID_40609 = 0x40609, - BNXT_ULP_CLASS_HID_50585 = 0x50585, - BNXT_ULP_CLASS_HID_51589 = 0x51589, - BNXT_ULP_CLASS_HID_49e0f = 0x49e0f, - BNXT_ULP_CLASS_HID_48d81 = 0x48d81, - BNXT_ULP_CLASS_HID_58d8d = 0x58d8d, - BNXT_ULP_CLASS_HID_59d01 = 0x59d01, - BNXT_ULP_CLASS_HID_40109 = 0x40109, - BNXT_ULP_CLASS_HID_4110d = 0x4110d, - BNXT_ULP_CLASS_HID_51109 = 0x51109, - BNXT_ULP_CLASS_HID_50003 = 0x50003, - BNXT_ULP_CLASS_HID_48901 = 0x48901, - BNXT_ULP_CLASS_HID_49905 = 0x49905, - BNXT_ULP_CLASS_HID_59901 = 0x59901, - BNXT_ULP_CLASS_HID_5880b = 0x5880b, - BNXT_ULP_CLASS_HID_10619 = 0x10619, - BNXT_ULP_CLASS_HID_11239 = 0x11239, - BNXT_ULP_CLASS_HID_14205 = 0x14205, - BNXT_ULP_CLASS_HID_15e25 = 0x15e25, - BNXT_ULP_CLASS_HID_12417 = 0x12417, - BNXT_ULP_CLASS_HID_13037 = 0x13037, - BNXT_ULP_CLASS_HID_16ff3 = 0x16ff3, - BNXT_ULP_CLASS_HID_17c13 = 0x17c13, - BNXT_ULP_CLASS_HID_1111d = 0x1111d, - BNXT_ULP_CLASS_HID_10cdb = 0x10cdb, - BNXT_ULP_CLASS_HID_15d19 = 0x15d19, - BNXT_ULP_CLASS_HID_148c7 = 0x148c7, - BNXT_ULP_CLASS_HID_13f0b = 0x13f0b, - BNXT_ULP_CLASS_HID_12ac9 = 0x12ac9, - BNXT_ULP_CLASS_HID_17b17 = 0x17b17, - BNXT_ULP_CLASS_HID_176d5 = 0x176d5, - BNXT_ULP_CLASS_HID_10bab = 0x10bab, - BNXT_ULP_CLASS_HID_10769 = 0x10769, - BNXT_ULP_CLASS_HID_15787 = 0x15787, - BNXT_ULP_CLASS_HID_14345 = 0x14345, - BNXT_ULP_CLASS_HID_12989 = 0x12989, - BNXT_ULP_CLASS_HID_12567 = 0x12567, - BNXT_ULP_CLASS_HID_17585 = 0x17585, - BNXT_ULP_CLASS_HID_16143 = 0x16143, - BNXT_ULP_CLASS_HID_1064d = 0x1064d, - BNXT_ULP_CLASS_HID_1128d = 0x1128d, - BNXT_ULP_CLASS_HID_14249 = 0x14249, - BNXT_ULP_CLASS_HID_15e49 = 0x15e49, - BNXT_ULP_CLASS_HID_1244b = 0x1244b, - BNXT_ULP_CLASS_HID_1304b = 0x1304b, - BNXT_ULP_CLASS_HID_16047 = 0x16047, - BNXT_ULP_CLASS_HID_17c47 = 0x17c47, - BNXT_ULP_CLASS_HID_11113 = 0x11113, - BNXT_ULP_CLASS_HID_10cd1 = 0x10cd1, - BNXT_ULP_CLASS_HID_15cf7 = 0x15cf7, - BNXT_ULP_CLASS_HID_148b5 = 0x148b5, - BNXT_ULP_CLASS_HID_13f01 = 0x13f01, - BNXT_ULP_CLASS_HID_12ac7 = 0x12ac7, - BNXT_ULP_CLASS_HID_17ae5 = 0x17ae5, - BNXT_ULP_CLASS_HID_176a3 = 0x176a3, - BNXT_ULP_CLASS_HID_10bd5 = 0x10bd5, - BNXT_ULP_CLASS_HID_10793 = 0x10793, - BNXT_ULP_CLASS_HID_15791 = 0x15791, - BNXT_ULP_CLASS_HID_14357 = 0x14357, - BNXT_ULP_CLASS_HID_129c3 = 0x129c3, - BNXT_ULP_CLASS_HID_12581 = 0x12581, - BNXT_ULP_CLASS_HID_17587 = 0x17587, - BNXT_ULP_CLASS_HID_16145 = 0x16145, - BNXT_ULP_CLASS_HID_10643 = 0x10643, - BNXT_ULP_CLASS_HID_11263 = 0x11263, - BNXT_ULP_CLASS_HID_14227 = 0x14227, - BNXT_ULP_CLASS_HID_15e47 = 0x15e47, - BNXT_ULP_CLASS_HID_12421 = 0x12421, - BNXT_ULP_CLASS_HID_13041 = 0x13041, - BNXT_ULP_CLASS_HID_16005 = 0x16005, - BNXT_ULP_CLASS_HID_17c25 = 0x17c25, - BNXT_ULP_CLASS_HID_11147 = 0x11147, - BNXT_ULP_CLASS_HID_10d05 = 0x10d05, - BNXT_ULP_CLASS_HID_15d43 = 0x15d43, - BNXT_ULP_CLASS_HID_14901 = 0x14901, - BNXT_ULP_CLASS_HID_13f45 = 0x13f45, - BNXT_ULP_CLASS_HID_12b03 = 0x12b03, - BNXT_ULP_CLASS_HID_17b01 = 0x17b01, - BNXT_ULP_CLASS_HID_176c7 = 0x176c7, - BNXT_ULP_CLASS_HID_11bcf = 0x11bcf, - BNXT_ULP_CLASS_HID_1178d = 0x1178d, - BNXT_ULP_CLASS_HID_1474d = 0x1474d, - BNXT_ULP_CLASS_HID_1536d = 0x1536d, - BNXT_ULP_CLASS_HID_139bd = 0x139bd, - BNXT_ULP_CLASS_HID_1357f = 0x1357f, - BNXT_ULP_CLASS_HID_16547 = 0x16547, - BNXT_ULP_CLASS_HID_17167 = 0x17167, - BNXT_ULP_CLASS_HID_11685 = 0x11685, - BNXT_ULP_CLASS_HID_1024f = 0x1024f, - BNXT_ULP_CLASS_HID_1524d = 0x1524d, - BNXT_ULP_CLASS_HID_14e0f = 0x14e0f, - BNXT_ULP_CLASS_HID_1345f = 0x1345f, - BNXT_ULP_CLASS_HID_1201d = 0x1201d, - BNXT_ULP_CLASS_HID_1705f = 0x1705f, - BNXT_ULP_CLASS_HID_16c1d = 0x16c1d, - BNXT_ULP_CLASS_HID_100ef = 0x100ef, - BNXT_ULP_CLASS_HID_11d0f = 0x11d0f, - BNXT_ULP_CLASS_HID_14ccf = 0x14ccf, - BNXT_ULP_CLASS_HID_158ef = 0x158ef, - BNXT_ULP_CLASS_HID_12eed = 0x12eed, - BNXT_ULP_CLASS_HID_13b0d = 0x13b0d, - BNXT_ULP_CLASS_HID_16acd = 0x16acd, - BNXT_ULP_CLASS_HID_16687 = 0x16687, - BNXT_ULP_CLASS_HID_11c07 = 0x11c07, - BNXT_ULP_CLASS_HID_117c5 = 0x117c5, - BNXT_ULP_CLASS_HID_1478d = 0x1478d, - BNXT_ULP_CLASS_HID_1538d = 0x1538d, - BNXT_ULP_CLASS_HID_13a05 = 0x13a05, - BNXT_ULP_CLASS_HID_135cf = 0x135cf, - BNXT_ULP_CLASS_HID_1658f = 0x1658f, - BNXT_ULP_CLASS_HID_1718f = 0x1718f, - BNXT_ULP_CLASS_HID_11667 = 0x11667, - BNXT_ULP_CLASS_HID_10225 = 0x10225, - BNXT_ULP_CLASS_HID_15247 = 0x15247, - BNXT_ULP_CLASS_HID_14e05 = 0x14e05, - BNXT_ULP_CLASS_HID_13455 = 0x13455, - BNXT_ULP_CLASS_HID_12017 = 0x12017, - BNXT_ULP_CLASS_HID_17035 = 0x17035, - BNXT_ULP_CLASS_HID_16bf7 = 0x16bf7, - BNXT_ULP_CLASS_HID_10115 = 0x10115, - BNXT_ULP_CLASS_HID_11d15 = 0x11d15, - BNXT_ULP_CLASS_HID_14d05 = 0x14d05, - BNXT_ULP_CLASS_HID_15905 = 0x15905, - BNXT_ULP_CLASS_HID_12f17 = 0x12f17, - BNXT_ULP_CLASS_HID_13b17 = 0x13b17, - BNXT_ULP_CLASS_HID_16ad7 = 0x16ad7, - BNXT_ULP_CLASS_HID_16695 = 0x16695, - BNXT_ULP_CLASS_HID_11be5 = 0x11be5, - BNXT_ULP_CLASS_HID_117a7 = 0x117a7, - BNXT_ULP_CLASS_HID_14767 = 0x14767, - BNXT_ULP_CLASS_HID_15387 = 0x15387, - BNXT_ULP_CLASS_HID_139e7 = 0x139e7, - BNXT_ULP_CLASS_HID_135a5 = 0x135a5, - BNXT_ULP_CLASS_HID_16565 = 0x16565, - BNXT_ULP_CLASS_HID_17185 = 0x17185, - BNXT_ULP_CLASS_HID_11687 = 0x11687, - BNXT_ULP_CLASS_HID_10245 = 0x10245, - BNXT_ULP_CLASS_HID_15287 = 0x15287, - BNXT_ULP_CLASS_HID_14e45 = 0x14e45, - BNXT_ULP_CLASS_HID_13485 = 0x13485, - BNXT_ULP_CLASS_HID_12047 = 0x12047, - BNXT_ULP_CLASS_HID_17085 = 0x17085, - BNXT_ULP_CLASS_HID_16c47 = 0x16c47, - BNXT_ULP_CLASS_HID_400f4 = 0x400f4, - BNXT_ULP_CLASS_HID_410c8 = 0x410c8, - BNXT_ULP_CLASS_HID_51084 = 0x51084, - BNXT_ULP_CLASS_HID_50ffe = 0x50ffe, - BNXT_ULP_CLASS_HID_488cc = 0x488cc, - BNXT_ULP_CLASS_HID_48726 = 0x48726, - BNXT_ULP_CLASS_HID_587f2 = 0x587f2, - BNXT_ULP_CLASS_HID_597b6 = 0x597b6, - BNXT_ULP_CLASS_HID_41b10 = 0x41b10, - BNXT_ULP_CLASS_HID_40b8a = 0x40b8a, - BNXT_ULP_CLASS_HID_50a46 = 0x50a46, - BNXT_ULP_CLASS_HID_51a1a = 0x51a1a, - BNXT_ULP_CLASS_HID_4838e = 0x4838e, - BNXT_ULP_CLASS_HID_49242 = 0x49242, - BNXT_ULP_CLASS_HID_5921e = 0x5921e, - BNXT_ULP_CLASS_HID_58150 = 0x58150, - BNXT_ULP_CLASS_HID_41686 = 0x41686, - BNXT_ULP_CLASS_HID_405e8 = 0x405e8, - BNXT_ULP_CLASS_HID_505a4 = 0x505a4, - BNXT_ULP_CLASS_HID_51588 = 0x51588, - BNXT_ULP_CLASS_HID_49d4e = 0x49d4e, - BNXT_ULP_CLASS_HID_48da0 = 0x48da0, - BNXT_ULP_CLASS_HID_58d8c = 0x58d8c, - BNXT_ULP_CLASS_HID_59c40 = 0x59c40, - BNXT_ULP_CLASS_HID_40040 = 0x40040, - BNXT_ULP_CLASS_HID_41004 = 0x41004, - BNXT_ULP_CLASS_HID_510c0 = 0x510c0, - BNXT_ULP_CLASS_HID_50f4a = 0x50f4a, - BNXT_ULP_CLASS_HID_48808 = 0x48808, - BNXT_ULP_CLASS_HID_48742 = 0x48742, - BNXT_ULP_CLASS_HID_5874e = 0x5874e, - BNXT_ULP_CLASS_HID_59702 = 0x59702, - BNXT_ULP_CLASS_HID_41bfe = 0x41bfe, - BNXT_ULP_CLASS_HID_40a58 = 0x40a58, - BNXT_ULP_CLASS_HID_50a2c = 0x50a2c, - BNXT_ULP_CLASS_HID_51ae8 = 0x51ae8, - BNXT_ULP_CLASS_HID_4825c = 0x4825c, - BNXT_ULP_CLASS_HID_49228 = 0x49228, - BNXT_ULP_CLASS_HID_592ec = 0x592ec, - BNXT_ULP_CLASS_HID_5815e = 0x5815e, - BNXT_ULP_CLASS_HID_41698 = 0x41698, - BNXT_ULP_CLASS_HID_4051a = 0x4051a, - BNXT_ULP_CLASS_HID_505ce = 0x505ce, - BNXT_ULP_CLASS_HID_5158a = 0x5158a, - BNXT_ULP_CLASS_HID_49d58 = 0x49d58, - BNXT_ULP_CLASS_HID_48dca = 0x48dca, - BNXT_ULP_CLASS_HID_58d8e = 0x58d8e, - BNXT_ULP_CLASS_HID_59c5a = 0x59c5a, - BNXT_ULP_CLASS_HID_4002e = 0x4002e, - BNXT_ULP_CLASS_HID_410ea = 0x410ea, - BNXT_ULP_CLASS_HID_510ae = 0x510ae, - BNXT_ULP_CLASS_HID_50f08 = 0x50f08, - BNXT_ULP_CLASS_HID_488ee = 0x488ee, - BNXT_ULP_CLASS_HID_48748 = 0x48748, - BNXT_ULP_CLASS_HID_5870c = 0x5870c, - BNXT_ULP_CLASS_HID_597e8 = 0x597e8, - BNXT_ULP_CLASS_HID_41b4a = 0x41b4a, - BNXT_ULP_CLASS_HID_40b8c = 0x40b8c, - BNXT_ULP_CLASS_HID_50a48 = 0x50a48, - BNXT_ULP_CLASS_HID_51a0c = 0x51a0c, - BNXT_ULP_CLASS_HID_48388 = 0x48388, - BNXT_ULP_CLASS_HID_4924c = 0x4924c, - BNXT_ULP_CLASS_HID_59208 = 0x59208, - BNXT_ULP_CLASS_HID_5828a = 0x5828a, - BNXT_ULP_CLASS_HID_40540 = 0x40540, - BNXT_ULP_CLASS_HID_41500 = 0x41500, - BNXT_ULP_CLASS_HID_515d0 = 0x515d0, - BNXT_ULP_CLASS_HID_5044a = 0x5044a, - BNXT_ULP_CLASS_HID_48d18 = 0x48d18, - BNXT_ULP_CLASS_HID_49dd8 = 0x49dd8, - BNXT_ULP_CLASS_HID_59da8 = 0x59da8, - BNXT_ULP_CLASS_HID_58c02 = 0x58c02, - BNXT_ULP_CLASS_HID_41048 = 0x41048, - BNXT_ULP_CLASS_HID_400c2 = 0x400c2, - BNXT_ULP_CLASS_HID_50092 = 0x50092, - BNXT_ULP_CLASS_HID_51f52 = 0x51f52, - BNXT_ULP_CLASS_HID_49800 = 0x49800, - BNXT_ULP_CLASS_HID_4889a = 0x4889a, - BNXT_ULP_CLASS_HID_5974a = 0x5974a, - BNXT_ULP_CLASS_HID_587c8 = 0x587c8, - BNXT_ULP_CLASS_HID_40bc2 = 0x40bc2, - BNXT_ULP_CLASS_HID_41b82 = 0x41b82, - BNXT_ULP_CLASS_HID_51a62 = 0x51a62, - BNXT_ULP_CLASS_HID_50ac0 = 0x50ac0, - BNXT_ULP_CLASS_HID_493aa = 0x493aa, - BNXT_ULP_CLASS_HID_48208 = 0x48208, - BNXT_ULP_CLASS_HID_582c8 = 0x582c8, - BNXT_ULP_CLASS_HID_59288 = 0x59288, - BNXT_ULP_CLASS_HID_40688 = 0x40688, - BNXT_ULP_CLASS_HID_41540 = 0x41540, - BNXT_ULP_CLASS_HID_51508 = 0x51508, - BNXT_ULP_CLASS_HID_50582 = 0x50582, - BNXT_ULP_CLASS_HID_48d40 = 0x48d40, - BNXT_ULP_CLASS_HID_49d08 = 0x49d08, - BNXT_ULP_CLASS_HID_59dc0 = 0x59dc0, - BNXT_ULP_CLASS_HID_58c4a = 0x58c4a, - BNXT_ULP_CLASS_HID_4104a = 0x4104a, - BNXT_ULP_CLASS_HID_400a8 = 0x400a8, - BNXT_ULP_CLASS_HID_50f78 = 0x50f78, - BNXT_ULP_CLASS_HID_51f38 = 0x51f38, - BNXT_ULP_CLASS_HID_4980a = 0x4980a, - BNXT_ULP_CLASS_HID_49768 = 0x49768, - BNXT_ULP_CLASS_HID_59738 = 0x59738, - BNXT_ULP_CLASS_HID_587aa = 0x587aa, - BNXT_ULP_CLASS_HID_40bd8 = 0x40bd8, - BNXT_ULP_CLASS_HID_41bc8 = 0x41bc8, - BNXT_ULP_CLASS_HID_51b88 = 0x51b88, - BNXT_ULP_CLASS_HID_50ada = 0x50ada, - BNXT_ULP_CLASS_HID_493c8 = 0x493c8, - BNXT_ULP_CLASS_HID_4820a = 0x4820a, - BNXT_ULP_CLASS_HID_582da = 0x582da, - BNXT_ULP_CLASS_HID_5929a = 0x5929a, - BNXT_ULP_CLASS_HID_4056a = 0x4056a, - BNXT_ULP_CLASS_HID_4152a = 0x4152a, - BNXT_ULP_CLASS_HID_5150a = 0x5150a, - BNXT_ULP_CLASS_HID_50468 = 0x50468, - BNXT_ULP_CLASS_HID_48d2a = 0x48d2a, - BNXT_ULP_CLASS_HID_49dea = 0x49dea, - BNXT_ULP_CLASS_HID_59dca = 0x59dca, - BNXT_ULP_CLASS_HID_58c28 = 0x58c28, - BNXT_ULP_CLASS_HID_4118a = 0x4118a, - BNXT_ULP_CLASS_HID_400c8 = 0x400c8, - BNXT_ULP_CLASS_HID_50088 = 0x50088, - BNXT_ULP_CLASS_HID_51088 = 0x51088, - BNXT_ULP_CLASS_HID_4984a = 0x4984a, - BNXT_ULP_CLASS_HID_48888 = 0x48888, - BNXT_ULP_CLASS_HID_58888 = 0x58888, - BNXT_ULP_CLASS_HID_587ca = 0x587ca, - BNXT_ULP_CLASS_HID_10690 = 0x10690, - BNXT_ULP_CLASS_HID_112b0 = 0x112b0, - BNXT_ULP_CLASS_HID_1428c = 0x1428c, - BNXT_ULP_CLASS_HID_15eac = 0x15eac, - BNXT_ULP_CLASS_HID_1249e = 0x1249e, - BNXT_ULP_CLASS_HID_130be = 0x130be, - BNXT_ULP_CLASS_HID_16f7a = 0x16f7a, - BNXT_ULP_CLASS_HID_17c9a = 0x17c9a, - BNXT_ULP_CLASS_HID_1119a = 0x1119a, - BNXT_ULP_CLASS_HID_10c58 = 0x10c58, - BNXT_ULP_CLASS_HID_15c7e = 0x15c7e, - BNXT_ULP_CLASS_HID_1483c = 0x1483c, - BNXT_ULP_CLASS_HID_13f88 = 0x13f88, - BNXT_ULP_CLASS_HID_12a4e = 0x12a4e, - BNXT_ULP_CLASS_HID_17a6c = 0x17a6c, - BNXT_ULP_CLASS_HID_1762a = 0x1762a, - BNXT_ULP_CLASS_HID_11b46 = 0x11b46, - BNXT_ULP_CLASS_HID_11704 = 0x11704, - BNXT_ULP_CLASS_HID_147c4 = 0x147c4, - BNXT_ULP_CLASS_HID_153e4 = 0x153e4, - BNXT_ULP_CLASS_HID_13934 = 0x13934, - BNXT_ULP_CLASS_HID_135f6 = 0x135f6, - BNXT_ULP_CLASS_HID_165ce = 0x165ce, - BNXT_ULP_CLASS_HID_171ee = 0x171ee, - BNXT_ULP_CLASS_HID_116ee = 0x116ee, - BNXT_ULP_CLASS_HID_102ac = 0x102ac, - BNXT_ULP_CLASS_HID_152ce = 0x152ce, - BNXT_ULP_CLASS_HID_14e8c = 0x14e8c, - BNXT_ULP_CLASS_HID_134dc = 0x134dc, - BNXT_ULP_CLASS_HID_1209e = 0x1209e, - BNXT_ULP_CLASS_HID_170bc = 0x170bc, - BNXT_ULP_CLASS_HID_16b7e = 0x16b7e, - BNXT_ULP_CLASS_HID_119ae = 0x119ae, - BNXT_ULP_CLASS_HID_1146a = 0x1146a, - BNXT_ULP_CLASS_HID_14426 = 0x14426, - BNXT_ULP_CLASS_HID_15046 = 0x15046, - BNXT_ULP_CLASS_HID_1263a = 0x1263a, - BNXT_ULP_CLASS_HID_1325a = 0x1325a, - BNXT_ULP_CLASS_HID_16216 = 0x16216, - BNXT_ULP_CLASS_HID_17e36 = 0x17e36, - BNXT_ULP_CLASS_HID_1133e = 0x1133e, - BNXT_ULP_CLASS_HID_10ffa = 0x10ffa, - BNXT_ULP_CLASS_HID_15f1a = 0x15f1a, - BNXT_ULP_CLASS_HID_14bee = 0x14bee, - BNXT_ULP_CLASS_HID_1312a = 0x1312a, - BNXT_ULP_CLASS_HID_12dea = 0x12dea, - BNXT_ULP_CLASS_HID_17d1e = 0x17d1e, - BNXT_ULP_CLASS_HID_169de = 0x169de, - BNXT_ULP_CLASS_HID_11ee6 = 0x11ee6, - BNXT_ULP_CLASS_HID_10abe = 0x10abe, - BNXT_ULP_CLASS_HID_15ade = 0x15ade, - BNXT_ULP_CLASS_HID_1569e = 0x1569e, - BNXT_ULP_CLASS_HID_13cee = 0x13cee, - BNXT_ULP_CLASS_HID_128ae = 0x128ae, - BNXT_ULP_CLASS_HID_1676e = 0x1676e, - BNXT_ULP_CLASS_HID_1748e = 0x1748e, - BNXT_ULP_CLASS_HID_1098e = 0x1098e, - BNXT_ULP_CLASS_HID_1044e = 0x1044e, - BNXT_ULP_CLASS_HID_1546e = 0x1546e, - BNXT_ULP_CLASS_HID_1402e = 0x1402e, - BNXT_ULP_CLASS_HID_1367e = 0x1367e, - BNXT_ULP_CLASS_HID_1223e = 0x1223e, - BNXT_ULP_CLASS_HID_1725e = 0x1725e, - BNXT_ULP_CLASS_HID_16e1e = 0x16e1e, - BNXT_ULP_CLASS_HID_1172f = 0x1172f, - BNXT_ULP_CLASS_HID_103ed = 0x103ed, - BNXT_ULP_CLASS_HID_1530b = 0x1530b, - BNXT_ULP_CLASS_HID_14fc9 = 0x14fc9, - BNXT_ULP_CLASS_HID_1351d = 0x1351d, - BNXT_ULP_CLASS_HID_121db = 0x121db, - BNXT_ULP_CLASS_HID_171f9 = 0x171f9, - BNXT_ULP_CLASS_HID_16db7 = 0x16db7, - BNXT_ULP_CLASS_HID_102bf = 0x102bf, - BNXT_ULP_CLASS_HID_11edf = 0x11edf, - BNXT_ULP_CLASS_HID_14e9b = 0x14e9b, - BNXT_ULP_CLASS_HID_15abb = 0x15abb, - BNXT_ULP_CLASS_HID_120ad = 0x120ad, - BNXT_ULP_CLASS_HID_13ccd = 0x13ccd, - BNXT_ULP_CLASS_HID_16c89 = 0x16c89, - BNXT_ULP_CLASS_HID_1675f = 0x1675f, - BNXT_ULP_CLASS_HID_10c67 = 0x10c67, - BNXT_ULP_CLASS_HID_11987 = 0x11987, - BNXT_ULP_CLASS_HID_1485f = 0x1485f, - BNXT_ULP_CLASS_HID_1441d = 0x1441d, - BNXT_ULP_CLASS_HID_12a55 = 0x12a55, - BNXT_ULP_CLASS_HID_1262f = 0x1262f, - BNXT_ULP_CLASS_HID_1764d = 0x1764d, - BNXT_ULP_CLASS_HID_1620f = 0x1620f, - BNXT_ULP_CLASS_HID_1070f = 0x1070f, - BNXT_ULP_CLASS_HID_1132f = 0x1132f, - BNXT_ULP_CLASS_HID_143ef = 0x143ef, - BNXT_ULP_CLASS_HID_15f0f = 0x15f0f, - BNXT_ULP_CLASS_HID_125fd = 0x125fd, - BNXT_ULP_CLASS_HID_1311d = 0x1311d, - BNXT_ULP_CLASS_HID_161dd = 0x161dd, - BNXT_ULP_CLASS_HID_17dfd = 0x17dfd, - BNXT_ULP_CLASS_HID_10acb = 0x10acb, - BNXT_ULP_CLASS_HID_10687 = 0x10687, - BNXT_ULP_CLASS_HID_156a7 = 0x156a7, - BNXT_ULP_CLASS_HID_14163 = 0x14163, - BNXT_ULP_CLASS_HID_128b7 = 0x128b7, - BNXT_ULP_CLASS_HID_12377 = 0x12377, - BNXT_ULP_CLASS_HID_17493 = 0x17493, - BNXT_ULP_CLASS_HID_16f53 = 0x16f53, - BNXT_ULP_CLASS_HID_1045b = 0x1045b, - BNXT_ULP_CLASS_HID_1107b = 0x1107b, - BNXT_ULP_CLASS_HID_1404f = 0x1404f, - BNXT_ULP_CLASS_HID_15c6f = 0x15c6f, - BNXT_ULP_CLASS_HID_1225f = 0x1225f, - BNXT_ULP_CLASS_HID_13e7f = 0x13e7f, - BNXT_ULP_CLASS_HID_16e3b = 0x16e3b, - BNXT_ULP_CLASS_HID_17a5b = 0x17a5b, - BNXT_ULP_CLASS_HID_10f1f = 0x10f1f, - BNXT_ULP_CLASS_HID_11b3f = 0x11b3f, - BNXT_ULP_CLASS_HID_14bff = 0x14bff, - BNXT_ULP_CLASS_HID_147b7 = 0x147b7, - BNXT_ULP_CLASS_HID_12d0f = 0x12d0f, - BNXT_ULP_CLASS_HID_1392f = 0x1392f, - BNXT_ULP_CLASS_HID_169e7 = 0x169e7, - BNXT_ULP_CLASS_HID_165a7 = 0x165a7, - BNXT_ULP_CLASS_HID_11a0f = 0x11a0f, - BNXT_ULP_CLASS_HID_116cf = 0x116cf, - BNXT_ULP_CLASS_HID_1468f = 0x1468f, - BNXT_ULP_CLASS_HID_152af = 0x152af, - BNXT_ULP_CLASS_HID_138ff = 0x138ff, - BNXT_ULP_CLASS_HID_134bf = 0x134bf, - BNXT_ULP_CLASS_HID_1648f = 0x1648f, - BNXT_ULP_CLASS_HID_170af = 0x170af, - BNXT_ULP_CLASS_HID_40c38 = 0x40c38, - BNXT_ULP_CLASS_HID_41c04 = 0x41c04, - BNXT_ULP_CLASS_HID_51c48 = 0x51c48, - BNXT_ULP_CLASS_HID_50332 = 0x50332, - BNXT_ULP_CLASS_HID_48400 = 0x48400, - BNXT_ULP_CLASS_HID_48bea = 0x48bea, - BNXT_ULP_CLASS_HID_58b3e = 0x58b3e, - BNXT_ULP_CLASS_HID_59b7a = 0x59b7a, - BNXT_ULP_CLASS_HID_417dc = 0x417dc, - BNXT_ULP_CLASS_HID_40746 = 0x40746, - BNXT_ULP_CLASS_HID_5068a = 0x5068a, - BNXT_ULP_CLASS_HID_516d6 = 0x516d6, - BNXT_ULP_CLASS_HID_48f42 = 0x48f42, - BNXT_ULP_CLASS_HID_49e8e = 0x49e8e, - BNXT_ULP_CLASS_HID_59ed2 = 0x59ed2, - BNXT_ULP_CLASS_HID_58d9c = 0x58d9c, - BNXT_ULP_CLASS_HID_41a4a = 0x41a4a, - BNXT_ULP_CLASS_HID_40924 = 0x40924, - BNXT_ULP_CLASS_HID_50968 = 0x50968, - BNXT_ULP_CLASS_HID_51944 = 0x51944, - BNXT_ULP_CLASS_HID_49182 = 0x49182, - BNXT_ULP_CLASS_HID_4816c = 0x4816c, - BNXT_ULP_CLASS_HID_58140 = 0x58140, - BNXT_ULP_CLASS_HID_5908c = 0x5908c, - BNXT_ULP_CLASS_HID_40c8c = 0x40c8c, - BNXT_ULP_CLASS_HID_41cc8 = 0x41cc8, - BNXT_ULP_CLASS_HID_51c0c = 0x51c0c, - BNXT_ULP_CLASS_HID_50386 = 0x50386, - BNXT_ULP_CLASS_HID_484c4 = 0x484c4, - BNXT_ULP_CLASS_HID_48b8e = 0x48b8e, - BNXT_ULP_CLASS_HID_58b82 = 0x58b82, - BNXT_ULP_CLASS_HID_59bce = 0x59bce, - BNXT_ULP_CLASS_HID_10a54 = 0x10a54, - BNXT_ULP_CLASS_HID_11e74 = 0x11e74, - BNXT_ULP_CLASS_HID_14e48 = 0x14e48, - BNXT_ULP_CLASS_HID_15268 = 0x15268, - BNXT_ULP_CLASS_HID_1285a = 0x1285a, - BNXT_ULP_CLASS_HID_13c7a = 0x13c7a, - BNXT_ULP_CLASS_HID_163be = 0x163be, - BNXT_ULP_CLASS_HID_1705e = 0x1705e, - BNXT_ULP_CLASS_HID_11d5e = 0x11d5e, - BNXT_ULP_CLASS_HID_1009c = 0x1009c, - BNXT_ULP_CLASS_HID_150ba = 0x150ba, - BNXT_ULP_CLASS_HID_144f8 = 0x144f8, - BNXT_ULP_CLASS_HID_1334c = 0x1334c, - BNXT_ULP_CLASS_HID_1268a = 0x1268a, - BNXT_ULP_CLASS_HID_176a8 = 0x176a8, - BNXT_ULP_CLASS_HID_17aee = 0x17aee, - BNXT_ULP_CLASS_HID_11782 = 0x11782, - BNXT_ULP_CLASS_HID_11bc0 = 0x11bc0, - BNXT_ULP_CLASS_HID_14b00 = 0x14b00, - BNXT_ULP_CLASS_HID_15f20 = 0x15f20, - BNXT_ULP_CLASS_HID_135f0 = 0x135f0, - BNXT_ULP_CLASS_HID_13932 = 0x13932, - BNXT_ULP_CLASS_HID_1690a = 0x1690a, - BNXT_ULP_CLASS_HID_17d2a = 0x17d2a, - BNXT_ULP_CLASS_HID_11a2a = 0x11a2a, - BNXT_ULP_CLASS_HID_10e68 = 0x10e68, - BNXT_ULP_CLASS_HID_15e0a = 0x15e0a, - BNXT_ULP_CLASS_HID_14248 = 0x14248, - BNXT_ULP_CLASS_HID_13818 = 0x13818, - BNXT_ULP_CLASS_HID_12c5a = 0x12c5a, - BNXT_ULP_CLASS_HID_17c78 = 0x17c78, - BNXT_ULP_CLASS_HID_167ba = 0x167ba, - BNXT_ULP_CLASS_HID_1f91 = 0x1f91, - BNXT_ULP_CLASS_HID_0763 = 0x0763, - BNXT_ULP_CLASS_HID_0f7b = 0x0f7b, - BNXT_ULP_CLASS_HID_16af = 0x16af, - BNXT_ULP_CLASS_HID_1daf = 0x1daf, - BNXT_ULP_CLASS_HID_0539 = 0x0539, - BNXT_ULP_CLASS_HID_01ed = 0x01ed, - BNXT_ULP_CLASS_HID_097f = 0x097f, - BNXT_ULP_CLASS_HID_81ab8 = 0x81ab8, - BNXT_ULP_CLASS_HID_8020e = 0x8020e, - BNXT_ULP_CLASS_HID_815d8 = 0x815d8, - BNXT_ULP_CLASS_HID_81cae = 0x81cae, - BNXT_ULP_CLASS_HID_810a8 = 0x810a8, - BNXT_ULP_CLASS_HID_8183e = 0x8183e, - BNXT_ULP_CLASS_HID_8036a = 0x8036a, - BNXT_ULP_CLASS_HID_80af8 = 0x80af8, - BNXT_ULP_CLASS_HID_206fe = 0x206fe, - BNXT_ULP_CLASS_HID_20e4c = 0x20e4c, - BNXT_ULP_CLASS_HID_2111e = 0x2111e, - BNXT_ULP_CLASS_HID_218ec = 0x218ec, - BNXT_ULP_CLASS_HID_60472 = 0x60472, - BNXT_ULP_CLASS_HID_603c0 = 0x603c0, - BNXT_ULP_CLASS_HID_61692 = 0x61692, - BNXT_ULP_CLASS_HID_61e60 = 0x61e60, - BNXT_ULP_CLASS_HID_1f81 = 0x1f81, - BNXT_ULP_CLASS_HID_0773 = 0x0773, - BNXT_ULP_CLASS_HID_0f6b = 0x0f6b, - BNXT_ULP_CLASS_HID_16bf = 0x16bf, - BNXT_ULP_CLASS_HID_03cf = 0x03cf, - BNXT_ULP_CLASS_HID_0ab1 = 0x0ab1, - BNXT_ULP_CLASS_HID_130b = 0x130b, - BNXT_ULP_CLASS_HID_1afd = 0x1afd, - BNXT_ULP_CLASS_HID_1591 = 0x1591, - BNXT_ULP_CLASS_HID_1d03 = 0x1d03, - BNXT_ULP_CLASS_HID_057b = 0x057b, - BNXT_ULP_CLASS_HID_0ced = 0x0ced, - BNXT_ULP_CLASS_HID_19df = 0x19df, - BNXT_ULP_CLASS_HID_0141 = 0x0141, - BNXT_ULP_CLASS_HID_08b9 = 0x08b9, - BNXT_ULP_CLASS_HID_108d = 0x108d, - BNXT_ULP_CLASS_HID_1dbf = 0x1dbf, - BNXT_ULP_CLASS_HID_0529 = 0x0529, - BNXT_ULP_CLASS_HID_01fd = 0x01fd, - BNXT_ULP_CLASS_HID_096f = 0x096f, - BNXT_ULP_CLASS_HID_810b7 = 0x810b7, - BNXT_ULP_CLASS_HID_81821 = 0x81821, - BNXT_ULP_CLASS_HID_804f5 = 0x804f5, - BNXT_ULP_CLASS_HID_80c67 = 0x80c67, - BNXT_ULP_CLASS_HID_41333 = 0x41333, - BNXT_ULP_CLASS_HID_41aad = 0x41aad, - BNXT_ULP_CLASS_HID_40771 = 0x40771, - BNXT_ULP_CLASS_HID_40ee3 = 0x40ee3, - BNXT_ULP_CLASS_HID_c16cb = 0xc16cb, - BNXT_ULP_CLASS_HID_c1da5 = 0xc1da5, - BNXT_ULP_CLASS_HID_c1a09 = 0xc1a09, - BNXT_ULP_CLASS_HID_c01fb = 0xc01fb, - BNXT_ULP_CLASS_HID_1ff1 = 0x1ff1, - BNXT_ULP_CLASS_HID_0703 = 0x0703, - BNXT_ULP_CLASS_HID_0f1b = 0x0f1b, - BNXT_ULP_CLASS_HID_16cf = 0x16cf, - BNXT_ULP_CLASS_HID_03bf = 0x03bf, - BNXT_ULP_CLASS_HID_0ac1 = 0x0ac1, - BNXT_ULP_CLASS_HID_137b = 0x137b, - BNXT_ULP_CLASS_HID_1a8d = 0x1a8d, - BNXT_ULP_CLASS_HID_15e1 = 0x15e1, - BNXT_ULP_CLASS_HID_1d73 = 0x1d73, - BNXT_ULP_CLASS_HID_050b = 0x050b, - BNXT_ULP_CLASS_HID_0c9d = 0x0c9d, - BNXT_ULP_CLASS_HID_19af = 0x19af, - BNXT_ULP_CLASS_HID_0131 = 0x0131, - BNXT_ULP_CLASS_HID_08c9 = 0x08c9, - BNXT_ULP_CLASS_HID_10fd = 0x10fd, - BNXT_ULP_CLASS_HID_1dcf = 0x1dcf, - BNXT_ULP_CLASS_HID_0559 = 0x0559, - BNXT_ULP_CLASS_HID_018d = 0x018d, - BNXT_ULP_CLASS_HID_091f = 0x091f, - BNXT_ULP_CLASS_HID_810c7 = 0x810c7, - BNXT_ULP_CLASS_HID_81851 = 0x81851, - BNXT_ULP_CLASS_HID_80485 = 0x80485, - BNXT_ULP_CLASS_HID_80c17 = 0x80c17, - BNXT_ULP_CLASS_HID_41343 = 0x41343, - BNXT_ULP_CLASS_HID_41add = 0x41add, - BNXT_ULP_CLASS_HID_40701 = 0x40701, - BNXT_ULP_CLASS_HID_40e93 = 0x40e93, - BNXT_ULP_CLASS_HID_c16bb = 0xc16bb, - BNXT_ULP_CLASS_HID_c1dd5 = 0xc1dd5, - BNXT_ULP_CLASS_HID_c1a79 = 0xc1a79, - BNXT_ULP_CLASS_HID_c018b = 0xc018b, - BNXT_ULP_CLASS_HID_81aa8 = 0x81aa8, - BNXT_ULP_CLASS_HID_8021e = 0x8021e, - BNXT_ULP_CLASS_HID_815c8 = 0x815c8, - BNXT_ULP_CLASS_HID_81cbe = 0x81cbe, - BNXT_ULP_CLASS_HID_810b8 = 0x810b8, - BNXT_ULP_CLASS_HID_8182e = 0x8182e, - BNXT_ULP_CLASS_HID_8037a = 0x8037a, - BNXT_ULP_CLASS_HID_80ae8 = 0x80ae8, - BNXT_ULP_CLASS_HID_c1834 = 0xc1834, - BNXT_ULP_CLASS_HID_c079a = 0xc079a, - BNXT_ULP_CLASS_HID_c0af6 = 0xc0af6, - BNXT_ULP_CLASS_HID_c123a = 0xc123a, - BNXT_ULP_CLASS_HID_c16c4 = 0xc16c4, - BNXT_ULP_CLASS_HID_c1daa = 0xc1daa, - BNXT_ULP_CLASS_HID_c0086 = 0xc0086, - BNXT_ULP_CLASS_HID_c0874 = 0xc0874, - BNXT_ULP_CLASS_HID_a19ea = 0xa19ea, - BNXT_ULP_CLASS_HID_a0158 = 0xa0158, - BNXT_ULP_CLASS_HID_a0bb4 = 0xa0bb4, - BNXT_ULP_CLASS_HID_a13f8 = 0xa13f8, - BNXT_ULP_CLASS_HID_a17fa = 0xa17fa, - BNXT_ULP_CLASS_HID_a1f68 = 0xa1f68, - BNXT_ULP_CLASS_HID_a0244 = 0xa0244, - BNXT_ULP_CLASS_HID_a092a = 0xa092a, - BNXT_ULP_CLASS_HID_e1f76 = 0xe1f76, - BNXT_ULP_CLASS_HID_e06e4 = 0xe06e4, - BNXT_ULP_CLASS_HID_e0930 = 0xe0930, - BNXT_ULP_CLASS_HID_e1104 = 0xe1104, - BNXT_ULP_CLASS_HID_e1506 = 0xe1506, - BNXT_ULP_CLASS_HID_e1cf4 = 0xe1cf4, - BNXT_ULP_CLASS_HID_e07c0 = 0xe07c0, - BNXT_ULP_CLASS_HID_e0eb6 = 0xe0eb6, - BNXT_ULP_CLASS_HID_206ee = 0x206ee, - BNXT_ULP_CLASS_HID_20e5c = 0x20e5c, - BNXT_ULP_CLASS_HID_2110e = 0x2110e, - BNXT_ULP_CLASS_HID_218fc = 0x218fc, - BNXT_ULP_CLASS_HID_60462 = 0x60462, - BNXT_ULP_CLASS_HID_603d0 = 0x603d0, - BNXT_ULP_CLASS_HID_61682 = 0x61682, - BNXT_ULP_CLASS_HID_61e70 = 0x61e70, - BNXT_ULP_CLASS_HID_3167e = 0x3167e, - BNXT_ULP_CLASS_HID_31dec = 0x31dec, - BNXT_ULP_CLASS_HID_30030 = 0x30030, - BNXT_ULP_CLASS_HID_30fae = 0x30fae, - BNXT_ULP_CLASS_HID_70b14 = 0x70b14, - BNXT_ULP_CLASS_HID_71360 = 0x71360, - BNXT_ULP_CLASS_HID_705b4 = 0x705b4, - BNXT_ULP_CLASS_HID_70d22 = 0x70d22, - BNXT_ULP_CLASS_HID_29e26 = 0x29e26, - BNXT_ULP_CLASS_HID_28594 = 0x28594, - BNXT_ULP_CLASS_HID_288f8 = 0x288f8, - BNXT_ULP_CLASS_HID_29034 = 0x29034, - BNXT_ULP_CLASS_HID_693ba = 0x693ba, - BNXT_ULP_CLASS_HID_69b28 = 0x69b28, - BNXT_ULP_CLASS_HID_68e7c = 0x68e7c, - BNXT_ULP_CLASS_HID_69648 = 0x69648, - BNXT_ULP_CLASS_HID_38de8 = 0x38de8, - BNXT_ULP_CLASS_HID_39524 = 0x39524, - BNXT_ULP_CLASS_HID_39808 = 0x39808, - BNXT_ULP_CLASS_HID_387e6 = 0x387e6, - BNXT_ULP_CLASS_HID_7836c = 0x7836c, - BNXT_ULP_CLASS_HID_78ada = 0x78ada, - BNXT_ULP_CLASS_HID_79d8c = 0x79d8c, - BNXT_ULP_CLASS_HID_7857a = 0x7857a, - BNXT_ULP_CLASS_HID_81ad8 = 0x81ad8, - BNXT_ULP_CLASS_HID_8026e = 0x8026e, - BNXT_ULP_CLASS_HID_815b8 = 0x815b8, - BNXT_ULP_CLASS_HID_81cce = 0x81cce, - BNXT_ULP_CLASS_HID_810c8 = 0x810c8, - BNXT_ULP_CLASS_HID_8185e = 0x8185e, - BNXT_ULP_CLASS_HID_8030a = 0x8030a, - BNXT_ULP_CLASS_HID_80a98 = 0x80a98, - BNXT_ULP_CLASS_HID_c1844 = 0xc1844, - BNXT_ULP_CLASS_HID_c07ea = 0xc07ea, - BNXT_ULP_CLASS_HID_c0a86 = 0xc0a86, - BNXT_ULP_CLASS_HID_c124a = 0xc124a, - BNXT_ULP_CLASS_HID_c16b4 = 0xc16b4, - BNXT_ULP_CLASS_HID_c1dda = 0xc1dda, - BNXT_ULP_CLASS_HID_c00f6 = 0xc00f6, - BNXT_ULP_CLASS_HID_c0804 = 0xc0804, - BNXT_ULP_CLASS_HID_a199a = 0xa199a, - BNXT_ULP_CLASS_HID_a0128 = 0xa0128, - BNXT_ULP_CLASS_HID_a0bc4 = 0xa0bc4, - BNXT_ULP_CLASS_HID_a1388 = 0xa1388, - BNXT_ULP_CLASS_HID_a178a = 0xa178a, - BNXT_ULP_CLASS_HID_a1f18 = 0xa1f18, - BNXT_ULP_CLASS_HID_a0234 = 0xa0234, - BNXT_ULP_CLASS_HID_a095a = 0xa095a, - BNXT_ULP_CLASS_HID_e1f06 = 0xe1f06, - BNXT_ULP_CLASS_HID_e0694 = 0xe0694, - BNXT_ULP_CLASS_HID_e0940 = 0xe0940, - BNXT_ULP_CLASS_HID_e1174 = 0xe1174, - BNXT_ULP_CLASS_HID_e1576 = 0xe1576, - BNXT_ULP_CLASS_HID_e1c84 = 0xe1c84, - BNXT_ULP_CLASS_HID_e07b0 = 0xe07b0, - BNXT_ULP_CLASS_HID_e0ec6 = 0xe0ec6, - BNXT_ULP_CLASS_HID_2069e = 0x2069e, - BNXT_ULP_CLASS_HID_20e2c = 0x20e2c, - BNXT_ULP_CLASS_HID_2117e = 0x2117e, - BNXT_ULP_CLASS_HID_2188c = 0x2188c, - BNXT_ULP_CLASS_HID_60412 = 0x60412, - BNXT_ULP_CLASS_HID_603a0 = 0x603a0, - BNXT_ULP_CLASS_HID_616f2 = 0x616f2, - BNXT_ULP_CLASS_HID_61e00 = 0x61e00, - BNXT_ULP_CLASS_HID_3160e = 0x3160e, - BNXT_ULP_CLASS_HID_31d9c = 0x31d9c, - BNXT_ULP_CLASS_HID_30040 = 0x30040, - BNXT_ULP_CLASS_HID_30fde = 0x30fde, - BNXT_ULP_CLASS_HID_70b64 = 0x70b64, - BNXT_ULP_CLASS_HID_71310 = 0x71310, - BNXT_ULP_CLASS_HID_705c4 = 0x705c4, - BNXT_ULP_CLASS_HID_70d52 = 0x70d52, - BNXT_ULP_CLASS_HID_29e56 = 0x29e56, - BNXT_ULP_CLASS_HID_285e4 = 0x285e4, - BNXT_ULP_CLASS_HID_28888 = 0x28888, - BNXT_ULP_CLASS_HID_29044 = 0x29044, - BNXT_ULP_CLASS_HID_693ca = 0x693ca, - BNXT_ULP_CLASS_HID_69b58 = 0x69b58, - BNXT_ULP_CLASS_HID_68e0c = 0x68e0c, - BNXT_ULP_CLASS_HID_69638 = 0x69638, - BNXT_ULP_CLASS_HID_38d98 = 0x38d98, - BNXT_ULP_CLASS_HID_39554 = 0x39554, - BNXT_ULP_CLASS_HID_39878 = 0x39878, - BNXT_ULP_CLASS_HID_38796 = 0x38796, - BNXT_ULP_CLASS_HID_7831c = 0x7831c, - BNXT_ULP_CLASS_HID_78aaa = 0x78aaa, - BNXT_ULP_CLASS_HID_79dfc = 0x79dfc, - BNXT_ULP_CLASS_HID_7850a = 0x7850a, - BNXT_ULP_CLASS_HID_03b7 = 0x03b7, - BNXT_ULP_CLASS_HID_13f3 = 0x13f3, - BNXT_ULP_CLASS_HID_0255 = 0x0255, - BNXT_ULP_CLASS_HID_1675 = 0x1675, - BNXT_ULP_CLASS_HID_80f52 = 0x80f52, - BNXT_ULP_CLASS_HID_819f2 = 0x819f2, - BNXT_ULP_CLASS_HID_80542 = 0x80542, - BNXT_ULP_CLASS_HID_817e2 = 0x817e2, - BNXT_ULP_CLASS_HID_20a98 = 0x20a98, - BNXT_ULP_CLASS_HID_20538 = 0x20538, - BNXT_ULP_CLASS_HID_6081c = 0x6081c, - BNXT_ULP_CLASS_HID_61abc = 0x61abc, - BNXT_ULP_CLASS_HID_03a7 = 0x03a7, - BNXT_ULP_CLASS_HID_13e3 = 0x13e3, - BNXT_ULP_CLASS_HID_1047 = 0x1047, - BNXT_ULP_CLASS_HID_0721 = 0x0721, - BNXT_ULP_CLASS_HID_19b7 = 0x19b7, - BNXT_ULP_CLASS_HID_0911 = 0x0911, - BNXT_ULP_CLASS_HID_0df5 = 0x0df5, - BNXT_ULP_CLASS_HID_1d31 = 0x1d31, - BNXT_ULP_CLASS_HID_0245 = 0x0245, - BNXT_ULP_CLASS_HID_1665 = 0x1665, - BNXT_ULP_CLASS_HID_8055d = 0x8055d, - BNXT_ULP_CLASS_HID_80893 = 0x80893, - BNXT_ULP_CLASS_HID_407d9 = 0x407d9, - BNXT_ULP_CLASS_HID_40b1f = 0x40b1f, - BNXT_ULP_CLASS_HID_c1ad1 = 0xc1ad1, - BNXT_ULP_CLASS_HID_c0e17 = 0xc0e17, - BNXT_ULP_CLASS_HID_03d7 = 0x03d7, - BNXT_ULP_CLASS_HID_1393 = 0x1393, - BNXT_ULP_CLASS_HID_1037 = 0x1037, - BNXT_ULP_CLASS_HID_0751 = 0x0751, - BNXT_ULP_CLASS_HID_19c7 = 0x19c7, - BNXT_ULP_CLASS_HID_0961 = 0x0961, - BNXT_ULP_CLASS_HID_0d85 = 0x0d85, - BNXT_ULP_CLASS_HID_1d41 = 0x1d41, - BNXT_ULP_CLASS_HID_0235 = 0x0235, - BNXT_ULP_CLASS_HID_1615 = 0x1615, - BNXT_ULP_CLASS_HID_8052d = 0x8052d, - BNXT_ULP_CLASS_HID_808e3 = 0x808e3, - BNXT_ULP_CLASS_HID_407a9 = 0x407a9, - BNXT_ULP_CLASS_HID_40b6f = 0x40b6f, - BNXT_ULP_CLASS_HID_c1aa1 = 0xc1aa1, - BNXT_ULP_CLASS_HID_c0e67 = 0xc0e67, - BNXT_ULP_CLASS_HID_80f42 = 0x80f42, - BNXT_ULP_CLASS_HID_819e2 = 0x819e2, - BNXT_ULP_CLASS_HID_80552 = 0x80552, - BNXT_ULP_CLASS_HID_817f2 = 0x817f2, - BNXT_ULP_CLASS_HID_c0cce = 0xc0cce, - BNXT_ULP_CLASS_HID_c1f6e = 0xc1f6e, - BNXT_ULP_CLASS_HID_c1ade = 0xc1ade, - BNXT_ULP_CLASS_HID_c157e = 0xc157e, - BNXT_ULP_CLASS_HID_a0d8c = 0xa0d8c, - BNXT_ULP_CLASS_HID_a182c = 0xa182c, - BNXT_ULP_CLASS_HID_a1b9c = 0xa1b9c, - BNXT_ULP_CLASS_HID_a163c = 0xa163c, - BNXT_ULP_CLASS_HID_e0308 = 0xe0308, - BNXT_ULP_CLASS_HID_e1da8 = 0xe1da8, - BNXT_ULP_CLASS_HID_e1918 = 0xe1918, - BNXT_ULP_CLASS_HID_e0bda = 0xe0bda, - BNXT_ULP_CLASS_HID_20a88 = 0x20a88, - BNXT_ULP_CLASS_HID_20528 = 0x20528, - BNXT_ULP_CLASS_HID_6080c = 0x6080c, - BNXT_ULP_CLASS_HID_61aac = 0x61aac, - BNXT_ULP_CLASS_HID_31a18 = 0x31a18, - BNXT_ULP_CLASS_HID_314b8 = 0x314b8, - BNXT_ULP_CLASS_HID_71f9c = 0x71f9c, - BNXT_ULP_CLASS_HID_70a5e = 0x70a5e, - BNXT_ULP_CLASS_HID_282c0 = 0x282c0, - BNXT_ULP_CLASS_HID_29d60 = 0x29d60, - BNXT_ULP_CLASS_HID_68044 = 0x68044, - BNXT_ULP_CLASS_HID_692e4 = 0x692e4, - BNXT_ULP_CLASS_HID_39250 = 0x39250, - BNXT_ULP_CLASS_HID_38c12 = 0x38c12, - BNXT_ULP_CLASS_HID_797d4 = 0x797d4, - BNXT_ULP_CLASS_HID_78196 = 0x78196, - BNXT_ULP_CLASS_HID_80f32 = 0x80f32, - BNXT_ULP_CLASS_HID_81992 = 0x81992, - BNXT_ULP_CLASS_HID_80522 = 0x80522, - BNXT_ULP_CLASS_HID_81782 = 0x81782, - BNXT_ULP_CLASS_HID_c0cbe = 0xc0cbe, - BNXT_ULP_CLASS_HID_c1f1e = 0xc1f1e, - BNXT_ULP_CLASS_HID_c1aae = 0xc1aae, - BNXT_ULP_CLASS_HID_c150e = 0xc150e, - BNXT_ULP_CLASS_HID_a0dfc = 0xa0dfc, - BNXT_ULP_CLASS_HID_a185c = 0xa185c, - BNXT_ULP_CLASS_HID_a1bec = 0xa1bec, - BNXT_ULP_CLASS_HID_a164c = 0xa164c, - BNXT_ULP_CLASS_HID_e0378 = 0xe0378, - BNXT_ULP_CLASS_HID_e1dd8 = 0xe1dd8, - BNXT_ULP_CLASS_HID_e1968 = 0xe1968, - BNXT_ULP_CLASS_HID_e0baa = 0xe0baa, - BNXT_ULP_CLASS_HID_20af8 = 0x20af8, - BNXT_ULP_CLASS_HID_20558 = 0x20558, - BNXT_ULP_CLASS_HID_6087c = 0x6087c, - BNXT_ULP_CLASS_HID_61adc = 0x61adc, - BNXT_ULP_CLASS_HID_31a68 = 0x31a68, - BNXT_ULP_CLASS_HID_314c8 = 0x314c8, - BNXT_ULP_CLASS_HID_71fec = 0x71fec, - BNXT_ULP_CLASS_HID_70a2e = 0x70a2e, - BNXT_ULP_CLASS_HID_282b0 = 0x282b0, - BNXT_ULP_CLASS_HID_29d10 = 0x29d10, - BNXT_ULP_CLASS_HID_68034 = 0x68034, - BNXT_ULP_CLASS_HID_69294 = 0x69294, - BNXT_ULP_CLASS_HID_39220 = 0x39220, - BNXT_ULP_CLASS_HID_38c62 = 0x38c62, - BNXT_ULP_CLASS_HID_797a4 = 0x797a4, - BNXT_ULP_CLASS_HID_781e6 = 0x781e6, - BNXT_ULP_CLASS_HID_0f05 = 0x0f05, - BNXT_ULP_CLASS_HID_0f09 = 0x0f09, - BNXT_ULP_CLASS_HID_0f06 = 0x0f06, - BNXT_ULP_CLASS_HID_19a6 = 0x19a6, - BNXT_ULP_CLASS_HID_0f0a = 0x0f0a, - BNXT_ULP_CLASS_HID_19aa = 0x19aa, - BNXT_ULP_CLASS_HID_0f15 = 0x0f15, - BNXT_ULP_CLASS_HID_0f19 = 0x0f19, - BNXT_ULP_CLASS_HID_0f65 = 0x0f65, - BNXT_ULP_CLASS_HID_0f69 = 0x0f69, - BNXT_ULP_CLASS_HID_0f16 = 0x0f16, - BNXT_ULP_CLASS_HID_19b6 = 0x19b6, - BNXT_ULP_CLASS_HID_0f1a = 0x0f1a, - BNXT_ULP_CLASS_HID_19ba = 0x19ba, - BNXT_ULP_CLASS_HID_0f66 = 0x0f66, - BNXT_ULP_CLASS_HID_19c6 = 0x19c6, - BNXT_ULP_CLASS_HID_0f6a = 0x0f6a, - BNXT_ULP_CLASS_HID_19ca = 0x19ca -}; - -enum bnxt_ulp_act_hid { - BNXT_ULP_ACT_HID_0000 = 0x0000, - BNXT_ULP_ACT_HID_0040 = 0x0040, - BNXT_ULP_ACT_HID_10000 = 0x10000, - BNXT_ULP_ACT_HID_cc40 = 0xcc40, - BNXT_ULP_ACT_HID_0400 = 0x0400, - BNXT_ULP_ACT_HID_1cc40 = 0x1cc40, - BNXT_ULP_ACT_HID_d040 = 0xd040, - BNXT_ULP_ACT_HID_0080 = 0x0080, - BNXT_ULP_ACT_HID_0200 = 0x0200, - BNXT_ULP_ACT_HID_0280 = 0x0280, - BNXT_ULP_ACT_HID_00c0 = 0x00c0, - BNXT_ULP_ACT_HID_10080 = 0x10080, - BNXT_ULP_ACT_HID_ccc0 = 0xccc0, - BNXT_ULP_ACT_HID_0480 = 0x0480, - BNXT_ULP_ACT_HID_1ccc0 = 0x1ccc0, - BNXT_ULP_ACT_HID_d0c0 = 0xd0c0, - BNXT_ULP_ACT_HID_19742 = 0x19742, - BNXT_ULP_ACT_HID_19782 = 0x19782, - BNXT_ULP_ACT_HID_29742 = 0x29742, - BNXT_ULP_ACT_HID_26382 = 0x26382, - BNXT_ULP_ACT_HID_19b42 = 0x19b42, - BNXT_ULP_ACT_HID_36382 = 0x36382, - BNXT_ULP_ACT_HID_26782 = 0x26782, - BNXT_ULP_ACT_HID_197c2 = 0x197c2, - BNXT_ULP_ACT_HID_19802 = 0x19802, - BNXT_ULP_ACT_HID_297c2 = 0x297c2, - BNXT_ULP_ACT_HID_26402 = 0x26402, - BNXT_ULP_ACT_HID_19bc2 = 0x19bc2, - BNXT_ULP_ACT_HID_36402 = 0x36402, - BNXT_ULP_ACT_HID_26802 = 0x26802, - BNXT_ULP_ACT_HID_bca0 = 0xbca0, - BNXT_ULP_ACT_HID_bce0 = 0xbce0, - BNXT_ULP_ACT_HID_1bca0 = 0x1bca0, - BNXT_ULP_ACT_HID_168e0 = 0x168e0, - BNXT_ULP_ACT_HID_a0a0 = 0xa0a0, - BNXT_ULP_ACT_HID_268e0 = 0x268e0, - BNXT_ULP_ACT_HID_16ce0 = 0x16ce0, - BNXT_ULP_ACT_HID_bd20 = 0xbd20, - BNXT_ULP_ACT_HID_bd60 = 0xbd60, - BNXT_ULP_ACT_HID_1bd20 = 0x1bd20, - BNXT_ULP_ACT_HID_16960 = 0x16960, - BNXT_ULP_ACT_HID_a120 = 0xa120, - BNXT_ULP_ACT_HID_26960 = 0x26960, - BNXT_ULP_ACT_HID_16d60 = 0x16d60, - BNXT_ULP_ACT_HID_4040 = 0x4040, - BNXT_ULP_ACT_HID_8040 = 0x8040, - BNXT_ULP_ACT_HID_c040 = 0xc040, - BNXT_ULP_ACT_HID_40c0 = 0x40c0, - BNXT_ULP_ACT_HID_80c0 = 0x80c0, - BNXT_ULP_ACT_HID_c0c0 = 0xc0c0, - BNXT_ULP_ACT_HID_4400 = 0x4400, - BNXT_ULP_ACT_HID_8400 = 0x8400, - BNXT_ULP_ACT_HID_c400 = 0xc400, - BNXT_ULP_ACT_HID_4480 = 0x4480, - BNXT_ULP_ACT_HID_8480 = 0x8480, - BNXT_ULP_ACT_HID_c480 = 0xc480, - BNXT_ULP_ACT_HID_1d782 = 0x1d782, - BNXT_ULP_ACT_HID_21782 = 0x21782, - BNXT_ULP_ACT_HID_25782 = 0x25782, - BNXT_ULP_ACT_HID_1d802 = 0x1d802, - BNXT_ULP_ACT_HID_21802 = 0x21802, - BNXT_ULP_ACT_HID_25802 = 0x25802, - BNXT_ULP_ACT_HID_1db42 = 0x1db42, - BNXT_ULP_ACT_HID_21b42 = 0x21b42, - BNXT_ULP_ACT_HID_25b42 = 0x25b42, - BNXT_ULP_ACT_HID_1dbc2 = 0x1dbc2, - BNXT_ULP_ACT_HID_21bc2 = 0x21bc2, - BNXT_ULP_ACT_HID_25bc2 = 0x25bc2, - BNXT_ULP_ACT_HID_fce0 = 0xfce0, - BNXT_ULP_ACT_HID_13ce0 = 0x13ce0, - BNXT_ULP_ACT_HID_17ce0 = 0x17ce0, - BNXT_ULP_ACT_HID_fd60 = 0xfd60, - BNXT_ULP_ACT_HID_13d60 = 0x13d60, - BNXT_ULP_ACT_HID_17d60 = 0x17d60, - BNXT_ULP_ACT_HID_e0a0 = 0xe0a0, - BNXT_ULP_ACT_HID_120a0 = 0x120a0, - BNXT_ULP_ACT_HID_160a0 = 0x160a0, - BNXT_ULP_ACT_HID_e120 = 0xe120, - BNXT_ULP_ACT_HID_12120 = 0x12120, - BNXT_ULP_ACT_HID_16120 = 0x16120, - BNXT_ULP_ACT_HID_32061 = 0x32061, - BNXT_ULP_ACT_HID_320e1 = 0x320e1, - BNXT_ULP_ACT_HID_388a = 0x388a, - BNXT_ULP_ACT_HID_4000 = 0x4000, - BNXT_ULP_ACT_HID_8000 = 0x8000, - BNXT_ULP_ACT_HID_c000 = 0xc000, - BNXT_ULP_ACT_HID_4080 = 0x4080, - BNXT_ULP_ACT_HID_8080 = 0x8080, - BNXT_ULP_ACT_HID_c080 = 0xc080, - BNXT_ULP_ACT_HID_8880 = 0x8880, - BNXT_ULP_ACT_HID_22100 = 0x22100, - BNXT_ULP_ACT_HID_11100 = 0x11100, - BNXT_ULP_ACT_HID_6420 = 0x6420, - BNXT_ULP_ACT_HID_1fca0 = 0x1fca0, - BNXT_ULP_ACT_HID_19980 = 0x19980, - BNXT_ULP_ACT_HID_28520 = 0x28520, - BNXT_ULP_ACT_HID_c880 = 0xc880, - BNXT_ULP_ACT_HID_26100 = 0x26100, - BNXT_ULP_ACT_HID_15100 = 0x15100, - BNXT_ULP_ACT_HID_a420 = 0xa420, - BNXT_ULP_ACT_HID_23ca0 = 0x23ca0, - BNXT_ULP_ACT_HID_1d980 = 0x1d980, - BNXT_ULP_ACT_HID_2c520 = 0x2c520, - BNXT_ULP_ACT_HID_10880 = 0x10880, - BNXT_ULP_ACT_HID_2a100 = 0x2a100, - BNXT_ULP_ACT_HID_19100 = 0x19100, - BNXT_ULP_ACT_HID_e420 = 0xe420, - BNXT_ULP_ACT_HID_27ca0 = 0x27ca0, - BNXT_ULP_ACT_HID_21980 = 0x21980, - BNXT_ULP_ACT_HID_30520 = 0x30520, - BNXT_ULP_ACT_HID_14880 = 0x14880, - BNXT_ULP_ACT_HID_2e100 = 0x2e100, - BNXT_ULP_ACT_HID_1d100 = 0x1d100, - BNXT_ULP_ACT_HID_12420 = 0x12420, - BNXT_ULP_ACT_HID_2bca0 = 0x2bca0, - BNXT_ULP_ACT_HID_25980 = 0x25980, - BNXT_ULP_ACT_HID_34520 = 0x34520, - BNXT_ULP_ACT_HID_8900 = 0x8900, - BNXT_ULP_ACT_HID_22180 = 0x22180, - BNXT_ULP_ACT_HID_11180 = 0x11180, - BNXT_ULP_ACT_HID_64a0 = 0x64a0, - BNXT_ULP_ACT_HID_1fd20 = 0x1fd20, - BNXT_ULP_ACT_HID_19a00 = 0x19a00, - BNXT_ULP_ACT_HID_285a0 = 0x285a0, - BNXT_ULP_ACT_HID_c900 = 0xc900, - BNXT_ULP_ACT_HID_26180 = 0x26180, - BNXT_ULP_ACT_HID_15180 = 0x15180, - BNXT_ULP_ACT_HID_a4a0 = 0xa4a0, - BNXT_ULP_ACT_HID_23d20 = 0x23d20, - BNXT_ULP_ACT_HID_1da00 = 0x1da00, - BNXT_ULP_ACT_HID_2c5a0 = 0x2c5a0, - BNXT_ULP_ACT_HID_10900 = 0x10900, - BNXT_ULP_ACT_HID_2a180 = 0x2a180, - BNXT_ULP_ACT_HID_19180 = 0x19180, - BNXT_ULP_ACT_HID_e4a0 = 0xe4a0, - BNXT_ULP_ACT_HID_27d20 = 0x27d20, - BNXT_ULP_ACT_HID_21a00 = 0x21a00, - BNXT_ULP_ACT_HID_305a0 = 0x305a0, - BNXT_ULP_ACT_HID_14900 = 0x14900, - BNXT_ULP_ACT_HID_2e180 = 0x2e180, - BNXT_ULP_ACT_HID_1d180 = 0x1d180, - BNXT_ULP_ACT_HID_124a0 = 0x124a0, - BNXT_ULP_ACT_HID_2bd20 = 0x2bd20, - BNXT_ULP_ACT_HID_25a00 = 0x25a00, - BNXT_ULP_ACT_HID_345a0 = 0x345a0, - BNXT_ULP_ACT_HID_154c0 = 0x154c0, - BNXT_ULP_ACT_HID_2ed40 = 0x2ed40, - BNXT_ULP_ACT_HID_1dd40 = 0x1dd40, - BNXT_ULP_ACT_HID_13060 = 0x13060, - BNXT_ULP_ACT_HID_2c8e0 = 0x2c8e0, - BNXT_ULP_ACT_HID_35160 = 0x35160, - BNXT_ULP_ACT_HID_15540 = 0x15540, - BNXT_ULP_ACT_HID_2edc0 = 0x2edc0, - BNXT_ULP_ACT_HID_1ddc0 = 0x1ddc0, - BNXT_ULP_ACT_HID_130e0 = 0x130e0, - BNXT_ULP_ACT_HID_2c960 = 0x2c960, - BNXT_ULP_ACT_HID_351e0 = 0x351e0, - BNXT_ULP_ACT_HID_194c0 = 0x194c0, - BNXT_ULP_ACT_HID_32d40 = 0x32d40, - BNXT_ULP_ACT_HID_21d40 = 0x21d40, - BNXT_ULP_ACT_HID_17060 = 0x17060, - BNXT_ULP_ACT_HID_308e0 = 0x308e0, - BNXT_ULP_ACT_HID_39160 = 0x39160, - BNXT_ULP_ACT_HID_19540 = 0x19540, - BNXT_ULP_ACT_HID_32dc0 = 0x32dc0, - BNXT_ULP_ACT_HID_21dc0 = 0x21dc0, - BNXT_ULP_ACT_HID_170e0 = 0x170e0, - BNXT_ULP_ACT_HID_30960 = 0x30960, - BNXT_ULP_ACT_HID_391e0 = 0x391e0, - BNXT_ULP_ACT_HID_1d4c0 = 0x1d4c0, - BNXT_ULP_ACT_HID_36d40 = 0x36d40, - BNXT_ULP_ACT_HID_25d40 = 0x25d40, - BNXT_ULP_ACT_HID_1b060 = 0x1b060, - BNXT_ULP_ACT_HID_348e0 = 0x348e0, - BNXT_ULP_ACT_HID_3d160 = 0x3d160, - BNXT_ULP_ACT_HID_1d540 = 0x1d540, - BNXT_ULP_ACT_HID_36dc0 = 0x36dc0, - BNXT_ULP_ACT_HID_25dc0 = 0x25dc0, - BNXT_ULP_ACT_HID_1b0e0 = 0x1b0e0, - BNXT_ULP_ACT_HID_34960 = 0x34960, - BNXT_ULP_ACT_HID_3d1e0 = 0x3d1e0, - BNXT_ULP_ACT_HID_214c0 = 0x214c0, - BNXT_ULP_ACT_HID_3ad40 = 0x3ad40, - BNXT_ULP_ACT_HID_29d40 = 0x29d40, - BNXT_ULP_ACT_HID_1f060 = 0x1f060, - BNXT_ULP_ACT_HID_388e0 = 0x388e0, - BNXT_ULP_ACT_HID_3380 = 0x3380, - BNXT_ULP_ACT_HID_21540 = 0x21540, - BNXT_ULP_ACT_HID_3adc0 = 0x3adc0, - BNXT_ULP_ACT_HID_29dc0 = 0x29dc0, - BNXT_ULP_ACT_HID_1f0e0 = 0x1f0e0, - BNXT_ULP_ACT_HID_38960 = 0x38960, - BNXT_ULP_ACT_HID_3400 = 0x3400, - BNXT_ULP_ACT_HID_1d742 = 0x1d742, - BNXT_ULP_ACT_HID_21742 = 0x21742, - BNXT_ULP_ACT_HID_25742 = 0x25742, - BNXT_ULP_ACT_HID_1d7c2 = 0x1d7c2, - BNXT_ULP_ACT_HID_217c2 = 0x217c2, - BNXT_ULP_ACT_HID_257c2 = 0x257c2, - BNXT_ULP_ACT_HID_21fc2 = 0x21fc2, - BNXT_ULP_ACT_HID_3b842 = 0x3b842, - BNXT_ULP_ACT_HID_2a842 = 0x2a842, - BNXT_ULP_ACT_HID_1fb62 = 0x1fb62, - BNXT_ULP_ACT_HID_393e2 = 0x393e2, - BNXT_ULP_ACT_HID_330c2 = 0x330c2, - BNXT_ULP_ACT_HID_3e82 = 0x3e82, - BNXT_ULP_ACT_HID_25fc2 = 0x25fc2, - BNXT_ULP_ACT_HID_1a62 = 0x1a62, - BNXT_ULP_ACT_HID_2e842 = 0x2e842, - BNXT_ULP_ACT_HID_23b62 = 0x23b62, - BNXT_ULP_ACT_HID_3d3e2 = 0x3d3e2, - BNXT_ULP_ACT_HID_370c2 = 0x370c2, - BNXT_ULP_ACT_HID_7e82 = 0x7e82, - BNXT_ULP_ACT_HID_29fc2 = 0x29fc2, - BNXT_ULP_ACT_HID_5a62 = 0x5a62, - BNXT_ULP_ACT_HID_32842 = 0x32842, - BNXT_ULP_ACT_HID_27b62 = 0x27b62, - BNXT_ULP_ACT_HID_3602 = 0x3602, - BNXT_ULP_ACT_HID_3b0c2 = 0x3b0c2, - BNXT_ULP_ACT_HID_be82 = 0xbe82, - BNXT_ULP_ACT_HID_2dfc2 = 0x2dfc2, - BNXT_ULP_ACT_HID_9a62 = 0x9a62, - BNXT_ULP_ACT_HID_36842 = 0x36842, - BNXT_ULP_ACT_HID_2bb62 = 0x2bb62, - BNXT_ULP_ACT_HID_7602 = 0x7602, - BNXT_ULP_ACT_HID_12e2 = 0x12e2, - BNXT_ULP_ACT_HID_fe82 = 0xfe82, - BNXT_ULP_ACT_HID_22042 = 0x22042, - BNXT_ULP_ACT_HID_3b8c2 = 0x3b8c2, - BNXT_ULP_ACT_HID_2a8c2 = 0x2a8c2, - BNXT_ULP_ACT_HID_1fbe2 = 0x1fbe2, - BNXT_ULP_ACT_HID_39462 = 0x39462, - BNXT_ULP_ACT_HID_33142 = 0x33142, - BNXT_ULP_ACT_HID_3f02 = 0x3f02, - BNXT_ULP_ACT_HID_26042 = 0x26042, - BNXT_ULP_ACT_HID_1ae2 = 0x1ae2, - BNXT_ULP_ACT_HID_2e8c2 = 0x2e8c2, - BNXT_ULP_ACT_HID_23be2 = 0x23be2, - BNXT_ULP_ACT_HID_3d462 = 0x3d462, - BNXT_ULP_ACT_HID_37142 = 0x37142, - BNXT_ULP_ACT_HID_7f02 = 0x7f02, - BNXT_ULP_ACT_HID_2a042 = 0x2a042, - BNXT_ULP_ACT_HID_5ae2 = 0x5ae2, - BNXT_ULP_ACT_HID_328c2 = 0x328c2, - BNXT_ULP_ACT_HID_27be2 = 0x27be2, - BNXT_ULP_ACT_HID_3682 = 0x3682, - BNXT_ULP_ACT_HID_3b142 = 0x3b142, - BNXT_ULP_ACT_HID_bf02 = 0xbf02, - BNXT_ULP_ACT_HID_2e042 = 0x2e042, - BNXT_ULP_ACT_HID_9ae2 = 0x9ae2, - BNXT_ULP_ACT_HID_368c2 = 0x368c2, - BNXT_ULP_ACT_HID_2bbe2 = 0x2bbe2, - BNXT_ULP_ACT_HID_7682 = 0x7682, - BNXT_ULP_ACT_HID_1362 = 0x1362, - BNXT_ULP_ACT_HID_ff02 = 0xff02, - BNXT_ULP_ACT_HID_2ec02 = 0x2ec02, - BNXT_ULP_ACT_HID_a6a2 = 0xa6a2, - BNXT_ULP_ACT_HID_37482 = 0x37482, - BNXT_ULP_ACT_HID_2c7a2 = 0x2c7a2, - BNXT_ULP_ACT_HID_8242 = 0x8242, - BNXT_ULP_ACT_HID_10ac2 = 0x10ac2, - BNXT_ULP_ACT_HID_2ec82 = 0x2ec82, - BNXT_ULP_ACT_HID_a722 = 0xa722, - BNXT_ULP_ACT_HID_37502 = 0x37502, - BNXT_ULP_ACT_HID_2c822 = 0x2c822, - BNXT_ULP_ACT_HID_82c2 = 0x82c2, - BNXT_ULP_ACT_HID_10b42 = 0x10b42, - BNXT_ULP_ACT_HID_32c02 = 0x32c02, - BNXT_ULP_ACT_HID_e6a2 = 0xe6a2, - BNXT_ULP_ACT_HID_3b482 = 0x3b482, - BNXT_ULP_ACT_HID_307a2 = 0x307a2, - BNXT_ULP_ACT_HID_c242 = 0xc242, - BNXT_ULP_ACT_HID_14ac2 = 0x14ac2, - BNXT_ULP_ACT_HID_32c82 = 0x32c82, - BNXT_ULP_ACT_HID_e722 = 0xe722, - BNXT_ULP_ACT_HID_3b502 = 0x3b502, - BNXT_ULP_ACT_HID_30822 = 0x30822, - BNXT_ULP_ACT_HID_c2c2 = 0xc2c2, - BNXT_ULP_ACT_HID_14b42 = 0x14b42, - BNXT_ULP_ACT_HID_36c02 = 0x36c02, - BNXT_ULP_ACT_HID_126a2 = 0x126a2, - BNXT_ULP_ACT_HID_16a2 = 0x16a2, - BNXT_ULP_ACT_HID_347a2 = 0x347a2, - BNXT_ULP_ACT_HID_10242 = 0x10242, - BNXT_ULP_ACT_HID_18ac2 = 0x18ac2, - BNXT_ULP_ACT_HID_36c82 = 0x36c82, - BNXT_ULP_ACT_HID_12722 = 0x12722, - BNXT_ULP_ACT_HID_1722 = 0x1722, - BNXT_ULP_ACT_HID_34822 = 0x34822, - BNXT_ULP_ACT_HID_102c2 = 0x102c2, - BNXT_ULP_ACT_HID_18b42 = 0x18b42, - BNXT_ULP_ACT_HID_3ac02 = 0x3ac02, - BNXT_ULP_ACT_HID_166a2 = 0x166a2, - BNXT_ULP_ACT_HID_56a2 = 0x56a2, - BNXT_ULP_ACT_HID_387a2 = 0x387a2, - BNXT_ULP_ACT_HID_14242 = 0x14242, - BNXT_ULP_ACT_HID_1cac2 = 0x1cac2, - BNXT_ULP_ACT_HID_3ac82 = 0x3ac82, - BNXT_ULP_ACT_HID_16722 = 0x16722, - BNXT_ULP_ACT_HID_5722 = 0x5722, - BNXT_ULP_ACT_HID_38822 = 0x38822, - BNXT_ULP_ACT_HID_142c2 = 0x142c2, - BNXT_ULP_ACT_HID_1cb42 = 0x1cb42, - BNXT_ULP_ACT_HID_12520 = 0x12520, - BNXT_ULP_ACT_HID_2bda0 = 0x2bda0, - BNXT_ULP_ACT_HID_1ada0 = 0x1ada0, - BNXT_ULP_ACT_HID_120c0 = 0x120c0, - BNXT_ULP_ACT_HID_2b940 = 0x2b940, - BNXT_ULP_ACT_HID_23620 = 0x23620, - BNXT_ULP_ACT_HID_321c0 = 0x321c0, - BNXT_ULP_ACT_HID_125a0 = 0x125a0, - BNXT_ULP_ACT_HID_2be20 = 0x2be20, - BNXT_ULP_ACT_HID_1ae20 = 0x1ae20, - BNXT_ULP_ACT_HID_12140 = 0x12140, - BNXT_ULP_ACT_HID_2b9c0 = 0x2b9c0, - BNXT_ULP_ACT_HID_236a0 = 0x236a0, - BNXT_ULP_ACT_HID_32240 = 0x32240, - BNXT_ULP_ACT_HID_1f160 = 0x1f160, - BNXT_ULP_ACT_HID_3a9e0 = 0x3a9e0, - BNXT_ULP_ACT_HID_279e0 = 0x279e0, - BNXT_ULP_ACT_HID_1ed00 = 0x1ed00, - BNXT_ULP_ACT_HID_36580 = 0x36580, - BNXT_ULP_ACT_HID_3020 = 0x3020, - BNXT_ULP_ACT_HID_1f1e0 = 0x1f1e0, - BNXT_ULP_ACT_HID_3aa60 = 0x3aa60, - BNXT_ULP_ACT_HID_27a60 = 0x27a60, - BNXT_ULP_ACT_HID_1ed80 = 0x1ed80, - BNXT_ULP_ACT_HID_36600 = 0x36600, - BNXT_ULP_ACT_HID_30a0 = 0x30a0, - BNXT_ULP_ACT_HID_0100 = 0x0100, - BNXT_ULP_ACT_HID_0180 = 0x0180, - BNXT_ULP_ACT_HID_32e84 = 0x32e84, - BNXT_ULP_ACT_HID_32f04 = 0x32f04, - BNXT_ULP_ACT_HID_19842 = 0x19842, - BNXT_ULP_ACT_HID_198c2 = 0x198c2, - BNXT_ULP_ACT_HID_e7e6 = 0xe7e6, - BNXT_ULP_ACT_HID_e866 = 0xe866, - BNXT_ULP_ACT_HID_a3e0 = 0xa3e0, - BNXT_ULP_ACT_HID_240e0 = 0x240e0, - BNXT_ULP_ACT_HID_322c8 = 0x322c8, - BNXT_ULP_ACT_HID_e228 = 0xe228, - BNXT_ULP_ACT_HID_36130 = 0x36130, - BNXT_ULP_ACT_HID_2e840 = 0x2e840, - BNXT_ULP_ACT_HID_2e880 = 0x2e880, - BNXT_ULP_ACT_HID_2e900 = 0x2e900, - BNXT_ULP_ACT_HID_170c0 = 0x170c0, - BNXT_ULP_ACT_HID_14ea0 = 0x14ea0, - BNXT_ULP_ACT_HID_3b480 = 0x3b480, - BNXT_ULP_ACT_HID_23d00 = 0x23d00, - BNXT_ULP_ACT_HID_21ae0 = 0x21ae0, - BNXT_ULP_ACT_HID_2e8c0 = 0x2e8c0, - BNXT_ULP_ACT_HID_17140 = 0x17140, - BNXT_ULP_ACT_HID_14f20 = 0x14f20, - BNXT_ULP_ACT_HID_3b500 = 0x3b500, - BNXT_ULP_ACT_HID_23d80 = 0x23d80, - BNXT_ULP_ACT_HID_21b60 = 0x21b60, - BNXT_ULP_ACT_HID_a1a2 = 0xa1a2, - BNXT_ULP_ACT_HID_a1e2 = 0xa1e2, - BNXT_ULP_ACT_HID_a262 = 0xa262, - BNXT_ULP_ACT_HID_30802 = 0x30802, - BNXT_ULP_ACT_HID_2e5e2 = 0x2e5e2, - BNXT_ULP_ACT_HID_16de2 = 0x16de2, - BNXT_ULP_ACT_HID_3d442 = 0x3d442, - BNXT_ULP_ACT_HID_3b222 = 0x3b222, - BNXT_ULP_ACT_HID_a222 = 0xa222, - BNXT_ULP_ACT_HID_30882 = 0x30882, - BNXT_ULP_ACT_HID_2e662 = 0x2e662, - BNXT_ULP_ACT_HID_16e62 = 0x16e62, - BNXT_ULP_ACT_HID_3d4c2 = 0x3d4c2, - BNXT_ULP_ACT_HID_3b2a2 = 0x3b2a2, - BNXT_ULP_ACT_HID_3a4e0 = 0x3a4e0, - BNXT_ULP_ACT_HID_3a520 = 0x3a520, - BNXT_ULP_ACT_HID_3a5a0 = 0x3a5a0, - BNXT_ULP_ACT_HID_22d60 = 0x22d60, - BNXT_ULP_ACT_HID_1eb40 = 0x1eb40, - BNXT_ULP_ACT_HID_7340 = 0x7340, - BNXT_ULP_ACT_HID_2f9a0 = 0x2f9a0, - BNXT_ULP_ACT_HID_2b780 = 0x2b780, - BNXT_ULP_ACT_HID_3a560 = 0x3a560, - BNXT_ULP_ACT_HID_22de0 = 0x22de0, - BNXT_ULP_ACT_HID_1ebc0 = 0x1ebc0, - BNXT_ULP_ACT_HID_73c0 = 0x73c0, - BNXT_ULP_ACT_HID_2fa20 = 0x2fa20, - BNXT_ULP_ACT_HID_2b800 = 0x2b800, - BNXT_ULP_ACT_HID_32840 = 0x32840, - BNXT_ULP_ACT_HID_36840 = 0x36840, - BNXT_ULP_ACT_HID_3a840 = 0x3a840, - BNXT_ULP_ACT_HID_328c0 = 0x328c0, - BNXT_ULP_ACT_HID_368c0 = 0x368c0, - BNXT_ULP_ACT_HID_3a8c0 = 0x3a8c0, - BNXT_ULP_ACT_HID_370c0 = 0x370c0, - BNXT_ULP_ACT_HID_12b60 = 0x12b60, - BNXT_ULP_ACT_HID_1b60 = 0x1b60, - BNXT_ULP_ACT_HID_34c60 = 0x34c60, - BNXT_ULP_ACT_HID_10700 = 0x10700, - BNXT_ULP_ACT_HID_18f80 = 0x18f80, - BNXT_ULP_ACT_HID_3b0c0 = 0x3b0c0, - BNXT_ULP_ACT_HID_16b60 = 0x16b60, - BNXT_ULP_ACT_HID_5b60 = 0x5b60, - BNXT_ULP_ACT_HID_38c60 = 0x38c60, - BNXT_ULP_ACT_HID_14700 = 0x14700, - BNXT_ULP_ACT_HID_1cf80 = 0x1cf80, - BNXT_ULP_ACT_HID_12e0 = 0x12e0, - BNXT_ULP_ACT_HID_1ab60 = 0x1ab60, - BNXT_ULP_ACT_HID_9b60 = 0x9b60, - BNXT_ULP_ACT_HID_3cc60 = 0x3cc60, - BNXT_ULP_ACT_HID_18700 = 0x18700, - BNXT_ULP_ACT_HID_20f80 = 0x20f80, - BNXT_ULP_ACT_HID_52e0 = 0x52e0, - BNXT_ULP_ACT_HID_1eb60 = 0x1eb60, - BNXT_ULP_ACT_HID_db60 = 0xdb60, - BNXT_ULP_ACT_HID_2e80 = 0x2e80, - BNXT_ULP_ACT_HID_1c700 = 0x1c700, - BNXT_ULP_ACT_HID_24f80 = 0x24f80, - BNXT_ULP_ACT_HID_37140 = 0x37140, - BNXT_ULP_ACT_HID_12be0 = 0x12be0, - BNXT_ULP_ACT_HID_1be0 = 0x1be0, - BNXT_ULP_ACT_HID_34ce0 = 0x34ce0, - BNXT_ULP_ACT_HID_10780 = 0x10780, - BNXT_ULP_ACT_HID_19000 = 0x19000, - BNXT_ULP_ACT_HID_3b140 = 0x3b140, - BNXT_ULP_ACT_HID_16be0 = 0x16be0, - BNXT_ULP_ACT_HID_5be0 = 0x5be0, - BNXT_ULP_ACT_HID_38ce0 = 0x38ce0, - BNXT_ULP_ACT_HID_14780 = 0x14780, - BNXT_ULP_ACT_HID_1d000 = 0x1d000, - BNXT_ULP_ACT_HID_1360 = 0x1360, - BNXT_ULP_ACT_HID_1abe0 = 0x1abe0, - BNXT_ULP_ACT_HID_9be0 = 0x9be0, - BNXT_ULP_ACT_HID_3cce0 = 0x3cce0, - BNXT_ULP_ACT_HID_18780 = 0x18780, - BNXT_ULP_ACT_HID_21000 = 0x21000, - BNXT_ULP_ACT_HID_5360 = 0x5360, - BNXT_ULP_ACT_HID_1ebe0 = 0x1ebe0, - BNXT_ULP_ACT_HID_dbe0 = 0xdbe0, - BNXT_ULP_ACT_HID_2f00 = 0x2f00, - BNXT_ULP_ACT_HID_1c780 = 0x1c780, - BNXT_ULP_ACT_HID_25000 = 0x25000, - BNXT_ULP_ACT_HID_5f20 = 0x5f20, - BNXT_ULP_ACT_HID_1f7a0 = 0x1f7a0, - BNXT_ULP_ACT_HID_e7a0 = 0xe7a0, - BNXT_ULP_ACT_HID_3ac0 = 0x3ac0, - BNXT_ULP_ACT_HID_1d340 = 0x1d340, - BNXT_ULP_ACT_HID_25bc0 = 0x25bc0, - BNXT_ULP_ACT_HID_5fa0 = 0x5fa0, - BNXT_ULP_ACT_HID_1f820 = 0x1f820, - BNXT_ULP_ACT_HID_e820 = 0xe820, - BNXT_ULP_ACT_HID_3b40 = 0x3b40, - BNXT_ULP_ACT_HID_1d3c0 = 0x1d3c0, - BNXT_ULP_ACT_HID_25c40 = 0x25c40, - BNXT_ULP_ACT_HID_237a0 = 0x237a0, - BNXT_ULP_ACT_HID_127a0 = 0x127a0, - BNXT_ULP_ACT_HID_7ac0 = 0x7ac0, - BNXT_ULP_ACT_HID_9f20 = 0x9f20, - BNXT_ULP_ACT_HID_21340 = 0x21340, - BNXT_ULP_ACT_HID_29bc0 = 0x29bc0, - BNXT_ULP_ACT_HID_9fa0 = 0x9fa0, - BNXT_ULP_ACT_HID_23820 = 0x23820, - BNXT_ULP_ACT_HID_12820 = 0x12820, - BNXT_ULP_ACT_HID_7b40 = 0x7b40, - BNXT_ULP_ACT_HID_213c0 = 0x213c0, - BNXT_ULP_ACT_HID_29c40 = 0x29c40, - BNXT_ULP_ACT_HID_df20 = 0xdf20, - BNXT_ULP_ACT_HID_277a0 = 0x277a0, - BNXT_ULP_ACT_HID_167a0 = 0x167a0, - BNXT_ULP_ACT_HID_bac0 = 0xbac0, - BNXT_ULP_ACT_HID_25340 = 0x25340, - BNXT_ULP_ACT_HID_2dbc0 = 0x2dbc0, - BNXT_ULP_ACT_HID_dfa0 = 0xdfa0, - BNXT_ULP_ACT_HID_27820 = 0x27820, - BNXT_ULP_ACT_HID_16820 = 0x16820, - BNXT_ULP_ACT_HID_bb40 = 0xbb40, - BNXT_ULP_ACT_HID_253c0 = 0x253c0, - BNXT_ULP_ACT_HID_2dc40 = 0x2dc40, - BNXT_ULP_ACT_HID_11f20 = 0x11f20, - BNXT_ULP_ACT_HID_2b7a0 = 0x2b7a0, - BNXT_ULP_ACT_HID_1a7a0 = 0x1a7a0, - BNXT_ULP_ACT_HID_fac0 = 0xfac0, - BNXT_ULP_ACT_HID_29340 = 0x29340, - BNXT_ULP_ACT_HID_31bc0 = 0x31bc0, - BNXT_ULP_ACT_HID_11fa0 = 0x11fa0, - BNXT_ULP_ACT_HID_2b820 = 0x2b820, - BNXT_ULP_ACT_HID_1a820 = 0x1a820, - BNXT_ULP_ACT_HID_fb40 = 0xfb40, - BNXT_ULP_ACT_HID_293c0 = 0x293c0, - BNXT_ULP_ACT_HID_31c40 = 0x31c40, - BNXT_ULP_ACT_HID_e1a2 = 0xe1a2, - BNXT_ULP_ACT_HID_121a2 = 0x121a2, - BNXT_ULP_ACT_HID_161a2 = 0x161a2, - BNXT_ULP_ACT_HID_e222 = 0xe222, - BNXT_ULP_ACT_HID_12222 = 0x12222, - BNXT_ULP_ACT_HID_16222 = 0x16222, - BNXT_ULP_ACT_HID_12a22 = 0x12a22, - BNXT_ULP_ACT_HID_2c2a2 = 0x2c2a2, - BNXT_ULP_ACT_HID_1b2a2 = 0x1b2a2, - BNXT_ULP_ACT_HID_105c2 = 0x105c2, - BNXT_ULP_ACT_HID_29e42 = 0x29e42, - BNXT_ULP_ACT_HID_326c2 = 0x326c2, - BNXT_ULP_ACT_HID_16a22 = 0x16a22, - BNXT_ULP_ACT_HID_302a2 = 0x302a2, - BNXT_ULP_ACT_HID_1f2a2 = 0x1f2a2, - BNXT_ULP_ACT_HID_145c2 = 0x145c2, - BNXT_ULP_ACT_HID_2de42 = 0x2de42, - BNXT_ULP_ACT_HID_366c2 = 0x366c2, - BNXT_ULP_ACT_HID_1aa22 = 0x1aa22, - BNXT_ULP_ACT_HID_342a2 = 0x342a2, - BNXT_ULP_ACT_HID_232a2 = 0x232a2, - BNXT_ULP_ACT_HID_185c2 = 0x185c2, - BNXT_ULP_ACT_HID_31e42 = 0x31e42, - BNXT_ULP_ACT_HID_3a6c2 = 0x3a6c2, - BNXT_ULP_ACT_HID_1ea22 = 0x1ea22, - BNXT_ULP_ACT_HID_382a2 = 0x382a2, - BNXT_ULP_ACT_HID_272a2 = 0x272a2, - BNXT_ULP_ACT_HID_1c5c2 = 0x1c5c2, - BNXT_ULP_ACT_HID_35e42 = 0x35e42, - BNXT_ULP_ACT_HID_08e2 = 0x08e2, - BNXT_ULP_ACT_HID_12aa2 = 0x12aa2, - BNXT_ULP_ACT_HID_2c322 = 0x2c322, - BNXT_ULP_ACT_HID_1b322 = 0x1b322, - BNXT_ULP_ACT_HID_10642 = 0x10642, - BNXT_ULP_ACT_HID_29ec2 = 0x29ec2, - BNXT_ULP_ACT_HID_32742 = 0x32742, - BNXT_ULP_ACT_HID_16aa2 = 0x16aa2, - BNXT_ULP_ACT_HID_30322 = 0x30322, - BNXT_ULP_ACT_HID_1f322 = 0x1f322, - BNXT_ULP_ACT_HID_14642 = 0x14642, - BNXT_ULP_ACT_HID_2dec2 = 0x2dec2, - BNXT_ULP_ACT_HID_36742 = 0x36742, - BNXT_ULP_ACT_HID_1aaa2 = 0x1aaa2, - BNXT_ULP_ACT_HID_34322 = 0x34322, - BNXT_ULP_ACT_HID_23322 = 0x23322, - BNXT_ULP_ACT_HID_18642 = 0x18642, - BNXT_ULP_ACT_HID_31ec2 = 0x31ec2, - BNXT_ULP_ACT_HID_3a742 = 0x3a742, - BNXT_ULP_ACT_HID_1eaa2 = 0x1eaa2, - BNXT_ULP_ACT_HID_38322 = 0x38322, - BNXT_ULP_ACT_HID_27322 = 0x27322, - BNXT_ULP_ACT_HID_1c642 = 0x1c642, - BNXT_ULP_ACT_HID_35ec2 = 0x35ec2, - BNXT_ULP_ACT_HID_0962 = 0x0962, - BNXT_ULP_ACT_HID_1f662 = 0x1f662, - BNXT_ULP_ACT_HID_38ee2 = 0x38ee2, - BNXT_ULP_ACT_HID_27ee2 = 0x27ee2, - BNXT_ULP_ACT_HID_1d202 = 0x1d202, - BNXT_ULP_ACT_HID_36a82 = 0x36a82, - BNXT_ULP_ACT_HID_1522 = 0x1522, - BNXT_ULP_ACT_HID_1f6e2 = 0x1f6e2, - BNXT_ULP_ACT_HID_38f62 = 0x38f62, - BNXT_ULP_ACT_HID_27f62 = 0x27f62, - BNXT_ULP_ACT_HID_1d282 = 0x1d282, - BNXT_ULP_ACT_HID_36b02 = 0x36b02, - BNXT_ULP_ACT_HID_15a2 = 0x15a2, - BNXT_ULP_ACT_HID_3cee2 = 0x3cee2, - BNXT_ULP_ACT_HID_2bee2 = 0x2bee2, - BNXT_ULP_ACT_HID_21202 = 0x21202, - BNXT_ULP_ACT_HID_23662 = 0x23662, - BNXT_ULP_ACT_HID_3aa82 = 0x3aa82, - BNXT_ULP_ACT_HID_5522 = 0x5522, - BNXT_ULP_ACT_HID_236e2 = 0x236e2, - BNXT_ULP_ACT_HID_3cf62 = 0x3cf62, - BNXT_ULP_ACT_HID_2bf62 = 0x2bf62, - BNXT_ULP_ACT_HID_21282 = 0x21282, - BNXT_ULP_ACT_HID_3ab02 = 0x3ab02, - BNXT_ULP_ACT_HID_55a2 = 0x55a2, - BNXT_ULP_ACT_HID_27662 = 0x27662, - BNXT_ULP_ACT_HID_3102 = 0x3102, - BNXT_ULP_ACT_HID_2fee2 = 0x2fee2, - BNXT_ULP_ACT_HID_25202 = 0x25202, - BNXT_ULP_ACT_HID_0ca2 = 0x0ca2, - BNXT_ULP_ACT_HID_9522 = 0x9522, - BNXT_ULP_ACT_HID_276e2 = 0x276e2, - BNXT_ULP_ACT_HID_3182 = 0x3182, - BNXT_ULP_ACT_HID_2ff62 = 0x2ff62, - BNXT_ULP_ACT_HID_25282 = 0x25282, - BNXT_ULP_ACT_HID_0d22 = 0x0d22, - BNXT_ULP_ACT_HID_95a2 = 0x95a2, - BNXT_ULP_ACT_HID_2b662 = 0x2b662, - BNXT_ULP_ACT_HID_7102 = 0x7102, - BNXT_ULP_ACT_HID_33ee2 = 0x33ee2, - BNXT_ULP_ACT_HID_29202 = 0x29202, - BNXT_ULP_ACT_HID_4ca2 = 0x4ca2, - BNXT_ULP_ACT_HID_d522 = 0xd522, - BNXT_ULP_ACT_HID_2b6e2 = 0x2b6e2, - BNXT_ULP_ACT_HID_7182 = 0x7182, - BNXT_ULP_ACT_HID_33f62 = 0x33f62, - BNXT_ULP_ACT_HID_29282 = 0x29282, - BNXT_ULP_ACT_HID_4d22 = 0x4d22, - BNXT_ULP_ACT_HID_d5a2 = 0xd5a2, - BNXT_ULP_ACT_HID_3e4e0 = 0x3e4e0, - BNXT_ULP_ACT_HID_2700 = 0x2700, - BNXT_ULP_ACT_HID_6700 = 0x6700, - BNXT_ULP_ACT_HID_3e560 = 0x3e560, - BNXT_ULP_ACT_HID_2780 = 0x2780, - BNXT_ULP_ACT_HID_6780 = 0x6780, - BNXT_ULP_ACT_HID_2f80 = 0x2f80, - BNXT_ULP_ACT_HID_1e800 = 0x1e800, - BNXT_ULP_ACT_HID_b800 = 0xb800, - BNXT_ULP_ACT_HID_2b20 = 0x2b20, - BNXT_ULP_ACT_HID_1a3a0 = 0x1a3a0, - BNXT_ULP_ACT_HID_22c20 = 0x22c20, - BNXT_ULP_ACT_HID_6f80 = 0x6f80, - BNXT_ULP_ACT_HID_22800 = 0x22800, - BNXT_ULP_ACT_HID_f800 = 0xf800, - BNXT_ULP_ACT_HID_6b20 = 0x6b20, - BNXT_ULP_ACT_HID_1e3a0 = 0x1e3a0, - BNXT_ULP_ACT_HID_26c20 = 0x26c20, - BNXT_ULP_ACT_HID_af80 = 0xaf80, - BNXT_ULP_ACT_HID_26800 = 0x26800, - BNXT_ULP_ACT_HID_13800 = 0x13800, - BNXT_ULP_ACT_HID_ab20 = 0xab20, - BNXT_ULP_ACT_HID_223a0 = 0x223a0, - BNXT_ULP_ACT_HID_2ac20 = 0x2ac20, - BNXT_ULP_ACT_HID_ef80 = 0xef80, - BNXT_ULP_ACT_HID_2a800 = 0x2a800, - BNXT_ULP_ACT_HID_17800 = 0x17800, - BNXT_ULP_ACT_HID_eb20 = 0xeb20, - BNXT_ULP_ACT_HID_263a0 = 0x263a0, - BNXT_ULP_ACT_HID_2ec20 = 0x2ec20, - BNXT_ULP_ACT_HID_3000 = 0x3000, - BNXT_ULP_ACT_HID_1e880 = 0x1e880, - BNXT_ULP_ACT_HID_b880 = 0xb880, - BNXT_ULP_ACT_HID_2ba0 = 0x2ba0, - BNXT_ULP_ACT_HID_1a420 = 0x1a420, - BNXT_ULP_ACT_HID_22ca0 = 0x22ca0, - BNXT_ULP_ACT_HID_7000 = 0x7000, - BNXT_ULP_ACT_HID_22880 = 0x22880, - BNXT_ULP_ACT_HID_f880 = 0xf880, - BNXT_ULP_ACT_HID_6ba0 = 0x6ba0, - BNXT_ULP_ACT_HID_1e420 = 0x1e420, - BNXT_ULP_ACT_HID_26ca0 = 0x26ca0, - BNXT_ULP_ACT_HID_b000 = 0xb000, - BNXT_ULP_ACT_HID_26880 = 0x26880, - BNXT_ULP_ACT_HID_13880 = 0x13880, - BNXT_ULP_ACT_HID_aba0 = 0xaba0, - BNXT_ULP_ACT_HID_22420 = 0x22420, - BNXT_ULP_ACT_HID_2aca0 = 0x2aca0, - BNXT_ULP_ACT_HID_f000 = 0xf000, - BNXT_ULP_ACT_HID_2a880 = 0x2a880, - BNXT_ULP_ACT_HID_17880 = 0x17880, - BNXT_ULP_ACT_HID_eba0 = 0xeba0, - BNXT_ULP_ACT_HID_26420 = 0x26420, - BNXT_ULP_ACT_HID_2eca0 = 0x2eca0, - BNXT_ULP_ACT_HID_fbc0 = 0xfbc0, - BNXT_ULP_ACT_HID_2b440 = 0x2b440, - BNXT_ULP_ACT_HID_1a440 = 0x1a440, - BNXT_ULP_ACT_HID_f760 = 0xf760, - BNXT_ULP_ACT_HID_26fe0 = 0x26fe0, - BNXT_ULP_ACT_HID_2f860 = 0x2f860, - BNXT_ULP_ACT_HID_fc40 = 0xfc40, - BNXT_ULP_ACT_HID_2b4c0 = 0x2b4c0, - BNXT_ULP_ACT_HID_1a4c0 = 0x1a4c0, - BNXT_ULP_ACT_HID_f7e0 = 0xf7e0, - BNXT_ULP_ACT_HID_27060 = 0x27060, - BNXT_ULP_ACT_HID_2f8e0 = 0x2f8e0, - BNXT_ULP_ACT_HID_2f440 = 0x2f440, - BNXT_ULP_ACT_HID_1e440 = 0x1e440, - BNXT_ULP_ACT_HID_13760 = 0x13760, - BNXT_ULP_ACT_HID_13bc0 = 0x13bc0, - BNXT_ULP_ACT_HID_2afe0 = 0x2afe0, - BNXT_ULP_ACT_HID_33860 = 0x33860, - BNXT_ULP_ACT_HID_13c40 = 0x13c40, - BNXT_ULP_ACT_HID_2f4c0 = 0x2f4c0, - BNXT_ULP_ACT_HID_1e4c0 = 0x1e4c0, - BNXT_ULP_ACT_HID_137e0 = 0x137e0, - BNXT_ULP_ACT_HID_2b060 = 0x2b060, - BNXT_ULP_ACT_HID_338e0 = 0x338e0, - BNXT_ULP_ACT_HID_17bc0 = 0x17bc0, - BNXT_ULP_ACT_HID_33440 = 0x33440, - BNXT_ULP_ACT_HID_22440 = 0x22440, - BNXT_ULP_ACT_HID_17760 = 0x17760, - BNXT_ULP_ACT_HID_2efe0 = 0x2efe0, - BNXT_ULP_ACT_HID_37860 = 0x37860, - BNXT_ULP_ACT_HID_17c40 = 0x17c40, - BNXT_ULP_ACT_HID_334c0 = 0x334c0, - BNXT_ULP_ACT_HID_224c0 = 0x224c0, - BNXT_ULP_ACT_HID_177e0 = 0x177e0, - BNXT_ULP_ACT_HID_2f060 = 0x2f060, - BNXT_ULP_ACT_HID_378e0 = 0x378e0, - BNXT_ULP_ACT_HID_1bbc0 = 0x1bbc0, - BNXT_ULP_ACT_HID_37440 = 0x37440, - BNXT_ULP_ACT_HID_26440 = 0x26440, - BNXT_ULP_ACT_HID_1b760 = 0x1b760, - BNXT_ULP_ACT_HID_32fe0 = 0x32fe0, - BNXT_ULP_ACT_HID_3b860 = 0x3b860, - BNXT_ULP_ACT_HID_1bc40 = 0x1bc40, - BNXT_ULP_ACT_HID_374c0 = 0x374c0, - BNXT_ULP_ACT_HID_264c0 = 0x264c0, - BNXT_ULP_ACT_HID_1b7e0 = 0x1b7e0, - BNXT_ULP_ACT_HID_33060 = 0x33060, - BNXT_ULP_ACT_HID_3b8e0 = 0x3b8e0, - BNXT_ULP_ACT_HID_18e80 = 0x18e80, - BNXT_ULP_ACT_HID_18f00 = 0x18f00, - BNXT_ULP_ACT_HID_1ce80 = 0x1ce80, - BNXT_ULP_ACT_HID_1cf00 = 0x1cf00, - BNXT_ULP_ACT_HID_20e80 = 0x20e80, - BNXT_ULP_ACT_HID_20f00 = 0x20f00, - BNXT_ULP_ACT_HID_24e80 = 0x24e80, - BNXT_ULP_ACT_HID_24f00 = 0x24f00, - BNXT_ULP_ACT_HID_325c2 = 0x325c2, - BNXT_ULP_ACT_HID_32642 = 0x32642, - BNXT_ULP_ACT_HID_365c2 = 0x365c2, - BNXT_ULP_ACT_HID_36642 = 0x36642, - BNXT_ULP_ACT_HID_3a5c2 = 0x3a5c2, - BNXT_ULP_ACT_HID_3a642 = 0x3a642, - BNXT_ULP_ACT_HID_07e2 = 0x07e2, - BNXT_ULP_ACT_HID_0862 = 0x0862, - BNXT_ULP_ACT_HID_22b20 = 0x22b20, - BNXT_ULP_ACT_HID_22ba0 = 0x22ba0, - BNXT_ULP_ACT_HID_26b20 = 0x26b20, - BNXT_ULP_ACT_HID_26ba0 = 0x26ba0, - BNXT_ULP_ACT_HID_2ab20 = 0x2ab20, - BNXT_ULP_ACT_HID_2aba0 = 0x2aba0, - BNXT_ULP_ACT_HID_2eb20 = 0x2eb20, - BNXT_ULP_ACT_HID_2eba0 = 0x2eba0, - BNXT_ULP_ACT_HID_199e0 = 0x199e0, - BNXT_ULP_ACT_HID_19960 = 0x19960, - BNXT_ULP_ACT_HID_33122 = 0x33122, - BNXT_ULP_ACT_HID_331a2 = 0x331a2, - BNXT_ULP_ACT_HID_23580 = 0x23580, - BNXT_ULP_ACT_HID_23700 = 0x23700, - BNXT_ULP_ACT_HID_db61 = 0xdb61, - BNXT_ULP_ACT_HID_dbe1 = 0xdbe1, - BNXT_ULP_ACT_HID_320ca = 0x320ca +enum ulp_thor2_sym { + ULP_THOR2_SYM_METADATA_OP_NORMAL = 0, + ULP_THOR2_SYM_METADATA_OP_L2_HASH = 1, + ULP_THOR2_SYM_METADATA_OP_L4_HASH = 2, + ULP_THOR2_SYM_FWD_OP_BYPASS_CFA = 0, + ULP_THOR2_SYM_FWD_OP_BYPASS_CFA_ROCE = 1, + ULP_THOR2_SYM_FWD_OP_BYPASS_LKUP = 2, + ULP_THOR2_SYM_FWD_OP_NORMAL_FLOW = 3, + ULP_THOR2_SYM_FWD_OP_DROP = 4, + ULP_THOR2_SYM_CTXT_OPCODE_BYPASS_CFA = 0, + ULP_THOR2_SYM_CTXT_OPCODE_BYPASS_LKUP = 1, + ULP_THOR2_SYM_CTXT_OPCODE_META_UPDATE = 0, + ULP_THOR2_SYM_CTXT_OPCODE_NORMAL_FLOW = 2, + ULP_THOR2_SYM_CTXT_OPCODE_DROP = 3, + ULP_THOR2_SYM_L2_CTXT_PRI_CATCHALL = 5, + ULP_THOR2_SYM_L2_CTXT_PRI_MC_BC = 40, + ULP_THOR2_SYM_L2_CTXT_PRI_PORT = 70, + ULP_THOR2_SYM_L2_CTXT_PRI_APP = 140, + ULP_THOR2_SYM_PROF_TCAM_PRI_CATCHALL = 1, + ULP_THOR2_SYM_PROF_TCAM_PRI_APP = 10, + ULP_THOR2_SYM_PKT_TYPE_IGNORE = 0, + ULP_THOR2_SYM_PKT_TYPE_L2 = 0, + ULP_THOR2_SYM_PKT_TYPE_0_IGNORE = 0, + ULP_THOR2_SYM_PKT_TYPE_0_L2 = 0, + ULP_THOR2_SYM_PKT_TYPE_1_IGNORE = 0, + ULP_THOR2_SYM_PKT_TYPE_1_L2 = 0, + ULP_THOR2_SYM_RECYCLE_CNT_IGNORE = 0, + ULP_THOR2_SYM_RECYCLE_CNT_ZERO = 0, + ULP_THOR2_SYM_RECYCLE_CNT_ONE = 1, + ULP_THOR2_SYM_RECYCLE_CNT_TWO = 2, + ULP_THOR2_SYM_RECYCLE_CNT_THREE = 3, + ULP_THOR2_SYM_AGG_ERROR_IGNORE = 0, + ULP_THOR2_SYM_AGG_ERROR_NO = 0, + ULP_THOR2_SYM_AGG_ERROR_YES = 1, + ULP_THOR2_SYM_RESERVED_IGNORE = 0, + ULP_THOR2_SYM_HREC_NEXT_IGNORE = 0, + ULP_THOR2_SYM_HREC_NEXT_NO = 0, + ULP_THOR2_SYM_HREC_NEXT_YES = 1, + ULP_THOR2_SYM_TL2_HDR_VALID_IGNORE = 0, + ULP_THOR2_SYM_TL2_HDR_VALID_NO = 0, + ULP_THOR2_SYM_TL2_HDR_VALID_YES = 1, + ULP_THOR2_SYM_TL2_HDR_TYPE_IGNORE = 0, + ULP_THOR2_SYM_TL2_HDR_TYPE_DIX = 0, + ULP_THOR2_SYM_TL2_UC_MC_BC_IGNORE = 0, + ULP_THOR2_SYM_TL2_UC_MC_BC_UC = 0, + ULP_THOR2_SYM_TL2_UC_MC_BC_MC = 2, + ULP_THOR2_SYM_TL2_UC_MC_BC_BC = 3, + ULP_THOR2_SYM_TL2_VTAG_PRESENT_IGNORE = 0, + ULP_THOR2_SYM_TL2_VTAG_PRESENT_NO = 0, + ULP_THOR2_SYM_TL2_VTAG_PRESENT_YES = 1, + ULP_THOR2_SYM_TL2_TWO_VTAGS_IGNORE = 0, + ULP_THOR2_SYM_TL2_TWO_VTAGS_NO = 0, + ULP_THOR2_SYM_TL2_TWO_VTAGS_YES = 1, + ULP_THOR2_SYM_TL3_HDR_VALID_IGNORE = 0, + ULP_THOR2_SYM_TL3_HDR_VALID_NO = 0, + ULP_THOR2_SYM_TL3_HDR_VALID_YES = 1, + ULP_THOR2_SYM_TL3_HDR_ERROR_IGNORE = 0, + ULP_THOR2_SYM_TL3_HDR_ERROR_NO = 0, + ULP_THOR2_SYM_TL3_HDR_ERROR_YES = 1, + ULP_THOR2_SYM_TL3_HDR_TYPE_IGNORE = 0, + ULP_THOR2_SYM_TL3_HDR_TYPE_IPV4 = 0, + ULP_THOR2_SYM_TL3_HDR_TYPE_IPV6 = 1, + ULP_THOR2_SYM_TL3_HDR_ISIP_IGNORE = 0, + ULP_THOR2_SYM_TL3_HDR_ISIP_NO = 0, + ULP_THOR2_SYM_TL3_HDR_ISIP_YES = 1, + ULP_THOR2_SYM_TL3_IPV6_CMP_SRC_IGNORE = 0, + ULP_THOR2_SYM_TL3_IPV6_CMP_SRC_NO = 0, + ULP_THOR2_SYM_TL3_IPV6_CMP_SRC_YES = 1, + ULP_THOR2_SYM_TL3_IPV6_CMP_DST_IGNORE = 0, + ULP_THOR2_SYM_TL3_IPV6_CMP_DST_NO = 0, + ULP_THOR2_SYM_TL3_IPV6_CMP_DST_YES = 1, + ULP_THOR2_SYM_TL4_HDR_VALID_IGNORE = 0, + ULP_THOR2_SYM_TL4_HDR_VALID_NO = 0, + ULP_THOR2_SYM_TL4_HDR_VALID_YES = 1, + ULP_THOR2_SYM_TL4_HDR_ERROR_IGNORE = 0, + ULP_THOR2_SYM_TL4_HDR_ERROR_NO = 0, + ULP_THOR2_SYM_TL4_HDR_ERROR_YES = 1, + ULP_THOR2_SYM_TL4_HDR_IS_UDP_TCP_IGNORE = 0, + ULP_THOR2_SYM_TL4_HDR_IS_UDP_TCP_NO = 0, + ULP_THOR2_SYM_TL4_HDR_IS_UDP_TCP_YES = 1, + ULP_THOR2_SYM_TL4_HDR_TYPE_IGNORE = 0, + ULP_THOR2_SYM_TL4_HDR_TYPE_TCP = 0, + ULP_THOR2_SYM_TL4_HDR_TYPE_UDP = 1, + ULP_THOR2_SYM_TUN_HDR_VALID_IGNORE = 0, + ULP_THOR2_SYM_TUN_HDR_VALID_NO = 0, + ULP_THOR2_SYM_TUN_HDR_VALID_YES = 1, + ULP_THOR2_SYM_TUN_HDR_ERROR_IGNORE = 0, + ULP_THOR2_SYM_TUN_HDR_ERROR_NO = 0, + ULP_THOR2_SYM_TUN_HDR_ERROR_YES = 1, + ULP_THOR2_SYM_TUN_HDR_TYPE_IGNORE = 0, + ULP_THOR2_SYM_TUN_HDR_TYPE_VXLAN = 0, + ULP_THOR2_SYM_TUN_HDR_TYPE_VXLAN_GPE = 27, + ULP_THOR2_SYM_TUN_HDR_TYPE_GENEVE = 1, + ULP_THOR2_SYM_TUN_HDR_TYPE_NVGRE = 2, + ULP_THOR2_SYM_TUN_HDR_TYPE_GRE = 3, + ULP_THOR2_SYM_TUN_HDR_TYPE_IPV4 = 4, + ULP_THOR2_SYM_TUN_HDR_TYPE_IPV6 = 5, + ULP_THOR2_SYM_TUN_HDR_TYPE_PPPOE = 6, + ULP_THOR2_SYM_TUN_HDR_TYPE_MPLS = 7, + ULP_THOR2_SYM_TUN_HDR_TYPE_UPAR1 = 8, + ULP_THOR2_SYM_TUN_HDR_TYPE_UPAR2 = 9, + ULP_THOR2_SYM_TUN_HDR_TYPE_UPAR3 = 10, + ULP_THOR2_SYM_TUN_HDR_TYPE_UPAR4 = 11, + ULP_THOR2_SYM_TUN_HDR_TYPE_UPAR5 = 12, + ULP_THOR2_SYM_TUN_HDR_TYPE_UPAR6 = 13, + ULP_THOR2_SYM_TUN_HDR_TYPE_UPAR7 = 14, + ULP_THOR2_SYM_TUN_HDR_TYPE_UPAR8 = 15, + ULP_THOR2_SYM_TUN_HDR_TYPE_ROE = 20, + ULP_THOR2_SYM_TUN_HDR_TYPE_ECPRI = 21, + ULP_THOR2_SYM_TUN_HDR_TYPE_GTP_V1_U = 22, + ULP_THOR2_SYM_TUN_HDR_TYPE_GTP_V2_C = 23, + ULP_THOR2_SYM_TUN_HDR_TYPE_PFCP_SESS = 24, + ULP_THOR2_SYM_TUN_HDR_TYPE_PFCP_NODE = 25, + ULP_THOR2_SYM_TUN_HDR_TYPE_NSH = 26, + ULP_THOR2_SYM_TUN_HDR_TYPE_VXLAN_IP = 28, + ULP_THOR2_SYM_TUN_HDR_TYPE_GRE_TEN = 29, + ULP_THOR2_SYM_TUN_HDR_TYPE_NONE = 31, + ULP_THOR2_SYM_TUN_HDR_TYPE_UPAR_MASK = 32, + ULP_THOR2_SYM_TUN_HDR_TYPE_TID_MASK = 33, + ULP_THOR2_SYM_TUN_HDR_FLAGS_IGNORE = 0, + ULP_THOR2_SYM_L2_HDR_VALID_IGNORE = 0, + ULP_THOR2_SYM_L2_HDR_VALID_NO = 0, + ULP_THOR2_SYM_L2_HDR_VALID_YES = 1, + ULP_THOR2_SYM_L2_HDR_ERROR_IGNORE = 0, + ULP_THOR2_SYM_L2_HDR_ERROR_NO = 0, + ULP_THOR2_SYM_L2_HDR_ERROR_YES = 1, + ULP_THOR2_SYM_L2_HDR_TYPE_IGNORE = 0, + ULP_THOR2_SYM_L2_HDR_TYPE_DIX = 0, + ULP_THOR2_SYM_L2_HDR_TYPE_LLC_SNAP = 1, + ULP_THOR2_SYM_L2_HDR_TYPE_LLC = 2, + ULP_THOR2_SYM_L2_UC_MC_BC_IGNORE = 0, + ULP_THOR2_SYM_L2_UC_MC_BC_UC = 0, + ULP_THOR2_SYM_L2_UC_MC_BC_MC = 2, + ULP_THOR2_SYM_L2_UC_MC_BC_BC = 3, + ULP_THOR2_SYM_L2_VTAG_PRESENT_IGNORE = 0, + ULP_THOR2_SYM_L2_VTAG_PRESENT_NO = 0, + ULP_THOR2_SYM_L2_VTAG_PRESENT_YES = 1, + ULP_THOR2_SYM_L2_TWO_VTAGS_IGNORE = 0, + ULP_THOR2_SYM_L2_TWO_VTAGS_NO = 0, + ULP_THOR2_SYM_L2_TWO_VTAGS_YES = 1, + ULP_THOR2_SYM_L2_CNTX_VLAN_SELECT_INNER = 0, + ULP_THOR2_SYM_L2_CNTX_VLAN_SELECT_TUN = 1, + ULP_THOR2_SYM_L2_CNTX_VLAN_SELECT_O_TUN = 2, + ULP_THOR2_SYM_L2_CNTX_VLAN_SELECT_OM_TUN = 3, + ULP_THOR2_SYM_L2_CNTX_TUN_SELECT_TUN_ID = 0, + ULP_THOR2_SYM_L2_CNTX_TUN_SELECT_TUN_CNTX = 1, + ULP_THOR2_SYM_L2_CNTX_TUN_SELECT_O_TUN_ID = 2, + ULP_THOR2_SYM_L2_CNTX_TUN_SELECT_O_TUN_CNTX = 3, + ULP_THOR2_SYM_L2_CNTX_TUN_SELECT_I_L4_PORTS = 4, + ULP_THOR2_SYM_L2_CNTX_TUN_SELECT_O_L4_PORTS = 5, + ULP_THOR2_SYM_L2_CNTX_TUN_SELECT_OM_TUN_ID = 6, + ULP_THOR2_SYM_L2_CNTX_TUN_SELECT_OM_TUN_CNTX = 7, + ULP_THOR2_SYM_L3_HDR_VALID_IGNORE = 0, + ULP_THOR2_SYM_L3_HDR_VALID_NO = 0, + ULP_THOR2_SYM_L3_HDR_VALID_YES = 1, + ULP_THOR2_SYM_L3_HDR_ERROR_IGNORE = 0, + ULP_THOR2_SYM_L3_HDR_ERROR_NO = 0, + ULP_THOR2_SYM_L3_HDR_ERROR_YES = 1, + ULP_THOR2_SYM_L3_HDR_TYPE_IGNORE = 0, + ULP_THOR2_SYM_L3_HDR_TYPE_IPV4 = 0, + ULP_THOR2_SYM_L3_HDR_TYPE_IPV6 = 1, + ULP_THOR2_SYM_L3_HDR_TYPE_ARP = 2, + ULP_THOR2_SYM_L3_HDR_TYPE_PTP = 3, + ULP_THOR2_SYM_L3_HDR_TYPE_EAPOL = 4, + ULP_THOR2_SYM_L3_HDR_TYPE_ROCE = 5, + ULP_THOR2_SYM_L3_HDR_TYPE_FCOE = 6, + ULP_THOR2_SYM_L3_HDR_TYPE_UPAR1 = 7, + ULP_THOR2_SYM_L3_HDR_TYPE_UPAR2 = 8, + ULP_THOR2_SYM_L3_HDR_ISIP_IGNORE = 0, + ULP_THOR2_SYM_L3_HDR_ISIP_NO = 0, + ULP_THOR2_SYM_L3_HDR_ISIP_YES = 1, + ULP_THOR2_SYM_L3_IPV6_CMP_SRC_IGNORE = 0, + ULP_THOR2_SYM_L3_IPV6_CMP_SRC_NO = 0, + ULP_THOR2_SYM_L3_IPV6_CMP_SRC_YES = 1, + ULP_THOR2_SYM_L3_IPV6_CMP_DST_IGNORE = 0, + ULP_THOR2_SYM_L3_IPV6_CMP_DST_NO = 0, + ULP_THOR2_SYM_L3_IPV6_CMP_DST_YES = 1, + ULP_THOR2_SYM_L4_HDR_VALID_IGNORE = 0, + ULP_THOR2_SYM_L4_HDR_VALID_NO = 0, + ULP_THOR2_SYM_L4_HDR_VALID_YES = 1, + ULP_THOR2_SYM_L4_HDR_ERROR_IGNORE = 0, + ULP_THOR2_SYM_L4_HDR_ERROR_NO = 0, + ULP_THOR2_SYM_L4_HDR_ERROR_YES = 1, + ULP_THOR2_SYM_L4_HDR_TYPE_IGNORE = 0, + ULP_THOR2_SYM_L4_HDR_TYPE_TCP = 0, + ULP_THOR2_SYM_L4_HDR_TYPE_UDP = 1, + ULP_THOR2_SYM_L4_HDR_TYPE_ICMP = 2, + ULP_THOR2_SYM_L4_HDR_TYPE_UPAR1 = 3, + ULP_THOR2_SYM_L4_HDR_TYPE_UPAR2 = 4, + ULP_THOR2_SYM_L4_HDR_TYPE_BTH_V1 = 0, + ULP_THOR2_SYM_L4_HDR_TYPE_IPSEC_AH = 8, + ULP_THOR2_SYM_L4_HDR_TYPE_IPSEC_ESP = 9, + ULP_THOR2_SYM_L4_HDR_IS_UDP_TCP_IGNORE = 0, + ULP_THOR2_SYM_L4_HDR_IS_UDP_TCP_NO = 0, + ULP_THOR2_SYM_L4_HDR_IS_UDP_TCP_YES = 1, + ULP_THOR2_SYM_EM_WM_OPCODE_OP_NORMAL = 0, + ULP_THOR2_SYM_EM_WM_OPCODE_OP_NORMAL_RFS = 1, + ULP_THOR2_SYM_EM_WM_OPCODE_OP_RFS_FAST = 3, + ULP_THOR2_SYM_EM_WM_OPCODE_OP_FAST = 2, + ULP_THOR2_SYM_EM_WM_OPCODE_OP_RFS_ACT = 0, + ULP_THOR2_SYM_EM_WM_OPCODE_OP_CT_MISS_DEF = 4, + ULP_THOR2_SYM_EM_WM_OPCODE_OP_CT_HIT_DEF = 6, + ULP_THOR2_SYM_EM_WM_OPCODE_OP_RECYCLE = 8, + ULP_THOR2_SYM_POP_VLAN_NO = 0, + ULP_THOR2_SYM_POP_VLAN_YES = 1, + ULP_THOR2_SYM_VLAN_DEL_RPT_DISABLED = 0, + ULP_THOR2_SYM_VLAN_DEL_RPT_STRIP_OUTER = 1, + ULP_THOR2_SYM_VLAN_DEL_RPT_STRIP_BOTH = 2, + ULP_THOR2_SYM_VLAN_DEL_RPT_DYN_STRIP = 3, + ULP_THOR2_SYM_DECAP_FUNC_NONE = 0, + ULP_THOR2_SYM_DECAP_FUNC_THRU_TL2 = 3, + ULP_THOR2_SYM_DECAP_FUNC_THRU_TL3 = 8, + ULP_THOR2_SYM_DECAP_FUNC_THRU_TL4 = 9, + ULP_THOR2_SYM_DECAP_FUNC_THRU_TUN = 10, + ULP_THOR2_SYM_DECAP_FUNC_THRU_L2 = 11, + ULP_THOR2_SYM_DECAP_FUNC_THRU_L3 = 12, + ULP_THOR2_SYM_DECAP_FUNC_THRU_L4 = 13, + ULP_THOR2_SYM_ECV_VALID_NO = 0, + ULP_THOR2_SYM_ECV_VALID_YES = 1, + ULP_THOR2_SYM_ECV_CUSTOM_EN_NO = 0, + ULP_THOR2_SYM_ECV_CUSTOM_EN_YES = 1, + ULP_THOR2_SYM_ECV_L2_EN_NO = 0, + ULP_THOR2_SYM_ECV_L2_EN_YES = 1, + ULP_THOR2_SYM_ECV_VTAG_TYPE_NOP = 0, + ULP_THOR2_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI = 1, + ULP_THOR2_SYM_ECV_VTAG_TYPE_ADD_1_IVLAN_PRI = 2, + ULP_THOR2_SYM_ECV_VTAG_TYPE_ADD_1_REMAP_DIFFSERV = 3, + ULP_THOR2_SYM_ECV_VTAG_TYPE_ADD_2_ENCAP_PRI = 4, + ULP_THOR2_SYM_ECV_VTAG_TYPE_ADD_2_REMAP_DIFFSERV = 5, + ULP_THOR2_SYM_ECV_VTAG_TYPE_ADD_0_ENCAP_PRI = 6, + ULP_THOR2_SYM_ECV_VTAG_TYPE_ADD_0_REMAP_DIFFSERV = 7, + ULP_THOR2_SYM_ECV_VTAG_TYPE_ADD_0_PRI_0 = 8, + ULP_THOR2_SYM_ECV_VTAG_TYPE_ADD_0_PRI_1 = 8, + ULP_THOR2_SYM_ECV_VTAG_TYPE_ADD_0_PRI_2 = 8, + ULP_THOR2_SYM_ECV_VTAG_TYPE_ADD_0_PRI_3 = 8, + ULP_THOR2_SYM_ECV_VTAG_TYPE_ADD_0_PRI_4 = 8, + ULP_THOR2_SYM_ECV_VTAG_TYPE_ADD_0_PRI_5 = 8, + ULP_THOR2_SYM_ECV_VTAG_TYPE_ADD_0_PRI_6 = 8, + ULP_THOR2_SYM_ECV_VTAG_TYPE_ADD_0_PRI_7 = 8, + ULP_THOR2_SYM_ECV_L3_TYPE_NONE = 0, + ULP_THOR2_SYM_ECV_L3_TYPE_IPV4 = 4, + ULP_THOR2_SYM_ECV_L3_TYPE_IPV6 = 5, + ULP_THOR2_SYM_ECV_L3_TYPE_MPLS_8847 = 6, + ULP_THOR2_SYM_ECV_L3_TYPE_MPLS_8848 = 7, + ULP_THOR2_SYM_ECV_L4_TYPE_NONE = 0, + ULP_THOR2_SYM_ECV_L4_TYPE_UDP = 4, + ULP_THOR2_SYM_ECV_L4_TYPE_UDP_CSUM = 5, + ULP_THOR2_SYM_ECV_L4_TYPE_UDP_ENTROPY = 6, + ULP_THOR2_SYM_ECV_L4_TYPE_UDP_ENTROPY_CSUM = 7, + ULP_THOR2_SYM_ECV_TUN_TYPE_NONE = 0, + ULP_THOR2_SYM_ECV_TUN_TYPE_GENERIC = 1, + ULP_THOR2_SYM_ECV_TUN_TYPE_VXLAN = 2, + ULP_THOR2_SYM_ECV_TUN_TYPE_NGE = 3, + ULP_THOR2_SYM_ECV_TUN_TYPE_NVGRE = 4, + ULP_THOR2_SYM_ECV_TUN_TYPE_GRE = 5, + ULP_THOR2_SYM_EEM_ACT_REC_INT = 0, + ULP_THOR2_SYM_EEM_EXT_FLOW_CNTR = 0, + ULP_THOR2_SYM_UC_ACT_REC = 0, + ULP_THOR2_SYM_MC_ACT_REC = 1, + ULP_THOR2_SYM_ACT_REC_DROP_YES = 1, + ULP_THOR2_SYM_ACT_REC_DROP_NO = 0, + ULP_THOR2_SYM_ACT_REC_POP_VLAN_YES = 1, + ULP_THOR2_SYM_ACT_REC_POP_VLAN_NO = 0, + ULP_THOR2_SYM_ACT_REC_METER_EN_YES = 1, + ULP_THOR2_SYM_ACT_REC_METER_EN_NO = 0, + ULP_THOR2_SYM_LOOPBACK_PORT = 16, + ULP_THOR2_SYM_LOOPBACK_PARIF = 15, + ULP_THOR2_SYM_EXT_EM_MAX_KEY_SIZE = 0, + ULP_THOR2_SYM_MATCH_TYPE_EM = 0, + ULP_THOR2_SYM_MATCH_TYPE_WM = 1, + ULP_THOR2_SYM_IP_PROTO_ICMP = 1, + ULP_THOR2_SYM_IP_PROTO_IGMP = 2, + ULP_THOR2_SYM_IP_PROTO_IP_IN_IP = 4, + ULP_THOR2_SYM_IP_PROTO_TCP = 6, + ULP_THOR2_SYM_IP_PROTO_UDP = 17, + ULP_THOR2_SYM_VF_FUNC_PARIF = 15, + ULP_THOR2_SYM_NO = 0, + ULP_THOR2_SYM_YES = 1, + ULP_THOR2_SYM_RECYCLE_DST = 0x800, + ULP_THOR2_SYM_VF_2_VFR_META_VAL = 536870912, + ULP_THOR2_SYM_VF_2_VF_META_VAL = 536870912, + ULP_THOR2_SYM_VF_2_VFR_META_MASK = 4026531840, + ULP_THOR2_SYM_META_PROFILE_0 = 0, + ULP_THOR2_SYM_CHAIN_META_VAL = 0, + ULP_THOR2_SYM_L2_ECPRI_ETYPE = 44798, + ULP_THOR2_SYM_L4_ECPRI_ETYPE = 2048, + ULP_THOR2_SYM_L2_ROE_ETYPE = 64573 }; enum bnxt_ulp_df_tpl { - BNXT_ULP_DF_TPL_DEFAULT_UPLINK_PORT = 4, - BNXT_ULP_DF_TPL_DEFAULT_VFR = 5 + BNXT_ULP_DF_TPL_DEFAULT_UPLINK_PORT = 3, + BNXT_ULP_DF_TPL_DEFAULT_VFR = 4 }; #endif diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h index fada6a6283..900217d605 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h @@ -19,6 +19,14 @@ enum bnxt_ulp_glb_hf { BNXT_ULP_GLB_HF_ID_I_ETH_SMAC, BNXT_ULP_GLB_HF_ID_O_ETH_TYPE, BNXT_ULP_GLB_HF_ID_I_ETH_TYPE, + BNXT_ULP_GLB_HF_ID_O_GENEVE_VER_OPT_LEN_O_C_RSVD0, + BNXT_ULP_GLB_HF_ID_I_GENEVE_VER_OPT_LEN_O_C_RSVD0, + BNXT_ULP_GLB_HF_ID_O_GENEVE_PROTO_TYPE, + BNXT_ULP_GLB_HF_ID_I_GENEVE_PROTO_TYPE, + BNXT_ULP_GLB_HF_ID_O_GENEVE_VNI, + BNXT_ULP_GLB_HF_ID_I_GENEVE_VNI, + BNXT_ULP_GLB_HF_ID_O_GENEVE_RSVD1, + BNXT_ULP_GLB_HF_ID_I_GENEVE_RSVD1, BNXT_ULP_GLB_HF_ID_T_GRE_VER, BNXT_ULP_GLB_HF_ID_T_GRE_PROTO_TYPE, BNXT_ULP_GLB_HF_ID_O_ICMP_TYPE, @@ -33,8 +41,8 @@ enum bnxt_ulp_glb_hf { BNXT_ULP_GLB_HF_ID_I_ICMP_SEQ_NUM, BNXT_ULP_GLB_HF_ID_O_IPV4_VER, BNXT_ULP_GLB_HF_ID_I_IPV4_VER, - BNXT_ULP_GLB_HF_ID_O_IPV4_TOS, - BNXT_ULP_GLB_HF_ID_I_IPV4_TOS, + BNXT_ULP_GLB_HF_ID_O_IPV4_QOS, + BNXT_ULP_GLB_HF_ID_I_IPV4_QOS, BNXT_ULP_GLB_HF_ID_O_IPV4_LEN, BNXT_ULP_GLB_HF_ID_I_IPV4_LEN, BNXT_ULP_GLB_HF_ID_O_IPV4_FRAG_ID, @@ -53,8 +61,8 @@ enum bnxt_ulp_glb_hf { BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR, BNXT_ULP_GLB_HF_ID_O_IPV6_VER, BNXT_ULP_GLB_HF_ID_I_IPV6_VER, - BNXT_ULP_GLB_HF_ID_O_IPV6_TC, - BNXT_ULP_GLB_HF_ID_I_IPV6_TC, + BNXT_ULP_GLB_HF_ID_O_IPV6_QOS, + BNXT_ULP_GLB_HF_ID_I_IPV6_QOS, BNXT_ULP_GLB_HF_ID_O_IPV6_FLOW_LABEL, BNXT_ULP_GLB_HF_ID_I_IPV6_FLOW_LABEL, BNXT_ULP_GLB_HF_ID_O_IPV6_PAYLOAD_LEN, @@ -130,1168 +138,4 @@ enum bnxt_ulp_glb_hf { BNXT_ULP_GLB_HF_ID_T_VXLAN_GPE_RSVD1 }; -enum bnxt_ulp_hf_0_1_0_bitmask { - BNXT_ULP_HF_0_1_0_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF_0_1_0_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_1_0_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF_0_1_0_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF_0_1_0_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF_0_1_0_BITMASK_O_IPV6_VER = 0x0400000000000000, - BNXT_ULP_HF_0_1_0_BITMASK_O_IPV6_TC = 0x0200000000000000, - BNXT_ULP_HF_0_1_0_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000, - BNXT_ULP_HF_0_1_0_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000, - BNXT_ULP_HF_0_1_0_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000, - BNXT_ULP_HF_0_1_0_BITMASK_O_IPV6_TTL = 0x0020000000000000, - BNXT_ULP_HF_0_1_0_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000, - BNXT_ULP_HF_0_1_0_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000 -}; - -enum bnxt_ulp_hf_0_1_1_bitmask { - BNXT_ULP_HF_0_1_1_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF_0_1_1_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_1_1_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF_0_1_1_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF_0_1_1_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF_0_1_1_BITMASK_O_IPV4_VER = 0x0400000000000000, - BNXT_ULP_HF_0_1_1_BITMASK_O_IPV4_TOS = 0x0200000000000000, - BNXT_ULP_HF_0_1_1_BITMASK_O_IPV4_LEN = 0x0100000000000000, - BNXT_ULP_HF_0_1_1_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000, - BNXT_ULP_HF_0_1_1_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000, - BNXT_ULP_HF_0_1_1_BITMASK_O_IPV4_TTL = 0x0020000000000000, - BNXT_ULP_HF_0_1_1_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000, - BNXT_ULP_HF_0_1_1_BITMASK_O_IPV4_CSUM = 0x0008000000000000, - BNXT_ULP_HF_0_1_1_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, - BNXT_ULP_HF_0_1_1_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000 -}; - -enum bnxt_ulp_hf_0_1_2_bitmask { - BNXT_ULP_HF_0_1_2_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF_0_1_2_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_1_2_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF_0_1_2_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF_0_1_2_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF_0_1_2_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, - BNXT_ULP_HF_0_1_2_BITMASK_OO_VLAN_VID = 0x0200000000000000, - BNXT_ULP_HF_0_1_2_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, - BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_VER = 0x0080000000000000, - BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_TC = 0x0040000000000000, - BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000, - BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000, - BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000, - BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_TTL = 0x0004000000000000, - BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000, - BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000 -}; - -enum bnxt_ulp_hf_0_1_3_bitmask { - BNXT_ULP_HF_0_1_3_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF_0_1_3_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_1_3_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF_0_1_3_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF_0_1_3_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF_0_1_3_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, - BNXT_ULP_HF_0_1_3_BITMASK_OO_VLAN_VID = 0x0200000000000000, - BNXT_ULP_HF_0_1_3_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, - BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_VER = 0x0080000000000000, - BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_TOS = 0x0040000000000000, - BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_LEN = 0x0020000000000000, - BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000, - BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000, - BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_TTL = 0x0004000000000000, - BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000, - BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_CSUM = 0x0001000000000000, - BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000, - BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000 -}; - -enum bnxt_ulp_hf_0_1_4_bitmask { - BNXT_ULP_HF_0_1_4_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF_0_1_4_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_1_4_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF_0_1_4_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF_0_1_4_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_VER = 0x0400000000000000, - BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_TC = 0x0200000000000000, - BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000, - BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000, - BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000, - BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_TTL = 0x0020000000000000, - BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000, - BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000, - BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_SRC_PORT = 0x0004000000000000, - BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DST_PORT = 0x0002000000000000, - BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_SENT_SEQ = 0x0001000000000000, - BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_RECV_ACK = 0x0000800000000000, - BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DATA_OFF = 0x0000400000000000, - BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_TCP_FLAGS = 0x0000200000000000, - BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_RX_WIN = 0x0000100000000000, - BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_CSUM = 0x0000080000000000, - BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_URP = 0x0000040000000000 -}; - -enum bnxt_ulp_hf_0_1_5_bitmask { - BNXT_ULP_HF_0_1_5_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF_0_1_5_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_1_5_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF_0_1_5_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF_0_1_5_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_VER = 0x0400000000000000, - BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_TOS = 0x0200000000000000, - BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_LEN = 0x0100000000000000, - BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000, - BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000, - BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_TTL = 0x0020000000000000, - BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000, - BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_CSUM = 0x0008000000000000, - BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, - BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000, - BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_SRC_PORT = 0x0001000000000000, - BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DST_PORT = 0x0000800000000000, - BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_SENT_SEQ = 0x0000400000000000, - BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_RECV_ACK = 0x0000200000000000, - BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DATA_OFF = 0x0000100000000000, - BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_TCP_FLAGS = 0x0000080000000000, - BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_RX_WIN = 0x0000040000000000, - BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_CSUM = 0x0000020000000000, - BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_URP = 0x0000010000000000 -}; - -enum bnxt_ulp_hf_0_1_6_bitmask { - BNXT_ULP_HF_0_1_6_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF_0_1_6_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_1_6_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF_0_1_6_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF_0_1_6_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_VER = 0x0400000000000000, - BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_TC = 0x0200000000000000, - BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000, - BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000, - BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000, - BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_TTL = 0x0020000000000000, - BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000, - BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000, - BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_SRC_PORT = 0x0004000000000000, - BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_DST_PORT = 0x0002000000000000, - BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_LENGTH = 0x0001000000000000, - BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_CSUM = 0x0000800000000000 -}; - -enum bnxt_ulp_hf_0_1_7_bitmask { - BNXT_ULP_HF_0_1_7_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF_0_1_7_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_1_7_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF_0_1_7_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF_0_1_7_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_VER = 0x0400000000000000, - BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_TOS = 0x0200000000000000, - BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_LEN = 0x0100000000000000, - BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000, - BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000, - BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_TTL = 0x0020000000000000, - BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000, - BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_CSUM = 0x0008000000000000, - BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, - BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000, - BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_SRC_PORT = 0x0001000000000000, - BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_DST_PORT = 0x0000800000000000, - BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_LENGTH = 0x0000400000000000, - BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_CSUM = 0x0000200000000000 -}; - -enum bnxt_ulp_hf_0_1_8_bitmask { - BNXT_ULP_HF_0_1_8_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF_0_1_8_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF_0_1_8_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, - BNXT_ULP_HF_0_1_8_BITMASK_OO_VLAN_VID = 0x0200000000000000, - BNXT_ULP_HF_0_1_8_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_VER = 0x0080000000000000, - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_TC = 0x0040000000000000, - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000, - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000, - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000, - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_TTL = 0x0004000000000000, - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000, - BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000, - BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT = 0x0000800000000000, - BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT = 0x0000400000000000, - BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SENT_SEQ = 0x0000200000000000, - BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_RECV_ACK = 0x0000100000000000, - BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DATA_OFF = 0x0000080000000000, - BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_TCP_FLAGS = 0x0000040000000000, - BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_RX_WIN = 0x0000020000000000, - BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_CSUM = 0x0000010000000000, - BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_URP = 0x0000008000000000 -}; - -enum bnxt_ulp_hf_0_1_9_bitmask { - BNXT_ULP_HF_0_1_9_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF_0_1_9_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF_0_1_9_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, - BNXT_ULP_HF_0_1_9_BITMASK_OO_VLAN_VID = 0x0200000000000000, - BNXT_ULP_HF_0_1_9_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_VER = 0x0080000000000000, - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_TOS = 0x0040000000000000, - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_LEN = 0x0020000000000000, - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000, - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000, - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_TTL = 0x0004000000000000, - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000, - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_CSUM = 0x0001000000000000, - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000, - BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000, - BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT = 0x0000200000000000, - BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT = 0x0000100000000000, - BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SENT_SEQ = 0x0000080000000000, - BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_RECV_ACK = 0x0000040000000000, - BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DATA_OFF = 0x0000020000000000, - BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_TCP_FLAGS = 0x0000010000000000, - BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_RX_WIN = 0x0000008000000000, - BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_CSUM = 0x0000004000000000, - BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_URP = 0x0000002000000000 -}; - -enum bnxt_ulp_hf_0_1_10_bitmask { - BNXT_ULP_HF_0_1_10_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF_0_1_10_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF_0_1_10_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, - BNXT_ULP_HF_0_1_10_BITMASK_OO_VLAN_VID = 0x0200000000000000, - BNXT_ULP_HF_0_1_10_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_VER = 0x0080000000000000, - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_TC = 0x0040000000000000, - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000, - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000, - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000, - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_TTL = 0x0004000000000000, - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000, - BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000, - BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT = 0x0000800000000000, - BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT = 0x0000400000000000, - BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_LENGTH = 0x0000200000000000, - BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_CSUM = 0x0000100000000000 -}; - -enum bnxt_ulp_hf_0_1_11_bitmask { - BNXT_ULP_HF_0_1_11_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF_0_1_11_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF_0_1_11_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, - BNXT_ULP_HF_0_1_11_BITMASK_OO_VLAN_VID = 0x0200000000000000, - BNXT_ULP_HF_0_1_11_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_VER = 0x0080000000000000, - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_TOS = 0x0040000000000000, - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_LEN = 0x0020000000000000, - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000, - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000, - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_TTL = 0x0004000000000000, - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000, - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_CSUM = 0x0001000000000000, - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000, - BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000, - BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT = 0x0000200000000000, - BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT = 0x0000100000000000, - BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_LENGTH = 0x0000080000000000, - BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_CSUM = 0x0000040000000000 -}; - -enum bnxt_ulp_hf_0_1_12_bitmask { - BNXT_ULP_HF_0_1_12_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF_0_1_12_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_1_12_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF_0_1_12_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF_0_1_12_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF_0_1_12_BITMASK_O_IPV4_VER = 0x0400000000000000, - BNXT_ULP_HF_0_1_12_BITMASK_O_IPV4_TOS = 0x0200000000000000, - BNXT_ULP_HF_0_1_12_BITMASK_O_IPV4_LEN = 0x0100000000000000, - BNXT_ULP_HF_0_1_12_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000, - BNXT_ULP_HF_0_1_12_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000, - BNXT_ULP_HF_0_1_12_BITMASK_O_IPV4_TTL = 0x0020000000000000, - BNXT_ULP_HF_0_1_12_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000, - BNXT_ULP_HF_0_1_12_BITMASK_O_IPV4_CSUM = 0x0008000000000000, - BNXT_ULP_HF_0_1_12_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, - BNXT_ULP_HF_0_1_12_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000, - BNXT_ULP_HF_0_1_12_BITMASK_O_UDP_SRC_PORT = 0x0001000000000000, - BNXT_ULP_HF_0_1_12_BITMASK_O_UDP_DST_PORT = 0x0000800000000000, - BNXT_ULP_HF_0_1_12_BITMASK_O_UDP_LENGTH = 0x0000400000000000, - BNXT_ULP_HF_0_1_12_BITMASK_O_UDP_CSUM = 0x0000200000000000, - BNXT_ULP_HF_0_1_12_BITMASK_T_VXLAN_FLAGS = 0x0000100000000000, - BNXT_ULP_HF_0_1_12_BITMASK_T_VXLAN_RSVD0 = 0x0000080000000000, - BNXT_ULP_HF_0_1_12_BITMASK_T_VXLAN_VNI = 0x0000040000000000, - BNXT_ULP_HF_0_1_12_BITMASK_T_VXLAN_RSVD1 = 0x0000020000000000 -}; - -enum bnxt_ulp_hf_0_2_13_bitmask { - BNXT_ULP_HF_0_2_13_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF_0_2_13_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_2_13_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF_0_2_13_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF_0_2_13_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF_0_2_13_BITMASK_O_IPV6_VER = 0x0400000000000000, - BNXT_ULP_HF_0_2_13_BITMASK_O_IPV6_TC = 0x0200000000000000, - BNXT_ULP_HF_0_2_13_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000, - BNXT_ULP_HF_0_2_13_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000, - BNXT_ULP_HF_0_2_13_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000, - BNXT_ULP_HF_0_2_13_BITMASK_O_IPV6_TTL = 0x0020000000000000, - BNXT_ULP_HF_0_2_13_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000, - BNXT_ULP_HF_0_2_13_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000, - BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_SRC_PORT = 0x0004000000000000, - BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT = 0x0002000000000000, - BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_LENGTH = 0x0001000000000000, - BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_CSUM = 0x0000800000000000, - BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_FLAGS = 0x0000400000000000, - BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_RSVD0 = 0x0000200000000000, - BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI = 0x0000100000000000, - BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_RSVD1 = 0x0000080000000000 -}; - -enum bnxt_ulp_hf_0_2_14_bitmask { - BNXT_ULP_HF_0_2_14_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF_0_2_14_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_2_14_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF_0_2_14_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF_0_2_14_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF_0_2_14_BITMASK_O_IPV4_VER = 0x0400000000000000, - BNXT_ULP_HF_0_2_14_BITMASK_O_IPV4_TOS = 0x0200000000000000, - BNXT_ULP_HF_0_2_14_BITMASK_O_IPV4_LEN = 0x0100000000000000, - BNXT_ULP_HF_0_2_14_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000, - BNXT_ULP_HF_0_2_14_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000, - BNXT_ULP_HF_0_2_14_BITMASK_O_IPV4_TTL = 0x0020000000000000, - BNXT_ULP_HF_0_2_14_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000, - BNXT_ULP_HF_0_2_14_BITMASK_O_IPV4_CSUM = 0x0008000000000000, - BNXT_ULP_HF_0_2_14_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, - BNXT_ULP_HF_0_2_14_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000, - BNXT_ULP_HF_0_2_14_BITMASK_O_UDP_SRC_PORT = 0x0001000000000000, - BNXT_ULP_HF_0_2_14_BITMASK_O_UDP_DST_PORT = 0x0000800000000000, - BNXT_ULP_HF_0_2_14_BITMASK_O_UDP_LENGTH = 0x0000400000000000, - BNXT_ULP_HF_0_2_14_BITMASK_O_UDP_CSUM = 0x0000200000000000, - BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_FLAGS = 0x0000100000000000, - BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_RSVD0 = 0x0000080000000000, - BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI = 0x0000040000000000, - BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_RSVD1 = 0x0000020000000000 -}; - -enum bnxt_ulp_hf_0_2_15_bitmask { - BNXT_ULP_HF_0_2_15_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF_0_2_15_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_VER = 0x2000000000000000, - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_TC = 0x1000000000000000, - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_FLOW_LABEL = 0x0800000000000000, - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0400000000000000, - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_PROTO_ID = 0x0200000000000000, - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_TTL = 0x0100000000000000, - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_SRC_ADDR = 0x0080000000000000, - BNXT_ULP_HF_0_2_15_BITMASK_O_IPV6_DST_ADDR = 0x0040000000000000, - BNXT_ULP_HF_0_2_15_BITMASK_O_UDP_SRC_PORT = 0x0020000000000000, - BNXT_ULP_HF_0_2_15_BITMASK_O_UDP_DST_PORT = 0x0010000000000000, - BNXT_ULP_HF_0_2_15_BITMASK_O_UDP_LENGTH = 0x0008000000000000, - BNXT_ULP_HF_0_2_15_BITMASK_O_UDP_CSUM = 0x0004000000000000, - BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_FLAGS = 0x0002000000000000, - BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_RSVD0 = 0x0001000000000000, - BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI = 0x0000800000000000, - BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_RSVD1 = 0x0000400000000000, - BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_DMAC = 0x0000200000000000, - BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_SMAC = 0x0000100000000000, - BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_TYPE = 0x0000080000000000, - BNXT_ULP_HF_0_2_15_BITMASK_I_IPV6_VER = 0x0000040000000000, - BNXT_ULP_HF_0_2_15_BITMASK_I_IPV6_TC = 0x0000020000000000, - BNXT_ULP_HF_0_2_15_BITMASK_I_IPV6_FLOW_LABEL = 0x0000010000000000, - BNXT_ULP_HF_0_2_15_BITMASK_I_IPV6_PAYLOAD_LEN = 0x0000008000000000, - BNXT_ULP_HF_0_2_15_BITMASK_I_IPV6_PROTO_ID = 0x0000004000000000, - BNXT_ULP_HF_0_2_15_BITMASK_I_IPV6_TTL = 0x0000002000000000, - BNXT_ULP_HF_0_2_15_BITMASK_I_IPV6_SRC_ADDR = 0x0000001000000000, - BNXT_ULP_HF_0_2_15_BITMASK_I_IPV6_DST_ADDR = 0x0000000800000000 -}; - -enum bnxt_ulp_hf_0_2_16_bitmask { - BNXT_ULP_HF_0_2_16_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF_0_2_16_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_VER = 0x2000000000000000, - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_TOS = 0x1000000000000000, - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_LEN = 0x0800000000000000, - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000, - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000, - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_TTL = 0x0100000000000000, - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000, - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_CSUM = 0x0040000000000000, - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000, - BNXT_ULP_HF_0_2_16_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000, - BNXT_ULP_HF_0_2_16_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000, - BNXT_ULP_HF_0_2_16_BITMASK_O_UDP_DST_PORT = 0x0004000000000000, - BNXT_ULP_HF_0_2_16_BITMASK_O_UDP_LENGTH = 0x0002000000000000, - BNXT_ULP_HF_0_2_16_BITMASK_O_UDP_CSUM = 0x0001000000000000, - BNXT_ULP_HF_0_2_16_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000, - BNXT_ULP_HF_0_2_16_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000, - BNXT_ULP_HF_0_2_16_BITMASK_T_VXLAN_VNI = 0x0000200000000000, - BNXT_ULP_HF_0_2_16_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000, - BNXT_ULP_HF_0_2_16_BITMASK_I_ETH_DMAC = 0x0000080000000000, - BNXT_ULP_HF_0_2_16_BITMASK_I_ETH_SMAC = 0x0000040000000000, - BNXT_ULP_HF_0_2_16_BITMASK_I_ETH_TYPE = 0x0000020000000000, - BNXT_ULP_HF_0_2_16_BITMASK_I_IPV6_VER = 0x0000010000000000, - BNXT_ULP_HF_0_2_16_BITMASK_I_IPV6_TC = 0x0000008000000000, - BNXT_ULP_HF_0_2_16_BITMASK_I_IPV6_FLOW_LABEL = 0x0000004000000000, - BNXT_ULP_HF_0_2_16_BITMASK_I_IPV6_PAYLOAD_LEN = 0x0000002000000000, - BNXT_ULP_HF_0_2_16_BITMASK_I_IPV6_PROTO_ID = 0x0000001000000000, - BNXT_ULP_HF_0_2_16_BITMASK_I_IPV6_TTL = 0x0000000800000000, - BNXT_ULP_HF_0_2_16_BITMASK_I_IPV6_SRC_ADDR = 0x0000000400000000, - BNXT_ULP_HF_0_2_16_BITMASK_I_IPV6_DST_ADDR = 0x0000000200000000 -}; - -enum bnxt_ulp_hf_0_2_17_bitmask { - BNXT_ULP_HF_0_2_17_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF_0_2_17_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_VER = 0x2000000000000000, - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_TC = 0x1000000000000000, - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_FLOW_LABEL = 0x0800000000000000, - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0400000000000000, - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_PROTO_ID = 0x0200000000000000, - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_TTL = 0x0100000000000000, - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_SRC_ADDR = 0x0080000000000000, - BNXT_ULP_HF_0_2_17_BITMASK_O_IPV6_DST_ADDR = 0x0040000000000000, - BNXT_ULP_HF_0_2_17_BITMASK_O_UDP_SRC_PORT = 0x0020000000000000, - BNXT_ULP_HF_0_2_17_BITMASK_O_UDP_DST_PORT = 0x0010000000000000, - BNXT_ULP_HF_0_2_17_BITMASK_O_UDP_LENGTH = 0x0008000000000000, - BNXT_ULP_HF_0_2_17_BITMASK_O_UDP_CSUM = 0x0004000000000000, - BNXT_ULP_HF_0_2_17_BITMASK_T_VXLAN_FLAGS = 0x0002000000000000, - BNXT_ULP_HF_0_2_17_BITMASK_T_VXLAN_RSVD0 = 0x0001000000000000, - BNXT_ULP_HF_0_2_17_BITMASK_T_VXLAN_VNI = 0x0000800000000000, - BNXT_ULP_HF_0_2_17_BITMASK_T_VXLAN_RSVD1 = 0x0000400000000000, - BNXT_ULP_HF_0_2_17_BITMASK_I_ETH_DMAC = 0x0000200000000000, - BNXT_ULP_HF_0_2_17_BITMASK_I_ETH_SMAC = 0x0000100000000000, - BNXT_ULP_HF_0_2_17_BITMASK_I_ETH_TYPE = 0x0000080000000000, - BNXT_ULP_HF_0_2_17_BITMASK_I_IPV4_VER = 0x0000040000000000, - BNXT_ULP_HF_0_2_17_BITMASK_I_IPV4_TOS = 0x0000020000000000, - BNXT_ULP_HF_0_2_17_BITMASK_I_IPV4_LEN = 0x0000010000000000, - BNXT_ULP_HF_0_2_17_BITMASK_I_IPV4_FRAG_ID = 0x0000008000000000, - BNXT_ULP_HF_0_2_17_BITMASK_I_IPV4_FRAG_OFF = 0x0000004000000000, - BNXT_ULP_HF_0_2_17_BITMASK_I_IPV4_TTL = 0x0000002000000000, - BNXT_ULP_HF_0_2_17_BITMASK_I_IPV4_PROTO_ID = 0x0000001000000000, - BNXT_ULP_HF_0_2_17_BITMASK_I_IPV4_CSUM = 0x0000000800000000, - BNXT_ULP_HF_0_2_17_BITMASK_I_IPV4_SRC_ADDR = 0x0000000400000000, - BNXT_ULP_HF_0_2_17_BITMASK_I_IPV4_DST_ADDR = 0x0000000200000000 -}; - -enum bnxt_ulp_hf_0_2_18_bitmask { - BNXT_ULP_HF_0_2_18_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF_0_2_18_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_VER = 0x2000000000000000, - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_TOS = 0x1000000000000000, - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_LEN = 0x0800000000000000, - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000, - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000, - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_TTL = 0x0100000000000000, - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000, - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_CSUM = 0x0040000000000000, - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000, - BNXT_ULP_HF_0_2_18_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000, - BNXT_ULP_HF_0_2_18_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000, - BNXT_ULP_HF_0_2_18_BITMASK_O_UDP_DST_PORT = 0x0004000000000000, - BNXT_ULP_HF_0_2_18_BITMASK_O_UDP_LENGTH = 0x0002000000000000, - BNXT_ULP_HF_0_2_18_BITMASK_O_UDP_CSUM = 0x0001000000000000, - BNXT_ULP_HF_0_2_18_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000, - BNXT_ULP_HF_0_2_18_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000, - BNXT_ULP_HF_0_2_18_BITMASK_T_VXLAN_VNI = 0x0000200000000000, - BNXT_ULP_HF_0_2_18_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000, - BNXT_ULP_HF_0_2_18_BITMASK_I_ETH_DMAC = 0x0000080000000000, - BNXT_ULP_HF_0_2_18_BITMASK_I_ETH_SMAC = 0x0000040000000000, - BNXT_ULP_HF_0_2_18_BITMASK_I_ETH_TYPE = 0x0000020000000000, - BNXT_ULP_HF_0_2_18_BITMASK_I_IPV4_VER = 0x0000010000000000, - BNXT_ULP_HF_0_2_18_BITMASK_I_IPV4_TOS = 0x0000008000000000, - BNXT_ULP_HF_0_2_18_BITMASK_I_IPV4_LEN = 0x0000004000000000, - BNXT_ULP_HF_0_2_18_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000, - BNXT_ULP_HF_0_2_18_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000, - BNXT_ULP_HF_0_2_18_BITMASK_I_IPV4_TTL = 0x0000000800000000, - BNXT_ULP_HF_0_2_18_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000, - BNXT_ULP_HF_0_2_18_BITMASK_I_IPV4_CSUM = 0x0000000200000000, - BNXT_ULP_HF_0_2_18_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000, - BNXT_ULP_HF_0_2_18_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000 -}; - -enum bnxt_ulp_hf_0_2_19_bitmask { - BNXT_ULP_HF_0_2_19_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF_0_2_19_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_VER = 0x2000000000000000, - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_TC = 0x1000000000000000, - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_FLOW_LABEL = 0x0800000000000000, - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0400000000000000, - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_PROTO_ID = 0x0200000000000000, - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_TTL = 0x0100000000000000, - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_SRC_ADDR = 0x0080000000000000, - BNXT_ULP_HF_0_2_19_BITMASK_O_IPV6_DST_ADDR = 0x0040000000000000, - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_SRC_PORT = 0x0020000000000000, - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_DST_PORT = 0x0010000000000000, - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_LENGTH = 0x0008000000000000, - BNXT_ULP_HF_0_2_19_BITMASK_O_UDP_CSUM = 0x0004000000000000, - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_FLAGS = 0x0002000000000000, - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_RSVD0 = 0x0001000000000000, - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_VNI = 0x0000800000000000, - BNXT_ULP_HF_0_2_19_BITMASK_T_VXLAN_RSVD1 = 0x0000400000000000, - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_DMAC = 0x0000200000000000, - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_SMAC = 0x0000100000000000, - BNXT_ULP_HF_0_2_19_BITMASK_I_ETH_TYPE = 0x0000080000000000, - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_VER = 0x0000040000000000, - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_TC = 0x0000020000000000, - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_FLOW_LABEL = 0x0000010000000000, - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_PAYLOAD_LEN = 0x0000008000000000, - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_PROTO_ID = 0x0000004000000000, - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_TTL = 0x0000002000000000, - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_SRC_ADDR = 0x0000001000000000, - BNXT_ULP_HF_0_2_19_BITMASK_I_IPV6_DST_ADDR = 0x0000000800000000, - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SRC_PORT = 0x0000000400000000, - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DST_PORT = 0x0000000200000000, - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_SENT_SEQ = 0x0000000100000000, - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_RECV_ACK = 0x0000000080000000, - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_DATA_OFF = 0x0000000040000000, - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_TCP_FLAGS = 0x0000000020000000, - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_RX_WIN = 0x0000000010000000, - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_CSUM = 0x0000000008000000, - BNXT_ULP_HF_0_2_19_BITMASK_I_TCP_URP = 0x0000000004000000 -}; - -enum bnxt_ulp_hf_0_2_20_bitmask { - BNXT_ULP_HF_0_2_20_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF_0_2_20_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_VER = 0x2000000000000000, - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_TOS = 0x1000000000000000, - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_LEN = 0x0800000000000000, - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000, - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000, - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_TTL = 0x0100000000000000, - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000, - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_CSUM = 0x0040000000000000, - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000, - BNXT_ULP_HF_0_2_20_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000, - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000, - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_DST_PORT = 0x0004000000000000, - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_LENGTH = 0x0002000000000000, - BNXT_ULP_HF_0_2_20_BITMASK_O_UDP_CSUM = 0x0001000000000000, - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000, - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000, - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_VNI = 0x0000200000000000, - BNXT_ULP_HF_0_2_20_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000, - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_DMAC = 0x0000080000000000, - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_SMAC = 0x0000040000000000, - BNXT_ULP_HF_0_2_20_BITMASK_I_ETH_TYPE = 0x0000020000000000, - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_VER = 0x0000010000000000, - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_TC = 0x0000008000000000, - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_FLOW_LABEL = 0x0000004000000000, - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_PAYLOAD_LEN = 0x0000002000000000, - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_PROTO_ID = 0x0000001000000000, - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_TTL = 0x0000000800000000, - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_SRC_ADDR = 0x0000000400000000, - BNXT_ULP_HF_0_2_20_BITMASK_I_IPV6_DST_ADDR = 0x0000000200000000, - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SRC_PORT = 0x0000000100000000, - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DST_PORT = 0x0000000080000000, - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_SENT_SEQ = 0x0000000040000000, - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_RECV_ACK = 0x0000000020000000, - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_DATA_OFF = 0x0000000010000000, - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_TCP_FLAGS = 0x0000000008000000, - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_RX_WIN = 0x0000000004000000, - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_CSUM = 0x0000000002000000, - BNXT_ULP_HF_0_2_20_BITMASK_I_TCP_URP = 0x0000000001000000 -}; - -enum bnxt_ulp_hf_0_2_21_bitmask { - BNXT_ULP_HF_0_2_21_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF_0_2_21_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_VER = 0x2000000000000000, - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_TC = 0x1000000000000000, - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_FLOW_LABEL = 0x0800000000000000, - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0400000000000000, - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_PROTO_ID = 0x0200000000000000, - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_TTL = 0x0100000000000000, - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_SRC_ADDR = 0x0080000000000000, - BNXT_ULP_HF_0_2_21_BITMASK_O_IPV6_DST_ADDR = 0x0040000000000000, - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_SRC_PORT = 0x0020000000000000, - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_DST_PORT = 0x0010000000000000, - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_LENGTH = 0x0008000000000000, - BNXT_ULP_HF_0_2_21_BITMASK_O_UDP_CSUM = 0x0004000000000000, - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_FLAGS = 0x0002000000000000, - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_RSVD0 = 0x0001000000000000, - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_VNI = 0x0000800000000000, - BNXT_ULP_HF_0_2_21_BITMASK_T_VXLAN_RSVD1 = 0x0000400000000000, - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_DMAC = 0x0000200000000000, - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_SMAC = 0x0000100000000000, - BNXT_ULP_HF_0_2_21_BITMASK_I_ETH_TYPE = 0x0000080000000000, - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_VER = 0x0000040000000000, - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_TOS = 0x0000020000000000, - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_LEN = 0x0000010000000000, - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_FRAG_ID = 0x0000008000000000, - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_FRAG_OFF = 0x0000004000000000, - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_TTL = 0x0000002000000000, - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_PROTO_ID = 0x0000001000000000, - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_CSUM = 0x0000000800000000, - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_SRC_ADDR = 0x0000000400000000, - BNXT_ULP_HF_0_2_21_BITMASK_I_IPV4_DST_ADDR = 0x0000000200000000, - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SRC_PORT = 0x0000000100000000, - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DST_PORT = 0x0000000080000000, - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_SENT_SEQ = 0x0000000040000000, - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_RECV_ACK = 0x0000000020000000, - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_DATA_OFF = 0x0000000010000000, - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_TCP_FLAGS = 0x0000000008000000, - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_RX_WIN = 0x0000000004000000, - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_CSUM = 0x0000000002000000, - BNXT_ULP_HF_0_2_21_BITMASK_I_TCP_URP = 0x0000000001000000 -}; - -enum bnxt_ulp_hf_0_2_22_bitmask { - BNXT_ULP_HF_0_2_22_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF_0_2_22_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_VER = 0x2000000000000000, - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_TOS = 0x1000000000000000, - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_LEN = 0x0800000000000000, - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000, - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000, - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_TTL = 0x0100000000000000, - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000, - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_CSUM = 0x0040000000000000, - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000, - BNXT_ULP_HF_0_2_22_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000, - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000, - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_DST_PORT = 0x0004000000000000, - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_LENGTH = 0x0002000000000000, - BNXT_ULP_HF_0_2_22_BITMASK_O_UDP_CSUM = 0x0001000000000000, - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000, - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000, - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_VNI = 0x0000200000000000, - BNXT_ULP_HF_0_2_22_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000, - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_DMAC = 0x0000080000000000, - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_SMAC = 0x0000040000000000, - BNXT_ULP_HF_0_2_22_BITMASK_I_ETH_TYPE = 0x0000020000000000, - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_VER = 0x0000010000000000, - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_TOS = 0x0000008000000000, - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_LEN = 0x0000004000000000, - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000, - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000, - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_TTL = 0x0000000800000000, - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000, - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_CSUM = 0x0000000200000000, - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000, - BNXT_ULP_HF_0_2_22_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000, - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SRC_PORT = 0x0000000040000000, - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DST_PORT = 0x0000000020000000, - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_SENT_SEQ = 0x0000000010000000, - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_RECV_ACK = 0x0000000008000000, - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_DATA_OFF = 0x0000000004000000, - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_TCP_FLAGS = 0x0000000002000000, - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_RX_WIN = 0x0000000001000000, - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_CSUM = 0x0000000000800000, - BNXT_ULP_HF_0_2_22_BITMASK_I_TCP_URP = 0x0000000000400000 -}; - -enum bnxt_ulp_hf_0_2_23_bitmask { - BNXT_ULP_HF_0_2_23_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF_0_2_23_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_VER = 0x2000000000000000, - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_TC = 0x1000000000000000, - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_FLOW_LABEL = 0x0800000000000000, - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0400000000000000, - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_PROTO_ID = 0x0200000000000000, - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_TTL = 0x0100000000000000, - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_SRC_ADDR = 0x0080000000000000, - BNXT_ULP_HF_0_2_23_BITMASK_O_IPV6_DST_ADDR = 0x0040000000000000, - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_SRC_PORT = 0x0020000000000000, - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_DST_PORT = 0x0010000000000000, - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_LENGTH = 0x0008000000000000, - BNXT_ULP_HF_0_2_23_BITMASK_O_UDP_CSUM = 0x0004000000000000, - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_FLAGS = 0x0002000000000000, - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_RSVD0 = 0x0001000000000000, - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_VNI = 0x0000800000000000, - BNXT_ULP_HF_0_2_23_BITMASK_T_VXLAN_RSVD1 = 0x0000400000000000, - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_DMAC = 0x0000200000000000, - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_SMAC = 0x0000100000000000, - BNXT_ULP_HF_0_2_23_BITMASK_I_ETH_TYPE = 0x0000080000000000, - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_VER = 0x0000040000000000, - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_TC = 0x0000020000000000, - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_FLOW_LABEL = 0x0000010000000000, - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_PAYLOAD_LEN = 0x0000008000000000, - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_PROTO_ID = 0x0000004000000000, - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_TTL = 0x0000002000000000, - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_SRC_ADDR = 0x0000001000000000, - BNXT_ULP_HF_0_2_23_BITMASK_I_IPV6_DST_ADDR = 0x0000000800000000, - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_SRC_PORT = 0x0000000400000000, - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_DST_PORT = 0x0000000200000000, - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_LENGTH = 0x0000000100000000, - BNXT_ULP_HF_0_2_23_BITMASK_I_UDP_CSUM = 0x0000000080000000 -}; - -enum bnxt_ulp_hf_0_2_24_bitmask { - BNXT_ULP_HF_0_2_24_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF_0_2_24_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_VER = 0x2000000000000000, - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_TOS = 0x1000000000000000, - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_LEN = 0x0800000000000000, - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000, - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000, - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_TTL = 0x0100000000000000, - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000, - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_CSUM = 0x0040000000000000, - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000, - BNXT_ULP_HF_0_2_24_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000, - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000, - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_DST_PORT = 0x0004000000000000, - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_LENGTH = 0x0002000000000000, - BNXT_ULP_HF_0_2_24_BITMASK_O_UDP_CSUM = 0x0001000000000000, - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000, - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000, - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_VNI = 0x0000200000000000, - BNXT_ULP_HF_0_2_24_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000, - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_DMAC = 0x0000080000000000, - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_SMAC = 0x0000040000000000, - BNXT_ULP_HF_0_2_24_BITMASK_I_ETH_TYPE = 0x0000020000000000, - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_VER = 0x0000010000000000, - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_TC = 0x0000008000000000, - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_FLOW_LABEL = 0x0000004000000000, - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_PAYLOAD_LEN = 0x0000002000000000, - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_PROTO_ID = 0x0000001000000000, - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_TTL = 0x0000000800000000, - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_SRC_ADDR = 0x0000000400000000, - BNXT_ULP_HF_0_2_24_BITMASK_I_IPV6_DST_ADDR = 0x0000000200000000, - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_SRC_PORT = 0x0000000100000000, - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_DST_PORT = 0x0000000080000000, - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_LENGTH = 0x0000000040000000, - BNXT_ULP_HF_0_2_24_BITMASK_I_UDP_CSUM = 0x0000000020000000 -}; - -enum bnxt_ulp_hf_0_2_25_bitmask { - BNXT_ULP_HF_0_2_25_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF_0_2_25_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_VER = 0x2000000000000000, - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_TC = 0x1000000000000000, - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_FLOW_LABEL = 0x0800000000000000, - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0400000000000000, - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_PROTO_ID = 0x0200000000000000, - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_TTL = 0x0100000000000000, - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_SRC_ADDR = 0x0080000000000000, - BNXT_ULP_HF_0_2_25_BITMASK_O_IPV6_DST_ADDR = 0x0040000000000000, - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_SRC_PORT = 0x0020000000000000, - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_DST_PORT = 0x0010000000000000, - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_LENGTH = 0x0008000000000000, - BNXT_ULP_HF_0_2_25_BITMASK_O_UDP_CSUM = 0x0004000000000000, - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_FLAGS = 0x0002000000000000, - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_RSVD0 = 0x0001000000000000, - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_VNI = 0x0000800000000000, - BNXT_ULP_HF_0_2_25_BITMASK_T_VXLAN_RSVD1 = 0x0000400000000000, - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_DMAC = 0x0000200000000000, - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_SMAC = 0x0000100000000000, - BNXT_ULP_HF_0_2_25_BITMASK_I_ETH_TYPE = 0x0000080000000000, - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_VER = 0x0000040000000000, - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_TOS = 0x0000020000000000, - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_LEN = 0x0000010000000000, - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_FRAG_ID = 0x0000008000000000, - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_FRAG_OFF = 0x0000004000000000, - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_TTL = 0x0000002000000000, - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_PROTO_ID = 0x0000001000000000, - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_CSUM = 0x0000000800000000, - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_SRC_ADDR = 0x0000000400000000, - BNXT_ULP_HF_0_2_25_BITMASK_I_IPV4_DST_ADDR = 0x0000000200000000, - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_SRC_PORT = 0x0000000100000000, - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_DST_PORT = 0x0000000080000000, - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_LENGTH = 0x0000000040000000, - BNXT_ULP_HF_0_2_25_BITMASK_I_UDP_CSUM = 0x0000000020000000 -}; - -enum bnxt_ulp_hf_0_2_26_bitmask { - BNXT_ULP_HF_0_2_26_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF_0_2_26_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_VER = 0x2000000000000000, - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_TOS = 0x1000000000000000, - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_LEN = 0x0800000000000000, - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000, - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000, - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_TTL = 0x0100000000000000, - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000, - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_CSUM = 0x0040000000000000, - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000, - BNXT_ULP_HF_0_2_26_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000, - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000, - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_DST_PORT = 0x0004000000000000, - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_LENGTH = 0x0002000000000000, - BNXT_ULP_HF_0_2_26_BITMASK_O_UDP_CSUM = 0x0001000000000000, - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000, - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000, - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_VNI = 0x0000200000000000, - BNXT_ULP_HF_0_2_26_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000, - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_DMAC = 0x0000080000000000, - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_SMAC = 0x0000040000000000, - BNXT_ULP_HF_0_2_26_BITMASK_I_ETH_TYPE = 0x0000020000000000, - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_VER = 0x0000010000000000, - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_TOS = 0x0000008000000000, - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_LEN = 0x0000004000000000, - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000, - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000, - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_TTL = 0x0000000800000000, - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000, - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_CSUM = 0x0000000200000000, - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000, - BNXT_ULP_HF_0_2_26_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000, - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_SRC_PORT = 0x0000000040000000, - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_DST_PORT = 0x0000000020000000, - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_LENGTH = 0x0000000010000000, - BNXT_ULP_HF_0_2_26_BITMASK_I_UDP_CSUM = 0x0000000008000000 -}; - -enum bnxt_ulp_hf_0_2_27_bitmask { - BNXT_ULP_HF_0_2_27_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF_0_2_27_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_VER = 0x2000000000000000, - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_TC = 0x1000000000000000, - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_FLOW_LABEL = 0x0800000000000000, - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0400000000000000, - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_PROTO_ID = 0x0200000000000000, - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_TTL = 0x0100000000000000, - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_SRC_ADDR = 0x0080000000000000, - BNXT_ULP_HF_0_2_27_BITMASK_O_IPV6_DST_ADDR = 0x0040000000000000, - BNXT_ULP_HF_0_2_27_BITMASK_O_UDP_SRC_PORT = 0x0020000000000000, - BNXT_ULP_HF_0_2_27_BITMASK_O_UDP_DST_PORT = 0x0010000000000000, - BNXT_ULP_HF_0_2_27_BITMASK_O_UDP_LENGTH = 0x0008000000000000, - BNXT_ULP_HF_0_2_27_BITMASK_O_UDP_CSUM = 0x0004000000000000, - BNXT_ULP_HF_0_2_27_BITMASK_T_VXLAN_FLAGS = 0x0002000000000000, - BNXT_ULP_HF_0_2_27_BITMASK_T_VXLAN_RSVD0 = 0x0001000000000000, - BNXT_ULP_HF_0_2_27_BITMASK_T_VXLAN_VNI = 0x0000800000000000, - BNXT_ULP_HF_0_2_27_BITMASK_T_VXLAN_RSVD1 = 0x0000400000000000, - BNXT_ULP_HF_0_2_27_BITMASK_I_ETH_DMAC = 0x0000200000000000, - BNXT_ULP_HF_0_2_27_BITMASK_I_ETH_SMAC = 0x0000100000000000, - BNXT_ULP_HF_0_2_27_BITMASK_I_ETH_TYPE = 0x0000080000000000, - BNXT_ULP_HF_0_2_27_BITMASK_I_IPV4_VER = 0x0000040000000000, - BNXT_ULP_HF_0_2_27_BITMASK_I_IPV4_TOS = 0x0000020000000000, - BNXT_ULP_HF_0_2_27_BITMASK_I_IPV4_LEN = 0x0000010000000000, - BNXT_ULP_HF_0_2_27_BITMASK_I_IPV4_FRAG_ID = 0x0000008000000000, - BNXT_ULP_HF_0_2_27_BITMASK_I_IPV4_FRAG_OFF = 0x0000004000000000, - BNXT_ULP_HF_0_2_27_BITMASK_I_IPV4_TTL = 0x0000002000000000, - BNXT_ULP_HF_0_2_27_BITMASK_I_IPV4_PROTO_ID = 0x0000001000000000, - BNXT_ULP_HF_0_2_27_BITMASK_I_IPV4_CSUM = 0x0000000800000000, - BNXT_ULP_HF_0_2_27_BITMASK_I_IPV4_SRC_ADDR = 0x0000000400000000, - BNXT_ULP_HF_0_2_27_BITMASK_I_IPV4_DST_ADDR = 0x0000000200000000, - BNXT_ULP_HF_0_2_27_BITMASK_I_ICMP_TYPE = 0x0000000100000000, - BNXT_ULP_HF_0_2_27_BITMASK_I_ICMP_CODE = 0x0000000080000000, - BNXT_ULP_HF_0_2_27_BITMASK_I_ICMP_CSUM = 0x0000000040000000, - BNXT_ULP_HF_0_2_27_BITMASK_I_ICMP_IDENT = 0x0000000020000000, - BNXT_ULP_HF_0_2_27_BITMASK_I_ICMP_SEQ_NUM = 0x0000000010000000 -}; - -enum bnxt_ulp_hf_0_2_28_bitmask { - BNXT_ULP_HF_0_2_28_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF_0_2_28_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_VER = 0x2000000000000000, - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_TOS = 0x1000000000000000, - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_LEN = 0x0800000000000000, - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000, - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000, - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_TTL = 0x0100000000000000, - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000, - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_CSUM = 0x0040000000000000, - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000, - BNXT_ULP_HF_0_2_28_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000, - BNXT_ULP_HF_0_2_28_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000, - BNXT_ULP_HF_0_2_28_BITMASK_O_UDP_DST_PORT = 0x0004000000000000, - BNXT_ULP_HF_0_2_28_BITMASK_O_UDP_LENGTH = 0x0002000000000000, - BNXT_ULP_HF_0_2_28_BITMASK_O_UDP_CSUM = 0x0001000000000000, - BNXT_ULP_HF_0_2_28_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000, - BNXT_ULP_HF_0_2_28_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000, - BNXT_ULP_HF_0_2_28_BITMASK_T_VXLAN_VNI = 0x0000200000000000, - BNXT_ULP_HF_0_2_28_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000, - BNXT_ULP_HF_0_2_28_BITMASK_I_ETH_DMAC = 0x0000080000000000, - BNXT_ULP_HF_0_2_28_BITMASK_I_ETH_SMAC = 0x0000040000000000, - BNXT_ULP_HF_0_2_28_BITMASK_I_ETH_TYPE = 0x0000020000000000, - BNXT_ULP_HF_0_2_28_BITMASK_I_IPV4_VER = 0x0000010000000000, - BNXT_ULP_HF_0_2_28_BITMASK_I_IPV4_TOS = 0x0000008000000000, - BNXT_ULP_HF_0_2_28_BITMASK_I_IPV4_LEN = 0x0000004000000000, - BNXT_ULP_HF_0_2_28_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000, - BNXT_ULP_HF_0_2_28_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000, - BNXT_ULP_HF_0_2_28_BITMASK_I_IPV4_TTL = 0x0000000800000000, - BNXT_ULP_HF_0_2_28_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000, - BNXT_ULP_HF_0_2_28_BITMASK_I_IPV4_CSUM = 0x0000000200000000, - BNXT_ULP_HF_0_2_28_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000, - BNXT_ULP_HF_0_2_28_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000, - BNXT_ULP_HF_0_2_28_BITMASK_I_ICMP_TYPE = 0x0000000040000000, - BNXT_ULP_HF_0_2_28_BITMASK_I_ICMP_CODE = 0x0000000020000000, - BNXT_ULP_HF_0_2_28_BITMASK_I_ICMP_CSUM = 0x0000000010000000, - BNXT_ULP_HF_0_2_28_BITMASK_I_ICMP_IDENT = 0x0000000008000000, - BNXT_ULP_HF_0_2_28_BITMASK_I_ICMP_SEQ_NUM = 0x0000000004000000 -}; - -enum bnxt_ulp_hf_0_3_29_bitmask { - BNXT_ULP_HF_0_3_29_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF_0_3_29_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_3_29_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF_0_3_29_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF_0_3_29_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF_0_3_29_BITMASK_O_IPV6_VER = 0x0400000000000000, - BNXT_ULP_HF_0_3_29_BITMASK_O_IPV6_TC = 0x0200000000000000, - BNXT_ULP_HF_0_3_29_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000, - BNXT_ULP_HF_0_3_29_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000, - BNXT_ULP_HF_0_3_29_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000, - BNXT_ULP_HF_0_3_29_BITMASK_O_IPV6_TTL = 0x0020000000000000, - BNXT_ULP_HF_0_3_29_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000, - BNXT_ULP_HF_0_3_29_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000 -}; - -enum bnxt_ulp_hf_0_3_30_bitmask { - BNXT_ULP_HF_0_3_30_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF_0_3_30_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_3_30_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF_0_3_30_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF_0_3_30_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF_0_3_30_BITMASK_O_IPV4_VER = 0x0400000000000000, - BNXT_ULP_HF_0_3_30_BITMASK_O_IPV4_TOS = 0x0200000000000000, - BNXT_ULP_HF_0_3_30_BITMASK_O_IPV4_LEN = 0x0100000000000000, - BNXT_ULP_HF_0_3_30_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000, - BNXT_ULP_HF_0_3_30_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000, - BNXT_ULP_HF_0_3_30_BITMASK_O_IPV4_TTL = 0x0020000000000000, - BNXT_ULP_HF_0_3_30_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000, - BNXT_ULP_HF_0_3_30_BITMASK_O_IPV4_CSUM = 0x0008000000000000, - BNXT_ULP_HF_0_3_30_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, - BNXT_ULP_HF_0_3_30_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000 -}; - -enum bnxt_ulp_hf_0_3_31_bitmask { - BNXT_ULP_HF_0_3_31_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF_0_3_31_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_3_31_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF_0_3_31_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF_0_3_31_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF_0_3_31_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, - BNXT_ULP_HF_0_3_31_BITMASK_OO_VLAN_VID = 0x0200000000000000, - BNXT_ULP_HF_0_3_31_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, - BNXT_ULP_HF_0_3_31_BITMASK_O_IPV6_VER = 0x0080000000000000, - BNXT_ULP_HF_0_3_31_BITMASK_O_IPV6_TC = 0x0040000000000000, - BNXT_ULP_HF_0_3_31_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000, - BNXT_ULP_HF_0_3_31_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000, - BNXT_ULP_HF_0_3_31_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000, - BNXT_ULP_HF_0_3_31_BITMASK_O_IPV6_TTL = 0x0004000000000000, - BNXT_ULP_HF_0_3_31_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000, - BNXT_ULP_HF_0_3_31_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000 -}; - -enum bnxt_ulp_hf_0_3_32_bitmask { - BNXT_ULP_HF_0_3_32_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF_0_3_32_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_3_32_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF_0_3_32_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF_0_3_32_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF_0_3_32_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, - BNXT_ULP_HF_0_3_32_BITMASK_OO_VLAN_VID = 0x0200000000000000, - BNXT_ULP_HF_0_3_32_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, - BNXT_ULP_HF_0_3_32_BITMASK_O_IPV4_VER = 0x0080000000000000, - BNXT_ULP_HF_0_3_32_BITMASK_O_IPV4_TOS = 0x0040000000000000, - BNXT_ULP_HF_0_3_32_BITMASK_O_IPV4_LEN = 0x0020000000000000, - BNXT_ULP_HF_0_3_32_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000, - BNXT_ULP_HF_0_3_32_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000, - BNXT_ULP_HF_0_3_32_BITMASK_O_IPV4_TTL = 0x0004000000000000, - BNXT_ULP_HF_0_3_32_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000, - BNXT_ULP_HF_0_3_32_BITMASK_O_IPV4_CSUM = 0x0001000000000000, - BNXT_ULP_HF_0_3_32_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000, - BNXT_ULP_HF_0_3_32_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000 -}; - -enum bnxt_ulp_hf_0_3_33_bitmask { - BNXT_ULP_HF_0_3_33_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF_0_3_33_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_3_33_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF_0_3_33_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF_0_3_33_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF_0_3_33_BITMASK_O_IPV6_VER = 0x0400000000000000, - BNXT_ULP_HF_0_3_33_BITMASK_O_IPV6_TC = 0x0200000000000000, - BNXT_ULP_HF_0_3_33_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000, - BNXT_ULP_HF_0_3_33_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000, - BNXT_ULP_HF_0_3_33_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000, - BNXT_ULP_HF_0_3_33_BITMASK_O_IPV6_TTL = 0x0020000000000000, - BNXT_ULP_HF_0_3_33_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000, - BNXT_ULP_HF_0_3_33_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000, - BNXT_ULP_HF_0_3_33_BITMASK_O_TCP_SRC_PORT = 0x0004000000000000, - BNXT_ULP_HF_0_3_33_BITMASK_O_TCP_DST_PORT = 0x0002000000000000, - BNXT_ULP_HF_0_3_33_BITMASK_O_TCP_SENT_SEQ = 0x0001000000000000, - BNXT_ULP_HF_0_3_33_BITMASK_O_TCP_RECV_ACK = 0x0000800000000000, - BNXT_ULP_HF_0_3_33_BITMASK_O_TCP_DATA_OFF = 0x0000400000000000, - BNXT_ULP_HF_0_3_33_BITMASK_O_TCP_TCP_FLAGS = 0x0000200000000000, - BNXT_ULP_HF_0_3_33_BITMASK_O_TCP_RX_WIN = 0x0000100000000000, - BNXT_ULP_HF_0_3_33_BITMASK_O_TCP_CSUM = 0x0000080000000000, - BNXT_ULP_HF_0_3_33_BITMASK_O_TCP_URP = 0x0000040000000000 -}; - -enum bnxt_ulp_hf_0_3_34_bitmask { - BNXT_ULP_HF_0_3_34_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF_0_3_34_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_3_34_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF_0_3_34_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF_0_3_34_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF_0_3_34_BITMASK_O_IPV4_VER = 0x0400000000000000, - BNXT_ULP_HF_0_3_34_BITMASK_O_IPV4_TOS = 0x0200000000000000, - BNXT_ULP_HF_0_3_34_BITMASK_O_IPV4_LEN = 0x0100000000000000, - BNXT_ULP_HF_0_3_34_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000, - BNXT_ULP_HF_0_3_34_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000, - BNXT_ULP_HF_0_3_34_BITMASK_O_IPV4_TTL = 0x0020000000000000, - BNXT_ULP_HF_0_3_34_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000, - BNXT_ULP_HF_0_3_34_BITMASK_O_IPV4_CSUM = 0x0008000000000000, - BNXT_ULP_HF_0_3_34_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, - BNXT_ULP_HF_0_3_34_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000, - BNXT_ULP_HF_0_3_34_BITMASK_O_TCP_SRC_PORT = 0x0001000000000000, - BNXT_ULP_HF_0_3_34_BITMASK_O_TCP_DST_PORT = 0x0000800000000000, - BNXT_ULP_HF_0_3_34_BITMASK_O_TCP_SENT_SEQ = 0x0000400000000000, - BNXT_ULP_HF_0_3_34_BITMASK_O_TCP_RECV_ACK = 0x0000200000000000, - BNXT_ULP_HF_0_3_34_BITMASK_O_TCP_DATA_OFF = 0x0000100000000000, - BNXT_ULP_HF_0_3_34_BITMASK_O_TCP_TCP_FLAGS = 0x0000080000000000, - BNXT_ULP_HF_0_3_34_BITMASK_O_TCP_RX_WIN = 0x0000040000000000, - BNXT_ULP_HF_0_3_34_BITMASK_O_TCP_CSUM = 0x0000020000000000, - BNXT_ULP_HF_0_3_34_BITMASK_O_TCP_URP = 0x0000010000000000 -}; - -enum bnxt_ulp_hf_0_3_35_bitmask { - BNXT_ULP_HF_0_3_35_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF_0_3_35_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_3_35_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF_0_3_35_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF_0_3_35_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF_0_3_35_BITMASK_O_IPV6_VER = 0x0400000000000000, - BNXT_ULP_HF_0_3_35_BITMASK_O_IPV6_TC = 0x0200000000000000, - BNXT_ULP_HF_0_3_35_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000, - BNXT_ULP_HF_0_3_35_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000, - BNXT_ULP_HF_0_3_35_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000, - BNXT_ULP_HF_0_3_35_BITMASK_O_IPV6_TTL = 0x0020000000000000, - BNXT_ULP_HF_0_3_35_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000, - BNXT_ULP_HF_0_3_35_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000, - BNXT_ULP_HF_0_3_35_BITMASK_O_UDP_SRC_PORT = 0x0004000000000000, - BNXT_ULP_HF_0_3_35_BITMASK_O_UDP_DST_PORT = 0x0002000000000000, - BNXT_ULP_HF_0_3_35_BITMASK_O_UDP_LENGTH = 0x0001000000000000, - BNXT_ULP_HF_0_3_35_BITMASK_O_UDP_CSUM = 0x0000800000000000 -}; - -enum bnxt_ulp_hf_0_3_36_bitmask { - BNXT_ULP_HF_0_3_36_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF_0_3_36_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_3_36_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF_0_3_36_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF_0_3_36_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF_0_3_36_BITMASK_O_IPV4_VER = 0x0400000000000000, - BNXT_ULP_HF_0_3_36_BITMASK_O_IPV4_TOS = 0x0200000000000000, - BNXT_ULP_HF_0_3_36_BITMASK_O_IPV4_LEN = 0x0100000000000000, - BNXT_ULP_HF_0_3_36_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000, - BNXT_ULP_HF_0_3_36_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000, - BNXT_ULP_HF_0_3_36_BITMASK_O_IPV4_TTL = 0x0020000000000000, - BNXT_ULP_HF_0_3_36_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000, - BNXT_ULP_HF_0_3_36_BITMASK_O_IPV4_CSUM = 0x0008000000000000, - BNXT_ULP_HF_0_3_36_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, - BNXT_ULP_HF_0_3_36_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000, - BNXT_ULP_HF_0_3_36_BITMASK_O_UDP_SRC_PORT = 0x0001000000000000, - BNXT_ULP_HF_0_3_36_BITMASK_O_UDP_DST_PORT = 0x0000800000000000, - BNXT_ULP_HF_0_3_36_BITMASK_O_UDP_LENGTH = 0x0000400000000000, - BNXT_ULP_HF_0_3_36_BITMASK_O_UDP_CSUM = 0x0000200000000000 -}; - -enum bnxt_ulp_hf_0_3_37_bitmask { - BNXT_ULP_HF_0_3_37_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF_0_3_37_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_3_37_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF_0_3_37_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF_0_3_37_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF_0_3_37_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, - BNXT_ULP_HF_0_3_37_BITMASK_OO_VLAN_VID = 0x0200000000000000, - BNXT_ULP_HF_0_3_37_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_VER = 0x0080000000000000, - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_TC = 0x0040000000000000, - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000, - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000, - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000, - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_TTL = 0x0004000000000000, - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000, - BNXT_ULP_HF_0_3_37_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000, - BNXT_ULP_HF_0_3_37_BITMASK_O_TCP_SRC_PORT = 0x0000800000000000, - BNXT_ULP_HF_0_3_37_BITMASK_O_TCP_DST_PORT = 0x0000400000000000, - BNXT_ULP_HF_0_3_37_BITMASK_O_TCP_SENT_SEQ = 0x0000200000000000, - BNXT_ULP_HF_0_3_37_BITMASK_O_TCP_RECV_ACK = 0x0000100000000000, - BNXT_ULP_HF_0_3_37_BITMASK_O_TCP_DATA_OFF = 0x0000080000000000, - BNXT_ULP_HF_0_3_37_BITMASK_O_TCP_TCP_FLAGS = 0x0000040000000000, - BNXT_ULP_HF_0_3_37_BITMASK_O_TCP_RX_WIN = 0x0000020000000000, - BNXT_ULP_HF_0_3_37_BITMASK_O_TCP_CSUM = 0x0000010000000000, - BNXT_ULP_HF_0_3_37_BITMASK_O_TCP_URP = 0x0000008000000000 -}; - -enum bnxt_ulp_hf_0_3_38_bitmask { - BNXT_ULP_HF_0_3_38_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF_0_3_38_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_3_38_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF_0_3_38_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF_0_3_38_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF_0_3_38_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, - BNXT_ULP_HF_0_3_38_BITMASK_OO_VLAN_VID = 0x0200000000000000, - BNXT_ULP_HF_0_3_38_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_VER = 0x0080000000000000, - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_TOS = 0x0040000000000000, - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_LEN = 0x0020000000000000, - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000, - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000, - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_TTL = 0x0004000000000000, - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000, - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_CSUM = 0x0001000000000000, - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000, - BNXT_ULP_HF_0_3_38_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000, - BNXT_ULP_HF_0_3_38_BITMASK_O_TCP_SRC_PORT = 0x0000200000000000, - BNXT_ULP_HF_0_3_38_BITMASK_O_TCP_DST_PORT = 0x0000100000000000, - BNXT_ULP_HF_0_3_38_BITMASK_O_TCP_SENT_SEQ = 0x0000080000000000, - BNXT_ULP_HF_0_3_38_BITMASK_O_TCP_RECV_ACK = 0x0000040000000000, - BNXT_ULP_HF_0_3_38_BITMASK_O_TCP_DATA_OFF = 0x0000020000000000, - BNXT_ULP_HF_0_3_38_BITMASK_O_TCP_TCP_FLAGS = 0x0000010000000000, - BNXT_ULP_HF_0_3_38_BITMASK_O_TCP_RX_WIN = 0x0000008000000000, - BNXT_ULP_HF_0_3_38_BITMASK_O_TCP_CSUM = 0x0000004000000000, - BNXT_ULP_HF_0_3_38_BITMASK_O_TCP_URP = 0x0000002000000000 -}; - -enum bnxt_ulp_hf_0_3_39_bitmask { - BNXT_ULP_HF_0_3_39_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF_0_3_39_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_3_39_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF_0_3_39_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF_0_3_39_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF_0_3_39_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, - BNXT_ULP_HF_0_3_39_BITMASK_OO_VLAN_VID = 0x0200000000000000, - BNXT_ULP_HF_0_3_39_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_VER = 0x0080000000000000, - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_TC = 0x0040000000000000, - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000, - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000, - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000, - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_TTL = 0x0004000000000000, - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000, - BNXT_ULP_HF_0_3_39_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000, - BNXT_ULP_HF_0_3_39_BITMASK_O_UDP_SRC_PORT = 0x0000800000000000, - BNXT_ULP_HF_0_3_39_BITMASK_O_UDP_DST_PORT = 0x0000400000000000, - BNXT_ULP_HF_0_3_39_BITMASK_O_UDP_LENGTH = 0x0000200000000000, - BNXT_ULP_HF_0_3_39_BITMASK_O_UDP_CSUM = 0x0000100000000000 -}; - -enum bnxt_ulp_hf_0_3_40_bitmask { - BNXT_ULP_HF_0_3_40_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF_0_3_40_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_3_40_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF_0_3_40_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF_0_3_40_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF_0_3_40_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, - BNXT_ULP_HF_0_3_40_BITMASK_OO_VLAN_VID = 0x0200000000000000, - BNXT_ULP_HF_0_3_40_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_VER = 0x0080000000000000, - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_TOS = 0x0040000000000000, - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_LEN = 0x0020000000000000, - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000, - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000, - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_TTL = 0x0004000000000000, - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000, - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_CSUM = 0x0001000000000000, - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000, - BNXT_ULP_HF_0_3_40_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000, - BNXT_ULP_HF_0_3_40_BITMASK_O_UDP_SRC_PORT = 0x0000200000000000, - BNXT_ULP_HF_0_3_40_BITMASK_O_UDP_DST_PORT = 0x0000100000000000, - BNXT_ULP_HF_0_3_40_BITMASK_O_UDP_LENGTH = 0x0000080000000000, - BNXT_ULP_HF_0_3_40_BITMASK_O_UDP_CSUM = 0x0000040000000000 -}; - #endif diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c index 2b29d12cde..f1930ef44d 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c @@ -8,387 +8,1662 @@ #include "ulp_template_struct.h" #include "ulp_template_db_tbl.h" -/* Specifies parameters for the cache and shared tables */ -struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[] = { +const struct bnxt_ulp_generic_tbl_params ulp_wh_plus_generic_tbl_params[] = { [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM << 1 | BNXT_ULP_DIRECTION_INGRESS] = { - .name = "INGRESS GENERIC_TABLE_L2_CNTXT_TCAM", - .result_num_entries = 2048, - .result_num_bytes = 8, - .key_num_bytes = 0, - .num_buckets = 0, - .hash_tbl_entries = 0, - .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + .name = "INGRESS GENERIC_TABLE_L2_CNTXT_TCAM", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_KEY_LIST, + .result_num_entries = 2048, + .result_num_bytes = 9, + .key_num_bytes = 1, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE }, [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM << 1 | BNXT_ULP_DIRECTION_EGRESS] = { - .name = "EGRESS GENERIC_TABLE_L2_CNTXT_TCAM", - .result_num_entries = 2048, - .result_num_bytes = 8, - .key_num_bytes = 0, - .num_buckets = 0, - .hash_tbl_entries = 0, - .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + .name = "EGRESS GENERIC_TABLE_L2_CNTXT_TCAM", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_KEY_LIST, + .result_num_entries = 2048, + .result_num_bytes = 9, + .key_num_bytes = 1, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE }, [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM << 1 | BNXT_ULP_DIRECTION_INGRESS] = { - .name = "INGRESS GENERIC_TABLE_PROFILE_TCAM", - .result_num_entries = 16384, - .result_num_bytes = 18, - .key_num_bytes = 0, - .num_buckets = 0, - .hash_tbl_entries = 0, - .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + .name = "INGRESS GENERIC_TABLE_PROFILE_TCAM", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_KEY_LIST, + .result_num_entries = 32768, + .result_num_bytes = 16, + .key_num_bytes = 2, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE }, [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM << 1 | BNXT_ULP_DIRECTION_EGRESS] = { - .name = "EGRESS GENERIC_TABLE_PROFILE_TCAM", - .result_num_entries = 16384, - .result_num_bytes = 18, - .key_num_bytes = 0, - .num_buckets = 0, - .hash_tbl_entries = 0, - .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + .name = "EGRESS GENERIC_TABLE_PROFILE_TCAM", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_KEY_LIST, + .result_num_entries = 32768, + .result_num_bytes = 16, + .key_num_bytes = 2, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE }, [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR << 1 | BNXT_ULP_DIRECTION_INGRESS] = { - .name = "INGRESS GENERIC_TABLE_SHARED_MIRROR", - .result_num_entries = 16, - .result_num_bytes = 8, - .key_num_bytes = 0, - .num_buckets = 0, - .hash_tbl_entries = 0, - .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + .name = "INGRESS GENERIC_TABLE_SHARED_MIRROR", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_KEY_LIST, + .result_num_entries = 32, + .result_num_bytes = 5, + .key_num_bytes = 1, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE }, [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR << 1 | BNXT_ULP_DIRECTION_EGRESS] = { - .name = "EGRESS GENERIC_TABLE_SHARED_MIRROR", - .result_num_entries = 16, - .result_num_bytes = 8, - .key_num_bytes = 0, - .num_buckets = 0, - .hash_tbl_entries = 0, - .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + .name = "EGRESS GENERIC_TABLE_SHARED_MIRROR", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_KEY_LIST, + .result_num_entries = 32, + .result_num_bytes = 5, + .key_num_bytes = 1, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_MAC_ADDR_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 512, + .result_num_bytes = 9, + .key_num_bytes = 13, + .num_buckets = 8, + .hash_tbl_entries = 2048, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_MAC_ADDR_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 512, + .result_num_bytes = 9, + .key_num_bytes = 13, + .num_buckets = 8, + .hash_tbl_entries = 2048, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_PORT_TABLE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_KEY_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_PORT_TABLE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_KEY_LIST, + .result_num_entries = 1024, + .result_num_bytes = 23, + .key_num_bytes = 1, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_TUNNEL_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 256, + .result_num_bytes = 7, + .key_num_bytes = 3, + .num_buckets = 8, + .hash_tbl_entries = 1024, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_TUNNEL_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_CACHE << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_SOURCE_PROPERTY_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_CACHE << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_SOURCE_PROPERTY_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 4096, + .result_num_bytes = 8, + .key_num_bytes = 18, + .num_buckets = 8, + .hash_tbl_entries = 16384, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOCKET_DIRECT_CACHE << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_SOCKET_DIRECT_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_KEY_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOCKET_DIRECT_CACHE << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_SOCKET_DIRECT_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_KEY_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_IPV6_REC_CACHE << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_VXLAN_ENCAP_IPV6_REC_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_IPV6_REC_CACHE << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_VXLAN_ENCAP_IPV6_REC_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 4096, + .result_num_bytes = 8, + .key_num_bytes = 30, + .num_buckets = 8, + .hash_tbl_entries = 16384, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_IPV6_CACHE << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_SOURCE_PROPERTY_IPV6_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_IPV6_CACHE << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_SOURCE_PROPERTY_IPV6_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_OUTER_TUNNEL_CACHE << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_OUTER_TUNNEL_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_OUTER_TUNNEL_CACHE << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_OUTER_TUNNEL_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_METER_TBL_CACHE << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_SHARED_METER_TBL_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_KEY_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_METER_TBL_CACHE << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_SHARED_METER_TBL_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_KEY_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_METER_PROFILE_TBL_CACHE << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_METER_PROFILE_TBL_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_KEY_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_METER_PROFILE_TBL_CACHE << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_METER_PROFILE_TBL_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_KEY_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_GLOBAL_REGISTER_TBL << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_GLOBAL_REGISTER_TBL", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_GLOBAL_REGISTER_TBL << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_GLOBAL_REGISTER_TBL", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_CHAIN_ID_CACHE << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_CHAIN_ID_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_CHAIN_ID_CACHE << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_CHAIN_ID_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_ENCAP_REC_CACHE << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_L2_ENCAP_REC_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_ENCAP_REC_CACHE << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_L2_ENCAP_REC_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SRV6_ENCAP_REC_CACHE << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_SRV6_ENCAP_REC_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SRV6_ENCAP_REC_CACHE << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_SRV6_ENCAP_REC_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_RSS_PARAMS << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_RSS_PARAMS", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_KEY_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_RSS_PARAMS << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_RSS_PARAMS", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_KEY_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TABLE_SCOPE_CACHE << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_TABLE_SCOPE_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_KEY_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TABLE_SCOPE_CACHE << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_TABLE_SCOPE_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_KEY_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_GENEVE_ENCAP_REC_CACHE << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_GENEVE_ENCAP_REC_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_GENEVE_ENCAP_REC_CACHE << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_GENEVE_ENCAP_REC_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROTO_HEADER << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_PROTO_HEADER", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROTO_HEADER << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_PROTO_HEADER", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_EM_FLOW_CONFLICT << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_EM_FLOW_CONFLICT", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_KEY_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_EM_FLOW_CONFLICT << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_EM_FLOW_CONFLICT", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_KEY_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_HDR_OVERLAP << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_HDR_OVERLAP", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_KEY_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_HDR_OVERLAP << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_HDR_OVERLAP", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_KEY_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, }, [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MULTI_SHARED_MIRROR << 1 | BNXT_ULP_DIRECTION_INGRESS] = { - .name = "INGRESS GENERIC_TABLE_SHARED_MIRROR", - .result_num_entries = 16, - .result_num_bytes = 8, - .key_num_bytes = 0, - .num_buckets = 0, - .hash_tbl_entries = 0, - .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + .name = "INGRESS GENERIC_TABLE_MULTI_SHARED_MIRROR", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_KEY_LIST, + .result_num_entries = 32, + .result_num_bytes = 5, + .key_num_bytes = 1, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE }, [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MULTI_SHARED_MIRROR << 1 | BNXT_ULP_DIRECTION_EGRESS] = { - .name = "EGRESS GENERIC_TABLE_SHARED_MIRROR", - .result_num_entries = 16, - .result_num_bytes = 8, - .key_num_bytes = 0, - .num_buckets = 0, - .hash_tbl_entries = 0, - .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + .name = "EGRESS GENERIC_TABLE_MULTI_SHARED_MIRROR", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_KEY_LIST, + .result_num_entries = 32, + .result_num_bytes = 5, + .key_num_bytes = 1, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + } +}; + +const struct bnxt_ulp_generic_tbl_params ulp_thor_generic_tbl_params[] = { + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_L2_CNTXT_TCAM", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_KEY_LIST, + .result_num_entries = 2048, + .result_num_bytes = 9, + .key_num_bytes = 2, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_L2_CNTXT_TCAM", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_KEY_LIST, + .result_num_entries = 2048, + .result_num_bytes = 9, + .key_num_bytes = 2, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_PROFILE_TCAM", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_KEY_LIST, + .result_num_entries = 32768, + .result_num_bytes = 18, + .key_num_bytes = 2, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_PROFILE_TCAM", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_KEY_LIST, + .result_num_entries = 32768, + .result_num_bytes = 18, + .key_num_bytes = 2, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_SHARED_MIRROR", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_KEY_LIST, + .result_num_entries = 32, + .result_num_bytes = 5, + .key_num_bytes = 1, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_SHARED_MIRROR", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_KEY_LIST, + .result_num_entries = 32, + .result_num_bytes = 5, + .key_num_bytes = 1, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE }, [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE << 1 | BNXT_ULP_DIRECTION_INGRESS] = { - .name = "INGRESS GENERIC_TABLE_MAC_ADDR_CACHE", - .result_num_entries = 512, - .result_num_bytes = 8, - .key_num_bytes = 12, - .num_buckets = 8, - .hash_tbl_entries = 2048, - .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + .name = "INGRESS GENERIC_TABLE_MAC_ADDR_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 512, + .result_num_bytes = 9, + .key_num_bytes = 14, + .num_buckets = 8, + .hash_tbl_entries = 2048, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE }, [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE << 1 | BNXT_ULP_DIRECTION_EGRESS] = { - .name = "EGRESS GENERIC_TABLE_MAC_ADDR_CACHE", - .result_num_entries = 512, - .result_num_bytes = 8, - .key_num_bytes = 12, - .num_buckets = 8, - .hash_tbl_entries = 2048, - .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + .name = "EGRESS GENERIC_TABLE_MAC_ADDR_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, }, [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE << 1 | BNXT_ULP_DIRECTION_INGRESS] = { - .name = "INGRESS GENERIC_TABLE_PORT_TABLE", - .result_num_entries = 1024, - .result_num_bytes = 25, - .key_num_bytes = 0, - .num_buckets = 0, - .hash_tbl_entries = 0, - .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + .name = "INGRESS GENERIC_TABLE_PORT_TABLE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_KEY_LIST, + .result_num_entries = 1024, + .result_num_bytes = 23, + .key_num_bytes = 2, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE }, [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE << 1 | BNXT_ULP_DIRECTION_EGRESS] = { - .name = "EGRESS GENERIC_TABLE_PORT_TABLE", - .result_num_entries = 1024, - .result_num_bytes = 25, - .key_num_bytes = 0, - .num_buckets = 0, - .hash_tbl_entries = 0, - .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + .name = "EGRESS GENERIC_TABLE_PORT_TABLE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_KEY_LIST, + .result_num_entries = 1024, + .result_num_bytes = 23, + .key_num_bytes = 2, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE }, [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE << 1 | BNXT_ULP_DIRECTION_INGRESS] = { - .name = "INGRESS GENERIC_TABLE_TUNNEL_CACHE", - .result_num_entries = 256, - .result_num_bytes = 7, - .key_num_bytes = 3, - .num_buckets = 8, - .hash_tbl_entries = 1024, - .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + .name = "INGRESS GENERIC_TABLE_TUNNEL_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 256, + .result_num_bytes = 7, + .key_num_bytes = 3, + .num_buckets = 8, + .hash_tbl_entries = 1024, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE }, [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE << 1 | BNXT_ULP_DIRECTION_EGRESS] = { - .name = "EGRESS GENERIC_TABLE_TUNNEL_CACHE", - .result_num_entries = 256, - .result_num_bytes = 7, - .key_num_bytes = 3, - .num_buckets = 8, - .hash_tbl_entries = 1024, - .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + .name = "EGRESS GENERIC_TABLE_TUNNEL_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, }, [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_CACHE << 1 | BNXT_ULP_DIRECTION_INGRESS] = { - .name = "INGRESS GEN_TABLE_SOURCE_PROPERTY_CACHE", - .result_num_entries = 4096, - .result_num_bytes = 6, - .key_num_bytes = 10, - .num_buckets = 4, - .hash_tbl_entries = 8192, - .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + .name = "INGRESS GENERIC_TABLE_SOURCE_PROPERTY_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, }, [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_CACHE << 1 | - BNXT_ULP_DIRECTION_EGRESS] = { - .name = "EGRESS GEN_TABLE_SOURCE_PROPERTY_CACHE", - .result_num_entries = 128, - .result_num_bytes = 6, - .key_num_bytes = 10, - .num_buckets = 4, - .hash_tbl_entries = 512, - .result_byte_order = BNXT_ULP_BYTE_ORDER_LE - }, - [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_ENCAP_REC_CACHE << 1 | - BNXT_ULP_DIRECTION_INGRESS] = { - .name = "INGRESS GEN_TABLE_L2_ENCAP_REC_CACHE", - .result_num_entries = 4096, - .result_num_bytes = 6, - .key_num_bytes = 14, - .num_buckets = 4, - .hash_tbl_entries = 8192, - .result_byte_order = BNXT_ULP_BYTE_ORDER_LE - }, - [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_ENCAP_REC_CACHE << 1 | BNXT_ULP_DIRECTION_EGRESS] = { - .name = "EGRESS GEN_TABLE_L2_ENCAP_REC_CACHE", - .result_num_entries = 0, - .result_num_bytes = 6, - .key_num_bytes = 14, - .num_buckets = 4, - .hash_tbl_entries = 0, - .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + .name = "EGRESS GENERIC_TABLE_SOURCE_PROPERTY_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 128, + .result_num_bytes = 8, + .key_num_bytes = 11, + .num_buckets = 4, + .hash_tbl_entries = 512, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE }, [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE << 1 | BNXT_ULP_DIRECTION_INGRESS] = { - .name = "INGRESS GEN_TABLE_VXLAN_ENCAP_REC_CACHE", - .result_num_entries = 0, - .result_num_bytes = 6, - .key_num_bytes = 17, - .num_buckets = 8, - .hash_tbl_entries = 0, - .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + .name = "INGRESS GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, }, [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE << 1 | BNXT_ULP_DIRECTION_EGRESS] = { - .name = "EGRESS GEN_TABLE_VXLAN_ENCAP_REC_CACHE", - .result_num_entries = 4096, - .result_num_bytes = 6, - .key_num_bytes = 17, - .num_buckets = 8, - .hash_tbl_entries = 16384, - .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + .name = "EGRESS GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 4096, + .result_num_bytes = 8, + .key_num_bytes = 18, + .num_buckets = 8, + .hash_tbl_entries = 16384, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE }, [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOCKET_DIRECT_CACHE << 1 | BNXT_ULP_DIRECTION_INGRESS] = { - .name = "INGRESS GEN_TABLE_SOCKET_DIRECT_CACHE", - .result_num_entries = 16, - .result_num_bytes = 14, - .key_num_bytes = 0, - .num_buckets = 0, - .hash_tbl_entries = 0, - .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + .name = "INGRESS GENERIC_TABLE_SOCKET_DIRECT_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_KEY_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, }, [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOCKET_DIRECT_CACHE << 1 | BNXT_ULP_DIRECTION_EGRESS] = { - .name = "EGRESS GEN_TABLE_SOCKET_DIRECT_CACHE", - .result_num_entries = 16, - .result_num_bytes = 14, - .key_num_bytes = 0, - .num_buckets = 0, - .hash_tbl_entries = 0, - .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + .name = "EGRESS GENERIC_TABLE_SOCKET_DIRECT_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_KEY_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_IPV6_REC_CACHE << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_VXLAN_ENCAP_IPV6_REC_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_IPV6_REC_CACHE << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_VXLAN_ENCAP_IPV6_REC_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 4096, + .result_num_bytes = 8, + .key_num_bytes = 30, + .num_buckets = 8, + .hash_tbl_entries = 16384, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE }, [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_IPV6_CACHE << 1 | BNXT_ULP_DIRECTION_INGRESS] = { - .name = "INGRESS GEN_TABLE_SOURCE_PROPERTY_IPV6_CACHE", - .result_num_entries = 0, - .result_num_bytes = 6, - .key_num_bytes = 22, - .num_buckets = 4, - .hash_tbl_entries = 0, - .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + .name = "INGRESS GENERIC_TABLE_SOURCE_PROPERTY_IPV6_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, }, [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_IPV6_CACHE << 1 | - BNXT_ULP_DIRECTION_EGRESS] = { - .name = "EGRESS GEN_TABLE_SOURCE_PROPERTY_IPV6_CACHE", - .result_num_entries = 2048, - .result_num_bytes = 6, - .key_num_bytes = 22, - .num_buckets = 4, - .hash_tbl_entries = 8192, - .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_SOURCE_PROPERTY_IPV6_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 2048, + .result_num_bytes = 6, + .key_num_bytes = 22, + .num_buckets = 4, + .hash_tbl_entries = 8192, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE }, - [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_IPV6_REC_CACHE << 1 | + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_OUTER_TUNNEL_CACHE << 1 | BNXT_ULP_DIRECTION_INGRESS] = { - .name = "INGRESS GEN_TABLE_VXLAN_ENCAP_IPV6_REC_CACHE", - .result_num_entries = 0, - .result_num_bytes = 6, - .key_num_bytes = 29, - .num_buckets = 8, - .hash_tbl_entries = 0, - .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + .name = "INGRESS GENERIC_TABLE_OUTER_TUNNEL_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, }, - [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_IPV6_REC_CACHE << 1 | + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_OUTER_TUNNEL_CACHE << 1 | BNXT_ULP_DIRECTION_EGRESS] = { - .name = "EGRESS GEN_TABLE_VXLAN_ENCAP_IPV6_REC_CACHE", - .result_num_entries = 4096, - .result_num_bytes = 6, - .key_num_bytes = 29, - .num_buckets = 8, - .hash_tbl_entries = 16384, - .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + .name = "EGRESS GENERIC_TABLE_OUTER_TUNNEL_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_METER_TBL_CACHE << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_SHARED_METER_TBL_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 1024, + .result_num_bytes = 10, + .key_num_bytes = 4, + .num_buckets = 8, + .hash_tbl_entries = 2048, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_METER_TBL_CACHE << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_SHARED_METER_TBL_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_METER_PROFILE_TBL_CACHE << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_METER_PROFILE_TBL_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 512, + .result_num_bytes = 6, + .key_num_bytes = 4, + .num_buckets = 8, + .hash_tbl_entries = 2048, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_METER_PROFILE_TBL_CACHE << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_METER_PROFILE_TBL_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_GLOBAL_REGISTER_TBL << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_GLOBAL_REGISTER_TBL", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_GLOBAL_REGISTER_TBL << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_GLOBAL_REGISTER_TBL", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_CHAIN_ID_CACHE << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_CHAIN_ID_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_CHAIN_ID_CACHE << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_CHAIN_ID_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_ENCAP_REC_CACHE << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_L2_ENCAP_REC_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_ENCAP_REC_CACHE << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_L2_ENCAP_REC_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, }, [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SRV6_ENCAP_REC_CACHE << 1 | BNXT_ULP_DIRECTION_INGRESS] = { - .name = "INGRESS GEN_TABLE_SRV6_ENCAP_REC_CACHE", - .result_num_entries = 0, - .result_num_bytes = 6, - .key_num_bytes = 29, - .num_buckets = 8, - .hash_tbl_entries = 0, - .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + .name = "INGRESS GENERIC_TABLE_SRV6_ENCAP_REC_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, }, [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SRV6_ENCAP_REC_CACHE << 1 | BNXT_ULP_DIRECTION_EGRESS] = { - .name = "EGRESS GEN_TABLE_SRV6_ENCAP_REC_CACHE", - .result_num_entries = 2048, - .result_num_bytes = 6, - .key_num_bytes = 86, - .num_buckets = 4, - .hash_tbl_entries = 8192, - .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + .name = "EGRESS GENERIC_TABLE_SRV6_ENCAP_REC_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_RSS_PARAMS << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_RSS_PARAMS", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_KEY_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_RSS_PARAMS << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_RSS_PARAMS", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_KEY_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TABLE_SCOPE_CACHE << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_TABLE_SCOPE_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_KEY_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TABLE_SCOPE_CACHE << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_TABLE_SCOPE_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_KEY_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_GENEVE_ENCAP_REC_CACHE << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_GENEVE_ENCAP_REC_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_GENEVE_ENCAP_REC_CACHE << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_GENEVE_ENCAP_REC_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 4096, + .result_num_bytes = 8, + .key_num_bytes = 62, + .num_buckets = 8, + .hash_tbl_entries = 16384, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROTO_HEADER << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_PROTO_HEADER", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 256, + .result_num_bytes = 10, + .key_num_bytes = 10, + .num_buckets = 4, + .hash_tbl_entries = 1024, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROTO_HEADER << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_PROTO_HEADER", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 256, + .result_num_bytes = 10, + .key_num_bytes = 10, + .num_buckets = 4, + .hash_tbl_entries = 1024, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_EM_FLOW_CONFLICT << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_EM_FLOW_CONFLICT", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 256, + .result_num_bytes = 12, + .key_num_bytes = 10, + .num_buckets = 4, + .hash_tbl_entries = 1024, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_EM_FLOW_CONFLICT << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_EM_FLOW_CONFLICT", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 256, + .result_num_bytes = 12, + .key_num_bytes = 10, + .num_buckets = 4, + .hash_tbl_entries = 1024, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_HDR_OVERLAP << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_HDR_OVERLAP", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_SIMPLE_LIST, + .result_num_entries = 256, + .result_num_bytes = 12, + .key_num_bytes = 2, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_HDR_OVERLAP << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_HDR_OVERLAP", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_SIMPLE_LIST, + .result_num_entries = 256, + .result_num_bytes = 12, + .key_num_bytes = 2, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE }, - [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_OUTER_TUNNEL_CACHE << 1 | + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MULTI_SHARED_MIRROR << 1 | BNXT_ULP_DIRECTION_INGRESS] = { - .name = "INGRESS GEN_TABLE_OUTER_TUNNEL_CACHE", - .result_num_entries = 4096, - .result_num_bytes = 4, - .key_num_bytes = 32, - .num_buckets = 4, - .hash_tbl_entries = 16384, - .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + .name = "INGRESS GENERIC_TABLE_MULTI_SHARED_MIRROR", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_KEY_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, }, - [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_OUTER_TUNNEL_CACHE << 1 | + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MULTI_SHARED_MIRROR << 1 | BNXT_ULP_DIRECTION_EGRESS] = { - .name = "EGRESS GEN_TABLE_OUTER_TUNNEL_CACHE", - .result_num_entries = 0, - .result_num_bytes = 4, - .key_num_bytes = 32, - .num_buckets = 8, - .hash_tbl_entries = 0, - .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + .name = "EGRESS GENERIC_TABLE_MULTI_SHARED_MIRROR", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_KEY_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + } +}; + +const struct bnxt_ulp_generic_tbl_params ulp_thor2_generic_tbl_params[] = { + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_L2_CNTXT_TCAM", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_KEY_LIST, + .result_num_entries = 2048, + .result_num_bytes = 12, + .key_num_bytes = 2, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE }, - [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_METER_PROFILE_TBL_CACHE << 1 | + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_L2_CNTXT_TCAM", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_KEY_LIST, + .result_num_entries = 2048, + .result_num_bytes = 12, + .key_num_bytes = 2, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM << 1 | BNXT_ULP_DIRECTION_INGRESS] = { - .name = "INGRESS GENERIC_TABLE_METER_PROFILE_TBL_CACHE", - .result_num_entries = 512, - .result_num_bytes = 8, - .key_num_bytes = 4, - .num_buckets = 8, - .hash_tbl_entries = 2048, - .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + .name = "INGRESS GENERIC_TABLE_PROFILE_TCAM", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_KEY_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, }, - [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_METER_PROFILE_TBL_CACHE << 1 | + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_PROFILE_TCAM", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_KEY_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_SHARED_MIRROR", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_KEY_LIST, + .result_num_entries = 32, + .result_num_bytes = 5, + .key_num_bytes = 1, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_SHARED_MIRROR", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_KEY_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_MAC_ADDR_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 512, + .result_num_bytes = 12, + .key_num_bytes = 17, + .num_buckets = 8, + .hash_tbl_entries = 2048, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_MAC_ADDR_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_PORT_TABLE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_KEY_LIST, + .result_num_entries = 1024, + .result_num_bytes = 22, + .key_num_bytes = 2, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_PORT_TABLE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_KEY_LIST, + .result_num_entries = 1024, + .result_num_bytes = 22, + .key_num_bytes = 2, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_TUNNEL_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 256, + .result_num_bytes = 7, + .key_num_bytes = 3, + .num_buckets = 8, + .hash_tbl_entries = 1024, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_TUNNEL_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_CACHE << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_SOURCE_PROPERTY_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_CACHE << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_SOURCE_PROPERTY_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 128, + .result_num_bytes = 8, + .key_num_bytes = 11, + .num_buckets = 4, + .hash_tbl_entries = 512, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 4096, + .result_num_bytes = 8, + .key_num_bytes = 18, + .num_buckets = 8, + .hash_tbl_entries = 16384, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOCKET_DIRECT_CACHE << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_SOCKET_DIRECT_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_KEY_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOCKET_DIRECT_CACHE << 1 | BNXT_ULP_DIRECTION_EGRESS] = { - .name = "EGRESS GENERIC_TABLE_METER_PROFILE_TBL_CACHE", - .result_num_entries = 512, - .result_num_bytes = 8, - .key_num_bytes = 4, - .num_buckets = 8, - .hash_tbl_entries = 2048, - .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + .name = "EGRESS GENERIC_TABLE_SOCKET_DIRECT_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_KEY_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_IPV6_REC_CACHE << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_VXLAN_ENCAP_IPV6_REC_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_IPV6_REC_CACHE << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_VXLAN_ENCAP_IPV6_REC_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_IPV6_CACHE << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_SOURCE_PROPERTY_IPV6_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_IPV6_CACHE << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_SOURCE_PROPERTY_IPV6_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_OUTER_TUNNEL_CACHE << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_OUTER_TUNNEL_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_OUTER_TUNNEL_CACHE << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_OUTER_TUNNEL_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, }, [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_METER_TBL_CACHE << 1 | BNXT_ULP_DIRECTION_INGRESS] = { - .name = "INGRESS GENERIC_TABLE_SHARED_METER_TBL_CACHE", - .result_num_entries = 1024, - .result_num_bytes = 10, - .key_num_bytes = 4, - .num_buckets = 8, - .hash_tbl_entries = 2048, - .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + .name = "INGRESS GENERIC_TABLE_SHARED_METER_TBL_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, }, [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_METER_TBL_CACHE << 1 | BNXT_ULP_DIRECTION_EGRESS] = { - .name = "EGRESS GENERIC_TABLE_SHARED_METER_TBL_CACHE", - .result_num_entries = 1024, - .result_num_bytes = 10, - .key_num_bytes = 4, - .num_buckets = 8, - .hash_tbl_entries = 2048, - .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + .name = "EGRESS GENERIC_TABLE_SHARED_METER_TBL_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_METER_PROFILE_TBL_CACHE << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_METER_PROFILE_TBL_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_METER_PROFILE_TBL_CACHE << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_METER_PROFILE_TBL_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, }, [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_GLOBAL_REGISTER_TBL << 1 | BNXT_ULP_DIRECTION_INGRESS] = { - .name = "INGRESS GENERIC_TABLE_GLOBAL_REGISTER_TBL", - .result_num_entries = 256, - .result_num_bytes = 8, - .key_num_bytes = 3, - .num_buckets = 4, - .hash_tbl_entries = 1024, - .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + .name = "INGRESS GENERIC_TABLE_GLOBAL_REGISTER_TBL", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, }, [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_GLOBAL_REGISTER_TBL << 1 | BNXT_ULP_DIRECTION_EGRESS] = { - .name = "EGRESS GENERIC_TABLE_GLOBAL_REGISTER_TBL", - .result_num_entries = 0, - .result_num_bytes = 8, - .key_num_bytes = 3, - .num_buckets = 0, - .hash_tbl_entries = 0, - .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + .name = "EGRESS GENERIC_TABLE_GLOBAL_REGISTER_TBL", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, }, [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_CHAIN_ID_CACHE << 1 | BNXT_ULP_DIRECTION_INGRESS] = { - .name = "INGRESS GEN_TABLE_CHAIN_ID_CACHE", - .result_num_entries = 0, - .result_num_bytes = 4, - .key_num_bytes = 4, - .num_buckets = 4, - .hash_tbl_entries = 0, - .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + .name = "INGRESS GENERIC_TABLE_CHAIN_ID_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, }, [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_CHAIN_ID_CACHE << 1 | BNXT_ULP_DIRECTION_EGRESS] = { - .name = "EGRESS GEN_TABLE_CHAIN_ID_CACHE", - .result_num_entries = 64, - .result_num_bytes = 4, - .key_num_bytes = 4, - .num_buckets = 4, - .hash_tbl_entries = 256, - .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + .name = "EGRESS GENERIC_TABLE_CHAIN_ID_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_ENCAP_REC_CACHE << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_L2_ENCAP_REC_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_ENCAP_REC_CACHE << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_L2_ENCAP_REC_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SRV6_ENCAP_REC_CACHE << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_SRV6_ENCAP_REC_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SRV6_ENCAP_REC_CACHE << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_SRV6_ENCAP_REC_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_RSS_PARAMS << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_RSS_PARAMS", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_KEY_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_RSS_PARAMS << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_RSS_PARAMS", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_KEY_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TABLE_SCOPE_CACHE << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_TABLE_SCOPE_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_KEY_LIST, + .result_num_entries = 64, + .result_num_bytes = 11, + .key_num_bytes = 1, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TABLE_SCOPE_CACHE << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_TABLE_SCOPE_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_KEY_LIST, + .result_num_entries = 64, + .result_num_bytes = 11, + .key_num_bytes = 1, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_GENEVE_ENCAP_REC_CACHE << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_GENEVE_ENCAP_REC_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_GENEVE_ENCAP_REC_CACHE << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_GENEVE_ENCAP_REC_CACHE", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 4096, + .result_num_bytes = 8, + .key_num_bytes = 62, + .num_buckets = 8, + .hash_tbl_entries = 16384, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROTO_HEADER << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_PROTO_HEADER", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 256, + .result_num_bytes = 10, + .key_num_bytes = 10, + .num_buckets = 4, + .hash_tbl_entries = 1024, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROTO_HEADER << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_PROTO_HEADER", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 256, + .result_num_bytes = 10, + .key_num_bytes = 10, + .num_buckets = 4, + .hash_tbl_entries = 1024, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_EM_FLOW_CONFLICT << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_EM_FLOW_CONFLICT", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 256, + .result_num_bytes = 12, + .key_num_bytes = 10, + .num_buckets = 4, + .hash_tbl_entries = 1024, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_EM_FLOW_CONFLICT << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_EM_FLOW_CONFLICT", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_HASH_LIST, + .result_num_entries = 256, + .result_num_bytes = 12, + .key_num_bytes = 10, + .num_buckets = 4, + .hash_tbl_entries = 1024, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_HDR_OVERLAP << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_HDR_OVERLAP", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_SIMPLE_LIST, + .result_num_entries = 256, + .result_num_bytes = 12, + .key_num_bytes = 2, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_HDR_OVERLAP << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_HDR_OVERLAP", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_SIMPLE_LIST, + .result_num_entries = 256, + .result_num_bytes = 12, + .key_num_bytes = 2, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MULTI_SHARED_MIRROR << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_MULTI_SHARED_MIRROR", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_KEY_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MULTI_SHARED_MIRROR << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_MULTI_SHARED_MIRROR", + .gen_tbl_type = BNXT_ULP_GEN_TBL_TYPE_KEY_LIST, + .result_num_entries = 0, + .result_num_bytes = 0, + .key_num_bytes = 0, + .num_buckets = 0, + .hash_tbl_entries = 0, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, } }; @@ -401,12 +1676,16 @@ const struct bnxt_ulp_template_device_tbls ulp_template_wh_plus_tbls[] = { .tbl_list_size = ULP_WH_PLUS_CLASS_TBL_LIST_SIZE, .key_info_list = ulp_wh_plus_class_key_info_list, .key_info_list_size = ULP_WH_PLUS_CLASS_KEY_INFO_LIST_SIZE, + .key_ext_list = ulp_wh_plus_class_key_ext_list, + .key_ext_list_size = ULP_WH_PLUS_CLASS_KEY_EXT_LIST_SIZE, .ident_list = ulp_wh_plus_class_ident_list, .ident_list_size = ULP_WH_PLUS_CLASS_IDENT_LIST_SIZE, .cond_list = ulp_wh_plus_class_cond_list, .cond_list_size = ULP_WH_PLUS_CLASS_COND_LIST_SIZE, .result_field_list = ulp_wh_plus_class_result_field_list, - .result_field_list_size = ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE + .result_field_list_size = ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE, + .cond_oper_list = ulp_wh_plus_class_cond_oper_list, + .cond_oper_list_size = ULP_WH_PLUS_CLASS_COND_OPER_LIST_SIZE }, [BNXT_ULP_TEMPLATE_TYPE_ACTION] = { .tmpl_list = ulp_wh_plus_act_tmpl_list, @@ -420,7 +1699,9 @@ const struct bnxt_ulp_template_device_tbls ulp_template_wh_plus_tbls[] = { .cond_list = ulp_wh_plus_act_cond_list, .cond_list_size = ULP_WH_PLUS_ACT_COND_LIST_SIZE, .result_field_list = ulp_wh_plus_act_result_field_list, - .result_field_list_size = ULP_WH_PLUS_ACT_RESULT_FIELD_LIST_SIZE + .result_field_list_size = ULP_WH_PLUS_ACT_RESULT_FIELD_LIST_SIZE, + .cond_oper_list = ulp_wh_plus_act_cond_oper_list, + .cond_oper_list_size = ULP_WH_PLUS_ACT_COND_OPER_LIST_SIZE } }; @@ -433,12 +1714,16 @@ const struct bnxt_ulp_template_device_tbls ulp_template_thor_tbls[] = { .tbl_list_size = ULP_THOR_CLASS_TBL_LIST_SIZE, .key_info_list = ulp_thor_class_key_info_list, .key_info_list_size = ULP_THOR_CLASS_KEY_INFO_LIST_SIZE, + .key_ext_list = ulp_thor_class_key_ext_list, + .key_ext_list_size = ULP_THOR_CLASS_KEY_EXT_LIST_SIZE, .ident_list = ulp_thor_class_ident_list, .ident_list_size = ULP_THOR_CLASS_IDENT_LIST_SIZE, .cond_list = ulp_thor_class_cond_list, .cond_list_size = ULP_THOR_CLASS_COND_LIST_SIZE, .result_field_list = ulp_thor_class_result_field_list, - .result_field_list_size = ULP_THOR_CLASS_RESULT_FIELD_LIST_SIZE + .result_field_list_size = ULP_THOR_CLASS_RESULT_FIELD_LIST_SIZE, + .cond_oper_list = ulp_thor_class_cond_oper_list, + .cond_oper_list_size = ULP_THOR_CLASS_COND_OPER_LIST_SIZE }, [BNXT_ULP_TEMPLATE_TYPE_ACTION] = { .tmpl_list = ulp_thor_act_tmpl_list, @@ -452,7 +1737,47 @@ const struct bnxt_ulp_template_device_tbls ulp_template_thor_tbls[] = { .cond_list = ulp_thor_act_cond_list, .cond_list_size = ULP_THOR_ACT_COND_LIST_SIZE, .result_field_list = ulp_thor_act_result_field_list, - .result_field_list_size = ULP_THOR_ACT_RESULT_FIELD_LIST_SIZE + .result_field_list_size = ULP_THOR_ACT_RESULT_FIELD_LIST_SIZE, + .cond_oper_list = ulp_thor_act_cond_oper_list, + .cond_oper_list_size = ULP_THOR_ACT_COND_OPER_LIST_SIZE + } +}; + +/* device tables */ +const struct bnxt_ulp_template_device_tbls ulp_template_thor2_tbls[] = { + [BNXT_ULP_TEMPLATE_TYPE_CLASS] = { + .tmpl_list = ulp_thor2_class_tmpl_list, + .tmpl_list_size = ULP_THOR2_CLASS_TMPL_LIST_SIZE, + .tbl_list = ulp_thor2_class_tbl_list, + .tbl_list_size = ULP_THOR2_CLASS_TBL_LIST_SIZE, + .key_info_list = ulp_thor2_class_key_info_list, + .key_info_list_size = ULP_THOR2_CLASS_KEY_INFO_LIST_SIZE, + .key_ext_list = ulp_thor2_class_key_ext_list, + .key_ext_list_size = ULP_THOR2_CLASS_KEY_EXT_LIST_SIZE, + .ident_list = ulp_thor2_class_ident_list, + .ident_list_size = ULP_THOR2_CLASS_IDENT_LIST_SIZE, + .cond_list = ulp_thor2_class_cond_list, + .cond_list_size = ULP_THOR2_CLASS_COND_LIST_SIZE, + .result_field_list = ulp_thor2_class_result_field_list, + .result_field_list_size = ULP_THOR2_CLASS_RESULT_FIELD_LIST_SIZE, + .cond_oper_list = ulp_thor2_class_cond_oper_list, + .cond_oper_list_size = ULP_THOR2_CLASS_COND_OPER_LIST_SIZE + }, + [BNXT_ULP_TEMPLATE_TYPE_ACTION] = { + .tmpl_list = ulp_thor2_act_tmpl_list, + .tmpl_list_size = ULP_THOR2_ACT_TMPL_LIST_SIZE, + .tbl_list = ulp_thor2_act_tbl_list, + .tbl_list_size = ULP_THOR2_ACT_TBL_LIST_SIZE, + .key_info_list = ulp_thor2_act_key_info_list, + .key_info_list_size = ULP_THOR2_ACT_KEY_INFO_LIST_SIZE, + .ident_list = ulp_thor2_act_ident_list, + .ident_list_size = ULP_THOR2_ACT_IDENT_LIST_SIZE, + .cond_list = ulp_thor2_act_cond_list, + .cond_list_size = ULP_THOR2_ACT_COND_LIST_SIZE, + .result_field_list = ulp_thor2_act_result_field_list, + .result_field_list_size = ULP_THOR2_ACT_RESULT_FIELD_LIST_SIZE, + .cond_oper_list = ulp_thor2_act_cond_oper_list, + .cond_oper_list_size = ULP_THOR2_ACT_COND_OPER_LIST_SIZE } }; @@ -488,6 +1813,7 @@ struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = { 0x00000003, 0x00000003}, .wc_mod_list_max_size = 4, .wc_ctl_size_bits = 16, + .gen_tbl_params = ulp_wh_plus_generic_tbl_params, .dev_tbls = ulp_template_wh_plus_tbls }, [BNXT_ULP_DEVICE_ID_THOR] = { @@ -534,7 +1860,54 @@ struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = { 0x0000000f, 0x0000000f}, .wc_mod_list_max_size = 4, .wc_ctl_size_bits = 32, + .gen_tbl_params = ulp_thor_generic_tbl_params, .dev_tbls = ulp_template_thor_tbls + }, + [BNXT_ULP_DEVICE_ID_THOR2] = { + .description = "Thor2", + .key_byte_order = BNXT_ULP_BYTE_ORDER_LE, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE, + .encap_byte_order = BNXT_ULP_BYTE_ORDER_BE, + .wc_key_byte_order = BNXT_ULP_BYTE_ORDER_BE, + .em_byte_order = BNXT_ULP_BYTE_ORDER_BE, + .encap_byte_swap = 1, + .int_flow_db_num_entries = 16384, + .ext_flow_db_num_entries = 32768, + .mark_db_lfid_entries = 65536, + .mark_db_gfid_entries = 65536, + .flow_count_db_entries = 16384, + .fdb_parent_flow_entries = 2, + .num_resources_per_flow = 8, + .num_phy_ports = 2, + .ext_cntr_table_type = 0, + .byte_count_mask = 0x00000007ffffffff, + .packet_count_mask = 0xfffffff800000000, + .byte_count_shift = 0, + .packet_count_shift = 35, + .wc_dynamic_pad_en = 1, + .em_dynamic_pad_en = 1, + .dynamic_sram_en = 1, + .dyn_encap_list_size = 4, + .dyn_encap_sizes = {{64, TF_TBL_TYPE_ACT_ENCAP_8B}, + {128, TF_TBL_TYPE_ACT_ENCAP_16B}, + {256, TF_TBL_TYPE_ACT_ENCAP_32B}, + {512, TF_TBL_TYPE_ACT_ENCAP_64B}}, + .dyn_modify_list_size = 4, + .dyn_modify_sizes = {{64, TF_TBL_TYPE_ACT_MODIFY_8B}, + {128, TF_TBL_TYPE_ACT_MODIFY_16B}, + {256, TF_TBL_TYPE_ACT_MODIFY_32B}, + {512, TF_TBL_TYPE_ACT_MODIFY_64B}}, + .em_blk_size_bits = 256, + .em_blk_align_bits = 128, + .em_key_align_bytes = 16, + .wc_slice_width = 172, + .wc_max_slices = 4, + .wc_mode_list = {0x00000004, 0x00000005, + 0x00000000, 0x00000006}, + .wc_mod_list_max_size = 4, + .wc_ctl_size_bits = 3, + .gen_tbl_params = ulp_thor2_generic_tbl_params, + .dev_tbls = ulp_template_thor2_tbls } }; @@ -566,7 +1939,26 @@ struct bnxt_ulp_app_capabilities_info ulp_app_cap_info_list[] = { .flags = 0, .default_priority = 0, .vxlan_port = 0, - .vxlan_ip_port = 0 + .vxlan_ip_port = 0, + .num_key_recipes_per_dir = 64 + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR2, + .flags = 0, + .default_priority = 0, + .vxlan_port = 0, + .vxlan_ip_port = 0, + .max_pools = 1, + .em_multiplier = 1, + .num_rx_flows = 2048, + .num_tx_flows = 2048, + .act_rx_max_sz = 128, + .act_tx_max_sz = 128, + .em_rx_key_max_sz = 16, + .em_tx_key_max_sz = 16, + .pbl_page_sz_in_bytes = 4096, + .num_key_recipes_per_dir = 128 } }; @@ -1036,6 +2428,60 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { .resource_type = TF_TBL_TYPE_EM_FKB, .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_1, .direction = TF_DIR_RX + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR2, + .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = CFA_RSUBTYPE_IDX_TBL_METADATA_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_METADATA_RX_PROF_0, + .direction = TF_DIR_RX + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR2, + .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = CFA_RSUBTYPE_IDX_TBL_METADATA_LKUP, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_METADATA_RX_LKUP_0, + .direction = TF_DIR_RX + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR2, + .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = CFA_RSUBTYPE_IDX_TBL_METADATA_ACT, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_METADATA_RX_ACT_0, + .direction = TF_DIR_RX + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR2, + .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = CFA_RSUBTYPE_IDX_TBL_METADATA_PROF, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_METADATA_TX_PROF_0, + .direction = TF_DIR_TX + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR2, + .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = CFA_RSUBTYPE_IDX_TBL_METADATA_LKUP, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_METADATA_TX_LKUP_0, + .direction = TF_DIR_TX + }, + { + .app_id = 0, + .device_id = BNXT_ULP_DEVICE_ID_THOR2, + .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT, + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = CFA_RSUBTYPE_IDX_TBL_METADATA_ACT, + .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_METADATA_TX_ACT_0, + .direction = TF_DIR_TX } }; @@ -1785,6 +3231,8 @@ uint32_t ulp_act_prop_map_table[] = { BNXT_ULP_ACT_PROP_SZ_JUMP, [BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE] = BNXT_ULP_ACT_PROP_SZ_SHARED_HANDLE, + [BNXT_ULP_ACT_PROP_IDX_RSS_FUNC] = + BNXT_ULP_ACT_PROP_SZ_RSS_FUNC, [BNXT_ULP_ACT_PROP_IDX_RSS_TYPES] = BNXT_ULP_ACT_PROP_SZ_RSS_TYPES, [BNXT_ULP_ACT_PROP_IDX_RSS_LEVEL] = @@ -1837,1054 +3285,9 @@ uint32_t ulp_act_prop_map_table[] = { BNXT_ULP_ACT_PROP_SZ_METER_INST_MTR_VAL, [BNXT_ULP_ACT_PROP_IDX_GOTO_CHAINID] = BNXT_ULP_ACT_PROP_SZ_GOTO_CHAINID, + [BNXT_ULP_ACT_PROP_IDX_SET_TTL] = + BNXT_ULP_ACT_PROP_SZ_SET_TTL, [BNXT_ULP_ACT_PROP_IDX_LAST] = BNXT_ULP_ACT_PROP_SZ_LAST }; -uint8_t ulp_glb_field_tbl[] = { - [8192] = 0, - [8193] = 1, - [8198] = 2, - [8200] = 3, - [8202] = 4, - [8236] = 5, - [8238] = 6, - [8240] = 7, - [8242] = 8, - [8244] = 9, - [8246] = 10, - [8248] = 11, - [8250] = 12, - [8320] = 0, - [8321] = 1, - [8326] = 2, - [8328] = 3, - [8330] = 4, - [8344] = 5, - [8346] = 6, - [8348] = 7, - [8350] = 8, - [8352] = 9, - [8354] = 10, - [8356] = 11, - [8358] = 12, - [8360] = 13, - [8362] = 14, - [8448] = 0, - [8449] = 1, - [8454] = 2, - [8456] = 3, - [8458] = 4, - [8492] = 8, - [8494] = 9, - [8496] = 10, - [8498] = 11, - [8500] = 12, - [8502] = 13, - [8504] = 14, - [8506] = 15, - [8548] = 5, - [8552] = 6, - [8556] = 7, - [8576] = 0, - [8577] = 1, - [8582] = 2, - [8584] = 3, - [8586] = 4, - [8600] = 8, - [8602] = 9, - [8604] = 10, - [8606] = 11, - [8608] = 12, - [8610] = 13, - [8612] = 14, - [8614] = 15, - [8616] = 16, - [8618] = 17, - [8676] = 5, - [8680] = 6, - [8684] = 7, - [8704] = 0, - [8705] = 1, - [8710] = 2, - [8712] = 3, - [8714] = 4, - [8748] = 5, - [8750] = 6, - [8752] = 7, - [8754] = 8, - [8756] = 9, - [8758] = 10, - [8760] = 11, - [8762] = 12, - [8778] = 13, - [8780] = 14, - [8782] = 15, - [8784] = 16, - [8786] = 17, - [8788] = 18, - [8790] = 19, - [8792] = 20, - [8794] = 21, - [8832] = 0, - [8833] = 1, - [8838] = 2, - [8840] = 3, - [8842] = 4, - [8856] = 5, - [8858] = 6, - [8860] = 7, - [8862] = 8, - [8864] = 9, - [8866] = 10, - [8868] = 11, - [8870] = 12, - [8872] = 13, - [8874] = 14, - [8906] = 15, - [8908] = 16, - [8910] = 17, - [8912] = 18, - [8914] = 19, - [8916] = 20, - [8918] = 21, - [8920] = 22, - [8922] = 23, - [8960] = 0, - [8961] = 1, - [8966] = 2, - [8968] = 3, - [8970] = 4, - [9004] = 5, - [9006] = 6, - [9008] = 7, - [9010] = 8, - [9012] = 9, - [9014] = 10, - [9016] = 11, - [9018] = 12, - [9052] = 13, - [9054] = 14, - [9056] = 15, - [9058] = 16, - [9088] = 0, - [9089] = 1, - [9094] = 2, - [9096] = 3, - [9098] = 4, - [9112] = 5, - [9114] = 6, - [9116] = 7, - [9118] = 8, - [9120] = 9, - [9122] = 10, - [9124] = 11, - [9126] = 12, - [9128] = 13, - [9130] = 14, - [9180] = 15, - [9182] = 16, - [9184] = 17, - [9186] = 18, - [9216] = 0, - [9217] = 1, - [9222] = 2, - [9224] = 3, - [9226] = 4, - [9260] = 8, - [9262] = 9, - [9264] = 10, - [9266] = 11, - [9268] = 12, - [9270] = 13, - [9272] = 14, - [9274] = 15, - [9290] = 16, - [9292] = 17, - [9294] = 18, - [9296] = 19, - [9298] = 20, - [9300] = 21, - [9302] = 22, - [9304] = 23, - [9306] = 24, - [9316] = 5, - [9320] = 6, - [9324] = 7, - [9344] = 0, - [9345] = 1, - [9350] = 2, - [9352] = 3, - [9354] = 4, - [9368] = 8, - [9370] = 9, - [9372] = 10, - [9374] = 11, - [9376] = 12, - [9378] = 13, - [9380] = 14, - [9382] = 15, - [9384] = 16, - [9386] = 17, - [9418] = 18, - [9420] = 19, - [9422] = 20, - [9424] = 21, - [9426] = 22, - [9428] = 23, - [9430] = 24, - [9432] = 25, - [9434] = 26, - [9444] = 5, - [9448] = 6, - [9452] = 7, - [9472] = 0, - [9473] = 1, - [9478] = 2, - [9480] = 3, - [9482] = 4, - [9516] = 8, - [9518] = 9, - [9520] = 10, - [9522] = 11, - [9524] = 12, - [9526] = 13, - [9528] = 14, - [9530] = 15, - [9564] = 16, - [9566] = 17, - [9568] = 18, - [9570] = 19, - [9572] = 5, - [9576] = 6, - [9580] = 7, - [9600] = 0, - [9601] = 1, - [9606] = 2, - [9608] = 3, - [9610] = 4, - [9624] = 8, - [9626] = 9, - [9628] = 10, - [9630] = 11, - [9632] = 12, - [9634] = 13, - [9636] = 14, - [9638] = 15, - [9640] = 16, - [9642] = 17, - [9692] = 18, - [9694] = 19, - [9696] = 20, - [9698] = 21, - [9700] = 5, - [9704] = 6, - [9708] = 7, - [9728] = 0, - [9729] = 1, - [9734] = 2, - [9736] = 3, - [9738] = 4, - [9752] = 5, - [9754] = 6, - [9756] = 7, - [9758] = 8, - [9760] = 9, - [9762] = 10, - [9764] = 11, - [9766] = 12, - [9768] = 13, - [9770] = 14, - [9820] = 15, - [9822] = 16, - [9824] = 17, - [9826] = 18, - [9840] = 19, - [9841] = 20, - [9842] = 21, - [9843] = 22, - [18048] = 0, - [18049] = 1, - [18054] = 2, - [18056] = 3, - [18058] = 4, - [18092] = 5, - [18094] = 6, - [18096] = 7, - [18098] = 8, - [18100] = 9, - [18102] = 10, - [18104] = 11, - [18106] = 12, - [18140] = 13, - [18142] = 14, - [18144] = 15, - [18146] = 16, - [18160] = 17, - [18161] = 18, - [18162] = 19, - [18163] = 20, - [18176] = 0, - [18177] = 1, - [18182] = 2, - [18184] = 3, - [18186] = 4, - [18200] = 5, - [18202] = 6, - [18204] = 7, - [18206] = 8, - [18208] = 9, - [18210] = 10, - [18212] = 11, - [18214] = 12, - [18216] = 13, - [18218] = 14, - [18268] = 15, - [18270] = 16, - [18272] = 17, - [18274] = 18, - [18288] = 19, - [18289] = 20, - [18290] = 21, - [18291] = 22, - [18304] = 0, - [18305] = 1, - [18311] = 18, - [18313] = 19, - [18315] = 20, - [18348] = 2, - [18349] = 21, - [18350] = 3, - [18351] = 22, - [18352] = 4, - [18353] = 23, - [18354] = 5, - [18355] = 24, - [18356] = 6, - [18357] = 25, - [18358] = 7, - [18359] = 26, - [18360] = 8, - [18361] = 27, - [18362] = 9, - [18363] = 28, - [18396] = 10, - [18398] = 11, - [18400] = 12, - [18402] = 13, - [18416] = 14, - [18417] = 15, - [18418] = 16, - [18419] = 17, - [18432] = 0, - [18433] = 1, - [18439] = 20, - [18441] = 21, - [18443] = 22, - [18456] = 2, - [18458] = 3, - [18460] = 4, - [18462] = 5, - [18464] = 6, - [18466] = 7, - [18468] = 8, - [18470] = 9, - [18472] = 10, - [18474] = 11, - [18477] = 23, - [18479] = 24, - [18481] = 25, - [18483] = 26, - [18485] = 27, - [18487] = 28, - [18489] = 29, - [18491] = 30, - [18524] = 12, - [18526] = 13, - [18528] = 14, - [18530] = 15, - [18544] = 16, - [18545] = 17, - [18546] = 18, - [18547] = 19, - [18560] = 0, - [18561] = 1, - [18567] = 18, - [18569] = 19, - [18571] = 20, - [18585] = 21, - [18587] = 22, - [18589] = 23, - [18591] = 24, - [18593] = 25, - [18595] = 26, - [18597] = 27, - [18599] = 28, - [18601] = 29, - [18603] = 30, - [18604] = 2, - [18606] = 3, - [18608] = 4, - [18610] = 5, - [18612] = 6, - [18614] = 7, - [18616] = 8, - [18618] = 9, - [18652] = 10, - [18654] = 11, - [18656] = 12, - [18658] = 13, - [18672] = 14, - [18673] = 15, - [18674] = 16, - [18675] = 17, - [18688] = 0, - [18689] = 1, - [18695] = 20, - [18697] = 21, - [18699] = 22, - [18712] = 2, - [18713] = 23, - [18714] = 3, - [18715] = 24, - [18716] = 4, - [18717] = 25, - [18718] = 5, - [18719] = 26, - [18720] = 6, - [18721] = 27, - [18722] = 7, - [18723] = 28, - [18724] = 8, - [18725] = 29, - [18726] = 9, - [18727] = 30, - [18728] = 10, - [18729] = 31, - [18730] = 11, - [18731] = 32, - [18780] = 12, - [18782] = 13, - [18784] = 14, - [18786] = 15, - [18800] = 16, - [18801] = 17, - [18802] = 18, - [18803] = 19, - [18816] = 0, - [18817] = 1, - [18823] = 18, - [18825] = 19, - [18827] = 20, - [18860] = 2, - [18861] = 21, - [18862] = 3, - [18863] = 22, - [18864] = 4, - [18865] = 23, - [18866] = 5, - [18867] = 24, - [18868] = 6, - [18869] = 25, - [18870] = 7, - [18871] = 26, - [18872] = 8, - [18873] = 27, - [18874] = 9, - [18875] = 28, - [18891] = 29, - [18893] = 30, - [18895] = 31, - [18897] = 32, - [18899] = 33, - [18901] = 34, - [18903] = 35, - [18905] = 36, - [18907] = 37, - [18908] = 10, - [18910] = 11, - [18912] = 12, - [18914] = 13, - [18928] = 14, - [18929] = 15, - [18930] = 16, - [18931] = 17, - [18944] = 0, - [18945] = 1, - [18951] = 20, - [18953] = 21, - [18955] = 22, - [18968] = 2, - [18970] = 3, - [18972] = 4, - [18974] = 5, - [18976] = 6, - [18978] = 7, - [18980] = 8, - [18982] = 9, - [18984] = 10, - [18986] = 11, - [18989] = 23, - [18991] = 24, - [18993] = 25, - [18995] = 26, - [18997] = 27, - [18999] = 28, - [19001] = 29, - [19003] = 30, - [19019] = 31, - [19021] = 32, - [19023] = 33, - [19025] = 34, - [19027] = 35, - [19029] = 36, - [19031] = 37, - [19033] = 38, - [19035] = 39, - [19036] = 12, - [19038] = 13, - [19040] = 14, - [19042] = 15, - [19056] = 16, - [19057] = 17, - [19058] = 18, - [19059] = 19, - [19072] = 0, - [19073] = 1, - [19079] = 18, - [19081] = 19, - [19083] = 20, - [19097] = 21, - [19099] = 22, - [19101] = 23, - [19103] = 24, - [19105] = 25, - [19107] = 26, - [19109] = 27, - [19111] = 28, - [19113] = 29, - [19115] = 30, - [19116] = 2, - [19118] = 3, - [19120] = 4, - [19122] = 5, - [19124] = 6, - [19126] = 7, - [19128] = 8, - [19130] = 9, - [19147] = 31, - [19149] = 32, - [19151] = 33, - [19153] = 34, - [19155] = 35, - [19157] = 36, - [19159] = 37, - [19161] = 38, - [19163] = 39, - [19164] = 10, - [19166] = 11, - [19168] = 12, - [19170] = 13, - [19184] = 14, - [19185] = 15, - [19186] = 16, - [19187] = 17, - [19200] = 0, - [19201] = 1, - [19207] = 20, - [19209] = 21, - [19211] = 22, - [19224] = 2, - [19225] = 23, - [19226] = 3, - [19227] = 24, - [19228] = 4, - [19229] = 25, - [19230] = 5, - [19231] = 26, - [19232] = 6, - [19233] = 27, - [19234] = 7, - [19235] = 28, - [19236] = 8, - [19237] = 29, - [19238] = 9, - [19239] = 30, - [19240] = 10, - [19241] = 31, - [19242] = 11, - [19243] = 32, - [19275] = 33, - [19277] = 34, - [19279] = 35, - [19281] = 36, - [19283] = 37, - [19285] = 38, - [19287] = 39, - [19289] = 40, - [19291] = 41, - [19292] = 12, - [19294] = 13, - [19296] = 14, - [19298] = 15, - [19312] = 16, - [19313] = 17, - [19314] = 18, - [19315] = 19, - [19328] = 0, - [19329] = 1, - [19335] = 18, - [19337] = 19, - [19339] = 20, - [19372] = 2, - [19373] = 21, - [19374] = 3, - [19375] = 22, - [19376] = 4, - [19377] = 23, - [19378] = 5, - [19379] = 24, - [19380] = 6, - [19381] = 25, - [19382] = 7, - [19383] = 26, - [19384] = 8, - [19385] = 27, - [19386] = 9, - [19387] = 28, - [19420] = 10, - [19421] = 29, - [19422] = 11, - [19423] = 30, - [19424] = 12, - [19425] = 31, - [19426] = 13, - [19427] = 32, - [19440] = 14, - [19441] = 15, - [19442] = 16, - [19443] = 17, - [19456] = 0, - [19457] = 1, - [19463] = 20, - [19465] = 21, - [19467] = 22, - [19480] = 2, - [19482] = 3, - [19484] = 4, - [19486] = 5, - [19488] = 6, - [19490] = 7, - [19492] = 8, - [19494] = 9, - [19496] = 10, - [19498] = 11, - [19501] = 23, - [19503] = 24, - [19505] = 25, - [19507] = 26, - [19509] = 27, - [19511] = 28, - [19513] = 29, - [19515] = 30, - [19548] = 12, - [19549] = 31, - [19550] = 13, - [19551] = 32, - [19552] = 14, - [19553] = 33, - [19554] = 15, - [19555] = 34, - [19568] = 16, - [19569] = 17, - [19570] = 18, - [19571] = 19, - [19584] = 0, - [19585] = 1, - [19591] = 18, - [19593] = 19, - [19595] = 20, - [19609] = 21, - [19611] = 22, - [19613] = 23, - [19615] = 24, - [19617] = 25, - [19619] = 26, - [19621] = 27, - [19623] = 28, - [19625] = 29, - [19627] = 30, - [19628] = 2, - [19630] = 3, - [19632] = 4, - [19634] = 5, - [19636] = 6, - [19638] = 7, - [19640] = 8, - [19642] = 9, - [19676] = 10, - [19677] = 31, - [19678] = 11, - [19679] = 32, - [19680] = 12, - [19681] = 33, - [19682] = 13, - [19683] = 34, - [19696] = 14, - [19697] = 15, - [19698] = 16, - [19699] = 17, - [19712] = 0, - [19713] = 1, - [19719] = 20, - [19721] = 21, - [19723] = 22, - [19736] = 2, - [19737] = 23, - [19738] = 3, - [19739] = 24, - [19740] = 4, - [19741] = 25, - [19742] = 5, - [19743] = 26, - [19744] = 6, - [19745] = 27, - [19746] = 7, - [19747] = 28, - [19748] = 8, - [19749] = 29, - [19750] = 9, - [19751] = 30, - [19752] = 10, - [19753] = 31, - [19754] = 11, - [19755] = 32, - [19804] = 12, - [19805] = 33, - [19806] = 13, - [19807] = 34, - [19808] = 14, - [19809] = 35, - [19810] = 15, - [19811] = 36, - [19824] = 16, - [19825] = 17, - [19826] = 18, - [19827] = 19, - [19840] = 0, - [19841] = 1, - [19847] = 18, - [19849] = 19, - [19851] = 20, - [19855] = 31, - [19857] = 32, - [19859] = 33, - [19861] = 34, - [19863] = 35, - [19865] = 21, - [19867] = 22, - [19869] = 23, - [19871] = 24, - [19873] = 25, - [19875] = 26, - [19877] = 27, - [19879] = 28, - [19881] = 29, - [19883] = 30, - [19884] = 2, - [19886] = 3, - [19888] = 4, - [19890] = 5, - [19892] = 6, - [19894] = 7, - [19896] = 8, - [19898] = 9, - [19932] = 10, - [19934] = 11, - [19936] = 12, - [19938] = 13, - [19952] = 14, - [19953] = 15, - [19954] = 16, - [19955] = 17, - [19968] = 0, - [19969] = 1, - [19975] = 20, - [19977] = 21, - [19979] = 22, - [19983] = 33, - [19985] = 34, - [19987] = 35, - [19989] = 36, - [19991] = 37, - [19992] = 2, - [19993] = 23, - [19994] = 3, - [19995] = 24, - [19996] = 4, - [19997] = 25, - [19998] = 5, - [19999] = 26, - [20000] = 6, - [20001] = 27, - [20002] = 7, - [20003] = 28, - [20004] = 8, - [20005] = 29, - [20006] = 9, - [20007] = 30, - [20008] = 10, - [20009] = 31, - [20010] = 11, - [20011] = 32, - [20060] = 12, - [20062] = 13, - [20064] = 14, - [20066] = 15, - [20080] = 16, - [20081] = 17, - [20082] = 18, - [20083] = 19, - [28288] = 0, - [28289] = 1, - [28294] = 2, - [28296] = 3, - [28298] = 4, - [28332] = 5, - [28334] = 6, - [28336] = 7, - [28338] = 8, - [28340] = 9, - [28342] = 10, - [28344] = 11, - [28346] = 12, - [28416] = 0, - [28417] = 1, - [28422] = 2, - [28424] = 3, - [28426] = 4, - [28440] = 5, - [28442] = 6, - [28444] = 7, - [28446] = 8, - [28448] = 9, - [28450] = 10, - [28452] = 11, - [28454] = 12, - [28456] = 13, - [28458] = 14, - [28544] = 0, - [28545] = 1, - [28550] = 2, - [28552] = 3, - [28554] = 4, - [28588] = 8, - [28590] = 9, - [28592] = 10, - [28594] = 11, - [28596] = 12, - [28598] = 13, - [28600] = 14, - [28602] = 15, - [28644] = 5, - [28648] = 6, - [28652] = 7, - [28672] = 0, - [28673] = 1, - [28678] = 2, - [28680] = 3, - [28682] = 4, - [28696] = 8, - [28698] = 9, - [28700] = 10, - [28702] = 11, - [28704] = 12, - [28706] = 13, - [28708] = 14, - [28710] = 15, - [28712] = 16, - [28714] = 17, - [28772] = 5, - [28776] = 6, - [28780] = 7, - [28800] = 0, - [28801] = 1, - [28806] = 2, - [28808] = 3, - [28810] = 4, - [28844] = 5, - [28846] = 6, - [28848] = 7, - [28850] = 8, - [28852] = 9, - [28854] = 10, - [28856] = 11, - [28858] = 12, - [28874] = 13, - [28876] = 14, - [28878] = 15, - [28880] = 16, - [28882] = 17, - [28884] = 18, - [28886] = 19, - [28888] = 20, - [28890] = 21, - [28928] = 0, - [28929] = 1, - [28934] = 2, - [28936] = 3, - [28938] = 4, - [28952] = 5, - [28954] = 6, - [28956] = 7, - [28958] = 8, - [28960] = 9, - [28962] = 10, - [28964] = 11, - [28966] = 12, - [28968] = 13, - [28970] = 14, - [29002] = 15, - [29004] = 16, - [29006] = 17, - [29008] = 18, - [29010] = 19, - [29012] = 20, - [29014] = 21, - [29016] = 22, - [29018] = 23, - [29056] = 0, - [29057] = 1, - [29062] = 2, - [29064] = 3, - [29066] = 4, - [29100] = 5, - [29102] = 6, - [29104] = 7, - [29106] = 8, - [29108] = 9, - [29110] = 10, - [29112] = 11, - [29114] = 12, - [29148] = 13, - [29150] = 14, - [29152] = 15, - [29154] = 16, - [29184] = 0, - [29185] = 1, - [29190] = 2, - [29192] = 3, - [29194] = 4, - [29208] = 5, - [29210] = 6, - [29212] = 7, - [29214] = 8, - [29216] = 9, - [29218] = 10, - [29220] = 11, - [29222] = 12, - [29224] = 13, - [29226] = 14, - [29276] = 15, - [29278] = 16, - [29280] = 17, - [29282] = 18, - [29312] = 0, - [29313] = 1, - [29318] = 2, - [29320] = 3, - [29322] = 4, - [29356] = 8, - [29358] = 9, - [29360] = 10, - [29362] = 11, - [29364] = 12, - [29366] = 13, - [29368] = 14, - [29370] = 15, - [29386] = 16, - [29388] = 17, - [29390] = 18, - [29392] = 19, - [29394] = 20, - [29396] = 21, - [29398] = 22, - [29400] = 23, - [29402] = 24, - [29412] = 5, - [29416] = 6, - [29420] = 7, - [29440] = 0, - [29441] = 1, - [29446] = 2, - [29448] = 3, - [29450] = 4, - [29464] = 8, - [29466] = 9, - [29468] = 10, - [29470] = 11, - [29472] = 12, - [29474] = 13, - [29476] = 14, - [29478] = 15, - [29480] = 16, - [29482] = 17, - [29514] = 18, - [29516] = 19, - [29518] = 20, - [29520] = 21, - [29522] = 22, - [29524] = 23, - [29526] = 24, - [29528] = 25, - [29530] = 26, - [29540] = 5, - [29544] = 6, - [29548] = 7, - [29568] = 0, - [29569] = 1, - [29574] = 2, - [29576] = 3, - [29578] = 4, - [29612] = 8, - [29614] = 9, - [29616] = 10, - [29618] = 11, - [29620] = 12, - [29622] = 13, - [29624] = 14, - [29626] = 15, - [29660] = 16, - [29662] = 17, - [29664] = 18, - [29666] = 19, - [29668] = 5, - [29672] = 6, - [29676] = 7, - [29696] = 0, - [29697] = 1, - [29702] = 2, - [29704] = 3, - [29706] = 4, - [29720] = 8, - [29722] = 9, - [29724] = 10, - [29726] = 11, - [29728] = 12, - [29730] = 13, - [29732] = 14, - [29734] = 15, - [29736] = 16, - [29738] = 17, - [29788] = 18, - [29790] = 19, - [29792] = 20, - [29794] = 21, - [29796] = 5, - [29800] = 6, - [29804] = 7 -}; - -uint32_t ulp_glb_app_sig_tbl[] = { - [0] = 0, -}; diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.h index 5dbafb8c45..d6f4089b6b 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.h +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.h @@ -18,11 +18,17 @@ extern struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[]; extern struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[]; +extern struct +bnxt_ulp_mapper_field_info ulp_wh_plus_class_key_ext_list[]; + extern struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[]; extern struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[]; +extern struct +bnxt_ulp_mapper_cond_list_info ulp_wh_plus_class_cond_oper_list[]; + extern struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_act_tmpl_list[]; extern struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[]; @@ -36,6 +42,9 @@ bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[]; extern struct bnxt_ulp_mapper_cond_info ulp_wh_plus_act_cond_list[]; +extern struct +bnxt_ulp_mapper_cond_list_info ulp_wh_plus_act_cond_oper_list[]; + extern struct bnxt_ulp_mapper_key_info ulp_wh_plus_act_key_info_list[]; extern struct bnxt_ulp_mapper_ident_info ulp_wh_plus_act_ident_list[]; @@ -70,6 +79,9 @@ bnxt_ulp_mapper_cond_info ulp_stingray_class_cond_list[]; extern struct bnxt_ulp_mapper_cond_info ulp_stingray_act_cond_list[]; +extern struct +bnxt_ulp_mapper_cond_list_info ulp_stingray_act_cond_oper_list[]; + /* Thor template table declarations */ extern struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[]; @@ -78,11 +90,17 @@ extern struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[]; extern struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[]; +extern struct +bnxt_ulp_mapper_field_info ulp_thor_class_key_ext_list[]; + extern struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[]; extern struct bnxt_ulp_mapper_ident_info ulp_thor_class_ident_list[]; +extern struct +bnxt_ulp_mapper_cond_list_info ulp_thor_class_cond_oper_list[]; + extern struct bnxt_ulp_mapper_tmpl_info ulp_thor_act_tmpl_list[]; extern struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[]; @@ -100,6 +118,9 @@ bnxt_ulp_mapper_cond_info ulp_thor_class_cond_list[]; extern struct bnxt_ulp_mapper_cond_info ulp_thor_act_cond_list[]; +extern struct +bnxt_ulp_mapper_cond_list_info ulp_thor_act_cond_oper_list[]; + extern struct bnxt_ulp_mapper_key_info ulp_wh_plus_act_key_info_list[]; extern struct bnxt_ulp_mapper_ident_info ulp_wh_plus_act_ident_list[]; @@ -107,8 +128,48 @@ extern struct bnxt_ulp_mapper_ident_info ulp_wh_plus_act_ident_list[]; /* Global declarations */ extern uint8_t ulp_glb_field_tbl[]; extern uint32_t ulp_glb_app_sig_tbl[]; -extern uint32_t ulp_glb_app_sig_tbl[]; extern struct bnxt_ulp_shared_act_info ulp_shared_act_info[]; + +/* Thor2 template table declarations */ +extern struct bnxt_ulp_mapper_tmpl_info ulp_thor2_class_tmpl_list[]; + +extern struct bnxt_ulp_mapper_tbl_info ulp_thor2_class_tbl_list[]; + +extern struct +bnxt_ulp_mapper_key_info ulp_thor2_class_key_info_list[]; + +extern struct +bnxt_ulp_mapper_field_info ulp_thor2_class_key_ext_list[]; + +extern struct +bnxt_ulp_mapper_field_info ulp_thor2_class_result_field_list[]; + +extern struct bnxt_ulp_mapper_ident_info ulp_thor2_class_ident_list[]; + +extern struct +bnxt_ulp_mapper_cond_list_info ulp_thor2_class_cond_oper_list[]; + +extern struct bnxt_ulp_mapper_tmpl_info ulp_thor2_act_tmpl_list[]; + +extern struct bnxt_ulp_mapper_tbl_info ulp_thor2_act_tbl_list[]; + +extern struct +bnxt_ulp_mapper_key_info ulp_thor2_act_key_info_list[]; + +extern struct +bnxt_ulp_mapper_field_info ulp_thor2_act_result_field_list[]; + +extern struct bnxt_ulp_mapper_ident_info ulp_thor2_act_ident_list[]; + +extern struct +bnxt_ulp_mapper_cond_info ulp_thor2_class_cond_list[]; + +extern struct +bnxt_ulp_mapper_cond_info ulp_thor2_act_cond_list[]; + +extern struct +bnxt_ulp_mapper_cond_list_info ulp_thor2_act_cond_oper_list[]; + #endif diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor2_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor2_act.c new file mode 100644 index 0000000000..763ee4ab21 --- /dev/null +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor2_act.c @@ -0,0 +1,7459 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2014-2024 Broadcom + * All rights reserved. + */ + +#include "ulp_template_db_enum.h" +#include "ulp_template_db_field.h" +#include "ulp_template_struct.h" +#include "ulp_template_db_tbl.h" + +/* Mapper templates for header act list */ +struct bnxt_ulp_mapper_tmpl_info ulp_thor2_act_tmpl_list[] = { + /* act_tid: 1, ingress */ + [1] = { + .device_name = BNXT_ULP_DEVICE_ID_THOR2, + .num_tbls = 10, + .start_tbl_idx = 0, + .reject_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 0, + .cond_nums = 5 } + }, + /* act_tid: 2, ingress */ + [2] = { + .device_name = BNXT_ULP_DEVICE_ID_THOR2, + .num_tbls = 12, + .start_tbl_idx = 10, + .reject_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, + .cond_start_idx = 13, + .cond_nums = 0 } + }, + /* act_tid: 3, ingress */ + [3] = { + .device_name = BNXT_ULP_DEVICE_ID_THOR2, + .num_tbls = 9, + .start_tbl_idx = 22, + .reject_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, + .cond_start_idx = 17, + .cond_nums = 0 } + }, + /* act_tid: 4, ingress */ + [4] = { + .device_name = BNXT_ULP_DEVICE_ID_THOR2, + .num_tbls = 7, + .start_tbl_idx = 31, + .reject_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 22, + .cond_nums = 1 } + }, + /* act_tid: 6, egress */ + [6] = { + .device_name = BNXT_ULP_DEVICE_ID_THOR2, + .num_tbls = 6, + .start_tbl_idx = 38, + .reject_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 27, + .cond_nums = 4 } + }, + /* act_tid: 7, egress */ + [7] = { + .device_name = BNXT_ULP_DEVICE_ID_THOR2, + .num_tbls = 7, + .start_tbl_idx = 44, + .reject_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 33, + .cond_nums = 1 } + }, + /* act_tid: 8, egress */ + [8] = { + .device_name = BNXT_ULP_DEVICE_ID_THOR2, + .num_tbls = 21, + .start_tbl_idx = 51, + .reject_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 37, + .cond_nums = 2 } + } +}; + +struct bnxt_ulp_mapper_tbl_info ulp_thor2_act_tbl_list[] = { + { /* act_tid: 1, , table: shared_mirror_record.rd */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 2, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 5, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .key_start_idx = 0, + .blob_key_bit_size = 5, + .key_bit_size = 5, + .key_num_fields = 1, + .ident_start_idx = 0, + .ident_nums = 1 + }, + { /* act_tid: 1, , table: control.mirror */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1023, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 6, + .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP + }, + { /* act_tid: 1, , table: control.check_mods */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 4, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 7, + .cond_nums = 3 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP + }, + { /* act_tid: 1, , table: mod_record.ing_no_ttl */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CMM_TABLE, + .resource_type = CFA_RSUBTYPE_CMM_ACT, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CMM_TABLE_ACT, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 10, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_CMM_MOD_HNDL, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .result_start_idx = 0, + .result_bit_size = 0, + .result_num_fields = 0, + .encap_num_fields = 18 + }, + { /* act_tid: 1, , table: mod_record.ing_ttl */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CMM_TABLE, + .resource_type = CFA_RSUBTYPE_CMM_ACT, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CMM_TABLE_ACT, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 11, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_CMM_MOD_HNDL, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .result_start_idx = 18, + .result_bit_size = 0, + .result_num_fields = 0, + .encap_num_fields = 26 + }, + { /* act_tid: 1, , table: control.mod_handle_to_offset */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 12, + .cond_nums = 0 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .func_info = { + .func_opc = BNXT_ULP_FUNC_OPC_HANDLE_TO_OFFSET, + .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE, + .func_opr1 = BNXT_ULP_RF_IDX_CMM_MOD_HNDL, + .func_src2 = BNXT_ULP_FUNC_SRC_CONST, + .func_opr2 = 8, + .func_dst_opr = BNXT_ULP_RF_IDX_MODIFY_PTR } + }, + { /* act_tid: 1, , table: cmm_stat_record.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CMM_STAT, + .resource_type = CFA_RSUBTYPE_CMM_ACT, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CMM_TABLE_ACT, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 12, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_CMM_STAT_HNDL, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .result_start_idx = 44, + .result_bit_size = 128, + .result_num_fields = 2 + }, + { /* act_tid: 1, , table: control.stat_handle_to_offset */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 13, + .cond_nums = 0 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .func_info = { + .func_opc = BNXT_ULP_FUNC_OPC_HANDLE_TO_OFFSET, + .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE, + .func_opr1 = BNXT_ULP_RF_IDX_CMM_STAT_HNDL, + .func_src2 = BNXT_ULP_FUNC_SRC_CONST, + .func_opr2 = 8, + .func_dst_opr = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 } + }, + { /* act_tid: 1, , table: cmm_full_act_record.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CMM_TABLE, + .resource_type = CFA_RSUBTYPE_CMM_ACT, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CMM_TABLE_ACT, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 13, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_CMM_ACT_HNDL, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .result_start_idx = 46, + .result_bit_size = 192, + .result_num_fields = 18 + }, + { /* act_tid: 1, , table: control.act_handle_to_offset */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 0, + .cond_false_goto = 0, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 13, + .cond_nums = 0 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .func_info = { + .func_opc = BNXT_ULP_FUNC_OPC_HANDLE_TO_OFFSET, + .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE, + .func_opr1 = BNXT_ULP_RF_IDX_CMM_ACT_HNDL, + .func_src2 = BNXT_ULP_FUNC_SRC_CONST, + .func_opr2 = 32, + .func_dst_opr = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR } + }, + { /* act_tid: 2, , table: control.delete_chk */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 4, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 13, + .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP + }, + { /* act_tid: 2, , table: shared_mirror_record.del_chk */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_type = CFA_RSUBTYPE_IDX_TBL_MIRROR, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 14, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .ref_cnt_opcode = BNXT_ULP_REF_CNT_OPC_NOP, + .key_start_idx = 1, + .blob_key_bit_size = 5, + .key_bit_size = 5, + .key_num_fields = 1, + .ident_start_idx = 1, + .ident_nums = 1 + }, + { /* act_tid: 2, , table: control.mirror_del_exist_chk */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 0, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 14, + .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP + }, + { /* act_tid: 2, , table: control.mirror_ref_cnt_chk */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 0, + .cond_false_goto = 1023, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 15, + .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_DELETE_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .func_info = { + .func_opc = BNXT_ULP_FUNC_OPC_EQ, + .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE, + .func_opr1 = BNXT_ULP_RF_IDX_REF_CNT, + .func_src2 = BNXT_ULP_FUNC_SRC_CONST, + .func_opr2 = 1, + .func_dst_opr = BNXT_ULP_RF_IDX_CC } + }, + { /* act_tid: 2, , table: control.create */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 16, + .cond_nums = 0 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID + }, + { /* act_tid: 2, , table: mirror_tbl.alloc */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = CFA_RSUBTYPE_IDX_TBL_MIRROR, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 16, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_MIRROR_PTR_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .result_start_idx = 64, + .result_bit_size = 128, + .result_num_fields = 12 + }, + { /* act_tid: 2, , table: cmm_stat_record.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CMM_STAT, + .resource_type = CFA_RSUBTYPE_CMM_ACT, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CMM_TABLE_ACT, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 16, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_CMM_STAT_HNDL, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .result_start_idx = 76, + .result_bit_size = 128, + .result_num_fields = 2 + }, + { /* act_tid: 2, , table: control.stat_handle_to_offset */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 17, + .cond_nums = 0 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .func_info = { + .func_opc = BNXT_ULP_FUNC_OPC_HANDLE_TO_OFFSET, + .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE, + .func_opr1 = BNXT_ULP_RF_IDX_CMM_STAT_HNDL, + .func_src2 = BNXT_ULP_FUNC_SRC_CONST, + .func_opr2 = 8, + .func_dst_opr = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 } + }, + { /* act_tid: 2, , table: cmm_full_act_record.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CMM_TABLE, + .resource_type = CFA_RSUBTYPE_CMM_ACT, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CMM_TABLE_ACT, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 17, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_CMM_ACT_HNDL, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .result_start_idx = 78, + .result_bit_size = 192, + .result_num_fields = 18 + }, + { /* act_tid: 2, , table: control.act_handle_to_offset */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 17, + .cond_nums = 0 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .func_info = { + .func_opc = BNXT_ULP_FUNC_OPC_HANDLE_TO_OFFSET, + .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE, + .func_opr1 = BNXT_ULP_RF_IDX_CMM_ACT_HNDL, + .func_src2 = BNXT_ULP_FUNC_SRC_CONST, + .func_opr2 = 32, + .func_dst_opr = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR } + }, + { /* act_tid: 2, , table: mirror_tbl.wr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = CFA_RSUBTYPE_IDX_TBL_MIRROR, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 17, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_MIRROR_PTR_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .result_start_idx = 96, + .result_bit_size = 128, + .result_num_fields = 12 + }, + { /* act_tid: 2, , table: shared_mirror_record.wr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_type = CFA_RSUBTYPE_IDX_TBL_MIRROR, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 0, + .cond_false_goto = 0, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 17, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .ref_cnt_opcode = BNXT_ULP_REF_CNT_OPC_INC, + .key_start_idx = 2, + .blob_key_bit_size = 5, + .key_bit_size = 5, + .key_num_fields = 1, + .result_start_idx = 108, + .result_bit_size = 37, + .result_num_fields = 2 + }, + { /* act_tid: 3, , table: shared_mirror_record.rd */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 2, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 17, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .key_start_idx = 3, + .blob_key_bit_size = 5, + .key_bit_size = 5, + .key_num_fields = 1, + .ident_start_idx = 2, + .ident_nums = 1 + }, + { /* act_tid: 3, , table: control.mirror */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1023, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 18, + .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP + }, + { /* act_tid: 3, , table: mod_record.ing_no_ttl */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CMM_TABLE, + .resource_type = CFA_RSUBTYPE_CMM_ACT, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CMM_TABLE_ACT, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 19, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_CMM_MOD_HNDL, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .result_start_idx = 110, + .result_bit_size = 0, + .result_num_fields = 0, + .encap_num_fields = 24 + }, + { /* act_tid: 3, , table: mod_record.ing_ttl */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CMM_TABLE, + .resource_type = CFA_RSUBTYPE_CMM_ACT, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CMM_TABLE_ACT, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 20, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_CMM_MOD_HNDL, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .result_start_idx = 134, + .result_bit_size = 0, + .result_num_fields = 0, + .encap_num_fields = 32 + }, + { /* act_tid: 3, , table: control.mod_handle_to_offset */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 21, + .cond_nums = 0 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .func_info = { + .func_opc = BNXT_ULP_FUNC_OPC_HANDLE_TO_OFFSET, + .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE, + .func_opr1 = BNXT_ULP_RF_IDX_CMM_MOD_HNDL, + .func_src2 = BNXT_ULP_FUNC_SRC_CONST, + .func_opr2 = 8, + .func_dst_opr = BNXT_ULP_RF_IDX_MODIFY_PTR } + }, + { /* act_tid: 3, , table: cmm_stat_record.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CMM_STAT, + .resource_type = CFA_RSUBTYPE_CMM_ACT, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CMM_TABLE_ACT, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 2, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 21, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_CMM_STAT_HNDL, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .result_start_idx = 166, + .result_bit_size = 128, + .result_num_fields = 2 + }, + { /* act_tid: 3, , table: control.stat_handle_to_offset */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 22, + .cond_nums = 0 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .func_info = { + .func_opc = BNXT_ULP_FUNC_OPC_HANDLE_TO_OFFSET, + .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE, + .func_opr1 = BNXT_ULP_RF_IDX_CMM_STAT_HNDL, + .func_src2 = BNXT_ULP_FUNC_SRC_CONST, + .func_opr2 = 8, + .func_dst_opr = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 } + }, + { /* act_tid: 3, , table: cmm_full_act_record.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CMM_TABLE, + .resource_type = CFA_RSUBTYPE_CMM_ACT, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CMM_TABLE_ACT, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 22, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_CMM_ACT_HNDL, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .result_start_idx = 168, + .result_bit_size = 192, + .result_num_fields = 18 + }, + { /* act_tid: 3, , table: control.act_handle_to_offset */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 0, + .cond_false_goto = 0, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 22, + .cond_nums = 0 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .func_info = { + .func_opc = BNXT_ULP_FUNC_OPC_HANDLE_TO_OFFSET, + .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE, + .func_opr1 = BNXT_ULP_RF_IDX_CMM_ACT_HNDL, + .func_src2 = BNXT_ULP_FUNC_SRC_CONST, + .func_opr2 = 32, + .func_dst_opr = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR } + }, + { /* act_tid: 4, , table: shared_mirror_record.rd */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_type = TF_TBL_TYPE_MIRROR_CONFIG, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 2, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 23, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .key_start_idx = 4, + .blob_key_bit_size = 5, + .key_bit_size = 5, + .key_num_fields = 1, + .ident_start_idx = 3, + .ident_nums = 1 + }, + { /* act_tid: 4, , table: control.mirror */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1023, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 24, + .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP + }, + { /* act_tid: 4, , table: vnic_interface_rss_config.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_VNIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_VNIC_TABLE_RSS, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 25, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_VNIC_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_RSS_VNIC, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .result_start_idx = 186, + .result_bit_size = 0, + .result_num_fields = 0 + }, + { /* act_tid: 4, , table: cmm_stat_record.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CMM_STAT, + .resource_type = CFA_RSUBTYPE_CMM_ACT, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CMM_TABLE_ACT, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 2, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 26, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_CMM_STAT_HNDL, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .result_start_idx = 186, + .result_bit_size = 128, + .result_num_fields = 2 + }, + { /* act_tid: 4, , table: control.stat_handle_to_offset */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 27, + .cond_nums = 0 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .func_info = { + .func_opc = BNXT_ULP_FUNC_OPC_HANDLE_TO_OFFSET, + .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE, + .func_opr1 = BNXT_ULP_RF_IDX_CMM_STAT_HNDL, + .func_src2 = BNXT_ULP_FUNC_SRC_CONST, + .func_opr2 = 8, + .func_dst_opr = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 } + }, + { /* act_tid: 4, , table: cmm_full_act_record.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CMM_TABLE, + .resource_type = CFA_RSUBTYPE_CMM_ACT, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CMM_TABLE_ACT, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 27, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_CMM_ACT_HNDL, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .result_start_idx = 188, + .result_bit_size = 192, + .result_num_fields = 18 + }, + { /* act_tid: 4, , table: control.act_handle_to_offset */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 0, + .cond_false_goto = 0, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 27, + .cond_nums = 0 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .func_info = { + .func_opc = BNXT_ULP_FUNC_OPC_HANDLE_TO_OFFSET, + .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE, + .func_opr1 = BNXT_ULP_RF_IDX_CMM_ACT_HNDL, + .func_src2 = BNXT_ULP_FUNC_SRC_CONST, + .func_opr2 = 32, + .func_dst_opr = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR } + }, + { /* act_tid: 6, , table: mod_record.ing_ttl */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CMM_TABLE, + .resource_type = CFA_RSUBTYPE_CMM_ACT, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CMM_TABLE_ACT, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 2, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 31, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_CMM_MOD_HNDL, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .result_start_idx = 206, + .result_bit_size = 0, + .result_num_fields = 0, + .encap_num_fields = 24 + }, + { /* act_tid: 6, , table: control.mod_handle_to_offset */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 32, + .cond_nums = 0 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .func_info = { + .func_opc = BNXT_ULP_FUNC_OPC_HANDLE_TO_OFFSET, + .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE, + .func_opr1 = BNXT_ULP_RF_IDX_CMM_MOD_HNDL, + .func_src2 = BNXT_ULP_FUNC_SRC_CONST, + .func_opr2 = 8, + .func_dst_opr = BNXT_ULP_RF_IDX_MODIFY_PTR } + }, + { /* act_tid: 6, , table: cmm_stat_record.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CMM_STAT, + .resource_type = CFA_RSUBTYPE_CMM_ACT, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CMM_TABLE_ACT, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 2, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 32, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_CMM_STAT_HNDL, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .result_start_idx = 230, + .result_bit_size = 128, + .result_num_fields = 2 + }, + { /* act_tid: 6, , table: control.stat_handle_to_offset */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 33, + .cond_nums = 0 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .func_info = { + .func_opc = BNXT_ULP_FUNC_OPC_HANDLE_TO_OFFSET, + .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE, + .func_opr1 = BNXT_ULP_RF_IDX_CMM_STAT_HNDL, + .func_src2 = BNXT_ULP_FUNC_SRC_CONST, + .func_opr2 = 8, + .func_dst_opr = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 } + }, + { /* act_tid: 6, , table: cmm_full_act_record.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CMM_TABLE, + .resource_type = CFA_RSUBTYPE_CMM_ACT, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CMM_TABLE_ACT, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 33, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_CMM_ACT_HNDL, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .result_start_idx = 232, + .result_bit_size = 192, + .result_num_fields = 18 + }, + { /* act_tid: 6, , table: control.act_handle_to_offset */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 0, + .cond_false_goto = 0, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 33, + .cond_nums = 0 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .func_info = { + .func_opc = BNXT_ULP_FUNC_OPC_HANDLE_TO_OFFSET, + .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE, + .func_opr1 = BNXT_ULP_RF_IDX_CMM_ACT_HNDL, + .func_src2 = BNXT_ULP_FUNC_SRC_CONST, + .func_opr2 = 32, + .func_dst_opr = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR } + }, + { /* act_tid: 7, , table: mod_record.egr_no_ttl */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CMM_TABLE, + .resource_type = CFA_RSUBTYPE_CMM_ACT, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CMM_TABLE_ACT, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 34, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_CMM_MOD_HNDL, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .result_start_idx = 250, + .result_bit_size = 0, + .result_num_fields = 0, + .encap_num_fields = 24 + }, + { /* act_tid: 7, , table: mod_record.egr_ttl */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CMM_TABLE, + .resource_type = CFA_RSUBTYPE_CMM_ACT, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CMM_TABLE_ACT, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 35, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_CMM_MOD_HNDL, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .result_start_idx = 274, + .result_bit_size = 0, + .result_num_fields = 0, + .encap_num_fields = 32 + }, + { /* act_tid: 7, , table: control.mod_handle_to_offset */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 36, + .cond_nums = 0 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .func_info = { + .func_opc = BNXT_ULP_FUNC_OPC_HANDLE_TO_OFFSET, + .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE, + .func_opr1 = BNXT_ULP_RF_IDX_CMM_MOD_HNDL, + .func_src2 = BNXT_ULP_FUNC_SRC_CONST, + .func_opr2 = 8, + .func_dst_opr = BNXT_ULP_RF_IDX_MODIFY_PTR } + }, + { /* act_tid: 7, , table: cmm_stat_record.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CMM_STAT, + .resource_type = CFA_RSUBTYPE_CMM_ACT, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CMM_TABLE_ACT, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 2, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 36, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_CMM_STAT_HNDL, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .result_start_idx = 306, + .result_bit_size = 128, + .result_num_fields = 2 + }, + { /* act_tid: 7, , table: control.stat_handle_to_offset */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 37, + .cond_nums = 0 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .func_info = { + .func_opc = BNXT_ULP_FUNC_OPC_HANDLE_TO_OFFSET, + .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE, + .func_opr1 = BNXT_ULP_RF_IDX_CMM_STAT_HNDL, + .func_src2 = BNXT_ULP_FUNC_SRC_CONST, + .func_opr2 = 8, + .func_dst_opr = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 } + }, + { /* act_tid: 7, , table: cmm_full_act_record.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CMM_TABLE, + .resource_type = CFA_RSUBTYPE_CMM_ACT, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CMM_TABLE_ACT, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 37, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_CMM_ACT_HNDL, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .result_start_idx = 308, + .result_bit_size = 192, + .result_num_fields = 18 + }, + { /* act_tid: 7, , table: control.act_handle_to_offset */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 0, + .cond_false_goto = 0, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 37, + .cond_nums = 0 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .func_info = { + .func_opc = BNXT_ULP_FUNC_OPC_HANDLE_TO_OFFSET, + .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE, + .func_opr1 = BNXT_ULP_RF_IDX_CMM_ACT_HNDL, + .func_src2 = BNXT_ULP_FUNC_SRC_CONST, + .func_opr2 = 32, + .func_dst_opr = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR } + }, + { /* act_tid: 8, , table: cmm_stat_record.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CMM_STAT, + .resource_type = CFA_RSUBTYPE_CMM_ACT, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CMM_TABLE_ACT, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 2, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 39, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_CMM_STAT_HNDL, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .result_start_idx = 326, + .result_bit_size = 128, + .result_num_fields = 2 + }, + { /* act_tid: 8, , table: control.stat_handle_to_offset */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 40, + .cond_nums = 0 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .func_info = { + .func_opc = BNXT_ULP_FUNC_OPC_HANDLE_TO_OFFSET, + .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE, + .func_opr1 = BNXT_ULP_RF_IDX_CMM_STAT_HNDL, + .func_src2 = BNXT_ULP_FUNC_SRC_CONST, + .func_opr2 = 8, + .func_dst_opr = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 } + }, + { /* act_tid: 8, , table: mod_record.egr_set_mac */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CMM_TABLE, + .resource_type = CFA_RSUBTYPE_CMM_ACT, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CMM_TABLE_ACT, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 2, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 40, + .cond_nums = 2 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_CMM_MOD_HNDL, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .result_start_idx = 328, + .result_bit_size = 0, + .result_num_fields = 0, + .encap_num_fields = 18 + }, + { /* act_tid: 8, , table: control.mod_handle_to_offset */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 42, + .cond_nums = 0 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .func_info = { + .func_opc = BNXT_ULP_FUNC_OPC_HANDLE_TO_OFFSET, + .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE, + .func_opr1 = BNXT_ULP_RF_IDX_CMM_MOD_HNDL, + .func_src2 = BNXT_ULP_FUNC_SRC_CONST, + .func_opr2 = 8, + .func_dst_opr = BNXT_ULP_RF_IDX_MODIFY_PTR } + }, + { /* act_tid: 8, , table: source_property_cache.rd */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_CACHE, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 5, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 42, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .key_start_idx = 5, + .blob_key_bit_size = 85, + .key_bit_size = 85, + .key_num_fields = 3, + .ident_start_idx = 4, + .ident_nums = 1 + }, + { /* act_tid: 8, , table: control.sp_rec_v4 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 14, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 43, + .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID + }, + { /* act_tid: 8, , table: sp_smac_ipv4.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CMM_TABLE, + .resource_type = CFA_RSUBTYPE_CMM_ACT, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CMM_TABLE_ACT, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 44, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_CMM_SRP_HNDL, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .result_start_idx = 346, + .result_bit_size = 0, + .result_num_fields = 0, + .encap_num_fields = 3 + }, + { /* act_tid: 8, , table: control.srp_handle_to_offset */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 45, + .cond_nums = 0 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .func_info = { + .func_opc = BNXT_ULP_FUNC_OPC_HANDLE_TO_OFFSET, + .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE, + .func_opr1 = BNXT_ULP_RF_IDX_CMM_SRP_HNDL, + .func_src2 = BNXT_ULP_FUNC_SRC_CONST, + .func_opr2 = 8, + .func_dst_opr = BNXT_ULP_RF_IDX_MAIN_SP_PTR } + }, + { /* act_tid: 8, , table: source_property_cache.wr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_CACHE, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 45, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .key_start_idx = 8, + .blob_key_bit_size = 85, + .key_bit_size = 85, + .key_num_fields = 3, + .result_start_idx = 349, + .result_bit_size = 64, + .result_num_fields = 2 + }, + { /* act_tid: 8, , table: vxlan_encap_rec_cache.rd */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 10, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 45, + .cond_nums = 2 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .key_start_idx = 11, + .blob_key_bit_size = 141, + .key_bit_size = 141, + .key_num_fields = 6, + .ident_start_idx = 5, + .ident_nums = 1 + }, + { /* act_tid: 8, , table: control.vxlan_v4_encap */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 4, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 47, + .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID + }, + { /* act_tid: 8, , table: ext_tun_vxlan_encap_record.ipv4_vxlan */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CMM_TABLE, + .resource_type = CFA_RSUBTYPE_CMM_ACT, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CMM_TABLE_ACT, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 48, + .cond_nums = 2 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_CMM_ENC_HNDL, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .result_start_idx = 351, + .result_bit_size = 0, + .result_num_fields = 0, + .encap_num_fields = 25 + }, + { /* act_tid: 8, , table: control.enc_handle_to_offset */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 50, + .cond_nums = 0 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .func_info = { + .func_opc = BNXT_ULP_FUNC_OPC_HANDLE_TO_OFFSET, + .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE, + .func_opr1 = BNXT_ULP_RF_IDX_CMM_ENC_HNDL, + .func_src2 = BNXT_ULP_FUNC_SRC_CONST, + .func_opr2 = 8, + .func_dst_opr = BNXT_ULP_RF_IDX_ENCAP_PTR_0 } + }, + { /* act_tid: 8, , table: vxlan_encap_rec_cache.wr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 50, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .key_start_idx = 17, + .blob_key_bit_size = 141, + .key_bit_size = 141, + .key_num_fields = 6, + .result_start_idx = 376, + .result_bit_size = 64, + .result_num_fields = 2 + }, + { /* act_tid: 8, , table: geneve_encap_rec_cache.rd */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_GENEVE_ENCAP_REC_CACHE, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 50, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .key_start_idx = 23, + .blob_key_bit_size = 493, + .key_bit_size = 493, + .key_num_fields = 15, + .ident_start_idx = 6, + .ident_nums = 1 + }, + { /* act_tid: 8, , table: control.geneve_encap */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 4, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 51, + .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID + }, + { /* act_tid: 8, , table: ext_tun_geneve_encap_record.ipv4_vxlan */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CMM_TABLE, + .resource_type = CFA_RSUBTYPE_CMM_ACT, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CMM_TABLE_ACT, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 52, + .cond_nums = 2 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_CMM_ENC_HNDL, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .result_start_idx = 378, + .result_bit_size = 0, + .result_num_fields = 0, + .encap_num_fields = 31 + }, + { /* act_tid: 8, , table: ext_tun_geneve_encap_record.ipv6_geneve */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CMM_TABLE, + .resource_type = CFA_RSUBTYPE_CMM_ACT, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CMM_TABLE_ACT, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 54, + .cond_nums = 2 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_CMM_ENC_HNDL, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .result_start_idx = 409, + .result_bit_size = 0, + .result_num_fields = 0, + .encap_num_fields = 29 + }, + { /* act_tid: 8, , table: geneve_encap_rec_cache.wr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_GENEVE_ENCAP_REC_CACHE, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 56, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .key_start_idx = 38, + .blob_key_bit_size = 493, + .key_bit_size = 493, + .key_num_fields = 15, + .result_start_idx = 438, + .result_bit_size = 64, + .result_num_fields = 2 + }, + { /* act_tid: 8, , table: cmm_full_act_record.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CMM_TABLE, + .resource_type = CFA_RSUBTYPE_CMM_ACT, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CMM_TABLE_ACT, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 57, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_CMM_ACT_HNDL, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .result_start_idx = 440, + .result_bit_size = 192, + .result_num_fields = 18 + }, + { /* act_tid: 8, , table: control.act_handle_to_offset */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 0, + .cond_false_goto = 0, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 57, + .cond_nums = 0 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .func_info = { + .func_opc = BNXT_ULP_FUNC_OPC_HANDLE_TO_OFFSET, + .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE, + .func_opr1 = BNXT_ULP_RF_IDX_CMM_ACT_HNDL, + .func_src2 = BNXT_ULP_FUNC_SRC_CONST, + .func_opr2 = 32, + .func_dst_opr = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR } + } +}; + +struct bnxt_ulp_mapper_cond_list_info ulp_thor2_act_cond_oper_list[] = { +}; + +struct bnxt_ulp_mapper_cond_info ulp_thor2_act_cond_list[] = { + /* cond_reject: thor2, act_tid: 1 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_POP_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_SET_VLAN_VID + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_SET_VLAN_PCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_METER + }, + /* cond_execute: act_tid: 1, shared_mirror_record.rd:5*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_SHARED_SAMPLE + }, + /* cond_execute: act_tid: 1, control.mirror:6*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + }, + /* cond_execute: act_tid: 1, control.check_mods:7*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_NOT_SET, + .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_NOT_SET, + .cond_operand = BNXT_ULP_ACT_BIT_SET_MAC_SRC + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_NOT_SET, + .cond_operand = BNXT_ULP_ACT_BIT_SET_MAC_DST + }, + /* cond_execute: act_tid: 1, mod_record.ing_no_ttl:10*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_NOT_SET, + .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL + }, + /* cond_execute: act_tid: 1, mod_record.ing_ttl:11*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL + }, + /* cond_execute: act_tid: 1, cmm_stat_record.0:12*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_COUNT + }, + /* cond_execute: act_tid: 2, control.delete_chk:13*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_DELETE + }, + /* cond_execute: act_tid: 2, control.mirror_del_exist_chk:14*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + }, + /* cond_execute: act_tid: 2, control.mirror_ref_cnt_chk:15*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_CC + }, + /* cond_execute: act_tid: 2, cmm_stat_record.0:16*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_COUNT + }, + /* cond_execute: act_tid: 3, shared_mirror_record.rd:17*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_SHARED_SAMPLE + }, + /* cond_execute: act_tid: 3, control.mirror:18*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + }, + /* cond_execute: act_tid: 3, mod_record.ing_no_ttl:19*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_NOT_SET, + .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL + }, + /* cond_execute: act_tid: 3, mod_record.ing_ttl:20*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL + }, + /* cond_execute: act_tid: 3, cmm_stat_record.0:21*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_COUNT + }, + /* cond_reject: thor2, act_tid: 4 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_QUEUE + }, + /* cond_execute: act_tid: 4, shared_mirror_record.rd:23*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_SHARED_SAMPLE + }, + /* cond_execute: act_tid: 4, control.mirror:24*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + }, + /* cond_execute: act_tid: 4, vnic_interface_rss_config.0:25*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_RSS + }, + /* cond_execute: act_tid: 4, cmm_stat_record.0:26*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_COUNT + }, + /* cond_reject: thor2, act_tid: 6 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_SET_VLAN_PCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_SET_VLAN_VID + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_SHARED_SAMPLE + }, + /* cond_execute: act_tid: 6, mod_record.ing_ttl:31*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL + }, + /* cond_execute: act_tid: 6, cmm_stat_record.0:32*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_COUNT + }, + /* cond_reject: thor2, act_tid: 7 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_SHARED_SAMPLE + }, + /* cond_execute: act_tid: 7, mod_record.egr_no_ttl:34*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_NOT_SET, + .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL + }, + /* cond_execute: act_tid: 7, mod_record.egr_ttl:35*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL + }, + /* cond_execute: act_tid: 7, cmm_stat_record.0:36*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_COUNT + }, + /* cond_reject: thor2, act_tid: 8 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_SHARED_SAMPLE + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, + .cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV6_FLAG + }, + /* cond_execute: act_tid: 8, cmm_stat_record.0:39*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_COUNT + }, + /* cond_execute: act_tid: 8, mod_record.egr_set_mac:40*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_SET_MAC_SRC + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_SET_MAC_DST + }, + /* cond_execute: act_tid: 8, source_property_cache.rd:42*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, + .cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG + }, + /* cond_execute: act_tid: 8, control.sp_rec_v4:43*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + }, + /* cond_execute: act_tid: 8, sp_smac_ipv4.0:44*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, + .cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG + }, + /* cond_execute: act_tid: 8, vxlan_encap_rec_cache.rd:45*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN + }, + /* cond_execute: act_tid: 8, control.vxlan_v4_encap:47*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + }, + /* cond_execute: act_tid: 8, ext_tun_vxlan_encap_record.ipv4_vxlan:48*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN + }, + /* cond_execute: act_tid: 8, geneve_encap_rec_cache.rd:50*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_GENEVE + }, + /* cond_execute: act_tid: 8, control.geneve_encap:51*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + }, + /* cond_execute: act_tid: 8, ext_tun_geneve_encap_record.ipv4_vxlan:52*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_GENEVE + }, + /* cond_execute: act_tid: 8, ext_tun_geneve_encap_record.ipv6_geneve:54*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_GENEVE + }, + /* cond_execute: act_tid: 8, geneve_encap_rec_cache.wr:56*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_GENEVE + } +}; + +struct bnxt_ulp_mapper_key_info ulp_thor2_act_key_info_list[] = { + /* act_tid: 1, , table: shared_mirror_record.rd */ + { + .field_info_mask = { + .description = "shared_index", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "shared_index", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE & 0xff} + } + }, + /* act_tid: 2, , table: shared_mirror_record.del_chk */ + { + .field_info_mask = { + .description = "shared_index", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "shared_index", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE & 0xff} + } + }, + /* act_tid: 2, , table: shared_mirror_record.wr */ + { + .field_info_mask = { + .description = "shared_index", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "shared_index", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff} + } + }, + /* act_tid: 3, , table: shared_mirror_record.rd */ + { + .field_info_mask = { + .description = "shared_index", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "shared_index", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE & 0xff} + } + }, + /* act_tid: 4, , table: shared_mirror_record.rd */ + { + .field_info_mask = { + .description = "shared_index", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "shared_index", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE & 0xff} + } + }, + /* act_tid: 8, , table: source_property_cache.rd */ + { + .field_info_mask = { + .description = "smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_ETH_SMAC & 0xff} + } + }, + { + .field_info_mask = { + .description = "ipv4_src_addr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "ipv4_src_addr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_IPV4_SADDR >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_SADDR & 0xff} + } + }, + { + .field_info_mask = { + .description = "tbl_scope", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tbl_scope", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_PORT_TABLE, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff, + (BNXT_ULP_PORT_TABLE_TABLE_SCOPE >> 8) & 0xff, + BNXT_ULP_PORT_TABLE_TABLE_SCOPE & 0xff} + } + }, + /* act_tid: 8, , table: source_property_cache.wr */ + { + .field_info_mask = { + .description = "smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_ETH_SMAC & 0xff} + } + }, + { + .field_info_mask = { + .description = "ipv4_src_addr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "ipv4_src_addr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_IPV4_SADDR >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_SADDR & 0xff} + } + }, + { + .field_info_mask = { + .description = "tbl_scope", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tbl_scope", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_PORT_TABLE, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff, + (BNXT_ULP_PORT_TABLE_TABLE_SCOPE >> 8) & 0xff, + BNXT_ULP_PORT_TABLE_TABLE_SCOPE & 0xff} + } + }, + /* act_tid: 8, , table: vxlan_encap_rec_cache.rd */ + { + .field_info_mask = { + .description = "dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_ETH_DMAC & 0xff} + } + }, + { + .field_info_mask = { + .description = "ipv4_dst_addr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "ipv4_dst_addr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_IPV4_DADDR >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_DADDR & 0xff} + } + }, + { + .field_info_mask = { + .description = "udp_sport", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "udp_sport", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff} + } + }, + { + .field_info_mask = { + .description = "udp_dport", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "udp_dport", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff} + } + }, + { + .field_info_mask = { + .description = "vni", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "vni", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff} + } + }, + { + .field_info_mask = { + .description = "tbl_scope", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tbl_scope", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_PORT_TABLE, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff, + (BNXT_ULP_PORT_TABLE_TABLE_SCOPE >> 8) & 0xff, + BNXT_ULP_PORT_TABLE_TABLE_SCOPE & 0xff} + } + }, + /* act_tid: 8, , table: vxlan_encap_rec_cache.wr */ + { + .field_info_mask = { + .description = "dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_ETH_DMAC & 0xff} + } + }, + { + .field_info_mask = { + .description = "ipv4_dst_addr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "ipv4_dst_addr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_IPV4_DADDR >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_DADDR & 0xff} + } + }, + { + .field_info_mask = { + .description = "udp_sport", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "udp_sport", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff} + } + }, + { + .field_info_mask = { + .description = "udp_dport", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "udp_dport", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff} + } + }, + { + .field_info_mask = { + .description = "vni", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "vni", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff} + } + }, + { + .field_info_mask = { + .description = "tbl_scope", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tbl_scope", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_PORT_TABLE, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff, + (BNXT_ULP_PORT_TABLE_TABLE_SCOPE >> 8) & 0xff, + BNXT_ULP_PORT_TABLE_TABLE_SCOPE & 0xff} + } + }, + /* act_tid: 8, , table: geneve_encap_rec_cache.rd */ + { + .field_info_mask = { + .description = "dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_ETH_DMAC & 0xff} + } + }, + { + .field_info_mask = { + .description = "ipv4_dst_addr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "ipv4_dst_addr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr2 = { + (BNXT_ULP_ENC_FIELD_IPV4_DADDR >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_DADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "ipv6_dst_addr", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "ipv6_dst_addr", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr2 = { + (BNXT_ULP_ENC_FIELD_IPV6_DADDR >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV6_DADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "udp_sport", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "udp_sport", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff} + } + }, + { + .field_info_mask = { + .description = "udp_dport", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "udp_dport", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff} + } + }, + { + .field_info_mask = { + .description = "ver_opt_len_o_c_rsvd0", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "ver_opt_len_o_c_rsvd0", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_GENEVE_VER_OPT_LEN_O_C_RSVD0 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_VER_OPT_LEN_O_C_RSVD0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "proto_type", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "proto_type", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_GENEVE_PROTO_TYPE >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_PROTO_TYPE & 0xff} + } + }, + { + .field_info_mask = { + .description = "vni", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "vni", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_GENEVE_VNI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_VNI & 0xff} + } + }, + { + .field_info_mask = { + .description = "opt_w0", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "opt_w0", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_GENEVE_OPT_W0 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_OPT_W0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "opt_w1", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "opt_w1", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_GENEVE_OPT_W1 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_OPT_W1 & 0xff} + } + }, + { + .field_info_mask = { + .description = "opt_w2", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "opt_w2", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_GENEVE_OPT_W2 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_OPT_W2 & 0xff} + } + }, + { + .field_info_mask = { + .description = "opt_w3", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "opt_w3", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_GENEVE_OPT_W3 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_OPT_W3 & 0xff} + } + }, + { + .field_info_mask = { + .description = "opt_w4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "opt_w4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_GENEVE_OPT_W4 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_OPT_W4 & 0xff} + } + }, + { + .field_info_mask = { + .description = "opt_w5", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "opt_w5", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_GENEVE_OPT_W5 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_OPT_W5 & 0xff} + } + }, + { + .field_info_mask = { + .description = "tbl_scope", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tbl_scope", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + /* act_tid: 8, , table: geneve_encap_rec_cache.wr */ + { + .field_info_mask = { + .description = "dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_ETH_DMAC & 0xff} + } + }, + { + .field_info_mask = { + .description = "ipv4_dst_addr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "ipv4_dst_addr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr2 = { + (BNXT_ULP_ENC_FIELD_IPV4_DADDR >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_DADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "ipv6_dst_addr", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "ipv6_dst_addr", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr2 = { + (BNXT_ULP_ENC_FIELD_IPV6_DADDR >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV6_DADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "udp_sport", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "udp_sport", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff} + } + }, + { + .field_info_mask = { + .description = "udp_dport", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "udp_dport", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff} + } + }, + { + .field_info_mask = { + .description = "ver_opt_len_o_c_rsvd0", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "ver_opt_len_o_c_rsvd0", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "proto_type", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "proto_type", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "vni", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "vni", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_GENEVE_VNI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_VNI & 0xff} + } + }, + { + .field_info_mask = { + .description = "opt_w0", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "opt_w0", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_GENEVE_OPT_W0 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_OPT_W0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "opt_w1", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "opt_w1", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_GENEVE_OPT_W1 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_OPT_W1 & 0xff} + } + }, + { + .field_info_mask = { + .description = "opt_w2", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "opt_w2", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_GENEVE_OPT_W2 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_OPT_W2 & 0xff} + } + }, + { + .field_info_mask = { + .description = "opt_w3", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "opt_w3", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_GENEVE_OPT_W3 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_OPT_W3 & 0xff} + } + }, + { + .field_info_mask = { + .description = "opt_w4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "opt_w4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_GENEVE_OPT_W4 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_OPT_W4 & 0xff} + } + }, + { + .field_info_mask = { + .description = "opt_w5", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "opt_w5", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_GENEVE_OPT_W5 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_OPT_W5 & 0xff} + } + }, + { + .field_info_mask = { + .description = "tbl_scope", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tbl_scope", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + } +}; + +struct bnxt_ulp_mapper_field_info ulp_thor2_act_key_ext_list[] = { +}; + +struct bnxt_ulp_mapper_field_info ulp_thor2_act_result_field_list[] = { + /* act_tid: 1, , table: mod_record.ing_no_ttl */ + { + .description = "metadata_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rem_ovlan", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rem_ivlan", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rep_add_ivlan", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rep_add_ovlan", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ttl_update", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tun_md_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "reserved_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_dmac_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_smac_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip_ipv6_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_dip_ipv6_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip_ipv4_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_dip_ipv4_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_sport_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_dport_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr2 = { + (BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr2 = { + (BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + /* act_tid: 1, , table: mod_record.ing_ttl */ + { + .description = "metadata_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rem_ovlan", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rem_ivlan", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rep_add_ivlan", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rep_add_ovlan", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ttl_update", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "tun_md_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "reserved_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_dmac_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_smac_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip_ipv6_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_dip_ipv6_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip_ipv4_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_dip_ipv4_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_sport_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_dport_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "alt_pfid", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "alt_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ttl_rsvd", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ttl_tl3_dec", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, + BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff} + }, + { + .description = "ttl_il3_dec", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, + BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff} + }, + { + .description = "ttl_otl3_rdir", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ttl_tl3_rdir", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ttl_il3_rdir", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr2 = { + (BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr2 = { + (BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + /* act_tid: 1, , table: cmm_stat_record.0 */ + { + .description = "packet_count", + .field_bit_size = 64, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "byte_count", + .field_bit_size = 64, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* act_tid: 1, , table: cmm_full_act_record.0 */ + { + .description = "type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "drop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff} + }, + { + .description = "vlan_del_rpt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "vnic_or_vport", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO, + .field_src3 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr3 = { + (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff} + }, + { + .description = "dest_op", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "decap_func", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_DECAP_FUNC_THRU_TUN}, + .field_src3 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr3 = { + ULP_THOR2_SYM_DECAP_FUNC_NONE} + }, + { + .description = "mirror", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_RF, + .field_opr2 = { + (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meter_ptr", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat0_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff} + }, + { + .description = "stat0_ing_egr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat0_ctr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat1_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat1_ing_egr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat1_ctr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "mod_rec_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MODIFY_PTR & 0xff} + }, + { + .description = "encap_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "src_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rsvd0", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* act_tid: 2, , table: mirror_tbl.alloc */ + { + .description = "reserved1", + .field_bit_size = 21, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "arp_relative", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "action_hint", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "sample_mode", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "trunc_mode", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ignore_drop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "copy_mode", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "mirr_cond", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "act_rec_ptr", + .field_bit_size = 26, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "reserved2", + .field_bit_size = 6, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "samp_cfg", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "padding1", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* act_tid: 2, , table: cmm_stat_record.0 */ + { + .description = "packet_count", + .field_bit_size = 64, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "byte_count", + .field_bit_size = 64, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* act_tid: 2, , table: cmm_full_act_record.0 */ + { + .description = "type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "drop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "vlan_del_rpt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "vnic_or_vport", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff} + }, + { + .description = "dest_op", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "decap_func", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "mirror", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meter_ptr", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat0_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff} + }, + { + .description = "stat0_ing_egr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat0_ctr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat1_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat1_ing_egr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat1_ctr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "mod_rec_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "encap_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "src_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rsvd0", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* act_tid: 2, , table: mirror_tbl.wr */ + { + .description = "reserved1", + .field_bit_size = 21, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "arp_relative", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "action_hint", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "sample_mode", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "trunc_mode", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ignore_drop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "copy_mode", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 3} + }, + { + .description = "mirr_cond", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "act_rec_ptr", + .field_bit_size = 26, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + }, + { + .description = "reserved2", + .field_bit_size = 6, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "samp_cfg", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff} + }, + { + .description = "padding1", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* act_tid: 2, , table: shared_mirror_record.wr */ + { + .description = "rid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff} + }, + { + .description = "mirror_id", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff} + }, + /* act_tid: 3, , table: mod_record.ing_no_ttl */ + { + .description = "metadata_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rem_ovlan", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rem_ivlan", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rep_add_ivlan", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rep_add_ovlan", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ttl_update", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tun_md_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "reserved_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_dmac_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_smac_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip_ipv6_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_dip_ipv6_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip_ipv4_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_dip_ipv4_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_sport_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_dport_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr2 = { + (BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr2 = { + (BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3_sip_ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr2 = { + (BNXT_ULP_ACT_PROP_IDX_SET_IPV6_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV6_SRC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3_dip_ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr2 = { + (BNXT_ULP_ACT_PROP_IDX_SET_IPV6_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV6_DST & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3_sip_ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr2 = { + (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3_dip_ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr2 = { + (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l4_sport", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr2 = { + (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l4_dport", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr2 = { + (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + /* act_tid: 3, , table: mod_record.ing_ttl */ + { + .description = "metadata_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rem_ovlan", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rem_ivlan", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rep_add_ivlan", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rep_add_ovlan", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ttl_update", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "tun_md_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "reserved_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_dmac_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_smac_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip_ipv6_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_dip_ipv6_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip_ipv4_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_dip_ipv4_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_sport_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_dport_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "alt_pfid", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "alt_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ttl_rsvd", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ttl_tl3_dec", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, + BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff} + }, + { + .description = "ttl_il3_dec", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, + BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff} + }, + { + .description = "ttl_otl3_rdir", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ttl_tl3_rdir", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ttl_il3_rdir", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr2 = { + (BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr2 = { + (BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3_sip_ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr2 = { + (BNXT_ULP_ACT_PROP_IDX_SET_IPV6_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV6_SRC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3_dip_ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr2 = { + (BNXT_ULP_ACT_PROP_IDX_SET_IPV6_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV6_DST & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3_sip_ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr2 = { + (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3_dip_ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr2 = { + (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l4_sport", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr2 = { + (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l4_dport", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr2 = { + (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + /* act_tid: 3, , table: cmm_stat_record.0 */ + { + .description = "packet_count", + .field_bit_size = 64, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "byte_count", + .field_bit_size = 64, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* act_tid: 3, , table: cmm_full_act_record.0 */ + { + .description = "type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "drop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff} + }, + { + .description = "vlan_del_rpt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "vnic_or_vport", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO, + .field_src3 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr3 = { + (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff} + }, + { + .description = "dest_op", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "decap_func", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "mirror", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_RF, + .field_opr2 = { + (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meter_ptr", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat0_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff} + }, + { + .description = "stat0_ing_egr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat0_ctr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat1_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat1_ing_egr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat1_ctr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "mod_rec_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MODIFY_PTR & 0xff} + }, + { + .description = "encap_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "src_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rsvd0", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* act_tid: 4, , table: vnic_interface_rss_config.0 */ + /* act_tid: 4, , table: cmm_stat_record.0 */ + { + .description = "packet_count", + .field_bit_size = 64, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "byte_count", + .field_bit_size = 64, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* act_tid: 4, , table: cmm_full_act_record.0 */ + { + .description = "type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "drop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "vlan_del_rpt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "vnic_or_vport", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_RSS_VNIC >> 8) & 0xff, + BNXT_ULP_RF_IDX_RSS_VNIC & 0xff} + }, + { + .description = "dest_op", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "decap_func", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "mirror", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_RF, + .field_opr2 = { + (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meter_ptr", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat0_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff} + }, + { + .description = "stat0_ing_egr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat0_ctr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat1_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat1_ing_egr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat1_ctr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "mod_rec_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "encap_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "src_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rsvd0", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* act_tid: 6, , table: mod_record.ing_ttl */ + { + .description = "metadata_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rem_ovlan", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rem_ivlan", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rep_add_ivlan", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rep_add_ovlan", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ttl_update", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "tun_md_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "reserved_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_dmac_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_smac_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip_ipv6_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_dip_ipv6_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip_ipv4_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_dip_ipv4_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_sport_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_dport_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "alt_pfid", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "alt_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ttl_rsvd", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ttl_tl3_dec", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, + BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff} + }, + { + .description = "ttl_il3_dec", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, + BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff} + }, + { + .description = "ttl_otl3_rdir", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ttl_tl3_rdir", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ttl_il3_rdir", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* act_tid: 6, , table: cmm_stat_record.0 */ + { + .description = "packet_count", + .field_bit_size = 64, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "byte_count", + .field_bit_size = 64, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* act_tid: 6, , table: cmm_full_act_record.0 */ + { + .description = "type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "drop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff} + }, + { + .description = "vlan_del_rpt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "vnic_or_vport", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff} + }, + { + .description = "dest_op", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "decap_func", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "mirror", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meter_ptr", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat0_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff} + }, + { + .description = "stat0_ing_egr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat0_ctr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat1_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat1_ing_egr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat1_ctr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "mod_rec_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MODIFY_PTR & 0xff} + }, + { + .description = "encap_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "src_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rsvd0", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* act_tid: 7, , table: mod_record.egr_no_ttl */ + { + .description = "metadata_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rem_ovlan", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rem_ivlan", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rep_add_ivlan", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rep_add_ovlan", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ttl_update", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tun_md_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "reserved_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_dmac_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_smac_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip_ipv6_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_dip_ipv6_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip_ipv4_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_dip_ipv4_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_sport_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_dport_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr2 = { + (BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr2 = { + (BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3_sip_ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr2 = { + (BNXT_ULP_ACT_PROP_IDX_SET_IPV6_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV6_SRC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3_dip_ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr2 = { + (BNXT_ULP_ACT_PROP_IDX_SET_IPV6_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV6_DST & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3_sip_ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr2 = { + (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3_dip_ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr2 = { + (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l4_sport", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr2 = { + (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l4_dport", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr2 = { + (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + /* act_tid: 7, , table: mod_record.egr_ttl */ + { + .description = "metadata_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rem_ovlan", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rem_ivlan", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rep_add_ivlan", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rep_add_ovlan", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ttl_update", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "tun_md_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "reserved_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_dmac_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_smac_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip_ipv6_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_dip_ipv6_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip_ipv4_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_dip_ipv4_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_sport_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_dport_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "alt_pfid", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "alt_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ttl_rsvd", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ttl_tl3_dec", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, + BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff} + }, + { + .description = "ttl_il3_dec", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, + BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff} + }, + { + .description = "ttl_otl3_rdir", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ttl_tl3_rdir", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ttl_il3_rdir", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr2 = { + (BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr2 = { + (BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3_sip_ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr2 = { + (BNXT_ULP_ACT_PROP_IDX_SET_IPV6_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV6_SRC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3_dip_ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr2 = { + (BNXT_ULP_ACT_PROP_IDX_SET_IPV6_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV6_DST & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3_sip_ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr2 = { + (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3_dip_ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr2 = { + (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l4_sport", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr2 = { + (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l4_dport", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr2 = { + (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + /* act_tid: 7, , table: cmm_stat_record.0 */ + { + .description = "packet_count", + .field_bit_size = 64, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "byte_count", + .field_bit_size = 64, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* act_tid: 7, , table: cmm_full_act_record.0 */ + { + .description = "type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "drop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff} + }, + { + .description = "vlan_del_rpt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "vnic_or_vport", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff} + }, + { + .description = "dest_op", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "decap_func", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "mirror", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meter_ptr", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat0_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff} + }, + { + .description = "stat0_ing_egr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat0_ctr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat1_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat1_ing_egr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat1_ctr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "mod_rec_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MODIFY_PTR & 0xff} + }, + { + .description = "encap_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "src_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rsvd0", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* act_tid: 8, , table: cmm_stat_record.0 */ + { + .description = "packet_count", + .field_bit_size = 64, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "byte_count", + .field_bit_size = 64, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* act_tid: 8, , table: mod_record.egr_set_mac */ + { + .description = "metadata_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rem_ovlan", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rem_ivlan", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rep_add_ivlan", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rep_add_ovlan", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ttl_update", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tun_md_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "reserved_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_dmac_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_smac_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip_ipv6_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_dip_ipv6_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip_ipv4_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_dip_ipv4_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_sport_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_dport_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr2 = { + (BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr2 = { + (BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + /* act_tid: 8, , table: sp_smac_ipv4.0 */ + { + .description = "smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_ETH_SMAC & 0xff} + }, + { + .description = "ipv4_src_addr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_IPV4_SADDR >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_SADDR & 0xff} + }, + { + .description = "reserved", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* act_tid: 8, , table: source_property_cache.wr */ + { + .description = "rid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff} + }, + { + .description = "sp_rec_ptr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MAIN_SP_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_SP_PTR & 0xff} + }, + /* act_tid: 8, , table: ext_tun_vxlan_encap_record.ipv4_vxlan */ + { + .description = "ecv_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR2_SYM_ECV_VALID_YES} + }, + { + .description = "ecv_custom_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ecv_vtag_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE & 0xff} + }, + { + .description = "ecv_l2_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR2_SYM_ECV_L2_EN_YES} + }, + { + .description = "ecv_l3_type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE & 0xff} + }, + { + .description = "ecv_l4_type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR2_SYM_ECV_L4_TYPE_UDP_CSUM} + }, + { + .description = "ecv_tun_type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR2_SYM_ECV_TUN_TYPE_VXLAN} + }, + { + .description = "enc_eth_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_ETH_DMAC & 0xff} + }, + { + .description = "enc_o_vlan_tag", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr2 = { + (BNXT_ULP_ENC_FIELD_O_VLAN_TCI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_O_VLAN_TCI & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "enc_o_vlan_type", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr2 = { + (BNXT_ULP_ENC_FIELD_O_VLAN_TYPE >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_O_VLAN_TYPE & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "enc_i_vlan_tag", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr2 = { + (BNXT_ULP_ENC_FIELD_I_VLAN_TCI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_I_VLAN_TCI & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "enc_i_vlan_type", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr2 = { + (BNXT_ULP_ENC_FIELD_I_VLAN_TYPE >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_I_VLAN_TYPE & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "enc_ipv4_ihl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_IPV4_IHL >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_IHL & 0xff} + }, + { + .description = "enc_ipv4_tos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_IPV4_TOS >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_TOS & 0xff} + }, + { + .description = "enc_ipv4_pkt_id", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_IPV4_PKT_ID >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_PKT_ID & 0xff} + }, + { + .description = "enc_ipv4_frag", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_IPV4_FRAG >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_FRAG & 0xff} + }, + { + .description = "enc_ipv4_ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_IPV4_TTL >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_TTL & 0xff} + }, + { + .description = "enc_ipv4_proto", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_IPV4_PROTO >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_PROTO & 0xff} + }, + { + .description = "enc_ipv4_daddr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_IPV4_DADDR >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_DADDR & 0xff} + }, + { + .description = "enc_udp_sport", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff} + }, + { + .description = "enc_udp_dport", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff} + }, + { + .description = "enc_vxlan_flags", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_VXLAN_FLAGS >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_VXLAN_FLAGS & 0xff} + }, + { + .description = "enc_vxlan_rsvd0", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 & 0xff} + }, + { + .description = "enc_vxlan_vni", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff} + }, + { + .description = "enc_vxlan_rsvd1", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 & 0xff} + }, + /* act_tid: 8, , table: vxlan_encap_rec_cache.wr */ + { + .description = "rid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff} + }, + { + .description = "enc_rec_ptr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff} + }, + /* act_tid: 8, , table: ext_tun_geneve_encap_record.ipv4_vxlan */ + { + .description = "ecv_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR2_SYM_ECV_VALID_YES} + }, + { + .description = "ecv_custom_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ecv_vtag_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE & 0xff} + }, + { + .description = "ecv_l2_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR2_SYM_ECV_L2_EN_YES} + }, + { + .description = "ecv_l3_type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE & 0xff} + }, + { + .description = "ecv_l4_type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR2_SYM_ECV_L4_TYPE_UDP_CSUM} + }, + { + .description = "ecv_tun_type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR2_SYM_ECV_TUN_TYPE_NGE} + }, + { + .description = "enc_eth_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_ETH_DMAC & 0xff} + }, + { + .description = "enc_o_vlan_tag", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr2 = { + (BNXT_ULP_ENC_FIELD_O_VLAN_TCI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_O_VLAN_TCI & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "enc_o_vlan_type", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr2 = { + (BNXT_ULP_ENC_FIELD_O_VLAN_TYPE >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_O_VLAN_TYPE & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "enc_i_vlan_tag", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr2 = { + (BNXT_ULP_ENC_FIELD_I_VLAN_TCI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_I_VLAN_TCI & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "enc_i_vlan_type", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr2 = { + (BNXT_ULP_ENC_FIELD_I_VLAN_TYPE >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_I_VLAN_TYPE & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "enc_ipv4_ihl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_IPV4_IHL >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_IHL & 0xff} + }, + { + .description = "enc_ipv4_tos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_IPV4_TOS >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_TOS & 0xff} + }, + { + .description = "enc_ipv4_pkt_id", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_IPV4_PKT_ID >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_PKT_ID & 0xff} + }, + { + .description = "enc_ipv4_frag", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_IPV4_FRAG >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_FRAG & 0xff} + }, + { + .description = "enc_ipv4_ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_IPV4_TTL >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_TTL & 0xff} + }, + { + .description = "enc_ipv4_proto", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_IPV4_PROTO >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_PROTO & 0xff} + }, + { + .description = "enc_ipv4_daddr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_IPV4_DADDR >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_DADDR & 0xff} + }, + { + .description = "enc_udp_sport", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff} + }, + { + .description = "enc_udp_dport", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff} + }, + { + .description = "enc_geneve_ver_opt_len_o_c_rsvd0", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_GENEVE_VER_OPT_LEN_O_C_RSVD0 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_VER_OPT_LEN_O_C_RSVD0 & 0xff} + }, + { + .description = "enc_geneve_proto_type", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_GENEVE_PROTO_TYPE >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_PROTO_TYPE & 0xff} + }, + { + .description = "enc_geneve_vni", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_GENEVE_VNI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_VNI & 0xff} + }, + { + .description = "enc_geneve_rsvd1", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_GENEVE_RSVD1 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_RSVD1 & 0xff} + }, + { + .description = "enc_geneve_opt_w0", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_GENEVE_OPT_W0 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_OPT_W0 & 0xff} + }, + { + .description = "enc_geneve_opt_w1", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_GENEVE_OPT_W1 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_OPT_W1 & 0xff} + }, + { + .description = "enc_geneve_opt_w2", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_GENEVE_OPT_W2 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_OPT_W2 & 0xff} + }, + { + .description = "enc_geneve_opt_w3", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_GENEVE_OPT_W3 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_OPT_W3 & 0xff} + }, + { + .description = "enc_geneve_opt_w4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_GENEVE_OPT_W4 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_OPT_W4 & 0xff} + }, + { + .description = "enc_geneve_opt_w5", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_GENEVE_OPT_W5 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_OPT_W5 & 0xff} + }, + /* act_tid: 8, , table: ext_tun_geneve_encap_record.ipv6_geneve */ + { + .description = "ecv_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR2_SYM_ECV_VALID_YES} + }, + { + .description = "ecv_custom_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ecv_vtag_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE & 0xff} + }, + { + .description = "ecv_l2_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR2_SYM_ECV_L2_EN_YES} + }, + { + .description = "ecv_l3_type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE & 0xff} + }, + { + .description = "ecv_l4_type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR2_SYM_ECV_L4_TYPE_UDP_CSUM} + }, + { + .description = "ecv_tun_type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR2_SYM_ECV_TUN_TYPE_NGE} + }, + { + .description = "enc_eth_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_ETH_DMAC & 0xff} + }, + { + .description = "enc_o_vlan_tag", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr2 = { + (BNXT_ULP_ENC_FIELD_O_VLAN_TCI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_O_VLAN_TCI & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "enc_o_vlan_type", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr2 = { + (BNXT_ULP_ENC_FIELD_O_VLAN_TYPE >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_O_VLAN_TYPE & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "enc_i_vlan_tag", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr2 = { + (BNXT_ULP_ENC_FIELD_I_VLAN_TCI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_I_VLAN_TCI & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "enc_i_vlan_type", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr2 = { + (BNXT_ULP_ENC_FIELD_I_VLAN_TYPE >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_I_VLAN_TYPE & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "enc_ipv6_vtc", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW & 0xff} + }, + { + .description = "enc_ipv6_zero", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "enc_ipv6_proto", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_IPV6_PROTO >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV6_PROTO & 0xff} + }, + { + .description = "enc_ipv6_ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_IPV6_TTL >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV6_TTL & 0xff} + }, + { + .description = "enc_ipv6_daddr", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_IPV6_DADDR >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV6_DADDR & 0xff} + }, + { + .description = "enc_udp_sport", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff} + }, + { + .description = "enc_udp_dport", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff} + }, + { + .description = "enc_geneve_ver_opt_len_o_c_rsvd0", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_GENEVE_VER_OPT_LEN_O_C_RSVD0 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_VER_OPT_LEN_O_C_RSVD0 & 0xff} + }, + { + .description = "enc_geneve_proto_type", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_GENEVE_PROTO_TYPE >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_PROTO_TYPE & 0xff} + }, + { + .description = "enc_geneve_vni", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_GENEVE_VNI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_VNI & 0xff} + }, + { + .description = "enc_geneve_rsvd1", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_GENEVE_RSVD1 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_RSVD1 & 0xff} + }, + { + .description = "enc_geneve_opt_w0", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_GENEVE_OPT_W0 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_OPT_W0 & 0xff} + }, + { + .description = "enc_geneve_opt_w1", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_GENEVE_OPT_W1 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_OPT_W1 & 0xff} + }, + { + .description = "enc_geneve_opt_w2", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_GENEVE_OPT_W2 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_OPT_W2 & 0xff} + }, + { + .description = "enc_geneve_opt_w3", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_GENEVE_OPT_W3 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_OPT_W3 & 0xff} + }, + { + .description = "enc_geneve_opt_w4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_GENEVE_OPT_W4 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_OPT_W4 & 0xff} + }, + { + .description = "enc_geneve_opt_w5", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_GENEVE_OPT_W5 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_OPT_W5 & 0xff} + }, + /* act_tid: 8, , table: geneve_encap_rec_cache.wr */ + { + .description = "rid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff} + }, + { + .description = "enc_rec_ptr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff} + }, + /* act_tid: 8, , table: cmm_full_act_record.0 */ + { + .description = "type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "drop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff} + }, + { + .description = "vlan_del_rpt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "vnic_or_vport", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff} + }, + { + .description = "dest_op", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "decap_func", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "mirror", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meter_ptr", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat0_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff} + }, + { + .description = "stat0_ing_egr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat0_ctr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat1_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat1_ing_egr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat1_ctr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "mod_rec_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MODIFY_PTR & 0xff} + }, + { + .description = "encap_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff} + }, + { + .description = "src_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MAIN_SP_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_SP_PTR & 0xff} + }, + { + .description = "rsvd0", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } +}; + +struct bnxt_ulp_mapper_ident_info ulp_thor2_act_ident_list[] = { + /* act_tid: 1, , table: shared_mirror_record.rd */ + { + .description = "mirror_id", + .regfile_idx = BNXT_ULP_RF_IDX_MIRROR_ID_0, + .ident_bit_size = 5, + .ident_bit_pos = 32 + }, + /* act_tid: 2, , table: shared_mirror_record.del_chk */ + { + .description = "rid", + .regfile_idx = BNXT_ULP_RF_IDX_RID, + .ident_bit_size = 32, + .ident_bit_pos = 0 + }, + /* act_tid: 3, , table: shared_mirror_record.rd */ + { + .description = "mirror_id", + .regfile_idx = BNXT_ULP_RF_IDX_MIRROR_ID_0, + .ident_bit_size = 5, + .ident_bit_pos = 32 + }, + /* act_tid: 4, , table: shared_mirror_record.rd */ + { + .description = "mirror_id", + .regfile_idx = BNXT_ULP_RF_IDX_MIRROR_ID_0, + .ident_bit_size = 5, + .ident_bit_pos = 32 + }, + /* act_tid: 8, , table: source_property_cache.rd */ + { + .description = "sp_rec_ptr", + .regfile_idx = BNXT_ULP_RF_IDX_MAIN_SP_PTR, + .ident_bit_size = 32, + .ident_bit_pos = 32 + }, + /* act_tid: 8, , table: vxlan_encap_rec_cache.rd */ + { + .description = "enc_rec_ptr", + .regfile_idx = BNXT_ULP_RF_IDX_ENCAP_PTR_0, + .ident_bit_size = 32, + .ident_bit_pos = 32 + }, + /* act_tid: 8, , table: geneve_encap_rec_cache.rd */ + { + .description = "enc_rec_ptr", + .regfile_idx = BNXT_ULP_RF_IDX_ENCAP_PTR_0, + .ident_bit_size = 32, + .ident_bit_pos = 32 + } +}; diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor2_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor2_class.c new file mode 100644 index 0000000000..e334c8448e --- /dev/null +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor2_class.c @@ -0,0 +1,51668 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2014-2024 Broadcom + * All rights reserved. + */ + +#include "ulp_template_db_enum.h" +#include "ulp_template_db_field.h" +#include "ulp_template_struct.h" +#include "ulp_template_db_tbl.h" + +/* Mapper templates for header class list */ +struct bnxt_ulp_mapper_tmpl_info ulp_thor2_class_tmpl_list[] = { + /* class_tid: 1, ingress */ + [1] = { + .device_name = BNXT_ULP_DEVICE_ID_THOR2, + .num_tbls = 30, + .start_tbl_idx = 0, + .reject_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, + .cond_start_idx = 0, + .cond_nums = 0 } + }, + /* class_tid: 2, egress */ + [2] = { + .device_name = BNXT_ULP_DEVICE_ID_THOR2, + .num_tbls = 20, + .start_tbl_idx = 30, + .reject_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, + .cond_start_idx = 1606, + .cond_nums = 0 } + }, + /* class_tid: 3, ingress */ + [3] = { + .device_name = BNXT_ULP_DEVICE_ID_THOR2, + .num_tbls = 38, + .start_tbl_idx = 50, + .reject_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, + .cond_start_idx = 3181, + .cond_nums = 0 } + }, + /* class_tid: 4, egress */ + [4] = { + .device_name = BNXT_ULP_DEVICE_ID_THOR2, + .num_tbls = 19, + .start_tbl_idx = 88, + .reject_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, + .cond_start_idx = 3186, + .cond_nums = 0 } + } +}; + +struct bnxt_ulp_mapper_tbl_info ulp_thor2_class_tbl_list[] = { + { /* class_tid: 1, , table: port_table.get_def_rd */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 0, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .key_start_idx = 0, + .blob_key_bit_size = 10, + .key_bit_size = 10, + .key_num_fields = 1, + .ident_start_idx = 0, + .ident_nums = 2 + }, + { /* class_tid: 1, , table: l2_cntxt_tcam_cache.def_rd */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 0, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .key_start_idx = 1, + .blob_key_bit_size = 11, + .key_bit_size = 11, + .key_num_fields = 1, + .ident_start_idx = 2, + .ident_nums = 1 + }, + { /* class_tid: 1, , table: control.check_f1_f2_flow */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 6, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 0, + .cond_nums = 2 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP + }, + { /* class_tid: 1, , table: tunnel_cache.f1_f2_rd */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 2, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .key_start_idx = 2, + .blob_key_bit_size = 19, + .key_bit_size = 19, + .key_num_fields = 2, + .ident_start_idx = 3, + .ident_nums = 1 + }, + { /* class_tid: 1, , table: control.tunnel_cache_check */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 3, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 2, + .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID + }, + { /* class_tid: 1, , table: l2_cntxt_tcam.f1_f2_alloc_l2_cntxt */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 3, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_IDENT, + .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, + .key_start_idx = 4, + .blob_key_bit_size = 256, + .key_bit_size = 256, + .key_num_fields = 24, + .result_start_idx = 0, + .result_bit_size = 127, + .result_num_fields = 17, + .ident_start_idx = 4, + .ident_nums = 1 + }, + { /* class_tid: 1, , table: tunnel_cache.f1_f2_wr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 3, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .key_start_idx = 28, + .blob_key_bit_size = 19, + .key_bit_size = 19, + .key_num_fields = 2, + .result_start_idx = 17, + .result_bit_size = 52, + .result_num_fields = 3 + }, + { /* class_tid: 1, , table: control.check_f2_flow */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 5, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 3, + .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP + }, + { /* class_tid: 1, , table: mac_addr_cache.l2_table_rd */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 4, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .key_start_idx = 30, + .blob_key_bit_size = 131, + .key_bit_size = 131, + .key_num_fields = 9, + .ident_start_idx = 5, + .ident_nums = 1 + }, + { /* class_tid: 1, , table: control.mac_addr_cache_check */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 3, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 12, + .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID + }, + { /* class_tid: 1, , table: l2_cntxt_tcam.l2_table_create */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = CFA_RSUBTYPE_TCAM_L2CTX, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 13, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .pri_opcode = BNXT_ULP_PRI_OPC_APP_PRI_OR_CONST, + .pri_operand = ULP_THOR2_SYM_L2_CTXT_PRI_APP, + .key_start_idx = 39, + .blob_key_bit_size = 256, + .key_bit_size = 256, + .key_num_fields = 24, + .result_start_idx = 20, + .result_bit_size = 127, + .result_num_fields = 17, + .ident_start_idx = 6, + .ident_nums = 1 + }, + { /* class_tid: 1, , table: mac_addr_cache.l2_table_wr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 23, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .key_start_idx = 63, + .blob_key_bit_size = 131, + .key_bit_size = 131, + .key_num_fields = 9, + .result_start_idx = 37, + .result_bit_size = 92, + .result_num_fields = 5 + }, + { /* class_tid: 1, , table: proto_header_cache.rd */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROTO_HEADER, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 31, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .key_start_idx = 72, + .blob_key_bit_size = 74, + .key_bit_size = 74, + .key_num_fields = 3, + .ident_start_idx = 7, + .ident_nums = 5 + }, + { /* class_tid: 1, , table: control.proto_header_cache_miss */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 9, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 31, + .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID + }, + { /* class_tid: 1, , table: hdr_overlap_cache.overlap_check */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_HDR_OVERLAP, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 32, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_SEARCH_OVERLAP, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_SEQ, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .key_start_idx = 75, + .blob_key_bit_size = 10, + .key_bit_size = 10, + .key_num_fields = 2, + .result_start_idx = 42, + .result_bit_size = 96, + .result_num_fields = 2 + }, + { /* class_tid: 1, , table: control.overlap_miss */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1023, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 32, + .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID_1 + }, + { /* class_tid: 1, , table: hdr_overlap_cache.overlap_wr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_HDR_OVERLAP, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 33, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_SIMPLE_WRITE, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_SEQ, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .key_start_idx = 77, + .blob_key_bit_size = 10, + .key_bit_size = 10, + .key_num_fields = 2, + .result_start_idx = 44, + .result_bit_size = 96, + .result_num_fields = 2 + }, + { /* class_tid: 1, , table: fkb_select.wc_gen_template */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = CFA_RSUBTYPE_IDX_TBL_WC_FKB, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 33, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_WC_KEY_ID_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .result_start_idx = 46, + .result_bit_size = 256, + .result_num_fields = 172 + }, + { /* class_tid: 1, , table: wm_key_recipe.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_KEY_RECIPE_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_KEY_RECIPE_TABLE_WM, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 287, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_KEY_RECIPE_TBL_OPC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_WC_KEY_ID_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .key_start_idx = 79, + .blob_key_bit_size = 0, + .key_bit_size = 0, + .key_num_fields = 32, + .result_start_idx = 218, + .result_bit_size = 0, + .result_num_fields = 0 + }, + { /* class_tid: 1, , table: fkb_select.em_gen_template_alloc */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = CFA_RSUBTYPE_IDX_TBL_EM_FKB, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 679, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_EM_KEY_ID_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .result_start_idx = 218, + .result_bit_size = 256, + .result_num_fields = 172 + }, + { /* class_tid: 1, , table: profile_tcam.gen_template */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = CFA_RSUBTYPE_TCAM_PROF_TCAM, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 679, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .pri_opcode = BNXT_ULP_PRI_OPC_APP_PRI_OR_CONST, + .pri_operand = ULP_THOR2_SYM_PROF_TCAM_PRI_APP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .key_start_idx = 111, + .blob_key_bit_size = 256, + .key_bit_size = 256, + .key_num_fields = 66, + .result_start_idx = 390, + .result_bit_size = 64, + .result_num_fields = 10, + .ident_start_idx = 12, + .ident_nums = 2 + }, + { /* class_tid: 1, , table: proto_header_cache.wr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROTO_HEADER, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 940, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .key_start_idx = 177, + .blob_key_bit_size = 74, + .key_bit_size = 74, + .key_num_fields = 3, + .result_start_idx = 400, + .result_bit_size = 74, + .result_num_fields = 6 + }, + { /* class_tid: 1, , table: em_flow_conflict_cache.rd */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_EM_FLOW_CONFLICT, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 7, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 940, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .key_start_idx = 180, + .blob_key_bit_size = 74, + .key_bit_size = 74, + .key_num_fields = 3, + .ident_start_idx = 14, + .ident_nums = 1 + }, + { /* class_tid: 1, , table: control.em_flow_conflict_cache_miss */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 4, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 941, + .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID + }, + { /* class_tid: 1, , table: fkb_select.em_gen_template */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = CFA_RSUBTYPE_IDX_TBL_EM_FKB, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 942, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_EM_KEY_ID_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .result_start_idx = 406, + .result_bit_size = 256, + .result_num_fields = 172 + }, + { /* class_tid: 1, , table: em_key_recipe.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_KEY_RECIPE_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_KEY_RECIPE_TABLE_EM, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 1199, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_KEY_RECIPE_TBL_OPC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_EM_KEY_ID_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .key_start_idx = 183, + .blob_key_bit_size = 0, + .key_bit_size = 0, + .key_num_fields = 33, + .result_start_idx = 578, + .result_bit_size = 0, + .result_num_fields = 0 + }, + { /* class_tid: 1, , table: em_flow_conflict_cache.wr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_EM_FLOW_CONFLICT, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 2, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 1603, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .key_start_idx = 216, + .blob_key_bit_size = 74, + .key_bit_size = 74, + .key_num_fields = 3, + .result_start_idx = 578, + .result_bit_size = 96, + .result_num_fields = 2 + }, + { /* class_tid: 1, , table: control.field_sig_validation */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1023, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 1603, + .cond_nums = 2 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .func_info = { + .func_opc = BNXT_ULP_FUNC_OPC_EQ, + .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE, + .func_opr1 = BNXT_ULP_RF_IDX_FLOW_SIG_ID, + .func_src2 = BNXT_ULP_FUNC_SRC_COMP_FIELD, + .func_opr2 = BNXT_ULP_CF_IDX_FLOW_SIG_ID, + .func_dst_opr = BNXT_ULP_RF_IDX_CC } + }, + { /* class_tid: 1, , table: em_normal.ingress_generic_template */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_MEM_INTERNAL, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 0, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 1605, + .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_DYN_KEY, + .key_recipe_operand = BNXT_ULP_RF_IDX_EM_KEY_ID_0, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, + .result_start_idx = 580, + .result_bit_size = 0, + .result_num_fields = 17 + }, + { /* class_tid: 1, , table: wm_normal.ingress_generic_template */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = CFA_RSUBTYPE_TCAM_WC, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 0, + .cond_false_goto = 0, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 1606, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_DYN_KEY, + .key_recipe_operand = BNXT_ULP_RF_IDX_WC_KEY_ID_0, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, + .result_start_idx = 597, + .result_bit_size = 128, + .result_num_fields = 15 + }, + { /* class_tid: 2, , table: port_table.get_def_rd */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 1606, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .key_start_idx = 219, + .blob_key_bit_size = 10, + .key_bit_size = 10, + .key_num_fields = 1, + .ident_start_idx = 15, + .ident_nums = 1 + }, + { /* class_tid: 2, , table: l2_cntxt_tcam_cache.def_rd */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 1606, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .key_start_idx = 220, + .blob_key_bit_size = 11, + .key_bit_size = 11, + .key_num_fields = 1, + .ident_start_idx = 16, + .ident_nums = 2 + }, + { /* class_tid: 2, , table: proto_header_cache.rd */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROTO_HEADER, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 1606, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .key_start_idx = 221, + .blob_key_bit_size = 74, + .key_bit_size = 74, + .key_num_fields = 3, + .ident_start_idx = 18, + .ident_nums = 5 + }, + { /* class_tid: 2, , table: control.proto_header_cache_miss */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 9, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 1606, + .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID + }, + { /* class_tid: 2, , table: hdr_overlap_cache.overlap_check */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_HDR_OVERLAP, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 1607, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_SEARCH_OVERLAP, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_SEQ, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .key_start_idx = 224, + .blob_key_bit_size = 10, + .key_bit_size = 10, + .key_num_fields = 2, + .result_start_idx = 612, + .result_bit_size = 96, + .result_num_fields = 2 + }, + { /* class_tid: 2, , table: control.overlap_miss */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1023, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 1607, + .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID_1 + }, + { /* class_tid: 2, , table: hdr_overlap_cache.overlap_wr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_HDR_OVERLAP, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 1608, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_SIMPLE_WRITE, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_SEQ, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .key_start_idx = 226, + .blob_key_bit_size = 10, + .key_bit_size = 10, + .key_num_fields = 2, + .result_start_idx = 614, + .result_bit_size = 96, + .result_num_fields = 2 + }, + { /* class_tid: 2, , table: fkb_select.wc_gen_template */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = CFA_RSUBTYPE_IDX_TBL_WC_FKB, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 1608, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_WC_KEY_ID_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .result_start_idx = 616, + .result_bit_size = 256, + .result_num_fields = 172 + }, + { /* class_tid: 2, , table: wm_key_recipe.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_KEY_RECIPE_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_KEY_RECIPE_TABLE_WM, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 1862, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_KEY_RECIPE_TBL_OPC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_WC_KEY_ID_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .key_start_idx = 228, + .blob_key_bit_size = 0, + .key_bit_size = 0, + .key_num_fields = 32, + .result_start_idx = 788, + .result_bit_size = 0, + .result_num_fields = 0 + }, + { /* class_tid: 2, , table: fkb_select.em_gen_template_alloc */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = CFA_RSUBTYPE_IDX_TBL_EM_FKB, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 2254, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_EM_KEY_ID_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .result_start_idx = 788, + .result_bit_size = 256, + .result_num_fields = 172 + }, + { /* class_tid: 2, , table: profile_tcam.gen_template */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = CFA_RSUBTYPE_TCAM_PROF_TCAM, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 2254, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .pri_opcode = BNXT_ULP_PRI_OPC_APP_PRI_OR_CONST, + .pri_operand = ULP_THOR2_SYM_PROF_TCAM_PRI_APP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .key_start_idx = 260, + .blob_key_bit_size = 256, + .key_bit_size = 256, + .key_num_fields = 66, + .result_start_idx = 960, + .result_bit_size = 64, + .result_num_fields = 10, + .ident_start_idx = 23, + .ident_nums = 2 + }, + { /* class_tid: 2, , table: proto_header_cache.wr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROTO_HEADER, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 2515, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .key_start_idx = 326, + .blob_key_bit_size = 74, + .key_bit_size = 74, + .key_num_fields = 3, + .result_start_idx = 970, + .result_bit_size = 74, + .result_num_fields = 6 + }, + { /* class_tid: 2, , table: em_flow_conflict_cache.rd */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_EM_FLOW_CONFLICT, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 7, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 2515, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .key_start_idx = 329, + .blob_key_bit_size = 74, + .key_bit_size = 74, + .key_num_fields = 3, + .ident_start_idx = 25, + .ident_nums = 1 + }, + { /* class_tid: 2, , table: control.em_flow_conflict_cache_miss */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 4, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 2516, + .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID + }, + { /* class_tid: 2, , table: fkb_select.em_gen_template */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = CFA_RSUBTYPE_IDX_TBL_EM_FKB, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 2517, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_EM_KEY_ID_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .result_start_idx = 976, + .result_bit_size = 256, + .result_num_fields = 172 + }, + { /* class_tid: 2, , table: em_key_recipe.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_KEY_RECIPE_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_KEY_RECIPE_TABLE_EM, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 2774, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_KEY_RECIPE_TBL_OPC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_EM_KEY_ID_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .key_start_idx = 332, + .blob_key_bit_size = 0, + .key_bit_size = 0, + .key_num_fields = 33, + .result_start_idx = 1148, + .result_bit_size = 0, + .result_num_fields = 0 + }, + { /* class_tid: 2, , table: em_flow_conflict_cache.wr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_EM_FLOW_CONFLICT, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 2, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 3178, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .key_start_idx = 365, + .blob_key_bit_size = 74, + .key_bit_size = 74, + .key_num_fields = 3, + .result_start_idx = 1148, + .result_bit_size = 96, + .result_num_fields = 2 + }, + { /* class_tid: 2, , table: control.field_sig_validation */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1023, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 3178, + .cond_nums = 2 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .func_info = { + .func_opc = BNXT_ULP_FUNC_OPC_EQ, + .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE, + .func_opr1 = BNXT_ULP_RF_IDX_FLOW_SIG_ID, + .func_src2 = BNXT_ULP_FUNC_SRC_COMP_FIELD, + .func_opr2 = BNXT_ULP_CF_IDX_FLOW_SIG_ID, + .func_dst_opr = BNXT_ULP_RF_IDX_CC } + }, + { /* class_tid: 2, , table: em_normal.egress_generic_template */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_MEM_INTERNAL, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 0, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 3180, + .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_DYN_KEY, + .key_recipe_operand = BNXT_ULP_RF_IDX_EM_KEY_ID_0, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, + .result_start_idx = 1150, + .result_bit_size = 0, + .result_num_fields = 17 + }, + { /* class_tid: 2, , table: wm_normal.egress_generic_template */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = CFA_RSUBTYPE_TCAM_WC, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 0, + .cond_false_goto = 0, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 3181, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_DYN_KEY, + .key_recipe_operand = BNXT_ULP_RF_IDX_WC_KEY_ID_0, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, + .result_start_idx = 1167, + .result_bit_size = 128, + .result_num_fields = 15 + }, + { /* class_tid: 3, , table: metadata_record.act_rx_wr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = CFA_RSUBTYPE_IDX_TBL_METADATA_ACT, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_CFA_TBLS, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 3181, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, + .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_METADATA_RX_ACT_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .result_start_idx = 1182, + .result_bit_size = 32, + .result_num_fields = 1 + }, + { /* class_tid: 3, , table: metadata_record.prof_rx_wr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = CFA_RSUBTYPE_IDX_TBL_METADATA_PROF, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_CFA_TBLS, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 3181, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, + .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_METADATA_RX_PROF_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .result_start_idx = 1183, + .result_bit_size = 32, + .result_num_fields = 1 + }, + { /* class_tid: 3, , table: metadata_record.lkup_rx_wr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = CFA_RSUBTYPE_IDX_TBL_METADATA_LKUP, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_CFA_TBLS, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 3181, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, + .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_METADATA_RX_LKUP_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .result_start_idx = 1184, + .result_bit_size = 32, + .result_num_fields = 1 + }, + { /* class_tid: 3, , table: metadata_record.act_tx_wr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = CFA_RSUBTYPE_IDX_TBL_METADATA_ACT, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_CFA_TBLS, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 3181, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, + .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_METADATA_TX_ACT_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .result_start_idx = 1185, + .result_bit_size = 32, + .result_num_fields = 1 + }, + { /* class_tid: 3, , table: metadata_record.prof_tx_wr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = CFA_RSUBTYPE_IDX_TBL_METADATA_PROF, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_CFA_TBLS, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 3181, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, + .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_METADATA_TX_PROF_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .result_start_idx = 1186, + .result_bit_size = 32, + .result_num_fields = 1 + }, + { /* class_tid: 3, , table: metadata_record.lkup_tx_wr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = CFA_RSUBTYPE_IDX_TBL_METADATA_LKUP, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_CFA_TBLS, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 3181, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, + .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_METADATA_TX_LKUP_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .result_start_idx = 1187, + .result_bit_size = 32, + .result_num_fields = 1 + }, + { /* class_tid: 3, , table: table_scope_cache.tsid_ing_rd */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TABLE_SCOPE_CACHE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 3181, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .key_start_idx = 368, + .blob_key_bit_size = 6, + .key_bit_size = 6, + .key_num_fields = 2, + .ident_start_idx = 26, + .ident_nums = 2 + }, + { /* class_tid: 3, , table: control.ts_ing_rd_check */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 7, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 3181, + .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID + }, + { /* class_tid: 3, , table: cmm_full_act_record.ing_default_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CMM_TABLE, + .resource_type = CFA_RSUBTYPE_CMM_ACT, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CMM_TABLE_ACT, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 3182, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_CMM_ACT_HNDL, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .result_start_idx = 1188, + .result_bit_size = 192, + .result_num_fields = 18 + }, + { /* class_tid: 3, , table: cmm_full_act_record.egr_default_1 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CMM_TABLE, + .resource_type = CFA_RSUBTYPE_CMM_ACT, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CMM_TABLE_ACT, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 3182, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_CMM_ACT_HNDL, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .result_start_idx = 1206, + .result_bit_size = 192, + .result_num_fields = 18 + }, + { /* class_tid: 3, , table: cmm_full_act_record.ing_default_1 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CMM_TABLE, + .resource_type = CFA_RSUBTYPE_CMM_ACT, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CMM_TABLE_ACT, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 3182, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_CMM_ACT_HNDL, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .result_start_idx = 1224, + .result_bit_size = 192, + .result_num_fields = 18 + }, + { /* class_tid: 3, , table: control.act_handle_to_offset */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 3182, + .cond_nums = 0 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .func_info = { + .func_opc = BNXT_ULP_FUNC_OPC_HANDLE_TO_OFFSET, + .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE, + .func_opr1 = BNXT_ULP_RF_IDX_CMM_ACT_HNDL, + .func_src2 = BNXT_ULP_FUNC_SRC_CONST, + .func_opr2 = 32, + .func_dst_opr = BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR } + }, + { /* class_tid: 3, , table: profile_tcam_bypass.ing_catch_all */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = CFA_RSUBTYPE_TCAM_PROF_TCAM, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 3182, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .pri_opcode = BNXT_ULP_PRI_OPC_APP_PRI_OR_CONST, + .pri_operand = ULP_THOR2_SYM_PROF_TCAM_PRI_CATCHALL, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .key_start_idx = 370, + .blob_key_bit_size = 256, + .key_bit_size = 256, + .key_num_fields = 66, + .result_start_idx = 1242, + .result_bit_size = 65, + .result_num_fields = 7, + .ident_start_idx = 28, + .ident_nums = 1 + }, + { /* class_tid: 3, , table: table_scope_cache.tsid_ing_wr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TABLE_SCOPE_CACHE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 3182, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .key_start_idx = 436, + .blob_key_bit_size = 6, + .key_bit_size = 6, + .key_num_fields = 2, + .result_start_idx = 1249, + .result_bit_size = 88, + .result_num_fields = 5 + }, + { /* class_tid: 3, , table: port_table.ing_wr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 3182, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .key_start_idx = 438, + .blob_key_bit_size = 10, + .key_bit_size = 10, + .key_num_fields = 1, + .result_start_idx = 1254, + .result_bit_size = 169, + .result_num_fields = 6 + }, + { /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_rd */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 3182, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .key_start_idx = 439, + .blob_key_bit_size = 11, + .key_bit_size = 11, + .key_num_fields = 1, + .ident_start_idx = 29, + .ident_nums = 0 + }, + { /* class_tid: 3, , table: control.ing_rd_check */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 3, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 3182, + .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID + }, + { /* class_tid: 3, , table: l2_cntxt_tcam.svif_ing */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = CFA_RSUBTYPE_TCAM_L2CTX, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 3183, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .pri_opcode = BNXT_ULP_PRI_OPC_APP_PRI_OR_CONST, + .pri_operand = ULP_THOR2_SYM_L2_CTXT_PRI_CATCHALL, + .key_start_idx = 440, + .blob_key_bit_size = 256, + .key_bit_size = 256, + .key_num_fields = 24, + .result_start_idx = 1260, + .result_bit_size = 127, + .result_num_fields = 17, + .ident_start_idx = 29, + .ident_nums = 1 + }, + { /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_wr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 3183, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .key_start_idx = 464, + .blob_key_bit_size = 11, + .key_bit_size = 11, + .key_num_fields = 1, + .result_start_idx = 1277, + .result_bit_size = 92, + .result_num_fields = 5 + }, + { /* class_tid: 3, , table: cmm_full_act_record.egr_default_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CMM_TABLE, + .resource_type = CFA_RSUBTYPE_CMM_ACT, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CMM_TABLE_ACT, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 3183, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_CMM_ACT_HNDL, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .result_start_idx = 1282, + .result_bit_size = 192, + .result_num_fields = 18 + }, + { /* class_tid: 3, , table: ilt_tbl.egr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, + .resource_type = CFA_RSUBTYPE_IF_TBL_ILT, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 3183, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, + .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_SVIF, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .func_info = { + .func_opc = BNXT_ULP_FUNC_OPC_HANDLE_TO_OFFSET, + .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE, + .func_opr1 = BNXT_ULP_RF_IDX_CMM_ACT_HNDL, + .func_src2 = BNXT_ULP_FUNC_SRC_CONST, + .func_opr2 = 32, + .func_dst_opr = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR }, + .result_start_idx = 1300, + .result_bit_size = 128, + .result_num_fields = 14 + }, + { /* class_tid: 3, , table: cmm_full_act_record.egr_default_2 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CMM_TABLE, + .resource_type = CFA_RSUBTYPE_CMM_ACT, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CMM_TABLE_ACT, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 3183, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_CMM_ACT_HNDL, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .result_start_idx = 1314, + .result_bit_size = 192, + .result_num_fields = 18, + .encap_num_fields = 0 + }, + { /* class_tid: 3, , table: port_table.egr_wr_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 3183, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .func_info = { + .func_opc = BNXT_ULP_FUNC_OPC_HANDLE_TO_OFFSET, + .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE, + .func_opr1 = BNXT_ULP_RF_IDX_CMM_ACT_HNDL, + .func_src2 = BNXT_ULP_FUNC_SRC_CONST, + .func_opr2 = 32, + .func_dst_opr = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR }, + .key_start_idx = 465, + .blob_key_bit_size = 10, + .key_bit_size = 10, + .key_num_fields = 1, + .result_start_idx = 1332, + .result_bit_size = 169, + .result_num_fields = 6 + }, + { /* class_tid: 3, , table: control.vfr_mark_bd_act_set */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 3183, + .cond_nums = 0 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .func_info = { + .func_opc = BNXT_ULP_FUNC_OPC_BD_ACT_SET, + .func_src1 = BNXT_ULP_FUNC_SRC_COMP_FIELD, + .func_opr1 = BNXT_ULP_CF_IDX_DEV_PORT_ID, + .func_src2 = BNXT_ULP_FUNC_SRC_REGFILE, + .func_opr2 = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .func_dst_opr = BNXT_ULP_RF_IDX_CC } + }, + { /* class_tid: 3, , table: control.egr_vfr_check_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 9, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 3183, + .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP + }, + { /* class_tid: 3, , table: table_scope_cache.tsid_vfr_rd */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TABLE_SCOPE_CACHE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 3184, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .key_start_idx = 466, + .blob_key_bit_size = 6, + .key_bit_size = 6, + .key_num_fields = 2, + .ident_start_idx = 30, + .ident_nums = 1 + }, + { /* class_tid: 3, , table: control.tsid_vfr_rd_check */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 0, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 3184, + .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID + }, + { /* class_tid: 3, , table: mod_record.svif2meta */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CMM_TABLE, + .resource_type = CFA_RSUBTYPE_CMM_ACT, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CMM_TABLE_ACT, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 3185, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_CMM_MOD_HNDL, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .result_start_idx = 1338, + .result_bit_size = 0, + .result_num_fields = 0, + .encap_num_fields = 20 + }, + { /* class_tid: 3, , table: control.mod_handle_to_offset_svif2meta */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 3185, + .cond_nums = 0 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .func_info = { + .func_opc = BNXT_ULP_FUNC_OPC_HANDLE_TO_OFFSET, + .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE, + .func_opr1 = BNXT_ULP_RF_IDX_CMM_MOD_HNDL, + .func_src2 = BNXT_ULP_FUNC_SRC_CONST, + .func_opr2 = 8, + .func_dst_opr = BNXT_ULP_RF_IDX_MODIFY_PTR } + }, + { /* class_tid: 3, , table: cmm_full_act_record.ing_vf2vf */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CMM_TABLE, + .resource_type = CFA_RSUBTYPE_CMM_ACT, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CMM_TABLE_ACT, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 3185, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_CMM_ACT_HNDL, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .result_start_idx = 1358, + .result_bit_size = 192, + .result_num_fields = 18 + }, + { /* class_tid: 3, , table: control.act_handle_to_offset_ing_vf2vf */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 3185, + .cond_nums = 0 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .func_info = { + .func_opc = BNXT_ULP_FUNC_OPC_HANDLE_TO_OFFSET, + .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE, + .func_opr1 = BNXT_ULP_RF_IDX_CMM_ACT_HNDL, + .func_src2 = BNXT_ULP_FUNC_SRC_CONST, + .func_opr2 = 32, + .func_dst_opr = BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR } + }, + { /* class_tid: 3, , table: l2_cntxt_tcam.vf2vf_ing */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = CFA_RSUBTYPE_TCAM_L2CTX, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 3185, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .pri_opcode = BNXT_ULP_PRI_OPC_APP_PRI_OR_CONST, + .pri_operand = ULP_THOR2_SYM_L2_CTXT_PRI_APP, + .key_start_idx = 468, + .blob_key_bit_size = 256, + .key_bit_size = 256, + .key_num_fields = 24, + .result_start_idx = 1376, + .result_bit_size = 127, + .result_num_fields = 17, + .ident_start_idx = 31, + .ident_nums = 1 + }, + { /* class_tid: 3, , table: table_scope_cache.tsid_vfr_wr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TABLE_SCOPE_CACHE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 0, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 3185, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .key_start_idx = 492, + .blob_key_bit_size = 6, + .key_bit_size = 6, + .key_num_fields = 2, + .result_start_idx = 1393, + .result_bit_size = 88, + .result_num_fields = 5 + }, + { /* class_tid: 3, , table: l2_cntxt_tcam_cache.no_vfr_egr_rd */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 3185, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .key_start_idx = 494, + .blob_key_bit_size = 11, + .key_bit_size = 11, + .key_num_fields = 1, + .ident_start_idx = 32, + .ident_nums = 0 + }, + { /* class_tid: 3, , table: control.no_vfr_egr_rd_check */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 0, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 3185, + .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID + }, + { /* class_tid: 3, , table: l2_cntxt_tcam.no_vfr_svif_egr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = CFA_RSUBTYPE_TCAM_L2CTX, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 3186, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .pri_opcode = BNXT_ULP_PRI_OPC_APP_PRI_OR_CONST, + .pri_operand = ULP_THOR2_SYM_L2_CTXT_PRI_CATCHALL, + .key_start_idx = 495, + .blob_key_bit_size = 256, + .key_bit_size = 256, + .key_num_fields = 24, + .result_start_idx = 1398, + .result_bit_size = 127, + .result_num_fields = 17, + .ident_start_idx = 32, + .ident_nums = 2 + }, + { /* class_tid: 3, , table: profile_tcam_bypass.no_vfr_egr_catch_all */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = CFA_RSUBTYPE_TCAM_PROF_TCAM, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 3186, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .pri_opcode = BNXT_ULP_PRI_OPC_APP_PRI_OR_CONST, + .pri_operand = ULP_THOR2_SYM_PROF_TCAM_PRI_CATCHALL, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .key_start_idx = 519, + .blob_key_bit_size = 256, + .key_bit_size = 256, + .key_num_fields = 66, + .result_start_idx = 1415, + .result_bit_size = 65, + .result_num_fields = 7 + }, + { /* class_tid: 3, , table: l2_cntxt_tcam_cache.no_vfr_egr_wr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 0, + .cond_false_goto = 0, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 3186, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .key_start_idx = 585, + .blob_key_bit_size = 11, + .key_bit_size = 11, + .key_num_fields = 1, + .result_start_idx = 1422, + .result_bit_size = 92, + .result_num_fields = 5 + }, + { /* class_tid: 4, , table: table_scope_cache.tsid_vfr_egr_rd */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TABLE_SCOPE_CACHE, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 3186, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .key_start_idx = 586, + .blob_key_bit_size = 6, + .key_bit_size = 6, + .key_num_fields = 2, + .ident_start_idx = 34, + .ident_nums = 3 + }, + { /* class_tid: 4, , table: control.tsid_vfr_egr_check */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 7, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 3186, + .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID + }, + { /* class_tid: 4, , table: mod_record.meta2uplink */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CMM_TABLE, + .resource_type = CFA_RSUBTYPE_CMM_ACT, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CMM_TABLE_ACT, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 3187, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_CMM_MOD_HNDL, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .func_info = { + .func_opc = BNXT_ULP_FUNC_OPC_BIT_OR, + .func_src1 = BNXT_ULP_FUNC_SRC_COMP_FIELD, + .func_opr1 = BNXT_ULP_CF_IDX_DRV_FUNC_VNIC, + .func_src2 = BNXT_ULP_FUNC_SRC_CONST, + .func_opr2 = ULP_THOR2_SYM_VF_2_VF_META_VAL, + .func_dst_opr = BNXT_ULP_RF_IDX_RF_0 }, + .result_start_idx = 1427, + .result_bit_size = 0, + .result_num_fields = 0, + .encap_num_fields = 20 + }, + { /* class_tid: 4, , table: control.mod_handle_to_offset_meta2uplink */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 3187, + .cond_nums = 0 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .func_info = { + .func_opc = BNXT_ULP_FUNC_OPC_HANDLE_TO_OFFSET, + .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE, + .func_opr1 = BNXT_ULP_RF_IDX_CMM_MOD_HNDL, + .func_src2 = BNXT_ULP_FUNC_SRC_CONST, + .func_opr2 = 8, + .func_dst_opr = BNXT_ULP_RF_IDX_MODIFY_PTR } + }, + { /* class_tid: 4, , table: cmm_full_act_record.endpoint_def_act */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CMM_TABLE, + .resource_type = CFA_RSUBTYPE_CMM_ACT, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CMM_TABLE_ACT, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 3187, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_CMM_ACT_HNDL, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .result_start_idx = 1447, + .result_bit_size = 192, + .result_num_fields = 18 + }, + { /* class_tid: 4, , table: control.act_handle_to_offset_endpoint_def_act */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 3187, + .cond_nums = 0 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .func_info = { + .func_opc = BNXT_ULP_FUNC_OPC_HANDLE_TO_OFFSET, + .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE, + .func_opr1 = BNXT_ULP_RF_IDX_CMM_ACT_HNDL, + .func_src2 = BNXT_ULP_FUNC_SRC_CONST, + .func_opr2 = 32, + .func_dst_opr = BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR } + }, + { /* class_tid: 4, , table: profile_tcam_bypass.tsid_vfr_egr_catch_all */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = CFA_RSUBTYPE_TCAM_PROF_TCAM, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 3187, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .pri_opcode = BNXT_ULP_PRI_OPC_APP_PRI_OR_CONST, + .pri_operand = ULP_THOR2_SYM_PROF_TCAM_PRI_CATCHALL, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .key_start_idx = 588, + .blob_key_bit_size = 256, + .key_bit_size = 256, + .key_num_fields = 66, + .result_start_idx = 1465, + .result_bit_size = 65, + .result_num_fields = 7, + .ident_start_idx = 37, + .ident_nums = 1 + }, + { /* class_tid: 4, , table: table_scope_cache.tsid_vfr_egr_wr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TABLE_SCOPE_CACHE, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 3187, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .key_start_idx = 654, + .blob_key_bit_size = 6, + .key_bit_size = 6, + .key_num_fields = 2, + .result_start_idx = 1472, + .result_bit_size = 88, + .result_num_fields = 5 + }, + { /* class_tid: 4, , table: l2_cntxt_tcam_cache.endpoint_def_egr_rd */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 3187, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .key_start_idx = 656, + .blob_key_bit_size = 11, + .key_bit_size = 11, + .key_num_fields = 1, + .ident_start_idx = 38, + .ident_nums = 1 + }, + { /* class_tid: 4, , table: control.endpoint_def_egr_rd_check */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 4, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 3187, + .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID + }, + { /* class_tid: 4, , table: l2_cntxt_tcam.vf2vf_egr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = CFA_RSUBTYPE_TCAM_L2CTX, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 3188, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .pri_opcode = BNXT_ULP_PRI_OPC_APP_PRI_OR_CONST, + .pri_operand = ULP_THOR2_SYM_L2_CTXT_PRI_CATCHALL, + .key_start_idx = 657, + .blob_key_bit_size = 256, + .key_bit_size = 256, + .key_num_fields = 24, + .result_start_idx = 1477, + .result_bit_size = 127, + .result_num_fields = 17, + .ident_start_idx = 39, + .ident_nums = 1 + }, + { /* class_tid: 4, , table: l2_cntxt_tcam_cache.endpoint_def_egr_wr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 3188, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .key_start_idx = 681, + .blob_key_bit_size = 11, + .key_bit_size = 11, + .key_num_fields = 1, + .ident_start_idx = 40, + .ident_nums = 3 + }, + { /* class_tid: 4, , table: port_table.egr_wr_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 3188, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .key_start_idx = 682, + .blob_key_bit_size = 10, + .key_bit_size = 10, + .key_num_fields = 1, + .result_start_idx = 1494, + .result_bit_size = 169, + .result_num_fields = 6 + }, + { /* class_tid: 4, , table: mod_record.vfr2vf */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CMM_TABLE, + .resource_type = CFA_RSUBTYPE_CMM_ACT, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CMM_TABLE_ACT, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 3188, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_CMM_MOD_HNDL, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .func_info = { + .func_opc = BNXT_ULP_FUNC_OPC_BIT_OR, + .func_src1 = BNXT_ULP_FUNC_SRC_COMP_FIELD, + .func_opr1 = BNXT_ULP_CF_IDX_VF_FUNC_VNIC, + .func_src2 = BNXT_ULP_FUNC_SRC_CONST, + .func_opr2 = ULP_THOR2_SYM_VF_2_VF_META_VAL, + .func_dst_opr = BNXT_ULP_RF_IDX_RF_0 }, + .result_start_idx = 1500, + .result_bit_size = 0, + .result_num_fields = 0, + .encap_num_fields = 20 + }, + { /* class_tid: 4, , table: control.mod_handle_to_offset_vfr2vf */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 3188, + .cond_nums = 0 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .func_info = { + .func_opc = BNXT_ULP_FUNC_OPC_HANDLE_TO_OFFSET, + .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE, + .func_opr1 = BNXT_ULP_RF_IDX_CMM_MOD_HNDL, + .func_src2 = BNXT_ULP_FUNC_SRC_CONST, + .func_opr2 = 8, + .func_dst_opr = BNXT_ULP_RF_IDX_MODIFY_PTR } + }, + { /* class_tid: 4, , table: cmm_full_act_record.vfr2vf_act */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CMM_TABLE, + .resource_type = CFA_RSUBTYPE_CMM_ACT, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CMM_TABLE_ACT, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 3188, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_CMM_ACT_HNDL, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .result_start_idx = 1520, + .result_bit_size = 192, + .result_num_fields = 18 + }, + { /* class_tid: 4, , table: control.act_handle_to_offset_vfr2vf_act */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 3188, + .cond_nums = 0 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .func_info = { + .func_opc = BNXT_ULP_FUNC_OPC_HANDLE_TO_OFFSET, + .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE, + .func_opr1 = BNXT_ULP_RF_IDX_CMM_ACT_HNDL, + .func_src2 = BNXT_ULP_FUNC_SRC_CONST, + .func_opr2 = 32, + .func_dst_opr = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR } + }, + { /* class_tid: 4, , table: control.bd_act_set */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 3188, + .cond_nums = 0 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .func_info = { + .func_opc = BNXT_ULP_FUNC_OPC_BD_ACT_SET, + .func_src1 = BNXT_ULP_FUNC_SRC_COMP_FIELD, + .func_opr1 = BNXT_ULP_CF_IDX_DEV_PORT_ID, + .func_src2 = BNXT_ULP_FUNC_SRC_REGFILE, + .func_opr2 = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .func_dst_opr = BNXT_ULP_RF_IDX_CC } + }, + { /* class_tid: 4, , table: control.vfr_mark_set */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 0, + .cond_false_goto = 0, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 3188, + .cond_nums = 0 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .func_info = { + .func_opc = BNXT_ULP_FUNC_OPC_VFR_MARK_SET, + .func_src1 = BNXT_ULP_FUNC_SRC_COMP_FIELD, + .func_opr1 = BNXT_ULP_CF_IDX_VF_FUNC_SVIF, + .func_src2 = BNXT_ULP_FUNC_SRC_COMP_FIELD, + .func_opr2 = BNXT_ULP_CF_IDX_DEV_PORT_ID, + .func_dst_opr = BNXT_ULP_RF_IDX_CC }, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG + } +}; + +struct bnxt_ulp_mapper_cond_list_info ulp_thor2_class_cond_oper_list[] = { +}; + +struct bnxt_ulp_mapper_cond_info ulp_thor2_class_cond_list[] = { + /* cond_execute: class_tid: 1, control.check_f1_f2_flow:0*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_F1 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_F2 + }, + /* cond_execute: class_tid: 1, control.tunnel_cache_check:2*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + }, + /* cond_execute: class_tid: 1, control.check_f2_flow:3*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_F2 + }, + /* field_cond: class_tid: 1, mac_addr_cache.l2_table_rd */ + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC + }, + /* field_cond: class_tid: 1, mac_addr_cache.l2_table_rd */ + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC + }, + /* field_cond: class_tid: 1, mac_addr_cache.l2_table_rd */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY + }, + /* field_cond: class_tid: 1, mac_addr_cache.l2_table_rd */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY + }, + /* field_cond: class_tid: 1, mac_addr_cache.l2_table_rd */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_RECYCLE_CNT + }, + /* field_cond: class_tid: 1, mac_addr_cache.l2_table_rd */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_METADATA + }, + /* cond_execute: class_tid: 1, control.mac_addr_cache_check:12*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + }, + /* field_cond: class_tid: 1, l2_cntxt_tcam.l2_table_create */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY + }, + /* field_cond: class_tid: 1, l2_cntxt_tcam.l2_table_create */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY + }, + /* field_cond: class_tid: 1, l2_cntxt_tcam.l2_table_create */ + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC + }, + /* field_cond: class_tid: 1, l2_cntxt_tcam.l2_table_create */ + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC + }, + /* field_cond: class_tid: 1, l2_cntxt_tcam.l2_table_create */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_METADATA + }, + /* field_cond: class_tid: 1, l2_cntxt_tcam.l2_table_create */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_METADATA + }, + /* field_cond: class_tid: 1, l2_cntxt_tcam.l2_table_create */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_RECYCLE_CNT + }, + /* field_cond: class_tid: 1, l2_cntxt_tcam.l2_table_create */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_RECYCLE_CNT + }, + /* field_cond: class_tid: 1, mac_addr_cache.l2_table_wr */ + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC + }, + /* field_cond: class_tid: 1, mac_addr_cache.l2_table_wr */ + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC + }, + /* field_cond: class_tid: 1, mac_addr_cache.l2_table_wr */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY + }, + /* field_cond: class_tid: 1, mac_addr_cache.l2_table_wr */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY + }, + /* field_cond: class_tid: 1, mac_addr_cache.l2_table_wr */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_RECYCLE_CNT + }, + /* field_cond: class_tid: 1, mac_addr_cache.l2_table_wr */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_METADATA + }, + /* cond_execute: class_tid: 1, control.proto_header_cache_miss:31*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + }, + /* cond_execute: class_tid: 1, control.overlap_miss:32*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_CNTXT_ID + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_METADATA + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_METADATA + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_RECYCLE_CNT + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_SMAC + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OI_VLAN_VID + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_TYPE + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_TTL + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_TTL + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_QOS + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_QOS + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN_GPE + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_T_VXLAN_GPE_VNI + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_DMAC + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_SMAC + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_SMAC + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_IO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_II_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_IO_VLAN_VID + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_IO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_II_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_II_VLAN_VID + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_IO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_II_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_IO_VLAN_VID + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OI_VLAN_VID + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_TYPE + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_TYPE + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_TTL + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_TTL + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_TTL + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_TTL + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_PROTO_ID + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_PROTO_ID + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_QOS + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_QOS + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_QOS + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_QOS + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_UDP_SRC_PORT + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_TCP_SRC_PORT + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_UDP_DST_PORT + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_TCP_DST_PORT + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_CNTXT_ID + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_CNTXT_ID + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_METADATA + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_METADATA + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_RECYCLE_CNT + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_RECYCLE_CNT + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_SMAC + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_SMAC + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OI_VLAN_VID + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OI_VLAN_VID + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_TYPE + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_TYPE + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_TTL + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_TTL + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_TTL + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_TTL + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_QOS + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_QOS + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_QOS + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_QOS + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN_GPE + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_T_VXLAN_GPE_VNI + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN_GPE + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_T_VXLAN_GPE_VNI + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_DMAC + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_DMAC + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_SMAC + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_SMAC + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_SMAC + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_SMAC + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_IO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_II_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_IO_VLAN_VID + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_IO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_II_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_IO_VLAN_VID + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_IO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_II_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_II_VLAN_VID + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_IO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_II_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_IO_VLAN_VID + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OI_VLAN_VID + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_IO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_II_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_II_VLAN_VID + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_IO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_II_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_IO_VLAN_VID + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OI_VLAN_VID + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_TYPE + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_TYPE + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_TYPE + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_TYPE + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_TTL + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_TTL + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_TTL + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_TTL + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_TTL + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_TTL + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_TTL + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_TTL + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_PROTO_ID + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_PROTO_ID + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_PROTO_ID + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_PROTO_ID + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_QOS + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_QOS + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_QOS + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_QOS + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_QOS + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_QOS + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_QOS + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_QOS + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_UDP_SRC_PORT + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_TCP_SRC_PORT + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_UDP_SRC_PORT + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_TCP_SRC_PORT + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_UDP_DST_PORT + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_TCP_DST_PORT + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_UDP_DST_PORT + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_TCP_DST_PORT + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT + }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_TCP + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_UDP + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_TCP + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_UDP + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_TCP + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_UDP + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_TCP + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_UDP + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_TCP + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_UDP + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_TCP + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_UDP + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_TCP + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_UDP + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_TCP + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_UDP + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, + .cond_operand = BNXT_ULP_CF_IDX_I_TWO_VTAGS + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, + .cond_operand = BNXT_ULP_CF_IDX_O_TWO_VTAGS + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, + .cond_operand = BNXT_ULP_CF_IDX_I_TWO_VTAGS + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, + .cond_operand = BNXT_ULP_CF_IDX_O_TWO_VTAGS + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, + .cond_operand = BNXT_ULP_CF_IDX_I_HAS_VTAG + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, + .cond_operand = BNXT_ULP_CF_IDX_O_HAS_VTAG + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, + .cond_operand = BNXT_ULP_CF_IDX_I_HAS_VTAG + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, + .cond_operand = BNXT_ULP_CF_IDX_O_HAS_VTAG + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_DIX_TRAFFIC + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_DIX_TRAFFIC + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN_GPE + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_GENEVE + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_GRE + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_UPAR1 + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_UPAR2 + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN_GPE + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_GENEVE + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_GRE + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_UPAR1 + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_UPAR2 + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, + .cond_operand = BNXT_ULP_CF_IDX_O_TWO_VTAGS + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, + .cond_operand = BNXT_ULP_CF_IDX_O_TWO_VTAGS + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, + .cond_operand = BNXT_ULP_CF_IDX_O_HAS_VTAG + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, + .cond_operand = BNXT_ULP_CF_IDX_O_HAS_VTAG + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_DIX_TRAFFIC + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_DIX_TRAFFIC + }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + /* cond_execute: class_tid: 1, em_flow_conflict_cache.rd:940*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET, + .cond_operand = BNXT_ULP_CF_IDX_WC_MATCH + }, + /* cond_execute: class_tid: 1, control.em_flow_conflict_cache_miss:941*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_CNTXT_ID + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_METADATA + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_METADATA + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_RECYCLE_CNT + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_EXCLUDE_FIELD_BIT_NOT_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_SMAC + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OI_VLAN_VID + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_TYPE + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_TTL + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_TTL + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_QOS + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_QOS + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN_GPE + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_T_VXLAN_GPE_VNI + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_DMAC + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_EXCLUDE_FIELD_BIT_NOT_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_DMAC + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_EXCLUDE_FIELD_BIT_NOT_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_SMAC + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_SMAC + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_IO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_II_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_IO_VLAN_VID + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_IO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_II_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_II_VLAN_VID + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_IO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_II_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_IO_VLAN_VID + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OI_VLAN_VID + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_TYPE + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_TYPE + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_TTL + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_TTL + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_TTL + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_TTL + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_PROTO_ID + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_PROTO_ID + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_QOS + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_QOS + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_QOS + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_QOS + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_UDP_SRC_PORT + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_TCP_SRC_PORT + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_UDP_DST_PORT + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_TCP_DST_PORT + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT + }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_CNTXT_ID + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_CNTXT_ID + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_METADATA + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_METADATA + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_RECYCLE_CNT + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_RECYCLE_CNT + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_EXCLUDE_FIELD_BIT_NOT_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_EXCLUDE_FIELD_BIT_NOT_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_SMAC + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_SMAC + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OI_VLAN_VID + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OI_VLAN_VID + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_TYPE + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_TYPE + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_TTL + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_TTL + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_TTL + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_TTL + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_QOS + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_QOS + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_QOS + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_QOS + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN_GPE + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_T_VXLAN_GPE_VNI + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN_GPE + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_T_VXLAN_GPE_VNI + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_DMAC + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_EXCLUDE_FIELD_BIT_NOT_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_DMAC + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_EXCLUDE_FIELD_BIT_NOT_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_DMAC + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_EXCLUDE_FIELD_BIT_NOT_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_DMAC + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_EXCLUDE_FIELD_BIT_NOT_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_SMAC + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_SMAC + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_SMAC + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_SMAC + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_IO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_II_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_IO_VLAN_VID + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_IO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_II_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_IO_VLAN_VID + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_IO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_II_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_II_VLAN_VID + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_IO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_II_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_IO_VLAN_VID + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OI_VLAN_VID + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_IO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_II_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_II_VLAN_VID + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_IO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_II_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_IO_VLAN_VID + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OI_VLAN_VID + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_TYPE + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_TYPE + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_TYPE + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_TYPE + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_TTL + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_TTL + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_TTL + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_TTL + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_TTL + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_TTL + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_TTL + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_TTL + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_PROTO_ID + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_PROTO_ID + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_PROTO_ID + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_PROTO_ID + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_QOS + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_QOS + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_QOS + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_QOS + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_QOS + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_QOS + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_QOS + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_QOS + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_UDP_SRC_PORT + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_TCP_SRC_PORT + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_UDP_SRC_PORT + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_TCP_SRC_PORT + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_UDP_DST_PORT + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_TCP_DST_PORT + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_UDP_DST_PORT + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_TCP_DST_PORT + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT + }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT + }, + /* cond_execute: class_tid: 1, control.field_sig_validation:1603*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET, + .cond_operand = BNXT_ULP_RF_IDX_CC + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_FLOW_SIG_ID + }, + /* cond_execute: class_tid: 1, em_normal.ingress_generic_template:1605*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET, + .cond_operand = BNXT_ULP_CF_IDX_WC_MATCH + }, + /* cond_execute: class_tid: 2, control.proto_header_cache_miss:1606*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + }, + /* cond_execute: class_tid: 2, control.overlap_miss:1607*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_CNTXT_ID + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_METADATA + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_METADATA + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_RECYCLE_CNT + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_SMAC + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OI_VLAN_VID + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_TYPE + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_TTL + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_TTL + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_QOS + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_QOS + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN_GPE + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_T_VXLAN_GPE_VNI + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_DMAC + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_SMAC + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_SMAC + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_IO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_II_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_IO_VLAN_VID + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_IO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_II_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_II_VLAN_VID + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_IO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_II_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_IO_VLAN_VID + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OI_VLAN_VID + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_TYPE + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_TYPE + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_TTL + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_TTL + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_TTL + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_TTL + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_PROTO_ID + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_PROTO_ID + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_QOS + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_QOS + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_QOS + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_QOS + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_UDP_SRC_PORT + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_TCP_SRC_PORT + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_UDP_DST_PORT + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_TCP_DST_PORT + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT + }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_CNTXT_ID + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_CNTXT_ID + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_METADATA + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_METADATA + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_RECYCLE_CNT + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_RECYCLE_CNT + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_SMAC + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_SMAC + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OI_VLAN_VID + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OI_VLAN_VID + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_TYPE + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_TYPE + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_TTL + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_TTL + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_TTL + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_TTL + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_QOS + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_QOS + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_QOS + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_QOS + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN_GPE + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_T_VXLAN_GPE_VNI + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN_GPE + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_T_VXLAN_GPE_VNI + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_DMAC + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_DMAC + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_SMAC + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_SMAC + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_SMAC + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_SMAC + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_IO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_II_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_IO_VLAN_VID + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_IO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_II_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_IO_VLAN_VID + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_IO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_II_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_II_VLAN_VID + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_IO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_II_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_IO_VLAN_VID + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OI_VLAN_VID + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_IO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_II_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_II_VLAN_VID + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_IO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_II_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_IO_VLAN_VID + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OI_VLAN_VID + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_TYPE + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_TYPE + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_TYPE + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_TYPE + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_TTL + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_TTL + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_TTL + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_TTL + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_TTL + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_TTL + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_TTL + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_TTL + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_PROTO_ID + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_PROTO_ID + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_PROTO_ID + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_PROTO_ID + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_QOS + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_QOS + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_QOS + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_QOS + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_QOS + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_QOS + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_QOS + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_QOS + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_UDP_SRC_PORT + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_TCP_SRC_PORT + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_UDP_SRC_PORT + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_TCP_SRC_PORT + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_UDP_DST_PORT + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_TCP_DST_PORT + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_UDP_DST_PORT + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_TCP_DST_PORT + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT + }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_TCP + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_UDP + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_TCP + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_UDP + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_TCP + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_UDP + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_TCP + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_UDP + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_TCP + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_UDP + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_TCP + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_UDP + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_TCP + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_UDP + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_TCP + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_UDP + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, + .cond_operand = BNXT_ULP_CF_IDX_I_TWO_VTAGS + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, + .cond_operand = BNXT_ULP_CF_IDX_O_TWO_VTAGS + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, + .cond_operand = BNXT_ULP_CF_IDX_I_TWO_VTAGS + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, + .cond_operand = BNXT_ULP_CF_IDX_O_TWO_VTAGS + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, + .cond_operand = BNXT_ULP_CF_IDX_I_HAS_VTAG + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, + .cond_operand = BNXT_ULP_CF_IDX_O_HAS_VTAG + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, + .cond_operand = BNXT_ULP_CF_IDX_I_HAS_VTAG + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, + .cond_operand = BNXT_ULP_CF_IDX_O_HAS_VTAG + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_DIX_TRAFFIC + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_DIX_TRAFFIC + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN_GPE + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_GENEVE + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_GRE + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_UPAR1 + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_UPAR2 + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN_GPE + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_GENEVE + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_GRE + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_UPAR1 + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_UPAR2 + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, + .cond_operand = BNXT_ULP_CF_IDX_O_TWO_VTAGS + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, + .cond_operand = BNXT_ULP_CF_IDX_O_TWO_VTAGS + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, + .cond_operand = BNXT_ULP_CF_IDX_O_HAS_VTAG + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, + .cond_operand = BNXT_ULP_CF_IDX_O_HAS_VTAG + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_DIX_TRAFFIC + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_DIX_TRAFFIC + }, + /* field_cond: class_tid: 2, profile_tcam.gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + /* cond_execute: class_tid: 2, em_flow_conflict_cache.rd:2515*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET, + .cond_operand = BNXT_ULP_CF_IDX_WC_MATCH + }, + /* cond_execute: class_tid: 2, control.em_flow_conflict_cache_miss:2516*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_CNTXT_ID + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_METADATA + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_METADATA + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_RECYCLE_CNT + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_EXCLUDE_FIELD_BIT_NOT_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_SMAC + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OI_VLAN_VID + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_TYPE + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_TTL + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_TTL + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_QOS + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_QOS + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN_GPE + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_T_VXLAN_GPE_VNI + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_DMAC + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_EXCLUDE_FIELD_BIT_NOT_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_DMAC + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_EXCLUDE_FIELD_BIT_NOT_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_SMAC + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_SMAC + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_IO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_II_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_IO_VLAN_VID + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_IO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_II_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_II_VLAN_VID + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_IO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_II_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_IO_VLAN_VID + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OI_VLAN_VID + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_TYPE + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_TYPE + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_TTL + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_TTL + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_TTL + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_TTL + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_PROTO_ID + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_PROTO_ID + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_QOS + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_QOS + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_QOS + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_QOS + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_UDP_SRC_PORT + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_TCP_SRC_PORT + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_UDP_DST_PORT + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_TCP_DST_PORT + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT + }, + /* field_cond: class_tid: 2, fkb_select.em_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_CNTXT_ID + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_CNTXT_ID + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_METADATA + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_METADATA + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_RECYCLE_CNT + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_RECYCLE_CNT + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_EXCLUDE_FIELD_BIT_NOT_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_EXCLUDE_FIELD_BIT_NOT_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_SMAC + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_SMAC + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OI_VLAN_VID + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OI_VLAN_VID + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_TYPE + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_TYPE + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_TTL + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_TTL + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_TTL + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_TTL + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_QOS + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_QOS + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_QOS + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_QOS + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN_GPE + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_T_VXLAN_GPE_VNI + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN_GPE + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_T_VXLAN_GPE_VNI + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_DMAC + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_EXCLUDE_FIELD_BIT_NOT_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_DMAC + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_EXCLUDE_FIELD_BIT_NOT_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_DMAC + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_EXCLUDE_FIELD_BIT_NOT_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_DMAC + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_EXCLUDE_FIELD_BIT_NOT_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_SMAC + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_SMAC + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_SMAC + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_SMAC + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_IO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_II_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_IO_VLAN_VID + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_IO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_II_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_IO_VLAN_VID + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_IO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_II_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_II_VLAN_VID + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_IO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_II_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_IO_VLAN_VID + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OI_VLAN_VID + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_IO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_II_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_II_VLAN_VID + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_IO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_II_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_IO_VLAN_VID + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OI_VLAN_VID + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_TYPE + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_TYPE + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_TYPE + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_TYPE + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_TTL + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_TTL + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_TTL + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_TTL + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_TTL + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_TTL + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_TTL + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_TTL + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_PROTO_ID + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_PROTO_ID + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_PROTO_ID + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_PROTO_ID + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_QOS + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_QOS + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_QOS + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_QOS + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_QOS + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_QOS + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_QOS + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_QOS + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_UDP_SRC_PORT + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_TCP_SRC_PORT + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_UDP_SRC_PORT + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_TCP_SRC_PORT + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_UDP_DST_PORT + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_TCP_DST_PORT + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_UDP_DST_PORT + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_TCP_DST_PORT + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT + }, + /* field_cond: class_tid: 2, em_key_recipe.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT + }, + /* cond_execute: class_tid: 2, control.field_sig_validation:3178*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET, + .cond_operand = BNXT_ULP_RF_IDX_CC + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_FLOW_SIG_ID + }, + /* cond_execute: class_tid: 2, em_normal.egress_generic_template:3180*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET, + .cond_operand = BNXT_ULP_CF_IDX_WC_MATCH + }, + /* cond_execute: class_tid: 3, control.ts_ing_rd_check:3181*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + }, + /* cond_execute: class_tid: 3, control.ing_rd_check:3182*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + }, + /* cond_execute: class_tid: 3, control.egr_vfr_check_0:3183*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, + .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE + }, + /* cond_execute: class_tid: 3, control.tsid_vfr_rd_check:3184*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + }, + /* cond_execute: class_tid: 3, control.no_vfr_egr_rd_check:3185*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + }, + /* cond_execute: class_tid: 4, control.tsid_vfr_egr_check:3186*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + }, + /* cond_execute: class_tid: 4, control.endpoint_def_egr_rd_check:3187*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + } +}; + +struct bnxt_ulp_mapper_key_info ulp_thor2_class_key_info_list[] = { + /* class_tid: 1, , table: port_table.get_def_rd */ + { + .field_info_mask = { + .description = "dev.port_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "dev.port_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff} + } + }, + /* class_tid: 1, , table: l2_cntxt_tcam_cache.def_rd */ + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + } + }, + /* class_tid: 1, , table: tunnel_cache.f1_f2_rd */ + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + } + }, + { + .field_info_mask = { + .description = "tunnel_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tunnel_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_TUNNEL_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_TUNNEL_ID & 0xff} + } + }, + /* class_tid: 1, , table: l2_cntxt_tcam.f1_f2_alloc_l2_cntxt */ + { + .field_info_mask = { + .description = "etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ivlan_tpid_sel", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ivlan_tpid_sel", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ovlan_tpid_sel", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ovlan_tpid_sel", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "addr1", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "addr1", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "addr0", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "addr0", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tunnel_id", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tunnel_id", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR2_SYM_TUN_HDR_TYPE_NONE} + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR2_SYM_TUN_HDR_TYPE_NONE} + } + }, + { + .field_info_mask = { + .description = "out_tun_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR2_SYM_TUN_HDR_TYPE_NONE} + }, + .field_info_spec = { + .description = "out_tun_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR2_SYM_TUN_HDR_TYPE_NONE} + } + }, + { + .field_info_mask = { + .description = "llc", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "llc", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "roce", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + .field_info_spec = { + .description = "roce", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2ip_func", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2ip_func", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "metadata", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "metadata", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "parif", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "parif", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "spif", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "spif", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "recycle_cnt", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "recycle_cnt", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "mpass_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "mpass_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "spare", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "spare", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + } + }, + /* class_tid: 1, , table: tunnel_cache.f1_f2_wr */ + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + } + }, + { + .field_info_mask = { + .description = "tunnel_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tunnel_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_TUNNEL_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_TUNNEL_ID & 0xff} + } + }, + /* class_tid: 1, , table: mac_addr_cache.l2_table_rd */ + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + } + }, + { + .field_info_mask = { + .description = "tun_hdr", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tun_hdr", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "one_tag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "one_tag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "mac_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (4 >> 8) & 0xff, + 4 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_PORT_TABLE, + .field_opr3 = { + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff, + (BNXT_ULP_PORT_TABLE_DRV_FUNC_MAC >> 8) & 0xff, + BNXT_ULP_PORT_TABLE_DRV_FUNC_MAC & 0xff} + }, + .field_info_spec = { + .description = "mac_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (6 >> 8) & 0xff, + 6 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_PORT_TABLE, + .field_opr3 = { + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff, + (BNXT_ULP_PORT_TABLE_DRV_FUNC_MAC >> 8) & 0xff, + BNXT_ULP_PORT_TABLE_DRV_FUNC_MAC & 0xff} + } + }, + { + .field_info_mask = { + .description = "etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (8 >> 8) & 0xff, + 8 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_TYPE >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_TYPE & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (9 >> 8) & 0xff, + 9 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_TYPE >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_TYPE & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (10 >> 8) & 0xff, + 10 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "metadata", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "metadata", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (11 >> 8) & 0xff, + 11 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tbl_scope", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tbl_scope", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + /* class_tid: 1, , table: l2_cntxt_tcam.l2_table_create */ + { + .field_info_mask = { + .description = "etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (13 >> 8) & 0xff, + 13 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (14 >> 8) & 0xff, + 14 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_TYPE >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_TYPE & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_CONST + } + }, + { + .field_info_mask = { + .description = "l2_ivlan_tpid_sel", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ivlan_tpid_sel", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ovlan_tpid_sel", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ovlan_tpid_sel", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "addr1", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "addr1", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "addr0", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (15 >> 8) & 0xff, + 15 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ONES + }, + .field_info_spec = { + .description = "addr0", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (17 >> 8) & 0xff, + 17 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_PORT_TABLE, + .field_opr3 = { + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff, + (BNXT_ULP_PORT_TABLE_DRV_FUNC_MAC >> 8) & 0xff, + BNXT_ULP_PORT_TABLE_DRV_FUNC_MAC & 0xff} + } + }, + { + .field_info_mask = { + .description = "tunnel_id", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tunnel_id", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "out_tun_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "out_tun_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "llc", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "llc", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "roce", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + .field_info_spec = { + .description = "roce", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2ip_func", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2ip_func", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "metadata", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (19 >> 8) & 0xff, + 19 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "metadata", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (20 >> 8) & 0xff, + 20 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_CONST + } + }, + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + } + }, + { + .field_info_mask = { + .description = "parif", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "parif", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "spif", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "spif", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "recycle_cnt", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (21 >> 8) & 0xff, + 21 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "recycle_cnt", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (22 >> 8) & 0xff, + 22 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_CONST + } + }, + { + .field_info_mask = { + .description = "mpass_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "mpass_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "spare", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "spare", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + } + }, + /* class_tid: 1, , table: mac_addr_cache.l2_table_wr */ + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + } + }, + { + .field_info_mask = { + .description = "tun_hdr", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tun_hdr", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "one_tag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "one_tag", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "mac_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (23 >> 8) & 0xff, + 23 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_PORT_TABLE, + .field_opr3 = { + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff, + (BNXT_ULP_PORT_TABLE_DRV_FUNC_MAC >> 8) & 0xff, + BNXT_ULP_PORT_TABLE_DRV_FUNC_MAC & 0xff} + }, + .field_info_spec = { + .description = "mac_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (25 >> 8) & 0xff, + 25 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_PORT_TABLE, + .field_opr3 = { + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff, + (BNXT_ULP_PORT_TABLE_DRV_FUNC_MAC >> 8) & 0xff, + BNXT_ULP_PORT_TABLE_DRV_FUNC_MAC & 0xff} + } + }, + { + .field_info_mask = { + .description = "etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (27 >> 8) & 0xff, + 27 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_TYPE >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_TYPE & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (28 >> 8) & 0xff, + 28 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_TYPE >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_TYPE & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (29 >> 8) & 0xff, + 29 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "metadata", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "metadata", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (30 >> 8) & 0xff, + 30 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tbl_scope", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tbl_scope", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + /* class_tid: 1, , table: proto_header_cache.rd */ + { + .field_info_mask = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "prof_func_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "prof_func_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_PROF_FUNC_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_PROF_FUNC_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "hdr_bitmap", + .field_bit_size = 64, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "hdr_bitmap", + .field_bit_size = 64, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_HDR_BITMAP >> 8) & 0xff, + BNXT_ULP_CF_IDX_HDR_BITMAP & 0xff} + } + }, + /* class_tid: 1, , table: hdr_overlap_cache.overlap_check */ + { + .field_info_mask = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "prof_func_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "prof_func_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_PROF_FUNC_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_PROF_FUNC_ID_0 & 0xff} + } + }, + /* class_tid: 1, , table: hdr_overlap_cache.overlap_wr */ + { + .field_info_mask = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "prof_func_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "prof_func_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_PROF_FUNC_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_PROF_FUNC_ID_0 & 0xff} + } + }, + /* class_tid: 1, , table: wm_key_recipe.0 */ + { + .field_info_mask = { + .description = "wc_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "wc_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_WC_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_WC_PROFILE_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2_cntxt_id", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (287 >> 8) & 0xff, + 287 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + .field_info_spec = { + .description = "l2_cntxt_id", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (288 >> 8) & 0xff, + 288 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_RF, + .field_opr2 = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + } + }, + { + .field_info_mask = { + .description = "meta", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (289 >> 8) & 0xff, + 289 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + .field_info_spec = { + .description = "meta", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (290 >> 8) & 0xff, + 290 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CF, + .field_opr2 = { + (BNXT_ULP_CF_IDX_VF_META_FID >> 8) & 0xff, + BNXT_ULP_CF_IDX_VF_META_FID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + } + }, + { + .field_info_mask = { + .description = "rcyc_cnt", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (291 >> 8) & 0xff, + 291 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + .field_info_spec = { + .description = "rcyc_cnt", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (292 >> 8) & 0xff, + 292 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_RF, + .field_opr2 = { + (BNXT_ULP_RF_IDX_RECYCLE_CNT >> 8) & 0xff, + BNXT_ULP_RF_IDX_RECYCLE_CNT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (293 >> 8) & 0xff, + 293 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + .field_info_spec = { + .description = "tl2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (296 >> 8) & 0xff, + 296 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (299 >> 8) & 0xff, + 299 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + .field_info_spec = { + .description = "tl2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (303 >> 8) & 0xff, + 303 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (307 >> 8) & 0xff, + 307 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_OI_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OI_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (43 >> 8) & 0xff, + 43 & 0xff} + }, + .field_info_spec = { + .description = "tl2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (315 >> 8) & 0xff, + 315 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_OI_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OI_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (44 >> 8) & 0xff, + 44 & 0xff} + } + }, + { + .field_info_mask = { + .description = "tl2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (323 >> 8) & 0xff, + 323 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_TYPE >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_TYPE & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + .field_info_spec = { + .description = "tl2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (327 >> 8) & 0xff, + 327 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_TYPE >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_TYPE & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (331 >> 8) & 0xff, + 331 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + .field_info_spec = { + .description = "tl3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (334 >> 8) & 0xff, + 334 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (337 >> 8) & 0xff, + 337 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + .field_info_spec = { + .description = "tl3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (340 >> 8) & 0xff, + 340 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (343 >> 8) & 0xff, + 343 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + .field_info_spec = { + .description = "tl3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (346 >> 8) & 0xff, + 346 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (349 >> 8) & 0xff, + 349 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + .field_info_spec = { + .description = "tl3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (352 >> 8) & 0xff, + 352 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (355 >> 8) & 0xff, + 355 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_TTL >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_TTL & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (45 >> 8) & 0xff, + 45 & 0xff} + }, + .field_info_spec = { + .description = "tl3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (361 >> 8) & 0xff, + 361 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_TTL >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_TTL & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (46 >> 8) & 0xff, + 46 & 0xff} + } + }, + { + .field_info_mask = { + .description = "tl3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (367 >> 8) & 0xff, + 367 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (47 >> 8) & 0xff, + 47 & 0xff} + }, + .field_info_spec = { + .description = "tl3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (373 >> 8) & 0xff, + 373 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (48 >> 8) & 0xff, + 48 & 0xff} + } + }, + { + .field_info_mask = { + .description = "tl3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (379 >> 8) & 0xff, + 379 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_QOS >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_QOS & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (49 >> 8) & 0xff, + 49 & 0xff} + }, + .field_info_spec = { + .description = "tl3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (385 >> 8) & 0xff, + 385 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_QOS >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_QOS & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (50 >> 8) & 0xff, + 50 & 0xff} + } + }, + { + .field_info_mask = { + .description = "tl4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (391 >> 8) & 0xff, + 391 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (51 >> 8) & 0xff, + 51 & 0xff} + }, + .field_info_spec = { + .description = "tl4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (397 >> 8) & 0xff, + 397 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (52 >> 8) & 0xff, + 52 & 0xff} + } + }, + { + .field_info_mask = { + .description = "tl4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (403 >> 8) & 0xff, + 403 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (53 >> 8) & 0xff, + 53 & 0xff} + }, + .field_info_spec = { + .description = "tl4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (409 >> 8) & 0xff, + 409 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (54 >> 8) & 0xff, + 54 & 0xff} + } + }, + { + .field_info_mask = { + .description = "tids", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (415 >> 8) & 0xff, + 415 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (55 >> 8) & 0xff, + 55 & 0xff} + }, + .field_info_spec = { + .description = "tids", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (419 >> 8) & 0xff, + 419 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (56 >> 8) & 0xff, + 56 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (423 >> 8) & 0xff, + 423 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (57 >> 8) & 0xff, + 57 & 0xff} + }, + .field_info_spec = { + .description = "l2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (429 >> 8) & 0xff, + 429 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (58 >> 8) & 0xff, + 58 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (435 >> 8) & 0xff, + 435 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (59 >> 8) & 0xff, + 59 & 0xff} + }, + .field_info_spec = { + .description = "l2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (441 >> 8) & 0xff, + 441 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (60 >> 8) & 0xff, + 60 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (447 >> 8) & 0xff, + 447 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_IO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_IO_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (61 >> 8) & 0xff, + 61 & 0xff} + }, + .field_info_spec = { + .description = "l2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (455 >> 8) & 0xff, + 455 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_IO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_IO_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (62 >> 8) & 0xff, + 62 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (463 >> 8) & 0xff, + 463 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_II_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_II_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (63 >> 8) & 0xff, + 63 & 0xff} + }, + .field_info_spec = { + .description = "l2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (479 >> 8) & 0xff, + 479 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_II_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_II_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (66 >> 8) & 0xff, + 66 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (495 >> 8) & 0xff, + 495 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_ETH_TYPE >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_ETH_TYPE & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (69 >> 8) & 0xff, + 69 & 0xff} + }, + .field_info_spec = { + .description = "l2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (503 >> 8) & 0xff, + 503 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_ETH_TYPE >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_ETH_TYPE & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (70 >> 8) & 0xff, + 70 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (511 >> 8) & 0xff, + 511 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (71 >> 8) & 0xff, + 71 & 0xff} + }, + .field_info_spec = { + .description = "l3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (517 >> 8) & 0xff, + 517 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (72 >> 8) & 0xff, + 72 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (523 >> 8) & 0xff, + 523 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (73 >> 8) & 0xff, + 73 & 0xff} + }, + .field_info_spec = { + .description = "l3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (529 >> 8) & 0xff, + 529 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (74 >> 8) & 0xff, + 74 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (535 >> 8) & 0xff, + 535 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (75 >> 8) & 0xff, + 75 & 0xff} + }, + .field_info_spec = { + .description = "l3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (541 >> 8) & 0xff, + 541 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (76 >> 8) & 0xff, + 76 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (547 >> 8) & 0xff, + 547 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (77 >> 8) & 0xff, + 77 & 0xff} + }, + .field_info_spec = { + .description = "l3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (553 >> 8) & 0xff, + 553 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (78 >> 8) & 0xff, + 78 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (559 >> 8) & 0xff, + 559 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_IPV6_TTL >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV6_TTL & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (79 >> 8) & 0xff, + 79 & 0xff} + }, + .field_info_spec = { + .description = "l3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (571 >> 8) & 0xff, + 571 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_IPV6_TTL >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV6_TTL & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (82 >> 8) & 0xff, + 82 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (583 >> 8) & 0xff, + 583 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_IPV6_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV6_PROTO_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (85 >> 8) & 0xff, + 85 & 0xff} + }, + .field_info_spec = { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (595 >> 8) & 0xff, + 595 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_IPV6_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV6_PROTO_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (88 >> 8) & 0xff, + 88 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (607 >> 8) & 0xff, + 607 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_IPV6_QOS >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV6_QOS & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (91 >> 8) & 0xff, + 91 & 0xff} + }, + .field_info_spec = { + .description = "l3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (619 >> 8) & 0xff, + 619 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_IPV6_QOS >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV6_QOS & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (94 >> 8) & 0xff, + 94 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (631 >> 8) & 0xff, + 631 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_UDP_SRC_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (97 >> 8) & 0xff, + 97 & 0xff} + }, + .field_info_spec = { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (643 >> 8) & 0xff, + 643 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_UDP_SRC_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (100 >> 8) & 0xff, + 100 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (655 >> 8) & 0xff, + 655 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_UDP_DST_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (103 >> 8) & 0xff, + 103 & 0xff} + }, + .field_info_spec = { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (667 >> 8) & 0xff, + 667 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_UDP_DST_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (106 >> 8) & 0xff, + 106 & 0xff} + } + }, + /* class_tid: 1, , table: profile_tcam.gen_template */ + { + .field_info_mask = { + .description = "l4_hdr_dcn_present", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l4_hdr_dcn_present", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4_hdr_flags", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l4_hdr_flags", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4_hdr_subtype", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l4_hdr_subtype", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (679 >> 8) & 0xff, + 679 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (109 >> 8) & 0xff, + 109 & 0xff} + }, + .field_info_spec = { + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (687 >> 8) & 0xff, + 687 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_L4_HDR_IS_UDP_TCP_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (112 >> 8) & 0xff, + 112 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (695 >> 8) & 0xff, + 695 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (115 >> 8) & 0xff, + 115 & 0xff} + }, + .field_info_spec = { + .description = "l4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (703 >> 8) & 0xff, + 703 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (118 >> 8) & 0xff, + 118 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (711 >> 8) & 0xff, + 711 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (121 >> 8) & 0xff, + 121 & 0xff} + }, + .field_info_spec = { + .description = "l4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (719 >> 8) & 0xff, + 719 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (124 >> 8) & 0xff, + 124 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (727 >> 8) & 0xff, + 727 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (127 >> 8) & 0xff, + 127 & 0xff} + }, + .field_info_spec = { + .description = "l4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (735 >> 8) & 0xff, + 735 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_L4_HDR_VALID_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (130 >> 8) & 0xff, + 130 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l3_protocol", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3_protocol", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (743 >> 8) & 0xff, + 743 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_L3_HDR_ISIP_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (133 >> 8) & 0xff, + 133 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (751 >> 8) & 0xff, + 751 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (136 >> 8) & 0xff, + 136 & 0xff} + }, + .field_info_spec = { + .description = "l3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (759 >> 8) & 0xff, + 759 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_L3_HDR_TYPE_IPV6}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (139 >> 8) & 0xff, + 139 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (767 >> 8) & 0xff, + 767 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (142 >> 8) & 0xff, + 142 & 0xff} + }, + .field_info_spec = { + .description = "l3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (775 >> 8) & 0xff, + 775 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (145 >> 8) & 0xff, + 145 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (783 >> 8) & 0xff, + 783 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (148 >> 8) & 0xff, + 148 & 0xff} + }, + .field_info_spec = { + .description = "l3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (791 >> 8) & 0xff, + 791 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_L3_HDR_VALID_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (151 >> 8) & 0xff, + 151 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (799 >> 8) & 0xff, + 799 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (154 >> 8) & 0xff, + 154 & 0xff} + }, + .field_info_spec = { + .description = "l2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (805 >> 8) & 0xff, + 805 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_L2_TWO_VTAGS_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (155 >> 8) & 0xff, + 155 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (811 >> 8) & 0xff, + 811 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (156 >> 8) & 0xff, + 156 & 0xff} + }, + .field_info_spec = { + .description = "l2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (817 >> 8) & 0xff, + 817 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_L2_VTAG_PRESENT_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (157 >> 8) & 0xff, + 157 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (823 >> 8) & 0xff, + 823 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (824 >> 8) & 0xff, + 824 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (825 >> 8) & 0xff, + 825 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (158 >> 8) & 0xff, + 158 & 0xff} + }, + .field_info_spec = { + .description = "l2_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (829 >> 8) & 0xff, + 829 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (159 >> 8) & 0xff, + 159 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (833 >> 8) & 0xff, + 833 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_L2_HDR_VALID_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (160 >> 8) & 0xff, + 160 & 0xff} + } + }, + { + .field_info_mask = { + .description = "tun_hdr_flags", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_flags", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (837 >> 8) & 0xff, + 837 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (161 >> 8) & 0xff, + 161 & 0xff} + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (849 >> 8) & 0xff, + 849 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (166 >> 8) & 0xff, + 166 & 0xff} + } + }, + { + .field_info_mask = { + .description = "tun_hdr_err", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (861 >> 8) & 0xff, + 861 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_err", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (862 >> 8) & 0xff, + 862 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tun_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (863 >> 8) & 0xff, + 863 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_TUN_HDR_VALID_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (864 >> 8) & 0xff, + 864 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (171 >> 8) & 0xff, + 171 & 0xff} + }, + .field_info_spec = { + .description = "tl4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (868 >> 8) & 0xff, + 868 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_TL4_HDR_IS_UDP_TCP_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (172 >> 8) & 0xff, + 172 & 0xff} + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (872 >> 8) & 0xff, + 872 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (173 >> 8) & 0xff, + 173 & 0xff} + }, + .field_info_spec = { + .description = "tl4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (876 >> 8) & 0xff, + 876 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (174 >> 8) & 0xff, + 174 & 0xff} + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (880 >> 8) & 0xff, + 880 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (175 >> 8) & 0xff, + 175 & 0xff} + }, + .field_info_spec = { + .description = "tl4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (884 >> 8) & 0xff, + 884 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (176 >> 8) & 0xff, + 176 & 0xff} + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (888 >> 8) & 0xff, + 888 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (177 >> 8) & 0xff, + 177 & 0xff} + }, + .field_info_spec = { + .description = "tl4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (892 >> 8) & 0xff, + 892 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_TL4_HDR_VALID_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (178 >> 8) & 0xff, + 178 & 0xff} + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (896 >> 8) & 0xff, + 896 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (179 >> 8) & 0xff, + 179 & 0xff} + }, + .field_info_spec = { + .description = "tl3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (900 >> 8) & 0xff, + 900 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_TL3_HDR_ISIP_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (180 >> 8) & 0xff, + 180 & 0xff} + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (904 >> 8) & 0xff, + 904 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (181 >> 8) & 0xff, + 181 & 0xff} + }, + .field_info_spec = { + .description = "tl3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (908 >> 8) & 0xff, + 908 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_TL3_HDR_TYPE_IPV6}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (182 >> 8) & 0xff, + 182 & 0xff} + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (912 >> 8) & 0xff, + 912 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (183 >> 8) & 0xff, + 183 & 0xff} + }, + .field_info_spec = { + .description = "tl3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (916 >> 8) & 0xff, + 916 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (184 >> 8) & 0xff, + 184 & 0xff} + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tl3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (920 >> 8) & 0xff, + 920 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_TL3_HDR_VALID_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (185 >> 8) & 0xff, + 185 & 0xff} + } + }, + { + .field_info_mask = { + .description = "tl2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (924 >> 8) & 0xff, + 924 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (927 >> 8) & 0xff, + 927 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_TL2_TWO_VTAGS_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_CONST + } + }, + { + .field_info_mask = { + .description = "tl2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (930 >> 8) & 0xff, + 930 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (933 >> 8) & 0xff, + 933 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_TL2_VTAG_PRESENT_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_CONST + } + }, + { + .field_info_mask = { + .description = "tl2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (936 >> 8) & 0xff, + 936 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (937 >> 8) & 0xff, + 937 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tl2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (938 >> 8) & 0xff, + 938 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_TL2_HDR_VALID_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "ot_hdr_flags", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "ot_hdr_flags", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "ot_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "ot_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "ot_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "ot_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "ot_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "ot_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl4_hdr_is_tcp_udp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl4_hdr_is_tcp_udp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "int_ifa_tail", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "int_ifa_tail", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "int_hdr_group", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "int_hdr_group", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "int_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "int_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "hrec_next", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "hrec_next", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "prof_func_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "prof_func_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_PROF_FUNC_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_PROF_FUNC_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2ip_func_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2ip_func_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "agg_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "agg_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "metadata", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "metadata", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "recycle_count", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "recycle_count", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "pkt_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "pkt_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "spare", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "spare", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + } + }, + { + .field_info_mask = { + .description = "padding", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "padding", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + /* class_tid: 1, , table: proto_header_cache.wr */ + { + .field_info_mask = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "prof_func_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "prof_func_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_PROF_FUNC_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_PROF_FUNC_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "hdr_bitmap", + .field_bit_size = 64, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "hdr_bitmap", + .field_bit_size = 64, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_HDR_BITMAP >> 8) & 0xff, + BNXT_ULP_CF_IDX_HDR_BITMAP & 0xff} + } + }, + /* class_tid: 1, , table: em_flow_conflict_cache.rd */ + { + .field_info_mask = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "prof_func_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "prof_func_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_PROF_FUNC_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_PROF_FUNC_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "hdr_bitmap", + .field_bit_size = 64, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "hdr_bitmap", + .field_bit_size = 64, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_HDR_BITMAP >> 8) & 0xff, + BNXT_ULP_CF_IDX_HDR_BITMAP & 0xff} + } + }, + /* class_tid: 1, , table: em_key_recipe.0 */ + { + .field_info_mask = { + .description = "em_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "em_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2_cntxt_id", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1199 >> 8) & 0xff, + 1199 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + .field_info_spec = { + .description = "l2_cntxt_id", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1200 >> 8) & 0xff, + 1200 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_RF, + .field_opr2 = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + } + }, + { + .field_info_mask = { + .description = "meta", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1201 >> 8) & 0xff, + 1201 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + .field_info_spec = { + .description = "meta", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1202 >> 8) & 0xff, + 1202 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CF, + .field_opr2 = { + (BNXT_ULP_CF_IDX_VF_META_FID >> 8) & 0xff, + BNXT_ULP_CF_IDX_VF_META_FID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + } + }, + { + .field_info_mask = { + .description = "rcyc_cnt", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1203 >> 8) & 0xff, + 1203 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + .field_info_spec = { + .description = "rcyc_cnt", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1204 >> 8) & 0xff, + 1204 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_RF, + .field_opr2 = { + (BNXT_ULP_RF_IDX_RECYCLE_CNT >> 8) & 0xff, + BNXT_ULP_RF_IDX_RECYCLE_CNT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1205 >> 8) & 0xff, + 1205 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + .field_info_spec = { + .description = "tl2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1209 >> 8) & 0xff, + 1209 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1213 >> 8) & 0xff, + 1213 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + .field_info_spec = { + .description = "tl2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1216 >> 8) & 0xff, + 1216 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1219 >> 8) & 0xff, + 1219 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + .field_info_spec = { + .description = "tl2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1223 >> 8) & 0xff, + 1223 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1227 >> 8) & 0xff, + 1227 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (229 >> 8) & 0xff, + 229 & 0xff} + }, + .field_info_spec = { + .description = "tl2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1235 >> 8) & 0xff, + 1235 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_OI_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OI_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (230 >> 8) & 0xff, + 230 & 0xff} + } + }, + { + .field_info_mask = { + .description = "tl2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1243 >> 8) & 0xff, + 1243 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + .field_info_spec = { + .description = "tl2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1247 >> 8) & 0xff, + 1247 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1251 >> 8) & 0xff, + 1251 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + .field_info_spec = { + .description = "tl3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1254 >> 8) & 0xff, + 1254 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1257 >> 8) & 0xff, + 1257 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + .field_info_spec = { + .description = "tl3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1260 >> 8) & 0xff, + 1260 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1263 >> 8) & 0xff, + 1263 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + .field_info_spec = { + .description = "tl3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1266 >> 8) & 0xff, + 1266 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1269 >> 8) & 0xff, + 1269 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + .field_info_spec = { + .description = "tl3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1272 >> 8) & 0xff, + 1272 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1275 >> 8) & 0xff, + 1275 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (231 >> 8) & 0xff, + 231 & 0xff} + }, + .field_info_spec = { + .description = "tl3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1281 >> 8) & 0xff, + 1281 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_TTL >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_TTL & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (232 >> 8) & 0xff, + 232 & 0xff} + } + }, + { + .field_info_mask = { + .description = "tl3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1287 >> 8) & 0xff, + 1287 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (233 >> 8) & 0xff, + 233 & 0xff} + }, + .field_info_spec = { + .description = "tl3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1293 >> 8) & 0xff, + 1293 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (234 >> 8) & 0xff, + 234 & 0xff} + } + }, + { + .field_info_mask = { + .description = "tl3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1299 >> 8) & 0xff, + 1299 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (235 >> 8) & 0xff, + 235 & 0xff} + }, + .field_info_spec = { + .description = "tl3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1305 >> 8) & 0xff, + 1305 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_QOS >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_QOS & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (236 >> 8) & 0xff, + 236 & 0xff} + } + }, + { + .field_info_mask = { + .description = "tl4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1311 >> 8) & 0xff, + 1311 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (237 >> 8) & 0xff, + 237 & 0xff} + }, + .field_info_spec = { + .description = "tl4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1317 >> 8) & 0xff, + 1317 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (238 >> 8) & 0xff, + 238 & 0xff} + } + }, + { + .field_info_mask = { + .description = "tl4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1323 >> 8) & 0xff, + 1323 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (239 >> 8) & 0xff, + 239 & 0xff} + }, + .field_info_spec = { + .description = "tl4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1329 >> 8) & 0xff, + 1329 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (240 >> 8) & 0xff, + 240 & 0xff} + } + }, + { + .field_info_mask = { + .description = "tids", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1335 >> 8) & 0xff, + 1335 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (241 >> 8) & 0xff, + 241 & 0xff} + }, + .field_info_spec = { + .description = "tids", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1339 >> 8) & 0xff, + 1339 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (242 >> 8) & 0xff, + 242 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1343 >> 8) & 0xff, + 1343 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (243 >> 8) & 0xff, + 243 & 0xff} + }, + .field_info_spec = { + .description = "l2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1351 >> 8) & 0xff, + 1351 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (244 >> 8) & 0xff, + 244 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1359 >> 8) & 0xff, + 1359 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (245 >> 8) & 0xff, + 245 & 0xff} + }, + .field_info_spec = { + .description = "l2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1365 >> 8) & 0xff, + 1365 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (246 >> 8) & 0xff, + 246 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1371 >> 8) & 0xff, + 1371 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (247 >> 8) & 0xff, + 247 & 0xff} + }, + .field_info_spec = { + .description = "l2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1379 >> 8) & 0xff, + 1379 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_IO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_IO_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (248 >> 8) & 0xff, + 248 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1387 >> 8) & 0xff, + 1387 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (249 >> 8) & 0xff, + 249 & 0xff} + }, + .field_info_spec = { + .description = "l2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1403 >> 8) & 0xff, + 1403 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_II_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_II_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (252 >> 8) & 0xff, + 252 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1419 >> 8) & 0xff, + 1419 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (255 >> 8) & 0xff, + 255 & 0xff} + }, + .field_info_spec = { + .description = "l2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1427 >> 8) & 0xff, + 1427 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_ETH_TYPE >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_ETH_TYPE & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (256 >> 8) & 0xff, + 256 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1435 >> 8) & 0xff, + 1435 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (257 >> 8) & 0xff, + 257 & 0xff} + }, + .field_info_spec = { + .description = "l3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1441 >> 8) & 0xff, + 1441 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (258 >> 8) & 0xff, + 258 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1447 >> 8) & 0xff, + 1447 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (259 >> 8) & 0xff, + 259 & 0xff} + }, + .field_info_spec = { + .description = "l3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1453 >> 8) & 0xff, + 1453 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (260 >> 8) & 0xff, + 260 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1459 >> 8) & 0xff, + 1459 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (261 >> 8) & 0xff, + 261 & 0xff} + }, + .field_info_spec = { + .description = "l3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1465 >> 8) & 0xff, + 1465 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (262 >> 8) & 0xff, + 262 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1471 >> 8) & 0xff, + 1471 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (263 >> 8) & 0xff, + 263 & 0xff} + }, + .field_info_spec = { + .description = "l3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1477 >> 8) & 0xff, + 1477 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (264 >> 8) & 0xff, + 264 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1483 >> 8) & 0xff, + 1483 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (265 >> 8) & 0xff, + 265 & 0xff} + }, + .field_info_spec = { + .description = "l3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1495 >> 8) & 0xff, + 1495 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_IPV6_TTL >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV6_TTL & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (268 >> 8) & 0xff, + 268 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1507 >> 8) & 0xff, + 1507 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (271 >> 8) & 0xff, + 271 & 0xff} + }, + .field_info_spec = { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1519 >> 8) & 0xff, + 1519 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_IPV6_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV6_PROTO_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (274 >> 8) & 0xff, + 274 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1531 >> 8) & 0xff, + 1531 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (277 >> 8) & 0xff, + 277 & 0xff} + }, + .field_info_spec = { + .description = "l3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1543 >> 8) & 0xff, + 1543 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_IPV6_QOS >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV6_QOS & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (280 >> 8) & 0xff, + 280 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1555 >> 8) & 0xff, + 1555 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (283 >> 8) & 0xff, + 283 & 0xff} + }, + .field_info_spec = { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1567 >> 8) & 0xff, + 1567 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_UDP_SRC_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (286 >> 8) & 0xff, + 286 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1579 >> 8) & 0xff, + 1579 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (289 >> 8) & 0xff, + 289 & 0xff} + }, + .field_info_spec = { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1591 >> 8) & 0xff, + 1591 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_UDP_DST_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (292 >> 8) & 0xff, + 292 & 0xff} + } + }, + /* class_tid: 1, , table: em_flow_conflict_cache.wr */ + { + .field_info_mask = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "prof_func_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "prof_func_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_PROF_FUNC_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_PROF_FUNC_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "hdr_bitmap", + .field_bit_size = 64, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "hdr_bitmap", + .field_bit_size = 64, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_HDR_BITMAP >> 8) & 0xff, + BNXT_ULP_CF_IDX_HDR_BITMAP & 0xff} + } + }, + /* class_tid: 2, , table: port_table.get_def_rd */ + { + .field_info_mask = { + .description = "dev.port_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "dev.port_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff} + } + }, + /* class_tid: 2, , table: l2_cntxt_tcam_cache.def_rd */ + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + } + }, + /* class_tid: 2, , table: proto_header_cache.rd */ + { + .field_info_mask = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "prof_func_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "prof_func_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_PROF_FUNC_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_PROF_FUNC_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "hdr_bitmap", + .field_bit_size = 64, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "hdr_bitmap", + .field_bit_size = 64, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_HDR_BITMAP >> 8) & 0xff, + BNXT_ULP_CF_IDX_HDR_BITMAP & 0xff} + } + }, + /* class_tid: 2, , table: hdr_overlap_cache.overlap_check */ + { + .field_info_mask = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "prof_func_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "prof_func_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_PROF_FUNC_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_PROF_FUNC_ID_0 & 0xff} + } + }, + /* class_tid: 2, , table: hdr_overlap_cache.overlap_wr */ + { + .field_info_mask = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "prof_func_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "prof_func_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_PROF_FUNC_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_PROF_FUNC_ID_0 & 0xff} + } + }, + /* class_tid: 2, , table: wm_key_recipe.0 */ + { + .field_info_mask = { + .description = "wc_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "wc_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_WC_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_WC_PROFILE_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2_cntxt_id", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1862 >> 8) & 0xff, + 1862 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + .field_info_spec = { + .description = "l2_cntxt_id", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1863 >> 8) & 0xff, + 1863 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_RF, + .field_opr2 = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + } + }, + { + .field_info_mask = { + .description = "meta", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1864 >> 8) & 0xff, + 1864 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + .field_info_spec = { + .description = "meta", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1865 >> 8) & 0xff, + 1865 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CF, + .field_opr2 = { + (BNXT_ULP_CF_IDX_VF_META_FID >> 8) & 0xff, + BNXT_ULP_CF_IDX_VF_META_FID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + } + }, + { + .field_info_mask = { + .description = "rcyc_cnt", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1866 >> 8) & 0xff, + 1866 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + .field_info_spec = { + .description = "rcyc_cnt", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1867 >> 8) & 0xff, + 1867 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_RF, + .field_opr2 = { + (BNXT_ULP_RF_IDX_RECYCLE_CNT >> 8) & 0xff, + BNXT_ULP_RF_IDX_RECYCLE_CNT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1868 >> 8) & 0xff, + 1868 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + .field_info_spec = { + .description = "tl2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1871 >> 8) & 0xff, + 1871 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1874 >> 8) & 0xff, + 1874 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + .field_info_spec = { + .description = "tl2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1878 >> 8) & 0xff, + 1878 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1882 >> 8) & 0xff, + 1882 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_OI_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OI_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (338 >> 8) & 0xff, + 338 & 0xff} + }, + .field_info_spec = { + .description = "tl2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1890 >> 8) & 0xff, + 1890 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_OI_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OI_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (339 >> 8) & 0xff, + 339 & 0xff} + } + }, + { + .field_info_mask = { + .description = "tl2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1898 >> 8) & 0xff, + 1898 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_TYPE >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_TYPE & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + .field_info_spec = { + .description = "tl2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1902 >> 8) & 0xff, + 1902 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_TYPE >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_TYPE & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1906 >> 8) & 0xff, + 1906 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + .field_info_spec = { + .description = "tl3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1909 >> 8) & 0xff, + 1909 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1912 >> 8) & 0xff, + 1912 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + .field_info_spec = { + .description = "tl3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1915 >> 8) & 0xff, + 1915 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1918 >> 8) & 0xff, + 1918 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + .field_info_spec = { + .description = "tl3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1921 >> 8) & 0xff, + 1921 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1924 >> 8) & 0xff, + 1924 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + .field_info_spec = { + .description = "tl3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1927 >> 8) & 0xff, + 1927 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1930 >> 8) & 0xff, + 1930 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_TTL >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_TTL & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (340 >> 8) & 0xff, + 340 & 0xff} + }, + .field_info_spec = { + .description = "tl3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1936 >> 8) & 0xff, + 1936 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_TTL >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_TTL & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (341 >> 8) & 0xff, + 341 & 0xff} + } + }, + { + .field_info_mask = { + .description = "tl3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1942 >> 8) & 0xff, + 1942 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (342 >> 8) & 0xff, + 342 & 0xff} + }, + .field_info_spec = { + .description = "tl3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1948 >> 8) & 0xff, + 1948 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (343 >> 8) & 0xff, + 343 & 0xff} + } + }, + { + .field_info_mask = { + .description = "tl3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1954 >> 8) & 0xff, + 1954 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_QOS >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_QOS & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (344 >> 8) & 0xff, + 344 & 0xff} + }, + .field_info_spec = { + .description = "tl3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1960 >> 8) & 0xff, + 1960 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_QOS >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_QOS & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (345 >> 8) & 0xff, + 345 & 0xff} + } + }, + { + .field_info_mask = { + .description = "tl4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1966 >> 8) & 0xff, + 1966 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (346 >> 8) & 0xff, + 346 & 0xff} + }, + .field_info_spec = { + .description = "tl4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1972 >> 8) & 0xff, + 1972 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (347 >> 8) & 0xff, + 347 & 0xff} + } + }, + { + .field_info_mask = { + .description = "tl4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1978 >> 8) & 0xff, + 1978 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (348 >> 8) & 0xff, + 348 & 0xff} + }, + .field_info_spec = { + .description = "tl4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1984 >> 8) & 0xff, + 1984 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (349 >> 8) & 0xff, + 349 & 0xff} + } + }, + { + .field_info_mask = { + .description = "tids", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1990 >> 8) & 0xff, + 1990 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (350 >> 8) & 0xff, + 350 & 0xff} + }, + .field_info_spec = { + .description = "tids", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1994 >> 8) & 0xff, + 1994 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (351 >> 8) & 0xff, + 351 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1998 >> 8) & 0xff, + 1998 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (352 >> 8) & 0xff, + 352 & 0xff} + }, + .field_info_spec = { + .description = "l2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2004 >> 8) & 0xff, + 2004 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (353 >> 8) & 0xff, + 353 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2010 >> 8) & 0xff, + 2010 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (354 >> 8) & 0xff, + 354 & 0xff} + }, + .field_info_spec = { + .description = "l2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2016 >> 8) & 0xff, + 2016 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (355 >> 8) & 0xff, + 355 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2022 >> 8) & 0xff, + 2022 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_IO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_IO_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (356 >> 8) & 0xff, + 356 & 0xff} + }, + .field_info_spec = { + .description = "l2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2030 >> 8) & 0xff, + 2030 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_IO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_IO_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (357 >> 8) & 0xff, + 357 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2038 >> 8) & 0xff, + 2038 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_II_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_II_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (358 >> 8) & 0xff, + 358 & 0xff} + }, + .field_info_spec = { + .description = "l2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2054 >> 8) & 0xff, + 2054 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_II_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_II_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (361 >> 8) & 0xff, + 361 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2070 >> 8) & 0xff, + 2070 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_ETH_TYPE >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_ETH_TYPE & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (364 >> 8) & 0xff, + 364 & 0xff} + }, + .field_info_spec = { + .description = "l2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2078 >> 8) & 0xff, + 2078 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_ETH_TYPE >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_ETH_TYPE & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (365 >> 8) & 0xff, + 365 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2086 >> 8) & 0xff, + 2086 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (366 >> 8) & 0xff, + 366 & 0xff} + }, + .field_info_spec = { + .description = "l3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2092 >> 8) & 0xff, + 2092 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (367 >> 8) & 0xff, + 367 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2098 >> 8) & 0xff, + 2098 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (368 >> 8) & 0xff, + 368 & 0xff} + }, + .field_info_spec = { + .description = "l3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2104 >> 8) & 0xff, + 2104 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (369 >> 8) & 0xff, + 369 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2110 >> 8) & 0xff, + 2110 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (370 >> 8) & 0xff, + 370 & 0xff} + }, + .field_info_spec = { + .description = "l3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2116 >> 8) & 0xff, + 2116 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (371 >> 8) & 0xff, + 371 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2122 >> 8) & 0xff, + 2122 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (372 >> 8) & 0xff, + 372 & 0xff} + }, + .field_info_spec = { + .description = "l3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2128 >> 8) & 0xff, + 2128 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (373 >> 8) & 0xff, + 373 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2134 >> 8) & 0xff, + 2134 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_IPV6_TTL >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV6_TTL & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (374 >> 8) & 0xff, + 374 & 0xff} + }, + .field_info_spec = { + .description = "l3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2146 >> 8) & 0xff, + 2146 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_IPV6_TTL >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV6_TTL & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (377 >> 8) & 0xff, + 377 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2158 >> 8) & 0xff, + 2158 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_IPV6_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV6_PROTO_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (380 >> 8) & 0xff, + 380 & 0xff} + }, + .field_info_spec = { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2170 >> 8) & 0xff, + 2170 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_IPV6_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV6_PROTO_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (383 >> 8) & 0xff, + 383 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2182 >> 8) & 0xff, + 2182 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_IPV6_QOS >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV6_QOS & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (386 >> 8) & 0xff, + 386 & 0xff} + }, + .field_info_spec = { + .description = "l3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2194 >> 8) & 0xff, + 2194 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_IPV6_QOS >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV6_QOS & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (389 >> 8) & 0xff, + 389 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2206 >> 8) & 0xff, + 2206 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_UDP_SRC_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (392 >> 8) & 0xff, + 392 & 0xff} + }, + .field_info_spec = { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2218 >> 8) & 0xff, + 2218 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_UDP_SRC_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (395 >> 8) & 0xff, + 395 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2230 >> 8) & 0xff, + 2230 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_UDP_DST_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (398 >> 8) & 0xff, + 398 & 0xff} + }, + .field_info_spec = { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2242 >> 8) & 0xff, + 2242 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_UDP_DST_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (401 >> 8) & 0xff, + 401 & 0xff} + } + }, + /* class_tid: 2, , table: profile_tcam.gen_template */ + { + .field_info_mask = { + .description = "l4_hdr_dcn_present", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l4_hdr_dcn_present", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4_hdr_flags", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l4_hdr_flags", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4_hdr_subtype", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l4_hdr_subtype", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2254 >> 8) & 0xff, + 2254 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (404 >> 8) & 0xff, + 404 & 0xff} + }, + .field_info_spec = { + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2262 >> 8) & 0xff, + 2262 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_L4_HDR_IS_UDP_TCP_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (407 >> 8) & 0xff, + 407 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2270 >> 8) & 0xff, + 2270 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (410 >> 8) & 0xff, + 410 & 0xff} + }, + .field_info_spec = { + .description = "l4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2278 >> 8) & 0xff, + 2278 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (413 >> 8) & 0xff, + 413 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2286 >> 8) & 0xff, + 2286 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (416 >> 8) & 0xff, + 416 & 0xff} + }, + .field_info_spec = { + .description = "l4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2294 >> 8) & 0xff, + 2294 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (419 >> 8) & 0xff, + 419 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2302 >> 8) & 0xff, + 2302 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (422 >> 8) & 0xff, + 422 & 0xff} + }, + .field_info_spec = { + .description = "l4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2310 >> 8) & 0xff, + 2310 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_L4_HDR_VALID_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (425 >> 8) & 0xff, + 425 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l3_protocol", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3_protocol", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2318 >> 8) & 0xff, + 2318 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_L3_HDR_ISIP_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (428 >> 8) & 0xff, + 428 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2326 >> 8) & 0xff, + 2326 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (431 >> 8) & 0xff, + 431 & 0xff} + }, + .field_info_spec = { + .description = "l3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2334 >> 8) & 0xff, + 2334 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_L3_HDR_TYPE_IPV6}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (434 >> 8) & 0xff, + 434 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2342 >> 8) & 0xff, + 2342 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (437 >> 8) & 0xff, + 437 & 0xff} + }, + .field_info_spec = { + .description = "l3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2350 >> 8) & 0xff, + 2350 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (440 >> 8) & 0xff, + 440 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2358 >> 8) & 0xff, + 2358 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (443 >> 8) & 0xff, + 443 & 0xff} + }, + .field_info_spec = { + .description = "l3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2366 >> 8) & 0xff, + 2366 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_L3_HDR_VALID_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (446 >> 8) & 0xff, + 446 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2374 >> 8) & 0xff, + 2374 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (449 >> 8) & 0xff, + 449 & 0xff} + }, + .field_info_spec = { + .description = "l2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2380 >> 8) & 0xff, + 2380 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_L2_TWO_VTAGS_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (450 >> 8) & 0xff, + 450 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2386 >> 8) & 0xff, + 2386 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (451 >> 8) & 0xff, + 451 & 0xff} + }, + .field_info_spec = { + .description = "l2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2392 >> 8) & 0xff, + 2392 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_L2_VTAG_PRESENT_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (452 >> 8) & 0xff, + 452 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2398 >> 8) & 0xff, + 2398 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2399 >> 8) & 0xff, + 2399 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2400 >> 8) & 0xff, + 2400 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (453 >> 8) & 0xff, + 453 & 0xff} + }, + .field_info_spec = { + .description = "l2_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2404 >> 8) & 0xff, + 2404 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (454 >> 8) & 0xff, + 454 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2408 >> 8) & 0xff, + 2408 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_L2_HDR_VALID_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (455 >> 8) & 0xff, + 455 & 0xff} + } + }, + { + .field_info_mask = { + .description = "tun_hdr_flags", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_flags", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2412 >> 8) & 0xff, + 2412 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (456 >> 8) & 0xff, + 456 & 0xff} + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2424 >> 8) & 0xff, + 2424 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (461 >> 8) & 0xff, + 461 & 0xff} + } + }, + { + .field_info_mask = { + .description = "tun_hdr_err", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2436 >> 8) & 0xff, + 2436 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_err", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2437 >> 8) & 0xff, + 2437 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tun_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2438 >> 8) & 0xff, + 2438 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_TUN_HDR_VALID_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2439 >> 8) & 0xff, + 2439 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (466 >> 8) & 0xff, + 466 & 0xff} + }, + .field_info_spec = { + .description = "tl4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2443 >> 8) & 0xff, + 2443 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_TL4_HDR_IS_UDP_TCP_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (467 >> 8) & 0xff, + 467 & 0xff} + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2447 >> 8) & 0xff, + 2447 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (468 >> 8) & 0xff, + 468 & 0xff} + }, + .field_info_spec = { + .description = "tl4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2451 >> 8) & 0xff, + 2451 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (469 >> 8) & 0xff, + 469 & 0xff} + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2455 >> 8) & 0xff, + 2455 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (470 >> 8) & 0xff, + 470 & 0xff} + }, + .field_info_spec = { + .description = "tl4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2459 >> 8) & 0xff, + 2459 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (471 >> 8) & 0xff, + 471 & 0xff} + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2463 >> 8) & 0xff, + 2463 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (472 >> 8) & 0xff, + 472 & 0xff} + }, + .field_info_spec = { + .description = "tl4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2467 >> 8) & 0xff, + 2467 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_TL4_HDR_VALID_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (473 >> 8) & 0xff, + 473 & 0xff} + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2471 >> 8) & 0xff, + 2471 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (474 >> 8) & 0xff, + 474 & 0xff} + }, + .field_info_spec = { + .description = "tl3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2475 >> 8) & 0xff, + 2475 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_TL3_HDR_ISIP_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (475 >> 8) & 0xff, + 475 & 0xff} + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2479 >> 8) & 0xff, + 2479 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (476 >> 8) & 0xff, + 476 & 0xff} + }, + .field_info_spec = { + .description = "tl3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2483 >> 8) & 0xff, + 2483 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_TL3_HDR_TYPE_IPV6}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (477 >> 8) & 0xff, + 477 & 0xff} + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2487 >> 8) & 0xff, + 2487 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (478 >> 8) & 0xff, + 478 & 0xff} + }, + .field_info_spec = { + .description = "tl3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2491 >> 8) & 0xff, + 2491 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (479 >> 8) & 0xff, + 479 & 0xff} + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tl3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2495 >> 8) & 0xff, + 2495 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_TL3_HDR_VALID_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (480 >> 8) & 0xff, + 480 & 0xff} + } + }, + { + .field_info_mask = { + .description = "tl2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2499 >> 8) & 0xff, + 2499 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2502 >> 8) & 0xff, + 2502 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_TL2_TWO_VTAGS_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_CONST + } + }, + { + .field_info_mask = { + .description = "tl2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2505 >> 8) & 0xff, + 2505 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2508 >> 8) & 0xff, + 2508 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_TL2_VTAG_PRESENT_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_CONST + } + }, + { + .field_info_mask = { + .description = "tl2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2511 >> 8) & 0xff, + 2511 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2512 >> 8) & 0xff, + 2512 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tl2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2513 >> 8) & 0xff, + 2513 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_TL2_HDR_VALID_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "ot_hdr_flags", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "ot_hdr_flags", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "ot_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "ot_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "ot_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "ot_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "ot_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "ot_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl4_hdr_is_tcp_udp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl4_hdr_is_tcp_udp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "int_ifa_tail", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "int_ifa_tail", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "int_hdr_group", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "int_hdr_group", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "int_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "int_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "hrec_next", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "hrec_next", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "prof_func_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "prof_func_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_PROF_FUNC_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_PROF_FUNC_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2ip_func_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2ip_func_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "agg_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "agg_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "metadata", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "metadata", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "recycle_count", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "recycle_count", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "pkt_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "pkt_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "spare", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "spare", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + } + }, + { + .field_info_mask = { + .description = "padding", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "padding", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + /* class_tid: 2, , table: proto_header_cache.wr */ + { + .field_info_mask = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "prof_func_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "prof_func_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_PROF_FUNC_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_PROF_FUNC_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "hdr_bitmap", + .field_bit_size = 64, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "hdr_bitmap", + .field_bit_size = 64, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_HDR_BITMAP >> 8) & 0xff, + BNXT_ULP_CF_IDX_HDR_BITMAP & 0xff} + } + }, + /* class_tid: 2, , table: em_flow_conflict_cache.rd */ + { + .field_info_mask = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "prof_func_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "prof_func_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_PROF_FUNC_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_PROF_FUNC_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "hdr_bitmap", + .field_bit_size = 64, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "hdr_bitmap", + .field_bit_size = 64, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_HDR_BITMAP >> 8) & 0xff, + BNXT_ULP_CF_IDX_HDR_BITMAP & 0xff} + } + }, + /* class_tid: 2, , table: em_key_recipe.0 */ + { + .field_info_mask = { + .description = "em_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "em_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2_cntxt_id", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2774 >> 8) & 0xff, + 2774 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + .field_info_spec = { + .description = "l2_cntxt_id", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2775 >> 8) & 0xff, + 2775 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_RF, + .field_opr2 = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + } + }, + { + .field_info_mask = { + .description = "meta", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2776 >> 8) & 0xff, + 2776 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + .field_info_spec = { + .description = "meta", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2777 >> 8) & 0xff, + 2777 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CF, + .field_opr2 = { + (BNXT_ULP_CF_IDX_VF_META_FID >> 8) & 0xff, + BNXT_ULP_CF_IDX_VF_META_FID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + } + }, + { + .field_info_mask = { + .description = "rcyc_cnt", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2778 >> 8) & 0xff, + 2778 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + .field_info_spec = { + .description = "rcyc_cnt", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2779 >> 8) & 0xff, + 2779 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_RF, + .field_opr2 = { + (BNXT_ULP_RF_IDX_RECYCLE_CNT >> 8) & 0xff, + BNXT_ULP_RF_IDX_RECYCLE_CNT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2780 >> 8) & 0xff, + 2780 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + .field_info_spec = { + .description = "tl2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2784 >> 8) & 0xff, + 2784 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2788 >> 8) & 0xff, + 2788 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + .field_info_spec = { + .description = "tl2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2791 >> 8) & 0xff, + 2791 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2794 >> 8) & 0xff, + 2794 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + .field_info_spec = { + .description = "tl2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2798 >> 8) & 0xff, + 2798 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2802 >> 8) & 0xff, + 2802 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (524 >> 8) & 0xff, + 524 & 0xff} + }, + .field_info_spec = { + .description = "tl2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2810 >> 8) & 0xff, + 2810 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_OI_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OI_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (525 >> 8) & 0xff, + 525 & 0xff} + } + }, + { + .field_info_mask = { + .description = "tl2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2818 >> 8) & 0xff, + 2818 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + .field_info_spec = { + .description = "tl2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2822 >> 8) & 0xff, + 2822 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2826 >> 8) & 0xff, + 2826 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + .field_info_spec = { + .description = "tl3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2829 >> 8) & 0xff, + 2829 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2832 >> 8) & 0xff, + 2832 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + .field_info_spec = { + .description = "tl3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2835 >> 8) & 0xff, + 2835 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2838 >> 8) & 0xff, + 2838 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + .field_info_spec = { + .description = "tl3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2841 >> 8) & 0xff, + 2841 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2844 >> 8) & 0xff, + 2844 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + .field_info_spec = { + .description = "tl3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2847 >> 8) & 0xff, + 2847 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + } + }, + { + .field_info_mask = { + .description = "tl3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2850 >> 8) & 0xff, + 2850 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (526 >> 8) & 0xff, + 526 & 0xff} + }, + .field_info_spec = { + .description = "tl3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2856 >> 8) & 0xff, + 2856 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_TTL >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_TTL & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (527 >> 8) & 0xff, + 527 & 0xff} + } + }, + { + .field_info_mask = { + .description = "tl3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2862 >> 8) & 0xff, + 2862 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (528 >> 8) & 0xff, + 528 & 0xff} + }, + .field_info_spec = { + .description = "tl3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2868 >> 8) & 0xff, + 2868 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (529 >> 8) & 0xff, + 529 & 0xff} + } + }, + { + .field_info_mask = { + .description = "tl3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2874 >> 8) & 0xff, + 2874 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (530 >> 8) & 0xff, + 530 & 0xff} + }, + .field_info_spec = { + .description = "tl3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2880 >> 8) & 0xff, + 2880 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_QOS >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_QOS & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (531 >> 8) & 0xff, + 531 & 0xff} + } + }, + { + .field_info_mask = { + .description = "tl4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2886 >> 8) & 0xff, + 2886 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (532 >> 8) & 0xff, + 532 & 0xff} + }, + .field_info_spec = { + .description = "tl4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2892 >> 8) & 0xff, + 2892 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (533 >> 8) & 0xff, + 533 & 0xff} + } + }, + { + .field_info_mask = { + .description = "tl4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2898 >> 8) & 0xff, + 2898 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (534 >> 8) & 0xff, + 534 & 0xff} + }, + .field_info_spec = { + .description = "tl4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2904 >> 8) & 0xff, + 2904 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (535 >> 8) & 0xff, + 535 & 0xff} + } + }, + { + .field_info_mask = { + .description = "tids", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2910 >> 8) & 0xff, + 2910 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (536 >> 8) & 0xff, + 536 & 0xff} + }, + .field_info_spec = { + .description = "tids", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2914 >> 8) & 0xff, + 2914 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (537 >> 8) & 0xff, + 537 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2918 >> 8) & 0xff, + 2918 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (538 >> 8) & 0xff, + 538 & 0xff} + }, + .field_info_spec = { + .description = "l2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2926 >> 8) & 0xff, + 2926 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (539 >> 8) & 0xff, + 539 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2934 >> 8) & 0xff, + 2934 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (540 >> 8) & 0xff, + 540 & 0xff} + }, + .field_info_spec = { + .description = "l2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2940 >> 8) & 0xff, + 2940 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (541 >> 8) & 0xff, + 541 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2946 >> 8) & 0xff, + 2946 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (542 >> 8) & 0xff, + 542 & 0xff} + }, + .field_info_spec = { + .description = "l2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2954 >> 8) & 0xff, + 2954 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_IO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_IO_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (543 >> 8) & 0xff, + 543 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2962 >> 8) & 0xff, + 2962 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (544 >> 8) & 0xff, + 544 & 0xff} + }, + .field_info_spec = { + .description = "l2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2978 >> 8) & 0xff, + 2978 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_II_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_II_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (547 >> 8) & 0xff, + 547 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2994 >> 8) & 0xff, + 2994 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (550 >> 8) & 0xff, + 550 & 0xff} + }, + .field_info_spec = { + .description = "l2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (3002 >> 8) & 0xff, + 3002 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_ETH_TYPE >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_ETH_TYPE & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (551 >> 8) & 0xff, + 551 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (3010 >> 8) & 0xff, + 3010 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (552 >> 8) & 0xff, + 552 & 0xff} + }, + .field_info_spec = { + .description = "l3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (3016 >> 8) & 0xff, + 3016 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (553 >> 8) & 0xff, + 553 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (3022 >> 8) & 0xff, + 3022 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (554 >> 8) & 0xff, + 554 & 0xff} + }, + .field_info_spec = { + .description = "l3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (3028 >> 8) & 0xff, + 3028 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (555 >> 8) & 0xff, + 555 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (3034 >> 8) & 0xff, + 3034 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (556 >> 8) & 0xff, + 556 & 0xff} + }, + .field_info_spec = { + .description = "l3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (3040 >> 8) & 0xff, + 3040 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (557 >> 8) & 0xff, + 557 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (3046 >> 8) & 0xff, + 3046 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (558 >> 8) & 0xff, + 558 & 0xff} + }, + .field_info_spec = { + .description = "l3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (3052 >> 8) & 0xff, + 3052 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (559 >> 8) & 0xff, + 559 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (3058 >> 8) & 0xff, + 3058 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (560 >> 8) & 0xff, + 560 & 0xff} + }, + .field_info_spec = { + .description = "l3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (3070 >> 8) & 0xff, + 3070 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_IPV6_TTL >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV6_TTL & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (563 >> 8) & 0xff, + 563 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (3082 >> 8) & 0xff, + 3082 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (566 >> 8) & 0xff, + 566 & 0xff} + }, + .field_info_spec = { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (3094 >> 8) & 0xff, + 3094 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_IPV6_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV6_PROTO_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (569 >> 8) & 0xff, + 569 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (3106 >> 8) & 0xff, + 3106 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (572 >> 8) & 0xff, + 572 & 0xff} + }, + .field_info_spec = { + .description = "l3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (3118 >> 8) & 0xff, + 3118 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_IPV6_QOS >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV6_QOS & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (575 >> 8) & 0xff, + 575 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (3130 >> 8) & 0xff, + 3130 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (578 >> 8) & 0xff, + 578 & 0xff} + }, + .field_info_spec = { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (3142 >> 8) & 0xff, + 3142 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_UDP_SRC_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (581 >> 8) & 0xff, + 581 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (3154 >> 8) & 0xff, + 3154 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (584 >> 8) & 0xff, + 584 & 0xff} + }, + .field_info_spec = { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (3166 >> 8) & 0xff, + 3166 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_UDP_DST_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (587 >> 8) & 0xff, + 587 & 0xff} + } + }, + /* class_tid: 2, , table: em_flow_conflict_cache.wr */ + { + .field_info_mask = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "prof_func_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "prof_func_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_PROF_FUNC_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_PROF_FUNC_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "hdr_bitmap", + .field_bit_size = 64, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "hdr_bitmap", + .field_bit_size = 64, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_HDR_BITMAP >> 8) & 0xff, + BNXT_ULP_CF_IDX_HDR_BITMAP & 0xff} + } + }, + /* class_tid: 3, , table: table_scope_cache.tsid_ing_rd */ + { + .field_info_mask = { + .description = "tbl_scope", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tbl_scope", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_PORT_TABLE, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff, + (BNXT_ULP_PORT_TABLE_TABLE_SCOPE >> 8) & 0xff, + BNXT_ULP_PORT_TABLE_TABLE_SCOPE & 0xff} + } + }, + { + .field_info_mask = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + /* class_tid: 3, , table: profile_tcam_bypass.ing_catch_all */ + { + .field_info_mask = { + .description = "l4_hdr_dcn_present", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l4_hdr_dcn_present", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4_hdr_flags", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l4_hdr_flags", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4_hdr_subtype", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l4_hdr_subtype", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_protocol", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3_protocol", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_flags", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_flags", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_err", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_err", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "ot_hdr_flags", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "ot_hdr_flags", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "ot_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "ot_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "ot_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "ot_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "ot_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "ot_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl4_hdr_is_tcp_udp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl4_hdr_is_tcp_udp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "int_ifa_tail", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "int_ifa_tail", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "int_hdr_group", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "int_hdr_group", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "int_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "int_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "hrec_next", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "hrec_next", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "prof_func_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "prof_func_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_PROF_FUNC_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_PROF_FUNC_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2ip_func_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2ip_func_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "agg_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "agg_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "metadata", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "metadata", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "recycle_count", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "recycle_count", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "pkt_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "pkt_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "spare", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "spare", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + } + }, + { + .field_info_mask = { + .description = "padding", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "padding", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + /* class_tid: 3, , table: table_scope_cache.tsid_ing_wr */ + { + .field_info_mask = { + .description = "tbl_scope", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tbl_scope", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_PORT_TABLE, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff, + (BNXT_ULP_PORT_TABLE_TABLE_SCOPE >> 8) & 0xff, + BNXT_ULP_PORT_TABLE_TABLE_SCOPE & 0xff} + } + }, + { + .field_info_mask = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + /* class_tid: 3, , table: port_table.ing_wr */ + { + .field_info_mask = { + .description = "dev.port_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "dev.port_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff} + } + }, + /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_rd */ + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff} + } + }, + /* class_tid: 3, , table: l2_cntxt_tcam.svif_ing */ + { + .field_info_mask = { + .description = "etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ivlan_tpid_sel", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ivlan_tpid_sel", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ovlan_tpid_sel", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ovlan_tpid_sel", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "addr1", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "addr1", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "addr0", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "addr0", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tunnel_id", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tunnel_id", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "out_tun_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "out_tun_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "llc", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "llc", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "roce", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "roce", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2ip_func", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2ip_func", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "metadata", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "metadata", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff} + } + }, + { + .field_info_mask = { + .description = "parif", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "parif", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "spif", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "spif", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "recycle_cnt", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "recycle_cnt", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "mpass_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "mpass_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "spare", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "spare", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + } + }, + /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_wr */ + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff} + } + }, + /* class_tid: 3, , table: port_table.egr_wr_0 */ + { + .field_info_mask = { + .description = "dev.port_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "dev.port_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff} + } + }, + /* class_tid: 3, , table: table_scope_cache.tsid_vfr_rd */ + { + .field_info_mask = { + .description = "tbl_scope", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tbl_scope", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_PORT_TABLE, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff, + (BNXT_ULP_PORT_TABLE_TABLE_SCOPE >> 8) & 0xff, + BNXT_ULP_PORT_TABLE_TABLE_SCOPE & 0xff} + } + }, + { + .field_info_mask = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + } + }, + /* class_tid: 3, , table: l2_cntxt_tcam.vf2vf_ing */ + { + .field_info_mask = { + .description = "etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ivlan_tpid_sel", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ivlan_tpid_sel", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ovlan_tpid_sel", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ovlan_tpid_sel", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "addr1", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "addr1", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "addr0", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "addr0", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tunnel_id", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tunnel_id", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "out_tun_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "out_tun_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "llc", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "llc", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "roce", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + .field_info_spec = { + .description = "roce", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2ip_func", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2ip_func", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "metadata", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + (ULP_THOR2_SYM_VF_2_VFR_META_MASK >> 24) & 0xff, + (ULP_THOR2_SYM_VF_2_VFR_META_MASK >> 16) & 0xff, + (ULP_THOR2_SYM_VF_2_VFR_META_MASK >> 8) & 0xff, + ULP_THOR2_SYM_VF_2_VFR_META_MASK & 0xff} + }, + .field_info_spec = { + .description = "metadata", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + (ULP_THOR2_SYM_VF_2_VF_META_VAL >> 24) & 0xff, + (ULP_THOR2_SYM_VF_2_VF_META_VAL >> 16) & 0xff, + (ULP_THOR2_SYM_VF_2_VF_META_VAL >> 8) & 0xff, + ULP_THOR2_SYM_VF_2_VF_META_VAL & 0xff} + } + }, + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "parif", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "parif", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "spif", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "spif", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + } + }, + { + .field_info_mask = { + .description = "recycle_cnt", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "recycle_cnt", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "mpass_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "mpass_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "spare", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "spare", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + } + }, + /* class_tid: 3, , table: table_scope_cache.tsid_vfr_wr */ + { + .field_info_mask = { + .description = "tbl_scope", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tbl_scope", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_PORT_TABLE, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff, + (BNXT_ULP_PORT_TABLE_TABLE_SCOPE >> 8) & 0xff, + BNXT_ULP_PORT_TABLE_TABLE_SCOPE & 0xff} + } + }, + { + .field_info_mask = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + } + }, + /* class_tid: 3, , table: l2_cntxt_tcam_cache.no_vfr_egr_rd */ + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + } + }, + /* class_tid: 3, , table: l2_cntxt_tcam.no_vfr_svif_egr */ + { + .field_info_mask = { + .description = "etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ivlan_tpid_sel", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ivlan_tpid_sel", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ovlan_tpid_sel", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ovlan_tpid_sel", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "addr1", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "addr1", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "addr0", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "addr0", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tunnel_id", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tunnel_id", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "out_tun_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "out_tun_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "llc", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "llc", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "roce", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + .field_info_spec = { + .description = "roce", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2ip_func", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2ip_func", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "metadata", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "metadata", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + } + }, + { + .field_info_mask = { + .description = "parif", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "parif", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "spif", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "spif", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "recycle_cnt", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "recycle_cnt", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "mpass_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "mpass_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "spare", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "spare", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + } + }, + /* class_tid: 3, , table: profile_tcam_bypass.no_vfr_egr_catch_all */ + { + .field_info_mask = { + .description = "l4_hdr_dcn_present", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l4_hdr_dcn_present", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4_hdr_flags", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l4_hdr_flags", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4_hdr_subtype", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l4_hdr_subtype", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_protocol", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3_protocol", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_flags", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_flags", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_err", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_err", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "ot_hdr_flags", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "ot_hdr_flags", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "ot_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "ot_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "ot_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "ot_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "ot_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "ot_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl4_hdr_is_tcp_udp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl4_hdr_is_tcp_udp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "int_ifa_tail", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "int_ifa_tail", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "int_hdr_group", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "int_hdr_group", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "int_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "int_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "hrec_next", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "hrec_next", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "prof_func_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "prof_func_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_PROF_FUNC_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_PROF_FUNC_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2ip_func_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2ip_func_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "agg_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "agg_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "metadata", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "metadata", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "recycle_count", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "recycle_count", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "pkt_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "pkt_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "spare", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "spare", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + } + }, + { + .field_info_mask = { + .description = "padding", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "padding", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + /* class_tid: 3, , table: l2_cntxt_tcam_cache.no_vfr_egr_wr */ + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + } + }, + /* class_tid: 4, , table: table_scope_cache.tsid_vfr_egr_rd */ + { + .field_info_mask = { + .description = "tbl_scope", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tbl_scope", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_PORT_TABLE, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff, + (BNXT_ULP_PORT_TABLE_TABLE_SCOPE >> 8) & 0xff, + BNXT_ULP_PORT_TABLE_TABLE_SCOPE & 0xff} + } + }, + { + .field_info_mask = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + /* class_tid: 4, , table: profile_tcam_bypass.tsid_vfr_egr_catch_all */ + { + .field_info_mask = { + .description = "l4_hdr_dcn_present", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l4_hdr_dcn_present", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4_hdr_flags", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l4_hdr_flags", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4_hdr_subtype", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l4_hdr_subtype", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_protocol", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3_protocol", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_flags", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_flags", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_err", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_err", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "ot_hdr_flags", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "ot_hdr_flags", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "ot_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "ot_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "ot_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "ot_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "ot_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "ot_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl4_hdr_is_tcp_udp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl4_hdr_is_tcp_udp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl2_uc_mc_bc", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl2_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "otl2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "otl2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "int_ifa_tail", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "int_ifa_tail", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "int_hdr_group", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "int_hdr_group", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "int_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "int_hdr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "hrec_next", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "hrec_next", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "prof_func_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "prof_func_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_PROF_FUNC_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_PROF_FUNC_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2ip_func_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2ip_func_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "agg_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "agg_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "metadata", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "metadata", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "recycle_count", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "recycle_count", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "pkt_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "pkt_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "spare", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "spare", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + } + }, + { + .field_info_mask = { + .description = "padding", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "padding", + .field_bit_size = 72, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + /* class_tid: 4, , table: table_scope_cache.tsid_vfr_egr_wr */ + { + .field_info_mask = { + .description = "tbl_scope", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tbl_scope", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_PORT_TABLE, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff, + (BNXT_ULP_PORT_TABLE_TABLE_SCOPE >> 8) & 0xff, + BNXT_ULP_PORT_TABLE_TABLE_SCOPE & 0xff} + } + }, + { + .field_info_mask = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + /* class_tid: 4, , table: l2_cntxt_tcam_cache.endpoint_def_egr_rd */ + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff} + } + }, + /* class_tid: 4, , table: l2_cntxt_tcam.vf2vf_egr */ + { + .field_info_mask = { + .description = "etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ivlan_tpid_sel", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ivlan_tpid_sel", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ovlan_tpid_sel", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ovlan_tpid_sel", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "addr1", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "addr1", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "addr0", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "addr0", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tunnel_id", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tunnel_id", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR2_SYM_TUN_HDR_TYPE_NONE} + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR2_SYM_TUN_HDR_TYPE_NONE} + } + }, + { + .field_info_mask = { + .description = "out_tun_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR2_SYM_TUN_HDR_TYPE_NONE} + }, + .field_info_spec = { + .description = "out_tun_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR2_SYM_TUN_HDR_TYPE_NONE} + } + }, + { + .field_info_mask = { + .description = "llc", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "llc", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "roce", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + .field_info_spec = { + .description = "roce", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2ip_func", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2ip_func", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "metadata", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "metadata", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff} + } + }, + { + .field_info_mask = { + .description = "parif", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "parif", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "spif", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "spif", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "loopback", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "recycle_cnt", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "recycle_cnt", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "mpass_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "mpass_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "spare", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "spare", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + } + }, + /* class_tid: 4, , table: l2_cntxt_tcam_cache.endpoint_def_egr_wr */ + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff} + } + }, + /* class_tid: 4, , table: port_table.egr_wr_0 */ + { + .field_info_mask = { + .description = "dev.port_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "dev.port_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff} + } + } +}; + +struct bnxt_ulp_mapper_field_info ulp_thor2_class_key_ext_list[] = { + { + .description = "tl2_ivv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (51 >> 8) & 0xff, + 51 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_sip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (71 >> 8) & 0xff, + 71 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_dip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (86 >> 8) & 0xff, + 86 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ttl.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (92 >> 8) & 0xff, + 92 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_prot.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (98 >> 8) & 0xff, + 98 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_qos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (104 >> 8) & 0xff, + 104 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_src.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (110 >> 8) & 0xff, + 110 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_dst.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (116 >> 8) & 0xff, + 116 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tids.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (121 >> 8) & 0xff, + 121 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_dmac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (126 >> 8) & 0xff, + 126 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_smac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (132 >> 8) & 0xff, + 132 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ovv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (139 >> 8) & 0xff, + 139 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ivv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (147 >> 8) & 0xff, + 147 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (13 >> 8) & 0xff, + 13 & 0xff} + }, + { + .description = "l2_ivv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (151 >> 8) & 0xff, + 151 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (14 >> 8) & 0xff, + 14 & 0xff} + }, + { + .description = "l2_ivv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (155 >> 8) & 0xff, + 155 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_etype.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (163 >> 8) & 0xff, + 163 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip3.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (170 >> 8) & 0xff, + 170 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip2.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (176 >> 8) & 0xff, + 176 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip1.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (182 >> 8) & 0xff, + 182 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (188 >> 8) & 0xff, + 188 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (20 >> 8) & 0xff, + 20 & 0xff} + }, + { + .description = "l3_sip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (191 >> 8) & 0xff, + 191 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (21 >> 8) & 0xff, + 21 & 0xff} + }, + { + .description = "l3_sip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (194 >> 8) & 0xff, + 194 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_dip3.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (200 >> 8) & 0xff, + 200 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_dip2.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (206 >> 8) & 0xff, + 206 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_dip1.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (212 >> 8) & 0xff, + 212 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_dip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (218 >> 8) & 0xff, + 218 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (26 >> 8) & 0xff, + 26 & 0xff} + }, + { + .description = "l3_dip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (221 >> 8) & 0xff, + 221 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (27 >> 8) & 0xff, + 27 & 0xff} + }, + { + .description = "l3_dip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (224 >> 8) & 0xff, + 224 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ttl.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (230 >> 8) & 0xff, + 230 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (29 >> 8) & 0xff, + 29 & 0xff} + }, + { + .description = "l3_ttl.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (233 >> 8) & 0xff, + 233 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (30 >> 8) & 0xff, + 30 & 0xff} + }, + { + .description = "l3_ttl.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (236 >> 8) & 0xff, + 236 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_prot.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (242 >> 8) & 0xff, + 242 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (32 >> 8) & 0xff, + 32 & 0xff} + }, + { + .description = "l3_prot.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (245 >> 8) & 0xff, + 245 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (33 >> 8) & 0xff, + 33 & 0xff} + }, + { + .description = "l3_prot.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (248 >> 8) & 0xff, + 248 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_qos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (254 >> 8) & 0xff, + 254 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (35 >> 8) & 0xff, + 35 & 0xff} + }, + { + .description = "l3_qos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (257 >> 8) & 0xff, + 257 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (36 >> 8) & 0xff, + 36 & 0xff} + }, + { + .description = "l3_qos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (260 >> 8) & 0xff, + 260 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_src.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (266 >> 8) & 0xff, + 266 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (38 >> 8) & 0xff, + 38 & 0xff} + }, + { + .description = "l4_src.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (269 >> 8) & 0xff, + 269 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (39 >> 8) & 0xff, + 39 & 0xff} + }, + { + .description = "l4_src.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (272 >> 8) & 0xff, + 272 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_dst.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (278 >> 8) & 0xff, + 278 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (41 >> 8) & 0xff, + 41 & 0xff} + }, + { + .description = "l4_dst.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (281 >> 8) & 0xff, + 281 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (42 >> 8) & 0xff, + 42 & 0xff} + }, + { + .description = "l4_dst.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (284 >> 8) & 0xff, + 284 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (311 >> 8) & 0xff, + 311 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "tl2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (319 >> 8) & 0xff, + 319 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "tl3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (358 >> 8) & 0xff, + 358 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_TTL >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_TTL & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "tl3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (364 >> 8) & 0xff, + 364 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_TTL >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_TTL & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "tl3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (370 >> 8) & 0xff, + 370 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "tl3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (376 >> 8) & 0xff, + 376 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "tl3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (382 >> 8) & 0xff, + 382 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_QOS >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_QOS & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "tl3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (388 >> 8) & 0xff, + 388 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_QOS >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_QOS & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "tl4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (394 >> 8) & 0xff, + 394 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "tl4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (400 >> 8) & 0xff, + 400 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "tl4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (406 >> 8) & 0xff, + 406 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "tl4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (412 >> 8) & 0xff, + 412 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "tids", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (417 >> 8) & 0xff, + 417 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_T_VXLAN_GPE_VNI >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_T_VXLAN_GPE_VNI & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "tids", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (421 >> 8) & 0xff, + 421 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_T_VXLAN_GPE_VNI >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_T_VXLAN_GPE_VNI & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (426 >> 8) & 0xff, + 426 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (432 >> 8) & 0xff, + 432 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (438 >> 8) & 0xff, + 438 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (444 >> 8) & 0xff, + 444 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (451 >> 8) & 0xff, + 451 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (459 >> 8) & 0xff, + 459 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (467 >> 8) & 0xff, + 467 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_IO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_IO_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (64 >> 8) & 0xff, + 64 & 0xff} + }, + { + .description = "l2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (471 >> 8) & 0xff, + 471 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_OI_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OI_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (65 >> 8) & 0xff, + 65 & 0xff} + }, + { + .description = "l2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (475 >> 8) & 0xff, + 475 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (483 >> 8) & 0xff, + 483 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_IO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_IO_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (67 >> 8) & 0xff, + 67 & 0xff} + }, + { + .description = "l2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (487 >> 8) & 0xff, + 487 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_OI_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OI_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (68 >> 8) & 0xff, + 68 & 0xff} + }, + { + .description = "l2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (491 >> 8) & 0xff, + 491 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (499 >> 8) & 0xff, + 499 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_TYPE >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_TYPE & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (507 >> 8) & 0xff, + 507 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_TYPE >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_TYPE & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (514 >> 8) & 0xff, + 514 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (520 >> 8) & 0xff, + 520 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (526 >> 8) & 0xff, + 526 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (532 >> 8) & 0xff, + 532 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (538 >> 8) & 0xff, + 538 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (544 >> 8) & 0xff, + 544 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (550 >> 8) & 0xff, + 550 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (556 >> 8) & 0xff, + 556 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (562 >> 8) & 0xff, + 562 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_IPV4_TTL >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV4_TTL & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (80 >> 8) & 0xff, + 80 & 0xff} + }, + { + .description = "l3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (565 >> 8) & 0xff, + 565 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_TTL >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_TTL & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (81 >> 8) & 0xff, + 81 & 0xff} + }, + { + .description = "l3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (568 >> 8) & 0xff, + 568 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_TTL >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_TTL & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (574 >> 8) & 0xff, + 574 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_IPV4_TTL >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV4_TTL & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (83 >> 8) & 0xff, + 83 & 0xff} + }, + { + .description = "l3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (577 >> 8) & 0xff, + 577 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_TTL >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_TTL & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (84 >> 8) & 0xff, + 84 & 0xff} + }, + { + .description = "l3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (580 >> 8) & 0xff, + 580 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_TTL >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_TTL & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (586 >> 8) & 0xff, + 586 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_IPV4_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV4_PROTO_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (86 >> 8) & 0xff, + 86 & 0xff} + }, + { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (589 >> 8) & 0xff, + 589 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (87 >> 8) & 0xff, + 87 & 0xff} + }, + { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (592 >> 8) & 0xff, + 592 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (598 >> 8) & 0xff, + 598 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_IPV4_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV4_PROTO_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (89 >> 8) & 0xff, + 89 & 0xff} + }, + { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (601 >> 8) & 0xff, + 601 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (90 >> 8) & 0xff, + 90 & 0xff} + }, + { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (604 >> 8) & 0xff, + 604 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (610 >> 8) & 0xff, + 610 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_IPV4_QOS >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV4_QOS & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (92 >> 8) & 0xff, + 92 & 0xff} + }, + { + .description = "l3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (613 >> 8) & 0xff, + 613 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_QOS >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_QOS & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (93 >> 8) & 0xff, + 93 & 0xff} + }, + { + .description = "l3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (616 >> 8) & 0xff, + 616 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_QOS >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_QOS & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (622 >> 8) & 0xff, + 622 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_IPV4_QOS >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV4_QOS & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (95 >> 8) & 0xff, + 95 & 0xff} + }, + { + .description = "l3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (625 >> 8) & 0xff, + 625 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_QOS >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_QOS & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (96 >> 8) & 0xff, + 96 & 0xff} + }, + { + .description = "l3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (628 >> 8) & 0xff, + 628 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_QOS >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_QOS & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (634 >> 8) & 0xff, + 634 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_TCP_SRC_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (98 >> 8) & 0xff, + 98 & 0xff} + }, + { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (637 >> 8) & 0xff, + 637 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (99 >> 8) & 0xff, + 99 & 0xff} + }, + { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (640 >> 8) & 0xff, + 640 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (646 >> 8) & 0xff, + 646 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_TCP_SRC_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (101 >> 8) & 0xff, + 101 & 0xff} + }, + { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (649 >> 8) & 0xff, + 649 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (102 >> 8) & 0xff, + 102 & 0xff} + }, + { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (652 >> 8) & 0xff, + 652 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (658 >> 8) & 0xff, + 658 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_TCP_DST_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (104 >> 8) & 0xff, + 104 & 0xff} + }, + { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (661 >> 8) & 0xff, + 661 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (105 >> 8) & 0xff, + 105 & 0xff} + }, + { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (664 >> 8) & 0xff, + 664 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (670 >> 8) & 0xff, + 670 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_TCP_DST_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (107 >> 8) & 0xff, + 107 & 0xff} + }, + { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (673 >> 8) & 0xff, + 673 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (108 >> 8) & 0xff, + 108 & 0xff} + }, + { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (676 >> 8) & 0xff, + 676 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (681 >> 8) & 0xff, + 681 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (110 >> 8) & 0xff, + 110 & 0xff} + }, + { + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (683 >> 8) & 0xff, + 683 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (111 >> 8) & 0xff, + 111 & 0xff} + }, + { + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (685 >> 8) & 0xff, + 685 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (689 >> 8) & 0xff, + 689 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_L4_HDR_IS_UDP_TCP_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (113 >> 8) & 0xff, + 113 & 0xff} + }, + { + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (691 >> 8) & 0xff, + 691 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_L4_HDR_IS_UDP_TCP_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (114 >> 8) & 0xff, + 114 & 0xff} + }, + { + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (693 >> 8) & 0xff, + 693 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_L4_HDR_IS_UDP_TCP_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (697 >> 8) & 0xff, + 697 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (116 >> 8) & 0xff, + 116 & 0xff} + }, + { + .description = "l4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (699 >> 8) & 0xff, + 699 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (117 >> 8) & 0xff, + 117 & 0xff} + }, + { + .description = "l4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (701 >> 8) & 0xff, + 701 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (705 >> 8) & 0xff, + 705 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (119 >> 8) & 0xff, + 119 & 0xff} + }, + { + .description = "l4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (707 >> 8) & 0xff, + 707 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_L4_HDR_TYPE_UDP}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (120 >> 8) & 0xff, + 120 & 0xff} + }, + { + .description = "l4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (709 >> 8) & 0xff, + 709 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_L4_HDR_TYPE_UDP}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (713 >> 8) & 0xff, + 713 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (122 >> 8) & 0xff, + 122 & 0xff} + }, + { + .description = "l4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (715 >> 8) & 0xff, + 715 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (123 >> 8) & 0xff, + 123 & 0xff} + }, + { + .description = "l4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (717 >> 8) & 0xff, + 717 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (721 >> 8) & 0xff, + 721 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (125 >> 8) & 0xff, + 125 & 0xff} + }, + { + .description = "l4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (723 >> 8) & 0xff, + 723 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (126 >> 8) & 0xff, + 126 & 0xff} + }, + { + .description = "l4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (725 >> 8) & 0xff, + 725 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (729 >> 8) & 0xff, + 729 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (128 >> 8) & 0xff, + 128 & 0xff} + }, + { + .description = "l4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (731 >> 8) & 0xff, + 731 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (129 >> 8) & 0xff, + 129 & 0xff} + }, + { + .description = "l4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (733 >> 8) & 0xff, + 733 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (737 >> 8) & 0xff, + 737 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_L4_HDR_VALID_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (131 >> 8) & 0xff, + 131 & 0xff} + }, + { + .description = "l4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (739 >> 8) & 0xff, + 739 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_L4_HDR_VALID_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (132 >> 8) & 0xff, + 132 & 0xff} + }, + { + .description = "l4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (741 >> 8) & 0xff, + 741 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_L4_HDR_VALID_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (745 >> 8) & 0xff, + 745 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_L3_HDR_ISIP_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (134 >> 8) & 0xff, + 134 & 0xff} + }, + { + .description = "l3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (747 >> 8) & 0xff, + 747 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_L3_HDR_ISIP_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (135 >> 8) & 0xff, + 135 & 0xff} + }, + { + .description = "l3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (749 >> 8) & 0xff, + 749 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_L3_HDR_ISIP_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (753 >> 8) & 0xff, + 753 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (137 >> 8) & 0xff, + 137 & 0xff} + }, + { + .description = "l3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (755 >> 8) & 0xff, + 755 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (138 >> 8) & 0xff, + 138 & 0xff} + }, + { + .description = "l3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (757 >> 8) & 0xff, + 757 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (761 >> 8) & 0xff, + 761 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_L3_HDR_TYPE_IPV6}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (140 >> 8) & 0xff, + 140 & 0xff} + }, + { + .description = "l3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (763 >> 8) & 0xff, + 763 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (141 >> 8) & 0xff, + 141 & 0xff} + }, + { + .description = "l3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (765 >> 8) & 0xff, + 765 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (769 >> 8) & 0xff, + 769 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (143 >> 8) & 0xff, + 143 & 0xff} + }, + { + .description = "l3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (771 >> 8) & 0xff, + 771 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (144 >> 8) & 0xff, + 144 & 0xff} + }, + { + .description = "l3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (773 >> 8) & 0xff, + 773 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (777 >> 8) & 0xff, + 777 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (146 >> 8) & 0xff, + 146 & 0xff} + }, + { + .description = "l3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (779 >> 8) & 0xff, + 779 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (147 >> 8) & 0xff, + 147 & 0xff} + }, + { + .description = "l3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (781 >> 8) & 0xff, + 781 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (785 >> 8) & 0xff, + 785 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (149 >> 8) & 0xff, + 149 & 0xff} + }, + { + .description = "l3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (787 >> 8) & 0xff, + 787 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (150 >> 8) & 0xff, + 150 & 0xff} + }, + { + .description = "l3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (789 >> 8) & 0xff, + 789 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (793 >> 8) & 0xff, + 793 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_L3_HDR_VALID_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (152 >> 8) & 0xff, + 152 & 0xff} + }, + { + .description = "l3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (795 >> 8) & 0xff, + 795 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_L3_HDR_VALID_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (153 >> 8) & 0xff, + 153 & 0xff} + }, + { + .description = "l3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (797 >> 8) & 0xff, + 797 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_L3_HDR_VALID_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (802 >> 8) & 0xff, + 802 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (808 >> 8) & 0xff, + 808 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_L2_TWO_VTAGS_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_CONST + }, + { + .description = "l2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (814 >> 8) & 0xff, + 814 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (820 >> 8) & 0xff, + 820 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_L2_VTAG_PRESENT_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_CONST + }, + { + .description = "l2_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (827 >> 8) & 0xff, + 827 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (831 >> 8) & 0xff, + 831 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (835 >> 8) & 0xff, + 835 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_L2_HDR_VALID_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tun_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (839 >> 8) & 0xff, + 839 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (162 >> 8) & 0xff, + 162 & 0xff} + }, + { + .description = "tun_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (841 >> 8) & 0xff, + 841 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (163 >> 8) & 0xff, + 163 & 0xff} + }, + { + .description = "tun_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (843 >> 8) & 0xff, + 843 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (164 >> 8) & 0xff, + 164 & 0xff} + }, + { + .description = "tun_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (845 >> 8) & 0xff, + 845 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (165 >> 8) & 0xff, + 165 & 0xff} + }, + { + .description = "tun_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (847 >> 8) & 0xff, + 847 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tun_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (851 >> 8) & 0xff, + 851 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_TUN_HDR_TYPE_VXLAN_GPE}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (167 >> 8) & 0xff, + 167 & 0xff} + }, + { + .description = "tun_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (853 >> 8) & 0xff, + 853 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_TUN_HDR_TYPE_GENEVE}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (168 >> 8) & 0xff, + 168 & 0xff} + }, + { + .description = "tun_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (855 >> 8) & 0xff, + 855 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_TUN_HDR_TYPE_GRE}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (169 >> 8) & 0xff, + 169 & 0xff} + }, + { + .description = "tun_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (857 >> 8) & 0xff, + 857 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_TUN_HDR_TYPE_UPAR1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (170 >> 8) & 0xff, + 170 & 0xff} + }, + { + .description = "tun_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (859 >> 8) & 0xff, + 859 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_TUN_HDR_TYPE_UPAR2}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (866 >> 8) & 0xff, + 866 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (870 >> 8) & 0xff, + 870 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_TL4_HDR_IS_UDP_TCP_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (874 >> 8) & 0xff, + 874 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (878 >> 8) & 0xff, + 878 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_TL4_HDR_TYPE_UDP}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (882 >> 8) & 0xff, + 882 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (886 >> 8) & 0xff, + 886 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (890 >> 8) & 0xff, + 890 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (894 >> 8) & 0xff, + 894 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_TL4_HDR_VALID_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (898 >> 8) & 0xff, + 898 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (902 >> 8) & 0xff, + 902 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_TL3_HDR_ISIP_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (906 >> 8) & 0xff, + 906 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (910 >> 8) & 0xff, + 910 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (914 >> 8) & 0xff, + 914 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (918 >> 8) & 0xff, + 918 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (922 >> 8) & 0xff, + 922 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_TL3_HDR_VALID_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ivv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (961 >> 8) & 0xff, + 961 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_sip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (981 >> 8) & 0xff, + 981 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_dip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (996 >> 8) & 0xff, + 996 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ttl.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1002 >> 8) & 0xff, + 1002 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_prot.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1008 >> 8) & 0xff, + 1008 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_qos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1014 >> 8) & 0xff, + 1014 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_src.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1020 >> 8) & 0xff, + 1020 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_dst.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1026 >> 8) & 0xff, + 1026 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tids.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1031 >> 8) & 0xff, + 1031 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_dmac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1037 >> 8) & 0xff, + 1037 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_smac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1044 >> 8) & 0xff, + 1044 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ovv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1051 >> 8) & 0xff, + 1051 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ivv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1059 >> 8) & 0xff, + 1059 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (199 >> 8) & 0xff, + 199 & 0xff} + }, + { + .description = "l2_ivv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1063 >> 8) & 0xff, + 1063 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (200 >> 8) & 0xff, + 200 & 0xff} + }, + { + .description = "l2_ivv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1067 >> 8) & 0xff, + 1067 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_etype.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1075 >> 8) & 0xff, + 1075 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip3.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1082 >> 8) & 0xff, + 1082 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip2.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1088 >> 8) & 0xff, + 1088 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip1.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1094 >> 8) & 0xff, + 1094 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1100 >> 8) & 0xff, + 1100 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (206 >> 8) & 0xff, + 206 & 0xff} + }, + { + .description = "l3_sip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1103 >> 8) & 0xff, + 1103 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (207 >> 8) & 0xff, + 207 & 0xff} + }, + { + .description = "l3_sip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1106 >> 8) & 0xff, + 1106 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_dip3.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1112 >> 8) & 0xff, + 1112 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_dip2.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1118 >> 8) & 0xff, + 1118 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_dip1.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1124 >> 8) & 0xff, + 1124 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_dip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1130 >> 8) & 0xff, + 1130 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (212 >> 8) & 0xff, + 212 & 0xff} + }, + { + .description = "l3_dip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1133 >> 8) & 0xff, + 1133 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (213 >> 8) & 0xff, + 213 & 0xff} + }, + { + .description = "l3_dip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1136 >> 8) & 0xff, + 1136 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ttl.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1142 >> 8) & 0xff, + 1142 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (215 >> 8) & 0xff, + 215 & 0xff} + }, + { + .description = "l3_ttl.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1145 >> 8) & 0xff, + 1145 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (216 >> 8) & 0xff, + 216 & 0xff} + }, + { + .description = "l3_ttl.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1148 >> 8) & 0xff, + 1148 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_prot.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1154 >> 8) & 0xff, + 1154 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (218 >> 8) & 0xff, + 218 & 0xff} + }, + { + .description = "l3_prot.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1157 >> 8) & 0xff, + 1157 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (219 >> 8) & 0xff, + 219 & 0xff} + }, + { + .description = "l3_prot.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1160 >> 8) & 0xff, + 1160 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_qos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1166 >> 8) & 0xff, + 1166 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (221 >> 8) & 0xff, + 221 & 0xff} + }, + { + .description = "l3_qos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1169 >> 8) & 0xff, + 1169 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (222 >> 8) & 0xff, + 222 & 0xff} + }, + { + .description = "l3_qos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1172 >> 8) & 0xff, + 1172 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_src.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1178 >> 8) & 0xff, + 1178 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (224 >> 8) & 0xff, + 224 & 0xff} + }, + { + .description = "l4_src.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1181 >> 8) & 0xff, + 1181 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (225 >> 8) & 0xff, + 225 & 0xff} + }, + { + .description = "l4_src.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1184 >> 8) & 0xff, + 1184 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_dst.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1190 >> 8) & 0xff, + 1190 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (227 >> 8) & 0xff, + 227 & 0xff} + }, + { + .description = "l4_dst.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1193 >> 8) & 0xff, + 1193 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (228 >> 8) & 0xff, + 228 & 0xff} + }, + { + .description = "l4_dst.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1196 >> 8) & 0xff, + 1196 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1231 >> 8) & 0xff, + 1231 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "tl2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1239 >> 8) & 0xff, + 1239 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "tl3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1278 >> 8) & 0xff, + 1278 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "tl3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1284 >> 8) & 0xff, + 1284 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_TTL >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_TTL & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "tl3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1290 >> 8) & 0xff, + 1290 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "tl3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1296 >> 8) & 0xff, + 1296 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "tl3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1302 >> 8) & 0xff, + 1302 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "tl3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1308 >> 8) & 0xff, + 1308 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_QOS >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_QOS & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "tl4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1314 >> 8) & 0xff, + 1314 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "tl4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1320 >> 8) & 0xff, + 1320 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "tl4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1326 >> 8) & 0xff, + 1326 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "tl4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1332 >> 8) & 0xff, + 1332 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "tids", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1337 >> 8) & 0xff, + 1337 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "tids", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1341 >> 8) & 0xff, + 1341 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_T_VXLAN_GPE_VNI >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_T_VXLAN_GPE_VNI & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1347 >> 8) & 0xff, + 1347 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1355 >> 8) & 0xff, + 1355 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1362 >> 8) & 0xff, + 1362 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1368 >> 8) & 0xff, + 1368 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1375 >> 8) & 0xff, + 1375 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1383 >> 8) & 0xff, + 1383 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1391 >> 8) & 0xff, + 1391 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (250 >> 8) & 0xff, + 250 & 0xff} + }, + { + .description = "l2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1395 >> 8) & 0xff, + 1395 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (251 >> 8) & 0xff, + 251 & 0xff} + }, + { + .description = "l2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1399 >> 8) & 0xff, + 1399 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1407 >> 8) & 0xff, + 1407 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_IO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_IO_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (253 >> 8) & 0xff, + 253 & 0xff} + }, + { + .description = "l2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1411 >> 8) & 0xff, + 1411 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_OI_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OI_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (254 >> 8) & 0xff, + 254 & 0xff} + }, + { + .description = "l2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1415 >> 8) & 0xff, + 1415 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1423 >> 8) & 0xff, + 1423 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1431 >> 8) & 0xff, + 1431 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_TYPE >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_TYPE & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1438 >> 8) & 0xff, + 1438 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1444 >> 8) & 0xff, + 1444 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1450 >> 8) & 0xff, + 1450 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1456 >> 8) & 0xff, + 1456 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1462 >> 8) & 0xff, + 1462 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1468 >> 8) & 0xff, + 1468 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1474 >> 8) & 0xff, + 1474 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1480 >> 8) & 0xff, + 1480 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1486 >> 8) & 0xff, + 1486 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (266 >> 8) & 0xff, + 266 & 0xff} + }, + { + .description = "l3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1489 >> 8) & 0xff, + 1489 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (267 >> 8) & 0xff, + 267 & 0xff} + }, + { + .description = "l3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1492 >> 8) & 0xff, + 1492 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1498 >> 8) & 0xff, + 1498 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_IPV4_TTL >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV4_TTL & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (269 >> 8) & 0xff, + 269 & 0xff} + }, + { + .description = "l3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1501 >> 8) & 0xff, + 1501 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_TTL >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_TTL & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (270 >> 8) & 0xff, + 270 & 0xff} + }, + { + .description = "l3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1504 >> 8) & 0xff, + 1504 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_TTL >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_TTL & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1510 >> 8) & 0xff, + 1510 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (272 >> 8) & 0xff, + 272 & 0xff} + }, + { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1513 >> 8) & 0xff, + 1513 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (273 >> 8) & 0xff, + 273 & 0xff} + }, + { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1516 >> 8) & 0xff, + 1516 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1522 >> 8) & 0xff, + 1522 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_IPV4_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV4_PROTO_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (275 >> 8) & 0xff, + 275 & 0xff} + }, + { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1525 >> 8) & 0xff, + 1525 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (276 >> 8) & 0xff, + 276 & 0xff} + }, + { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1528 >> 8) & 0xff, + 1528 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1534 >> 8) & 0xff, + 1534 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (278 >> 8) & 0xff, + 278 & 0xff} + }, + { + .description = "l3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1537 >> 8) & 0xff, + 1537 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (279 >> 8) & 0xff, + 279 & 0xff} + }, + { + .description = "l3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1540 >> 8) & 0xff, + 1540 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1546 >> 8) & 0xff, + 1546 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_IPV4_QOS >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV4_QOS & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (281 >> 8) & 0xff, + 281 & 0xff} + }, + { + .description = "l3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1549 >> 8) & 0xff, + 1549 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_QOS >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_QOS & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (282 >> 8) & 0xff, + 282 & 0xff} + }, + { + .description = "l3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1552 >> 8) & 0xff, + 1552 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_QOS >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_QOS & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1558 >> 8) & 0xff, + 1558 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (284 >> 8) & 0xff, + 284 & 0xff} + }, + { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1561 >> 8) & 0xff, + 1561 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (285 >> 8) & 0xff, + 285 & 0xff} + }, + { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1564 >> 8) & 0xff, + 1564 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1570 >> 8) & 0xff, + 1570 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_TCP_SRC_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (287 >> 8) & 0xff, + 287 & 0xff} + }, + { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1573 >> 8) & 0xff, + 1573 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (288 >> 8) & 0xff, + 288 & 0xff} + }, + { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1576 >> 8) & 0xff, + 1576 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1582 >> 8) & 0xff, + 1582 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (290 >> 8) & 0xff, + 290 & 0xff} + }, + { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1585 >> 8) & 0xff, + 1585 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (291 >> 8) & 0xff, + 291 & 0xff} + }, + { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1588 >> 8) & 0xff, + 1588 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1594 >> 8) & 0xff, + 1594 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_TCP_DST_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (293 >> 8) & 0xff, + 293 & 0xff} + }, + { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1597 >> 8) & 0xff, + 1597 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (294 >> 8) & 0xff, + 294 & 0xff} + }, + { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1600 >> 8) & 0xff, + 1600 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "tl2_ivv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1626 >> 8) & 0xff, + 1626 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_sip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1646 >> 8) & 0xff, + 1646 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_dip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1661 >> 8) & 0xff, + 1661 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ttl.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1667 >> 8) & 0xff, + 1667 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_prot.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1673 >> 8) & 0xff, + 1673 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_qos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1679 >> 8) & 0xff, + 1679 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_src.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1685 >> 8) & 0xff, + 1685 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_dst.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1691 >> 8) & 0xff, + 1691 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tids.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1696 >> 8) & 0xff, + 1696 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_dmac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1701 >> 8) & 0xff, + 1701 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_smac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1707 >> 8) & 0xff, + 1707 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ovv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1714 >> 8) & 0xff, + 1714 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ivv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1722 >> 8) & 0xff, + 1722 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (308 >> 8) & 0xff, + 308 & 0xff} + }, + { + .description = "l2_ivv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1726 >> 8) & 0xff, + 1726 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (309 >> 8) & 0xff, + 309 & 0xff} + }, + { + .description = "l2_ivv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1730 >> 8) & 0xff, + 1730 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_etype.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1738 >> 8) & 0xff, + 1738 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip3.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1745 >> 8) & 0xff, + 1745 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip2.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1751 >> 8) & 0xff, + 1751 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip1.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1757 >> 8) & 0xff, + 1757 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1763 >> 8) & 0xff, + 1763 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (315 >> 8) & 0xff, + 315 & 0xff} + }, + { + .description = "l3_sip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1766 >> 8) & 0xff, + 1766 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (316 >> 8) & 0xff, + 316 & 0xff} + }, + { + .description = "l3_sip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1769 >> 8) & 0xff, + 1769 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_dip3.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1775 >> 8) & 0xff, + 1775 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_dip2.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1781 >> 8) & 0xff, + 1781 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_dip1.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1787 >> 8) & 0xff, + 1787 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_dip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1793 >> 8) & 0xff, + 1793 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (321 >> 8) & 0xff, + 321 & 0xff} + }, + { + .description = "l3_dip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1796 >> 8) & 0xff, + 1796 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (322 >> 8) & 0xff, + 322 & 0xff} + }, + { + .description = "l3_dip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1799 >> 8) & 0xff, + 1799 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ttl.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1805 >> 8) & 0xff, + 1805 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (324 >> 8) & 0xff, + 324 & 0xff} + }, + { + .description = "l3_ttl.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1808 >> 8) & 0xff, + 1808 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (325 >> 8) & 0xff, + 325 & 0xff} + }, + { + .description = "l3_ttl.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1811 >> 8) & 0xff, + 1811 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_prot.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1817 >> 8) & 0xff, + 1817 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (327 >> 8) & 0xff, + 327 & 0xff} + }, + { + .description = "l3_prot.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1820 >> 8) & 0xff, + 1820 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (328 >> 8) & 0xff, + 328 & 0xff} + }, + { + .description = "l3_prot.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1823 >> 8) & 0xff, + 1823 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_qos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1829 >> 8) & 0xff, + 1829 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (330 >> 8) & 0xff, + 330 & 0xff} + }, + { + .description = "l3_qos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1832 >> 8) & 0xff, + 1832 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (331 >> 8) & 0xff, + 331 & 0xff} + }, + { + .description = "l3_qos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1835 >> 8) & 0xff, + 1835 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_src.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1841 >> 8) & 0xff, + 1841 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (333 >> 8) & 0xff, + 333 & 0xff} + }, + { + .description = "l4_src.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1844 >> 8) & 0xff, + 1844 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (334 >> 8) & 0xff, + 334 & 0xff} + }, + { + .description = "l4_src.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1847 >> 8) & 0xff, + 1847 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_dst.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1853 >> 8) & 0xff, + 1853 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (336 >> 8) & 0xff, + 336 & 0xff} + }, + { + .description = "l4_dst.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1856 >> 8) & 0xff, + 1856 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (337 >> 8) & 0xff, + 337 & 0xff} + }, + { + .description = "l4_dst.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1859 >> 8) & 0xff, + 1859 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1886 >> 8) & 0xff, + 1886 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "tl2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1894 >> 8) & 0xff, + 1894 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "tl3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1933 >> 8) & 0xff, + 1933 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_TTL >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_TTL & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "tl3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1939 >> 8) & 0xff, + 1939 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_TTL >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_TTL & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "tl3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1945 >> 8) & 0xff, + 1945 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "tl3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1951 >> 8) & 0xff, + 1951 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "tl3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1957 >> 8) & 0xff, + 1957 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_QOS >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_QOS & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "tl3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1963 >> 8) & 0xff, + 1963 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_QOS >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_QOS & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "tl4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1969 >> 8) & 0xff, + 1969 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "tl4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1975 >> 8) & 0xff, + 1975 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "tl4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1981 >> 8) & 0xff, + 1981 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "tl4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1987 >> 8) & 0xff, + 1987 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "tids", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1992 >> 8) & 0xff, + 1992 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_T_VXLAN_GPE_VNI >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_T_VXLAN_GPE_VNI & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "tids", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1996 >> 8) & 0xff, + 1996 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_T_VXLAN_GPE_VNI >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_T_VXLAN_GPE_VNI & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2001 >> 8) & 0xff, + 2001 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2007 >> 8) & 0xff, + 2007 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2013 >> 8) & 0xff, + 2013 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2019 >> 8) & 0xff, + 2019 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2026 >> 8) & 0xff, + 2026 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2034 >> 8) & 0xff, + 2034 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2042 >> 8) & 0xff, + 2042 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_IO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_IO_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (359 >> 8) & 0xff, + 359 & 0xff} + }, + { + .description = "l2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2046 >> 8) & 0xff, + 2046 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_OI_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OI_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (360 >> 8) & 0xff, + 360 & 0xff} + }, + { + .description = "l2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2050 >> 8) & 0xff, + 2050 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2058 >> 8) & 0xff, + 2058 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_IO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_IO_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (362 >> 8) & 0xff, + 362 & 0xff} + }, + { + .description = "l2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2062 >> 8) & 0xff, + 2062 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_OI_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OI_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (363 >> 8) & 0xff, + 363 & 0xff} + }, + { + .description = "l2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2066 >> 8) & 0xff, + 2066 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2074 >> 8) & 0xff, + 2074 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_TYPE >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_TYPE & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2082 >> 8) & 0xff, + 2082 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_TYPE >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_TYPE & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2089 >> 8) & 0xff, + 2089 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2095 >> 8) & 0xff, + 2095 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2101 >> 8) & 0xff, + 2101 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2107 >> 8) & 0xff, + 2107 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2113 >> 8) & 0xff, + 2113 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2119 >> 8) & 0xff, + 2119 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2125 >> 8) & 0xff, + 2125 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2131 >> 8) & 0xff, + 2131 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2137 >> 8) & 0xff, + 2137 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_IPV4_TTL >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV4_TTL & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (375 >> 8) & 0xff, + 375 & 0xff} + }, + { + .description = "l3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2140 >> 8) & 0xff, + 2140 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_TTL >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_TTL & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (376 >> 8) & 0xff, + 376 & 0xff} + }, + { + .description = "l3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2143 >> 8) & 0xff, + 2143 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_TTL >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_TTL & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2149 >> 8) & 0xff, + 2149 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_IPV4_TTL >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV4_TTL & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (378 >> 8) & 0xff, + 378 & 0xff} + }, + { + .description = "l3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2152 >> 8) & 0xff, + 2152 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_TTL >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_TTL & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (379 >> 8) & 0xff, + 379 & 0xff} + }, + { + .description = "l3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2155 >> 8) & 0xff, + 2155 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_TTL >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_TTL & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2161 >> 8) & 0xff, + 2161 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_IPV4_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV4_PROTO_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (381 >> 8) & 0xff, + 381 & 0xff} + }, + { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2164 >> 8) & 0xff, + 2164 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (382 >> 8) & 0xff, + 382 & 0xff} + }, + { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2167 >> 8) & 0xff, + 2167 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2173 >> 8) & 0xff, + 2173 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_IPV4_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV4_PROTO_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (384 >> 8) & 0xff, + 384 & 0xff} + }, + { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2176 >> 8) & 0xff, + 2176 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (385 >> 8) & 0xff, + 385 & 0xff} + }, + { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2179 >> 8) & 0xff, + 2179 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2185 >> 8) & 0xff, + 2185 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_IPV4_QOS >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV4_QOS & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (387 >> 8) & 0xff, + 387 & 0xff} + }, + { + .description = "l3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2188 >> 8) & 0xff, + 2188 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_QOS >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_QOS & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (388 >> 8) & 0xff, + 388 & 0xff} + }, + { + .description = "l3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2191 >> 8) & 0xff, + 2191 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_QOS >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_QOS & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2197 >> 8) & 0xff, + 2197 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_IPV4_QOS >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV4_QOS & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (390 >> 8) & 0xff, + 390 & 0xff} + }, + { + .description = "l3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2200 >> 8) & 0xff, + 2200 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_QOS >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_QOS & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (391 >> 8) & 0xff, + 391 & 0xff} + }, + { + .description = "l3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2203 >> 8) & 0xff, + 2203 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_QOS >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_QOS & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2209 >> 8) & 0xff, + 2209 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_TCP_SRC_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (393 >> 8) & 0xff, + 393 & 0xff} + }, + { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2212 >> 8) & 0xff, + 2212 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (394 >> 8) & 0xff, + 394 & 0xff} + }, + { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2215 >> 8) & 0xff, + 2215 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2221 >> 8) & 0xff, + 2221 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_TCP_SRC_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (396 >> 8) & 0xff, + 396 & 0xff} + }, + { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2224 >> 8) & 0xff, + 2224 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (397 >> 8) & 0xff, + 397 & 0xff} + }, + { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2227 >> 8) & 0xff, + 2227 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2233 >> 8) & 0xff, + 2233 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_TCP_DST_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (399 >> 8) & 0xff, + 399 & 0xff} + }, + { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2236 >> 8) & 0xff, + 2236 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (400 >> 8) & 0xff, + 400 & 0xff} + }, + { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2239 >> 8) & 0xff, + 2239 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2245 >> 8) & 0xff, + 2245 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_TCP_DST_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (402 >> 8) & 0xff, + 402 & 0xff} + }, + { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2248 >> 8) & 0xff, + 2248 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (403 >> 8) & 0xff, + 403 & 0xff} + }, + { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2251 >> 8) & 0xff, + 2251 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2256 >> 8) & 0xff, + 2256 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (405 >> 8) & 0xff, + 405 & 0xff} + }, + { + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2258 >> 8) & 0xff, + 2258 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (406 >> 8) & 0xff, + 406 & 0xff} + }, + { + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2260 >> 8) & 0xff, + 2260 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2264 >> 8) & 0xff, + 2264 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_L4_HDR_IS_UDP_TCP_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (408 >> 8) & 0xff, + 408 & 0xff} + }, + { + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2266 >> 8) & 0xff, + 2266 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_L4_HDR_IS_UDP_TCP_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (409 >> 8) & 0xff, + 409 & 0xff} + }, + { + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2268 >> 8) & 0xff, + 2268 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_L4_HDR_IS_UDP_TCP_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2272 >> 8) & 0xff, + 2272 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (411 >> 8) & 0xff, + 411 & 0xff} + }, + { + .description = "l4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2274 >> 8) & 0xff, + 2274 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (412 >> 8) & 0xff, + 412 & 0xff} + }, + { + .description = "l4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2276 >> 8) & 0xff, + 2276 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2280 >> 8) & 0xff, + 2280 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (414 >> 8) & 0xff, + 414 & 0xff} + }, + { + .description = "l4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2282 >> 8) & 0xff, + 2282 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_L4_HDR_TYPE_UDP}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (415 >> 8) & 0xff, + 415 & 0xff} + }, + { + .description = "l4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2284 >> 8) & 0xff, + 2284 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_L4_HDR_TYPE_UDP}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2288 >> 8) & 0xff, + 2288 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (417 >> 8) & 0xff, + 417 & 0xff} + }, + { + .description = "l4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2290 >> 8) & 0xff, + 2290 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (418 >> 8) & 0xff, + 418 & 0xff} + }, + { + .description = "l4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2292 >> 8) & 0xff, + 2292 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2296 >> 8) & 0xff, + 2296 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (420 >> 8) & 0xff, + 420 & 0xff} + }, + { + .description = "l4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2298 >> 8) & 0xff, + 2298 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (421 >> 8) & 0xff, + 421 & 0xff} + }, + { + .description = "l4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2300 >> 8) & 0xff, + 2300 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2304 >> 8) & 0xff, + 2304 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (423 >> 8) & 0xff, + 423 & 0xff} + }, + { + .description = "l4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2306 >> 8) & 0xff, + 2306 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (424 >> 8) & 0xff, + 424 & 0xff} + }, + { + .description = "l4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2308 >> 8) & 0xff, + 2308 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2312 >> 8) & 0xff, + 2312 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_L4_HDR_VALID_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (426 >> 8) & 0xff, + 426 & 0xff} + }, + { + .description = "l4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2314 >> 8) & 0xff, + 2314 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_L4_HDR_VALID_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (427 >> 8) & 0xff, + 427 & 0xff} + }, + { + .description = "l4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2316 >> 8) & 0xff, + 2316 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_L4_HDR_VALID_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2320 >> 8) & 0xff, + 2320 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_L3_HDR_ISIP_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (429 >> 8) & 0xff, + 429 & 0xff} + }, + { + .description = "l3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2322 >> 8) & 0xff, + 2322 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_L3_HDR_ISIP_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (430 >> 8) & 0xff, + 430 & 0xff} + }, + { + .description = "l3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2324 >> 8) & 0xff, + 2324 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_L3_HDR_ISIP_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2328 >> 8) & 0xff, + 2328 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (432 >> 8) & 0xff, + 432 & 0xff} + }, + { + .description = "l3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2330 >> 8) & 0xff, + 2330 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (433 >> 8) & 0xff, + 433 & 0xff} + }, + { + .description = "l3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2332 >> 8) & 0xff, + 2332 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2336 >> 8) & 0xff, + 2336 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_L3_HDR_TYPE_IPV6}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (435 >> 8) & 0xff, + 435 & 0xff} + }, + { + .description = "l3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2338 >> 8) & 0xff, + 2338 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (436 >> 8) & 0xff, + 436 & 0xff} + }, + { + .description = "l3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2340 >> 8) & 0xff, + 2340 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2344 >> 8) & 0xff, + 2344 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (438 >> 8) & 0xff, + 438 & 0xff} + }, + { + .description = "l3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2346 >> 8) & 0xff, + 2346 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (439 >> 8) & 0xff, + 439 & 0xff} + }, + { + .description = "l3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2348 >> 8) & 0xff, + 2348 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2352 >> 8) & 0xff, + 2352 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (441 >> 8) & 0xff, + 441 & 0xff} + }, + { + .description = "l3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2354 >> 8) & 0xff, + 2354 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (442 >> 8) & 0xff, + 442 & 0xff} + }, + { + .description = "l3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2356 >> 8) & 0xff, + 2356 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2360 >> 8) & 0xff, + 2360 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (444 >> 8) & 0xff, + 444 & 0xff} + }, + { + .description = "l3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2362 >> 8) & 0xff, + 2362 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (445 >> 8) & 0xff, + 445 & 0xff} + }, + { + .description = "l3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2364 >> 8) & 0xff, + 2364 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2368 >> 8) & 0xff, + 2368 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_L3_HDR_VALID_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (447 >> 8) & 0xff, + 447 & 0xff} + }, + { + .description = "l3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2370 >> 8) & 0xff, + 2370 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_L3_HDR_VALID_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (448 >> 8) & 0xff, + 448 & 0xff} + }, + { + .description = "l3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2372 >> 8) & 0xff, + 2372 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_L3_HDR_VALID_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2377 >> 8) & 0xff, + 2377 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_two_vtags", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2383 >> 8) & 0xff, + 2383 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_L2_TWO_VTAGS_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_CONST + }, + { + .description = "l2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2389 >> 8) & 0xff, + 2389 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_vtag_present", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2395 >> 8) & 0xff, + 2395 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_L2_VTAG_PRESENT_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_CONST + }, + { + .description = "l2_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2402 >> 8) & 0xff, + 2402 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2406 >> 8) & 0xff, + 2406 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2410 >> 8) & 0xff, + 2410 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_L2_HDR_VALID_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tun_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2414 >> 8) & 0xff, + 2414 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (457 >> 8) & 0xff, + 457 & 0xff} + }, + { + .description = "tun_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2416 >> 8) & 0xff, + 2416 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (458 >> 8) & 0xff, + 458 & 0xff} + }, + { + .description = "tun_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2418 >> 8) & 0xff, + 2418 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (459 >> 8) & 0xff, + 459 & 0xff} + }, + { + .description = "tun_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2420 >> 8) & 0xff, + 2420 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (460 >> 8) & 0xff, + 460 & 0xff} + }, + { + .description = "tun_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2422 >> 8) & 0xff, + 2422 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tun_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2426 >> 8) & 0xff, + 2426 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_TUN_HDR_TYPE_VXLAN_GPE}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (462 >> 8) & 0xff, + 462 & 0xff} + }, + { + .description = "tun_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2428 >> 8) & 0xff, + 2428 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_TUN_HDR_TYPE_GENEVE}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (463 >> 8) & 0xff, + 463 & 0xff} + }, + { + .description = "tun_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2430 >> 8) & 0xff, + 2430 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_TUN_HDR_TYPE_GRE}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (464 >> 8) & 0xff, + 464 & 0xff} + }, + { + .description = "tun_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2432 >> 8) & 0xff, + 2432 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_TUN_HDR_TYPE_UPAR1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (465 >> 8) & 0xff, + 465 & 0xff} + }, + { + .description = "tun_hdr_type", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2434 >> 8) & 0xff, + 2434 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_TUN_HDR_TYPE_UPAR2}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2441 >> 8) & 0xff, + 2441 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_hdr_is_udp_tcp", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2445 >> 8) & 0xff, + 2445 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_TL4_HDR_IS_UDP_TCP_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2449 >> 8) & 0xff, + 2449 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2453 >> 8) & 0xff, + 2453 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_TL4_HDR_TYPE_UDP}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2457 >> 8) & 0xff, + 2457 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2461 >> 8) & 0xff, + 2461 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2465 >> 8) & 0xff, + 2465 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2469 >> 8) & 0xff, + 2469 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_TL4_HDR_VALID_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2473 >> 8) & 0xff, + 2473 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_hdr_isIP", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2477 >> 8) & 0xff, + 2477 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_TL3_HDR_ISIP_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2481 >> 8) & 0xff, + 2481 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2485 >> 8) & 0xff, + 2485 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2489 >> 8) & 0xff, + 2489 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2493 >> 8) & 0xff, + 2493 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ZERO, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2497 >> 8) & 0xff, + 2497 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_THOR2_SYM_TL3_HDR_VALID_YES}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ivv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2536 >> 8) & 0xff, + 2536 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_sip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2556 >> 8) & 0xff, + 2556 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_dip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2571 >> 8) & 0xff, + 2571 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ttl.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2577 >> 8) & 0xff, + 2577 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_prot.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2583 >> 8) & 0xff, + 2583 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_qos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2589 >> 8) & 0xff, + 2589 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_src.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2595 >> 8) & 0xff, + 2595 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_dst.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2601 >> 8) & 0xff, + 2601 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tids.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2606 >> 8) & 0xff, + 2606 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_dmac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2612 >> 8) & 0xff, + 2612 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_smac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2619 >> 8) & 0xff, + 2619 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ovv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2626 >> 8) & 0xff, + 2626 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ivv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2634 >> 8) & 0xff, + 2634 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (494 >> 8) & 0xff, + 494 & 0xff} + }, + { + .description = "l2_ivv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2638 >> 8) & 0xff, + 2638 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (495 >> 8) & 0xff, + 495 & 0xff} + }, + { + .description = "l2_ivv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2642 >> 8) & 0xff, + 2642 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_etype.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2650 >> 8) & 0xff, + 2650 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip3.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2657 >> 8) & 0xff, + 2657 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip2.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2663 >> 8) & 0xff, + 2663 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip1.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2669 >> 8) & 0xff, + 2669 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2675 >> 8) & 0xff, + 2675 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (501 >> 8) & 0xff, + 501 & 0xff} + }, + { + .description = "l3_sip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2678 >> 8) & 0xff, + 2678 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (502 >> 8) & 0xff, + 502 & 0xff} + }, + { + .description = "l3_sip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2681 >> 8) & 0xff, + 2681 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_dip3.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2687 >> 8) & 0xff, + 2687 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_dip2.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2693 >> 8) & 0xff, + 2693 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_dip1.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2699 >> 8) & 0xff, + 2699 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_dip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2705 >> 8) & 0xff, + 2705 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (507 >> 8) & 0xff, + 507 & 0xff} + }, + { + .description = "l3_dip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2708 >> 8) & 0xff, + 2708 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (508 >> 8) & 0xff, + 508 & 0xff} + }, + { + .description = "l3_dip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2711 >> 8) & 0xff, + 2711 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ttl.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2717 >> 8) & 0xff, + 2717 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (510 >> 8) & 0xff, + 510 & 0xff} + }, + { + .description = "l3_ttl.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2720 >> 8) & 0xff, + 2720 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (511 >> 8) & 0xff, + 511 & 0xff} + }, + { + .description = "l3_ttl.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2723 >> 8) & 0xff, + 2723 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_prot.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2729 >> 8) & 0xff, + 2729 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (513 >> 8) & 0xff, + 513 & 0xff} + }, + { + .description = "l3_prot.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2732 >> 8) & 0xff, + 2732 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (514 >> 8) & 0xff, + 514 & 0xff} + }, + { + .description = "l3_prot.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2735 >> 8) & 0xff, + 2735 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_qos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2741 >> 8) & 0xff, + 2741 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (516 >> 8) & 0xff, + 516 & 0xff} + }, + { + .description = "l3_qos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2744 >> 8) & 0xff, + 2744 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (517 >> 8) & 0xff, + 517 & 0xff} + }, + { + .description = "l3_qos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2747 >> 8) & 0xff, + 2747 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_src.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2753 >> 8) & 0xff, + 2753 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (519 >> 8) & 0xff, + 519 & 0xff} + }, + { + .description = "l4_src.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2756 >> 8) & 0xff, + 2756 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (520 >> 8) & 0xff, + 520 & 0xff} + }, + { + .description = "l4_src.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2759 >> 8) & 0xff, + 2759 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_dst.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2765 >> 8) & 0xff, + 2765 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (522 >> 8) & 0xff, + 522 & 0xff} + }, + { + .description = "l4_dst.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2768 >> 8) & 0xff, + 2768 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (523 >> 8) & 0xff, + 523 & 0xff} + }, + { + .description = "l4_dst.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2771 >> 8) & 0xff, + 2771 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2806 >> 8) & 0xff, + 2806 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "tl2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2814 >> 8) & 0xff, + 2814 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "tl3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2853 >> 8) & 0xff, + 2853 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "tl3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2859 >> 8) & 0xff, + 2859 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_TTL >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_TTL & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "tl3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2865 >> 8) & 0xff, + 2865 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "tl3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2871 >> 8) & 0xff, + 2871 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "tl3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2877 >> 8) & 0xff, + 2877 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "tl3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2883 >> 8) & 0xff, + 2883 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_QOS >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_QOS & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "tl4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2889 >> 8) & 0xff, + 2889 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "tl4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2895 >> 8) & 0xff, + 2895 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "tl4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2901 >> 8) & 0xff, + 2901 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "tl4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2907 >> 8) & 0xff, + 2907 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "tids", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2912 >> 8) & 0xff, + 2912 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "tids", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2916 >> 8) & 0xff, + 2916 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_T_VXLAN_GPE_VNI >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_T_VXLAN_GPE_VNI & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2922 >> 8) & 0xff, + 2922 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2930 >> 8) & 0xff, + 2930 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2937 >> 8) & 0xff, + 2937 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2943 >> 8) & 0xff, + 2943 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2950 >> 8) & 0xff, + 2950 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l2_ovv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2958 >> 8) & 0xff, + 2958 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2966 >> 8) & 0xff, + 2966 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (545 >> 8) & 0xff, + 545 & 0xff} + }, + { + .description = "l2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2970 >> 8) & 0xff, + 2970 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (546 >> 8) & 0xff, + 546 & 0xff} + }, + { + .description = "l2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2974 >> 8) & 0xff, + 2974 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2982 >> 8) & 0xff, + 2982 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_IO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_IO_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (548 >> 8) & 0xff, + 548 & 0xff} + }, + { + .description = "l2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2986 >> 8) & 0xff, + 2986 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_OI_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OI_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (549 >> 8) & 0xff, + 549 & 0xff} + }, + { + .description = "l2_ivv", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2990 >> 8) & 0xff, + 2990 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2998 >> 8) & 0xff, + 2998 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l2_etype", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (3006 >> 8) & 0xff, + 3006 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_TYPE >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_TYPE & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (3013 >> 8) & 0xff, + 3013 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3.sip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (3019 >> 8) & 0xff, + 3019 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (3025 >> 8) & 0xff, + 3025 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3.sip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (3031 >> 8) & 0xff, + 3031 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (3037 >> 8) & 0xff, + 3037 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3.dip.ipv4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (3043 >> 8) & 0xff, + 3043 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (3049 >> 8) & 0xff, + 3049 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3.dip.ipv6", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (3055 >> 8) & 0xff, + 3055 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (3061 >> 8) & 0xff, + 3061 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (561 >> 8) & 0xff, + 561 & 0xff} + }, + { + .description = "l3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (3064 >> 8) & 0xff, + 3064 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (562 >> 8) & 0xff, + 562 & 0xff} + }, + { + .description = "l3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (3067 >> 8) & 0xff, + 3067 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (3073 >> 8) & 0xff, + 3073 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_IPV4_TTL >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV4_TTL & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (564 >> 8) & 0xff, + 564 & 0xff} + }, + { + .description = "l3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (3076 >> 8) & 0xff, + 3076 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_TTL >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_TTL & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (565 >> 8) & 0xff, + 565 & 0xff} + }, + { + .description = "l3.ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (3079 >> 8) & 0xff, + 3079 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_TTL >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_TTL & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (3085 >> 8) & 0xff, + 3085 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (567 >> 8) & 0xff, + 567 & 0xff} + }, + { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (3088 >> 8) & 0xff, + 3088 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (568 >> 8) & 0xff, + 568 & 0xff} + }, + { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (3091 >> 8) & 0xff, + 3091 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (3097 >> 8) & 0xff, + 3097 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_IPV4_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV4_PROTO_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (570 >> 8) & 0xff, + 570 & 0xff} + }, + { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (3100 >> 8) & 0xff, + 3100 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (571 >> 8) & 0xff, + 571 & 0xff} + }, + { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (3103 >> 8) & 0xff, + 3103 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (3109 >> 8) & 0xff, + 3109 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (573 >> 8) & 0xff, + 573 & 0xff} + }, + { + .description = "l3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (3112 >> 8) & 0xff, + 3112 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (574 >> 8) & 0xff, + 574 & 0xff} + }, + { + .description = "l3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (3115 >> 8) & 0xff, + 3115 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (3121 >> 8) & 0xff, + 3121 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_IPV4_QOS >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_IPV4_QOS & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (576 >> 8) & 0xff, + 576 & 0xff} + }, + { + .description = "l3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (3124 >> 8) & 0xff, + 3124 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_QOS >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_QOS & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (577 >> 8) & 0xff, + 577 & 0xff} + }, + { + .description = "l3.qos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (3127 >> 8) & 0xff, + 3127 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_QOS >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_QOS & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (3133 >> 8) & 0xff, + 3133 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (579 >> 8) & 0xff, + 579 & 0xff} + }, + { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (3136 >> 8) & 0xff, + 3136 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (580 >> 8) & 0xff, + 580 & 0xff} + }, + { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (3139 >> 8) & 0xff, + 3139 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (3145 >> 8) & 0xff, + 3145 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_TCP_SRC_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (582 >> 8) & 0xff, + 582 & 0xff} + }, + { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (3148 >> 8) & 0xff, + 3148 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (583 >> 8) & 0xff, + 583 & 0xff} + }, + { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (3151 >> 8) & 0xff, + 3151 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (3157 >> 8) & 0xff, + 3157 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (585 >> 8) & 0xff, + 585 & 0xff} + }, + { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (3160 >> 8) & 0xff, + 3160 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (586 >> 8) & 0xff, + 586 & 0xff} + }, + { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (3163 >> 8) & 0xff, + 3163 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (3169 >> 8) & 0xff, + 3169 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_I_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_TCP_DST_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (588 >> 8) & 0xff, + 588 & 0xff} + }, + { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (3172 >> 8) & 0xff, + 3172 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (589 >> 8) & 0xff, + 589 & 0xff} + }, + { + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (3175 >> 8) & 0xff, + 3175 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + } +}; + +struct bnxt_ulp_mapper_field_info ulp_thor2_class_result_field_list[] = { + /* class_tid: 1, , table: l2_cntxt_tcam.f1_f2_alloc_l2_cntxt */ + { + .description = "l2ip_dest_data", + .field_bit_size = 17, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2ip_dest_enb", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2ip_rfs_data", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2ip_rfs_enb", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2ip_act_rec_ptr", + .field_bit_size = 26, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2ip_act_scope", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2ip_act_hint", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2ip_act_enb", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2ip_meta", + .field_bit_size = 35, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2ip_meta_enb", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ctxt_opcode", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "prof_func_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "prsv_prof_func_id", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_cntxt_id", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "prsv_l2ip_cntxt_id", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "parif", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "prsv_parif", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 1, , table: tunnel_cache.f1_f2_wr */ + { + .description = "rid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff} + }, + { + .description = "l2_cntxt_tcam_index", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + }, + /* class_tid: 1, , table: l2_cntxt_tcam.l2_table_create */ + { + .description = "l2ip_dest_data", + .field_bit_size = 17, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2ip_dest_enb", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2ip_rfs_data", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2ip_rfs_enb", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2ip_act_rec_ptr", + .field_bit_size = 26, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff} + }, + { + .description = "l2ip_act_scope", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_PORT_TABLE, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff, + (BNXT_ULP_PORT_TABLE_TABLE_SCOPE >> 8) & 0xff, + BNXT_ULP_PORT_TABLE_TABLE_SCOPE & 0xff} + }, + { + .description = "l2ip_act_hint", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2ip_act_enb", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "l2ip_meta", + .field_bit_size = 35, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2ip_meta_enb", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ctxt_opcode", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR2_SYM_CTXT_OPCODE_NORMAL_FLOW} + }, + { + .description = "prof_func_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_PROF_FUNC_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_PROF_FUNC_ID_0 & 0xff} + }, + { + .description = "prsv_prof_func_id", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_cntxt_id", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + }, + { + .description = "prsv_l2ip_cntxt_id", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "parif", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "prsv_parif", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 1, , table: mac_addr_cache.l2_table_wr */ + { + .description = "rid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff} + }, + { + .description = "l2_cntxt_tcam_index", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + }, + { + .description = "src_property_ptr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "prof_func_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_PROF_FUNC_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_PROF_FUNC_ID_0 & 0xff} + }, + /* class_tid: 1, , table: hdr_overlap_cache.overlap_check */ + { + .description = "rid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "hdr_bitmap", + .field_bit_size = 64, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_HDR_BITMAP >> 8) & 0xff, + BNXT_ULP_CF_IDX_HDR_BITMAP & 0xff} + }, + /* class_tid: 1, , table: hdr_overlap_cache.overlap_wr */ + { + .description = "rid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_RID_1 >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID_1 & 0xff} + }, + { + .description = "hdr_bitmap", + .field_bit_size = 64, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_HDR_BITMAP >> 8) & 0xff, + BNXT_ULP_CF_IDX_HDR_BITMAP & 0xff} + }, + /* class_tid: 1, , table: fkb_select.wc_gen_template */ + { + .description = "l2_cntxt_id.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (33 >> 8) & 0xff, + 33 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2ip_func.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "parif.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "spif.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "svif.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "lcos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meta_hi.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (34 >> 8) & 0xff, + 34 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meta_lo.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (35 >> 8) & 0xff, + 35 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rcyc_cnt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (36 >> 8) & 0xff, + 36 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "loopback.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_l2type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_dmac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_smac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_dt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_sa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_nvt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_ovp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_ovd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_ovv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_ovt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_ivp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_ivd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_ivv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_ivt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_etype.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_l3type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_sip3.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_sip2.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_sip1.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_sip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_dip3.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_dip2.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_dip1.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_dip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_ttl.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_prot.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_fid.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_qos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_ieh_nonext.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_ieh_esp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_ieh_auth.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_ieh_dest.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_ieh_frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_ieh_rthdr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_ieh_hop.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_ieh_1frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_df.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_l3err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl4_l4type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl4_src.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl4_dst.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl4_flags.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl4_seq.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl4_pa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl4_opt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl4_tcpts.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl4_err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otuntype.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otflags.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otids.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otid.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otctxts.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otctxt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otqos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "oterr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_l2type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_dmac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (37 >> 8) & 0xff, + 37 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_smac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (40 >> 8) & 0xff, + 40 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_dt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_sa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_nvt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ovp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ovd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ovv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (43 >> 8) & 0xff, + 43 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ovt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ivp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ivd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ivv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (47 >> 8) & 0xff, + 47 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT + }, + { + .description = "tl2_ivt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_etype.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (55 >> 8) & 0xff, + 55 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_l3type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_sip3.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (59 >> 8) & 0xff, + 59 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_sip2.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (62 >> 8) & 0xff, + 62 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_sip1.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (65 >> 8) & 0xff, + 65 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_sip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (68 >> 8) & 0xff, + 68 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (1 >> 8) & 0xff, + 1 & 0xff} + }, + { + .description = "tl3_dip3.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (74 >> 8) & 0xff, + 74 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_dip2.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (77 >> 8) & 0xff, + 77 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_dip1.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (80 >> 8) & 0xff, + 80 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_dip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (83 >> 8) & 0xff, + 83 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (2 >> 8) & 0xff, + 2 & 0xff} + }, + { + .description = "tl3_ttl.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (89 >> 8) & 0xff, + 89 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (3 >> 8) & 0xff, + 3 & 0xff} + }, + { + .description = "tl3_prot.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (95 >> 8) & 0xff, + 95 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (4 >> 8) & 0xff, + 4 & 0xff} + }, + { + .description = "tl3_fid.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_qos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (101 >> 8) & 0xff, + 101 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (5 >> 8) & 0xff, + 5 & 0xff} + }, + { + .description = "tl3_ieh_nonext.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_esp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_auth.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_dest.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_rthdr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_hop.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_1frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_df.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_l3err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_l4type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_src.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (107 >> 8) & 0xff, + 107 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (6 >> 8) & 0xff, + 6 & 0xff} + }, + { + .description = "tl4_dst.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (113 >> 8) & 0xff, + 113 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (7 >> 8) & 0xff, + 7 & 0xff} + }, + { + .description = "tl4_flags.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_seq.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_pa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_opt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_tcpts.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tuntype.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tflags.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tids.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (119 >> 8) & 0xff, + 119 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (8 >> 8) & 0xff, + 8 & 0xff} + }, + { + .description = "tid.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tctxts.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tctxt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tqos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "terr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_l2type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_dmac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (123 >> 8) & 0xff, + 123 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (9 >> 8) & 0xff, + 9 & 0xff} + }, + { + .description = "l2_smac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (129 >> 8) & 0xff, + 129 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (10 >> 8) & 0xff, + 10 & 0xff} + }, + { + .description = "l2_dt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_sa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_nvt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ovp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ovd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ovv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (135 >> 8) & 0xff, + 135 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (11 >> 8) & 0xff, + 11 & 0xff} + }, + { + .description = "l2_ovt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ivp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ivd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ivv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (143 >> 8) & 0xff, + 143 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (12 >> 8) & 0xff, + 12 & 0xff} + }, + { + .description = "l2_ivt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_etype.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (159 >> 8) & 0xff, + 159 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (15 >> 8) & 0xff, + 15 & 0xff} + }, + { + .description = "l3_l3type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip3.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (167 >> 8) & 0xff, + 167 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (16 >> 8) & 0xff, + 16 & 0xff} + }, + { + .description = "l3_sip2.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (173 >> 8) & 0xff, + 173 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (17 >> 8) & 0xff, + 17 & 0xff} + }, + { + .description = "l3_sip1.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (179 >> 8) & 0xff, + 179 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (18 >> 8) & 0xff, + 18 & 0xff} + }, + { + .description = "l3_sip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (185 >> 8) & 0xff, + 185 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (19 >> 8) & 0xff, + 19 & 0xff} + }, + { + .description = "l3_dip3.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (197 >> 8) & 0xff, + 197 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (22 >> 8) & 0xff, + 22 & 0xff} + }, + { + .description = "l3_dip2.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (203 >> 8) & 0xff, + 203 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (23 >> 8) & 0xff, + 23 & 0xff} + }, + { + .description = "l3_dip1.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (209 >> 8) & 0xff, + 209 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (24 >> 8) & 0xff, + 24 & 0xff} + }, + { + .description = "l3_dip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (215 >> 8) & 0xff, + 215 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (25 >> 8) & 0xff, + 25 & 0xff} + }, + { + .description = "l3_ttl.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (227 >> 8) & 0xff, + 227 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (28 >> 8) & 0xff, + 28 & 0xff} + }, + { + .description = "l3_prot.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (239 >> 8) & 0xff, + 239 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (31 >> 8) & 0xff, + 31 & 0xff} + }, + { + .description = "l3_fid.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_qos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (251 >> 8) & 0xff, + 251 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (34 >> 8) & 0xff, + 34 & 0xff} + }, + { + .description = "l3_ieh_nonext.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_esp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_auth.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_dest.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_rthdr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_hop.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_1frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_df.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_l3err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_l4type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_src.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (263 >> 8) & 0xff, + 263 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (37 >> 8) & 0xff, + 37 & 0xff} + }, + { + .description = "l4_dst.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (275 >> 8) & 0xff, + 275 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (40 >> 8) & 0xff, + 40 & 0xff} + }, + { + .description = "l4_flags.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_seq.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_ack.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_win.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_pa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_opt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_tcpts.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_tsval.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_txecr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "padding", + .field_bit_size = 85, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 1, , table: fkb_select.em_gen_template_alloc */ + { + .description = "l2_cntxt_id.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2ip_func.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "parif.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "spif.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "svif.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "lcos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meta_hi.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meta_lo.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rcyc_cnt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "loopback.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_l2type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_dmac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_smac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_dt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_sa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_nvt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_ovp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_ovd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_ovv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_ovt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_ivp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_ivd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_ivv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_ivt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_etype.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_l3type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_sip3.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_sip2.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_sip1.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_sip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_dip3.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_dip2.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_dip1.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_dip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_ttl.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_prot.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_fid.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_qos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_ieh_nonext.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_ieh_esp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_ieh_auth.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_ieh_dest.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_ieh_frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_ieh_rthdr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_ieh_hop.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_ieh_1frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_df.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_l3err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl4_l4type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl4_src.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl4_dst.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl4_flags.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl4_seq.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl4_pa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl4_opt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl4_tcpts.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl4_err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otuntype.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otflags.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otids.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otid.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otctxts.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otctxt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otqos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "oterr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_l2type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_dmac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_smac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_dt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_sa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_nvt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ovp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ovd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ovv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ovt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ivp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ivd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ivv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ivt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_etype.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_l3type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_sip3.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_sip2.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_sip1.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_sip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_dip3.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_dip2.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_dip1.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_dip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ttl.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_prot.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_fid.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_qos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_nonext.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_esp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_auth.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_dest.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_rthdr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_hop.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_1frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_df.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_l3err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_l4type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_src.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_dst.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_flags.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_seq.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_pa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_opt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_tcpts.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tuntype.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tflags.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tids.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tid.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tctxts.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tctxt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tqos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "terr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_l2type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_dmac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_smac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_dt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_sa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_nvt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ovp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ovd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ovv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ovt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ivp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ivd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ivv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ivt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_etype.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_l3type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip3.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip2.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip1.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_dip3.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_dip2.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_dip1.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_dip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ttl.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_prot.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_fid.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_qos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_nonext.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_esp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_auth.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_dest.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_rthdr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_hop.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_1frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_df.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_l3err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_l4type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_src.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_dst.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_flags.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_seq.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_ack.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_win.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_pa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_opt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_tcpts.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_tsval.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_txecr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "padding", + .field_bit_size = 85, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 1, , table: profile_tcam.gen_template */ + { + .description = "wc_scope", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_PORT_TABLE, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff, + (BNXT_ULP_PORT_TABLE_TABLE_SCOPE >> 8) & 0xff, + BNXT_ULP_PORT_TABLE_TABLE_SCOPE & 0xff} + }, + { + .description = "wc_key_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_WC_KEY_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_WC_KEY_ID_0 & 0xff} + }, + { + .description = "wc_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_WC_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_WC_PROFILE_ID_0 & 0xff} + }, + { + .description = "wc_search_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "em_scope", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_PORT_TABLE, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff, + (BNXT_ULP_PORT_TABLE_TABLE_SCOPE >> 8) & 0xff, + BNXT_ULP_PORT_TABLE_TABLE_SCOPE & 0xff} + }, + { + .description = "em_key_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff} + }, + { + .description = "em_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + }, + { + .description = "em_search_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "pl_byp_lkup_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "padding", + .field_bit_size = 21, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 1, , table: proto_header_cache.wr */ + { + .description = "rid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff} + }, + { + .description = "profile_tcam_index", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff} + }, + { + .description = "em_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + }, + { + .description = "em_key_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff} + }, + { + .description = "wc_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_WC_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_WC_PROFILE_ID_0 & 0xff} + }, + { + .description = "wc_key_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_WC_KEY_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_WC_KEY_ID_0 & 0xff} + }, + /* class_tid: 1, , table: fkb_select.em_gen_template */ + { + .description = "l2_cntxt_id.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (942 >> 8) & 0xff, + 942 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2ip_func.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "parif.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "spif.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "svif.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "lcos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meta_hi.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (943 >> 8) & 0xff, + 943 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meta_lo.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (944 >> 8) & 0xff, + 944 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rcyc_cnt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (945 >> 8) & 0xff, + 945 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "loopback.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_l2type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_dmac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_smac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_dt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_sa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_nvt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_ovp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_ovd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_ovv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_ovt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_ivp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_ivd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_ivv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_ivt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_etype.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_l3type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_sip3.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_sip2.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_sip1.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_sip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_dip3.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_dip2.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_dip1.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_dip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_ttl.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_prot.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_fid.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_qos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_ieh_nonext.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_ieh_esp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_ieh_auth.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_ieh_dest.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_ieh_frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_ieh_rthdr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_ieh_hop.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_ieh_1frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_df.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_l3err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl4_l4type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl4_src.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl4_dst.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl4_flags.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl4_seq.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl4_pa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl4_opt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl4_tcpts.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl4_err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otuntype.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otflags.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otids.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otid.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otctxts.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otctxt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otqos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "oterr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_l2type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_dmac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (946 >> 8) & 0xff, + 946 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_smac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (950 >> 8) & 0xff, + 950 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_dt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_sa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_nvt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ovp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ovd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ovv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (953 >> 8) & 0xff, + 953 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ovt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ivp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ivd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ivv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (957 >> 8) & 0xff, + 957 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (186 >> 8) & 0xff, + 186 & 0xff} + }, + { + .description = "tl2_ivt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_etype.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (965 >> 8) & 0xff, + 965 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_l3type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_sip3.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (969 >> 8) & 0xff, + 969 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_sip2.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (972 >> 8) & 0xff, + 972 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_sip1.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (975 >> 8) & 0xff, + 975 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_sip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (978 >> 8) & 0xff, + 978 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (187 >> 8) & 0xff, + 187 & 0xff} + }, + { + .description = "tl3_dip3.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (984 >> 8) & 0xff, + 984 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_dip2.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (987 >> 8) & 0xff, + 987 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_dip1.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (990 >> 8) & 0xff, + 990 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_dip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (993 >> 8) & 0xff, + 993 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (188 >> 8) & 0xff, + 188 & 0xff} + }, + { + .description = "tl3_ttl.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (999 >> 8) & 0xff, + 999 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (189 >> 8) & 0xff, + 189 & 0xff} + }, + { + .description = "tl3_prot.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1005 >> 8) & 0xff, + 1005 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (190 >> 8) & 0xff, + 190 & 0xff} + }, + { + .description = "tl3_fid.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_qos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1011 >> 8) & 0xff, + 1011 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (191 >> 8) & 0xff, + 191 & 0xff} + }, + { + .description = "tl3_ieh_nonext.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_esp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_auth.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_dest.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_rthdr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_hop.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_1frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_df.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_l3err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_l4type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_src.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1017 >> 8) & 0xff, + 1017 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (192 >> 8) & 0xff, + 192 & 0xff} + }, + { + .description = "tl4_dst.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1023 >> 8) & 0xff, + 1023 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (193 >> 8) & 0xff, + 193 & 0xff} + }, + { + .description = "tl4_flags.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_seq.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_pa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_opt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_tcpts.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tuntype.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tflags.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tids.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1029 >> 8) & 0xff, + 1029 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (194 >> 8) & 0xff, + 194 & 0xff} + }, + { + .description = "tid.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tctxts.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tctxt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tqos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "terr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_l2type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_dmac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1033 >> 8) & 0xff, + 1033 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (195 >> 8) & 0xff, + 195 & 0xff} + }, + { + .description = "l2_smac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1041 >> 8) & 0xff, + 1041 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (196 >> 8) & 0xff, + 196 & 0xff} + }, + { + .description = "l2_dt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_sa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_nvt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ovp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ovd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ovv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1047 >> 8) & 0xff, + 1047 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (197 >> 8) & 0xff, + 197 & 0xff} + }, + { + .description = "l2_ovt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ivp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ivd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ivv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1055 >> 8) & 0xff, + 1055 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (198 >> 8) & 0xff, + 198 & 0xff} + }, + { + .description = "l2_ivt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_etype.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1071 >> 8) & 0xff, + 1071 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (201 >> 8) & 0xff, + 201 & 0xff} + }, + { + .description = "l3_l3type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip3.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1079 >> 8) & 0xff, + 1079 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (202 >> 8) & 0xff, + 202 & 0xff} + }, + { + .description = "l3_sip2.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1085 >> 8) & 0xff, + 1085 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (203 >> 8) & 0xff, + 203 & 0xff} + }, + { + .description = "l3_sip1.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1091 >> 8) & 0xff, + 1091 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (204 >> 8) & 0xff, + 204 & 0xff} + }, + { + .description = "l3_sip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1097 >> 8) & 0xff, + 1097 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (205 >> 8) & 0xff, + 205 & 0xff} + }, + { + .description = "l3_dip3.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1109 >> 8) & 0xff, + 1109 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (208 >> 8) & 0xff, + 208 & 0xff} + }, + { + .description = "l3_dip2.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1115 >> 8) & 0xff, + 1115 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (209 >> 8) & 0xff, + 209 & 0xff} + }, + { + .description = "l3_dip1.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1121 >> 8) & 0xff, + 1121 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (210 >> 8) & 0xff, + 210 & 0xff} + }, + { + .description = "l3_dip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1127 >> 8) & 0xff, + 1127 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (211 >> 8) & 0xff, + 211 & 0xff} + }, + { + .description = "l3_ttl.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1139 >> 8) & 0xff, + 1139 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (214 >> 8) & 0xff, + 214 & 0xff} + }, + { + .description = "l3_prot.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1151 >> 8) & 0xff, + 1151 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (217 >> 8) & 0xff, + 217 & 0xff} + }, + { + .description = "l3_fid.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_qos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1163 >> 8) & 0xff, + 1163 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (220 >> 8) & 0xff, + 220 & 0xff} + }, + { + .description = "l3_ieh_nonext.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_esp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_auth.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_dest.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_rthdr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_hop.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_1frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_df.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_l3err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_l4type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_src.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1175 >> 8) & 0xff, + 1175 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (223 >> 8) & 0xff, + 223 & 0xff} + }, + { + .description = "l4_dst.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1187 >> 8) & 0xff, + 1187 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (226 >> 8) & 0xff, + 226 & 0xff} + }, + { + .description = "l4_flags.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_seq.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_ack.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_win.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_pa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_opt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_tcpts.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_tsval.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_txecr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "padding", + .field_bit_size = 85, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 1, , table: em_flow_conflict_cache.wr */ + { + .description = "rid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff} + }, + { + .description = "flow_sig_id", + .field_bit_size = 64, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff} + }, + /* class_tid: 1, , table: em_normal.ingress_generic_template */ + { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "rec_size", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "epoch0", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_FUNCTION_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_FUNCTION_ID & 0xff} + }, + { + .description = "epoch1", + .field_bit_size = 6, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "opcode", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "strength", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 3} + }, + { + .description = "act_hint", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "act_rec_ptr", + .field_bit_size = 26, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + }, + { + .description = "ring_table_idx", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "act_rec_size", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "paths_m1", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "fc_op", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "fc_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "fc_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "pad2", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "range_profile", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "range_index", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 1, , table: wm_normal.ingress_generic_template */ + { + .description = "fc_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "fc_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "fc_op", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "paths_m1", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "act_rec_size", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ring_table_idx", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "act_rec_ptr", + .field_bit_size = 26, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + }, + { + .description = "act_hint", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "strength", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "opcode", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "epoch1", + .field_bit_size = 6, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "epoch0", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_FUNCTION_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_FUNCTION_ID & 0xff} + }, + { + .description = "rec_size", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "pad1", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 2, , table: hdr_overlap_cache.overlap_check */ + { + .description = "rid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "hdr_bitmap", + .field_bit_size = 64, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_HDR_BITMAP >> 8) & 0xff, + BNXT_ULP_CF_IDX_HDR_BITMAP & 0xff} + }, + /* class_tid: 2, , table: hdr_overlap_cache.overlap_wr */ + { + .description = "rid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_RID_1 >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID_1 & 0xff} + }, + { + .description = "hdr_bitmap", + .field_bit_size = 64, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_HDR_BITMAP >> 8) & 0xff, + BNXT_ULP_CF_IDX_HDR_BITMAP & 0xff} + }, + /* class_tid: 2, , table: fkb_select.wc_gen_template */ + { + .description = "l2_cntxt_id.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1608 >> 8) & 0xff, + 1608 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2ip_func.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "parif.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "spif.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "svif.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "lcos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meta_hi.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1609 >> 8) & 0xff, + 1609 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meta_lo.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1610 >> 8) & 0xff, + 1610 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rcyc_cnt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1611 >> 8) & 0xff, + 1611 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "loopback.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_l2type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_dmac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_smac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_dt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_sa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_nvt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_ovp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_ovd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_ovv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_ovt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_ivp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_ivd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_ivv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_ivt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_etype.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_l3type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_sip3.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_sip2.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_sip1.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_sip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_dip3.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_dip2.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_dip1.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_dip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_ttl.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_prot.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_fid.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_qos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_ieh_nonext.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_ieh_esp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_ieh_auth.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_ieh_dest.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_ieh_frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_ieh_rthdr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_ieh_hop.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_ieh_1frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_df.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_l3err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl4_l4type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl4_src.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl4_dst.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl4_flags.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl4_seq.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl4_pa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl4_opt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl4_tcpts.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl4_err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otuntype.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otflags.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otids.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otid.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otctxts.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otctxt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otqos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "oterr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_l2type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_dmac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1612 >> 8) & 0xff, + 1612 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_smac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1615 >> 8) & 0xff, + 1615 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_dt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_sa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_nvt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ovp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ovd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ovv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1618 >> 8) & 0xff, + 1618 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ovt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ivp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ivd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ivv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1622 >> 8) & 0xff, + 1622 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (295 >> 8) & 0xff, + 295 & 0xff} + }, + { + .description = "tl2_ivt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_etype.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1630 >> 8) & 0xff, + 1630 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_l3type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_sip3.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1634 >> 8) & 0xff, + 1634 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_sip2.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1637 >> 8) & 0xff, + 1637 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_sip1.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1640 >> 8) & 0xff, + 1640 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_sip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1643 >> 8) & 0xff, + 1643 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (296 >> 8) & 0xff, + 296 & 0xff} + }, + { + .description = "tl3_dip3.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1649 >> 8) & 0xff, + 1649 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_dip2.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1652 >> 8) & 0xff, + 1652 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_dip1.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1655 >> 8) & 0xff, + 1655 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_dip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1658 >> 8) & 0xff, + 1658 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (297 >> 8) & 0xff, + 297 & 0xff} + }, + { + .description = "tl3_ttl.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1664 >> 8) & 0xff, + 1664 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (298 >> 8) & 0xff, + 298 & 0xff} + }, + { + .description = "tl3_prot.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1670 >> 8) & 0xff, + 1670 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (299 >> 8) & 0xff, + 299 & 0xff} + }, + { + .description = "tl3_fid.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_qos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1676 >> 8) & 0xff, + 1676 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (300 >> 8) & 0xff, + 300 & 0xff} + }, + { + .description = "tl3_ieh_nonext.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_esp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_auth.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_dest.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_rthdr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_hop.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_1frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_df.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_l3err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_l4type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_src.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1682 >> 8) & 0xff, + 1682 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (301 >> 8) & 0xff, + 301 & 0xff} + }, + { + .description = "tl4_dst.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1688 >> 8) & 0xff, + 1688 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (302 >> 8) & 0xff, + 302 & 0xff} + }, + { + .description = "tl4_flags.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_seq.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_pa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_opt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_tcpts.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tuntype.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tflags.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tids.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1694 >> 8) & 0xff, + 1694 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (303 >> 8) & 0xff, + 303 & 0xff} + }, + { + .description = "tid.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tctxts.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tctxt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tqos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "terr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_l2type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_dmac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1698 >> 8) & 0xff, + 1698 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (304 >> 8) & 0xff, + 304 & 0xff} + }, + { + .description = "l2_smac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1704 >> 8) & 0xff, + 1704 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (305 >> 8) & 0xff, + 305 & 0xff} + }, + { + .description = "l2_dt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_sa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_nvt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ovp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ovd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ovv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1710 >> 8) & 0xff, + 1710 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (306 >> 8) & 0xff, + 306 & 0xff} + }, + { + .description = "l2_ovt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ivp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ivd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ivv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1718 >> 8) & 0xff, + 1718 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (307 >> 8) & 0xff, + 307 & 0xff} + }, + { + .description = "l2_ivt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_etype.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1734 >> 8) & 0xff, + 1734 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (310 >> 8) & 0xff, + 310 & 0xff} + }, + { + .description = "l3_l3type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip3.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1742 >> 8) & 0xff, + 1742 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (311 >> 8) & 0xff, + 311 & 0xff} + }, + { + .description = "l3_sip2.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1748 >> 8) & 0xff, + 1748 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (312 >> 8) & 0xff, + 312 & 0xff} + }, + { + .description = "l3_sip1.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1754 >> 8) & 0xff, + 1754 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (313 >> 8) & 0xff, + 313 & 0xff} + }, + { + .description = "l3_sip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1760 >> 8) & 0xff, + 1760 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (314 >> 8) & 0xff, + 314 & 0xff} + }, + { + .description = "l3_dip3.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1772 >> 8) & 0xff, + 1772 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (317 >> 8) & 0xff, + 317 & 0xff} + }, + { + .description = "l3_dip2.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1778 >> 8) & 0xff, + 1778 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (318 >> 8) & 0xff, + 318 & 0xff} + }, + { + .description = "l3_dip1.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1784 >> 8) & 0xff, + 1784 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (319 >> 8) & 0xff, + 319 & 0xff} + }, + { + .description = "l3_dip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1790 >> 8) & 0xff, + 1790 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (320 >> 8) & 0xff, + 320 & 0xff} + }, + { + .description = "l3_ttl.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1802 >> 8) & 0xff, + 1802 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (323 >> 8) & 0xff, + 323 & 0xff} + }, + { + .description = "l3_prot.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1814 >> 8) & 0xff, + 1814 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (326 >> 8) & 0xff, + 326 & 0xff} + }, + { + .description = "l3_fid.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_qos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1826 >> 8) & 0xff, + 1826 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (329 >> 8) & 0xff, + 329 & 0xff} + }, + { + .description = "l3_ieh_nonext.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_esp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_auth.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_dest.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_rthdr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_hop.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_1frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_df.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_l3err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_l4type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_src.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1838 >> 8) & 0xff, + 1838 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (332 >> 8) & 0xff, + 332 & 0xff} + }, + { + .description = "l4_dst.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (1850 >> 8) & 0xff, + 1850 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (335 >> 8) & 0xff, + 335 & 0xff} + }, + { + .description = "l4_flags.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_seq.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_ack.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_win.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_pa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_opt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_tcpts.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_tsval.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_txecr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "padding", + .field_bit_size = 85, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 2, , table: fkb_select.em_gen_template_alloc */ + { + .description = "l2_cntxt_id.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2ip_func.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "parif.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "spif.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "svif.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "lcos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meta_hi.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meta_lo.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rcyc_cnt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "loopback.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_l2type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_dmac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_smac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_dt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_sa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_nvt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_ovp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_ovd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_ovv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_ovt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_ivp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_ivd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_ivv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_ivt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_etype.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_l3type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_sip3.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_sip2.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_sip1.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_sip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_dip3.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_dip2.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_dip1.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_dip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_ttl.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_prot.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_fid.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_qos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_ieh_nonext.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_ieh_esp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_ieh_auth.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_ieh_dest.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_ieh_frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_ieh_rthdr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_ieh_hop.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_ieh_1frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_df.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_l3err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl4_l4type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl4_src.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl4_dst.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl4_flags.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl4_seq.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl4_pa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl4_opt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl4_tcpts.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl4_err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otuntype.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otflags.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otids.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otid.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otctxts.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otctxt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otqos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "oterr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_l2type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_dmac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_smac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_dt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_sa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_nvt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ovp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ovd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ovv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ovt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ivp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ivd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ivv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ivt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_etype.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_l3type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_sip3.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_sip2.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_sip1.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_sip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_dip3.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_dip2.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_dip1.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_dip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ttl.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_prot.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_fid.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_qos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_nonext.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_esp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_auth.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_dest.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_rthdr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_hop.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_1frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_df.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_l3err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_l4type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_src.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_dst.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_flags.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_seq.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_pa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_opt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_tcpts.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tuntype.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tflags.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tids.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tid.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tctxts.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tctxt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tqos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "terr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_l2type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_dmac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_smac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_dt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_sa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_nvt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ovp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ovd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ovv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ovt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ivp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ivd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ivv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ivt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_etype.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_l3type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip3.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip2.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip1.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_dip3.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_dip2.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_dip1.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_dip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ttl.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_prot.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_fid.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_qos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_nonext.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_esp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_auth.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_dest.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_rthdr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_hop.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_1frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_df.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_l3err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_l4type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_src.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_dst.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_flags.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_seq.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_ack.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_win.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_pa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_opt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_tcpts.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_tsval.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_txecr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "padding", + .field_bit_size = 85, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 2, , table: profile_tcam.gen_template */ + { + .description = "wc_scope", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_PORT_TABLE, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff, + (BNXT_ULP_PORT_TABLE_TABLE_SCOPE >> 8) & 0xff, + BNXT_ULP_PORT_TABLE_TABLE_SCOPE & 0xff} + }, + { + .description = "wc_key_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_WC_KEY_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_WC_KEY_ID_0 & 0xff} + }, + { + .description = "wc_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_WC_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_WC_PROFILE_ID_0 & 0xff} + }, + { + .description = "wc_search_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "em_scope", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_PORT_TABLE, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff, + (BNXT_ULP_PORT_TABLE_TABLE_SCOPE >> 8) & 0xff, + BNXT_ULP_PORT_TABLE_TABLE_SCOPE & 0xff} + }, + { + .description = "em_key_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff} + }, + { + .description = "em_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + }, + { + .description = "em_search_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "pl_byp_lkup_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "padding", + .field_bit_size = 21, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 2, , table: proto_header_cache.wr */ + { + .description = "rid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff} + }, + { + .description = "profile_tcam_index", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff} + }, + { + .description = "em_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + }, + { + .description = "em_key_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff} + }, + { + .description = "wc_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_WC_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_WC_PROFILE_ID_0 & 0xff} + }, + { + .description = "wc_key_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_WC_KEY_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_WC_KEY_ID_0 & 0xff} + }, + /* class_tid: 2, , table: fkb_select.em_gen_template */ + { + .description = "l2_cntxt_id.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2517 >> 8) & 0xff, + 2517 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2ip_func.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "parif.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "spif.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "svif.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "lcos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meta_hi.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2518 >> 8) & 0xff, + 2518 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meta_lo.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2519 >> 8) & 0xff, + 2519 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rcyc_cnt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2520 >> 8) & 0xff, + 2520 & 0xff, + (1 >> 8) & 0xff, + 1 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "loopback.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_l2type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_dmac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_smac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_dt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_sa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_nvt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_ovp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_ovd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_ovv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_ovt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_ivp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_ivd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_ivv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_ivt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl2_etype.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_l3type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_sip3.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_sip2.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_sip1.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_sip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_dip3.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_dip2.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_dip1.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_dip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_ttl.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_prot.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_fid.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_qos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_ieh_nonext.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_ieh_esp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_ieh_auth.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_ieh_dest.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_ieh_frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_ieh_rthdr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_ieh_hop.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_ieh_1frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_df.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl3_l3err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl4_l4type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl4_src.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl4_dst.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl4_flags.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl4_seq.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl4_pa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl4_opt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl4_tcpts.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otl4_err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otuntype.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otflags.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otids.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otid.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otctxts.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otctxt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "otqos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "oterr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_l2type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_dmac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2521 >> 8) & 0xff, + 2521 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_smac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2525 >> 8) & 0xff, + 2525 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_dt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_sa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_nvt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ovp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ovd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ovv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2528 >> 8) & 0xff, + 2528 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ovt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ivp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ivd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_ivv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2532 >> 8) & 0xff, + 2532 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (481 >> 8) & 0xff, + 481 & 0xff} + }, + { + .description = "tl2_ivt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl2_etype.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2540 >> 8) & 0xff, + 2540 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_l3type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_sip3.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2544 >> 8) & 0xff, + 2544 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_sip2.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2547 >> 8) & 0xff, + 2547 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_sip1.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2550 >> 8) & 0xff, + 2550 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_sip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2553 >> 8) & 0xff, + 2553 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (482 >> 8) & 0xff, + 482 & 0xff} + }, + { + .description = "tl3_dip3.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2559 >> 8) & 0xff, + 2559 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_dip2.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2562 >> 8) & 0xff, + 2562 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_dip1.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2565 >> 8) & 0xff, + 2565 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_dip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2568 >> 8) & 0xff, + 2568 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (483 >> 8) & 0xff, + 483 & 0xff} + }, + { + .description = "tl3_ttl.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2574 >> 8) & 0xff, + 2574 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (484 >> 8) & 0xff, + 484 & 0xff} + }, + { + .description = "tl3_prot.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2580 >> 8) & 0xff, + 2580 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (485 >> 8) & 0xff, + 485 & 0xff} + }, + { + .description = "tl3_fid.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_qos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2586 >> 8) & 0xff, + 2586 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (486 >> 8) & 0xff, + 486 & 0xff} + }, + { + .description = "tl3_ieh_nonext.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_esp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_auth.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_dest.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_rthdr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_hop.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_ieh_1frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_df.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl3_l3err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_l4type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_src.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2592 >> 8) & 0xff, + 2592 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (487 >> 8) & 0xff, + 487 & 0xff} + }, + { + .description = "tl4_dst.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2598 >> 8) & 0xff, + 2598 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (488 >> 8) & 0xff, + 488 & 0xff} + }, + { + .description = "tl4_flags.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_seq.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_pa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_opt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_tcpts.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tl4_err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tuntype.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tflags.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tids.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2604 >> 8) & 0xff, + 2604 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (489 >> 8) & 0xff, + 489 & 0xff} + }, + { + .description = "tid.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tctxts.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tctxt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tqos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "terr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_l2type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_dmac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2608 >> 8) & 0xff, + 2608 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (490 >> 8) & 0xff, + 490 & 0xff} + }, + { + .description = "l2_smac.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2616 >> 8) & 0xff, + 2616 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (491 >> 8) & 0xff, + 491 & 0xff} + }, + { + .description = "l2_dt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_sa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_nvt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ovp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ovd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ovv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2622 >> 8) & 0xff, + 2622 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (492 >> 8) & 0xff, + 492 & 0xff} + }, + { + .description = "l2_ovt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ivp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ivd.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_ivv.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2630 >> 8) & 0xff, + 2630 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (493 >> 8) & 0xff, + 493 & 0xff} + }, + { + .description = "l2_ivt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_etype.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2646 >> 8) & 0xff, + 2646 & 0xff, + (4 >> 8) & 0xff, + 4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (496 >> 8) & 0xff, + 496 & 0xff} + }, + { + .description = "l3_l3type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip3.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2654 >> 8) & 0xff, + 2654 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (497 >> 8) & 0xff, + 497 & 0xff} + }, + { + .description = "l3_sip2.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2660 >> 8) & 0xff, + 2660 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (498 >> 8) & 0xff, + 498 & 0xff} + }, + { + .description = "l3_sip1.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2666 >> 8) & 0xff, + 2666 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (499 >> 8) & 0xff, + 499 & 0xff} + }, + { + .description = "l3_sip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2672 >> 8) & 0xff, + 2672 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (500 >> 8) & 0xff, + 500 & 0xff} + }, + { + .description = "l3_dip3.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2684 >> 8) & 0xff, + 2684 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (503 >> 8) & 0xff, + 503 & 0xff} + }, + { + .description = "l3_dip2.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2690 >> 8) & 0xff, + 2690 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (504 >> 8) & 0xff, + 504 & 0xff} + }, + { + .description = "l3_dip1.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2696 >> 8) & 0xff, + 2696 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (505 >> 8) & 0xff, + 505 & 0xff} + }, + { + .description = "l3_dip0.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2702 >> 8) & 0xff, + 2702 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (506 >> 8) & 0xff, + 506 & 0xff} + }, + { + .description = "l3_ttl.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2714 >> 8) & 0xff, + 2714 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (509 >> 8) & 0xff, + 509 & 0xff} + }, + { + .description = "l3_prot.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2726 >> 8) & 0xff, + 2726 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (512 >> 8) & 0xff, + 512 & 0xff} + }, + { + .description = "l3_fid.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_qos.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2738 >> 8) & 0xff, + 2738 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (515 >> 8) & 0xff, + 515 & 0xff} + }, + { + .description = "l3_ieh_nonext.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_esp.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_auth.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_dest.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_rthdr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_hop.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_ieh_1frag.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_df.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_l3err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_l4type.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_src.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2750 >> 8) & 0xff, + 2750 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (518 >> 8) & 0xff, + 518 & 0xff} + }, + { + .description = "l4_dst.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_AND, + .field_opr1 = { + (2762 >> 8) & 0xff, + 2762 & 0xff, + (3 >> 8) & 0xff, + 3 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_NEXT, + .field_opr3 = { + (521 >> 8) & 0xff, + 521 & 0xff} + }, + { + .description = "l4_flags.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_seq.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_ack.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_win.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_pa.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_opt.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_tcpts.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_tsval.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_txecr.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_err.en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "padding", + .field_bit_size = 85, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 2, , table: em_flow_conflict_cache.wr */ + { + .description = "rid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff} + }, + { + .description = "flow_sig_id", + .field_bit_size = 64, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff} + }, + /* class_tid: 2, , table: em_normal.egress_generic_template */ + { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "rec_size", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "epoch0", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_FUNCTION_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_FUNCTION_ID & 0xff} + }, + { + .description = "epoch1", + .field_bit_size = 6, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "opcode", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "strength", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 3} + }, + { + .description = "act_hint", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "act_rec_ptr", + .field_bit_size = 26, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + }, + { + .description = "ring_table_idx", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "act_rec_size", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "paths_m1", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "fc_op", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "fc_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "fc_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "pad2", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "range_profile", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "range_index", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 2, , table: wm_normal.egress_generic_template */ + { + .description = "fc_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "fc_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "fc_op", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "paths_m1", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "act_rec_size", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ring_table_idx", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "act_rec_ptr", + .field_bit_size = 26, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + }, + { + .description = "act_hint", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "strength", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "opcode", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "epoch1", + .field_bit_size = 6, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "epoch0", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_FUNCTION_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_FUNCTION_ID & 0xff} + }, + { + .description = "rec_size", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "pad1", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 3, , table: metadata_record.act_rx_wr */ + { + .description = "meta_mask", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + (0xffffffff >> 24) & 0xff, + (0xffffffff >> 16) & 0xff, + (0xffffffff >> 8) & 0xff, + 0xffffffff & 0xff} + }, + /* class_tid: 3, , table: metadata_record.prof_rx_wr */ + { + .description = "meta_mask", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + (0xffffffff >> 24) & 0xff, + (0xffffffff >> 16) & 0xff, + (0xffffffff >> 8) & 0xff, + 0xffffffff & 0xff} + }, + /* class_tid: 3, , table: metadata_record.lkup_rx_wr */ + { + .description = "meta_mask", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + (0xffffffff >> 24) & 0xff, + (0xffffffff >> 16) & 0xff, + (0xffffffff >> 8) & 0xff, + 0xffffffff & 0xff} + }, + /* class_tid: 3, , table: metadata_record.act_tx_wr */ + { + .description = "meta_mask", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + (0xffffffff >> 24) & 0xff, + (0xffffffff >> 16) & 0xff, + (0xffffffff >> 8) & 0xff, + 0xffffffff & 0xff} + }, + /* class_tid: 3, , table: metadata_record.prof_tx_wr */ + { + .description = "meta_mask", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + (0xffffffff >> 24) & 0xff, + (0xffffffff >> 16) & 0xff, + (0xffffffff >> 8) & 0xff, + 0xffffffff & 0xff} + }, + /* class_tid: 3, , table: metadata_record.lkup_tx_wr */ + { + .description = "meta_mask", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + (0xffffffff >> 24) & 0xff, + (0xffffffff >> 16) & 0xff, + (0xffffffff >> 8) & 0xff, + 0xffffffff & 0xff} + }, + /* class_tid: 3, , table: cmm_full_act_record.ing_default_0 */ + { + .description = "type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "drop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "vlan_del_rpt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "vnic_or_vport", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "dest_op", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "decap_func", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "mirror", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meter_ptr", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat0_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat0_ing_egr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat0_ctr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat1_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat1_ing_egr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat1_ctr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "mod_rec_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "encap_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "src_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rsvd0", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 3, , table: cmm_full_act_record.egr_default_1 */ + { + .description = "type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "drop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "vlan_del_rpt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "vnic_or_vport", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "dest_op", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "decap_func", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "mirror", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meter_ptr", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat0_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat0_ing_egr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat0_ctr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat1_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat1_ing_egr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat1_ctr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "mod_rec_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "encap_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "src_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rsvd0", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 3, , table: cmm_full_act_record.ing_default_1 */ + { + .description = "type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "drop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "vlan_del_rpt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "vnic_or_vport", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff} + }, + { + .description = "dest_op", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "decap_func", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "mirror", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meter_ptr", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat0_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat0_ing_egr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat0_ctr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat1_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat1_ing_egr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat1_ctr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "mod_rec_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "encap_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "src_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rsvd0", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 3, , table: profile_tcam_bypass.ing_catch_all */ + { + .description = "act_rec_ptr", + .field_bit_size = 26, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff} + }, + { + .description = "act_scope", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_PORT_TABLE, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff, + (BNXT_ULP_PORT_TABLE_TABLE_SCOPE >> 8) & 0xff, + BNXT_ULP_PORT_TABLE_TABLE_SCOPE & 0xff} + }, + { + .description = "act_hint", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "bypass_op", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "reserved", + .field_bit_size = 6, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "pl_byp_lkup_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "padding", + .field_bit_size = 22, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 3, , table: table_scope_cache.tsid_ing_wr */ + { + .description = "rid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff} + }, + { + .description = "default_arec_ptr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff} + }, + { + .description = "prof_func", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_PROF_FUNC_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_PROF_FUNC_ID_0 & 0xff} + }, + { + .description = "parif", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "uplink_vnic", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 3, , table: port_table.ing_wr */ + { + .description = "rid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "drv_func.mac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "drv_func.parent.mac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "phy_port", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "port_is_pf", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "default_arec_ptr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff} + }, + /* class_tid: 3, , table: l2_cntxt_tcam.svif_ing */ + { + .description = "l2ip_dest_data", + .field_bit_size = 17, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2ip_dest_enb", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2ip_rfs_data", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2ip_rfs_enb", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2ip_act_rec_ptr", + .field_bit_size = 26, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff} + }, + { + .description = "l2ip_act_scope", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_PORT_TABLE, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff, + (BNXT_ULP_PORT_TABLE_TABLE_SCOPE >> 8) & 0xff, + BNXT_ULP_PORT_TABLE_TABLE_SCOPE & 0xff} + }, + { + .description = "l2ip_act_hint", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2ip_act_enb", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "l2ip_meta", + .field_bit_size = 35, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2ip_meta_enb", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ctxt_opcode", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR2_SYM_CTXT_OPCODE_NORMAL_FLOW} + }, + { + .description = "prof_func_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_PROF_FUNC_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_PROF_FUNC_ID_0 & 0xff} + }, + { + .description = "prsv_prof_func_id", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_cntxt_id", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "prsv_l2ip_cntxt_id", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "parif", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "prsv_parif", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_wr */ + { + .description = "rid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff} + }, + { + .description = "l2_cntxt_tcam_index", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff} + }, + { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + }, + { + .description = "src_property_ptr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "prof_func_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_PROF_FUNC_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_PROF_FUNC_ID_0 & 0xff} + }, + /* class_tid: 3, , table: cmm_full_act_record.egr_default_0 */ + { + .description = "type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "drop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "vlan_del_rpt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "vnic_or_vport", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "dest_op", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "decap_func", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "mirror", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meter_ptr", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat0_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat0_ing_egr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat0_ctr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat1_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat1_ing_egr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat1_ctr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "mod_rec_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "encap_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "src_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rsvd0", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 3, , table: ilt_tbl.egr */ + { + .description = "ilt_destination", + .field_bit_size = 17, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "act_rec_ptr", + .field_bit_size = 26, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + }, + { + .description = "table_scope", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_PORT_TABLE, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff, + (BNXT_ULP_PORT_TABLE_TABLE_SCOPE >> 8) & 0xff, + BNXT_ULP_PORT_TABLE_TABLE_SCOPE & 0xff} + }, + { + .description = "act_hint", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "fwd_op", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR2_SYM_FWD_OP_NORMAL_FLOW} + }, + { + .description = "en_ilt_dest", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "en_bd_action", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "en_bd_meta", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2ip_func", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "parif", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff} + }, + { + .description = "ilt_meta", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ilt_meta_prof", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "en_ilt_meta", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "reserved", + .field_bit_size = 23, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 3, , table: cmm_full_act_record.egr_default_2 */ + { + .description = "type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "drop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "vlan_del_rpt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "vnic_or_vport", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_PHY_PORT_VPORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_VPORT & 0xff} + }, + { + .description = "dest_op", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "decap_func", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "mirror", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meter_ptr", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat0_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat0_ing_egr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat0_ctr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat1_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat1_ing_egr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat1_ctr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "mod_rec_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "encap_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "src_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rsvd0", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 3, , table: port_table.egr_wr_0 */ + { + .description = "rid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "drv_func.mac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "drv_func.parent.mac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "phy_port", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "port_is_pf", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "default_arec_ptr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + }, + /* class_tid: 3, , table: mod_record.svif2meta */ + { + .description = "metadata_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "rem_ovlan", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rem_ivlan", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rep_add_ivlan", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rep_add_ovlan", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ttl_update", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tun_md_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "reserved_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_dmac_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_smac_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip_ipv6_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_dip_ipv6_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip_ipv4_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_dip_ipv4_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_sport_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_dport_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "metadata_rsvd", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "metadata_op", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 3} + }, + { + .description = "metadata_prof", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_GLB_METADATA_RX_ACT_0 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_METADATA_RX_ACT_0 & 0xff} + }, + { + .description = "metadata_data", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 3, , table: cmm_full_act_record.ing_vf2vf */ + { + .description = "type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "drop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "vlan_del_rpt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "vnic_or_vport", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "dest_op", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 2} + }, + { + .description = "decap_func", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "mirror", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meter_ptr", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat0_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat0_ing_egr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat0_ctr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat1_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat1_ing_egr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat1_ctr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "mod_rec_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MODIFY_PTR & 0xff} + }, + { + .description = "encap_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "src_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rsvd0", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 3, , table: l2_cntxt_tcam.vf2vf_ing */ + { + .description = "l2ip_dest_data", + .field_bit_size = 17, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2ip_dest_enb", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2ip_rfs_data", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2ip_rfs_enb", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2ip_act_rec_ptr", + .field_bit_size = 26, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff} + }, + { + .description = "l2ip_act_scope", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_PORT_TABLE, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff, + (BNXT_ULP_PORT_TABLE_TABLE_SCOPE >> 8) & 0xff, + BNXT_ULP_PORT_TABLE_TABLE_SCOPE & 0xff} + }, + { + .description = "l2ip_act_hint", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2ip_act_enb", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "l2ip_meta", + .field_bit_size = 35, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2ip_meta_enb", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ctxt_opcode", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR2_SYM_CTXT_OPCODE_BYPASS_LKUP} + }, + { + .description = "prof_func_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "prsv_prof_func_id", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_cntxt_id", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "prsv_l2ip_cntxt_id", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "parif", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "prsv_parif", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 3, , table: table_scope_cache.tsid_vfr_wr */ + { + .description = "rid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "default_arec_ptr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff} + }, + { + .description = "prof_func", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "parif", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "uplink_vnic", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 3, , table: l2_cntxt_tcam.no_vfr_svif_egr */ + { + .description = "l2ip_dest_data", + .field_bit_size = 17, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2ip_dest_enb", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2ip_rfs_data", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2ip_rfs_enb", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2ip_act_rec_ptr", + .field_bit_size = 26, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + }, + { + .description = "l2ip_act_scope", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_PORT_TABLE, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff, + (BNXT_ULP_PORT_TABLE_TABLE_SCOPE >> 8) & 0xff, + BNXT_ULP_PORT_TABLE_TABLE_SCOPE & 0xff} + }, + { + .description = "l2ip_act_hint", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2ip_act_enb", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "l2ip_meta", + .field_bit_size = 35, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2ip_meta_enb", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ctxt_opcode", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR2_SYM_CTXT_OPCODE_NORMAL_FLOW} + }, + { + .description = "prof_func_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_PROF_FUNC_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_PROF_FUNC_ID_0 & 0xff} + }, + { + .description = "prsv_prof_func_id", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_cntxt_id", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + }, + { + .description = "prsv_l2ip_cntxt_id", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "parif", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "prsv_parif", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + /* class_tid: 3, , table: profile_tcam_bypass.no_vfr_egr_catch_all */ + { + .description = "act_rec_ptr", + .field_bit_size = 26, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + }, + { + .description = "act_scope", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_PORT_TABLE, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff, + (BNXT_ULP_PORT_TABLE_TABLE_SCOPE >> 8) & 0xff, + BNXT_ULP_PORT_TABLE_TABLE_SCOPE & 0xff} + }, + { + .description = "act_hint", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "bypass_op", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "reserved", + .field_bit_size = 6, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "pl_byp_lkup_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "padding", + .field_bit_size = 22, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 3, , table: l2_cntxt_tcam_cache.no_vfr_egr_wr */ + { + .description = "rid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff} + }, + { + .description = "l2_cntxt_tcam_index", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff} + }, + { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + }, + { + .description = "src_property_ptr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "prof_func_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_PROF_FUNC_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_PROF_FUNC_ID_0 & 0xff} + }, + /* class_tid: 4, , table: mod_record.meta2uplink */ + { + .description = "metadata_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "rem_ovlan", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rem_ivlan", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rep_add_ivlan", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rep_add_ovlan", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ttl_update", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tun_md_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "reserved_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_dmac_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_smac_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip_ipv6_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_dip_ipv6_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip_ipv4_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_dip_ipv4_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_sport_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_dport_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "metadata_rsvd", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "metadata_op", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "metadata_prof", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_GLB_METADATA_TX_ACT_0 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_METADATA_TX_ACT_0 & 0xff} + }, + { + .description = "metadata_data", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_RF_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_RF_0 & 0xff} + }, + /* class_tid: 4, , table: cmm_full_act_record.endpoint_def_act */ + { + .description = "type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "drop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "vlan_del_rpt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "vnic_or_vport", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + (ULP_THOR2_SYM_LOOPBACK_PORT >> 8) & 0xff, + ULP_THOR2_SYM_LOOPBACK_PORT & 0xff} + }, + { + .description = "dest_op", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "decap_func", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "mirror", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meter_ptr", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat0_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat0_ing_egr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat0_ctr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat1_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat1_ing_egr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat1_ctr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "mod_rec_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MODIFY_PTR & 0xff} + }, + { + .description = "encap_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "src_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rsvd0", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 4, , table: profile_tcam_bypass.tsid_vfr_egr_catch_all */ + { + .description = "act_rec_ptr", + .field_bit_size = 26, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff} + }, + { + .description = "act_scope", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_PORT_TABLE, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff, + (BNXT_ULP_PORT_TABLE_TABLE_SCOPE >> 8) & 0xff, + BNXT_ULP_PORT_TABLE_TABLE_SCOPE & 0xff} + }, + { + .description = "act_hint", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "bypass_op", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "reserved", + .field_bit_size = 6, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "pl_byp_lkup_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "padding", + .field_bit_size = 22, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 4, , table: table_scope_cache.tsid_vfr_egr_wr */ + { + .description = "rid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff} + }, + { + .description = "default_arec_ptr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff} + }, + { + .description = "prof_func", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_PROF_FUNC_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_PROF_FUNC_ID_0 & 0xff} + }, + { + .description = "parif", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "uplink_vnic", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 4, , table: l2_cntxt_tcam.vf2vf_egr */ + { + .description = "l2ip_dest_data", + .field_bit_size = 17, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2ip_dest_enb", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2ip_rfs_data", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2ip_rfs_enb", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2ip_act_rec_ptr", + .field_bit_size = 26, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff} + }, + { + .description = "l2ip_act_scope", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_PORT_TABLE, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff, + (BNXT_ULP_PORT_TABLE_TABLE_SCOPE >> 8) & 0xff, + BNXT_ULP_PORT_TABLE_TABLE_SCOPE & 0xff} + }, + { + .description = "l2ip_act_hint", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2ip_act_enb", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "l2ip_meta", + .field_bit_size = 35, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2ip_meta_enb", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ctxt_opcode", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR2_SYM_CTXT_OPCODE_NORMAL_FLOW} + }, + { + .description = "prof_func_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_PROF_FUNC_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_PROF_FUNC_ID_0 & 0xff} + }, + { + .description = "prsv_prof_func_id", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_cntxt_id", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "prsv_l2ip_cntxt_id", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "parif", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "prsv_parif", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + /* class_tid: 4, , table: port_table.egr_wr_0 */ + { + .description = "rid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "drv_func.mac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "drv_func.parent.mac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "phy_port", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "port_is_pf", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "default_arec_ptr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff} + }, + /* class_tid: 4, , table: mod_record.vfr2vf */ + { + .description = "metadata_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "rem_ovlan", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rem_ivlan", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rep_add_ivlan", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rep_add_ovlan", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ttl_update", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tun_md_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "reserved_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_dmac_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_smac_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip_ipv6_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_dip_ipv6_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip_ipv4_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_dip_ipv4_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_sport_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_dport_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "metadata_rsvd", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "metadata_op", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "metadata_prof", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_GLB_METADATA_TX_ACT_0 >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_METADATA_TX_ACT_0 & 0xff} + }, + { + .description = "metadata_data", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_RF_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_RF_0 & 0xff} + }, + /* class_tid: 4, , table: cmm_full_act_record.vfr2vf_act */ + { + .description = "type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "drop", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "vlan_del_rpt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "vnic_or_vport", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + (ULP_THOR2_SYM_LOOPBACK_PORT >> 8) & 0xff, + ULP_THOR2_SYM_LOOPBACK_PORT & 0xff} + }, + { + .description = "dest_op", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "decap_func", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "mirror", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "meter_ptr", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat0_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat0_ing_egr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat0_ctr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat1_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat1_ing_egr", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "stat1_ctr_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "mod_rec_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MODIFY_PTR & 0xff} + }, + { + .description = "encap_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "src_ptr", + .field_bit_size = 28, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rsvd0", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } +}; + +struct bnxt_ulp_mapper_ident_info ulp_thor2_class_ident_list[] = { + /* class_tid: 1, , table: port_table.get_def_rd */ + { + .description = "default_arec_ptr", + .regfile_idx = BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR, + .ident_bit_size = 32, + .ident_bit_pos = 137 + }, + { + .description = "phy_port", + .regfile_idx = BNXT_ULP_RF_IDX_PHY_PORT, + .ident_bit_size = 8, + .ident_bit_pos = 128 + }, + /* class_tid: 1, , table: l2_cntxt_tcam_cache.def_rd */ + { + .description = "prof_func_id", + .regfile_idx = BNXT_ULP_RF_IDX_PROF_FUNC_ID_0, + .ident_bit_size = 8, + .ident_bit_pos = 84 + }, + /* class_tid: 1, , table: tunnel_cache.f1_f2_rd */ + { + .description = "l2_cntxt_id", + .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0, + .ident_bit_size = 10, + .ident_bit_pos = 42 + }, + /* class_tid: 1, , table: l2_cntxt_tcam.f1_f2_alloc_l2_cntxt */ + { + .description = "l2_cntxt_id", + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0, + .ident_bit_size = 11, + .ident_bit_pos = 109 + }, + /* class_tid: 1, , table: mac_addr_cache.l2_table_rd */ + { + .description = "l2_cntxt_id", + .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0, + .ident_bit_size = 10, + .ident_bit_pos = 42 + }, + /* class_tid: 1, , table: l2_cntxt_tcam.l2_table_create */ + { + .description = "l2_cntxt_id", + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0, + .ident_bit_size = 11, + .ident_bit_pos = 109 + }, + /* class_tid: 1, , table: proto_header_cache.rd */ + { + .description = "em_key_id", + .regfile_idx = BNXT_ULP_RF_IDX_EM_KEY_ID_0, + .ident_bit_size = 8, + .ident_bit_pos = 50 + }, + { + .description = "em_profile_id", + .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0, + .ident_bit_size = 8, + .ident_bit_pos = 42 + }, + { + .description = "profile_tcam_index", + .regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, + .ident_bit_size = 10, + .ident_bit_pos = 32 + }, + { + .description = "wc_key_id", + .regfile_idx = BNXT_ULP_RF_IDX_WC_KEY_ID_0, + .ident_bit_size = 8, + .ident_bit_pos = 66 + }, + { + .description = "wc_profile_id", + .regfile_idx = BNXT_ULP_RF_IDX_WC_PROFILE_ID_0, + .ident_bit_size = 8, + .ident_bit_pos = 58 + }, + /* class_tid: 1, , table: profile_tcam.gen_template */ + { + .description = "em_profile_id", + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .ident_type = TF_IDENT_TYPE_EM_PROF, + .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0, + .ident_bit_size = 8, + .ident_bit_pos = 33 + }, + { + .description = "wc_profile_id", + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .ident_type = TF_IDENT_TYPE_WC_PROF, + .regfile_idx = BNXT_ULP_RF_IDX_WC_PROFILE_ID_0, + .ident_bit_size = 8, + .ident_bit_pos = 12 + }, + /* class_tid: 1, , table: em_flow_conflict_cache.rd */ + { + .description = "flow_sig_id", + .regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID, + .ident_bit_size = 64, + .ident_bit_pos = 32 + }, + /* class_tid: 2, , table: port_table.get_def_rd */ + { + .description = "default_arec_ptr", + .regfile_idx = BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR, + .ident_bit_size = 32, + .ident_bit_pos = 137 + }, + /* class_tid: 2, , table: l2_cntxt_tcam_cache.def_rd */ + { + .description = "l2_cntxt_id", + .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0, + .ident_bit_size = 10, + .ident_bit_pos = 42 + }, + { + .description = "prof_func_id", + .regfile_idx = BNXT_ULP_RF_IDX_PROF_FUNC_ID_0, + .ident_bit_size = 8, + .ident_bit_pos = 84 + }, + /* class_tid: 2, , table: proto_header_cache.rd */ + { + .description = "em_key_id", + .regfile_idx = BNXT_ULP_RF_IDX_EM_KEY_ID_0, + .ident_bit_size = 8, + .ident_bit_pos = 50 + }, + { + .description = "em_profile_id", + .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0, + .ident_bit_size = 8, + .ident_bit_pos = 42 + }, + { + .description = "profile_tcam_index", + .regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, + .ident_bit_size = 10, + .ident_bit_pos = 32 + }, + { + .description = "wc_key_id", + .regfile_idx = BNXT_ULP_RF_IDX_WC_KEY_ID_0, + .ident_bit_size = 8, + .ident_bit_pos = 66 + }, + { + .description = "wc_profile_id", + .regfile_idx = BNXT_ULP_RF_IDX_WC_PROFILE_ID_0, + .ident_bit_size = 8, + .ident_bit_pos = 58 + }, + /* class_tid: 2, , table: profile_tcam.gen_template */ + { + .description = "em_profile_id", + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .ident_type = TF_IDENT_TYPE_EM_PROF, + .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0, + .ident_bit_size = 8, + .ident_bit_pos = 33 + }, + { + .description = "wc_profile_id", + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .ident_type = TF_IDENT_TYPE_WC_PROF, + .regfile_idx = BNXT_ULP_RF_IDX_WC_PROFILE_ID_0, + .ident_bit_size = 8, + .ident_bit_pos = 12 + }, + /* class_tid: 2, , table: em_flow_conflict_cache.rd */ + { + .description = "flow_sig_id", + .regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID, + .ident_bit_size = 64, + .ident_bit_pos = 32 + }, + /* class_tid: 3, , table: table_scope_cache.tsid_ing_rd */ + { + .description = "default_arec_ptr", + .regfile_idx = BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR, + .ident_bit_size = 32, + .ident_bit_pos = 32 + }, + { + .description = "prof_func", + .regfile_idx = BNXT_ULP_RF_IDX_PROF_FUNC_ID_0, + .ident_bit_size = 8, + .ident_bit_pos = 64 + }, + /* class_tid: 3, , table: profile_tcam_bypass.ing_catch_all */ + { + .description = "prof_func_id", + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .ident_type = TF_IDENT_TYPE_PROF_FUNC, + .regfile_idx = BNXT_ULP_RF_IDX_PROF_FUNC_ID_0, + .ident_bit_size = 0, + .ident_bit_pos = 0 + }, + /* class_tid: 3, , table: l2_cntxt_tcam.svif_ing */ + { + .description = "l2_cntxt_id", + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0, + .ident_bit_size = 11, + .ident_bit_pos = 109 + }, + /* class_tid: 3, , table: table_scope_cache.tsid_vfr_rd */ + { + .description = "default_arec_ptr", + .regfile_idx = BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR, + .ident_bit_size = 32, + .ident_bit_pos = 32 + }, + /* class_tid: 3, , table: l2_cntxt_tcam.vf2vf_ing */ + { + .description = "l2_cntxt_id", + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0, + .ident_bit_size = 11, + .ident_bit_pos = 109 + }, + /* class_tid: 3, , table: l2_cntxt_tcam.no_vfr_svif_egr */ + { + .description = "prof_func_id", + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .ident_type = TF_IDENT_TYPE_PROF_FUNC, + .regfile_idx = BNXT_ULP_RF_IDX_PROF_FUNC_ID_0, + .ident_bit_size = 8, + .ident_bit_pos = 100 + }, + { + .description = "l2_cntxt_id", + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0, + .ident_bit_size = 11, + .ident_bit_pos = 109 + }, + /* class_tid: 4, , table: table_scope_cache.tsid_vfr_egr_rd */ + { + .description = "default_arec_ptr", + .regfile_idx = BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR, + .ident_bit_size = 32, + .ident_bit_pos = 32 + }, + { + .description = "parif", + .regfile_idx = BNXT_ULP_RF_IDX_RF_0, + .ident_bit_size = 5, + .ident_bit_pos = 72 + }, + { + .description = "prof_func", + .regfile_idx = BNXT_ULP_RF_IDX_PROF_FUNC_ID_0, + .ident_bit_size = 8, + .ident_bit_pos = 64 + }, + /* class_tid: 4, , table: profile_tcam_bypass.tsid_vfr_egr_catch_all */ + { + .description = "prof_func_id", + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .ident_type = TF_IDENT_TYPE_PROF_FUNC, + .regfile_idx = BNXT_ULP_RF_IDX_PROF_FUNC_ID_0, + .ident_bit_size = 0, + .ident_bit_pos = 0 + }, + /* class_tid: 4, , table: l2_cntxt_tcam_cache.endpoint_def_egr_rd */ + { + .description = "l2_cntxt_id", + .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0, + .ident_bit_size = 10, + .ident_bit_pos = 42 + }, + /* class_tid: 4, , table: l2_cntxt_tcam.vf2vf_egr */ + { + .description = "l2_cntxt_id", + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0, + .ident_bit_size = 11, + .ident_bit_pos = 109 + }, + /* class_tid: 4, , table: l2_cntxt_tcam_cache.endpoint_def_egr_wr */ + { + .description = "l2_cntxt_id", + .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0, + .ident_bit_size = 10, + .ident_bit_pos = 42 + }, + { + .description = "prof_func_id", + .regfile_idx = BNXT_ULP_RF_IDX_PROF_FUNC_ID_0, + .ident_bit_size = 8, + .ident_bit_pos = 84 + }, + { + .description = "rid", + .regfile_idx = BNXT_ULP_RF_IDX_RID, + .ident_bit_size = 32, + .ident_bit_pos = 0 + } +}; + diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c index c53d28c24b..57cd1bf1a0 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c @@ -27,7 +27,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_act_tmpl_list[] = { .start_tbl_idx = 9, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 10, + .cond_start_idx = 14, .cond_nums = 0 } }, /* act_tid: 3, ingress */ @@ -37,7 +37,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_act_tmpl_list[] = { .start_tbl_idx = 19, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 14, + .cond_start_idx = 18, .cond_nums = 1 } }, /* act_tid: 4, ingress */ @@ -46,9 +46,9 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_act_tmpl_list[] = { .num_tbls = 7, .start_tbl_idx = 25, .reject_info = { - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 20, - .cond_nums = 0 } + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 24, + .cond_nums = 2 } }, /* act_tid: 5, ingress */ [5] = { @@ -57,7 +57,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_act_tmpl_list[] = { .start_tbl_idx = 32, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 27, + .cond_start_idx = 33, .cond_nums = 0 } }, /* act_tid: 6, egress */ @@ -67,7 +67,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_act_tmpl_list[] = { .start_tbl_idx = 52, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 42, + .cond_start_idx = 48, .cond_nums = 1 } }, /* act_tid: 7, egress */ @@ -77,37 +77,37 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_act_tmpl_list[] = { .start_tbl_idx = 59, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 50, + .cond_start_idx = 56, .cond_nums = 1 } }, /* act_tid: 8, egress */ [8] = { .device_name = BNXT_ULP_DEVICE_ID_THOR, - .num_tbls = 20, + .num_tbls = 25, .start_tbl_idx = 65, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 56, + .cond_start_idx = 62, .cond_nums = 1 } }, /* act_tid: 9, egress */ [9] = { .device_name = BNXT_ULP_DEVICE_ID_THOR, .num_tbls = 5, - .start_tbl_idx = 85, + .start_tbl_idx = 90, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 81, + .cond_start_idx = 94, .cond_nums = 1 } }, /* act_tid: 10, egress */ [10] = { .device_name = BNXT_ULP_DEVICE_ID_THOR, .num_tbls = 11, - .start_tbl_idx = 90, + .start_tbl_idx = 95, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 85, + .cond_start_idx = 98, .cond_nums = 0 } } }; @@ -126,6 +126,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .key_start_idx = 0, .blob_key_bit_size = 32, @@ -143,6 +144,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, .cond_start_idx = 2, .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP }, { /* act_tid: 1, , table: shared_mirror_record.rd */ @@ -159,10 +161,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .key_start_idx = 1, - .blob_key_bit_size = 4, - .key_bit_size = 4, + .blob_key_bit_size = 8, + .key_bit_size = 8, .key_num_fields = 1, .ident_start_idx = 1, .ident_nums = 1 @@ -176,6 +179,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, .cond_start_idx = 4, .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP }, { /* act_tid: 1, , table: int_flow_counter_tbl.0 */ @@ -192,6 +196,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .result_start_idx = 0, @@ -212,11 +217,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .result_start_idx = 1, .result_bit_size = 0, .result_num_fields = 0, - .encap_num_fields = 47 + .encap_num_fields = 25 }, { /* act_tid: 1, , table: mod_record.ing_no_ttl */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -227,16 +233,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .execute_info = { .cond_true_goto = 1, .cond_false_goto = 2, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 7, - .cond_nums = 3 }, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_LIST_AND, + .cond_start_idx = 0, + .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .result_start_idx = 48, + .result_start_idx = 26, .result_bit_size = 0, .result_num_fields = 0, - .encap_num_fields = 47 + .encap_num_fields = 18 }, { /* act_tid: 1, , table: int_full_act_record.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -252,9 +259,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 95, + .result_start_idx = 44, .result_bit_size = 128, .result_num_fields = 17 }, @@ -268,13 +276,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 10, + .cond_start_idx = 12, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 112, + .result_start_idx = 61, .result_bit_size = 64, .result_num_fields = 13 }, @@ -285,8 +294,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 4, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 10, + .cond_start_idx = 14, .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP }, { /* act_tid: 2, , table: shared_mirror_record.del_chk */ @@ -299,15 +309,16 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 11, + .cond_start_idx = 15, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, .ref_cnt_opcode = BNXT_ULP_REF_CNT_OPC_NOP, .key_start_idx = 2, - .blob_key_bit_size = 4, - .key_bit_size = 4, + .blob_key_bit_size = 8, + .key_bit_size = 8, .key_num_fields = 1, .ident_start_idx = 2, .ident_nums = 1 @@ -319,8 +330,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 11, + .cond_start_idx = 15, .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP }, { /* act_tid: 2, , table: control.mirror_ref_cnt_chk */ @@ -330,8 +342,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 12, + .cond_start_idx = 16, .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_DELETE_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .func_info = { @@ -349,8 +362,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 13, + .cond_start_idx = 17, .cond_nums = 0 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID }, @@ -364,14 +378,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 13, + .cond_start_idx = 17, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MIRROR_PTR_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 125, + .result_start_idx = 74, .result_bit_size = 32, .result_num_fields = 5 }, @@ -385,14 +400,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 13, + .cond_start_idx = 17, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 130, + .result_start_idx = 79, .result_bit_size = 64, .result_num_fields = 1 }, @@ -406,14 +422,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 14, + .cond_start_idx = 18, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 131, + .result_start_idx = 80, .result_bit_size = 64, .result_num_fields = 13, .encap_num_fields = 0 @@ -428,13 +445,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 14, + .cond_start_idx = 18, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MIRROR_PTR_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 144, + .result_start_idx = 93, .result_bit_size = 32, .result_num_fields = 5 }, @@ -448,18 +466,19 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 14, + .cond_start_idx = 18, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .ref_cnt_opcode = BNXT_ULP_REF_CNT_OPC_INC, .key_start_idx = 3, - .blob_key_bit_size = 4, - .key_bit_size = 4, + .blob_key_bit_size = 8, + .key_bit_size = 8, .key_num_fields = 1, - .result_start_idx = 149, + .result_start_idx = 98, .result_bit_size = 36, .result_num_fields = 2 }, @@ -473,14 +492,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 2, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 15, + .cond_start_idx = 19, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .key_start_idx = 4, - .blob_key_bit_size = 4, - .key_bit_size = 4, + .blob_key_bit_size = 8, + .key_bit_size = 8, .key_num_fields = 1, .ident_start_idx = 3, .ident_nums = 1 @@ -492,8 +512,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1023, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 16, + .cond_start_idx = 20, .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP }, { /* act_tid: 3, , table: int_flow_counter_tbl.0 */ @@ -506,12 +527,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 17, + .cond_start_idx = 21, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .result_start_idx = 151, + .result_start_idx = 100, .result_bit_size = 64, .result_num_fields = 1 }, @@ -525,15 +547,16 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 2, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 18, + .cond_start_idx = 22, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .result_start_idx = 152, + .result_start_idx = 101, .result_bit_size = 0, .result_num_fields = 0, - .encap_num_fields = 47 + .encap_num_fields = 31 }, { /* act_tid: 3, , table: mod_record.ing_no_ttl */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -545,15 +568,16 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 19, + .cond_start_idx = 23, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .result_start_idx = 199, + .result_start_idx = 132, .result_bit_size = 0, .result_num_fields = 0, - .encap_num_fields = 47 + .encap_num_fields = 24 }, { /* act_tid: 3, , table: int_full_act_record.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -565,12 +589,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 20, + .cond_start_idx = 24, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .result_start_idx = 246, + .result_start_idx = 156, .result_bit_size = 128, .result_num_fields = 17 }, @@ -584,14 +609,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 2, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 20, + .cond_start_idx = 26, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .key_start_idx = 5, - .blob_key_bit_size = 4, - .key_bit_size = 4, + .blob_key_bit_size = 8, + .key_bit_size = 8, .key_num_fields = 1, .ident_start_idx = 4, .ident_nums = 1 @@ -603,8 +629,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1023, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 21, + .cond_start_idx = 27, .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP }, { /* act_tid: 4, , table: int_flow_counter_tbl.0 */ @@ -617,13 +644,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 22, + .cond_start_idx = 28, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 263, + .result_start_idx = 173, .result_bit_size = 64, .result_num_fields = 1 }, @@ -636,12 +664,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 23, + .cond_start_idx = 29, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_VNIC_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_RSS_VNIC, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .result_start_idx = 264, + .result_start_idx = 174, .result_bit_size = 0, .result_num_fields = 0 }, @@ -654,12 +683,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 24, + .cond_start_idx = 30, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_VNIC_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_RSS_VNIC, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .result_start_idx = 264, + .result_start_idx = 174, .result_bit_size = 0, .result_num_fields = 0 }, @@ -673,13 +703,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 25, + .cond_start_idx = 31, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 264, + .result_start_idx = 174, .result_bit_size = 64, .result_num_fields = 13, .encap_num_fields = 0 @@ -694,13 +725,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 27, + .cond_start_idx = 33, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 277, + .result_start_idx = 187, .result_bit_size = 64, .result_num_fields = 13, .encap_num_fields = 0 @@ -712,8 +744,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 11, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 27, + .cond_start_idx = 33, .cond_nums = 2 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP }, { /* act_tid: 5, , table: meter_profile_tbl_cache.rd */ @@ -725,10 +758,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 4, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 29, + .cond_start_idx = 35, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, .ref_cnt_opcode = BNXT_ULP_REF_CNT_OPC_NOP, .key_start_idx = 6, @@ -745,8 +779,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 30, + .cond_start_idx = 36, .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID }, @@ -760,13 +795,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 31, + .cond_start_idx = 37, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_METER_PROFILE_PTR_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, - .result_start_idx = 290, + .result_start_idx = 200, .result_bit_size = 65, .result_num_fields = 11 }, @@ -780,17 +816,18 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 31, + .cond_start_idx = 37, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .key_start_idx = 7, .blob_key_bit_size = 32, .key_bit_size = 32, .key_num_fields = 1, - .result_start_idx = 301, + .result_start_idx = 211, .result_bit_size = 42, .result_num_fields = 2 }, @@ -803,10 +840,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 31, + .cond_start_idx = 37, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, .ref_cnt_opcode = BNXT_ULP_REF_CNT_OPC_NOP, .key_start_idx = 8, @@ -823,8 +861,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 32, + .cond_start_idx = 38, .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID }, @@ -837,10 +876,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 33, + .cond_start_idx = 39, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .key_start_idx = 9, @@ -857,8 +897,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1023, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 33, + .cond_start_idx = 39, .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP }, { /* act_tid: 5, , table: meter_tbl.0 */ @@ -871,13 +912,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 34, + .cond_start_idx = 40, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_METER_PTR_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, - .result_start_idx = 303, + .result_start_idx = 213, .result_bit_size = 64, .result_num_fields = 5 }, @@ -890,17 +932,18 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 34, + .cond_start_idx = 40, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .key_start_idx = 10, .blob_key_bit_size = 32, .key_bit_size = 32, .key_num_fields = 1, - .result_start_idx = 308, + .result_start_idx = 218, .result_bit_size = 74, .result_num_fields = 3 }, @@ -911,8 +954,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 5, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 34, + .cond_start_idx = 40, .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP }, { /* act_tid: 5, , table: meter_profile_tbl_cache.del_chk */ @@ -924,10 +968,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 2, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 35, + .cond_start_idx = 41, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, .ref_cnt_opcode = BNXT_ULP_REF_CNT_OPC_NOP, .key_start_idx = 11, @@ -944,8 +989,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 36, + .cond_start_idx = 42, .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_DELETE_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .func_info = { @@ -965,10 +1011,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 37, + .cond_start_idx = 43, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, .ref_cnt_opcode = BNXT_ULP_REF_CNT_OPC_NOP, .key_start_idx = 12, @@ -985,8 +1032,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 38, + .cond_start_idx = 44, .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_DELETE_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .func_info = { @@ -1004,8 +1052,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 39, + .cond_start_idx = 45, .cond_nums = 0 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP }, { /* act_tid: 5, , table: shared_meter_tbl_cache.rd_update */ @@ -1017,10 +1066,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 39, + .cond_start_idx = 45, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, .ref_cnt_opcode = BNXT_ULP_REF_CNT_OPC_NOP, .key_start_idx = 13, @@ -1040,10 +1090,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 40, + .cond_start_idx = 46, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_RD_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_METER_PTR_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, .ident_start_idx = 9, .ident_nums = 3, @@ -1059,12 +1110,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 42, + .cond_start_idx = 48, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_METER_PTR_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, - .result_start_idx = 311, + .result_start_idx = 221, .result_bit_size = 64, .result_num_fields = 5 }, @@ -1078,14 +1130,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 2, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 43, + .cond_start_idx = 49, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .key_start_idx = 14, - .blob_key_bit_size = 4, - .key_bit_size = 4, + .blob_key_bit_size = 8, + .key_bit_size = 8, .key_num_fields = 1, .ident_start_idx = 12, .ident_nums = 1 @@ -1097,8 +1150,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1023, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 44, + .cond_start_idx = 50, .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP }, { /* act_tid: 6, , table: int_flow_counter_tbl.0 */ @@ -1111,12 +1165,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 45, + .cond_start_idx = 51, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .result_start_idx = 316, + .result_start_idx = 226, .result_bit_size = 64, .result_num_fields = 1 }, @@ -1130,12 +1185,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 46, + .cond_start_idx = 52, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .result_start_idx = 317, + .result_start_idx = 227, .result_bit_size = 0, .result_num_fields = 0, .encap_num_fields = 11 @@ -1150,15 +1206,16 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 47, + .cond_start_idx = 53, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .result_start_idx = 328, + .result_start_idx = 238, .result_bit_size = 0, .result_num_fields = 0, - .encap_num_fields = 47 + .encap_num_fields = 23 }, { /* act_tid: 6, , table: int_full_act_record.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -1170,12 +1227,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 48, + .cond_start_idx = 54, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .result_start_idx = 375, + .result_start_idx = 261, .result_bit_size = 128, .result_num_fields = 17 }, @@ -1189,12 +1247,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 50, + .cond_start_idx = 56, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .result_start_idx = 392, + .result_start_idx = 278, .result_bit_size = 64, .result_num_fields = 13 }, @@ -1208,14 +1267,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 2, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 51, + .cond_start_idx = 57, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .key_start_idx = 15, - .blob_key_bit_size = 4, - .key_bit_size = 4, + .blob_key_bit_size = 8, + .key_bit_size = 8, .key_num_fields = 1, .ident_start_idx = 13, .ident_nums = 1 @@ -1227,8 +1287,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1023, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 52, + .cond_start_idx = 58, .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP }, { /* act_tid: 7, , table: int_flow_counter_tbl.0 */ @@ -1241,12 +1302,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 53, + .cond_start_idx = 59, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .result_start_idx = 405, + .result_start_idx = 291, .result_bit_size = 64, .result_num_fields = 1 }, @@ -1260,15 +1322,16 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 2, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 54, + .cond_start_idx = 60, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .result_start_idx = 406, + .result_start_idx = 292, .result_bit_size = 0, .result_num_fields = 0, - .encap_num_fields = 47 + .encap_num_fields = 31 }, { /* act_tid: 7, , table: mod_record.ing_no_ttl */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -1280,15 +1343,16 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 55, + .cond_start_idx = 61, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .result_start_idx = 453, + .result_start_idx = 323, .result_bit_size = 0, .result_num_fields = 0, - .encap_num_fields = 47 + .encap_num_fields = 24 }, { /* act_tid: 7, , table: int_full_act_record.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -1300,12 +1364,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 56, + .cond_start_idx = 62, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .result_start_idx = 500, + .result_start_idx = 347, .result_bit_size = 128, .result_num_fields = 17 }, @@ -1319,14 +1384,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 2, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 57, + .cond_start_idx = 63, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .key_start_idx = 16, - .blob_key_bit_size = 4, - .key_bit_size = 4, + .blob_key_bit_size = 8, + .key_bit_size = 8, .key_num_fields = 1, .ident_start_idx = 14, .ident_nums = 1 @@ -1338,8 +1404,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1023, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 58, + .cond_start_idx = 64, .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP }, { /* act_tid: 8, , table: int_flow_counter_tbl.0 */ @@ -1352,12 +1419,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 59, + .cond_start_idx = 65, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .result_start_idx = 517, + .result_start_idx = 364, .result_bit_size = 64, .result_num_fields = 1 }, @@ -1370,27 +1438,29 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 4, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 60, + .cond_start_idx = 66, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .key_start_idx = 17, - .blob_key_bit_size = 80, - .key_bit_size = 80, - .key_num_fields = 2, + .blob_key_bit_size = 85, + .key_bit_size = 85, + .key_num_fields = 3, .ident_start_idx = 15, .ident_nums = 1 }, - { /* act_tid: 8, , table: control.0 */ + { /* act_tid: 8, , table: control.sp_rec_v4 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, .direction = TF_DIR_TX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 61, + .cond_start_idx = 67, .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID }, @@ -1404,14 +1474,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 62, + .cond_start_idx = 68, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .record_size = 16, - .result_start_idx = 518, + .result_start_idx = 365, .result_bit_size = 0, .result_num_fields = 0, .encap_num_fields = 3 @@ -1425,17 +1496,18 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 63, + .cond_start_idx = 69, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 19, - .blob_key_bit_size = 80, - .key_bit_size = 80, - .key_num_fields = 2, - .result_start_idx = 521, - .result_bit_size = 48, + .key_start_idx = 20, + .blob_key_bit_size = 85, + .key_bit_size = 85, + .key_num_fields = 3, + .result_start_idx = 368, + .result_bit_size = 64, .result_num_fields = 2 }, { /* act_tid: 8, , table: source_property_ipv6_cache.rd */ @@ -1447,27 +1519,29 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 4, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 63, + .cond_start_idx = 69, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 21, + .key_start_idx = 23, .blob_key_bit_size = 176, .key_bit_size = 176, .key_num_fields = 2, .ident_start_idx = 16, .ident_nums = 1 }, - { /* act_tid: 8, , table: control.0.ipv6 */ + { /* act_tid: 8, , table: control.sp_rec_v6 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, .direction = TF_DIR_TX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 64, + .cond_start_idx = 70, .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID }, @@ -1481,13 +1555,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 65, + .cond_start_idx = 71, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .record_size = 32, - .result_start_idx = 523, + .result_start_idx = 370, .result_bit_size = 0, .result_num_fields = 0, .encap_num_fields = 3 @@ -1501,16 +1576,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 66, + .cond_start_idx = 72, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 23, + .key_start_idx = 25, .blob_key_bit_size = 176, .key_bit_size = 176, .key_num_fields = 2, - .result_start_idx = 526, + .result_start_idx = 373, .result_bit_size = 48, .result_num_fields = 2 }, @@ -1524,15 +1600,16 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, - .cond_start_idx = 66, + .cond_start_idx = 72, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .result_start_idx = 528, + .result_start_idx = 375, .result_bit_size = 0, .result_num_fields = 0, - .encap_num_fields = 47 + .encap_num_fields = 18 }, { /* act_tid: 8, , table: vxlan_encap_rec_cache.rd */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, @@ -1543,15 +1620,16 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 68, + .cond_start_idx = 74, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 25, - .blob_key_bit_size = 136, - .key_bit_size = 136, - .key_num_fields = 5, + .key_start_idx = 27, + .blob_key_bit_size = 141, + .key_bit_size = 141, + .key_num_fields = 6, .ident_start_idx = 17, .ident_nums = 1 }, @@ -1564,27 +1642,29 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 70, + .cond_start_idx = 76, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 30, - .blob_key_bit_size = 232, - .key_bit_size = 232, - .key_num_fields = 5, + .key_start_idx = 33, + .blob_key_bit_size = 237, + .key_bit_size = 237, + .key_num_fields = 6, .ident_start_idx = 18, .ident_nums = 1 }, - { /* act_tid: 8, , table: control.1 */ + { /* act_tid: 8, , table: control.vxlan_v6_encap */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, .direction = TF_DIR_TX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 5, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 72, + .cond_start_idx = 78, .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID }, @@ -1598,16 +1678,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 73, + .cond_start_idx = 79, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, - .result_start_idx = 575, + .result_start_idx = 393, .result_bit_size = 0, .result_num_fields = 0, - .encap_num_fields = 30 + .encap_num_fields = 25 }, { /* act_tid: 8, , table: int_tun_encap_record.ipv6_vxlan */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -1619,15 +1700,16 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 75, + .cond_start_idx = 81, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .result_start_idx = 605, + .result_start_idx = 418, .result_bit_size = 0, .result_num_fields = 0, - .encap_num_fields = 30 + .encap_num_fields = 23 }, { /* act_tid: 8, , table: vxlan_encap_rec_cache.wr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, @@ -1638,17 +1720,18 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 77, + .cond_start_idx = 83, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 35, - .blob_key_bit_size = 136, - .key_bit_size = 136, - .key_num_fields = 5, - .result_start_idx = 635, - .result_bit_size = 48, + .key_start_idx = 39, + .blob_key_bit_size = 141, + .key_bit_size = 141, + .key_num_fields = 6, + .result_start_idx = 441, + .result_bit_size = 64, .result_num_fields = 2 }, { /* act_tid: 8, , table: vxlan_encap_ipv6_rec_cache.wr */ @@ -1660,17 +1743,119 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 79, + .cond_start_idx = 85, .cond_nums = 2 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 40, - .blob_key_bit_size = 232, - .key_bit_size = 232, - .key_num_fields = 5, - .result_start_idx = 637, - .result_bit_size = 48, + .key_start_idx = 45, + .blob_key_bit_size = 237, + .key_bit_size = 237, + .key_num_fields = 6, + .result_start_idx = 443, + .result_bit_size = 64, + .result_num_fields = 2 + }, + { /* act_tid: 8, , table: geneve_encap_rec_cache.rd */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_GENEVE_ENCAP_REC_CACHE, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 87, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .key_start_idx = 51, + .blob_key_bit_size = 493, + .key_bit_size = 493, + .key_num_fields = 15, + .ident_start_idx = 19, + .ident_nums = 1 + }, + { /* act_tid: 8, , table: control.geneve_encap */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 4, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 88, + .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID + }, + { /* act_tid: 8, , table: int_geneve_encap_record.ipv4_geneve */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 89, + .cond_nums = 2 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .result_start_idx = 445, + .result_bit_size = 0, + .result_num_fields = 0, + .encap_num_fields = 31 + }, + { /* act_tid: 8, , table: int_geneve_encap_record.ipv6_geneve */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 91, + .cond_nums = 2 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .result_start_idx = 476, + .result_bit_size = 0, + .result_num_fields = 0, + .encap_num_fields = 29 + }, + { /* act_tid: 8, , table: geneve_encap_rec_cache.wr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_GENEVE_ENCAP_REC_CACHE, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 93, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .key_start_idx = 66, + .blob_key_bit_size = 493, + .key_bit_size = 493, + .key_num_fields = 15, + .result_start_idx = 505, + .result_bit_size = 64, .result_num_fields = 2 }, { /* act_tid: 8, , table: int_full_act_record.0 */ @@ -1683,13 +1868,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 81, + .cond_start_idx = 94, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 639, + .result_start_idx = 507, .result_bit_size = 128, .result_num_fields = 17 }, @@ -1703,16 +1889,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 2, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 82, + .cond_start_idx = 95, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 45, - .blob_key_bit_size = 4, - .key_bit_size = 4, + .key_start_idx = 81, + .blob_key_bit_size = 8, + .key_bit_size = 8, .key_num_fields = 1, - .ident_start_idx = 19, + .ident_start_idx = 20, .ident_nums = 1 }, { /* act_tid: 9, , table: control.mirror */ @@ -1722,8 +1909,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1023, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 83, + .cond_start_idx = 96, .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP }, { /* act_tid: 9, , table: int_flow_counter_tbl.0 */ @@ -1736,12 +1924,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 84, + .cond_start_idx = 97, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .result_start_idx = 656, + .result_start_idx = 524, .result_bit_size = 64, .result_num_fields = 1 }, @@ -1755,15 +1944,16 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 85, + .cond_start_idx = 98, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .result_start_idx = 657, + .result_start_idx = 525, .result_bit_size = 0, .result_num_fields = 0, - .encap_num_fields = 47 + .encap_num_fields = 20 }, { /* act_tid: 9, , table: int_full_act_record.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -1775,12 +1965,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 85, + .cond_start_idx = 98, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .result_start_idx = 704, + .result_start_idx = 545, .result_bit_size = 128, .result_num_fields = 17 }, @@ -1791,8 +1982,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 4, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 85, + .cond_start_idx = 98, .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP }, { /* act_tid: 10, , table: shared_mirror_record.del_chk */ @@ -1805,17 +1997,18 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 86, + .cond_start_idx = 99, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, .ref_cnt_opcode = BNXT_ULP_REF_CNT_OPC_NOP, - .key_start_idx = 46, - .blob_key_bit_size = 4, - .key_bit_size = 4, + .key_start_idx = 82, + .blob_key_bit_size = 8, + .key_bit_size = 8, .key_num_fields = 1, - .ident_start_idx = 20, + .ident_start_idx = 21, .ident_nums = 1 }, { /* act_tid: 10, , table: control.mirror_del_exist_chk */ @@ -1825,8 +2018,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 86, + .cond_start_idx = 99, .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP }, { /* act_tid: 10, , table: control.mirror_ref_cnt_chk */ @@ -1836,8 +2030,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 87, + .cond_start_idx = 100, .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_DELETE_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .func_info = { @@ -1855,8 +2050,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 88, + .cond_start_idx = 101, .cond_nums = 0 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID }, @@ -1870,14 +2066,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 88, + .cond_start_idx = 101, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MIRROR_PTR_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 721, + .result_start_idx = 562, .result_bit_size = 32, .result_num_fields = 5 }, @@ -1891,14 +2088,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 88, + .cond_start_idx = 101, .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 726, + .result_start_idx = 567, .result_bit_size = 64, .result_num_fields = 1 }, @@ -1912,16 +2110,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 89, + .cond_start_idx = 102, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, - .result_start_idx = 727, + .result_start_idx = 568, .result_bit_size = 0, .result_num_fields = 0, - .encap_num_fields = 47 + .encap_num_fields = 20 }, { /* act_tid: 10, , table: int_full_act_record.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, @@ -1933,14 +2132,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 89, + .cond_start_idx = 102, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 774, + .result_start_idx = 588, .result_bit_size = 128, .result_num_fields = 17 }, @@ -1954,13 +2154,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 89, + .cond_start_idx = 102, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MIRROR_PTR_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 791, + .result_start_idx = 605, .result_bit_size = 32, .result_num_fields = 5 }, @@ -1974,64 +2175,81 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 89, + .cond_start_idx = 102, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .ref_cnt_opcode = BNXT_ULP_REF_CNT_OPC_INC, - .key_start_idx = 47, - .blob_key_bit_size = 4, - .key_bit_size = 4, + .key_start_idx = 83, + .blob_key_bit_size = 8, + .key_bit_size = 8, .key_num_fields = 1, - .result_start_idx = 796, + .result_start_idx = 610, .result_bit_size = 36, .result_num_fields = 2 } }; +struct bnxt_ulp_mapper_cond_list_info ulp_thor_act_cond_oper_list[] = { + /* cond_execute: act_tid: 1, mod_record.ing_no_ttl:7*/ + { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 7, + .cond_nums = 1 + }, + /* cond_execute: act_tid: 1, mod_record.ing_no_ttl:7*/ + { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 8, + .cond_nums = 2 + } +}; + struct bnxt_ulp_mapper_cond_info ulp_thor_act_cond_list[] = { /* cond_reject: thor, act_tid: 1 */ { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_MULTIPLE_PORT }, - /* cond_execute: act_tid: 1, shared_meter_tbl_cache.rd */ + /* cond_execute: act_tid: 1, shared_meter_tbl_cache.rd:1*/ { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_METER }, - /* cond_execute: act_tid: 1, control.meter_chk */ + /* cond_execute: act_tid: 1, control.meter_chk:2*/ { .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, - /* cond_execute: act_tid: 1, shared_mirror_record.rd */ + /* cond_execute: act_tid: 1, shared_mirror_record.rd:3*/ { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_SHARED_SAMPLE }, - /* cond_execute: act_tid: 1, control.mirror */ + /* cond_execute: act_tid: 1, control.mirror:4*/ { .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, - /* cond_execute: act_tid: 1, int_flow_counter_tbl.0 */ + /* cond_execute: act_tid: 1, int_flow_counter_tbl.0:5*/ { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_COUNT }, - /* cond_execute: act_tid: 1, mod_record.ing_ttl */ + /* cond_execute: act_tid: 1, mod_record.ing_ttl:6*/ { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL }, - /* cond_execute: act_tid: 1, mod_record.ing_no_ttl */ + /* cond_execute: act_tid: 1, mod_record.ing_no_ttl:7*/ { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_NOT_SET, .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL }, + /* cond_execute: act_tid: 1, mod_record.ing_no_ttl:7*/ { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_SET_MAC_SRC @@ -2040,22 +2258,40 @@ struct bnxt_ulp_mapper_cond_info ulp_thor_act_cond_list[] = { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_SET_MAC_DST }, - /* cond_execute: act_tid: 2, control.delete_chk */ + /* field_cond: act_tid: 1, int_full_act_record.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_VXLAN_DECAP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_GENEVE_DECAP + }, + /* field_cond: act_tid: 1, int_compact_act_record.0 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_VXLAN_DECAP + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_GENEVE_DECAP + }, + /* cond_execute: act_tid: 2, control.delete_chk:14*/ { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_DELETE }, - /* cond_execute: act_tid: 2, control.mirror_del_exist_chk */ + /* cond_execute: act_tid: 2, control.mirror_del_exist_chk:15*/ { .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, - /* cond_execute: act_tid: 2, control.mirror_ref_cnt_chk */ + /* cond_execute: act_tid: 2, control.mirror_ref_cnt_chk:16*/ { .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, .cond_operand = BNXT_ULP_RF_IDX_CC }, - /* cond_execute: act_tid: 2, int_flow_counter_tbl.0 */ + /* cond_execute: act_tid: 2, int_flow_counter_tbl.0:17*/ { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_COUNT @@ -2065,57 +2301,66 @@ struct bnxt_ulp_mapper_cond_info ulp_thor_act_cond_list[] = { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_MULTIPLE_PORT }, - /* cond_execute: act_tid: 3, shared_mirror_record.rd */ + /* cond_execute: act_tid: 3, shared_mirror_record.rd:19*/ { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_SHARED_SAMPLE }, - /* cond_execute: act_tid: 3, control.mirror */ + /* cond_execute: act_tid: 3, control.mirror:20*/ { .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, - /* cond_execute: act_tid: 3, int_flow_counter_tbl.0 */ + /* cond_execute: act_tid: 3, int_flow_counter_tbl.0:21*/ { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_COUNT }, - /* cond_execute: act_tid: 3, mod_record.ing_ttl */ + /* cond_execute: act_tid: 3, mod_record.ing_ttl:22*/ { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL }, - /* cond_execute: act_tid: 3, mod_record.ing_no_ttl */ + /* cond_execute: act_tid: 3, mod_record.ing_no_ttl:23*/ { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_NOT_SET, .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL }, - /* cond_execute: act_tid: 4, shared_mirror_record.rd */ + /* cond_reject: thor, act_tid: 4 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_RSS + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACT_BIT_QUEUE + }, + /* cond_execute: act_tid: 4, shared_mirror_record.rd:26*/ { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_SHARED_SAMPLE }, - /* cond_execute: act_tid: 4, control.mirror */ + /* cond_execute: act_tid: 4, control.mirror:27*/ { .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, - /* cond_execute: act_tid: 4, int_flow_counter_tbl.0 */ + /* cond_execute: act_tid: 4, int_flow_counter_tbl.0:28*/ { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_COUNT }, - /* cond_execute: act_tid: 4, vnic_interface_rss_config.0 */ + /* cond_execute: act_tid: 4, vnic_interface_rss_config.0:29*/ { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_RSS }, - /* cond_execute: act_tid: 4, vnic_interface_queue_config.0 */ + /* cond_execute: act_tid: 4, vnic_interface_queue_config.0:30*/ { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_QUEUE }, - /* cond_execute: act_tid: 4, int_compact_act_record.0 */ + /* cond_execute: act_tid: 4, int_compact_act_record.0:31*/ { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_QUEUE @@ -2124,7 +2369,7 @@ struct bnxt_ulp_mapper_cond_info ulp_thor_act_cond_list[] = { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_RSS }, - /* cond_execute: act_tid: 5, control.create_check */ + /* cond_execute: act_tid: 5, control.create_check:33*/ { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_NOT_SET, .cond_operand = BNXT_ULP_ACT_BIT_UPDATE @@ -2133,62 +2378,62 @@ struct bnxt_ulp_mapper_cond_info ulp_thor_act_cond_list[] = { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_NOT_SET, .cond_operand = BNXT_ULP_ACT_BIT_DELETE }, - /* cond_execute: act_tid: 5, meter_profile_tbl_cache.rd */ + /* cond_execute: act_tid: 5, meter_profile_tbl_cache.rd:35*/ { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_METER_PROFILE }, - /* cond_execute: act_tid: 5, control.shared_meter_profile_0 */ + /* cond_execute: act_tid: 5, control.shared_meter_profile_0:36*/ { .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, - /* cond_execute: act_tid: 5, shared_meter_tbl_cache.rd */ + /* cond_execute: act_tid: 5, shared_meter_tbl_cache.rd:37*/ { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_SHARED_METER }, - /* cond_execute: act_tid: 5, control.meter_created_chk */ + /* cond_execute: act_tid: 5, control.meter_created_chk:38*/ { .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, - /* cond_execute: act_tid: 5, control.shared_meter_profile_chk */ + /* cond_execute: act_tid: 5, control.shared_meter_profile_chk:39*/ { .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, - /* cond_execute: act_tid: 5, control.delete_check */ + /* cond_execute: act_tid: 5, control.delete_check:40*/ { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_DELETE }, - /* cond_execute: act_tid: 5, meter_profile_tbl_cache.del_chk */ + /* cond_execute: act_tid: 5, meter_profile_tbl_cache.del_chk:41*/ { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_METER_PROFILE }, - /* cond_execute: act_tid: 5, control.mtr_prof_ref_cnt_chk */ + /* cond_execute: act_tid: 5, control.mtr_prof_ref_cnt_chk:42*/ { .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, .cond_operand = BNXT_ULP_RF_IDX_CC }, - /* cond_execute: act_tid: 5, shared_meter_tbl_cache.del_chk */ + /* cond_execute: act_tid: 5, shared_meter_tbl_cache.del_chk:43*/ { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_SHARED_METER }, - /* cond_execute: act_tid: 5, control.shared_mtr_ref_cnt_chk */ + /* cond_execute: act_tid: 5, control.shared_mtr_ref_cnt_chk:44*/ { .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, .cond_operand = BNXT_ULP_RF_IDX_CC }, - /* cond_execute: act_tid: 5, shared_meter_tbl_cache.rd_update */ + /* cond_execute: act_tid: 5, shared_meter_tbl_cache.rd_update:45*/ { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_SHARED_METER }, - /* cond_execute: act_tid: 5, meter_tbl.update_rd */ + /* cond_execute: act_tid: 5, meter_tbl.update_rd:46*/ { .cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET, .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS @@ -2202,32 +2447,32 @@ struct bnxt_ulp_mapper_cond_info ulp_thor_act_cond_list[] = { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_MULTIPLE_PORT }, - /* cond_execute: act_tid: 6, shared_mirror_record.rd */ + /* cond_execute: act_tid: 6, shared_mirror_record.rd:49*/ { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_SHARED_SAMPLE }, - /* cond_execute: act_tid: 6, control.mirror */ + /* cond_execute: act_tid: 6, control.mirror:50*/ { .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, - /* cond_execute: act_tid: 6, int_flow_counter_tbl.0 */ + /* cond_execute: act_tid: 6, int_flow_counter_tbl.0:51*/ { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_COUNT }, - /* cond_execute: act_tid: 6, int_vtag_encap_record.0 */ + /* cond_execute: act_tid: 6, int_vtag_encap_record.0:52*/ { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN }, - /* cond_execute: act_tid: 6, mod_record.dec_ttl_egr */ + /* cond_execute: act_tid: 6, mod_record.dec_ttl_egr:53*/ { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL }, - /* cond_execute: act_tid: 6, int_full_act_record.0 */ + /* cond_execute: act_tid: 6, int_full_act_record.0:54*/ { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL @@ -2241,27 +2486,27 @@ struct bnxt_ulp_mapper_cond_info ulp_thor_act_cond_list[] = { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_MULTIPLE_PORT }, - /* cond_execute: act_tid: 7, shared_mirror_record.rd */ + /* cond_execute: act_tid: 7, shared_mirror_record.rd:57*/ { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_SHARED_SAMPLE }, - /* cond_execute: act_tid: 7, control.mirror */ + /* cond_execute: act_tid: 7, control.mirror:58*/ { .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, - /* cond_execute: act_tid: 7, int_flow_counter_tbl.0 */ + /* cond_execute: act_tid: 7, int_flow_counter_tbl.0:59*/ { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_COUNT }, - /* cond_execute: act_tid: 7, mod_record.ing_ttl */ + /* cond_execute: act_tid: 7, mod_record.ing_ttl:60*/ { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL }, - /* cond_execute: act_tid: 7, mod_record.ing_no_ttl */ + /* cond_execute: act_tid: 7, mod_record.ing_no_ttl:61*/ { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_NOT_SET, .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL @@ -2271,52 +2516,52 @@ struct bnxt_ulp_mapper_cond_info ulp_thor_act_cond_list[] = { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_MULTIPLE_PORT }, - /* cond_execute: act_tid: 8, shared_mirror_record.rd */ + /* cond_execute: act_tid: 8, shared_mirror_record.rd:63*/ { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_SHARED_SAMPLE }, - /* cond_execute: act_tid: 8, control.mirror */ + /* cond_execute: act_tid: 8, control.mirror:64*/ { .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, - /* cond_execute: act_tid: 8, int_flow_counter_tbl.0 */ + /* cond_execute: act_tid: 8, int_flow_counter_tbl.0:65*/ { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_COUNT }, - /* cond_execute: act_tid: 8, source_property_cache.rd */ + /* cond_execute: act_tid: 8, source_property_cache.rd:66*/ { .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, .cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG }, - /* cond_execute: act_tid: 8, control.0 */ + /* cond_execute: act_tid: 8, control.sp_rec_v4:67*/ { .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, - /* cond_execute: act_tid: 8, sp_smac_ipv4.0 */ + /* cond_execute: act_tid: 8, sp_smac_ipv4.0:68*/ { .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, .cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG }, - /* cond_execute: act_tid: 8, source_property_ipv6_cache.rd */ + /* cond_execute: act_tid: 8, source_property_ipv6_cache.rd:69*/ { .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, .cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV6_FLAG }, - /* cond_execute: act_tid: 8, control.0.ipv6 */ + /* cond_execute: act_tid: 8, control.sp_rec_v6:70*/ { .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, - /* cond_execute: act_tid: 8, sp_smac_ipv6.0 */ + /* cond_execute: act_tid: 8, sp_smac_ipv6.0:71*/ { .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, .cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV6_FLAG }, - /* cond_execute: act_tid: 8, mod_record.ing_l2write */ + /* cond_execute: act_tid: 8, mod_record.ing_l2write:72*/ { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_SET_MAC_SRC @@ -2325,7 +2570,7 @@ struct bnxt_ulp_mapper_cond_info ulp_thor_act_cond_list[] = { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_SET_MAC_DST }, - /* cond_execute: act_tid: 8, vxlan_encap_rec_cache.rd */ + /* cond_execute: act_tid: 8, vxlan_encap_rec_cache.rd:74*/ { .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET, .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 @@ -2334,7 +2579,7 @@ struct bnxt_ulp_mapper_cond_info ulp_thor_act_cond_list[] = { .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET, .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN }, - /* cond_execute: act_tid: 8, vxlan_encap_ipv6_rec_cache.rd */ + /* cond_execute: act_tid: 8, vxlan_encap_ipv6_rec_cache.rd:76*/ { .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET, .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 @@ -2343,12 +2588,12 @@ struct bnxt_ulp_mapper_cond_info ulp_thor_act_cond_list[] = { .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET, .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN }, - /* cond_execute: act_tid: 8, control.1 */ + /* cond_execute: act_tid: 8, control.vxlan_v6_encap:78*/ { .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, - /* cond_execute: act_tid: 8, int_tun_encap_record.ipv4_vxlan */ + /* cond_execute: act_tid: 8, int_tun_encap_record.ipv4_vxlan:79*/ { .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET, .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 @@ -2357,7 +2602,7 @@ struct bnxt_ulp_mapper_cond_info ulp_thor_act_cond_list[] = { .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET, .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN }, - /* cond_execute: act_tid: 8, int_tun_encap_record.ipv6_vxlan */ + /* cond_execute: act_tid: 8, int_tun_encap_record.ipv6_vxlan:81*/ { .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET, .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 @@ -2366,7 +2611,7 @@ struct bnxt_ulp_mapper_cond_info ulp_thor_act_cond_list[] = { .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET, .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN }, - /* cond_execute: act_tid: 8, vxlan_encap_rec_cache.wr */ + /* cond_execute: act_tid: 8, vxlan_encap_rec_cache.wr:83*/ { .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET, .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 @@ -2375,7 +2620,7 @@ struct bnxt_ulp_mapper_cond_info ulp_thor_act_cond_list[] = { .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET, .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN }, - /* cond_execute: act_tid: 8, vxlan_encap_ipv6_rec_cache.wr */ + /* cond_execute: act_tid: 8, vxlan_encap_ipv6_rec_cache.wr:85*/ { .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET, .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 @@ -2384,42 +2629,75 @@ struct bnxt_ulp_mapper_cond_info ulp_thor_act_cond_list[] = { .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET, .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN }, + /* cond_execute: act_tid: 8, geneve_encap_rec_cache.rd:87*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_GENEVE + }, + /* cond_execute: act_tid: 8, control.geneve_encap:88*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + }, + /* cond_execute: act_tid: 8, int_geneve_encap_record.ipv4_geneve:89*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_GENEVE + }, + /* cond_execute: act_tid: 8, int_geneve_encap_record.ipv6_geneve:91*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_GENEVE + }, + /* cond_execute: act_tid: 8, geneve_encap_rec_cache.wr:93*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_GENEVE + }, /* cond_reject: thor, act_tid: 9 */ { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_MULTIPLE_PORT }, - /* cond_execute: act_tid: 9, shared_mirror_record.rd */ + /* cond_execute: act_tid: 9, shared_mirror_record.rd:95*/ { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_SHARED_SAMPLE }, - /* cond_execute: act_tid: 9, control.mirror */ + /* cond_execute: act_tid: 9, control.mirror:96*/ { .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, - /* cond_execute: act_tid: 9, int_flow_counter_tbl.0 */ + /* cond_execute: act_tid: 9, int_flow_counter_tbl.0:97*/ { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_COUNT }, - /* cond_execute: act_tid: 10, control.delete_chk */ + /* cond_execute: act_tid: 10, control.delete_chk:98*/ { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_DELETE }, - /* cond_execute: act_tid: 10, control.mirror_del_exist_chk */ + /* cond_execute: act_tid: 10, control.mirror_del_exist_chk:99*/ { .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, - /* cond_execute: act_tid: 10, control.mirror_ref_cnt_chk */ + /* cond_execute: act_tid: 10, control.mirror_ref_cnt_chk:100*/ { .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, .cond_operand = BNXT_ULP_RF_IDX_CC }, - /* cond_execute: act_tid: 10, int_flow_counter_tbl.0 */ + /* cond_execute: act_tid: 10, int_flow_counter_tbl.0:101*/ { .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET, .cond_operand = BNXT_ULP_ACT_BIT_COUNT @@ -2454,7 +2732,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_act_key_info_list[] = { { .field_info_mask = { .description = "shared_index", - .field_bit_size = 4, + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { @@ -2462,7 +2740,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_act_key_info_list[] = { }, .field_info_spec = { .description = "shared_index", - .field_bit_size = 4, + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { @@ -2474,7 +2752,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_act_key_info_list[] = { { .field_info_mask = { .description = "shared_index", - .field_bit_size = 4, + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { @@ -2482,7 +2760,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_act_key_info_list[] = { }, .field_info_spec = { .description = "shared_index", - .field_bit_size = 4, + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { @@ -2494,7 +2772,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_act_key_info_list[] = { { .field_info_mask = { .description = "shared_index", - .field_bit_size = 4, + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { @@ -2502,7 +2780,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_act_key_info_list[] = { }, .field_info_spec = { .description = "shared_index", - .field_bit_size = 4, + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -2514,7 +2792,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_act_key_info_list[] = { { .field_info_mask = { .description = "shared_index", - .field_bit_size = 4, + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { @@ -2522,7 +2800,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_act_key_info_list[] = { }, .field_info_spec = { .description = "shared_index", - .field_bit_size = 4, + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { @@ -2534,7 +2812,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_act_key_info_list[] = { { .field_info_mask = { .description = "shared_index", - .field_bit_size = 4, + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { @@ -2542,7 +2820,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_act_key_info_list[] = { }, .field_info_spec = { .description = "shared_index", - .field_bit_size = 4, + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { @@ -2738,7 +3016,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_act_key_info_list[] = { { .field_info_mask = { .description = "shared_index", - .field_bit_size = 4, + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { @@ -2746,7 +3024,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_act_key_info_list[] = { }, .field_info_spec = { .description = "shared_index", - .field_bit_size = 4, + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { @@ -2758,7 +3036,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_act_key_info_list[] = { { .field_info_mask = { .description = "shared_index", - .field_bit_size = 4, + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { @@ -2766,7 +3044,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_act_key_info_list[] = { }, .field_info_spec = { .description = "shared_index", - .field_bit_size = 4, + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { @@ -2778,7 +3056,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_act_key_info_list[] = { { .field_info_mask = { .description = "shared_index", - .field_bit_size = 4, + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { @@ -2786,7 +3064,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_act_key_info_list[] = { }, .field_info_spec = { .description = "shared_index", - .field_bit_size = 4, + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, .field_opr1 = { @@ -2841,6 +3119,20 @@ struct bnxt_ulp_mapper_key_info ulp_thor_act_key_info_list[] = { BNXT_ULP_ENC_FIELD_IPV4_SADDR & 0xff} } }, + { + .field_info_mask = { + .description = "tbl_scope", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tbl_scope", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, /* act_tid: 8, , table: source_property_cache.wr */ { .field_info_mask = { @@ -2888,6 +3180,20 @@ struct bnxt_ulp_mapper_key_info ulp_thor_act_key_info_list[] = { BNXT_ULP_ENC_FIELD_IPV4_SADDR & 0xff} } }, + { + .field_info_mask = { + .description = "tbl_scope", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tbl_scope", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, /* act_tid: 8, , table: source_property_ipv6_cache.rd */ { .field_info_mask = { @@ -3114,6 +3420,20 @@ struct bnxt_ulp_mapper_key_info ulp_thor_act_key_info_list[] = { BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff} } }, + { + .field_info_mask = { + .description = "tbl_scope", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tbl_scope", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, /* act_tid: 8, , table: vxlan_encap_ipv6_rec_cache.rd */ { .field_info_mask = { @@ -3234,6 +3554,20 @@ struct bnxt_ulp_mapper_key_info ulp_thor_act_key_info_list[] = { BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff} } }, + { + .field_info_mask = { + .description = "tbl_scope", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tbl_scope", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, /* act_tid: 8, , table: vxlan_encap_rec_cache.wr */ { .field_info_mask = { @@ -3342,6 +3676,20 @@ struct bnxt_ulp_mapper_key_info ulp_thor_act_key_info_list[] = { BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff} } }, + { + .field_info_mask = { + .description = "tbl_scope", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tbl_scope", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, /* act_tid: 8, , table: vxlan_encap_ipv6_rec_cache.wr */ { .field_info_mask = { @@ -3462,100 +3810,817 @@ struct bnxt_ulp_mapper_key_info ulp_thor_act_key_info_list[] = { BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff} } }, - /* act_tid: 9, , table: shared_mirror_record.rd */ { .field_info_mask = { - .description = "shared_index", - .field_bit_size = 4, + .description = "tbl_scope", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tbl_scope", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + /* act_tid: 8, , table: geneve_encap_rec_cache.rd */ + { + .field_info_mask = { + .description = "dmac", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, 0xff} }, .field_info_spec = { - .description = "shared_index", - .field_bit_size = 4, + .description = "dmac", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr1 = { - (BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE & 0xff} + (BNXT_ULP_ENC_FIELD_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_ETH_DMAC & 0xff} } }, - /* act_tid: 10, , table: shared_mirror_record.del_chk */ { .field_info_mask = { - .description = "shared_index", - .field_bit_size = 4, + .description = "ipv4_dst_addr", + .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { + 0xff, + 0xff, + 0xff, 0xff} }, .field_info_spec = { - .description = "shared_index", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .description = "ipv4_dst_addr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT, .field_opr1 = { - (BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE & 0xff} + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr2 = { + (BNXT_ULP_ENC_FIELD_IPV4_DADDR >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_DADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, - /* act_tid: 10, , table: shared_mirror_record.wr */ { .field_info_mask = { - .description = "shared_index", - .field_bit_size = 4, + .description = "ipv6_dst_addr", + .field_bit_size = 128, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, 0xff} }, .field_info_spec = { - .description = "shared_index", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .description = "ipv6_dst_addr", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT, .field_opr1 = { - (BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff} + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr2 = { + (BNXT_ULP_ENC_FIELD_IPV6_DADDR >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV6_DADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } - } -}; - -struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { - /* act_tid: 1, , table: int_flow_counter_tbl.0 */ - { - .description = "count", - .field_bit_size = 64, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* act_tid: 1, , table: mod_record.ing_ttl */ { - .description = "metadata_en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "udp_sport", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "udp_sport", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff} + } }, { - .description = "rem_ovlan", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "udp_dport", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "udp_dport", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff} + } }, { - .description = "rem_ivlan", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "ver_opt_len_o_c_rsvd0", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "ver_opt_len_o_c_rsvd0", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_GENEVE_VER_OPT_LEN_O_C_RSVD0 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_VER_OPT_LEN_O_C_RSVD0 & 0xff} + } }, { - .description = "rep_add_ivlan", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "proto_type", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "proto_type", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_GENEVE_PROTO_TYPE >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_PROTO_TYPE & 0xff} + } + }, + { + .field_info_mask = { + .description = "vni", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "vni", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_GENEVE_VNI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_VNI & 0xff} + } + }, + { + .field_info_mask = { + .description = "opt_w0", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "opt_w0", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_GENEVE_OPT_W0 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_OPT_W0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "opt_w1", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "opt_w1", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_GENEVE_OPT_W1 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_OPT_W1 & 0xff} + } + }, + { + .field_info_mask = { + .description = "opt_w2", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "opt_w2", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_GENEVE_OPT_W2 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_OPT_W2 & 0xff} + } + }, + { + .field_info_mask = { + .description = "opt_w3", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "opt_w3", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_GENEVE_OPT_W3 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_OPT_W3 & 0xff} + } + }, + { + .field_info_mask = { + .description = "opt_w4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "opt_w4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_GENEVE_OPT_W4 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_OPT_W4 & 0xff} + } + }, + { + .field_info_mask = { + .description = "opt_w5", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "opt_w5", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_GENEVE_OPT_W5 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_OPT_W5 & 0xff} + } + }, + { + .field_info_mask = { + .description = "tbl_scope", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tbl_scope", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + /* act_tid: 8, , table: geneve_encap_rec_cache.wr */ + { + .field_info_mask = { + .description = "dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_ETH_DMAC & 0xff} + } + }, + { + .field_info_mask = { + .description = "ipv4_dst_addr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "ipv4_dst_addr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr2 = { + (BNXT_ULP_ENC_FIELD_IPV4_DADDR >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_DADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "ipv6_dst_addr", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "ipv6_dst_addr", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr2 = { + (BNXT_ULP_ENC_FIELD_IPV6_DADDR >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV6_DADDR & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "udp_sport", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "udp_sport", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff} + } + }, + { + .field_info_mask = { + .description = "udp_dport", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "udp_dport", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff} + } + }, + { + .field_info_mask = { + .description = "ver_opt_len_o_c_rsvd0", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "ver_opt_len_o_c_rsvd0", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_GENEVE_VER_OPT_LEN_O_C_RSVD0 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_VER_OPT_LEN_O_C_RSVD0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "proto_type", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "proto_type", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_GENEVE_PROTO_TYPE >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_PROTO_TYPE & 0xff} + } + }, + { + .field_info_mask = { + .description = "vni", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "vni", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_GENEVE_VNI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_VNI & 0xff} + } + }, + { + .field_info_mask = { + .description = "opt_w0", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "opt_w0", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_GENEVE_OPT_W0 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_OPT_W0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "opt_w1", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "opt_w1", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_GENEVE_OPT_W1 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_OPT_W1 & 0xff} + } + }, + { + .field_info_mask = { + .description = "opt_w2", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "opt_w2", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_GENEVE_OPT_W2 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_OPT_W2 & 0xff} + } + }, + { + .field_info_mask = { + .description = "opt_w3", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "opt_w3", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_GENEVE_OPT_W3 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_OPT_W3 & 0xff} + } + }, + { + .field_info_mask = { + .description = "opt_w4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "opt_w4", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_GENEVE_OPT_W4 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_OPT_W4 & 0xff} + } + }, + { + .field_info_mask = { + .description = "opt_w5", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff, + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "opt_w5", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_GENEVE_OPT_W5 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_OPT_W5 & 0xff} + } + }, + { + .field_info_mask = { + .description = "tbl_scope", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tbl_scope", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + /* act_tid: 9, , table: shared_mirror_record.rd */ + { + .field_info_mask = { + .description = "shared_index", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "shared_index", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE & 0xff} + } + }, + /* act_tid: 10, , table: shared_mirror_record.del_chk */ + { + .field_info_mask = { + .description = "shared_index", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "shared_index", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE & 0xff} + } + }, + /* act_tid: 10, , table: shared_mirror_record.wr */ + { + .field_info_mask = { + .description = "shared_index", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "shared_index", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff} + } + } +}; + +struct bnxt_ulp_mapper_field_info ulp_thor_act_key_ext_list[] = { +}; + +struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { + /* act_tid: 1, , table: int_flow_counter_tbl.0 */ + { + .description = "count", + .field_bit_size = 64, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* act_tid: 1, , table: mod_record.ing_ttl */ + { + .description = "metadata_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rem_ovlan", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rem_ivlan", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "rep_add_ivlan", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "rep_add_ovlan", @@ -3658,66 +4723,6 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "metadata_data", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "metadata_rsvd", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "metadata_op", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "metadata_prof", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ivlan_tpid", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ivlan_pri", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ivlan_de", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ovlan_tpid", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ovlan_pri", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ovlan_de", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { .description = "alt_pfid", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, @@ -3766,26 +4771,6 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tun_new_prot", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "tun_ex_prot", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "tun_mv", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "reserved", - .field_bit_size = 0, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { .description = "l2_dmac", .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, @@ -3825,36 +4810,6 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC & 0xff}, .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, - { - .description = "l3_sip_ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "l3_dip_ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "l3_sip_ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "l3_dip_ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "l4_sport", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "l4_dport", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, /* act_tid: 1, , table: mod_record.ing_no_ttl */ { .description = "metadata_en", @@ -3979,121 +4934,6 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "metadata_data", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "metadata_rsvd", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "metadata_op", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "metadata_prof", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ivlan_tpid", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ivlan_pri", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ivlan_de", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ovlan_tpid", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ovlan_pri", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ovlan_de", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "alt_pfid", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "alt_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ttl_rsvd", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ttl_tl3_dec", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ttl_il3_dec", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ttl_tl3_rdir", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ttl_il3_rdir", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "tun_new_prot", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "tun_ex_prot", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "tun_mv", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "reserved", - .field_bit_size = 0, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { .description = "l2_dmac", .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, @@ -4131,37 +4971,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { .field_opr2 = { (BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC >> 8) & 0xff, BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_SKIP - }, - { - .description = "l3_sip_ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "l3_dip_ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "l3_sip_ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "l3_dip_ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "l4_sport", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "l4_dport", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, /* act_tid: 1, , table: int_full_act_record.0 */ { @@ -4200,23 +5010,17 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { { .description = "decap_func", .field_bit_size = 5, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_OR, .field_opr1 = { - ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff}, + (10 >> 8) & 0xff, + 10 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { ULP_THOR_SYM_DECAP_FUNC_THRU_TUN}, - .field_src3 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr3 = { - ULP_THOR_SYM_DECAP_FUNC_NONE} + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter", @@ -4354,23 +5158,17 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { { .description = "decap_func", .field_bit_size = 5, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opc = BNXT_ULP_FIELD_OPC_TERNARY_LIST, + .field_src1 = BNXT_ULP_FIELD_SRC_LIST_OR, .field_opr1 = { - ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff}, + (12 >> 8) & 0xff, + 12 & 0xff, + (2 >> 8) & 0xff, + 2 & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, .field_opr2 = { ULP_THOR_SYM_DECAP_FUNC_THRU_TUN}, - .field_src3 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr3 = { - ULP_THOR_SYM_DECAP_FUNC_NONE} + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "meter", @@ -4779,14 +5577,40 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { { .description = "l3_sip_ipv6_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_dip_ipv6_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_sip_ipv4_en", @@ -4865,66 +5689,6 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "metadata_data", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "metadata_rsvd", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "metadata_op", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "metadata_prof", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ivlan_tpid", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ivlan_pri", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ivlan_de", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ovlan_tpid", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ovlan_pri", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ovlan_de", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { .description = "alt_pfid", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, @@ -4973,26 +5737,6 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tun_new_prot", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "tun_ex_prot", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "tun_mv", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "reserved", - .field_bit_size = 0, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { .description = "l2_dmac", .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, @@ -5035,12 +5779,42 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { { .description = "l3_sip_ipv6", .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr2 = { + (BNXT_ULP_ACT_PROP_IDX_SET_IPV6_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV6_SRC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { .description = "l3_dip_ipv6", .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr2 = { + (BNXT_ULP_ACT_PROP_IDX_SET_IPV6_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV6_DST & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { .description = "l3_sip_ipv4", @@ -5212,14 +5986,40 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { { .description = "l3_sip_ipv6_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_dip_ipv6_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_sip_ipv4_en", @@ -5298,121 +6098,6 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "metadata_data", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "metadata_rsvd", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "metadata_op", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "metadata_prof", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ivlan_tpid", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ivlan_pri", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ivlan_de", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ovlan_tpid", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ovlan_pri", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ovlan_de", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "alt_pfid", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "alt_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ttl_rsvd", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ttl_tl3_dec", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ttl_il3_dec", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ttl_tl3_rdir", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ttl_il3_rdir", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "tun_new_prot", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "tun_ex_prot", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "tun_mv", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "reserved", - .field_bit_size = 0, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { .description = "l2_dmac", .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, @@ -5455,12 +6140,42 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { { .description = "l3_sip_ipv6", .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr2 = { + (BNXT_ULP_ACT_PROP_IDX_SET_IPV6_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV6_SRC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { .description = "l3_dip_ipv6", .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr2 = { + (BNXT_ULP_ACT_PROP_IDX_SET_IPV6_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV6_DST & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { .description = "l3_sip_ipv4", @@ -6267,93 +6982,33 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { }, { .description = "l3_dip_ipv6_en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l3_sip_ipv4_en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l3_dip_ipv4_en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l4_sport_en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "l4_dport_en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "metadata_data", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "metadata_rsvd", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "metadata_op", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "metadata_prof", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ivlan_tpid", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ivlan_pri", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ivlan_de", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "ovlan_tpid", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP + .description = "l3_sip_ipv4_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "ovlan_pri", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP + .description = "l3_dip_ipv4_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "ovlan_de", + .description = "l4_sport_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP + .description = "l4_dport_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "alt_pfid", @@ -6379,8 +7034,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, - BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff} + (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, + BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff} }, { .description = "ttl_il3_dec", @@ -6388,8 +7043,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, - BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff} + (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, + BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff} }, { .description = "ttl_tl3_rdir", @@ -6403,66 +7058,6 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - { - .description = "tun_new_prot", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "tun_ex_prot", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "tun_mv", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "reserved", - .field_bit_size = 0, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "l2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "l2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "l3_sip_ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "l3_dip_ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "l3_sip_ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "l3_dip_ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "l4_sport", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "l4_dport", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, /* act_tid: 6, , table: int_full_act_record.0 */ { .description = "sp_rec_ptr", @@ -6814,14 +7409,40 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { { .description = "l3_sip_ipv6_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_dip_ipv6_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_sip_ipv4_en", @@ -6900,66 +7521,6 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "metadata_data", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "metadata_rsvd", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "metadata_op", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "metadata_prof", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ivlan_tpid", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ivlan_pri", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ivlan_de", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ovlan_tpid", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ovlan_pri", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ovlan_de", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { .description = "alt_pfid", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, @@ -7008,26 +7569,6 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tun_new_prot", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "tun_ex_prot", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "tun_mv", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "reserved", - .field_bit_size = 0, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { .description = "l2_dmac", .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, @@ -7070,12 +7611,42 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { { .description = "l3_sip_ipv6", .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr2 = { + (BNXT_ULP_ACT_PROP_IDX_SET_IPV6_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV6_SRC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { .description = "l3_dip_ipv6", .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr2 = { + (BNXT_ULP_ACT_PROP_IDX_SET_IPV6_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV6_DST & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { .description = "l3_sip_ipv4", @@ -7247,14 +7818,40 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { { .description = "l3_sip_ipv6_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_dip_ipv6_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l3_sip_ipv4_en", @@ -7328,124 +7925,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff, (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff}, .field_src2 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr2 = { - 1}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - }, - { - .description = "metadata_data", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "metadata_rsvd", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "metadata_op", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "metadata_prof", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ivlan_tpid", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ivlan_pri", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ivlan_de", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ovlan_tpid", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ovlan_pri", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ovlan_de", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "alt_pfid", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "alt_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ttl_rsvd", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ttl_tl3_dec", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ttl_il3_dec", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ttl_tl3_rdir", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ttl_il3_rdir", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "tun_new_prot", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "tun_ex_prot", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "tun_mv", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "reserved", - .field_bit_size = 0, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP + .field_opr2 = { + 1}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { .description = "l2_dmac", @@ -7490,12 +7972,42 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { { .description = "l3_sip_ipv6", .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_SRC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr2 = { + (BNXT_ULP_ACT_PROP_IDX_SET_IPV6_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV6_SRC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { .description = "l3_dip_ipv6", .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV6_DST & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr2 = { + (BNXT_ULP_ACT_PROP_IDX_SET_IPV6_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV6_DST & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { .description = "l3_sip_ipv4", @@ -7747,7 +8259,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { }, { .description = "sp_rec_ptr", - .field_bit_size = 16, + .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -7886,227 +8398,625 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l3_sip_ipv6_en", - .field_bit_size = 1, + .description = "l3_sip_ipv6_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_dip_ipv6_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_sip_ipv4_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l3_dip_ipv4_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_sport_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l4_dport_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr2 = { + (BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "l2_smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr2 = { + (BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + /* act_tid: 8, , table: int_tun_encap_record.ipv4_vxlan */ + { + .description = "ecv_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR_SYM_ECV_VALID_YES} + }, + { + .description = "ecv_custom_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "ecv_vtag_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE & 0xff} + }, + { + .description = "ecv_l2_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR_SYM_ECV_L2_EN_YES} + }, + { + .description = "ecv_l3_type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE & 0xff} + }, + { + .description = "ecv_l4_type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR_SYM_ECV_L4_TYPE_UDP_CSUM} + }, + { + .description = "ecv_tun_type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR_SYM_ECV_TUN_TYPE_VXLAN} + }, + { + .description = "enc_eth_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_ETH_DMAC & 0xff} + }, + { + .description = "enc_o_vlan_tag", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr2 = { + (BNXT_ULP_ENC_FIELD_O_VLAN_TCI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_O_VLAN_TCI & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "enc_o_vlan_type", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr2 = { + (BNXT_ULP_ENC_FIELD_O_VLAN_TYPE >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_O_VLAN_TYPE & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "enc_i_vlan_tag", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr2 = { + (BNXT_ULP_ENC_FIELD_I_VLAN_TCI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_I_VLAN_TCI & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "enc_i_vlan_type", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr2 = { + (BNXT_ULP_ENC_FIELD_I_VLAN_TYPE >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_I_VLAN_TYPE & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + }, + { + .description = "enc_ipv4_ihl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_IPV4_IHL >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_IHL & 0xff} + }, + { + .description = "enc_ipv4_tos", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_IPV4_TOS >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_TOS & 0xff} + }, + { + .description = "enc_ipv4_pkt_id", + .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_IPV4_PKT_ID >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_PKT_ID & 0xff} }, { - .description = "l3_dip_ipv6_en", - .field_bit_size = 1, + .description = "enc_ipv4_frag", + .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_IPV4_FRAG >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_FRAG & 0xff} }, { - .description = "l3_sip_ipv4_en", - .field_bit_size = 1, + .description = "enc_ipv4_ttl", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_IPV4_TTL >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_TTL & 0xff} }, { - .description = "l3_dip_ipv4_en", - .field_bit_size = 1, + .description = "enc_ipv4_proto", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_IPV4_PROTO >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_PROTO & 0xff} }, { - .description = "l4_sport_en", - .field_bit_size = 1, + .description = "enc_ipv4_daddr", + .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_IPV4_DADDR >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV4_DADDR & 0xff} }, { - .description = "l4_dport_en", - .field_bit_size = 1, + .description = "enc_udp_sport", + .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff} }, { - .description = "metadata_data", + .description = "enc_udp_dport", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff} }, { - .description = "metadata_rsvd", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP + .description = "enc_vxlan_flags", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_VXLAN_FLAGS >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_VXLAN_FLAGS & 0xff} }, { - .description = "metadata_op", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP + .description = "enc_vxlan_rsvd0", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 & 0xff} }, { - .description = "metadata_prof", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP + .description = "enc_vxlan_vni", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff} }, { - .description = "ivlan_tpid", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP + .description = "enc_vxlan_rsvd1", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 & 0xff} }, + /* act_tid: 8, , table: int_tun_encap_record.ipv6_vxlan */ { - .description = "ivlan_pri", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP + .description = "ecv_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR_SYM_ECV_VALID_YES} }, { - .description = "ivlan_de", + .description = "ecv_custom_en", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP + .description = "ecv_vtag_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE & 0xff} }, { - .description = "ovlan_tpid", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP + .description = "ecv_l2_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR_SYM_ECV_L2_EN_YES} + }, + { + .description = "ecv_l3_type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP, + .field_opr1 = { + (BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE & 0xff} }, { - .description = "ovlan_pri", + .description = "ecv_l4_type", .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR_SYM_ECV_L4_TYPE_UDP_CSUM} }, { - .description = "ovlan_de", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP + .description = "ecv_tun_type", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_THOR_SYM_ECV_TUN_TYPE_VXLAN} }, { - .description = "ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP + .description = "enc_eth_dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_ETH_DMAC & 0xff} }, { - .description = "alt_pfid", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP + .description = "enc_o_vlan_tag", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr2 = { + (BNXT_ULP_ENC_FIELD_O_VLAN_TCI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_O_VLAN_TCI & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { - .description = "alt_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP + .description = "enc_o_vlan_type", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr2 = { + (BNXT_ULP_ENC_FIELD_O_VLAN_TYPE >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_O_VLAN_TYPE & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { - .description = "ttl_rsvd", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP + .description = "enc_i_vlan_tag", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr2 = { + (BNXT_ULP_ENC_FIELD_I_VLAN_TCI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_I_VLAN_TCI & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { - .description = "ttl_tl3_dec", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP + .description = "enc_i_vlan_type", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr2 = { + (BNXT_ULP_ENC_FIELD_I_VLAN_TYPE >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_I_VLAN_TYPE & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { - .description = "ttl_il3_dec", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP + .description = "enc_ipv6_vtc", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW & 0xff} }, { - .description = "ttl_tl3_rdir", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP + .description = "enc_ipv6_zero", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "enc_ipv6_proto", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_IPV6_PROTO >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV6_PROTO & 0xff} }, { - .description = "ttl_il3_rdir", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP + .description = "enc_ipv6_ttl", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_IPV6_TTL >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV6_TTL & 0xff} }, { - .description = "tun_new_prot", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP + .description = "enc_ipv6_daddr", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_IPV6_DADDR >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV6_DADDR & 0xff} }, { - .description = "tun_ex_prot", + .description = "enc_udp_sport", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff} }, { - .description = "tun_mv", + .description = "enc_udp_dport", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "reserved", - .field_bit_size = 0, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff} }, { - .description = "l2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .description = "enc_vxlan_flags", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr1 = { - ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, - .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + (BNXT_ULP_ENC_FIELD_VXLAN_FLAGS >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_VXLAN_FLAGS & 0xff} }, { - .description = "l2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT, + .description = "enc_vxlan_rsvd0", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr1 = { - ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP, - .field_opr2 = { - (BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_SKIP + (BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 & 0xff} }, { - .description = "l3_sip_ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP + .description = "enc_vxlan_vni", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff} }, { - .description = "l3_dip_ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP + .description = "enc_vxlan_rsvd1", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 & 0xff} }, + /* act_tid: 8, , table: vxlan_encap_rec_cache.wr */ { - .description = "l3_sip_ipv4", + .description = "rid", .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff} }, { - .description = "l3_dip_ipv4", + .description = "enc_rec_ptr", .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff} }, + /* act_tid: 8, , table: vxlan_encap_ipv6_rec_cache.wr */ { - .description = "l4_sport", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP + .description = "rid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff} }, { - .description = "l4_dport", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP + .description = "enc_rec_ptr", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff} }, - /* act_tid: 8, , table: int_tun_encap_record.ipv4_vxlan */ + /* act_tid: 8, , table: int_geneve_encap_record.ipv4_geneve */ { .description = "ecv_valid", .field_bit_size = 1, @@ -8161,7 +9071,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - ULP_THOR_SYM_ECV_TUN_TYPE_VXLAN} + ULP_THOR_SYM_ECV_TUN_TYPE_NGE} }, { .description = "enc_eth_dmac", @@ -8316,85 +9226,114 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { BNXT_ULP_ENC_FIELD_IPV4_DADDR & 0xff} }, { - .description = "enc_ipv6_vtc", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP + .description = "enc_udp_sport", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff} }, { - .description = "enc_ipv6_zero", + .description = "enc_udp_dport", .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff} }, { - .description = "enc_ipv6_proto", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP + .description = "enc_geneve_ver_opt_len_o_c_rsvd0", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_GENEVE_VER_OPT_LEN_O_C_RSVD0 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_VER_OPT_LEN_O_C_RSVD0 & 0xff} }, { - .description = "enc_ipv6_ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP + .description = "enc_geneve_proto_type", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_GENEVE_PROTO_TYPE >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_PROTO_TYPE & 0xff} }, { - .description = "enc_ipv6_daddr", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP + .description = "enc_geneve_vni", + .field_bit_size = 24, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_GENEVE_VNI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_VNI & 0xff} }, { - .description = "enc_udp_sport", - .field_bit_size = 16, + .description = "enc_geneve_rsvd1", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr1 = { - (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff} + (BNXT_ULP_ENC_FIELD_GENEVE_RSVD1 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_RSVD1 & 0xff} }, { - .description = "enc_udp_dport", - .field_bit_size = 16, + .description = "enc_geneve_opt_w0", + .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr1 = { - (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff} + (BNXT_ULP_ENC_FIELD_GENEVE_OPT_W0 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_OPT_W0 & 0xff} }, { - .description = "enc_vxlan_flags", - .field_bit_size = 8, + .description = "enc_geneve_opt_w1", + .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr1 = { - (BNXT_ULP_ENC_FIELD_VXLAN_FLAGS >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_VXLAN_FLAGS & 0xff} + (BNXT_ULP_ENC_FIELD_GENEVE_OPT_W1 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_OPT_W1 & 0xff} }, { - .description = "enc_vxlan_rsvd0", - .field_bit_size = 24, + .description = "enc_geneve_opt_w2", + .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr1 = { - (BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 & 0xff} + (BNXT_ULP_ENC_FIELD_GENEVE_OPT_W2 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_OPT_W2 & 0xff} }, { - .description = "enc_vxlan_vni", - .field_bit_size = 24, + .description = "enc_geneve_opt_w3", + .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr1 = { - (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff} + (BNXT_ULP_ENC_FIELD_GENEVE_OPT_W3 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_OPT_W3 & 0xff} }, { - .description = "enc_vxlan_rsvd1", - .field_bit_size = 8, + .description = "enc_geneve_opt_w4", + .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr1 = { - (BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 & 0xff} + (BNXT_ULP_ENC_FIELD_GENEVE_OPT_W4 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_OPT_W4 & 0xff} }, - /* act_tid: 8, , table: int_tun_encap_record.ipv6_vxlan */ + { + .description = "enc_geneve_opt_w5", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_GENEVE_OPT_W5 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_OPT_W5 & 0xff} + }, + /* act_tid: 8, , table: int_geneve_encap_record.ipv6_geneve */ { .description = "ecv_valid", .field_bit_size = 1, @@ -8449,7 +9388,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - ULP_THOR_SYM_ECV_TUN_TYPE_VXLAN} + ULP_THOR_SYM_ECV_TUN_TYPE_NGE} }, { .description = "enc_eth_dmac", @@ -8541,41 +9480,6 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { .field_src3 = BNXT_ULP_FIELD_SRC_SKIP }, { - .description = "enc_ipv4_ihl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "enc_ipv4_tos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "enc_ipv4_pkt_id", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "enc_ipv4_frag", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "enc_ipv4_ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "enc_ipv4_proto", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "enc_ipv4_daddr", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { .description = "enc_ipv6_vtc", .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, @@ -8614,83 +9518,118 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr1 = { - (BNXT_ULP_ENC_FIELD_IPV6_DADDR >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_IPV6_DADDR & 0xff} + (BNXT_ULP_ENC_FIELD_IPV6_DADDR >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_IPV6_DADDR & 0xff} + }, + { + .description = "enc_udp_sport", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff} + }, + { + .description = "enc_udp_dport", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff} + }, + { + .description = "enc_geneve_ver_opt_len_o_c_rsvd0", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_GENEVE_VER_OPT_LEN_O_C_RSVD0 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_VER_OPT_LEN_O_C_RSVD0 & 0xff} }, { - .description = "enc_udp_sport", + .description = "enc_geneve_proto_type", .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr1 = { - (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff} + (BNXT_ULP_ENC_FIELD_GENEVE_PROTO_TYPE >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_PROTO_TYPE & 0xff} }, { - .description = "enc_udp_dport", - .field_bit_size = 16, + .description = "enc_geneve_vni", + .field_bit_size = 24, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr1 = { - (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff} + (BNXT_ULP_ENC_FIELD_GENEVE_VNI >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_VNI & 0xff} }, { - .description = "enc_vxlan_flags", + .description = "enc_geneve_rsvd1", .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr1 = { - (BNXT_ULP_ENC_FIELD_VXLAN_FLAGS >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_VXLAN_FLAGS & 0xff} + (BNXT_ULP_ENC_FIELD_GENEVE_RSVD1 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_RSVD1 & 0xff} }, { - .description = "enc_vxlan_rsvd0", - .field_bit_size = 24, + .description = "enc_geneve_opt_w0", + .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr1 = { - (BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 & 0xff} + (BNXT_ULP_ENC_FIELD_GENEVE_OPT_W0 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_OPT_W0 & 0xff} }, { - .description = "enc_vxlan_vni", - .field_bit_size = 24, + .description = "enc_geneve_opt_w1", + .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr1 = { - (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff} + (BNXT_ULP_ENC_FIELD_GENEVE_OPT_W1 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_OPT_W1 & 0xff} }, { - .description = "enc_vxlan_rsvd1", - .field_bit_size = 8, + .description = "enc_geneve_opt_w2", + .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr1 = { - (BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 >> 8) & 0xff, - BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 & 0xff} + (BNXT_ULP_ENC_FIELD_GENEVE_OPT_W2 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_OPT_W2 & 0xff} }, - /* act_tid: 8, , table: vxlan_encap_rec_cache.wr */ { - .description = "rid", + .description = "enc_geneve_opt_w3", .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr1 = { - (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, - BNXT_ULP_RF_IDX_RID & 0xff} + (BNXT_ULP_ENC_FIELD_GENEVE_OPT_W3 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_OPT_W3 & 0xff} }, { - .description = "enc_rec_ptr", - .field_bit_size = 16, + .description = "enc_geneve_opt_w4", + .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, .field_opr1 = { - (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff} + (BNXT_ULP_ENC_FIELD_GENEVE_OPT_W4 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_OPT_W4 & 0xff} }, - /* act_tid: 8, , table: vxlan_encap_ipv6_rec_cache.wr */ + { + .description = "enc_geneve_opt_w5", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD, + .field_opr1 = { + (BNXT_ULP_ENC_FIELD_GENEVE_OPT_W5 >> 8) & 0xff, + BNXT_ULP_ENC_FIELD_GENEVE_OPT_W5 & 0xff} + }, + /* act_tid: 8, , table: geneve_encap_rec_cache.wr */ { .description = "rid", .field_bit_size = 32, @@ -8702,7 +9641,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { }, { .description = "enc_rec_ptr", - .field_bit_size = 16, + .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { @@ -8969,141 +9908,6 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - { - .description = "ivlan_tpid", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ivlan_pri", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ivlan_de", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ovlan_tpid", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ovlan_pri", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ovlan_de", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "alt_pfid", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "alt_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ttl_rsvd", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ttl_tl3_dec", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ttl_il3_dec", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ttl_tl3_rdir", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ttl_il3_rdir", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "tun_new_prot", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "tun_ex_prot", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "tun_mv", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "reserved", - .field_bit_size = 0, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "l2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "l2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "l3_sip_ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "l3_dip_ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "l3_sip_ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "l3_dip_ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "l4_sport", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "l4_dport", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, /* act_tid: 9, , table: int_full_act_record.0 */ { .description = "sp_rec_ptr", @@ -9402,141 +10206,6 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - { - .description = "ivlan_tpid", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ivlan_pri", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ivlan_de", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ovlan_tpid", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ovlan_pri", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ovlan_de", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "alt_pfid", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "alt_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ttl_rsvd", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ttl_tl3_dec", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ttl_il3_dec", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ttl_tl3_rdir", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "ttl_il3_rdir", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "tun_new_prot", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "tun_ex_prot", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "tun_mv", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "reserved", - .field_bit_size = 0, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "l2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "l2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "l3_sip_ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "l3_dip_ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "l3_sip_ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "l3_dip_ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "l4_sport", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - { - .description = "l4_dport", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, /* act_tid: 10, , table: int_full_act_record.0 */ { .description = "sp_rec_ptr", @@ -9820,7 +10489,7 @@ struct bnxt_ulp_mapper_ident_info ulp_thor_act_ident_list[] = { { .description = "sp_rec_ptr", .regfile_idx = BNXT_ULP_RF_IDX_MAIN_SP_PTR, - .ident_bit_size = 16, + .ident_bit_size = 32, .ident_bit_pos = 32 }, /* act_tid: 8, , table: source_property_ipv6_cache.rd */ @@ -9834,14 +10503,21 @@ struct bnxt_ulp_mapper_ident_info ulp_thor_act_ident_list[] = { { .description = "enc_rec_ptr", .regfile_idx = BNXT_ULP_RF_IDX_ENCAP_PTR_0, - .ident_bit_size = 16, + .ident_bit_size = 32, .ident_bit_pos = 32 }, /* act_tid: 8, , table: vxlan_encap_ipv6_rec_cache.rd */ { .description = "enc_rec_ptr", .regfile_idx = BNXT_ULP_RF_IDX_ENCAP_PTR_0, - .ident_bit_size = 16, + .ident_bit_size = 32, + .ident_bit_pos = 32 + }, + /* act_tid: 8, , table: geneve_encap_rec_cache.rd */ + { + .description = "enc_rec_ptr", + .regfile_idx = BNXT_ULP_RF_IDX_ENCAP_PTR_0, + .ident_bit_size = 32, .ident_bit_pos = 32 }, /* act_tid: 9, , table: shared_mirror_record.rd */ diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c index 702da11d74..780a1c28f2 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c @@ -13,51 +13,41 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = { /* class_tid: 1, ingress */ [1] = { .device_name = BNXT_ULP_DEVICE_ID_THOR, - .num_tbls = 28, + .num_tbls = 32, .start_tbl_idx = 0, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, .cond_start_idx = 0, .cond_nums = 0 } }, - /* class_tid: 2, ingress */ + /* class_tid: 2, egress */ [2] = { .device_name = BNXT_ULP_DEVICE_ID_THOR, - .num_tbls = 24, - .start_tbl_idx = 28, + .num_tbls = 20, + .start_tbl_idx = 32, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 28, + .cond_start_idx = 1503, .cond_nums = 0 } }, - /* class_tid: 3, egress */ + /* class_tid: 3, ingress */ [3] = { .device_name = BNXT_ULP_DEVICE_ID_THOR, - .num_tbls = 18, + .num_tbls = 22, .start_tbl_idx = 52, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 38, + .cond_start_idx = 2955, .cond_nums = 0 } }, - /* class_tid: 4, ingress */ + /* class_tid: 4, egress */ [4] = { .device_name = BNXT_ULP_DEVICE_ID_THOR, - .num_tbls = 21, - .start_tbl_idx = 70, + .num_tbls = 34, + .start_tbl_idx = 74, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 47, - .cond_nums = 0 } - }, - /* class_tid: 5, egress */ - [5] = { - .device_name = BNXT_ULP_DEVICE_ID_THOR, - .num_tbls = 33, - .start_tbl_idx = 91, - .reject_info = { - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 51, + .cond_start_idx = 2959, .cond_nums = 0 } } }; @@ -76,6 +66,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, .key_start_idx = 0, .blob_key_bit_size = 10, @@ -86,18 +77,18 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { }, { /* class_tid: 1, , table: l2_cntxt_tcam_cache.rd */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, .direction = TF_DIR_RX, .execute_info = { - .cond_true_goto = 5, + .cond_true_goto = 1, .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 0, - .cond_nums = 1 }, + .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .key_start_idx = 1, .blob_key_bit_size = 11, @@ -106,40 +97,54 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .ident_start_idx = 3, .ident_nums = 1 }, - { /* class_tid: 1, , table: mac_addr_cache.rd */ + { /* class_tid: 1, , table: control.check_f1_f2_flow */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 6, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR, + .cond_start_idx = 0, + .cond_nums = 2 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP + }, + { /* class_tid: 1, , table: tunnel_cache.f1_f2_rd */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE, .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 1, + .cond_start_idx = 2, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .key_start_idx = 2, - .blob_key_bit_size = 92, - .key_bit_size = 92, - .key_num_fields = 6, + .blob_key_bit_size = 19, + .key_bit_size = 19, + .key_num_fields = 2, .ident_start_idx = 4, .ident_nums = 1 }, - { /* class_tid: 1, , table: control.0 */ + { /* class_tid: 1, , table: control.tunnel_cache_check */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 1, + .cond_start_idx = 2, .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID }, - { /* class_tid: 1, , table: l2_cntxt_tcam.0 */ + { /* class_tid: 1, , table: l2_cntxt_tcam.f1_f2_alloc_l2_cntxt */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, @@ -147,15 +152,16 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 2, + .cond_start_idx = 3, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_IDENT, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, - .key_start_idx = 8, + .key_start_idx = 4, .blob_key_bit_size = 213, .key_bit_size = 213, .key_num_fields = 21, @@ -165,1054 +171,708 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .ident_start_idx = 5, .ident_nums = 1 }, - { /* class_tid: 1, , table: mac_addr_cache.wr */ + { /* class_tid: 1, , table: tunnel_cache.f1_f2_wr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE, .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 2, + .cond_start_idx = 3, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 29, - .blob_key_bit_size = 92, - .key_bit_size = 92, - .key_num_fields = 6, + .key_start_idx = 25, + .blob_key_bit_size = 19, + .key_bit_size = 19, + .key_num_fields = 2, .result_start_idx = 6, - .result_bit_size = 62, - .result_num_fields = 4 + .result_bit_size = 52, + .result_num_fields = 3 }, - { /* class_tid: 1, , table: control.ipv6_check */ + { /* class_tid: 1, , table: control.check_f2_flow */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, .direction = TF_DIR_RX, .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 8, + .cond_true_goto = 7, + .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 2, + .cond_start_idx = 3, .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP }, - { /* class_tid: 1, , table: profile_tcam_cache.ipv6_rd */ + { /* class_tid: 1, , table: mac_addr_cache.rd */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE, .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, - .cond_false_goto = 1023, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 3, - .cond_nums = 1 }, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 4, + .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, - .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 35, - .blob_key_bit_size = 15, - .key_bit_size = 15, - .key_num_fields = 3, + .key_start_idx = 27, + .blob_key_bit_size = 110, + .key_bit_size = 110, + .key_num_fields = 8, .ident_start_idx = 6, - .ident_nums = 4 + .ident_nums = 1 }, - { /* class_tid: 1, , table: control.ipv6_prof_cache_check */ + { /* class_tid: 1, , table: control.mac_addr_cache_miss */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, .direction = TF_DIR_RX, .execute_info = { - .cond_true_goto = 2, - .cond_false_goto = 1, + .cond_true_goto = 1, + .cond_false_goto = 5, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 4, + .cond_start_idx = 12, .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID }, - { /* class_tid: 1, , table: control.v6_conflict_check */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 4, - .cond_false_goto = 1023, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 5, - .cond_nums = 1 }, - .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, - .func_info = { - .func_opc = BNXT_ULP_FUNC_OPC_EQ, - .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE, - .func_opr1 = BNXT_ULP_RF_IDX_FLOW_SIG_ID, - .func_src2 = BNXT_ULP_FUNC_SRC_COMP_FIELD, - .func_opr2 = BNXT_ULP_CF_IDX_FLOW_SIG_ID, - .func_dst_opr = BNXT_ULP_RF_IDX_CC } - }, - { /* class_tid: 1, , table: fkb_select.l2_l3_l4_v6_em */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_EM_FKB, + { /* class_tid: 1, , table: l2_cntxt_tcam.allocate_l2_context */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 6, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_EM_KEY_ID_0, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 13, + .cond_nums = 2 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_IDENT, + .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, - .result_start_idx = 10, - .result_bit_size = 106, - .result_num_fields = 106 + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, + .key_start_idx = 35, + .blob_key_bit_size = 213, + .key_bit_size = 213, + .key_num_fields = 21, + .result_start_idx = 9, + .result_bit_size = 43, + .result_num_fields = 6, + .ident_start_idx = 7, + .ident_nums = 1 }, - { /* class_tid: 1, , table: profile_tcam.l2_l3_l4_v6_em */ + { /* class_tid: 1, , table: l2_cntxt_tcam.ingress_entry */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, - .cond_false_goto = 1023, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 6, - .cond_nums = 1 }, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 15, + .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, + .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 38, - .blob_key_bit_size = 94, - .key_bit_size = 94, - .key_num_fields = 43, - .result_start_idx = 116, - .result_bit_size = 33, - .result_num_fields = 8, - .ident_start_idx = 10, - .ident_nums = 1 + .key_start_idx = 56, + .blob_key_bit_size = 213, + .key_bit_size = 213, + .key_num_fields = 21, + .result_start_idx = 15, + .result_bit_size = 43, + .result_num_fields = 6, + .ident_start_idx = 8, + .ident_nums = 0 }, - { /* class_tid: 1, , table: profile_tcam_cache.l2_l3_l4_v6_wr */ + { /* class_tid: 1, , table: mac_addr_cache.wr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE, .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 7, + .cond_start_idx = 25, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, - .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 81, - .blob_key_bit_size = 15, - .key_bit_size = 15, - .key_num_fields = 3, - .result_start_idx = 124, - .result_bit_size = 138, - .result_num_fields = 7 + .key_start_idx = 77, + .blob_key_bit_size = 110, + .key_bit_size = 110, + .key_num_fields = 8, + .result_start_idx = 21, + .result_bit_size = 70, + .result_num_fields = 5 }, - { /* class_tid: 1, , table: em.l2_l3_l4_v6.0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, - .resource_type = TF_MEM_INTERNAL, + { /* class_tid: 1, , table: control.check_f1_flow */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 0, .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 7, - .cond_nums = 0 }, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .key_start_idx = 84, - .blob_key_bit_size = 0, - .key_bit_size = 0, - .key_num_fields = 114, - .result_start_idx = 131, - .result_bit_size = 0, - .result_num_fields = 6 + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 33, + .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP }, - { /* class_tid: 1, , table: profile_tcam_cache.rd */ + { /* class_tid: 1, , table: proto_header_cache.rd */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROTO_HEADER, .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 7, + .cond_start_idx = 34, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, - .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 198, - .blob_key_bit_size = 15, - .key_bit_size = 15, + .key_start_idx = 85, + .blob_key_bit_size = 73, + .key_bit_size = 73, .key_num_fields = 3, - .ident_start_idx = 11, - .ident_nums = 2 + .ident_start_idx = 8, + .ident_nums = 5 }, - { /* class_tid: 1, , table: control.gen_tbl_miss */ + { /* class_tid: 1, , table: control.proto_header_cache_miss */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, - .cond_false_goto = 6, + .cond_false_goto = 9, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 7, + .cond_start_idx = 34, .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID }, - { /* class_tid: 1, , table: fkb_select.l3_l4_wm */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_WC_FKB, + { /* class_tid: 1, , table: hdr_overlap_cache.overlap_check */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_HDR_OVERLAP, .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 35, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_SEARCH_OVERLAP, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_SEQ, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .key_start_idx = 88, + .blob_key_bit_size = 9, + .key_bit_size = 9, + .key_num_fields = 2, + .result_start_idx = 26, + .result_bit_size = 96, + .result_num_fields = 2 + }, + { /* class_tid: 1, , table: control.overlap_miss */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .false_message = "rejected due to overlapping flow", + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 8, + .cond_start_idx = 35, .cond_nums = 1 }, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, - .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0, - .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, - .result_start_idx = 137, - .result_bit_size = 106, - .result_num_fields = 106 + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID_1 + }, + { /* class_tid: 1, , table: hdr_overlap_cache.overlap_wr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_HDR_OVERLAP, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 36, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_SIMPLE_WRITE, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_SEQ, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .key_start_idx = 90, + .blob_key_bit_size = 9, + .key_bit_size = 9, + .key_num_fields = 2, + .result_start_idx = 28, + .result_bit_size = 96, + .result_num_fields = 2 }, - { /* class_tid: 1, , table: fkb_select.l3_l4_wm_vxlan */ + { /* class_tid: 1, , table: fkb_select.wc_gen_template */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_WC_FKB, .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 9, - .cond_nums = 1 }, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, - .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2, - .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, - .result_start_idx = 243, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 36, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_WC_KEY_ID_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .result_start_idx = 30, .result_bit_size = 106, .result_num_fields = 106 }, - { /* class_tid: 1, , table: profile_tcam.l3_l4.ip */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + { /* class_tid: 1, , table: wm_key_recipe.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_KEY_RECIPE_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_KEY_RECIPE_TABLE_WM, .direction = TF_DIR_RX, .execute_info = { - .cond_true_goto = 2, + .cond_true_goto = 1, .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 10, - .cond_nums = 2 }, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 235, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_KEY_RECIPE_TBL_OPC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_WC_KEY_ID_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 201, - .blob_key_bit_size = 94, - .key_bit_size = 94, - .key_num_fields = 43, - .result_start_idx = 349, - .result_bit_size = 33, - .result_num_fields = 8, - .ident_start_idx = 13, - .ident_nums = 0 + .key_start_idx = 92, + .blob_key_bit_size = 0, + .key_bit_size = 0, + .key_num_fields = 33, + .result_start_idx = 136, + .result_bit_size = 0, + .result_num_fields = 0 + }, + { /* class_tid: 1, , table: fkb_select.em_gen_template_alloc */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_EM_FKB, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 633, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_EM_KEY_ID_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .result_start_idx = 136, + .result_bit_size = 106, + .result_num_fields = 106 }, - { /* class_tid: 1, , table: profile_tcam.l3_l4.vxlan */ + { /* class_tid: 1, , table: profile_tcam.gen_template */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 12, - .cond_nums = 1 }, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 633, + .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 244, + .key_start_idx = 125, .blob_key_bit_size = 94, .key_bit_size = 94, .key_num_fields = 43, - .result_start_idx = 357, + .result_start_idx = 242, .result_bit_size = 33, .result_num_fields = 8, .ident_start_idx = 13, - .ident_nums = 0 + .ident_nums = 2 }, - { /* class_tid: 1, , table: profile_tcam_cache.wr */ + { /* class_tid: 1, , table: proto_header_cache.wr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROTO_HEADER, .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 13, + .cond_start_idx = 892, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, - .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 287, - .blob_key_bit_size = 15, - .key_bit_size = 15, + .key_start_idx = 168, + .blob_key_bit_size = 73, + .key_bit_size = 73, .key_num_fields = 3, - .result_start_idx = 365, - .result_bit_size = 138, - .result_num_fields = 7 + .result_start_idx = 250, + .result_bit_size = 74, + .result_num_fields = 6 }, - { /* class_tid: 1, , table: wm.l3_l4.ipv4 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + { /* class_tid: 1, , table: em_flow_conflict_cache.rd */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_EM_FLOW_CONFLICT, .direction = TF_DIR_RX, .execute_info = { - .cond_true_goto = 0, - .cond_false_goto = 1, + .cond_true_goto = 1, + .cond_false_goto = 7, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 13, - .cond_nums = 3 }, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, + .cond_start_idx = 892, + .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .key_start_idx = 290, - .blob_key_bit_size = 0, - .key_bit_size = 0, - .key_num_fields = 114, - .result_start_idx = 372, - .result_bit_size = 38, - .result_num_fields = 5 + .key_start_idx = 171, + .blob_key_bit_size = 73, + .key_bit_size = 73, + .key_num_fields = 3, + .ident_start_idx = 15, + .ident_nums = 1 }, - { /* class_tid: 1, , table: wm.l3_l4.ipv6 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + { /* class_tid: 1, , table: control.em_flow_conflict_cache_miss */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, .direction = TF_DIR_RX, .execute_info = { - .cond_true_goto = 0, - .cond_false_goto = 1, + .cond_true_goto = 1, + .cond_false_goto = 4, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 16, - .cond_nums = 3 }, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .key_start_idx = 404, - .blob_key_bit_size = 0, - .key_bit_size = 0, - .key_num_fields = 114, - .result_start_idx = 377, - .result_bit_size = 38, - .result_num_fields = 5 + .cond_start_idx = 893, + .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID }, - { /* class_tid: 1, , table: wm.l3.ipv4 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + { /* class_tid: 1, , table: fkb_select.em_gen_template */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_EM_FKB, .direction = TF_DIR_RX, .execute_info = { - .cond_true_goto = 0, + .cond_true_goto = 1, .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 19, - .cond_nums = 2 }, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .key_start_idx = 518, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 894, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_EM_KEY_ID_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .result_start_idx = 256, + .result_bit_size = 106, + .result_num_fields = 106 + }, + { /* class_tid: 1, , table: em_key_recipe.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_KEY_RECIPE_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_KEY_RECIPE_TABLE_EM, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 1096, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_KEY_RECIPE_TBL_OPC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_EM_KEY_ID_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .key_start_idx = 174, .blob_key_bit_size = 0, .key_bit_size = 0, - .key_num_fields = 114, - .result_start_idx = 382, - .result_bit_size = 38, - .result_num_fields = 5 + .key_num_fields = 33, + .result_start_idx = 362, + .result_bit_size = 0, + .result_num_fields = 0 }, - { /* class_tid: 1, , table: wm.l3.ipv6 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + { /* class_tid: 1, , table: em_flow_conflict_cache.wr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_EM_FLOW_CONFLICT, .direction = TF_DIR_RX, .execute_info = { - .cond_true_goto = 0, + .cond_true_goto = 2, .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 21, - .cond_nums = 2 }, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 1500, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .key_start_idx = 632, - .blob_key_bit_size = 0, - .key_bit_size = 0, - .key_num_fields = 114, - .result_start_idx = 387, - .result_bit_size = 38, - .result_num_fields = 5 + .key_start_idx = 207, + .blob_key_bit_size = 73, + .key_bit_size = 73, + .key_num_fields = 3, + .result_start_idx = 362, + .result_bit_size = 96, + .result_num_fields = 2 }, - { /* class_tid: 1, , table: wm.l2 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + { /* class_tid: 1, , table: control.field_sig_validation */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, .direction = TF_DIR_RX, .execute_info = { - .cond_true_goto = 0, + .cond_true_goto = 1023, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 23, - .cond_nums = 1 }, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .key_start_idx = 746, - .blob_key_bit_size = 0, - .key_bit_size = 0, - .key_num_fields = 114, - .result_start_idx = 392, - .result_bit_size = 38, - .result_num_fields = 5 + .cond_start_idx = 1500, + .cond_nums = 2 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .func_info = { + .func_opc = BNXT_ULP_FUNC_OPC_EQ, + .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE, + .func_opr1 = BNXT_ULP_RF_IDX_FLOW_SIG_ID, + .func_src2 = BNXT_ULP_FUNC_SRC_COMP_FIELD, + .func_opr2 = BNXT_ULP_CF_IDX_FLOW_SIG_ID, + .func_dst_opr = BNXT_ULP_RF_IDX_CC } }, - { /* class_tid: 1, , table: wm.l3_l4.vxlan.ipv4 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + { /* class_tid: 1, , table: em.ingress_generic_template */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_MEM_INTERNAL, .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 24, - .cond_nums = 2 }, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, + .cond_start_idx = 1502, + .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_DYN_KEY, + .key_recipe_operand = BNXT_ULP_RF_IDX_EM_KEY_ID_0, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .key_start_idx = 860, - .blob_key_bit_size = 0, - .key_bit_size = 0, - .key_num_fields = 114, - .result_start_idx = 397, - .result_bit_size = 38, - .result_num_fields = 5 + .result_start_idx = 364, + .result_bit_size = 0, + .result_num_fields = 6 }, - { /* class_tid: 1, , table: wm.l3_l4.vxlan.ipv6 */ + { /* class_tid: 1, , table: wm.ingress_generic_template */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 0, - .cond_false_goto = 1023, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 26, - .cond_nums = 2 }, + .cond_false_goto = 0, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 1503, + .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_DYN_KEY, + .key_recipe_operand = BNXT_ULP_RF_IDX_WC_KEY_ID_0, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .key_start_idx = 974, - .blob_key_bit_size = 0, - .key_bit_size = 0, - .key_num_fields = 114, - .result_start_idx = 402, + .result_start_idx = 370, .result_bit_size = 38, .result_num_fields = 5 }, - { /* class_tid: 2, , table: port_table.rd */ + { /* class_tid: 2, , table: l2_cntxt_tcam_cache.rd */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE, - .direction = TF_DIR_RX, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, + .direction = TF_DIR_TX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 28, + .cond_start_idx = 1503, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, - .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, - .key_start_idx = 1088, - .blob_key_bit_size = 10, - .key_bit_size = 10, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .key_start_idx = 210, + .blob_key_bit_size = 11, + .key_bit_size = 11, .key_num_fields = 1, - .ident_start_idx = 13, - .ident_nums = 3 + .ident_start_idx = 16, + .ident_nums = 2 + }, + { /* class_tid: 2, , table: control.ipv6_wc_check */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1023, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 1503, + .cond_nums = 2 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP }, - { /* class_tid: 2, , table: tunnel_cache.rd */ + { /* class_tid: 2, , table: proto_header_cache.rd */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE, - .direction = TF_DIR_RX, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROTO_HEADER, + .direction = TF_DIR_TX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 28, + .cond_start_idx = 1505, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 1089, - .blob_key_bit_size = 19, - .key_bit_size = 19, - .key_num_fields = 2, - .ident_start_idx = 16, - .ident_nums = 1 + .key_start_idx = 211, + .blob_key_bit_size = 73, + .key_bit_size = 73, + .key_num_fields = 3, + .ident_start_idx = 18, + .ident_nums = 5 }, - { /* class_tid: 2, , table: control.tunnel_cache_check */ + { /* class_tid: 2, , table: control.proto_header_cache_miss */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, - .direction = TF_DIR_RX, + .direction = TF_DIR_TX, .execute_info = { .cond_true_goto = 1, - .cond_false_goto = 3, + .cond_false_goto = 9, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 28, + .cond_start_idx = 1505, .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID }, - { /* class_tid: 2, , table: l2_cntxt_tcam.1 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 29, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_IDENT, - .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, - .fdb_operand = BNXT_ULP_RF_IDX_RID, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 1091, - .blob_key_bit_size = 213, - .key_bit_size = 213, - .key_num_fields = 21, - .result_start_idx = 407, - .result_bit_size = 43, - .result_num_fields = 6, - .ident_start_idx = 17, - .ident_nums = 1 - }, - { /* class_tid: 2, , table: tunnel_cache.wr */ + { /* class_tid: 2, , table: hdr_overlap_cache.overlap_check */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE, - .direction = TF_DIR_RX, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_HDR_OVERLAP, + .direction = TF_DIR_TX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 29, + .cond_start_idx = 1506, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, - .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 1112, - .blob_key_bit_size = 19, - .key_bit_size = 19, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_SEARCH_OVERLAP, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_SEQ, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .key_start_idx = 214, + .blob_key_bit_size = 9, + .key_bit_size = 9, .key_num_fields = 2, - .result_start_idx = 413, - .result_bit_size = 52, - .result_num_fields = 3 + .result_start_idx = 375, + .result_bit_size = 96, + .result_num_fields = 2 }, - { /* class_tid: 2, , table: control.flow_type_check */ + { /* class_tid: 2, , table: control.overlap_miss */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, - .direction = TF_DIR_RX, + .direction = TF_DIR_TX, .execute_info = { .cond_true_goto = 1, - .cond_false_goto = 5, + .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 29, + .cond_start_idx = 1506, .cond_nums = 1 }, - .fdb_opcode = BNXT_ULP_FDB_OPC_NOP + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID_1 }, - { /* class_tid: 2, , table: mac_addr_cache.rd */ + { /* class_tid: 2, , table: hdr_overlap_cache.overlap_wr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE, - .direction = TF_DIR_RX, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_HDR_OVERLAP, + .direction = TF_DIR_TX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 30, + .cond_start_idx = 1507, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, - .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 1114, - .blob_key_bit_size = 92, - .key_bit_size = 92, - .key_num_fields = 6, - .ident_start_idx = 18, - .ident_nums = 1 + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_SIMPLE_WRITE, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_SEQ, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .key_start_idx = 216, + .blob_key_bit_size = 9, + .key_bit_size = 9, + .key_num_fields = 2, + .result_start_idx = 377, + .result_bit_size = 96, + .result_num_fields = 2 }, - { /* class_tid: 2, , table: control.mac_addr_cache_check */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 0, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 30, - .cond_nums = 1 }, - .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, - .fdb_operand = BNXT_ULP_RF_IDX_RID - }, - { /* class_tid: 2, , table: l2_cntxt_tcam.0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 31, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, - .fdb_operand = BNXT_ULP_RF_IDX_RID, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 1120, - .blob_key_bit_size = 213, - .key_bit_size = 213, - .key_num_fields = 21, - .result_start_idx = 416, - .result_bit_size = 43, - .result_num_fields = 6, - .ident_start_idx = 19, - .ident_nums = 0 - }, - { /* class_tid: 2, , table: mac_addr_cache.wr */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 0, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 31, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, - .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 1141, - .blob_key_bit_size = 92, - .key_bit_size = 92, - .key_num_fields = 6, - .result_start_idx = 422, - .result_bit_size = 62, - .result_num_fields = 4 - }, - { /* class_tid: 2, , table: control.ipv6_check */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 8, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 31, - .cond_nums = 1 }, - .fdb_opcode = BNXT_ULP_FDB_OPC_NOP - }, - { /* class_tid: 2, , table: profile_tcam_cache.f2_ipv6_rd */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 1023, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 32, - .cond_nums = 1 }, - .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, - .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 1147, - .blob_key_bit_size = 15, - .key_bit_size = 15, - .key_num_fields = 3, - .ident_start_idx = 19, - .ident_nums = 4 - }, - { /* class_tid: 2, , table: control.f2_ipv6_prof_cache_check */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 2, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 33, - .cond_nums = 1 }, - .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, - .fdb_operand = BNXT_ULP_RF_IDX_RID - }, - { /* class_tid: 2, , table: control.f2_v6_conflict_check */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 4, - .cond_false_goto = 1023, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 34, - .cond_nums = 1 }, - .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, - .func_info = { - .func_opc = BNXT_ULP_FUNC_OPC_EQ, - .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE, - .func_opr1 = BNXT_ULP_RF_IDX_FLOW_SIG_ID, - .func_src2 = BNXT_ULP_FUNC_SRC_COMP_FIELD, - .func_opr2 = BNXT_ULP_CF_IDX_FLOW_SIG_ID, - .func_dst_opr = BNXT_ULP_RF_IDX_CC } - }, - { /* class_tid: 2, , table: fkb_select.f2_l2_l3_l4_v6_em */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_EM_FKB, - .direction = TF_DIR_RX, + { /* class_tid: 2, , table: fkb_select.wc_gen_template */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_WC_FKB, + .direction = TF_DIR_TX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 35, + .cond_start_idx = 1507, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_EM_KEY_ID_0, + .tbl_operand = BNXT_ULP_RF_IDX_WC_KEY_ID_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, - .result_start_idx = 426, + .result_start_idx = 379, .result_bit_size = 106, .result_num_fields = 106 }, - { /* class_tid: 2, , table: profile_tcam.f2_l2_l3_l4_v6_em */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 35, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, - .fdb_operand = BNXT_ULP_RF_IDX_RID, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 1150, - .blob_key_bit_size = 94, - .key_bit_size = 94, - .key_num_fields = 43, - .result_start_idx = 532, - .result_bit_size = 33, - .result_num_fields = 8, - .ident_start_idx = 23, - .ident_nums = 1 - }, - { /* class_tid: 2, , table: profile_tcam_cache.f2_l2_l3_l4_v6_wr */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 35, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, - .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 1193, - .blob_key_bit_size = 15, - .key_bit_size = 15, - .key_num_fields = 3, - .result_start_idx = 540, - .result_bit_size = 138, - .result_num_fields = 7 - }, - { /* class_tid: 2, , table: em.f2_l2_l3_l4_v6.0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, - .resource_type = TF_MEM_INTERNAL, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 0, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 35, - .cond_nums = 0 }, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .key_start_idx = 1196, - .blob_key_bit_size = 0, - .key_bit_size = 0, - .key_num_fields = 114, - .result_start_idx = 547, - .result_bit_size = 0, - .result_num_fields = 6 - }, - { /* class_tid: 2, , table: profile_tcam_cache.f2_rd */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + { /* class_tid: 2, , table: wm_key_recipe.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_KEY_RECIPE_TABLE, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 35, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, - .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 1310, - .blob_key_bit_size = 15, - .key_bit_size = 15, - .key_num_fields = 3, - .ident_start_idx = 24, - .ident_nums = 3 - }, - { /* class_tid: 2, , table: control.profile_tcam_cache.f2_check */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 4, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 35, - .cond_nums = 1 }, - .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, - .fdb_operand = BNXT_ULP_RF_IDX_RID - }, - { /* class_tid: 2, , table: fkb_select.f2_wm */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_WC_FKB, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 36, - .cond_nums = 1 }, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, - .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4, - .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, - .result_start_idx = 553, - .result_bit_size = 106, - .result_num_fields = 106 - }, - { /* class_tid: 2, , table: profile_tcam.f2 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .direction = TF_DIR_RX, + BNXT_ULP_RESOURCE_SUB_TYPE_KEY_RECIPE_TABLE_WM, + .direction = TF_DIR_TX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 37, + .cond_start_idx = 1706, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, + .tbl_opcode = BNXT_ULP_KEY_RECIPE_TBL_OPC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_WC_KEY_ID_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 1, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 1313, - .blob_key_bit_size = 94, - .key_bit_size = 94, - .key_num_fields = 43, - .result_start_idx = 659, - .result_bit_size = 33, - .result_num_fields = 8 - }, - { /* class_tid: 2, , table: profile_tcam_cache.f2_wr */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 37, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, - .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 1356, - .blob_key_bit_size = 15, - .key_bit_size = 15, - .key_num_fields = 3, - .result_start_idx = 667, - .result_bit_size = 138, - .result_num_fields = 7 - }, - { /* class_tid: 2, , table: wm.l3_l4.ipv4 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 0, - .cond_false_goto = 0, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 37, - .cond_nums = 1 }, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .key_start_idx = 1359, + .key_start_idx = 218, .blob_key_bit_size = 0, .key_bit_size = 0, - .key_num_fields = 114, - .result_start_idx = 674, - .result_bit_size = 38, - .result_num_fields = 5 - }, - { /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, - .direction = TF_DIR_TX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 38, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, - .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 1473, - .blob_key_bit_size = 11, - .key_bit_size = 11, - .key_num_fields = 1, - .ident_start_idx = 27, - .ident_nums = 1 - }, - { /* class_tid: 3, , table: control.ipv6_check */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, - .direction = TF_DIR_TX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 8, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 38, - .cond_nums = 1 }, - .fdb_opcode = BNXT_ULP_FDB_OPC_NOP - }, - { /* class_tid: 3, , table: profile_tcam_cache.ipv6_rd */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_TX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 1023, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 39, - .cond_nums = 1 }, - .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, - .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 1474, - .blob_key_bit_size = 15, - .key_bit_size = 15, - .key_num_fields = 3, - .ident_start_idx = 28, - .ident_nums = 4 - }, - { /* class_tid: 3, , table: control.ipv6_prof_cache_check */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, - .direction = TF_DIR_TX, - .execute_info = { - .cond_true_goto = 2, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 40, - .cond_nums = 1 }, - .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, - .fdb_operand = BNXT_ULP_RF_IDX_RID - }, - { /* class_tid: 3, , table: control.v6_conflict_check */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, - .direction = TF_DIR_TX, - .execute_info = { - .cond_true_goto = 4, - .cond_false_goto = 1023, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 41, - .cond_nums = 1 }, - .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, - .func_info = { - .func_opc = BNXT_ULP_FUNC_OPC_EQ, - .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE, - .func_opr1 = BNXT_ULP_RF_IDX_FLOW_SIG_ID, - .func_src2 = BNXT_ULP_FUNC_SRC_COMP_FIELD, - .func_opr2 = BNXT_ULP_CF_IDX_FLOW_SIG_ID, - .func_dst_opr = BNXT_ULP_RF_IDX_CC } + .key_num_fields = 33, + .result_start_idx = 485, + .result_bit_size = 0, + .result_num_fields = 0 }, - { /* class_tid: 3, , table: fkb_select.l2_l3_l4_v6_em */ + { /* class_tid: 2, , table: fkb_select.em_gen_template_alloc */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_EM_FKB, .direction = TF_DIR_TX, @@ -1220,17 +880,18 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 42, + .cond_start_idx = 2104, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_EM_KEY_ID_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, - .result_start_idx = 679, + .result_start_idx = 485, .result_bit_size = 106, .result_num_fields = 106 }, - { /* class_tid: 3, , table: profile_tcam.l2_l3_l4_v6_em */ + { /* class_tid: 2, , table: profile_tcam.gen_template */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_TX, @@ -1238,249 +899,188 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 42, + .cond_start_idx = 2104, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 1477, + .key_start_idx = 251, .blob_key_bit_size = 94, .key_bit_size = 94, .key_num_fields = 43, - .result_start_idx = 785, + .result_start_idx = 591, .result_bit_size = 33, .result_num_fields = 8, - .ident_start_idx = 32, - .ident_nums = 1 + .ident_start_idx = 23, + .ident_nums = 2 }, - { /* class_tid: 3, , table: profile_tcam_cache.l2_l3_l4_v6_wr */ + { /* class_tid: 2, , table: proto_header_cache.wr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROTO_HEADER, .direction = TF_DIR_TX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 42, + .cond_start_idx = 2353, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, - .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 1520, - .blob_key_bit_size = 15, - .key_bit_size = 15, + .key_start_idx = 294, + .blob_key_bit_size = 73, + .key_bit_size = 73, .key_num_fields = 3, - .result_start_idx = 793, - .result_bit_size = 138, - .result_num_fields = 7 - }, - { /* class_tid: 3, , table: em.l2_l3_l4_v6.0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, - .resource_type = TF_MEM_INTERNAL, - .direction = TF_DIR_TX, - .execute_info = { - .cond_true_goto = 0, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 42, - .cond_nums = 0 }, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .key_start_idx = 1523, - .blob_key_bit_size = 0, - .key_bit_size = 0, - .key_num_fields = 114, - .result_start_idx = 800, - .result_bit_size = 0, + .result_start_idx = 599, + .result_bit_size = 74, .result_num_fields = 6 }, - { /* class_tid: 3, , table: profile_tcam_cache.rd */ + { /* class_tid: 2, , table: em_flow_conflict_cache.rd */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_EM_FLOW_CONFLICT, .direction = TF_DIR_TX, .execute_info = { .cond_true_goto = 1, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 42, - .cond_nums = 0 }, + .cond_false_goto = 7, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 2353, + .cond_nums = 1 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, - .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 1637, - .blob_key_bit_size = 15, - .key_bit_size = 15, + .key_start_idx = 297, + .blob_key_bit_size = 73, + .key_bit_size = 73, .key_num_fields = 3, - .ident_start_idx = 33, - .ident_nums = 2 + .ident_start_idx = 25, + .ident_nums = 1 }, - { /* class_tid: 3, , table: control.gen_tbl_miss */ + { /* class_tid: 2, , table: control.em_flow_conflict_cache_check */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, .direction = TF_DIR_TX, .execute_info = { .cond_true_goto = 1, - .cond_false_goto = 5, + .cond_false_goto = 4, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 42, + .cond_start_idx = 2354, .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID }, - { /* class_tid: 3, , table: fkb_select.l3_l4_wc */ + { /* class_tid: 2, , table: fkb_select.em_gen_template */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_WC_FKB, + .resource_type = TF_TBL_TYPE_EM_FKB, .direction = TF_DIR_TX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 43, + .cond_start_idx = 2355, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, - .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_EM_KEY_ID_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, - .result_start_idx = 806, + .result_start_idx = 605, .result_bit_size = 106, .result_num_fields = 106 }, - { /* class_tid: 3, , table: profile_tcam.l3_l4.ip */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .direction = TF_DIR_TX, - .execute_info = { - .cond_true_goto = 2, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 43, - .cond_nums = 1 }, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, - .fdb_operand = BNXT_ULP_RF_IDX_RID, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 1640, - .blob_key_bit_size = 94, - .key_bit_size = 94, - .key_num_fields = 43, - .result_start_idx = 912, - .result_bit_size = 33, - .result_num_fields = 8, - .ident_start_idx = 35, - .ident_nums = 0 - }, - { /* class_tid: 3, , table: profile_tcam.l3_l4.nonip */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + { /* class_tid: 2, , table: em_key_recipe.0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_KEY_RECIPE_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_KEY_RECIPE_TABLE_EM, .direction = TF_DIR_TX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 44, + .cond_start_idx = 2554, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, + .tbl_opcode = BNXT_ULP_KEY_RECIPE_TBL_OPC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_EM_KEY_ID_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 1683, - .blob_key_bit_size = 94, - .key_bit_size = 94, - .key_num_fields = 43, - .result_start_idx = 920, - .result_bit_size = 33, - .result_num_fields = 8, - .ident_start_idx = 35, - .ident_nums = 0 + .key_start_idx = 300, + .blob_key_bit_size = 0, + .key_bit_size = 0, + .key_num_fields = 33, + .result_start_idx = 711, + .result_bit_size = 0, + .result_num_fields = 0 }, - { /* class_tid: 3, , table: profile_tcam_cache.wr */ + { /* class_tid: 2, , table: em_flow_conflict_cache.wr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_EM_FLOW_CONFLICT, .direction = TF_DIR_TX, .execute_info = { - .cond_true_goto = 1, + .cond_true_goto = 2, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 44, + .cond_start_idx = 2952, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, - .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 1726, - .blob_key_bit_size = 15, - .key_bit_size = 15, + .key_start_idx = 333, + .blob_key_bit_size = 73, + .key_bit_size = 73, .key_num_fields = 3, - .result_start_idx = 928, - .result_bit_size = 138, - .result_num_fields = 7 + .result_start_idx = 711, + .result_bit_size = 96, + .result_num_fields = 2 }, - { /* class_tid: 3, , table: wm.l3_l4.ipv4 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + { /* class_tid: 2, , table: control.field_sig_validation */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, .direction = TF_DIR_TX, .execute_info = { - .cond_true_goto = 0, + .cond_true_goto = 1023, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 44, + .cond_start_idx = 2952, .cond_nums = 2 }, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .key_start_idx = 1729, - .blob_key_bit_size = 0, - .key_bit_size = 0, - .key_num_fields = 114, - .result_start_idx = 935, - .result_bit_size = 38, - .result_num_fields = 5 + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .func_info = { + .func_opc = BNXT_ULP_FUNC_OPC_EQ, + .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE, + .func_opr1 = BNXT_ULP_RF_IDX_FLOW_SIG_ID, + .func_src2 = BNXT_ULP_FUNC_SRC_COMP_FIELD, + .func_opr2 = BNXT_ULP_CF_IDX_FLOW_SIG_ID, + .func_dst_opr = BNXT_ULP_RF_IDX_CC } }, - { /* class_tid: 3, , table: wm.l3.ipv4 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, + { /* class_tid: 2, , table: em.egress_generic_template */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_MEM_INTERNAL, .direction = TF_DIR_TX, .execute_info = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 46, + .cond_start_idx = 2954, .cond_nums = 1 }, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_DYN_KEY, + .key_recipe_operand = BNXT_ULP_RF_IDX_EM_KEY_ID_0, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .key_start_idx = 1843, - .blob_key_bit_size = 0, - .key_bit_size = 0, - .key_num_fields = 114, - .result_start_idx = 940, - .result_bit_size = 38, - .result_num_fields = 5 + .result_start_idx = 713, + .result_bit_size = 0, + .result_num_fields = 6 }, - { /* class_tid: 3, , table: wm.l2 */ + { /* class_tid: 2, , table: wm.egress_generic_template */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM, .direction = TF_DIR_TX, @@ -1488,24 +1088,22 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 47, + .cond_start_idx = 2955, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_WC_TCAM_INDEX_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_DYN_KEY, + .key_recipe_operand = BNXT_ULP_RF_IDX_WC_KEY_ID_0, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .key_start_idx = 1957, - .blob_key_bit_size = 0, - .key_bit_size = 0, - .key_num_fields = 114, - .result_start_idx = 945, + .result_start_idx = 719, .result_bit_size = 38, .result_num_fields = 5 }, - { /* class_tid: 4, , table: int_full_act_record.0 */ + { /* class_tid: 3, , table: int_full_act_record.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = @@ -1515,17 +1113,18 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 47, + .cond_start_idx = 2955, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 950, + .result_start_idx = 724, .result_bit_size = 128, .result_num_fields = 17 }, - { /* class_tid: 4, , table: port_table.ing_wr_0 */ + { /* class_tid: 3, , table: port_table.ing_wr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE, @@ -1534,20 +1133,21 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 47, + .cond_start_idx = 2955, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 2071, + .key_start_idx = 336, .blob_key_bit_size = 10, .key_bit_size = 10, .key_num_fields = 1, - .result_start_idx = 967, + .result_start_idx = 741, .result_bit_size = 179, .result_num_fields = 8 }, - { /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_rd */ + { /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_rd */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, @@ -1556,31 +1156,33 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 47, + .cond_start_idx = 2955, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 2072, + .key_start_idx = 337, .blob_key_bit_size = 11, .key_bit_size = 11, .key_num_fields = 1, - .ident_start_idx = 35, + .ident_start_idx = 26, .ident_nums = 0 }, - { /* class_tid: 4, , table: control.ing_0 */ + { /* class_tid: 3, , table: control.ing_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 47, + .cond_start_idx = 2955, .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID }, - { /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */ + { /* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_RX, @@ -1588,27 +1190,28 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 48, + .cond_start_idx = 2956, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 2073, + .key_start_idx = 338, .blob_key_bit_size = 213, .key_bit_size = 213, .key_num_fields = 21, - .result_start_idx = 975, + .result_start_idx = 749, .result_bit_size = 43, .result_num_fields = 6, - .ident_start_idx = 35, - .ident_nums = 1 + .ident_start_idx = 26, + .ident_nums = 2 }, - { /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */ + { /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_wr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, @@ -1617,20 +1220,21 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 48, + .cond_start_idx = 2956, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 2094, + .key_start_idx = 359, .blob_key_bit_size = 11, .key_bit_size = 11, .key_num_fields = 1, - .result_start_idx = 981, - .result_bit_size = 62, - .result_num_fields = 4 + .result_start_idx = 755, + .result_bit_size = 70, + .result_num_fields = 5 }, - { /* class_tid: 4, , table: parif_def_arec_ptr.ing_0 */ + { /* class_tid: 3, , table: parif_def_arec_ptr.ing_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, .direction = TF_DIR_RX, @@ -1638,16 +1242,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 48, + .cond_start_idx = 2956, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, - .result_start_idx = 985, + .result_start_idx = 760, .result_bit_size = 32, .result_num_fields = 1 }, - { /* class_tid: 4, , table: parif_def_err_arec_ptr.ing_0 */ + { /* class_tid: 3, , table: parif_def_err_arec_ptr.ing_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, .direction = TF_DIR_RX, @@ -1655,16 +1260,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 48, + .cond_start_idx = 2956, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, - .result_start_idx = 986, + .result_start_idx = 761, .result_bit_size = 32, .result_num_fields = 1 }, - { /* class_tid: 4, , table: int_full_act_record.egr_0 */ + { /* class_tid: 3, , table: int_full_act_record.egr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = @@ -1674,18 +1280,19 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 48, + .cond_start_idx = 2956, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 987, + .result_start_idx = 762, .result_bit_size = 128, .result_num_fields = 17, .encap_num_fields = 0 }, - { /* class_tid: 4, , table: port_table.egr_wr_0 */ + { /* class_tid: 3, , table: port_table.egr_wr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE, @@ -1694,31 +1301,33 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 48, + .cond_start_idx = 2956, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 2095, + .key_start_idx = 360, .blob_key_bit_size = 10, .key_bit_size = 10, .key_num_fields = 1, - .result_start_idx = 1004, + .result_start_idx = 779, .result_bit_size = 179, .result_num_fields = 8 }, - { /* class_tid: 4, , table: control.egr_0 */ + { /* class_tid: 3, , table: control.egr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, - .cond_false_goto = 5, + .cond_false_goto = 6, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 48, + .cond_start_idx = 2956, .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP }, - { /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_rd_vfr */ + { /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_rd_vfr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, @@ -1727,31 +1336,60 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 49, + .cond_start_idx = 2957, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 2096, + .key_start_idx = 361, .blob_key_bit_size = 11, .key_bit_size = 11, .key_num_fields = 1, - .ident_start_idx = 36, + .ident_start_idx = 28, .ident_nums = 0 }, - { /* class_tid: 4, , table: control.egr_1 */ + { /* class_tid: 3, , table: control.egr_1 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 49, + .cond_start_idx = 2957, .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID }, - { /* class_tid: 4, , table: ilt_tbl.egr_vfr */ + { /* class_tid: 3, , table: l2_cntxt_tcam.drv_func_prof_func_alloc */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 2958, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_IDENT, + .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, + .key_start_idx = 362, + .blob_key_bit_size = 213, + .key_bit_size = 213, + .key_num_fields = 21, + .result_start_idx = 787, + .result_bit_size = 43, + .result_num_fields = 6, + .ident_start_idx = 28, + .ident_nums = 1 + }, + { /* class_tid: 3, , table: ilt_tbl.egr_vfr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_ILT, .direction = TF_DIR_TX, @@ -1759,17 +1397,18 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 50, + .cond_start_idx = 2958, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_SVIF, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, - .result_start_idx = 1012, + .result_start_idx = 793, .result_bit_size = 64, .result_num_fields = 8 }, - { /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr_vfr */ + { /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_wr_vfr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, @@ -1778,20 +1417,21 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 50, + .cond_start_idx = 2958, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 2097, + .key_start_idx = 383, .blob_key_bit_size = 11, .key_bit_size = 11, .key_num_fields = 1, - .result_start_idx = 1020, - .result_bit_size = 62, - .result_num_fields = 4 + .result_start_idx = 801, + .result_bit_size = 70, + .result_num_fields = 5 }, - { /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_rd */ + { /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_rd */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, @@ -1800,31 +1440,33 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 50, + .cond_start_idx = 2958, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 2098, + .key_start_idx = 384, .blob_key_bit_size = 11, .key_bit_size = 11, .key_num_fields = 1, - .ident_start_idx = 36, + .ident_start_idx = 29, .ident_nums = 0 }, - { /* class_tid: 4, , table: control.egr_2 */ + { /* class_tid: 3, , table: control.egr_2 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 50, + .cond_start_idx = 2958, .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID }, - { /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */ + { /* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_TX, @@ -1832,25 +1474,26 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 51, + .cond_start_idx = 2959, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 2099, + .key_start_idx = 385, .blob_key_bit_size = 213, .key_bit_size = 213, .key_num_fields = 21, - .result_start_idx = 1024, + .result_start_idx = 806, .result_bit_size = 43, .result_num_fields = 6, - .ident_start_idx = 36, - .ident_nums = 1 + .ident_start_idx = 29, + .ident_nums = 2 }, - { /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr */ + { /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_wr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, @@ -1859,20 +1502,21 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 51, + .cond_start_idx = 2959, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 2120, + .key_start_idx = 406, .blob_key_bit_size = 11, .key_bit_size = 11, .key_num_fields = 1, - .result_start_idx = 1030, - .result_bit_size = 62, - .result_num_fields = 4 + .result_start_idx = 812, + .result_bit_size = 70, + .result_num_fields = 5 }, - { /* class_tid: 4, , table: parif_def_arec_ptr.egr_0 */ + { /* class_tid: 3, , table: parif_def_arec_ptr.egr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, .direction = TF_DIR_TX, @@ -1880,16 +1524,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 51, + .cond_start_idx = 2959, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .result_start_idx = 1034, + .result_start_idx = 817, .result_bit_size = 32, .result_num_fields = 1 }, - { /* class_tid: 4, , table: parif_def_err_arec_ptr.egr_0 */ + { /* class_tid: 3, , table: parif_def_err_arec_ptr.egr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, .direction = TF_DIR_TX, @@ -1897,16 +1542,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 51, + .cond_start_idx = 2959, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .result_start_idx = 1035, + .result_start_idx = 818, .result_bit_size = 32, .result_num_fields = 1 }, - { /* class_tid: 5, , table: profile_tcam_cache.vfr_glb_act_rec_rd */ + { /* class_tid: 4, , table: profile_tcam_cache.vfr_glb_act_rec_rd */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = @@ -1916,31 +1562,33 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 51, + .cond_start_idx = 2959, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 2121, + .key_start_idx = 407, .blob_key_bit_size = 15, .key_bit_size = 15, .key_num_fields = 3, - .ident_start_idx = 37, + .ident_start_idx = 31, .ident_nums = 0 }, - { /* class_tid: 5, , table: control.prof_tcam_cache.vfr_glb_act_rec_rd.0 */ + { /* class_tid: 4, , table: control.prof_tcam_cache.vfr_glb_act_rec_rd.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, .direction = TF_DIR_TX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 6, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 51, + .cond_start_idx = 2959, .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID }, - { /* class_tid: 5, , table: mod_record.vf_2_vfr_egr */ + { /* class_tid: 4, , table: mod_record.vf_2_vfr_egr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B, .resource_sub_type = @@ -1950,17 +1598,18 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 52, + .cond_start_idx = 2960, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_MODIFY_PTR, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, - .result_start_idx = 1036, + .result_start_idx = 819, .result_bit_size = 0, .result_num_fields = 0, - .encap_num_fields = 47 + .encap_num_fields = 20 }, - { /* class_tid: 5, , table: int_full_act_record.vf_2_vfr_loopback */ + { /* class_tid: 4, , table: int_full_act_record.vf_2_vfr_loopback */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = @@ -1970,18 +1619,19 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 52, + .cond_start_idx = 2960, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 1083, + .result_start_idx = 839, .result_bit_size = 128, .result_num_fields = 17, .encap_num_fields = 0 }, - { /* class_tid: 5, , table: parif_def_arec_ptr.vf_egr */ + { /* class_tid: 4, , table: parif_def_arec_ptr.vf_egr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, .direction = TF_DIR_TX, @@ -1989,17 +1639,18 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 52, + .cond_start_idx = 2960, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, .tbl_operand = ULP_THOR_SYM_LOOPBACK_PARIF, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, - .result_start_idx = 1100, + .result_start_idx = 856, .result_bit_size = 32, .result_num_fields = 1 }, - { /* class_tid: 5, , table: parif_def_err_arec_ptr.vf_egr */ + { /* class_tid: 4, , table: parif_def_err_arec_ptr.vf_egr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, .direction = TF_DIR_TX, @@ -2007,17 +1658,18 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 52, + .cond_start_idx = 2960, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, .tbl_operand = ULP_THOR_SYM_LOOPBACK_PARIF, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, - .result_start_idx = 1101, + .result_start_idx = 857, .result_bit_size = 32, .result_num_fields = 1 }, - { /* class_tid: 5, , table: profile_tcam_cache.vfr_glb_act_rec_wr */ + { /* class_tid: 4, , table: profile_tcam_cache.vfr_glb_act_rec_wr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = @@ -2027,20 +1679,21 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 52, + .cond_start_idx = 2960, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 2124, + .key_start_idx = 410, .blob_key_bit_size = 15, .key_bit_size = 15, .key_num_fields = 3, - .result_start_idx = 1102, + .result_start_idx = 858, .result_bit_size = 138, .result_num_fields = 7 }, - { /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_rd_egr */ + { /* class_tid: 4, , table: l2_cntxt_tcam_cache.vf_rd_egr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, @@ -2049,57 +1702,82 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 52, + .cond_start_idx = 2960, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 2127, + .key_start_idx = 413, .blob_key_bit_size = 11, .key_bit_size = 11, .key_num_fields = 1, - .ident_start_idx = 37, + .ident_start_idx = 31, .ident_nums = 0 }, - { /* class_tid: 5, , table: control.vf_2_vfr.0 */ + { /* class_tid: 4, , table: control.vf_2_vfr.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, .direction = TF_DIR_TX, .execute_info = { .cond_true_goto = 1, - .cond_false_goto = 3, + .cond_false_goto = 4, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 52, + .cond_start_idx = 2960, .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID }, - { /* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + { /* class_tid: 4, , table: l2_cntxt_tcam_cache.get_drv_func_prof_func */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, .direction = TF_DIR_TX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 53, + .cond_start_idx = 2961, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, - .fdb_operand = BNXT_ULP_RF_IDX_RID, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .key_start_idx = 2128, - .blob_key_bit_size = 213, - .key_bit_size = 213, - .key_num_fields = 21, - .result_start_idx = 1109, - .result_bit_size = 43, - .result_num_fields = 6, - .ident_start_idx = 37, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .key_start_idx = 414, + .blob_key_bit_size = 11, + .key_bit_size = 11, + .key_num_fields = 1, + .ident_start_idx = 31, + .ident_nums = 1 + }, + { /* class_tid: 4, , table: l2_cntxt_tcam.vf_egr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 2961, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, + .key_start_idx = 415, + .blob_key_bit_size = 213, + .key_bit_size = 213, + .key_num_fields = 21, + .result_start_idx = 865, + .result_bit_size = 43, + .result_num_fields = 6, + .ident_start_idx = 32, .ident_nums = 1 }, - { /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_egr_wr */ + { /* class_tid: 4, , table: l2_cntxt_tcam_cache.vf_egr_wr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, @@ -2108,20 +1786,21 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 53, + .cond_start_idx = 2961, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 2149, + .key_start_idx = 436, .blob_key_bit_size = 11, .key_bit_size = 11, .key_num_fields = 1, - .result_start_idx = 1115, - .result_bit_size = 62, - .result_num_fields = 4 + .result_start_idx = 871, + .result_bit_size = 70, + .result_num_fields = 5 }, - { /* class_tid: 5, , table: int_full_act_record.vf_2_vfr_ing */ + { /* class_tid: 4, , table: int_full_act_record.vf_2_vfr_ing */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = @@ -2131,17 +1810,18 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 53, + .cond_start_idx = 2961, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG, - .result_start_idx = 1119, + .result_start_idx = 876, .result_bit_size = 128, .result_num_fields = 17 }, - { /* class_tid: 5, , table: profile_tcam_cache.vfr_rd */ + { /* class_tid: 4, , table: profile_tcam_cache.vfr_rd */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = @@ -2151,31 +1831,33 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 53, + .cond_start_idx = 2961, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 2150, + .key_start_idx = 437, .blob_key_bit_size = 15, .key_bit_size = 15, .key_num_fields = 3, - .ident_start_idx = 38, + .ident_start_idx = 33, .ident_nums = 0 }, - { /* class_tid: 5, , table: control.prof_tcam_cache.vfr.0 */ + { /* class_tid: 4, , table: control.prof_tcam_cache.vfr.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, .direction = TF_DIR_TX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 10, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 53, + .cond_start_idx = 2961, .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID }, - { /* class_tid: 5, , table: int_full_act_record.drop_action */ + { /* class_tid: 4, , table: int_full_act_record.drop_action */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = @@ -2185,18 +1867,19 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 54, + .cond_start_idx = 2962, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_DROP_AREC_PTR, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 1136, + .result_start_idx = 893, .result_bit_size = 128, .result_num_fields = 17, .encap_num_fields = 0 }, - { /* class_tid: 5, , table: l2_cntxt_tcam.vf_2_vfr_ing.0 */ + { /* class_tid: 4, , table: l2_cntxt_tcam.vf_2_vfr_ing.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, @@ -2204,27 +1887,28 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 54, + .cond_start_idx = 2962, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 2153, + .key_start_idx = 440, .blob_key_bit_size = 213, .key_bit_size = 213, .key_num_fields = 21, - .result_start_idx = 1153, + .result_start_idx = 910, .result_bit_size = 43, .result_num_fields = 6, - .ident_start_idx = 38, + .ident_start_idx = 33, .ident_nums = 0 }, - { /* class_tid: 5, , table: l2_cntxt_tcam.vfr_2_vf_ing.0 */ + { /* class_tid: 4, , table: l2_cntxt_tcam.vfr_2_vf_ing.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, @@ -2232,27 +1916,28 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 54, + .cond_start_idx = 2962, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 2174, + .key_start_idx = 461, .blob_key_bit_size = 213, .key_bit_size = 213, .key_num_fields = 21, - .result_start_idx = 1159, + .result_start_idx = 916, .result_bit_size = 43, .result_num_fields = 6, - .ident_start_idx = 38, + .ident_start_idx = 33, .ident_nums = 0 }, - { /* class_tid: 5, , table: fkb_select.vfr_em */ + { /* class_tid: 4, , table: fkb_select.vfr_em */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_EM_FKB, .direction = TF_DIR_RX, @@ -2260,16 +1945,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 54, + .cond_start_idx = 2962, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, - .result_start_idx = 1165, + .result_start_idx = 922, .result_bit_size = 106, .result_num_fields = 106 }, - { /* class_tid: 5, , table: fkb_select.vf_em */ + { /* class_tid: 4, , table: fkb_select.vf_em */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_EM_FKB, .direction = TF_DIR_RX, @@ -2277,16 +1963,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 54, + .cond_start_idx = 2962, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE, .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_1, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, - .result_start_idx = 1271, + .result_start_idx = 1028, .result_bit_size = 106, .result_num_fields = 106 }, - { /* class_tid: 5, , table: profile_tcam.vf_2_vfr.0 */ + { /* class_tid: 4, , table: profile_tcam.vf_2_vfr.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, @@ -2294,25 +1981,26 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 54, + .cond_start_idx = 2962, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 2195, + .key_start_idx = 482, .blob_key_bit_size = 94, .key_bit_size = 94, .key_num_fields = 43, - .result_start_idx = 1377, + .result_start_idx = 1134, .result_bit_size = 33, .result_num_fields = 8 }, - { /* class_tid: 5, , table: profile_tcam.vfr_2_vf.0 */ + { /* class_tid: 4, , table: profile_tcam.vfr_2_vf.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_RX, @@ -2320,25 +2008,26 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 54, + .cond_start_idx = 2962, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 2238, + .key_start_idx = 525, .blob_key_bit_size = 94, .key_bit_size = 94, .key_num_fields = 43, - .result_start_idx = 1385, + .result_start_idx = 1142, .result_bit_size = 33, .result_num_fields = 8 }, - { /* class_tid: 5, , table: profile_tcam_cache.vfr_wr */ + { /* class_tid: 4, , table: profile_tcam_cache.vfr_wr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = @@ -2348,20 +2037,21 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 54, + .cond_start_idx = 2962, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 2281, + .key_start_idx = 568, .blob_key_bit_size = 15, .key_bit_size = 15, .key_num_fields = 3, - .result_start_idx = 1393, + .result_start_idx = 1150, .result_bit_size = 138, .result_num_fields = 7 }, - { /* class_tid: 5, , table: ilt_tbl.vfr_ing */ + { /* class_tid: 4, , table: ilt_tbl.vfr_ing */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_ILT, .direction = TF_DIR_RX, @@ -2369,16 +2059,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 54, + .cond_start_idx = 2962, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_SVIF, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .result_start_idx = 1400, + .result_start_idx = 1157, .result_bit_size = 64, .result_num_fields = 8 }, - { /* class_tid: 5, , table: em.vf_2_vfr.0 */ + { /* class_tid: 4, , table: em.vf_2_vfr.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_MEM_INTERNAL, .direction = TF_DIR_RX, @@ -2386,19 +2077,20 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 54, + .cond_start_idx = 2962, .cond_nums = 0 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .key_start_idx = 2284, + .key_start_idx = 571, .blob_key_bit_size = 0, .key_bit_size = 0, - .key_num_fields = 114, - .result_start_idx = 1408, + .key_num_fields = 3, + .result_start_idx = 1165, .result_bit_size = 0, .result_num_fields = 6 }, - { /* class_tid: 5, , table: l2_cntxt_tcam_cache.rd_egr0 */ + { /* class_tid: 4, , table: l2_cntxt_tcam_cache.rd_egr0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .resource_sub_type = @@ -2408,31 +2100,33 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 54, + .cond_start_idx = 2962, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 2398, + .key_start_idx = 574, .blob_key_bit_size = 11, .key_bit_size = 11, .key_num_fields = 1, - .ident_start_idx = 38, + .ident_start_idx = 33, .ident_nums = 0 }, - { /* class_tid: 5, , table: control.0 */ + { /* class_tid: 4, , table: control.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, .direction = TF_DIR_TX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 4, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 54, + .cond_start_idx = 2962, .cond_nums = 1 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID }, - { /* class_tid: 5, , table: ilt_tbl.vfr_egr */ + { /* class_tid: 4, , table: ilt_tbl.vfr_egr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_ILT, .direction = TF_DIR_TX, @@ -2440,17 +2134,18 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 55, + .cond_start_idx = 2963, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_SVIF, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, - .result_start_idx = 1414, + .result_start_idx = 1171, .result_bit_size = 64, .result_num_fields = 8 }, - { /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */ + { /* class_tid: 4, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, @@ -2459,20 +2154,21 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 55, + .cond_start_idx = 2963, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .key_start_idx = 2399, + .key_start_idx = 575, .blob_key_bit_size = 11, .key_bit_size = 11, .key_num_fields = 1, - .result_start_idx = 1422, - .result_bit_size = 62, - .result_num_fields = 4 + .result_start_idx = 1179, + .result_bit_size = 70, + .result_num_fields = 5 }, - { /* class_tid: 5, , table: ilt_tbl.vf_egr */ + { /* class_tid: 4, , table: ilt_tbl.vf_egr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_ILT, .direction = TF_DIR_TX, @@ -2480,16 +2176,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 55, + .cond_start_idx = 2963, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, .tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_SVIF, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .result_start_idx = 1426, + .result_start_idx = 1184, .result_bit_size = 64, .result_num_fields = 8 }, - { /* class_tid: 5, , table: mod_record.vfr_2_vf_egr */ + { /* class_tid: 4, , table: mod_record.vfr_2_vf_egr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B, .resource_sub_type = @@ -2499,17 +2196,18 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 55, + .cond_start_idx = 2963, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .result_start_idx = 1434, + .result_start_idx = 1192, .result_bit_size = 0, .result_num_fields = 0, - .encap_num_fields = 47 + .encap_num_fields = 20 }, - { /* class_tid: 5, , table: int_full_act_record.vfr_egr */ + { /* class_tid: 4, , table: int_full_act_record.vfr_egr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = @@ -2519,17 +2217,18 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 55, + .cond_start_idx = 2963, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 1481, + .result_start_idx = 1212, .result_bit_size = 128, .result_num_fields = 17 }, - { /* class_tid: 5, , table: int_full_act_record.vfr_2_vf.ing0 */ + { /* class_tid: 4, , table: int_full_act_record.vfr_2_vf.ing0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = @@ -2539,17 +2238,18 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 55, + .cond_start_idx = 2963, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .result_start_idx = 1498, + .result_start_idx = 1229, .result_bit_size = 128, .result_num_fields = 17 }, - { /* class_tid: 5, , table: em.vfr_2_vf.0 */ + { /* class_tid: 4, , table: em.vfr_2_vf.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_MEM_INTERNAL, .direction = TF_DIR_RX, @@ -2557,35605 +2257,34865 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .cond_true_goto = 0, .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 55, + .cond_start_idx = 2963, .cond_nums = 0 }, + .key_recipe_opcode = BNXT_ULP_KEY_RECIPE_OPC_NOP, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, - .key_start_idx = 2400, + .key_start_idx = 576, .blob_key_bit_size = 0, .key_bit_size = 0, - .key_num_fields = 114, - .result_start_idx = 1515, + .key_num_fields = 2, + .result_start_idx = 1246, .result_bit_size = 0, .result_num_fields = 6 } }; +struct bnxt_ulp_mapper_cond_list_info ulp_thor_class_cond_oper_list[] = { +}; + struct bnxt_ulp_mapper_cond_info ulp_thor_class_cond_list[] = { - /* cond_execute: class_tid: 1, l2_cntxt_tcam_cache.rd */ + /* cond_execute: class_tid: 1, control.check_f1_f2_flow:0*/ { - .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET, - .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_F1 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_F2 }, - /* cond_execute: class_tid: 1, control.0 */ + /* cond_execute: class_tid: 1, control.tunnel_cache_check:2*/ { .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, - /* cond_execute: class_tid: 1, control.ipv6_check */ + /* cond_execute: class_tid: 1, control.check_f2_flow:3*/ { .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, - .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + .cond_operand = BNXT_ULP_HDR_BIT_F2 }, - /* cond_execute: class_tid: 1, profile_tcam_cache.ipv6_rd */ + /* field_cond: class_tid: 1, mac_addr_cache.rd */ { - .cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET, - .cond_operand = BNXT_ULP_CF_IDX_WC_MATCH + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH }, - /* cond_execute: class_tid: 1, control.ipv6_prof_cache_check */ { - .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, - .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC }, - /* cond_execute: class_tid: 1, control.v6_conflict_check */ + /* field_cond: class_tid: 1, mac_addr_cache.rd */ { - .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, - .cond_operand = BNXT_ULP_RF_IDX_CC + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH }, - /* cond_execute: class_tid: 1, profile_tcam.l2_l3_l4_v6_em */ { - .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, - .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC + }, + /* field_cond: class_tid: 1, mac_addr_cache.rd */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY + }, + /* field_cond: class_tid: 1, mac_addr_cache.rd */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY + }, + /* field_cond: class_tid: 1, mac_addr_cache.rd */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_RECYCLE_CNT + }, + /* field_cond: class_tid: 1, mac_addr_cache.rd */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_METADATA }, - /* cond_execute: class_tid: 1, control.gen_tbl_miss */ + /* cond_execute: class_tid: 1, control.mac_addr_cache_miss:12*/ { .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, - /* cond_execute: class_tid: 1, fkb_select.l3_l4_wm */ + /* cond_execute: class_tid: 1, l2_cntxt_tcam.allocate_l2_context:13*/ { .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, - .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN + .cond_operand = BNXT_ULP_HDR_BIT_F1 }, - /* cond_execute: class_tid: 1, fkb_select.l3_l4_wm_vxlan */ { - .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, - .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_F2 }, - /* cond_execute: class_tid: 1, profile_tcam.l3_l4.ip */ + /* field_cond: class_tid: 1, l2_cntxt_tcam.ingress_entry */ { - .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, - .cond_operand = BNXT_ULP_CF_IDX_O_L3 + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY }, + /* field_cond: class_tid: 1, l2_cntxt_tcam.ingress_entry */ { - .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, - .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY }, - /* cond_execute: class_tid: 1, profile_tcam.l3_l4.vxlan */ + /* field_cond: class_tid: 1, l2_cntxt_tcam.ingress_entry */ { .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, - .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH }, - /* cond_execute: class_tid: 1, wm.l3_l4.ipv4 */ { - .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, - .cond_operand = BNXT_ULP_CF_IDX_O_L4 + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC }, + /* field_cond: class_tid: 1, l2_cntxt_tcam.ingress_entry */ { .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, - .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH }, { - .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, - .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC }, - /* cond_execute: class_tid: 1, wm.l3_l4.ipv6 */ + /* field_cond: class_tid: 1, l2_cntxt_tcam.ingress_entry */ { - .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, - .cond_operand = BNXT_ULP_CF_IDX_O_L4 + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_METADATA }, + /* field_cond: class_tid: 1, l2_cntxt_tcam.ingress_entry */ { - .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, - .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_METADATA }, + /* field_cond: class_tid: 1, l2_cntxt_tcam.ingress_entry */ { - .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, - .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_RECYCLE_CNT + }, + /* field_cond: class_tid: 1, l2_cntxt_tcam.ingress_entry */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_RECYCLE_CNT }, - /* cond_execute: class_tid: 1, wm.l3.ipv4 */ + /* field_cond: class_tid: 1, mac_addr_cache.wr */ { .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, - .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH }, { - .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, - .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC }, - /* cond_execute: class_tid: 1, wm.l3.ipv6 */ + /* field_cond: class_tid: 1, mac_addr_cache.wr */ { .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, - .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH }, { - .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, - .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC }, - /* cond_execute: class_tid: 1, wm.l2 */ + /* field_cond: class_tid: 1, mac_addr_cache.wr */ { - .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, - .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY }, - /* cond_execute: class_tid: 1, wm.l3_l4.vxlan.ipv4 */ + /* field_cond: class_tid: 1, mac_addr_cache.wr */ { - .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, - .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY }, + /* field_cond: class_tid: 1, mac_addr_cache.wr */ { - .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, - .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_RECYCLE_CNT }, - /* cond_execute: class_tid: 1, wm.l3_l4.vxlan.ipv6 */ + /* field_cond: class_tid: 1, mac_addr_cache.wr */ { - .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, - .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_METADATA }, + /* cond_execute: class_tid: 1, control.check_f1_flow:33*/ { .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, - .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + .cond_operand = BNXT_ULP_HDR_BIT_F1 + }, + /* cond_execute: class_tid: 1, control.proto_header_cache_miss:34*/ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, - /* cond_execute: class_tid: 2, control.tunnel_cache_check */ + /* cond_execute: class_tid: 1, control.overlap_miss:35*/ { .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, - /* cond_execute: class_tid: 2, control.flow_type_check */ + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_CNTXT_ID + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_METADATA + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_RECYCLE_CNT + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, { .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, - .cond_operand = BNXT_ULP_HDR_BIT_F1 + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH }, - /* cond_execute: class_tid: 2, control.mac_addr_cache_check */ { - .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, - .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, - /* cond_execute: class_tid: 2, control.ipv6_check */ { .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, - .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH }, - /* cond_execute: class_tid: 2, profile_tcam_cache.f2_ipv6_rd */ { - .cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET, - .cond_operand = BNXT_ULP_CF_IDX_WC_MATCH + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_SMAC }, - /* cond_execute: class_tid: 2, control.f2_ipv6_prof_cache_check */ + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ { - .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, - .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, - /* cond_execute: class_tid: 2, control.f2_v6_conflict_check */ { - .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, - .cond_operand = BNXT_ULP_RF_IDX_CC + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN }, - /* cond_execute: class_tid: 2, control.profile_tcam_cache.f2_check */ { - .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, - .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, - /* cond_execute: class_tid: 2, fkb_select.f2_wm */ { .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, - .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN }, - /* cond_execute: class_tid: 2, wm.l3_l4.ipv4 */ { .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, - .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OI_VLAN_VID + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, - /* cond_execute: class_tid: 3, control.ipv6_check */ { .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, - .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN }, - /* cond_execute: class_tid: 3, profile_tcam_cache.ipv6_rd */ { - .cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET, - .cond_operand = BNXT_ULP_CF_IDX_WC_MATCH + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN }, - /* cond_execute: class_tid: 3, control.ipv6_prof_cache_check */ { - .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, - .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID }, - /* cond_execute: class_tid: 3, control.v6_conflict_check */ + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ { - .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, - .cond_operand = BNXT_ULP_RF_IDX_CC + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY }, - /* cond_execute: class_tid: 3, control.gen_tbl_miss */ { - .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, - .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, - /* cond_execute: class_tid: 3, profile_tcam.l3_l4.ip */ { - .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, - .cond_operand = BNXT_ULP_CF_IDX_O_L3 + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH }, - /* cond_execute: class_tid: 3, wm.l3_l4.ipv4 */ { - .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, - .cond_operand = BNXT_ULP_CF_IDX_O_L4 + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_TYPE + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, - .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 + }, + { + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR + }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, - /* cond_execute: class_tid: 3, wm.l3.ipv4 */ { .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, - /* cond_execute: class_tid: 4, control.ing_0 */ { - .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, - .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR }, - /* cond_execute: class_tid: 4, control.egr_0 */ + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ { - .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, - .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, - /* cond_execute: class_tid: 4, control.egr_1 */ { - .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, - .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, - /* cond_execute: class_tid: 4, control.egr_2 */ { - .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, - .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR }, - /* cond_execute: class_tid: 5, control.prof_tcam_cache.vfr_glb_act_rec_rd.0 */ + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ { - .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, - .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, - /* cond_execute: class_tid: 5, control.vf_2_vfr.0 */ { - .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, - .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, - /* cond_execute: class_tid: 5, control.prof_tcam_cache.vfr.0 */ { - .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, - .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR }, - /* cond_execute: class_tid: 5, control.0 */ + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ { - .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, - .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS - } -}; - -struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { - /* class_tid: 1, , table: port_table.rd */ + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL + }, { - .field_info_mask = { - .description = "dev.port_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "dev.port_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, - /* class_tid: 1, , table: l2_cntxt_tcam_cache.rd */ { - .field_info_mask = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_TTL }, - /* class_tid: 1, , table: mac_addr_cache.rd */ + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tun_hdr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_TUN_HDR_TYPE_NONE} - }, - .field_info_spec = { - .description = "tun_hdr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_TUN_HDR_TYPE_NONE} - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "one_tag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "one_tag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_TTL }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "mac_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} - }, - .field_info_spec = { - .description = "mac_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID }, - /* class_tid: 1, , table: l2_cntxt_tcam.0 */ + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_ivlan_tpid_sel", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_ivlan_tpid_sel", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "l2_ovlan_tpid_sel", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_ovlan_tpid_sel", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_QOS }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "mac1_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "mac1_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "mac0_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} - }, - .field_info_spec = { - .description = "mac0_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_QOS }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "tunnel_id", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tunnel_id", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP }, { - .field_info_mask = { - .description = "llc", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "llc", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "roce", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "roce", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "metadata", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "metadata", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP }, { - .field_info_mask = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "spif", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "spif", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP }, { - .field_info_mask = { - .description = "loopback", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "loopback", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "mpass_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 2} - }, - .field_info_spec = { - .description = "mpass_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP }, { - .field_info_mask = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - .field_info_spec = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT }, - /* class_tid: 1, , table: mac_addr_cache.wr */ + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN }, { - .field_info_mask = { - .description = "tun_hdr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_TUN_HDR_TYPE_NONE} - }, - .field_info_spec = { - .description = "tun_hdr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_TUN_HDR_TYPE_NONE} - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "one_tag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "one_tag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN_GPE }, { - .field_info_mask = { - .description = "vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_T_VXLAN_GPE_VNI }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "mac_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} - }, - .field_info_spec = { - .description = "mac_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH }, - /* class_tid: 1, , table: profile_tcam_cache.ipv6_rd */ { - .field_info_mask = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_DMAC }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr3 = { - (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "hdr_sig_id", - .field_bit_size = 6, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "hdr_sig_id", - .field_bit_size = 6, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH }, - /* class_tid: 1, , table: profile_tcam.l2_l3_l4_v6_em */ { - .field_info_mask = { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "l4_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ONES, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l4_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, - .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr2 = { - ULP_THOR_SYM_L4_HDR_TYPE_TCP}, - .field_src3 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr3 = { - ULP_THOR_SYM_L4_HDR_TYPE_UDP} - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l4_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff} - }, - .field_info_spec = { - .description = "l4_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH }, { - .field_info_mask = { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff} - }, - .field_info_spec = { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_SMAC }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "ieh", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "ieh", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH }, { - .field_info_mask = { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_SMAC }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l3_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_L3_HDR_TYPE_IPV6} - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_IO_VLAN }, { - .field_info_mask = { - .description = "l3_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l3_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_II_VLAN }, { - .field_info_mask = { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_L3_HDR_VALID_YES} - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_IO_VLAN_VID }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "l2_two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN }, { - .field_info_mask = { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN }, { - .field_info_mask = { - .description = "l2_hdr_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l2_hdr_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "l2_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l2_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_L2_HDR_VALID_YES} - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_IO_VLAN }, { - .field_info_mask = { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_II_VLAN }, { - .field_info_mask = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_II_VLAN_VID }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "tun_hdr_err", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tun_hdr_err", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_IO_VLAN }, { - .field_info_mask = { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_II_VLAN }, { - .field_info_mask = { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_IO_VLAN_VID }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN }, { - .field_info_mask = { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN }, { - .field_info_mask = { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OI_VLAN_VID }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN }, { - .field_info_mask = { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN }, { - .field_info_mask = { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY }, { - .field_info_mask = { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH }, { - .field_info_mask = { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_TYPE }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY }, { - .field_info_mask = { - .description = "hrec_next", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "hrec_next", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr3 = { - (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH }, { - .field_info_mask = { - .description = "agg_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "agg_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_TYPE }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "metadata", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "metadata", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "pkt_type_0", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "pkt_type_0", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 }, { - .field_info_mask = { - .description = "pkt_type_1", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "pkt_type_1", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - .field_info_spec = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, - /* class_tid: 1, , table: profile_tcam_cache.l2_l3_l4_v6_wr */ { - .field_info_mask = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 }, { - .field_info_mask = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr3 = { - (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "hdr_sig_id", - .field_bit_size = 6, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "hdr_sig_id", - .field_bit_size = 6, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, - /* class_tid: 1, , table: em.l2_l3_l4_v6.0 */ { - .field_info_mask = { - .description = "em_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "em_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "spif", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "spif", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "lcos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "lcos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "meta", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "meta", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 }, { - .field_info_mask = { - .description = "rcyc_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "rcyc_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "loopback", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "loopback", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 }, { - .field_info_mask = { - .description = "tl2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "tl2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "tl2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "tl2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "tl2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "tl2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 }, { - .field_info_mask = { - .description = "tl2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_TTL }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "tl2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 }, { - .field_info_mask = { - .description = "tl2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_TTL }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "tl2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "tl3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_TTL }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "tl3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "tl3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_TTL }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "tl3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 }, { - .field_info_mask = { - .description = "tl3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_PROTO_ID }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "tl3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 }, { - .field_info_mask = { - .description = "tl3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_PROTO_ID }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "tl3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "tl3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "tl3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "tl3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "tl3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 }, { - .field_info_mask = { - .description = "tl3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_QOS }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "tl3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.l3err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.l3err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 }, { - .field_info_mask = { - .description = "tl4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_QOS }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "tl4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "tl4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_QOS }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "tl4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "tl4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_QOS }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "tl4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_UDP }, { - .field_info_mask = { - .description = "tuntype", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tuntype", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_UDP_SRC_PORT }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "tflags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tflags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tids", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tids", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_TCP }, { - .field_info_mask = { - .description = "tid", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tid", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_TCP_SRC_PORT }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "tctxts", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tctxts", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tctxt", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tctxt", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP }, { - .field_info_mask = { - .description = "tqos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tqos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "terr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "terr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP }, { - .field_info_mask = { - .description = "l2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "l2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_SKIP - }, - .field_info_spec = { - .description = "l2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_UDP }, { - .field_info_mask = { - .description = "l2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_UDP_DST_PORT }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "l2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_TCP }, { - .field_info_mask = { - .description = "l2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_TCP_DST_PORT }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "l2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP }, { - .field_info_mask = { - .description = "l2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT }, + /* field_cond: class_tid: 1, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "l2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff, - BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_SKIP - }, - .field_info_spec = { - .description = "l2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff, - BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP }, { - .field_info_mask = { - .description = "l2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "l2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_CNTXT_ID }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "l3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_CNTXT_ID }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "l3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_METADATA }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "l3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_SKIP - }, - .field_info_spec = { - .description = "l3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_METADATA }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "l3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_RECYCLE_CNT }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "l3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_RECYCLE_CNT }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "l3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_SKIP - }, - .field_info_spec = { - .description = "l3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH }, { - .field_info_mask = { - .description = "l3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "l3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CF, - .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH }, { - .field_info_mask = { - .description = "l3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "l3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH }, { - .field_info_mask = { - .description = "l3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_SMAC }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "l3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH }, { - .field_info_mask = { - .description = "l3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_SMAC }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "l3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN }, { - .field_info_mask = { - .description = "l3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN }, { - .field_info_mask = { - .description = "l3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "l3.l3err.ipv4", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3err.ipv4", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.l3err.ipv6", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3err.ipv6", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN }, { - .field_info_mask = { - .description = "l4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN }, { - .field_info_mask = { - .description = "l4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "l4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CF, - .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "l4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "l4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CF, - .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN }, { - .field_info_mask = { - .description = "l4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN }, { - .field_info_mask = { - .description = "l4.ack", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.ack", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OI_VLAN_VID }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "l4.win", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.win", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN }, { - .field_info_mask = { - .description = "l4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN }, { - .field_info_mask = { - .description = "l4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "l4.tsval", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.tsval", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l4.txecr", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.txecr", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN }, { - .field_info_mask = { - .description = "l4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN }, - /* class_tid: 1, , table: profile_tcam_cache.rd */ { - .field_info_mask = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OI_VLAN_VID }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr3 = { - (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "hdr_sig_id", - .field_bit_size = 6, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "hdr_sig_id", - .field_bit_size = 6, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN }, - /* class_tid: 1, , table: profile_tcam.l3_l4.ip */ { - .field_info_mask = { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN }, { - .field_info_mask = { - .description = "l4_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ONES, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l4_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, - .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr2 = { - ULP_THOR_SYM_L4_HDR_TYPE_TCP}, - .field_src3 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr3 = { - ULP_THOR_SYM_L4_HDR_TYPE_UDP} - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "l4_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ONES, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l4_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY }, { - .field_info_mask = { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ONES, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr2 = { - ULP_THOR_SYM_L4_HDR_VALID_YES}, - .field_src3 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr3 = { - ULP_THOR_SYM_L4_HDR_VALID_IGNORE} - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "ieh", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "ieh", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH }, { - .field_info_mask = { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_TYPE }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY }, { - .field_info_mask = { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L3 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3 & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ONES, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, - .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr2 = { - ULP_THOR_SYM_L3_HDR_TYPE_IPV4}, - .field_src3 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr3 = { - ULP_THOR_SYM_L3_HDR_TYPE_IPV6} - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH }, { - .field_info_mask = { - .description = "l3_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l3_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_TYPE }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_L3_HDR_VALID_YES} - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l2_two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "l2_vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_VLAN_NO_IGNORE >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_VLAN_NO_IGNORE & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ZERO, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_HAS_VTAG >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_HAS_VTAG & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr2 = { - ULP_THOR_SYM_L2_VTAG_PRESENT_YES}, - .field_src3 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr3 = { - ULP_THOR_SYM_L2_VTAG_PRESENT_NO} - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_hdr_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l2_hdr_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "l2_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l2_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_L2_HDR_VALID_YES} - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "tun_hdr_err", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tun_hdr_err", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "hrec_next", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "hrec_next", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_TTL }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr3 = { - (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "agg_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "agg_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "metadata", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "metadata", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_TTL }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "pkt_type_0", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "pkt_type_0", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "pkt_type_1", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "pkt_type_1", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - .field_info_spec = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_TTL }, - /* class_tid: 1, , table: profile_tcam.l3_l4.vxlan */ + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l4_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l4_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "l4_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l4_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_TTL }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "ieh", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "ieh", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "l3_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "l3_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l3_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_L3_HDR_VALID_YES} - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "l2_two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "l2_vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "l2_hdr_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_hdr_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "l2_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_L3_HDR_VALID_YES} - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_QOS }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tun_hdr_err", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tun_hdr_err", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_TUN_HDR_VALID_YES} - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_QOS }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_QOS }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_TL4_HDR_VALID_YES} - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_QOS }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L3 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3 & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ONES, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, - .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr2 = { - ULP_THOR_SYM_L3_HDR_TYPE_IPV4}, - .field_src3 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr3 = { - ULP_THOR_SYM_L3_HDR_TYPE_IPV6} - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP }, { - .field_info_mask = { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_TL3_HDR_VALID_YES} - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP }, { - .field_info_mask = { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP }, { - .field_info_mask = { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_TL2_HDR_VALID_YES} - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "hrec_next", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "hrec_next", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr3 = { - (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP }, { - .field_info_mask = { - .description = "agg_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "agg_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "metadata", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "metadata", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "pkt_type_0", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "pkt_type_0", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP }, { - .field_info_mask = { - .description = "pkt_type_1", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "pkt_type_1", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - .field_info_spec = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, - /* class_tid: 1, , table: profile_tcam_cache.wr */ { - .field_info_mask = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP }, { - .field_info_mask = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr3 = { - (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "hdr_sig_id", - .field_bit_size = 6, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "hdr_sig_id", - .field_bit_size = 6, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, - /* class_tid: 1, , table: wm.l3_l4.ipv4 */ { - .field_info_mask = { - .description = "wc_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "wc_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP }, { - .field_info_mask = { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "spif", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "spif", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP }, { - .field_info_mask = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "lcos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "lcos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN }, { - .field_info_mask = { - .description = "meta", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "meta", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "rcyc_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "rcyc_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN_GPE }, { - .field_info_mask = { - .description = "loopback", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "loopback", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_T_VXLAN_GPE_VNI }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "tl2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN }, { - .field_info_mask = { - .description = "tl2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "tl2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN_GPE }, { - .field_info_mask = { - .description = "tl2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_T_VXLAN_GPE_VNI }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "tl2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH }, { - .field_info_mask = { - .description = "tl2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_DMAC }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "tl2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH }, { - .field_info_mask = { - .description = "tl2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "tl2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH }, { - .field_info_mask = { - .description = "tl2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_DMAC }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "tl2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH }, { - .field_info_mask = { - .description = "tl3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "tl3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH }, { - .field_info_mask = { - .description = "tl3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_SMAC }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "tl3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH }, { - .field_info_mask = { - .description = "tl3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_SMAC }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "tl3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH }, { - .field_info_mask = { - .description = "tl3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_SMAC }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "tl3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH }, { - .field_info_mask = { - .description = "tl3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_SMAC }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "tl3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_IO_VLAN }, { - .field_info_mask = { - .description = "tl3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_II_VLAN }, { - .field_info_mask = { - .description = "tl3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_IO_VLAN_VID }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "tl3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN }, { - .field_info_mask = { - .description = "tl3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN }, { - .field_info_mask = { - .description = "tl3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "tl3.l3err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.l3err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_IO_VLAN }, { - .field_info_mask = { - .description = "tl4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_II_VLAN }, { - .field_info_mask = { - .description = "tl4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_IO_VLAN_VID }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "tl4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN }, { - .field_info_mask = { - .description = "tl4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN }, { - .field_info_mask = { - .description = "tl4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "tl4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_IO_VLAN }, { - .field_info_mask = { - .description = "tuntype", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tuntype", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_II_VLAN }, { - .field_info_mask = { - .description = "tflags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tflags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_II_VLAN_VID }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "tids", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tids", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tid", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tid", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_IO_VLAN }, { - .field_info_mask = { - .description = "tctxts", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tctxts", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_II_VLAN }, { - .field_info_mask = { - .description = "tctxt", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tctxt", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_IO_VLAN_VID }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "tqos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tqos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "terr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "terr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN }, { - .field_info_mask = { - .description = "l2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN }, { - .field_info_mask = { - .description = "l2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OI_VLAN_VID }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "l2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN }, { - .field_info_mask = { - .description = "l2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN }, { - .field_info_mask = { - .description = "l2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "l2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_IO_VLAN }, { - .field_info_mask = { - .description = "l2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_II_VLAN }, { - .field_info_mask = { - .description = "l2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_II_VLAN_VID }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "l2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_IO_VLAN }, { - .field_info_mask = { - .description = "l2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff, - BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff, - BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_II_VLAN }, { - .field_info_mask = { - .description = "l2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_IO_VLAN_VID }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "l2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN }, { - .field_info_mask = { - .description = "l3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN }, { - .field_info_mask = { - .description = "l3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OI_VLAN_VID }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "l3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN }, { - .field_info_mask = { - .description = "l3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN }, { - .field_info_mask = { - .description = "l3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "l3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY }, { - .field_info_mask = { - .description = "l3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ONES, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CF, - .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH }, { - .field_info_mask = { - .description = "l3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_TYPE }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "l3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY }, { - .field_info_mask = { - .description = "l3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH }, { - .field_info_mask = { - .description = "l3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_TYPE }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "l3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY }, { - .field_info_mask = { - .description = "l3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH }, { - .field_info_mask = { - .description = "l3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_TYPE }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "l3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY }, { - .field_info_mask = { - .description = "l3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.l3err.ipv4", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3err.ipv4", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH }, { - .field_info_mask = { - .description = "l3.l3err.ipv6", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3err.ipv6", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_TYPE }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "l4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CF, - .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CF, - .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 }, { - .field_info_mask = { - .description = "l4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CF, - .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CF, - .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "l4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "l4.ack", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.ack", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "l4.win", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.win", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 }, { - .field_info_mask = { - .description = "l4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "l4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l4.tsval", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.tsval", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "l4.txecr", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.txecr", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "l4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, - /* class_tid: 1, , table: wm.l3_l4.ipv6 */ { - .field_info_mask = { - .description = "wc_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "wc_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 }, { - .field_info_mask = { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "spif", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "spif", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "lcos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "lcos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "meta", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "meta", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 }, { - .field_info_mask = { - .description = "rcyc_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "rcyc_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "loopback", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "loopback", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "tl2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "tl2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 }, { - .field_info_mask = { - .description = "tl2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "tl2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "tl2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "tl2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 }, { - .field_info_mask = { - .description = "tl2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "tl2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "tl2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "tl2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 }, { - .field_info_mask = { - .description = "tl3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "tl3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "tl3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "tl3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 }, { - .field_info_mask = { - .description = "tl3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "tl3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "tl3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "tl3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 }, { - .field_info_mask = { - .description = "tl3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_TTL }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "tl3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 }, { - .field_info_mask = { - .description = "tl3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_TTL }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "tl3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "tl3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_TTL }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "tl3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.l3err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.l3err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "tl4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_TTL }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "tl4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 }, { - .field_info_mask = { - .description = "tl4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_TTL }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "tl4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 }, { - .field_info_mask = { - .description = "tl4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_TTL }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "tl4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "tuntype", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tuntype", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_TTL }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "tflags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tflags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tids", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tids", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "tid", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tid", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_TTL }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "tctxts", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tctxts", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tctxt", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tctxt", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 }, { - .field_info_mask = { - .description = "tqos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tqos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_PROTO_ID }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "terr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "terr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 }, { - .field_info_mask = { - .description = "l2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_PROTO_ID }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "l2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "l2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "l2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "l2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "l2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 }, { - .field_info_mask = { - .description = "l2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_PROTO_ID }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "l2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff, - BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff, - BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 }, { - .field_info_mask = { - .description = "l2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_PROTO_ID }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "l2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "l3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "l3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "l3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "l3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 }, { - .field_info_mask = { - .description = "l3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_QOS }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "l3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ONES, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CF, - .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 }, { - .field_info_mask = { - .description = "l3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_QOS }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "l3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "l3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_QOS }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "l3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "l3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_QOS }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "l3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 }, { - .field_info_mask = { - .description = "l3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_QOS }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "l3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.l3err.ipv4", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3err.ipv4", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 }, { - .field_info_mask = { - .description = "l3.l3err.ipv6", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3err.ipv6", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_QOS }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "l4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ONES, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CF, - .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "l4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ONES, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CF, - .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_QOS }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "l4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "l4.ack", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.ack", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_QOS }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "l4.win", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.win", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_UDP }, { - .field_info_mask = { - .description = "l4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_UDP_SRC_PORT }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "l4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l4.tsval", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.tsval", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_TCP }, { - .field_info_mask = { - .description = "l4.txecr", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.txecr", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_TCP_SRC_PORT }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "l4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, - /* class_tid: 1, , table: wm.l3.ipv4 */ { - .field_info_mask = { - .description = "wc_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "wc_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP }, { - .field_info_mask = { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "spif", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "spif", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP }, { - .field_info_mask = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "lcos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "lcos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "meta", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "meta", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_UDP }, { - .field_info_mask = { - .description = "rcyc_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "rcyc_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_UDP_SRC_PORT }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "loopback", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "loopback", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_TCP }, { - .field_info_mask = { - .description = "tl2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_TCP_SRC_PORT }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "tl2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP }, { - .field_info_mask = { - .description = "tl2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "tl2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP }, { - .field_info_mask = { - .description = "tl2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "tl2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_UDP }, { - .field_info_mask = { - .description = "tl2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_UDP_DST_PORT }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "tl2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_TCP }, { - .field_info_mask = { - .description = "tl2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_TCP_DST_PORT }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "tl2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP }, { - .field_info_mask = { - .description = "tl3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "tl3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP }, { - .field_info_mask = { - .description = "tl3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "tl3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_UDP }, { - .field_info_mask = { - .description = "tl3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_UDP_DST_PORT }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "tl3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_TCP }, { - .field_info_mask = { - .description = "tl3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_TCP_DST_PORT }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "tl3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP }, { - .field_info_mask = { - .description = "tl3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT }, + /* field_cond: class_tid: 1, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "tl3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP }, { - .field_info_mask = { - .description = "tl3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "tl3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_TCP }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "tl3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "tl3.l3err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.l3err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_UDP }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "tl4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "tl4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_TCP }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "tl4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "tl4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_UDP }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "tuntype", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tuntype", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tflags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tflags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "tids", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tids", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tid", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tid", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_TCP }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "tctxts", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tctxts", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tctxt", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tctxt", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "tqos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tqos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "terr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "terr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_UDP }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "l2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "l2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_TCP }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "l2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "l2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_UDP }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "l2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "l2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_TCP }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "l2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff, - BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff, - BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "l2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_UDP }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "l3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "l3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_TCP }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "l3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "l3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ONES, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CF, - .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_UDP }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "l3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "l3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_TCP }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "l3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "l3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_UDP }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "l3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "l3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "l3.l3err.ipv4", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3err.ipv4", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.l3err.ipv6", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3err.ipv6", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "l4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "l4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "l4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l4.ack", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.ack", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "l4.win", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.win", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "l4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "l4.tsval", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.tsval", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l4.txecr", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.txecr", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "l4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, - /* class_tid: 1, , table: wm.l3.ipv6 */ { - .field_info_mask = { - .description = "wc_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "wc_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "spif", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "spif", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "lcos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "lcos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "meta", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "meta", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "rcyc_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "rcyc_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "loopback", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "loopback", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "tl2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "tl2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "tl2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "tl2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "tl2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "tl2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "tl2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "tl2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "tl3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "tl3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "tl3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "tl3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "tl3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "tl3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "tl3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "tl3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "tl3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "tl3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "tl3.l3err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.l3err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "tl4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH }, { - .field_info_mask = { - .description = "tl4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, + .cond_operand = BNXT_ULP_CF_IDX_I_TWO_VTAGS }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "tl4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH }, { - .field_info_mask = { - .description = "tl4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, + .cond_operand = BNXT_ULP_CF_IDX_O_TWO_VTAGS }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "tl4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH }, { - .field_info_mask = { - .description = "tuntype", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tuntype", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, + .cond_operand = BNXT_ULP_CF_IDX_I_TWO_VTAGS }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "tflags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tflags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tids", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tids", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH }, { - .field_info_mask = { - .description = "tid", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tid", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, + .cond_operand = BNXT_ULP_CF_IDX_O_TWO_VTAGS }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "tctxts", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tctxts", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tctxt", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tctxt", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH }, { - .field_info_mask = { - .description = "tqos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tqos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, + .cond_operand = BNXT_ULP_CF_IDX_I_HAS_VTAG }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "terr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "terr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH }, { - .field_info_mask = { - .description = "l2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, + .cond_operand = BNXT_ULP_CF_IDX_O_HAS_VTAG }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "l2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH }, { - .field_info_mask = { - .description = "l2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, + .cond_operand = BNXT_ULP_CF_IDX_I_HAS_VTAG }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "l2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH }, { - .field_info_mask = { - .description = "l2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, + .cond_operand = BNXT_ULP_CF_IDX_O_HAS_VTAG }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "l2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_DIX_TRAFFIC }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "l2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_DIX_TRAFFIC }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "l2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "l2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff, - BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff, - BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "l2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "l3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "l3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "l3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "l3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ONES, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CF, - .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "l3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN_GPE }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "l3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_GENEVE }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "l3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_GRE }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "l3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_UPAR1 }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "l3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_UPAR2 }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "l3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "l3.l3err.ipv4", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3err.ipv4", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.l3err.ipv6", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3err.ipv6", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN_GPE }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "l4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_GENEVE }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "l4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_GRE }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "l4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l4.ack", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.ack", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_UPAR1 }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "l4.win", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.win", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_UPAR2 }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "l4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "l4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "l4.tsval", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.tsval", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "l4.txecr", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.txecr", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP }, - /* class_tid: 1, , table: wm.l2 */ + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "wc_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "wc_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "spif", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "spif", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "lcos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "lcos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "meta", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "meta", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "rcyc_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "rcyc_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "loopback", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "loopback", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "tl2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "tl2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "tl2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "tl2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "tl2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "tl2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "tl2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "tl3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "tl3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "tl3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "tl3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "tl3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "tl3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "tl3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "tl3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "tl3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "tl3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "tl3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.l3err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.l3err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "tl4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "tl4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "tl4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "tl4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "tl4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tuntype", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tuntype", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH }, { - .field_info_mask = { - .description = "tflags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tflags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, + .cond_operand = BNXT_ULP_CF_IDX_O_TWO_VTAGS }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "tids", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tids", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tid", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tid", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH }, { - .field_info_mask = { - .description = "tctxts", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tctxts", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, + .cond_operand = BNXT_ULP_CF_IDX_O_TWO_VTAGS }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "tctxt", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tctxt", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tqos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tqos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH }, { - .field_info_mask = { - .description = "terr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "terr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, + .cond_operand = BNXT_ULP_CF_IDX_O_HAS_VTAG }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "l2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH }, { - .field_info_mask = { - .description = "l2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, + .cond_operand = BNXT_ULP_CF_IDX_O_HAS_VTAG }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "l2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_DIX_TRAFFIC }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "l2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_DIX_TRAFFIC }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "l2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH }, + /* field_cond: class_tid: 1, profile_tcam.gen_template */ { - .field_info_mask = { - .description = "l2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_F2 }, + /* cond_execute: class_tid: 1, em_flow_conflict_cache.rd:892*/ { - .field_info_mask = { - .description = "l2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET, + .cond_operand = BNXT_ULP_CF_IDX_WC_MATCH }, + /* cond_execute: class_tid: 1, control.em_flow_conflict_cache_miss:893*/ { - .field_info_mask = { - .description = "l2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "l2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_CNTXT_ID }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "l2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff, - BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff, - BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_METADATA }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "l2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_RECYCLE_CNT }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "l2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH }, { - .field_info_mask = { - .description = "l3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC }, { - .field_info_mask = { - .description = "l3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_EXCLUDE_FIELD_BIT_NOT_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "l3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH }, { - .field_info_mask = { - .description = "l3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_SMAC }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "l3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN }, { - .field_info_mask = { - .description = "l3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN }, { - .field_info_mask = { - .description = "l3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "l3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN }, { - .field_info_mask = { - .description = "l3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN }, { - .field_info_mask = { - .description = "l3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OI_VLAN_VID }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "l3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN }, { - .field_info_mask = { - .description = "l3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN }, { - .field_info_mask = { - .description = "l3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "l3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY }, { - .field_info_mask = { - .description = "l3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH }, { - .field_info_mask = { - .description = "l3.l3err.ipv4", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3err.ipv4", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_TYPE }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "l3.l3err.ipv6", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3err.ipv6", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "l4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "l4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "l4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "l4.ack", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.ack", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l4.win", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.win", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "l4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "l4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "l4.tsval", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.tsval", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "l4.txecr", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.txecr", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, - /* class_tid: 1, , table: wm.l3_l4.vxlan.ipv4 */ { - .field_info_mask = { - .description = "wc_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "wc_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2 & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_TTL }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "spif", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "spif", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_TTL }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "lcos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "lcos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "meta", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "meta", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "rcyc_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "rcyc_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "loopback", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "loopback", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "tl2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "tl2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "tl2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_QOS }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "tl2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "tl2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_QOS }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "tl2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP }, { - .field_info_mask = { - .description = "tl2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "tl2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP }, { - .field_info_mask = { - .description = "tl2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff, - BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff, - BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "tl2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP }, { - .field_info_mask = { - .description = "tl3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "tl3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP }, { - .field_info_mask = { - .description = "tl3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "tl3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN }, { - .field_info_mask = { - .description = "tl3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "tl3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN_GPE }, { - .field_info_mask = { - .description = "tl3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_T_VXLAN_GPE_VNI }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "tl3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ONES, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CF, - .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH }, { - .field_info_mask = { - .description = "tl3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_DMAC }, { - .field_info_mask = { - .description = "tl3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_EXCLUDE_FIELD_BIT_NOT_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_DMAC }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "tl3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH }, { - .field_info_mask = { - .description = "tl3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC }, { - .field_info_mask = { - .description = "tl3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_EXCLUDE_FIELD_BIT_NOT_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "tl3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH }, { - .field_info_mask = { - .description = "tl3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_SMAC }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "tl3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH }, { - .field_info_mask = { - .description = "tl3.l3err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.l3err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_SMAC }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "tl4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CF, - .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CF, - .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_IO_VLAN }, { - .field_info_mask = { - .description = "tl4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CF, - .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CF, - .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_II_VLAN }, { - .field_info_mask = { - .description = "tl4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_IO_VLAN_VID }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "tl4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN }, { - .field_info_mask = { - .description = "tl4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN }, { - .field_info_mask = { - .description = "tl4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "tl4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tuntype", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tuntype", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_IO_VLAN }, { - .field_info_mask = { - .description = "tflags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tflags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_II_VLAN }, { - .field_info_mask = { - .description = "tids", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tids", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_II_VLAN_VID }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "tid", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tid", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tctxts", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tctxts", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_IO_VLAN }, { - .field_info_mask = { - .description = "tctxt", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tctxt", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_II_VLAN }, { - .field_info_mask = { - .description = "tqos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tqos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_IO_VLAN_VID }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "terr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "terr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN }, { - .field_info_mask = { - .description = "l2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN }, { - .field_info_mask = { - .description = "l2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OI_VLAN_VID }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "l2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN }, { - .field_info_mask = { - .description = "l2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN }, { - .field_info_mask = { - .description = "l2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "l2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY }, { - .field_info_mask = { - .description = "l2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH }, { - .field_info_mask = { - .description = "l2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_TYPE }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "l2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY }, { - .field_info_mask = { - .description = "l2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH }, { - .field_info_mask = { - .description = "l2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_TYPE }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "l3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 }, { - .field_info_mask = { - .description = "l3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "l3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 }, { - .field_info_mask = { - .description = "l3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "l3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "l3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "l3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "l3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "l3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 }, { - .field_info_mask = { - .description = "l3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "l3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 }, { - .field_info_mask = { - .description = "l3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "l3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "l3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "l3.l3err.ipv4", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3err.ipv4", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.l3err.ipv6", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3err.ipv6", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "l4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "l4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 }, { - .field_info_mask = { - .description = "l4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_TTL }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "l4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l4.ack", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.ack", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 }, { - .field_info_mask = { - .description = "l4.win", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.win", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_TTL }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "l4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "l4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_TTL }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "l4.tsval", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.tsval", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l4.txecr", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.txecr", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "l4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_TTL }, - /* class_tid: 1, , table: wm.l3_l4.vxlan.ipv6 */ + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "wc_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "wc_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 }, { - .field_info_mask = { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_PROTO_ID }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "spif", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "spif", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 }, { - .field_info_mask = { - .description = "lcos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "lcos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_PROTO_ID }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "meta", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "meta", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "rcyc_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "rcyc_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "loopback", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "loopback", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "tl2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "tl2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "tl2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 }, { - .field_info_mask = { - .description = "tl2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_QOS }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "tl2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 }, { - .field_info_mask = { - .description = "tl2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_QOS }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "tl2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "tl2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_QOS }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "tl2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff, - BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff, - BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "tl2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_QOS }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "tl3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_UDP }, { - .field_info_mask = { - .description = "tl3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_UDP_SRC_PORT }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "tl3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_TCP }, { - .field_info_mask = { - .description = "tl3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_TCP_SRC_PORT }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "tl3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP }, { - .field_info_mask = { - .description = "tl3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ONES, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CF, - .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "tl3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP }, { - .field_info_mask = { - .description = "tl3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "tl3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_UDP }, { - .field_info_mask = { - .description = "tl3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_UDP_DST_PORT }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "tl3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_TCP }, { - .field_info_mask = { - .description = "tl3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_TCP_DST_PORT }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "tl3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP }, { - .field_info_mask = { - .description = "tl3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT }, + /* field_cond: class_tid: 1, fkb_select.em_gen_template */ { - .field_info_mask = { - .description = "tl3.l3err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.l3err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP }, { - .field_info_mask = { - .description = "tl4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CF, - .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT_MASK & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CF, - .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "tl4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CF, - .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CF, - .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_CNTXT_ID }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "tl4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_CNTXT_ID }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "tl4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_METADATA }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "tl4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_METADATA }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "tl4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_RECYCLE_CNT }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "tl4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_RECYCLE_CNT }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "tl4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tuntype", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tuntype", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH }, { - .field_info_mask = { - .description = "tflags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tflags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC }, { - .field_info_mask = { - .description = "tids", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tids", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_EXCLUDE_FIELD_BIT_NOT_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "tid", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tid", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tctxts", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tctxts", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH }, { - .field_info_mask = { - .description = "tctxt", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tctxt", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC }, { - .field_info_mask = { - .description = "tqos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tqos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_EXCLUDE_FIELD_BIT_NOT_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "terr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "terr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH }, { - .field_info_mask = { - .description = "l2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_SMAC }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "l2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH }, { - .field_info_mask = { - .description = "l2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_SMAC }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "l2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN }, { - .field_info_mask = { - .description = "l2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN }, { - .field_info_mask = { - .description = "l2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "l2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN }, { - .field_info_mask = { - .description = "l2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN }, { - .field_info_mask = { - .description = "l2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "l2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN }, { - .field_info_mask = { - .description = "l3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN }, { - .field_info_mask = { - .description = "l3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OI_VLAN_VID }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "l3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN }, { - .field_info_mask = { - .description = "l3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN }, { - .field_info_mask = { - .description = "l3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "l3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN }, { - .field_info_mask = { - .description = "l3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN }, { - .field_info_mask = { - .description = "l3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OI_VLAN_VID }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "l3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN }, { - .field_info_mask = { - .description = "l3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN }, { - .field_info_mask = { - .description = "l3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "l3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY }, { - .field_info_mask = { - .description = "l3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH }, { - .field_info_mask = { - .description = "l3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_TYPE }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "l3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY }, { - .field_info_mask = { - .description = "l3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH }, { - .field_info_mask = { - .description = "l3.l3err.ipv4", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3err.ipv4", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_TYPE }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "l3.l3err.ipv6", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3err.ipv6", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "l4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "l4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "l4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "l4.ack", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.ack", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l4.win", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.win", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "l4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "l4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "l4.tsval", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.tsval", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "l4.txecr", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.txecr", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, - /* class_tid: 2, , table: port_table.rd */ { - .field_info_mask = { - .description = "dev.port_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "dev.port_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR }, - /* class_tid: 2, , table: tunnel_cache.rd */ + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tunnel_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tunnel_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_TUNNEL_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_TUNNEL_ID & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, - /* class_tid: 2, , table: l2_cntxt_tcam.1 */ { - .field_info_mask = { - .description = "etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "l2_ivlan_tpid_sel", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_ivlan_tpid_sel", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "l2_ovlan_tpid_sel", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_ovlan_tpid_sel", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "mac1_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "mac1_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "mac0_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "mac0_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "tunnel_id", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tunnel_id", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_TTL }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_TUN_HDR_TYPE_NONE} - }, - .field_info_spec = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_TUN_HDR_TYPE_NONE} - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "llc", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "llc", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "roce", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "roce", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_TTL }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "metadata", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "metadata", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_TTL }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "spif", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "spif", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "loopback", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "loopback", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_TTL }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "mpass_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "mpass_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - .field_info_spec = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, - /* class_tid: 2, , table: tunnel_cache.wr */ { - .field_info_mask = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "tunnel_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tunnel_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_TUNNEL_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_TUNNEL_ID & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, - /* class_tid: 2, , table: mac_addr_cache.rd */ { - .field_info_mask = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "tun_hdr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tun_hdr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "one_tag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "one_tag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "mac_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} - }, - .field_info_spec = { - .description = "mac_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, - /* class_tid: 2, , table: l2_cntxt_tcam.0 */ { - .field_info_mask = { - .description = "etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "l2_ivlan_tpid_sel", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_ivlan_tpid_sel", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_ovlan_tpid_sel", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_ovlan_tpid_sel", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_QOS }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "mac1_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "mac1_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_QOS }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "mac0_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} - }, - .field_info_spec = { - .description = "mac0_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tunnel_id", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tunnel_id", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_QOS }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "llc", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "llc", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "roce", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "roce", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "metadata", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "metadata", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_QOS }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP }, { - .field_info_mask = { - .description = "spif", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "spif", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "loopback", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "loopback", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP }, { - .field_info_mask = { - .description = "mpass_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 2} - }, - .field_info_spec = { - .description = "mpass_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - .field_info_spec = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, - /* class_tid: 2, , table: mac_addr_cache.wr */ { - .field_info_mask = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP }, { - .field_info_mask = { - .description = "tun_hdr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tun_hdr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "one_tag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "one_tag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP }, { - .field_info_mask = { - .description = "mac_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} - }, - .field_info_spec = { - .description = "mac_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, - /* class_tid: 2, , table: profile_tcam_cache.f2_ipv6_rd */ { - .field_info_mask = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP }, { - .field_info_mask = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "hdr_sig_id", - .field_bit_size = 6, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "hdr_sig_id", - .field_bit_size = 6, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, - /* class_tid: 2, , table: profile_tcam.f2_l2_l3_l4_v6_em */ { - .field_info_mask = { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP }, { - .field_info_mask = { - .description = "l4_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_I_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_I_L4 & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ONES, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l4_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, - .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_I_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_I_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_I_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_I_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_I_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_I_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_I_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_I_TCP & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr2 = { - ULP_THOR_SYM_L4_HDR_TYPE_TCP}, - .field_src3 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr3 = { - ULP_THOR_SYM_L4_HDR_TYPE_UDP} - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "l4_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_I_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_I_L4 & 0xff} - }, - .field_info_spec = { - .description = "l4_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_I_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_I_L4 & 0xff} - }, - .field_info_spec = { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_I_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_I_L4 & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP }, { - .field_info_mask = { - .description = "ieh", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "ieh", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP }, { - .field_info_mask = { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "l3_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l3_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_L3_HDR_TYPE_IPV6} - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN }, { - .field_info_mask = { - .description = "l3_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l3_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_L3_HDR_VALID_YES} - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN_GPE }, { - .field_info_mask = { - .description = "l2_two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_T_VXLAN_GPE_VNI }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "l2_vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN }, { - .field_info_mask = { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "l2_hdr_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l2_hdr_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN_GPE }, { - .field_info_mask = { - .description = "l2_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l2_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_T_VXLAN_GPE_VNI }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_L2_HDR_VALID_YES} - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH }, { - .field_info_mask = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_DMAC }, { - .field_info_mask = { - .description = "tun_hdr_err", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tun_hdr_err", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_EXCLUDE_FIELD_BIT_NOT_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_DMAC }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_TUN_HDR_VALID_YES} - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH }, { - .field_info_mask = { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_TL4_HDR_TYPE_UDP} - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC }, { - .field_info_mask = { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_EXCLUDE_FIELD_BIT_NOT_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_TL4_HDR_VALID_YES} - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH }, { - .field_info_mask = { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_DMAC }, { - .field_info_mask = { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_EXCLUDE_FIELD_BIT_NOT_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_DMAC }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, - .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr2 = { - ULP_THOR_SYM_TL3_HDR_TYPE_IPV4}, - .field_src3 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr3 = { - ULP_THOR_SYM_TL3_HDR_TYPE_IPV6} - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH }, { - .field_info_mask = { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_TL3_HDR_VALID_YES} - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC }, { - .field_info_mask = { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_EXCLUDE_FIELD_BIT_NOT_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH }, { - .field_info_mask = { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_SMAC }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_TL2_HDR_VALID_YES} - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "hrec_next", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "hrec_next", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH }, { - .field_info_mask = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_SMAC }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "agg_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "agg_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "metadata", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "metadata", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH }, { - .field_info_mask = { - .description = "pkt_type_0", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "pkt_type_0", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_SMAC }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "pkt_type_1", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "pkt_type_1", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - .field_info_spec = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH }, - /* class_tid: 2, , table: profile_tcam_cache.f2_l2_l3_l4_v6_wr */ { - .field_info_mask = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_SMAC }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "hdr_sig_id", - .field_bit_size = 6, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "hdr_sig_id", - .field_bit_size = 6, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_IO_VLAN }, - /* class_tid: 2, , table: em.f2_l2_l3_l4_v6.0 */ { - .field_info_mask = { - .description = "em_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "em_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_II_VLAN }, { - .field_info_mask = { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_IO_VLAN_VID }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "spif", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "spif", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN }, { - .field_info_mask = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN }, { - .field_info_mask = { - .description = "lcos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "lcos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "meta", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "meta", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "rcyc_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "rcyc_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_IO_VLAN }, { - .field_info_mask = { - .description = "loopback", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "loopback", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_II_VLAN }, { - .field_info_mask = { - .description = "tl2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_IO_VLAN_VID }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "tl2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN }, { - .field_info_mask = { - .description = "tl2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN }, { - .field_info_mask = { - .description = "tl2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "tl2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_IO_VLAN }, { - .field_info_mask = { - .description = "tl2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_II_VLAN }, { - .field_info_mask = { - .description = "tl2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_II_VLAN_VID }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "tl2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_IO_VLAN }, { - .field_info_mask = { - .description = "tl2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_II_VLAN }, { - .field_info_mask = { - .description = "tl2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_IO_VLAN_VID }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "tl2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN }, { - .field_info_mask = { - .description = "tl3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN }, { - .field_info_mask = { - .description = "tl3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OI_VLAN_VID }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "tl3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN }, { - .field_info_mask = { - .description = "tl3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN }, { - .field_info_mask = { - .description = "tl3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "tl3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_IO_VLAN }, { - .field_info_mask = { - .description = "tl3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_II_VLAN }, { - .field_info_mask = { - .description = "tl3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_II_VLAN_VID }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "tl3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_IO_VLAN }, { - .field_info_mask = { - .description = "tl3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_II_VLAN }, { - .field_info_mask = { - .description = "tl3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_IO_VLAN_VID }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "tl3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN }, { - .field_info_mask = { - .description = "tl3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN }, { - .field_info_mask = { - .description = "tl3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OI_VLAN_VID }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "tl3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN }, { - .field_info_mask = { - .description = "tl3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN }, { - .field_info_mask = { - .description = "tl3.l3err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.l3err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "tl4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY }, { - .field_info_mask = { - .description = "tl4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH }, { - .field_info_mask = { - .description = "tl4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_TYPE }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "tl4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY }, { - .field_info_mask = { - .description = "tl4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH }, { - .field_info_mask = { - .description = "tl4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_TYPE }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "tl4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY }, { - .field_info_mask = { - .description = "tuntype", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tuntype", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tflags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tflags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH }, { - .field_info_mask = { - .description = "tids", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_SKIP - }, - .field_info_spec = { - .description = "tids", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_TYPE }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "tid", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tid", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY }, { - .field_info_mask = { - .description = "tctxts", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tctxts", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tctxt", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tctxt", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH }, { - .field_info_mask = { - .description = "tqos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tqos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_TYPE }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "terr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "terr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 }, { - .field_info_mask = { - .description = "l2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_SKIP - }, - .field_info_spec = { - .description = "l2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "l2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_SKIP - }, - .field_info_spec = { - .description = "l2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "l2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "l2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 }, { - .field_info_mask = { - .description = "l2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "l2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "l2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "l2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 }, { - .field_info_mask = { - .description = "l2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "l2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "l3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "l3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_SKIP - }, - .field_info_spec = { - .description = "l3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 }, { - .field_info_mask = { - .description = "l3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "l3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_SKIP - }, - .field_info_spec = { - .description = "l3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "l3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "l3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CF, - .field_opr2 = { - (BNXT_ULP_CF_IDX_I_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_I_L3_PROTO_ID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 }, { - .field_info_mask = { - .description = "l3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "l3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "l3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "l3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 }, { - .field_info_mask = { - .description = "l3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "l3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "l3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "l3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.l3err.ipv4", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3err.ipv4", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 }, { - .field_info_mask = { - .description = "l3.l3err.ipv6", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3err.ipv6", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "l4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "l4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CF, - .field_opr2 = { - (BNXT_ULP_CF_IDX_I_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_I_L4_SRC_PORT & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "l4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "l4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CF, - .field_opr2 = { - (BNXT_ULP_CF_IDX_I_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_I_L4_DST_PORT & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "l4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 }, { - .field_info_mask = { - .description = "l4.ack", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.ack", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "l4.win", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.win", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "l4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "l4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l4.tsval", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.tsval", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 }, { - .field_info_mask = { - .description = "l4.txecr", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.txecr", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_TTL }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "l4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, - /* class_tid: 2, , table: profile_tcam_cache.f2_rd */ { - .field_info_mask = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 }, { - .field_info_mask = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_TTL }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "hdr_sig_id", - .field_bit_size = 6, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "hdr_sig_id", - .field_bit_size = 6, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, - /* class_tid: 2, , table: profile_tcam.f2 */ { - .field_info_mask = { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "l4_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l4_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_TTL }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "l4_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l4_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "ieh", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "ieh", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_TTL }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 }, { - .field_info_mask = { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_TTL }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "l3_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l3_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l3_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 }, { - .field_info_mask = { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_L3_HDR_VALID_YES} - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_TTL }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "l2_two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_TTL }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "l2_hdr_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l2_hdr_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l2_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_L2_HDR_VALID_YES} - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_TTL }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 }, { - .field_info_mask = { - .description = "tun_hdr_err", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tun_hdr_err", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_PROTO_ID }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_TUN_HDR_VALID_YES} - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 }, { - .field_info_mask = { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_TL4_HDR_TYPE_UDP} - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_PROTO_ID }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_TL4_HDR_VALID_YES} - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, - .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr2 = { - ULP_THOR_SYM_TL3_HDR_TYPE_IPV4}, - .field_src3 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr3 = { - ULP_THOR_SYM_TL3_HDR_TYPE_IPV6} - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_TL3_HDR_VALID_YES} - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 }, { - .field_info_mask = { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_PROTO_ID }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 }, { - .field_info_mask = { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_PROTO_ID }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_TL2_HDR_VALID_YES} - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "hrec_next", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "hrec_next", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "agg_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "agg_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "metadata", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "metadata", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "pkt_type_0", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "pkt_type_0", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "pkt_type_1", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "pkt_type_1", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - .field_info_spec = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 }, - /* class_tid: 2, , table: profile_tcam_cache.f2_wr */ { - .field_info_mask = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_QOS }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "hdr_sig_id", - .field_bit_size = 6, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "hdr_sig_id", - .field_bit_size = 6, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 }, - /* class_tid: 2, , table: wm.l3_l4.ipv4 */ { - .field_info_mask = { - .description = "wc_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "wc_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, - .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr3 = { - (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_QOS }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "spif", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "spif", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_QOS }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "lcos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "lcos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "meta", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "meta", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_QOS }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "rcyc_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "rcyc_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "loopback", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "loopback", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 }, { - .field_info_mask = { - .description = "tl2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_QOS }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "tl2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 }, { - .field_info_mask = { - .description = "tl2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_QOS }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "tl2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "tl2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_QOS }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "tl2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "tl2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_QOS }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "tl2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_UDP }, { - .field_info_mask = { - .description = "tl2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_UDP_SRC_PORT }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "tl2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_TCP }, { - .field_info_mask = { - .description = "tl3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_TCP_SRC_PORT }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "tl3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP }, { - .field_info_mask = { - .description = "tl3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "tl3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP }, { - .field_info_mask = { - .description = "tl3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "tl3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_UDP }, { - .field_info_mask = { - .description = "tl3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_UDP_SRC_PORT }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "tl3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_TCP }, { - .field_info_mask = { - .description = "tl3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_TCP_SRC_PORT }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "tl3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP }, { - .field_info_mask = { - .description = "tl3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "tl3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP }, { - .field_info_mask = { - .description = "tl3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "tl3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_UDP }, { - .field_info_mask = { - .description = "tl3.l3err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.l3err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_UDP_DST_PORT }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "tl4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_TCP }, { - .field_info_mask = { - .description = "tl4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_TCP_DST_PORT }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "tl4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP }, { - .field_info_mask = { - .description = "tl4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "tl4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP }, { - .field_info_mask = { - .description = "tl4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "tuntype", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tuntype", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tflags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tflags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_UDP }, { - .field_info_mask = { - .description = "tids", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tids", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_UDP_DST_PORT }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "tid", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tid", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tctxts", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tctxts", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_TCP }, { - .field_info_mask = { - .description = "tctxt", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tctxt", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_TCP_DST_PORT }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "tqos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tqos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "terr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "terr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP }, { - .field_info_mask = { - .description = "l2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT }, + /* field_cond: class_tid: 1, em_key_recipe.0 */ { - .field_info_mask = { - .description = "l2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP }, { - .field_info_mask = { - .description = "l2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT }, + /* cond_execute: class_tid: 1, control.field_sig_validation:1500*/ { - .field_info_mask = { - .description = "l2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET, + .cond_operand = BNXT_ULP_RF_IDX_CC }, { - .field_info_mask = { - .description = "l2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_FLOW_SIG_ID }, + /* cond_execute: class_tid: 1, em.ingress_generic_template:1502*/ { - .field_info_mask = { - .description = "l2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET, + .cond_operand = BNXT_ULP_CF_IDX_WC_MATCH }, + /* cond_execute: class_tid: 2, control.ipv6_wc_check:1503*/ { - .field_info_mask = { - .description = "l2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "l2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, + .cond_operand = BNXT_ULP_CF_IDX_WC_MATCH }, + /* cond_execute: class_tid: 2, control.proto_header_cache_miss:1505*/ { - .field_info_mask = { - .description = "l2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, + /* cond_execute: class_tid: 2, control.overlap_miss:1506*/ { - .field_info_mask = { - .description = "l2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "l2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_CNTXT_ID }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "l2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_METADATA }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "l2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_RECYCLE_CNT }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "l2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH }, { - .field_info_mask = { - .description = "l3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "l3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH }, { - .field_info_mask = { - .description = "l3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_SMAC }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "l3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN }, { - .field_info_mask = { - .description = "l3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN }, { - .field_info_mask = { - .description = "l3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ONES, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CF, - .field_opr2 = { - (BNXT_ULP_CF_IDX_I_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_I_L3_PROTO_ID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "l3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN }, { - .field_info_mask = { - .description = "l3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN }, { - .field_info_mask = { - .description = "l3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OI_VLAN_VID }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "l3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN }, { - .field_info_mask = { - .description = "l3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN }, { - .field_info_mask = { - .description = "l3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "l3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY }, { - .field_info_mask = { - .description = "l3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH }, { - .field_info_mask = { - .description = "l3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_TYPE }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "l3.l3err.ipv4", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3err.ipv4", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.l3err.ipv6", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3err.ipv6", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "l4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "l4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CF, - .field_opr2 = { - (BNXT_ULP_CF_IDX_I_L4_SRC_PORT_MASK >> 8) & 0xff, - BNXT_ULP_CF_IDX_I_L4_SRC_PORT_MASK & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CF, - .field_opr2 = { - (BNXT_ULP_CF_IDX_I_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_I_L4_SRC_PORT & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CF, - .field_opr2 = { - (BNXT_ULP_CF_IDX_I_L4_DST_PORT_MASK >> 8) & 0xff, - BNXT_ULP_CF_IDX_I_L4_DST_PORT_MASK & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CF, - .field_opr2 = { - (BNXT_ULP_CF_IDX_I_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_I_L4_DST_PORT & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "l4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "l4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l4.ack", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.ack", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "l4.win", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.win", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "l4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "l4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "l4.tsval", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.tsval", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l4.txecr", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.txecr", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "l4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_TTL }, - /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */ + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, - /* class_tid: 3, , table: profile_tcam_cache.ipv6_rd */ { - .field_info_mask = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_TTL }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "hdr_sig_id", - .field_bit_size = 6, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "hdr_sig_id", - .field_bit_size = 6, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, - /* class_tid: 3, , table: profile_tcam.l2_l3_l4_v6_em */ { - .field_info_mask = { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "l4_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ONES, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l4_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, - .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr2 = { - ULP_THOR_SYM_L4_HDR_TYPE_TCP}, - .field_src3 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr3 = { - ULP_THOR_SYM_L4_HDR_TYPE_UDP} - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "l4_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff} - }, - .field_info_spec = { - .description = "l4_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff} - }, - .field_info_spec = { - .description = "l4_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "ieh", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "ieh", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l3_hdr_isIP", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_QOS }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "l3_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l3_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_L3_HDR_TYPE_IPV6} - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l3_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l3_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_L3_HDR_VALID_YES} - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_QOS }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "l2_two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP }, { - .field_info_mask = { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "l2_hdr_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l2_hdr_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l2_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP }, { - .field_info_mask = { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l2_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_THOR_SYM_L2_HDR_VALID_YES} - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tun_hdr_flags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP }, { - .field_info_mask = { - .description = "tun_hdr_err", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tun_hdr_err", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tun_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP }, { - .field_info_mask = { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl4_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN }, { - .field_info_mask = { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN_GPE }, { - .field_info_mask = { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_T_VXLAN_GPE_VNI }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH }, { - .field_info_mask = { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl3_hdr_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_DMAC }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl3_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_two_vtags", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH }, { - .field_info_mask = { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_vtag_present", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_hdr_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH }, { - .field_info_mask = { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "tl2_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_SMAC }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "hrec_next", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "hrec_next", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH }, { - .field_info_mask = { - .description = "agg_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "agg_error", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_SMAC }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "metadata", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "metadata", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "pkt_type_0", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "pkt_type_0", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_IO_VLAN }, { - .field_info_mask = { - .description = "pkt_type_1", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "pkt_type_1", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_II_VLAN }, { - .field_info_mask = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - .field_info_spec = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_IO_VLAN_VID }, - /* class_tid: 3, , table: profile_tcam_cache.l2_l3_l4_v6_wr */ + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN }, { - .field_info_mask = { - .description = "hdr_sig_id", - .field_bit_size = 6, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "hdr_sig_id", - .field_bit_size = 6, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN }, - /* class_tid: 3, , table: em.l2_l3_l4_v6.0 */ { - .field_info_mask = { - .description = "em_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "em_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "parif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_IO_VLAN }, { - .field_info_mask = { - .description = "spif", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "spif", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_II_VLAN }, { - .field_info_mask = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "svif", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_II_VLAN_VID }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "lcos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "lcos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "meta", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "meta", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_IO_VLAN }, { - .field_info_mask = { - .description = "rcyc_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "rcyc_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_II_VLAN }, { - .field_info_mask = { - .description = "loopback", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "loopback", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_IO_VLAN_VID }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "tl2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN }, { - .field_info_mask = { - .description = "tl2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN }, { - .field_info_mask = { - .description = "tl2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OI_VLAN_VID }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "tl2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OO_VLAN }, { - .field_info_mask = { - .description = "tl2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET, + .cond_operand = BNXT_ULP_HDR_BIT_OI_VLAN }, { - .field_info_mask = { - .description = "tl2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_OO_VLAN_VID }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "tl2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY }, { - .field_info_mask = { - .description = "tl2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_ETH }, { - .field_info_mask = { - .description = "tl2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_ETH_TYPE }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "tl2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_ONLY }, { - .field_info_mask = { - .description = "tl2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_ETH }, { - .field_info_mask = { - .description = "tl3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_TYPE }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "tl3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 }, { - .field_info_mask = { - .description = "tl3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "tl3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 }, { - .field_info_mask = { - .description = "tl3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "tl3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "tl3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "tl3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "tl3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "tl3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 }, { - .field_info_mask = { - .description = "tl3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "tl3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 }, { - .field_info_mask = { - .description = "tl3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "tl3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "tl3.l3err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl3.l3err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "tl4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "tl4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "tl4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 }, { - .field_info_mask = { - .description = "tl4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_TTL }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "tl4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tl4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 }, { - .field_info_mask = { - .description = "tl4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tl4.err", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_TTL }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "tuntype", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tuntype", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tflags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tflags", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "tids", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tids", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_TTL }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "tid", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tid", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "tctxts", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tctxts", - .field_bit_size = 24, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "tctxt", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tctxt", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_TTL }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "tqos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "tqos", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "terr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "terr", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 }, { - .field_info_mask = { - .description = "l2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_l2type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_PROTO_ID }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "l2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_SKIP - }, - .field_info_spec = { - .description = "l2_dmac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_SKIP - }, - .field_info_spec = { - .description = "l2_smac", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 }, { - .field_info_mask = { - .description = "l2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_dt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_PROTO_ID }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "l2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_sa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_nvt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "l2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "l2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "l2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ovt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "l2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivp", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivd", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV6 }, { - .field_info_mask = { - .description = "l2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff, - BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_SKIP - }, - .field_info_spec = { - .description = "l2_ivv", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_OO_VLAN_FB_VID >> 8) & 0xff, - BNXT_ULP_CF_IDX_OO_VLAN_FB_VID & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV6_QOS }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "l2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_ivt", - .field_bit_size = 3, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l2_etype", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4 }, { - .field_info_mask = { - .description = "l3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_IPV4_QOS }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "l3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.sip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_SKIP - }, - .field_info_spec = { - .description = "l3.sip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6 }, { - .field_info_mask = { - .description = "l3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.sip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV6_QOS }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "l3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.dip.ipv4", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_SKIP - }, - .field_info_spec = { - .description = "l3.dip.ipv6", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, { - .field_info_mask = { - .description = "l3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.dip_selcmp.ipv6", - .field_bit_size = 72, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_IPV4_QOS }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "l3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ttl", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} - }, - .field_info_spec = { - .description = "l3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CF, - .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_UDP }, { - .field_info_mask = { - .description = "l3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.fid.ipv4", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_UDP_SRC_PORT }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "l3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.fid.ipv6", - .field_bit_size = 20, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.qos", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_TCP }, { - .field_info_mask = { - .description = "l3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_nonext", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_TCP_SRC_PORT }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "l3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_esp", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_auth", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP }, { - .field_info_mask = { - .description = "l3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_dest", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "l3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_rthdr", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP }, { - .field_info_mask = { - .description = "l3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_hop", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "l3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.ieh_1frag", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.df", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_UDP }, { - .field_info_mask = { - .description = "l3.l3err.ipv4", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3err.ipv4", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_UDP_DST_PORT }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "l3.l3err.ipv6", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l3.l3err.ipv6", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.l4type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_I_TCP }, { - .field_info_mask = { - .description = "l4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "l4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CF, - .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_I_TCP_DST_PORT }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "l4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "l4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CF, - .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.flags", - .field_bit_size = 9, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_UDP }, { - .field_info_mask = { - .description = "l4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.seq", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT }, + /* field_cond: class_tid: 2, fkb_select.wc_gen_template */ { - .field_info_mask = { - .description = "l4.ack", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.ack", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_NOT_SET, + .cond_operand = BNXT_ULP_CF_BIT_IS_TUNNEL }, { - .field_info_mask = { - .description = "l4.win", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.win", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_O_TCP }, { - .field_info_mask = { - .description = "l4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.pa", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_WC_FIELD_BIT_IS_SET, + .cond_operand = BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "l4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.opt", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_CNTXT_ID }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "l4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.tcpts", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_L2_CNTXT_ID }, + /* field_cond: class_tid: 2, wm_key_recipe.0 */ { - .field_info_mask = { - .description = "l4.tsval", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - }, - .field_info_spec = { - .description = "l4.tsval", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SKIP - } + .cond_opcode = BNXT_ULP_COND_OPC_CF_BIT_IS_SET, + .cond_operand = BNXT_ULP_CF_BIT_METADATA }, + /* field_cond: class_tid: 2, wm_key_rec