From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4682745A5E; Sun, 29 Sep 2024 18:08:29 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 16758402A3; Sun, 29 Sep 2024 18:08:29 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 2379440273; Sun, 29 Sep 2024 18:08:27 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 48TFVTjf017101; Sun, 29 Sep 2024 09:08:26 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=j 05fXQ+gQpCBimDVR8CbUlTaFTCt4TLk+H4X7nf7O7M=; b=XZJ1CHbP+t2gCOlEV mfadVqyAU21kfdTFD/hnDzvTIyb0o1NPICwzL5QMxS5BCEiyseA4naQNdVVnfcjk pLv0WiYfLn2j4LIc8zOLr7Ys8Rbq4GJjsY6S0rErA9Ec+lAgOdCtHyVOjF9Vt+8d 0sr15P4n94R5Jaep3KVqcGIZDbYxZ8Ajhqnb7AipMdniu2J7ZinDD62k7RuwlZ3T YlcbUnxa/HczzJZQnR4EzkBv312r2aG1tjgErqL+6EYuhnQ5ZZ+uEASXA+P3g7Fl oDNLyok6QlGitxYQKO7I9gmgu28wAByIZxo9pPW0IKTruuBRR236BaKTAxORM2W3 e2Njw== Received: from dc5-exch05.marvell.com ([199.233.59.128]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 41xhag3h3w-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sun, 29 Sep 2024 09:08:26 -0700 (PDT) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Sun, 29 Sep 2024 09:08:24 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Sun, 29 Sep 2024 09:08:24 -0700 Received: from MININT-80QBFE8.corp.innovium.com (MININT-80QBFE8.marvell.com [10.28.164.106]) by maili.marvell.com (Postfix) with ESMTP id 174265B692B; Sun, 29 Sep 2024 09:08:20 -0700 (PDT) From: To: , , , "Nithin Dabilpuram" , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Pavan Nikhilesh , Subject: [PATCH v3] common/cnxk: fix IRQ reconfiguration Date: Sun, 29 Sep 2024 21:38:15 +0530 Message-ID: <20240929160815.2868-1-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240919180243.1255-1-pbhagavatula@marvell.com> References: <20240919180243.1255-1-pbhagavatula@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: OLrxZFLPMh9pPf8PPDDvNpXt0MMpGTQ4 X-Proofpoint-ORIG-GUID: OLrxZFLPMh9pPf8PPDDvNpXt0MMpGTQ4 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Pavan Nikhilesh Unregister SSO device and NPA IRQs before resizing IRQs to cleanup stale IRQ handles. Fixes: 993107f0f440 ("common/cnxk: limit SSO interrupt allocation count") Cc: stable@dpdk.org Signed-off-by: Pavan Nikhilesh --- v2 Changes: - Reorder npa interrupt un-registration. v3 Changes: - Update commit type to fixes. drivers/common/cnxk/roc_dev.c | 16 +++++++--------- drivers/common/cnxk/roc_dev_priv.h | 2 ++ drivers/common/cnxk/roc_sso.c | 7 +++++++ 3 files changed, 16 insertions(+), 9 deletions(-) diff --git a/drivers/common/cnxk/roc_dev.c b/drivers/common/cnxk/roc_dev.c index daf7684d8e..4a5787e7f9 100644 --- a/drivers/common/cnxk/roc_dev.c +++ b/drivers/common/cnxk/roc_dev.c @@ -1017,8 +1017,8 @@ mbox_unregister_vf_irq(struct plt_pci_device *pci_dev, struct dev *dev) RVU_VF_INT_VEC_MBOX); } -static void -mbox_unregister_irq(struct plt_pci_device *pci_dev, struct dev *dev) +void +dev_mbox_unregister_irq(struct plt_pci_device *pci_dev, struct dev *dev) { if (dev_is_vf(dev)) mbox_unregister_vf_irq(pci_dev, dev); @@ -1096,8 +1096,8 @@ roc_pf_vf_flr_irq(void *param) } } -static int -vf_flr_unregister_irqs(struct plt_pci_device *pci_dev, struct dev *dev) +void +dev_vf_flr_unregister_irqs(struct plt_pci_device *pci_dev, struct dev *dev) { struct plt_intr_handle *intr_handle = pci_dev->intr_handle; int i; @@ -1113,8 +1113,6 @@ vf_flr_unregister_irqs(struct plt_pci_device *pci_dev, struct dev *dev) dev_irq_unregister(intr_handle, roc_pf_vf_flr_irq, dev, RVU_PF_INT_VEC_VFFLR1); - - return 0; } int @@ -1600,7 +1598,7 @@ dev_init(struct dev *dev, struct plt_pci_device *pci_dev) iounmap: dev_vf_mbase_put(pci_dev, vf_mbase); mbox_unregister: - mbox_unregister_irq(pci_dev, dev); + dev_mbox_unregister_irq(pci_dev, dev); if (dev->ops) plt_free(dev->ops); mbox_fini: @@ -1636,10 +1634,10 @@ dev_fini(struct dev *dev, struct plt_pci_device *pci_dev) if (dev->lmt_mz) plt_memzone_free(dev->lmt_mz); - mbox_unregister_irq(pci_dev, dev); + dev_mbox_unregister_irq(pci_dev, dev); if (!dev_is_vf(dev)) - vf_flr_unregister_irqs(pci_dev, dev); + dev_vf_flr_unregister_irqs(pci_dev, dev); /* Release PF - VF */ mbox = &dev->mbox_vfpf; if (mbox->hwbase && mbox->dev) diff --git a/drivers/common/cnxk/roc_dev_priv.h b/drivers/common/cnxk/roc_dev_priv.h index 50e12cbf17..df7dc222ed 100644 --- a/drivers/common/cnxk/roc_dev_priv.h +++ b/drivers/common/cnxk/roc_dev_priv.h @@ -131,6 +131,8 @@ int dev_irqs_disable(struct plt_intr_handle *intr_handle); int dev_irq_reconfigure(struct plt_intr_handle *intr_handle, uint16_t max_intr); int dev_mbox_register_irq(struct plt_pci_device *pci_dev, struct dev *dev); +void dev_mbox_unregister_irq(struct plt_pci_device *pci_dev, struct dev *dev); int dev_vf_flr_register_irqs(struct plt_pci_device *pci_dev, struct dev *dev); +void dev_vf_flr_unregister_irqs(struct plt_pci_device *pci_dev, struct dev *dev); #endif /* _ROC_DEV_PRIV_H */ diff --git a/drivers/common/cnxk/roc_sso.c b/drivers/common/cnxk/roc_sso.c index 293b0c81a1..7d45b06dda 100644 --- a/drivers/common/cnxk/roc_sso.c +++ b/drivers/common/cnxk/roc_sso.c @@ -842,7 +842,14 @@ sso_update_msix_vec_count(struct roc_sso *roc_sso, uint16_t sso_vec_cnt) return dev_irq_reconfigure(pci_dev->intr_handle, mbox_vec_cnt + npa_vec_cnt); } + /* Before re-configuring unregister irqs */ npa_vec_cnt = (dev->npa.pci_dev == pci_dev) ? NPA_LF_INT_VEC_POISON + 1 : 0; + if (npa_vec_cnt) + npa_unregister_irqs(&dev->npa); + + dev_mbox_unregister_irq(pci_dev, dev); + if (!dev_is_vf(dev)) + dev_vf_flr_unregister_irqs(pci_dev, dev); /* Re-configure to include SSO vectors */ rc = dev_irq_reconfigure(pci_dev->intr_handle, mbox_vec_cnt + npa_vec_cnt + sso_vec_cnt); -- 2.25.1