From: Brian Dooley <brian.dooley@intel.com>
To: Kai Ji <kai.ji@intel.com>,
Pablo de Lara <pablo.de.lara.guarch@intel.com>
Cc: dev@dpdk.org, gakhil@marvell.com, Brian Dooley <brian.dooley@intel.com>
Subject: [PATCH v2 3/4] crypto/ipsec_mb: add SM4 algorithm support
Date: Mon, 30 Sep 2024 14:55:30 +0100 [thread overview]
Message-ID: <20240930135531.3494777-3-brian.dooley@intel.com> (raw)
In-Reply-To: <20240930135531.3494777-1-brian.dooley@intel.com>
This patch introduces SM4 algorithm support for SM4 CBC, SM4 ECB
and SM4 CTR to the AESNI_MB PMD.
Signed-off-by: Brian Dooley <brian.dooley@intel.com>
---
v2:
Add Intel IPsec MB version check to capabilities
Add SM4 CTR algorithm support
---
drivers/crypto/ipsec_mb/pmd_aesni_mb.c | 26 ++++++++
drivers/crypto/ipsec_mb/pmd_aesni_mb_priv.h | 69 +++++++++++++++++++++
2 files changed, 95 insertions(+)
diff --git a/drivers/crypto/ipsec_mb/pmd_aesni_mb.c b/drivers/crypto/ipsec_mb/pmd_aesni_mb.c
index 019867fe1c..8790b53b1a 100644
--- a/drivers/crypto/ipsec_mb/pmd_aesni_mb.c
+++ b/drivers/crypto/ipsec_mb/pmd_aesni_mb.c
@@ -451,6 +451,9 @@ aesni_mb_set_session_cipher_parameters(const IMB_MGR *mb_mgr,
uint8_t is_zuc = 0;
uint8_t is_snow3g = 0;
uint8_t is_kasumi = 0;
+#if IMB_VERSION(1, 5, 0) <= IMB_VERSION_NUM
+ uint8_t is_sm4 = 0;
+#endif
if (xform == NULL) {
sess->template_job.cipher_mode = IMB_CIPHER_NULL;
@@ -521,6 +524,20 @@ aesni_mb_set_session_cipher_parameters(const IMB_MGR *mb_mgr,
sess->iv.offset = xform->cipher.iv.offset;
sess->template_job.iv_len_in_bytes = xform->cipher.iv.length;
return 0;
+#if IMB_VERSION(1, 5, 0) <= IMB_VERSION_NUM
+ case RTE_CRYPTO_CIPHER_SM4_CBC:
+ sess->template_job.cipher_mode = IMB_CIPHER_SM4_CBC;
+ is_sm4 = 1;
+ break;
+ case RTE_CRYPTO_CIPHER_SM4_ECB:
+ sess->template_job.cipher_mode = IMB_CIPHER_SM4_ECB;
+ is_sm4 = 1;
+ break;
+ case RTE_CRYPTO_CIPHER_SM4_CTR:
+ sess->template_job.cipher_mode = IMB_CIPHER_SM4_CNTR;
+ is_sm4 = 1;
+ break;
+#endif
default:
IPSEC_MB_LOG(ERR, "Unsupported cipher mode parameter");
return -ENOTSUP;
@@ -655,6 +672,15 @@ aesni_mb_set_session_cipher_parameters(const IMB_MGR *mb_mgr,
&sess->cipher.pKeySched_kasumi_cipher);
sess->template_job.enc_keys = &sess->cipher.pKeySched_kasumi_cipher;
sess->template_job.dec_keys = &sess->cipher.pKeySched_kasumi_cipher;
+#if IMB_VERSION(1, 5, 0) <= IMB_VERSION_NUM
+ } else if (is_sm4) {
+ sess->template_job.key_len_in_bytes = IMB_KEY_128_BYTES;
+ IMB_SM4_KEYEXP(mb_mgr, xform->cipher.key.data,
+ sess->cipher.expanded_sm4_keys.encode,
+ sess->cipher.expanded_sm4_keys.decode);
+ sess->template_job.enc_keys = sess->cipher.expanded_sm4_keys.encode;
+ sess->template_job.dec_keys = sess->cipher.expanded_sm4_keys.decode;
+#endif
} else {
if (xform->cipher.key.length != 8) {
IPSEC_MB_LOG(ERR, "Invalid cipher key length");
diff --git a/drivers/crypto/ipsec_mb/pmd_aesni_mb_priv.h b/drivers/crypto/ipsec_mb/pmd_aesni_mb_priv.h
index 24c2686952..af462d2569 100644
--- a/drivers/crypto/ipsec_mb/pmd_aesni_mb_priv.h
+++ b/drivers/crypto/ipsec_mb/pmd_aesni_mb_priv.h
@@ -732,6 +732,7 @@ static const struct rte_cryptodev_capabilities aesni_mb_capabilities[] = {
}, }
}, }
},
+#if IMB_VERSION(1, 5, 0) <= IMB_VERSION_NUM
{ /* SM3 */
.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
{.sym = {
@@ -774,6 +775,63 @@ static const struct rte_cryptodev_capabilities aesni_mb_capabilities[] = {
}, }
}, }
},
+ { /* SM4 CBC */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+ {.cipher = {
+ .algo = RTE_CRYPTO_CIPHER_SM4_CBC,
+ .block_size = 16,
+ .key_size = {
+ .min = 16,
+ .max = 16,
+ .increment = 0
+ },
+ .iv_size = {
+ .min = 16,
+ .max = 16,
+ .increment = 0
+ }
+ }, }
+ }, }
+ },
+ { /* SM4 ECB */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+ {.cipher = {
+ .algo = RTE_CRYPTO_CIPHER_SM4_ECB,
+ .block_size = 16,
+ .key_size = {
+ .min = 16,
+ .max = 16,
+ .increment = 0
+ },
+ .iv_size = { 0 }
+ }, }
+ }, }
+ },
+ { /* SM4 CTR */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+ {.cipher = {
+ .algo = RTE_CRYPTO_CIPHER_SM4_CTR,
+ .block_size = 16,
+ .key_size = {
+ .min = 16,
+ .max = 16,
+ .increment = 0
+ },
+ .iv_size = {
+ .min = 16,
+ .max = 16,
+ .increment = 0
+ }
+ }, }
+ }, }
+ },
+#endif
RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
};
@@ -951,6 +1009,17 @@ struct __rte_cache_aligned aesni_mb_session {
/* *< SNOW3G scheduled cipher key */
kasumi_key_sched_t pKeySched_kasumi_cipher;
/* *< KASUMI scheduled cipher key */
+#if IMB_VERSION(1, 5, 0) <= IMB_VERSION_NUM
+ struct {
+ alignas(16) uint32_t encode[IMB_SM4_KEY_SCHEDULE_ROUNDS];
+ /* *< encode key */
+ alignas(16) uint32_t decode[IMB_SM4_KEY_SCHEDULE_ROUNDS];
+ /* *< decode key */
+ } expanded_sm4_keys;
+ /* *< Expanded SM4 keys - Original 128 bit key is
+ * expanded into 32 round keys, each 32 bits.
+ */
+#endif
};
} cipher;
--
2.25.1
next prev parent reply other threads:[~2024-09-30 13:55 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-06 12:39 [PATCH v1 1/3] crypto/ipsec_mb: add SM3 " Brian Dooley
2024-09-06 12:39 ` [PATCH v1 2/3] crypto/ipsec_mb: add HMAC " Brian Dooley
2024-09-06 12:39 ` [PATCH v1 3/3] crypto/ipsec_mb: add SM4 " Brian Dooley
2024-09-18 5:53 ` [EXTERNAL] " Akhil Goyal
2024-09-30 13:55 ` [PATCH v2 1/4] crypto/ipsec_mb: add SM3 " Brian Dooley
2024-09-30 13:55 ` [PATCH v2 2/4] crypto/ipsec_mb: add HMAC " Brian Dooley
2024-09-30 13:55 ` Brian Dooley [this message]
2024-09-30 13:55 ` [PATCH v2 4/4] doc: updated feature matrix for AESNI MB PMD Brian Dooley
2024-10-01 7:59 ` [EXTERNAL] " Akhil Goyal
2024-10-01 8:40 ` Dooley, Brian
2024-10-01 8:00 ` Akhil Goyal
2024-10-03 17:05 ` [PATCH v3 1/3] crypto/ipsec_mb: add SM3 algorithm support Brian Dooley
2024-10-03 17:05 ` [PATCH v3 2/3] crypto/ipsec_mb: add HMAC " Brian Dooley
2024-10-04 12:05 ` De Lara Guarch, Pablo
2024-10-03 17:05 ` [PATCH v3 3/3] crypto/ipsec_mb: add SM4 " Brian Dooley
2024-10-04 12:05 ` De Lara Guarch, Pablo
2024-10-04 12:05 ` [PATCH v3 1/3] crypto/ipsec_mb: add SM3 " De Lara Guarch, Pablo
2024-10-09 15:21 ` Akhil Goyal
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