From: Sriharsha Basavapatna <sriharsha.basavapatna@broadcom.com>
To: dev@dpdk.org
Cc: Manish Kurup <manish.kurup@broadcom.com>,
Sriharsha Basavapatna <sriharsha.basavapatna@broadcom.com>,
Kishore Padmanabha <kishore.padmanabha@broadcom.com>,
Ajit Khaparde <ajit.khaparde@broadcom.com>
Subject: [PATCH v3 15/47] net/bnxt: tf_ulp: Wh+ mirroring support
Date: Tue, 1 Oct 2024 11:28:01 +0530 [thread overview]
Message-ID: <20241001055833.757163-16-sriharsha.basavapatna@broadcom.com> (raw)
In-Reply-To: <20241001055833.757163-1-sriharsha.basavapatna@broadcom.com>
From: Manish Kurup <manish.kurup@broadcom.com>
1. ULP fixes to enable primitives to support mirroring
2. RTE parser changes to support and use multiple ports in RTE
input msgs
3. Template changes required to support ingress mirroring
4. Template changes required to support egress mirroring
(using VFR pipeline)
Signed-off-by: Manish Kurup <manish.kurup@broadcom.com>
Signed-off-by: Sriharsha Basavapatna <sriharsha.basavapatna@broadcom.com>
Reviewed-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 8 +
drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 179 ++++++++++++++++++++---
2 files changed, 167 insertions(+), 20 deletions(-)
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index 9dda70d75b..eb0f95cfee 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -3789,6 +3789,8 @@ ulp_mapper_func_info_process(struct bnxt_ulp_mapper_parms *parms,
case BNXT_ULP_FUNC_OPC_GT:
case BNXT_ULP_FUNC_OPC_LE:
case BNXT_ULP_FUNC_OPC_LT:
+ case BNXT_ULP_FUNC_OPC_ADD:
+ case BNXT_ULP_FUNC_OPC_SUB:
process_src1 = 1;
process_src2 = 1;
break;
@@ -3841,6 +3843,12 @@ ulp_mapper_func_info_process(struct bnxt_ulp_mapper_parms *parms,
if (res1 < res2)
res = 1;
break;
+ case BNXT_ULP_FUNC_OPC_ADD:
+ res = res1 + res2;
+ break;
+ case BNXT_ULP_FUNC_OPC_SUB:
+ res = res1 - res2;
+ break;
case BNXT_ULP_FUNC_OPC_COPY_SRC1_TO_RF:
res = res1;
break;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
index 013d8b0a59..da20b41c72 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
@@ -330,9 +330,21 @@ ulp_post_process_normal_flow(struct ulp_rte_parser_params *params)
/* Evaluate the VF to VF flag */
if (act_port_set && act_port_type == BNXT_ULP_INTF_TYPE_VF_REP &&
- match_port_type == BNXT_ULP_INTF_TYPE_VF_REP)
- ULP_BITMAP_SET(params->act_bitmap.bits,
- BNXT_ULP_ACT_BIT_VF_TO_VF);
+ match_port_type == BNXT_ULP_INTF_TYPE_VF_REP) {
+ if (!ULP_BITMAP_ISSET(params->act_bitmap.bits,
+ BNXT_ULP_ACT_BIT_MULTIPLE_PORT)) {
+ ULP_BITMAP_SET(params->act_bitmap.bits,
+ BNXT_ULP_ACT_BIT_VF_TO_VF);
+ } else {
+ if (ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_MP_A_IS_VFREP) &&
+ ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_MP_B_IS_VFREP))
+ ULP_BITMAP_SET(params->act_bitmap.bits,
+ BNXT_ULP_ACT_BIT_VF_TO_VF);
+ else
+ ULP_BITMAP_RESET(params->act_bitmap.bits,
+ BNXT_ULP_ACT_BIT_VF_TO_VF);
+ }
+ }
/* Update the decrement ttl computational fields */
if (ULP_BITMAP_ISSET(params->act_bitmap.bits,
@@ -2349,15 +2361,74 @@ ulp_rte_count_act_handler(const struct rte_flow_action *action_item,
return BNXT_TF_RC_SUCCESS;
}
+static bool ulp_rte_parser_is_portb_vfrep(struct ulp_rte_parser_params *param)
+{
+ return ULP_COMP_FLD_IDX_RD(param, BNXT_ULP_CF_IDX_MP_B_IS_VFREP);
+}
+
+/*
+ * Swaps info related to multi-port:
+ * common:
+ * BNXT_ULP_CF_IDX_MP_B_IS_VFREP, BNXT_ULP_CF_IDX_MP_A_IS_VFREP
+ * BNXT_ULP_CF_IDX_MP_PORT_A, BNXT_ULP_CF_IDX_MP_PORT_B
+ *
+ * ingress:
+ * BNXT_ULP_CF_IDX_MP_VNIC_B, BNXT_ULP_CF_IDX_MP_VNIC_A
+ *
+ * egress:
+ * BNXT_ULP_CF_IDX_MP_MDATA_B, BNXT_ULP_CF_IDX_MP_MDATA_A
+ * BNXT_ULP_CF_IDX_MP_VPORT_B, BNXT_ULP_CF_IDX_MP_VPORT_A
+ *
+ * Note: This is done as OVS could give us a non-VFREP port in port B, and we
+ * cannot use that to mirror, so we swap out the ports so that a VFREP is now
+ * in port B instead.
+ */
+static int32_t
+ulp_rte_parser_normalize_port_info(struct ulp_rte_parser_params *param)
+{
+ uint16_t mp_port_a, mp_port_b, mp_mdata_a, mp_mdata_b,
+ mp_vport_a, mp_vport_b, mp_vnic_a, mp_vnic_b,
+ mp_is_vfrep_a, mp_is_vfrep_b;
+
+ mp_is_vfrep_a = ULP_COMP_FLD_IDX_RD(param, BNXT_ULP_CF_IDX_MP_A_IS_VFREP);
+ mp_is_vfrep_b = ULP_COMP_FLD_IDX_RD(param, BNXT_ULP_CF_IDX_MP_B_IS_VFREP);
+ ULP_COMP_FLD_IDX_WR(param, BNXT_ULP_CF_IDX_MP_B_IS_VFREP, mp_is_vfrep_a);
+ ULP_COMP_FLD_IDX_WR(param, BNXT_ULP_CF_IDX_MP_A_IS_VFREP, mp_is_vfrep_b);
+
+ mp_port_a = ULP_COMP_FLD_IDX_RD(param, BNXT_ULP_CF_IDX_MP_PORT_A);
+ mp_port_b = ULP_COMP_FLD_IDX_RD(param, BNXT_ULP_CF_IDX_MP_PORT_B);
+ ULP_COMP_FLD_IDX_WR(param, BNXT_ULP_CF_IDX_MP_PORT_B, mp_port_a);
+ ULP_COMP_FLD_IDX_WR(param, BNXT_ULP_CF_IDX_MP_PORT_A, mp_port_b);
+
+ mp_vport_a = ULP_COMP_FLD_IDX_RD(param, BNXT_ULP_CF_IDX_MP_VPORT_A);
+ mp_vport_b = ULP_COMP_FLD_IDX_RD(param, BNXT_ULP_CF_IDX_MP_VPORT_B);
+ ULP_COMP_FLD_IDX_WR(param, BNXT_ULP_CF_IDX_MP_VPORT_B, mp_vport_a);
+ ULP_COMP_FLD_IDX_WR(param, BNXT_ULP_CF_IDX_MP_VPORT_A, mp_vport_b);
+
+ mp_vnic_a = ULP_COMP_FLD_IDX_RD(param, BNXT_ULP_CF_IDX_MP_VNIC_A);
+ mp_vnic_b = ULP_COMP_FLD_IDX_RD(param, BNXT_ULP_CF_IDX_MP_VNIC_B);
+ ULP_COMP_FLD_IDX_WR(param, BNXT_ULP_CF_IDX_MP_VNIC_B, mp_vnic_a);
+ ULP_COMP_FLD_IDX_WR(param, BNXT_ULP_CF_IDX_MP_VNIC_A, mp_vnic_b);
+
+ mp_mdata_a = ULP_COMP_FLD_IDX_RD(param, BNXT_ULP_CF_IDX_MP_MDATA_A);
+ mp_mdata_b = ULP_COMP_FLD_IDX_RD(param, BNXT_ULP_CF_IDX_MP_MDATA_B);
+ ULP_COMP_FLD_IDX_WR(param, BNXT_ULP_CF_IDX_MP_MDATA_B, mp_mdata_a);
+ ULP_COMP_FLD_IDX_WR(param, BNXT_ULP_CF_IDX_MP_MDATA_A, mp_mdata_b);
+
+ return BNXT_TF_RC_SUCCESS;
+}
+
+
/* Function to handle the parsing of action ports. */
static int32_t
ulp_rte_parser_act_port_set(struct ulp_rte_parser_params *param,
- uint32_t ifindex,
+ uint32_t ifindex, bool multi_port,
enum bnxt_ulp_direction_type act_dir)
{
enum bnxt_ulp_direction_type dir;
uint16_t pid_s;
- uint32_t pid;
+ uint8_t *p_mdata;
+ uint32_t pid, port_index;
struct ulp_rte_act_prop *act = ¶m->act_prop;
enum bnxt_ulp_intf_type port_type;
uint32_t vnic_type;
@@ -2367,27 +2438,63 @@ ulp_rte_parser_act_port_set(struct ulp_rte_parser_params *param,
dir = (act_dir == BNXT_ULP_DIR_INVALID) ?
ULP_COMP_FLD_IDX_RD(param, BNXT_ULP_CF_IDX_DIRECTION) :
act_dir;
- port_type = ULP_COMP_FLD_IDX_RD(param, BNXT_ULP_CF_IDX_ACT_PORT_TYPE);
- if (dir == BNXT_ULP_DIR_EGRESS &&
- port_type != BNXT_ULP_INTF_TYPE_VF_REP) {
+
+ port_type = ULP_COMP_FLD_IDX_RD(param,
+ BNXT_ULP_CF_IDX_ACT_PORT_TYPE);
+
+ /* Update flag if Port A/B type is VF-REP */
+ ULP_COMP_FLD_IDX_WR(param, multi_port ?
+ BNXT_ULP_CF_IDX_MP_B_IS_VFREP :
+ BNXT_ULP_CF_IDX_MP_A_IS_VFREP,
+ (port_type == BNXT_ULP_INTF_TYPE_VF_REP) ? 1 : 0);
+ if (dir == BNXT_ULP_DIR_EGRESS) {
/* For egress direction, fill vport */
if (ulp_port_db_vport_get(param->ulp_ctx, ifindex, &pid_s))
return BNXT_TF_RC_ERROR;
pid = pid_s;
pid = rte_cpu_to_be_32(pid);
- memcpy(&act->act_details[BNXT_ULP_ACT_PROP_IDX_VPORT],
- &pid, BNXT_ULP_ACT_PROP_SZ_VPORT);
+ if (!multi_port)
+ memcpy(&act->act_details[BNXT_ULP_ACT_PROP_IDX_VPORT],
+ &pid, BNXT_ULP_ACT_PROP_SZ_VPORT);
+
+ /* Fill metadata */
+ if (port_type == BNXT_ULP_INTF_TYPE_VF_REP) {
+ port_index = ULP_COMP_FLD_IDX_RD(param, multi_port ?
+ BNXT_ULP_CF_IDX_MP_PORT_B :
+ BNXT_ULP_CF_IDX_MP_PORT_A);
+ if (ulp_port_db_port_meta_data_get(param->ulp_ctx,
+ port_index, &p_mdata))
+ return BNXT_TF_RC_ERROR;
+ /*
+ * Update appropriate port (A/B) metadata based on multi-port
+ * indication
+ */
+ ULP_COMP_FLD_IDX_WR(param,
+ multi_port ?
+ BNXT_ULP_CF_IDX_MP_MDATA_B :
+ BNXT_ULP_CF_IDX_MP_MDATA_A,
+ rte_cpu_to_be_16(*((uint16_t *)p_mdata)));
+ }
+ /*
+ * Update appropriate port (A/B) VPORT based on multi-port
+ * indication.
+ */
+ ULP_COMP_FLD_IDX_WR(param,
+ multi_port ?
+ BNXT_ULP_CF_IDX_MP_VPORT_B :
+ BNXT_ULP_CF_IDX_MP_VPORT_A,
+ pid_s);
} else {
/* For ingress direction, fill vnic */
/*
- * Action Destination
+ * Action Destination
* ------------------------------------
- * PORT_REPRESENTOR Driver Function
+ * PORT_REPRESENTOR Driver Function
* ------------------------------------
- * REPRESENTED_PORT VF
+ * REPRESENTED_PORT VF
* ------------------------------------
- * PORT_ID VF
+ * PORT_ID VF
*/
if (act_dir != BNXT_ULP_DIR_INGRESS &&
port_type == BNXT_ULP_INTF_TYPE_VF_REP)
@@ -2401,10 +2508,23 @@ ulp_rte_parser_act_port_set(struct ulp_rte_parser_params *param,
pid = pid_s;
pid = rte_cpu_to_be_32(pid);
- memcpy(&act->act_details[BNXT_ULP_ACT_PROP_IDX_VNIC],
- &pid, BNXT_ULP_ACT_PROP_SZ_VNIC);
+ if (!multi_port)
+ memcpy(&act->act_details[BNXT_ULP_ACT_PROP_IDX_VNIC],
+ &pid, BNXT_ULP_ACT_PROP_SZ_VNIC);
+ /*
+ * Update appropriate port (A/B) VNIC based on multi-port
+ * indication.
+ */
+ ULP_COMP_FLD_IDX_WR(param,
+ multi_port ?
+ BNXT_ULP_CF_IDX_MP_VNIC_B :
+ BNXT_ULP_CF_IDX_MP_VNIC_A,
+ pid_s);
}
+ if (multi_port && !ulp_rte_parser_is_portb_vfrep(param))
+ ulp_rte_parser_normalize_port_info(param);
+
/* Update the action port set bit */
ULP_COMP_FLD_IDX_WR(param, BNXT_ULP_CF_IDX_ACT_PORT_IS_SET, 1);
return BNXT_TF_RC_SUCCESS;
@@ -2437,7 +2557,7 @@ ulp_rte_pf_act_handler(const struct rte_flow_action *action_item __rte_unused,
}
/* Update the action properties */
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_ACT_PORT_TYPE, intf_type);
- return ulp_rte_parser_act_port_set(params, ifindex,
+ return ulp_rte_parser_act_port_set(params, ifindex, false,
BNXT_ULP_DIR_INVALID);
}
@@ -2489,7 +2609,7 @@ ulp_rte_vf_act_handler(const struct rte_flow_action *action_item,
/* Update the action properties */
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_ACT_PORT_TYPE, intf_type);
- return ulp_rte_parser_act_port_set(params, ifindex,
+ return ulp_rte_parser_act_port_set(params, ifindex, false,
BNXT_ULP_DIR_INVALID);
}
@@ -2500,12 +2620,14 @@ ulp_rte_port_act_handler(const struct rte_flow_action *act_item,
{
uint32_t ethdev_id;
uint32_t ifindex;
+ const struct rte_flow_action_port_id *port_id = act_item->conf;
+ uint32_t num_ports;
enum bnxt_ulp_intf_type intf_type;
enum bnxt_ulp_direction_type act_dir;
if (!act_item->conf) {
BNXT_TF_DBG(ERR,
- "ParseErr: Invalid Argument\n");
+ "ParseErr: Invalid Argument\n");
return BNXT_TF_RC_PARSE_ERR;
}
switch (act_item->type) {
@@ -2540,6 +2662,18 @@ ulp_rte_port_act_handler(const struct rte_flow_action *act_item,
return BNXT_TF_RC_ERROR;
}
+ num_ports = ULP_COMP_FLD_IDX_RD(param, BNXT_ULP_CF_IDX_MP_NPORTS);
+
+ if (num_ports) {
+ ULP_COMP_FLD_IDX_WR(param, BNXT_ULP_CF_IDX_MP_PORT_B,
+ port_id->id);
+ ULP_BITMAP_SET(param->act_bitmap.bits,
+ BNXT_ULP_ACT_BIT_MULTIPLE_PORT);
+ } else {
+ ULP_COMP_FLD_IDX_WR(param, BNXT_ULP_CF_IDX_MP_PORT_A,
+ port_id->id);
+ }
+
/* Get the port db ifindex */
if (ulp_port_db_dev_port_to_ulp_index(param->ulp_ctx, ethdev_id,
&ifindex)) {
@@ -2558,7 +2692,12 @@ ulp_rte_port_act_handler(const struct rte_flow_action *act_item,
ULP_COMP_FLD_IDX_WR(param, BNXT_ULP_CF_IDX_ACT_PORT_TYPE, intf_type);
ULP_COMP_FLD_IDX_WR(param, BNXT_ULP_CF_IDX_DEV_ACT_PORT_ID,
ethdev_id);
- return ulp_rte_parser_act_port_set(param, ifindex, act_dir);
+
+ ULP_COMP_FLD_IDX_WR(param, BNXT_ULP_CF_IDX_MP_NPORTS, ++num_ports);
+ return ulp_rte_parser_act_port_set(param, ifindex,
+ ULP_BITMAP_ISSET(param->act_bitmap.bits,
+ BNXT_ULP_ACT_BIT_MULTIPLE_PORT),
+ act_dir);
}
/* Function to handle the parsing of RTE Flow action pop vlan. */
--
2.39.3
next prev parent reply other threads:[~2024-10-01 5:50 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-01 5:57 [PATCH v3 00/47] TruFlow update for Thor2 Sriharsha Basavapatna
2024-10-01 5:57 ` [PATCH v3 01/47] net/bnxt: tf_core: fix wc tcam multi slice delete issue Sriharsha Basavapatna
2024-10-01 5:57 ` [PATCH v3 02/47] net/bnxt: tf_core: tcam manager data corruption Sriharsha Basavapatna
2024-10-01 5:57 ` [PATCH v3 03/47] net/bnxt: tf_core: External EM support cleanup Sriharsha Basavapatna
2024-10-01 5:57 ` [PATCH v3 04/47] net/bnxt: tf_core: Thor TF EM key size check Sriharsha Basavapatna
2024-10-01 5:57 ` [PATCH v3 05/47] net/bnxt: tf_core: flow scale improvement Sriharsha Basavapatna
2024-10-01 5:57 ` [PATCH v3 06/47] net/bnxt: tf_core: TF support flow scale query Sriharsha Basavapatna
2024-10-01 5:57 ` [PATCH v3 07/47] net/bnxt: tf_core: fix slice count in case of HA entry move Sriharsha Basavapatna
2024-10-01 5:57 ` [PATCH v3 08/47] net/bnxt: tf_core: convert priority based TCAM manager to dynamic allocation Sriharsha Basavapatna
2024-10-01 5:57 ` [PATCH v3 09/47] net/bnxt: tf_core: remove dead AFM code from session-based priority TCAM mgr Sriharsha Basavapatna
2024-10-01 5:57 ` [PATCH v3 10/47] net/bnxt: tf_core: remove dead " Sriharsha Basavapatna
2024-10-01 5:57 ` [PATCH v3 13/47] net/bnxt: tf_ulp: add custom l2 etype tunnel support Sriharsha Basavapatna
2024-10-01 5:58 ` [PATCH v3 14/47] net/bnxt: tf_ulp: add support for vf to vf flow offload Sriharsha Basavapatna
2024-10-01 5:58 ` Sriharsha Basavapatna [this message]
2024-10-01 5:58 ` [PATCH v3 16/47] net/bnxt: tf_ulp: miscellaneous fixes Sriharsha Basavapatna
2024-10-01 5:58 ` [PATCH v3 19/47] net/bnxt: tf_ulp: convert recipe table to dynamic memory Sriharsha Basavapatna
2024-10-01 5:58 ` [PATCH v3 21/47] net/bnxt: tf_ulp: add action read and clear support Sriharsha Basavapatna
2024-10-01 5:58 ` [PATCH v3 23/47] net/bnxt: tf_ulp: VFR updates for Thor 2 Sriharsha Basavapatna
2024-10-01 5:58 ` [PATCH v3 25/47] net/bnxt: tf_ulp: update template files Sriharsha Basavapatna
2024-10-01 5:58 ` [PATCH v3 26/47] net/bnxt: tf_ulp: enable recipe id generation Sriharsha Basavapatna
2024-10-01 5:58 ` [PATCH v3 27/47] net/bnxt: tf_ulp: fixed parent child db counters Sriharsha Basavapatna
2024-10-01 5:58 ` [PATCH v3 28/47] net/bnxt: tf_ulp: modify return values to adhere to C coding standard Sriharsha Basavapatna
2024-10-01 5:58 ` [PATCH v3 29/47] net/bnxt: tf_ulp: update template files Sriharsha Basavapatna
2024-10-01 5:58 ` [PATCH v3 30/47] net/bnxt: tf_ulp: add mask defaults when mask is not specified Sriharsha Basavapatna
2024-10-01 5:58 ` [PATCH v3 32/47] net/bnxt: tf_ulp: add support for flow priority Sriharsha Basavapatna
2024-10-01 5:58 ` [PATCH v3 34/47] net/bnxt: tf_ulp: add rte_mtr support for Thor2 Sriharsha Basavapatna
2024-10-01 5:58 ` [PATCH v3 35/47] net/bnxt: tf_ulp: TF support flow scale query Sriharsha Basavapatna
2024-10-01 5:58 ` [PATCH v3 36/47] net/bnxt: tf_ulp: add support for rss flow query to ULP Sriharsha Basavapatna
2024-10-01 5:58 ` [PATCH v3 38/47] net/bnxt: tf_ulp: inline utility functions and use likely/unlikely Sriharsha Basavapatna
2024-10-01 5:58 ` [PATCH v3 39/47] net/bnxt: tf_ulp: switch ulp to use rte crc32 hash Sriharsha Basavapatna
2024-10-01 5:58 ` [PATCH v3 41/47] net/bnxt: tf_ulp: support a few generic template items Sriharsha Basavapatna
2024-10-01 5:58 ` [PATCH v3 42/47] net/bnxt: tf_ulp: TFC support flow scale query for Thor2 Sriharsha Basavapatna
2024-10-01 5:58 ` [PATCH v3 44/47] net/bnxt: tf_ulp: enable support for truflow feature configuration Sriharsha Basavapatna
2024-10-01 5:58 ` [PATCH v3 45/47] net/bnxt: tf_ulp: support a few feature extensions Sriharsha Basavapatna
2024-10-01 5:58 ` [PATCH v3 47/47] net/bnxt: tf_ulp: add stats cache for thor2 Sriharsha Basavapatna
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