From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 516D345A74; Tue, 1 Oct 2024 08:02:03 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1A00E40B92; Tue, 1 Oct 2024 08:01:33 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 1E8EF40A7F for ; Tue, 1 Oct 2024 08:01:30 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4914DbnO023533 for ; Mon, 30 Sep 2024 23:01:30 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=9 rL6K+lFuWo3544bKt4fvdsyIFx7ppLbyM47zWmYaBY=; b=QrjAWaZVYI1CplHGH QsAqBj8Nm74mON2jL+xN/VVFyLgd/SFyvJns43AOUjn3I8RuSM1nJv0irB6/l4vO VJOE0qXbkjqRfLuAoPlWIQJTKVvQ7ODo6S1afz0iTuuLWNpdUoYMCCgTpxHYDyWe aFO1qM6T1soqxynA0hFedALIFf3NyRsxoktkdc/x9kRPtaJfkB52szbR/rMZaOOh Y5zsHmRtmSKHT4JiM9YwgvBDaZmNK5fwHHY8WEEfM1fOGECD4mcTl0DRQ6cUu5hg MO2bKWlhHISHaorhN+SXZ/HIORHLWRz96iju4I8kaInpcSqUAIe3Jqnb9pN53V9Y IiIwA== Received: from dc5-exch05.marvell.com ([199.233.59.128]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 41xf5m2eq4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 30 Sep 2024 23:01:29 -0700 (PDT) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 30 Sep 2024 23:01:28 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Mon, 30 Sep 2024 23:01:28 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 0EAD93F7070; Mon, 30 Sep 2024 23:01:24 -0700 (PDT) From: Nithin Dabilpuram To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao , Harman Kalra CC: Subject: [PATCH v2 09/17] common/cnxk: add flush wait after write of inline ctx Date: Tue, 1 Oct 2024 11:30:47 +0530 Message-ID: <20241001060055.3747591-9-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241001060055.3747591-1-ndabilpuram@marvell.com> References: <20241001060055.3747591-1-ndabilpuram@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: DqZXnyPTjOpAw6i2MIA_cWkX_78BKpVe X-Proofpoint-GUID: DqZXnyPTjOpAw6i2MIA_cWkX_78BKpVe X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Reading a CPT_LF_CTX_ERR csr will ensure writes for FLUSH are complete and also tell whether flush is complete or not. Signed-off-by: Nithin Dabilpuram --- drivers/common/cnxk/roc_nix_inl.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c index a984ac56d9..d0328921a7 100644 --- a/drivers/common/cnxk/roc_nix_inl.c +++ b/drivers/common/cnxk/roc_nix_inl.c @@ -1748,6 +1748,7 @@ roc_nix_inl_ctx_write(struct roc_nix *roc_nix, void *sa_dptr, void *sa_cptr, struct nix_inl_dev *inl_dev = NULL; struct roc_cpt_lf *outb_lf = NULL; union cpt_lf_ctx_flush flush; + union cpt_lf_ctx_err err; bool get_inl_lf = true; uintptr_t rbase; struct nix *nix; @@ -1789,6 +1790,13 @@ roc_nix_inl_ctx_write(struct roc_nix *roc_nix, void *sa_dptr, void *sa_cptr, flush.s.cptr = ((uintptr_t)sa_cptr) >> 7; plt_write64(flush.u, rbase + CPT_LF_CTX_FLUSH); + plt_atomic_thread_fence(__ATOMIC_ACQ_REL); + + /* Read a CSR to ensure that the FLUSH operation is complete */ + err.u = plt_read64(rbase + CPT_LF_CTX_ERR); + + if (err.s.flush_st_flt) + plt_warn("CTX flush could not complete"); return 0; } plt_nix_dbg("Could not get CPT LF for CTX write"); -- 2.34.1