From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id EE49F45A76; Tue, 1 Oct 2024 08:14:57 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5FE6940B97; Tue, 1 Oct 2024 08:14:41 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 4751F40DCE for ; Tue, 1 Oct 2024 08:14:39 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 48UNtA9e000399; Mon, 30 Sep 2024 23:14:38 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=7 8hcAOPWh1CSF+Rl9f33JUBuOj7K/QUURUCX0Hf7fcw=; b=gnC1lG3SAcXf5GT1w 2ENMMUiCMfHBCBuLbQbZEvoop/NZKFFm1OQ8bCn5tPpS5rTp29Oo2hwZkoWRIWEp ZwOy6Bl1XZ1C9A6Sruiuooa9HJLZlcuaZtf/WmuDloPC1P9J0uvLGJ8cTtqUDNfx cny2CSlTLyM9zsEQ4feIzC1vrb2N4DrydmC9kK4bZWel3fengf2reUp3jyau8OOQ AjufPNeoeScx0f7dFg2Ht66ueezBSmJzfD+Mp8ugJ/WYa8ML3ommvUnHkZCg+6hB a4cJMhv+SCcSKNizvk/JHBoJPBerxR822Iyr3zcFrslsqukPOHlcaE9Yv/eGHfwD /AbFw== Received: from dc6wp-exch02.marvell.com ([4.21.29.225]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 41xf5m2gxj-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 30 Sep 2024 23:14:38 -0700 (PDT) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 30 Sep 2024 23:14:37 -0700 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Mon, 30 Sep 2024 23:14:36 -0700 Received: from MININT-80QBFE8.corp.innovium.com (MININT-80QBFE8.marvell.com [10.28.164.106]) by maili.marvell.com (Postfix) with ESMTP id 503CF3F7066; Mon, 30 Sep 2024 23:14:32 -0700 (PDT) From: To: , , , , , , , , , Pavan Nikhilesh CC: Subject: [PATCH v3 4/6] event/cnkx: add pre-schedule support Date: Tue, 1 Oct 2024 11:44:09 +0530 Message-ID: <20241001061411.2537-5-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241001061411.2537-1-pbhagavatula@marvell.com> References: <20240917071106.8815-1-pbhagavatula@marvell.com> <20241001061411.2537-1-pbhagavatula@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: bXzTdVl9vOuIyRPm6c3GqdUvEFBUO-7z X-Proofpoint-GUID: bXzTdVl9vOuIyRPm6c3GqdUvEFBUO-7z X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Pavan Nikhilesh Add device level and port level pre-schedule support for cnxk eventdev. Signed-off-by: Pavan Nikhilesh --- doc/guides/eventdevs/features/cnxk.ini | 1 + drivers/event/cnxk/cn10k_eventdev.c | 40 ++++++++++++++++++++++++-- drivers/event/cnxk/cnxk_eventdev.c | 2 -- drivers/event/cnxk/cnxk_eventdev.h | 1 - 4 files changed, 39 insertions(+), 5 deletions(-) diff --git a/doc/guides/eventdevs/features/cnxk.ini b/doc/guides/eventdevs/features/cnxk.ini index d1516372fa..5ba528f086 100644 --- a/doc/guides/eventdevs/features/cnxk.ini +++ b/doc/guides/eventdevs/features/cnxk.ini @@ -17,6 +17,7 @@ carry_flow_id = Y maintenance_free = Y runtime_queue_attr = Y profile_links = Y +preschedule = Y [Eth Rx adapter Features] internal_port = Y diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c index 2d7b169974..0624f29a90 100644 --- a/drivers/event/cnxk/cn10k_eventdev.c +++ b/drivers/event/cnxk/cn10k_eventdev.c @@ -18,6 +18,27 @@ #define CN10K_SET_EVDEV_ENQ_OP(dev, enq_op, enq_ops) \ enq_op = enq_ops[dev->tx_offloads & (NIX_TX_OFFLOAD_MAX - 1)] +static int +cn10k_sso_hws_preschedule_modify(void *port, rte_event_dev_preschedule_type_t type) +{ + struct cn10k_sso_hws *ws = port; + + ws->gw_wdata &= (BIT(19) | BIT(20)); + switch (type) { + default: + case RTE_EVENT_DEV_PRESCHEDULE_NONE: + break; + case RTE_EVENT_DEV_PRESCHEDULE: + ws->gw_wdata |= BIT(19); + break; + case RTE_EVENT_DEV_PRESCHEDULE_ADAPTIVE: + ws->gw_wdata |= BIT(19) | BIT(20); + break; + } + + return 0; +} + static uint32_t cn10k_sso_gw_mode_wdata(struct cnxk_sso_evdev *dev) { @@ -527,6 +548,7 @@ cn10k_sso_fp_fns_set(struct rte_eventdev *event_dev) event_dev->dma_enqueue = cn10k_dma_adapter_enqueue; event_dev->profile_switch = cn10k_sso_hws_profile_switch; + event_dev->preschedule_modify = cn10k_sso_hws_preschedule_modify; #else RTE_SET_USED(event_dev); #endif @@ -541,6 +563,9 @@ cn10k_sso_info_get(struct rte_eventdev *event_dev, dev_info->driver_name = RTE_STR(EVENTDEV_NAME_CN10K_PMD); cnxk_sso_info_get(dev, dev_info); dev_info->max_event_port_enqueue_depth = UINT32_MAX; + dev_info->event_dev_cap |= RTE_EVENT_DEV_CAP_EVENT_PRESCHEDULE | + RTE_EVENT_DEV_CAP_EVENT_PRESCHEDULE_ADAPTIVE | + RTE_EVENT_DEV_CAP_EVENT_PER_PORT_PRESCHEDULE; } static int @@ -566,6 +591,19 @@ cn10k_sso_dev_configure(const struct rte_eventdev *event_dev) if (rc < 0) goto cnxk_rsrc_fini; + switch (event_dev->data->dev_conf.preschedule_type) { + default: + case RTE_EVENT_DEV_PRESCHEDULE_NONE: + dev->gw_mode = CN10K_GW_MODE_NONE; + break; + case RTE_EVENT_DEV_PRESCHEDULE: + dev->gw_mode = CN10K_GW_MODE_PREF; + break; + case RTE_EVENT_DEV_PRESCHEDULE_ADAPTIVE: + dev->gw_mode = CN10K_GW_MODE_PREF_WFE; + break; + } + rc = cnxk_setup_event_ports(event_dev, cn10k_sso_init_hws_mem, cn10k_sso_hws_setup); if (rc < 0) @@ -1199,7 +1237,6 @@ cn10k_sso_init(struct rte_eventdev *event_dev) return 0; } - dev->gw_mode = CN10K_GW_MODE_PREF_WFE; rc = cnxk_sso_init(event_dev); if (rc < 0) return rc; @@ -1256,7 +1293,6 @@ RTE_PMD_REGISTER_KMOD_DEP(event_cn10k, "vfio-pci"); RTE_PMD_REGISTER_PARAM_STRING(event_cn10k, CNXK_SSO_XAE_CNT "=" CNXK_SSO_GGRP_QOS "=" CNXK_SSO_FORCE_BP "=1" - CN10K_SSO_GW_MODE "=" CN10K_SSO_STASH "=" CNXK_TIM_DISABLE_NPA "=1" CNXK_TIM_CHNK_SLOTS "=" diff --git a/drivers/event/cnxk/cnxk_eventdev.c b/drivers/event/cnxk/cnxk_eventdev.c index 4b2d6bffa6..c1df481827 100644 --- a/drivers/event/cnxk/cnxk_eventdev.c +++ b/drivers/event/cnxk/cnxk_eventdev.c @@ -624,8 +624,6 @@ cnxk_sso_parse_devargs(struct cnxk_sso_evdev *dev, struct rte_devargs *devargs) &dev->force_ena_bp); rte_kvargs_process(kvlist, CN9K_SSO_SINGLE_WS, &parse_kvargs_flag, &single_ws); - rte_kvargs_process(kvlist, CN10K_SSO_GW_MODE, &parse_kvargs_value, - &dev->gw_mode); rte_kvargs_process(kvlist, CN10K_SSO_STASH, &parse_sso_kvargs_stash_dict, dev); dev->dual_ws = !single_ws; diff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h index ece49394e7..f147ef3c78 100644 --- a/drivers/event/cnxk/cnxk_eventdev.h +++ b/drivers/event/cnxk/cnxk_eventdev.h @@ -30,7 +30,6 @@ #define CNXK_SSO_GGRP_QOS "qos" #define CNXK_SSO_FORCE_BP "force_rx_bp" #define CN9K_SSO_SINGLE_WS "single_ws" -#define CN10K_SSO_GW_MODE "gw_mode" #define CN10K_SSO_STASH "stash" #define CNXK_SSO_MAX_PROFILES 2 -- 2.25.1