From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3D4B045A7A; Tue, 1 Oct 2024 14:41:19 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B7F6040664; Tue, 1 Oct 2024 14:41:15 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 5B24440651 for ; Tue, 1 Oct 2024 14:41:13 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 49192LXT000750 for ; Tue, 1 Oct 2024 05:41:12 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=l sXg4Yl9iiFMOdUwBMVbKir5nAQTlx/XkI7tcphdAGU=; b=d+Dk+FiYdyFABqfqP XRrcGV6HATgbrZ9DazxLtgnshwt4V5iPo+MW1a3rEr2fD2VgZruFqP1BKS6YeUsK +aQoWrYajXCbyFt8Y/J/w0U/aHsIt1lkKEZ4KU8+1Y5BP+S31xYUkDF+YWJP6NZq B9k3KpKUJAtm0hOkflXcVYSWHUjO2bp9MkRjmrPPFx9+pSy9lCjzQORD61ISkH2y LAzS/QhON3xPkYdDQsYgd/PpydFU1yeeR1lvKQKs8vP21+Q+o/8TmcAIzBbRSud2 rd3PEb+B24/uX2LO7IIJCg74F4IDG7BrHJ3MjWnZpQUDSeTPqj0NebWsLpNknS5+ wGVzQ== Received: from dc5-exch05.marvell.com ([199.233.59.128]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 41yt6gdjb2-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 01 Oct 2024 05:41:12 -0700 (PDT) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 1 Oct 2024 05:41:11 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Tue, 1 Oct 2024 05:41:11 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 3A26A5C68E6; Tue, 1 Oct 2024 05:41:07 -0700 (PDT) From: Nithin Dabilpuram To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao , Harman Kalra CC: , Ashwin Sekhar T K Subject: [PATCH v3 02/18] common/cnxk: accommodate change in aura field width Date: Tue, 1 Oct 2024 18:10:37 +0530 Message-ID: <20241001124053.3774325-3-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241001124053.3774325-1-ndabilpuram@marvell.com> References: <20240910085909.1514457-1-ndabilpuram@marvell.com> <20241001124053.3774325-1-ndabilpuram@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: CoUZW1GUyOjuCKtkeMjXwAn5j_MGwf83 X-Proofpoint-ORIG-GUID: CoUZW1GUyOjuCKtkeMjXwAn5j_MGwf83 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Ashwin Sekhar T K Aura field width has changed from 20 bits to 17 bits in cn20k. Adjust the bit fields accordingly for register reads/writes. Signed-off-by: Ashwin Sekhar T K --- drivers/common/cnxk/roc_npa.h | 24 ++++++++++++++++-------- 1 file changed, 16 insertions(+), 8 deletions(-) diff --git a/drivers/common/cnxk/roc_npa.h b/drivers/common/cnxk/roc_npa.h index 4ad5f044b5..fbf75b2fca 100644 --- a/drivers/common/cnxk/roc_npa.h +++ b/drivers/common/cnxk/roc_npa.h @@ -16,6 +16,7 @@ #else #include "roc_io_generic.h" #endif +#include "roc_model.h" #include "roc_npa_dp.h" #define ROC_AURA_OP_LIMIT_MASK (BIT_ULL(36) - 1) @@ -68,11 +69,12 @@ roc_npa_aura_op_alloc(uint64_t aura_handle, const int drop) static inline uint64_t roc_npa_aura_op_cnt_get(uint64_t aura_handle) { - uint64_t wdata; + uint64_t wdata, shift; int64_t *addr; uint64_t reg; - wdata = roc_npa_aura_handle_to_aura(aura_handle) << 44; + shift = roc_model_is_cn20k() ? 47 : 44; + wdata = roc_npa_aura_handle_to_aura(aura_handle) << shift; addr = (int64_t *)(roc_npa_aura_handle_to_base(aura_handle) + NPA_LF_AURA_OP_CNT); reg = roc_atomic64_add_nosync(wdata, addr); @@ -87,11 +89,13 @@ static inline void roc_npa_aura_op_cnt_set(uint64_t aura_handle, const int sign, uint64_t count) { uint64_t reg = count & (BIT_ULL(36) - 1); + uint64_t shift; if (sign) reg |= BIT_ULL(43); /* CNT_ADD */ - reg |= (roc_npa_aura_handle_to_aura(aura_handle) << 44); + shift = roc_model_is_cn20k() ? 47 : 44; + reg |= (roc_npa_aura_handle_to_aura(aura_handle) << shift); plt_write64(reg, roc_npa_aura_handle_to_base(aura_handle) + NPA_LF_AURA_OP_CNT); @@ -100,11 +104,12 @@ roc_npa_aura_op_cnt_set(uint64_t aura_handle, const int sign, uint64_t count) static inline uint64_t roc_npa_aura_op_limit_get(uint64_t aura_handle) { - uint64_t wdata; + uint64_t wdata, shift; int64_t *addr; uint64_t reg; - wdata = roc_npa_aura_handle_to_aura(aura_handle) << 44; + shift = roc_model_is_cn20k() ? 47 : 44; + wdata = roc_npa_aura_handle_to_aura(aura_handle) << shift; addr = (int64_t *)(roc_npa_aura_handle_to_base(aura_handle) + NPA_LF_AURA_OP_LIMIT); reg = roc_atomic64_add_nosync(wdata, addr); @@ -119,8 +124,10 @@ static inline void roc_npa_aura_op_limit_set(uint64_t aura_handle, uint64_t limit) { uint64_t reg = limit & ROC_AURA_OP_LIMIT_MASK; + uint64_t shift; - reg |= (roc_npa_aura_handle_to_aura(aura_handle) << 44); + shift = roc_model_is_cn20k() ? 47 : 44; + reg |= (roc_npa_aura_handle_to_aura(aura_handle) << shift); plt_write64(reg, roc_npa_aura_handle_to_base(aura_handle) + NPA_LF_AURA_OP_LIMIT); @@ -129,11 +136,12 @@ roc_npa_aura_op_limit_set(uint64_t aura_handle, uint64_t limit) static inline uint64_t roc_npa_aura_op_available(uint64_t aura_handle) { - uint64_t wdata; + uint64_t wdata, shift; uint64_t reg; int64_t *addr; - wdata = roc_npa_aura_handle_to_aura(aura_handle) << 44; + shift = roc_model_is_cn20k() ? 47 : 44; + wdata = roc_npa_aura_handle_to_aura(aura_handle) << shift; addr = (int64_t *)(roc_npa_aura_handle_to_base(aura_handle) + NPA_LF_POOL_OP_AVAILABLE); reg = roc_atomic64_add_nosync(wdata, addr); -- 2.34.1