From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6F2D545AA0; Thu, 3 Oct 2024 15:24:09 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EF2A640663; Thu, 3 Oct 2024 15:23:15 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id EA8E2406B7 for ; Thu, 3 Oct 2024 15:23:14 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 492Hl3kf009666 for ; Thu, 3 Oct 2024 06:23:14 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=+ 0C18Z7zq8kuKmie3ZY3UnXBcNA2jYVDkF7e4Gishes=; b=b4t+sDcc63gxcxNsO g/VQStbJELDBf/mOPMhE5tk/jEFdHrRa3gFj3SFY1uH4jaI1zSwrusDBpNL/GFEJ eegHhZl6SQPQnBk8/sXxJS+YKNjoj5EgB/Ps9QmVlPVGYgy5wzkvF58CoXuChSxQ 5J+XKbACLtKLkHfn7cHsQ1O2n57eaqaVUB7hOA4SUwASgmoQhC8GpgcbdXeSOI5w eJ4D0GvZeCU5aIPM3+HYOnhKDozJiZLrj6jd/J11CPSAn3dheKTegRKWj6TIw+ab xewhVg8JEjwuyGoeab78q6D3IltS8XA2D9ORQNycOxREKBHyfJ2OB7POQOr3J0Fg abIwg== Received: from dc5-exch05.marvell.com ([199.233.59.128]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 421avd9sje-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 03 Oct 2024 06:23:13 -0700 (PDT) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 3 Oct 2024 06:23:13 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Thu, 3 Oct 2024 06:23:13 -0700 Received: from MININT-80QBFE8.corp.innovium.com (MININT-80QBFE8.marvell.com [10.28.164.106]) by maili.marvell.com (Postfix) with ESMTP id 5D1195C704D; Thu, 3 Oct 2024 06:23:11 -0700 (PDT) From: To: , Pavan Nikhilesh , "Shijith Thotton" CC: Subject: [PATCH 13/20] event/cnxk: support CN20K Rx adapter Date: Thu, 3 Oct 2024 18:52:30 +0530 Message-ID: <20241003132237.20193-13-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241003132237.20193-1-pbhagavatula@marvell.com> References: <20241003132237.20193-1-pbhagavatula@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: p6PoCx2ciwk7j6ON1tdNNgLufAI9_mve X-Proofpoint-ORIG-GUID: p6PoCx2ciwk7j6ON1tdNNgLufAI9_mve X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Pavan Nikhilesh Add support for CN20K event eth Rx adapter. Signed-off-by: Pavan Nikhilesh --- drivers/event/cnxk/cn20k_eventdev.c | 122 +++++++++++++++++++++++++++- drivers/event/cnxk/cn20k_eventdev.h | 4 + 2 files changed, 125 insertions(+), 1 deletion(-) diff --git a/drivers/event/cnxk/cn20k_eventdev.c b/drivers/event/cnxk/cn20k_eventdev.c index e4fecc3e32..a3ef7f8747 100644 --- a/drivers/event/cnxk/cn20k_eventdev.c +++ b/drivers/event/cnxk/cn20k_eventdev.c @@ -4,6 +4,7 @@ #include "roc_api.h" +#include "cn20k_ethdev.h" #include "cn20k_eventdev.h" #include "cn20k_worker.h" #include "cnxk_common.h" @@ -412,6 +413,118 @@ cn20k_sso_selftest(void) return cnxk_sso_selftest(RTE_STR(event_cn20k)); } +static int +cn20k_sso_rx_adapter_caps_get(const struct rte_eventdev *event_dev, + const struct rte_eth_dev *eth_dev, uint32_t *caps) +{ + int rc; + + RTE_SET_USED(event_dev); + rc = strncmp(eth_dev->device->driver->name, "net_cn20k", 9); + if (rc) + *caps = RTE_EVENT_ETH_RX_ADAPTER_SW_CAP; + else + *caps = RTE_EVENT_ETH_RX_ADAPTER_CAP_INTERNAL_PORT | + RTE_EVENT_ETH_RX_ADAPTER_CAP_MULTI_EVENTQ | + RTE_EVENT_ETH_RX_ADAPTER_CAP_OVERRIDE_FLOW_ID; + + return 0; +} + +static void +cn20k_sso_set_priv_mem(const struct rte_eventdev *event_dev, void *lookup_mem) +{ + struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev); + int i; + + for (i = 0; i < dev->nb_event_ports; i++) { + struct cn20k_sso_hws *ws = event_dev->data->ports[i]; + ws->xaq_lmt = dev->xaq_lmt; + ws->fc_mem = (int64_t *)dev->fc_iova; + ws->tstamp = dev->tstamp; + if (lookup_mem) + ws->lookup_mem = lookup_mem; + } +} + +static void +eventdev_fops_tstamp_update(struct rte_eventdev *event_dev) +{ + struct rte_event_fp_ops *fp_op = rte_event_fp_ops + event_dev->data->dev_id; + + fp_op->dequeue = event_dev->dequeue; + fp_op->dequeue_burst = event_dev->dequeue_burst; +} + +static void +cn20k_sso_tstamp_hdl_update(uint16_t port_id, uint16_t flags, bool ptp_en) +{ + struct rte_eth_dev *dev = &rte_eth_devices[port_id]; + struct cnxk_eth_dev *cnxk_eth_dev = dev->data->dev_private; + struct rte_eventdev *event_dev = cnxk_eth_dev->evdev_priv; + struct cnxk_sso_evdev *evdev = cnxk_sso_pmd_priv(event_dev); + + evdev->rx_offloads |= flags; + if (ptp_en) + evdev->tstamp[port_id] = &cnxk_eth_dev->tstamp; + else + evdev->tstamp[port_id] = NULL; + cn20k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev); + eventdev_fops_tstamp_update(event_dev); +} + +static int +cn20k_sso_rx_adapter_queue_add(const struct rte_eventdev *event_dev, + const struct rte_eth_dev *eth_dev, int32_t rx_queue_id, + const struct rte_event_eth_rx_adapter_queue_conf *queue_conf) +{ + struct cnxk_eth_dev *cnxk_eth_dev = eth_dev->data->dev_private; + struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev); + struct roc_sso_hwgrp_stash stash; + struct cn20k_eth_rxq *rxq; + void *lookup_mem; + int rc; + + rc = strncmp(eth_dev->device->driver->name, "net_cn20k", 8); + if (rc) + return -EINVAL; + + rc = cnxk_sso_rx_adapter_queue_add(event_dev, eth_dev, rx_queue_id, queue_conf); + if (rc) + return -EINVAL; + + cnxk_eth_dev->cnxk_sso_ptp_tstamp_cb = cn20k_sso_tstamp_hdl_update; + cnxk_eth_dev->evdev_priv = (struct rte_eventdev *)(uintptr_t)event_dev; + + rxq = eth_dev->data->rx_queues[0]; + lookup_mem = rxq->lookup_mem; + cn20k_sso_set_priv_mem(event_dev, lookup_mem); + cn20k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev); + if (roc_feature_sso_has_stash() && dev->nb_event_ports > 1) { + stash.hwgrp = queue_conf->ev.queue_id; + stash.stash_offset = CN20K_SSO_DEFAULT_STASH_OFFSET; + stash.stash_count = CN20K_SSO_DEFAULT_STASH_LENGTH; + rc = roc_sso_hwgrp_stash_config(&dev->sso, &stash, 1); + if (rc < 0) + plt_warn("failed to configure HWGRP WQE stashing rc = %d", rc); + } + + return 0; +} + +static int +cn20k_sso_rx_adapter_queue_del(const struct rte_eventdev *event_dev, + const struct rte_eth_dev *eth_dev, int32_t rx_queue_id) +{ + int rc; + + rc = strncmp(eth_dev->device->driver->name, "net_cn20k", 8); + if (rc) + return -EINVAL; + + return cnxk_sso_rx_adapter_queue_del(event_dev, eth_dev, rx_queue_id); +} + static struct eventdev_ops cn20k_sso_dev_ops = { .dev_infos_get = cn20k_sso_info_get, .dev_configure = cn20k_sso_dev_configure, @@ -431,6 +544,12 @@ static struct eventdev_ops cn20k_sso_dev_ops = { .port_unlink_profile = cn20k_sso_port_unlink_profile, .timeout_ticks = cnxk_sso_timeout_ticks, + .eth_rx_adapter_caps_get = cn20k_sso_rx_adapter_caps_get, + .eth_rx_adapter_queue_add = cn20k_sso_rx_adapter_queue_add, + .eth_rx_adapter_queue_del = cn20k_sso_rx_adapter_queue_del, + .eth_rx_adapter_start = cnxk_sso_rx_adapter_start, + .eth_rx_adapter_stop = cnxk_sso_rx_adapter_stop, + .xstats_get = cnxk_sso_xstats_get, .xstats_reset = cnxk_sso_xstats_reset, .xstats_get_names = cnxk_sso_xstats_get_names, @@ -509,4 +628,5 @@ RTE_PMD_REGISTER_PARAM_STRING(event_cn20k, CNXK_SSO_XAE_CNT "=" CNXK_SSO_GGRP_QOS "=" CNXK_SSO_STASH "=" - CNXK_SSO_GW_MODE "="); + CNXK_SSO_GW_MODE "=" + CNXK_SSO_FORCE_BP "=1"); diff --git a/drivers/event/cnxk/cn20k_eventdev.h b/drivers/event/cnxk/cn20k_eventdev.h index 50a9df77cb..ce12628f81 100644 --- a/drivers/event/cnxk/cn20k_eventdev.h +++ b/drivers/event/cnxk/cn20k_eventdev.h @@ -11,9 +11,13 @@ struct __rte_cache_aligned cn20k_sso_hws { uint64_t base; uint32_t gw_wdata; + void *lookup_mem; uint64_t gw_rdata; uint8_t swtag_req; uint8_t hws_id; + /* PTP timestamp */ + struct cnxk_timesync_info **tstamp; + uint64_t meta_aura; /* Add Work Fastpath data */ alignas(RTE_CACHE_LINE_SIZE) int64_t *fc_mem; int64_t *fc_cache_space; -- 2.25.1