From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 12AB645AA0; Thu, 3 Oct 2024 15:24:24 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 457C340A67; Thu, 3 Oct 2024 15:23:23 +0200 (CEST) Received: from mx0a-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 0E6DF4064E for ; Thu, 3 Oct 2024 15:23:21 +0200 (CEST) Received: from pps.filterd (m0431384.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4935MlBD011655 for ; Thu, 3 Oct 2024 06:23:21 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=1 jrWSkBj8R0KUbZoWeB31ROv34NlN2bjfjgwDRt0IrM=; b=MQuMqaXFe5rSkk5aY 04I54hnOm3CsB724ZKQEjXOaxOFtOU9FMcftCP2oIPEV77Fx4s6VNBZBo85A6vM3 K/N3qKOr92BULpURhDiw4XyTDI+tLia8Tla4KIC1c7glhqSIUxk6FP5sevcGT+HK kOTvC8oa1T0Q+mkZo6bbhC51oJRGEq5eO0erA8eo+85uBk78IN3XW0bo/KBWUy+p /w0c78ffQchf1ACOYTT/4afg1xm/4xUaVu9JaABkrbS2rG4bhmLR073+r9PtAy5J 2f9nR5Yv+EqLdH4mRxiESxBCFKuKw+M14HUwfIDEsIJhmQu3jKYIXItxJXMa5fVT Qv3DA== Received: from dc5-exch05.marvell.com ([199.233.59.128]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 421b3g1qqm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 03 Oct 2024 06:23:19 -0700 (PDT) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 3 Oct 2024 06:23:18 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Thu, 3 Oct 2024 06:23:18 -0700 Received: from MININT-80QBFE8.corp.innovium.com (MININT-80QBFE8.marvell.com [10.28.164.106]) by maili.marvell.com (Postfix) with ESMTP id B98ED5C7050; Thu, 3 Oct 2024 06:23:16 -0700 (PDT) From: To: , Pavan Nikhilesh , "Shijith Thotton" CC: Subject: [PATCH 15/20] event/cnxk: support CN20K Tx adapter Date: Thu, 3 Oct 2024 18:52:32 +0530 Message-ID: <20241003132237.20193-15-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241003132237.20193-1-pbhagavatula@marvell.com> References: <20241003132237.20193-1-pbhagavatula@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: jEjgFkhkrK55cJ8unnJ8T3TkvotS-PBg X-Proofpoint-GUID: jEjgFkhkrK55cJ8unnJ8T3TkvotS-PBg X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.687,Hydra:6.0.235,FMLib:17.0.607.475 definitions=2020-10-13_15,2020-10-13_02,2020-04-07_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Pavan Nikhilesh Add support for event eth Tx adapter. Signed-off-by: Pavan Nikhilesh --- drivers/event/cnxk/cn20k_eventdev.c | 126 +++++++++++++++++++++++++++ drivers/event/cnxk/cn20k_eventdev.h | 4 + drivers/event/cnxk/cn20k_tx_worker.h | 16 ++++ 3 files changed, 146 insertions(+) create mode 100644 drivers/event/cnxk/cn20k_tx_worker.h diff --git a/drivers/event/cnxk/cn20k_eventdev.c b/drivers/event/cnxk/cn20k_eventdev.c index f5be3f3e89..06cf201146 100644 --- a/drivers/event/cnxk/cn20k_eventdev.c +++ b/drivers/event/cnxk/cn20k_eventdev.c @@ -6,6 +6,7 @@ #include "cn20k_ethdev.h" #include "cn20k_eventdev.h" +#include "cn20k_tx_worker.h" #include "cn20k_worker.h" #include "cnxk_common.h" #include "cnxk_eventdev.h" @@ -166,6 +167,35 @@ cn20k_sso_rsrc_init(void *arg, uint8_t hws, uint8_t hwgrp) return roc_sso_rsrc_init(&dev->sso, hws, hwgrp, nb_tim_lfs); } +static int +cn20k_sso_updt_tx_adptr_data(const struct rte_eventdev *event_dev) +{ + struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev); + int i; + + if (dev->tx_adptr_data == NULL) + return 0; + + for (i = 0; i < dev->nb_event_ports; i++) { + struct cn20k_sso_hws *ws = event_dev->data->ports[i]; + void *ws_cookie; + + ws_cookie = cnxk_sso_hws_get_cookie(ws); + ws_cookie = rte_realloc_socket(ws_cookie, + sizeof(struct cnxk_sso_hws_cookie) + + sizeof(struct cn20k_sso_hws) + + dev->tx_adptr_data_sz, + RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); + if (ws_cookie == NULL) + return -ENOMEM; + ws = RTE_PTR_ADD(ws_cookie, sizeof(struct cnxk_sso_hws_cookie)); + memcpy(&ws->tx_adptr_data, dev->tx_adptr_data, dev->tx_adptr_data_sz); + event_dev->data->ports[i] = ws; + } + + return 0; +} + #if defined(RTE_ARCH_ARM64) static inline void cn20k_sso_fp_tmplt_fns_set(struct rte_eventdev *event_dev) @@ -697,6 +727,95 @@ cn20k_sso_rx_adapter_queue_del(const struct rte_eventdev *event_dev, return cnxk_sso_rx_adapter_queue_del(event_dev, eth_dev, rx_queue_id); } +static int +cn20k_sso_tx_adapter_caps_get(const struct rte_eventdev *dev, const struct rte_eth_dev *eth_dev, + uint32_t *caps) +{ + int ret; + + RTE_SET_USED(dev); + ret = strncmp(eth_dev->device->driver->name, "net_cn20k", 8); + if (ret) + *caps = 0; + else + *caps = RTE_EVENT_ETH_TX_ADAPTER_CAP_INTERNAL_PORT; + + return 0; +} + +static void +cn20k_sso_txq_fc_update(const struct rte_eth_dev *eth_dev, int32_t tx_queue_id) +{ + struct cnxk_eth_dev *cnxk_eth_dev = eth_dev->data->dev_private; + struct cn20k_eth_txq *txq; + struct roc_nix_sq *sq; + int i; + + if (tx_queue_id < 0) { + for (i = 0; i < eth_dev->data->nb_tx_queues; i++) + cn20k_sso_txq_fc_update(eth_dev, i); + } else { + uint16_t sqes_per_sqb; + + sq = &cnxk_eth_dev->sqs[tx_queue_id]; + txq = eth_dev->data->tx_queues[tx_queue_id]; + sqes_per_sqb = 1U << txq->sqes_per_sqb_log2; + if (cnxk_eth_dev->tx_offloads & RTE_ETH_TX_OFFLOAD_SECURITY) + sq->nb_sqb_bufs_adj -= (cnxk_eth_dev->outb.nb_desc / sqes_per_sqb); + txq->nb_sqb_bufs_adj = sq->nb_sqb_bufs_adj; + } +} + +static int +cn20k_sso_tx_adapter_queue_add(uint8_t id, const struct rte_eventdev *event_dev, + const struct rte_eth_dev *eth_dev, int32_t tx_queue_id) +{ + struct cnxk_eth_dev *cnxk_eth_dev = eth_dev->data->dev_private; + struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev); + uint64_t tx_offloads; + int rc; + + RTE_SET_USED(id); + rc = cnxk_sso_tx_adapter_queue_add(event_dev, eth_dev, tx_queue_id); + if (rc < 0) + return rc; + + /* Can't enable tstamp if all the ports don't have it enabled. */ + tx_offloads = cnxk_eth_dev->tx_offload_flags; + if (dev->tx_adptr_configured) { + uint8_t tstmp_req = !!(tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F); + uint8_t tstmp_ena = !!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F); + + if (tstmp_ena && !tstmp_req) + dev->tx_offloads &= ~(NIX_TX_OFFLOAD_TSTAMP_F); + else if (!tstmp_ena && tstmp_req) + tx_offloads &= ~(NIX_TX_OFFLOAD_TSTAMP_F); + } + + dev->tx_offloads |= tx_offloads; + cn20k_sso_txq_fc_update(eth_dev, tx_queue_id); + rc = cn20k_sso_updt_tx_adptr_data(event_dev); + if (rc < 0) + return rc; + cn20k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev); + dev->tx_adptr_configured = 1; + + return 0; +} + +static int +cn20k_sso_tx_adapter_queue_del(uint8_t id, const struct rte_eventdev *event_dev, + const struct rte_eth_dev *eth_dev, int32_t tx_queue_id) +{ + int rc; + + RTE_SET_USED(id); + rc = cnxk_sso_tx_adapter_queue_del(event_dev, eth_dev, tx_queue_id); + if (rc < 0) + return rc; + return cn20k_sso_updt_tx_adptr_data(event_dev); +} + static struct eventdev_ops cn20k_sso_dev_ops = { .dev_infos_get = cn20k_sso_info_get, .dev_configure = cn20k_sso_dev_configure, @@ -722,6 +841,13 @@ static struct eventdev_ops cn20k_sso_dev_ops = { .eth_rx_adapter_start = cnxk_sso_rx_adapter_start, .eth_rx_adapter_stop = cnxk_sso_rx_adapter_stop, + .eth_tx_adapter_caps_get = cn20k_sso_tx_adapter_caps_get, + .eth_tx_adapter_queue_add = cn20k_sso_tx_adapter_queue_add, + .eth_tx_adapter_queue_del = cn20k_sso_tx_adapter_queue_del, + .eth_tx_adapter_start = cnxk_sso_tx_adapter_start, + .eth_tx_adapter_stop = cnxk_sso_tx_adapter_stop, + .eth_tx_adapter_free = cnxk_sso_tx_adapter_free, + .xstats_get = cnxk_sso_xstats_get, .xstats_reset = cnxk_sso_xstats_reset, .xstats_get_names = cnxk_sso_xstats_get_names, diff --git a/drivers/event/cnxk/cn20k_eventdev.h b/drivers/event/cnxk/cn20k_eventdev.h index ce12628f81..8623f790a2 100644 --- a/drivers/event/cnxk/cn20k_eventdev.h +++ b/drivers/event/cnxk/cn20k_eventdev.h @@ -24,6 +24,10 @@ struct __rte_cache_aligned cn20k_sso_hws { uintptr_t aw_lmt; uintptr_t grp_base; int32_t xaq_lmt; + /* Tx Fastpath data */ + alignas(RTE_CACHE_LINE_SIZE) uintptr_t lmt_base; + uint64_t lso_tun_fmt; + uint8_t tx_adptr_data[]; }; #endif /* __CN20K_EVENTDEV_H__ */ diff --git a/drivers/event/cnxk/cn20k_tx_worker.h b/drivers/event/cnxk/cn20k_tx_worker.h new file mode 100644 index 0000000000..63fbdf5328 --- /dev/null +++ b/drivers/event/cnxk/cn20k_tx_worker.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2024 Marvell. + */ + +#ifndef __CN20K_TX_WORKER_H__ +#define __CN20K_TX_WORKER_H__ + +#include +#include + +#include "cn20k_eventdev.h" +#include "cn20k_tx.h" +#include "cnxk_eventdev_dp.h" +#include + +#endif -- 2.25.1