From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id F06B545AA0; Thu, 3 Oct 2024 15:23:07 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A0B4F4064C; Thu, 3 Oct 2024 15:22:55 +0200 (CEST) Received: from mx0a-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id BA123402F1 for ; Thu, 3 Oct 2024 15:22:53 +0200 (CEST) Received: from pps.filterd (m0431384.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 493Ax94W004138 for ; Thu, 3 Oct 2024 06:22:53 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=g GR3T829RPV0S1r7wa0k+SR62FsZSI64Ql4LZBY08Rk=; b=H4G12uZm7owP0pl/d R1E0M9LSWjClSnJV7funBfnNeBHMm2Yv7Pzwyyeu+CQuXUrR5aONhywKv9N4gBXf SZPcFwQDikAdUTp/khdmSR5A+JnfygDz23l8ZNspioEn+gqrZPB1vq6VNDxvrAC5 GhKHejXAItSJ9aYDrBsuRY5lb6g5VEd6ihJDo6cmkGyG2b+dY8RGlJ8dQW9bPdYc SuyqLuQaKqTc1HQy4kop3MeukW1/q6XGRd9mB4A7IQfv8EpbnuXIZyqSzRBPLN7Y B9kUwtsdUOIF7rWjlx2mMWgEA1xsdtMgPfiyRN2oTMUudFI1IKtKgLliZk1BfpGr SfdYA== Received: from dc5-exch05.marvell.com ([199.233.59.128]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 421b3g1qm9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 03 Oct 2024 06:22:52 -0700 (PDT) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 3 Oct 2024 06:22:51 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Thu, 3 Oct 2024 06:22:51 -0700 Received: from MININT-80QBFE8.corp.innovium.com (MININT-80QBFE8.marvell.com [10.28.164.106]) by maili.marvell.com (Postfix) with ESMTP id 337495C704D; Thu, 3 Oct 2024 06:22:49 -0700 (PDT) From: To: , Pavan Nikhilesh , "Shijith Thotton" CC: Subject: [PATCH 04/20] event/cnxk: add CN20k event queue config Date: Thu, 3 Oct 2024 18:52:21 +0530 Message-ID: <20241003132237.20193-4-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241003132237.20193-1-pbhagavatula@marvell.com> References: <20241003132237.20193-1-pbhagavatula@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: f0Zruv0u3u3PrrrMvSHYnQz1-VIEnklN X-Proofpoint-GUID: f0Zruv0u3u3PrrrMvSHYnQz1-VIEnklN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.687,Hydra:6.0.235,FMLib:17.0.607.475 definitions=2020-10-13_15,2020-10-13_02,2020-04-07_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Pavan Nikhilesh Add setup and release functions for event queues i.e. SSO HWGRPs. Allocate buffers in DRAM that hold inflight events. Register device args to modify inflight event buffer count, HWGRP QoS and stash. Signed-off-by: Pavan Nikhilesh --- drivers/event/cnxk/cn10k_eventdev.c | 2 +- drivers/event/cnxk/cn20k_eventdev.c | 14 ++++++++++++++ drivers/event/cnxk/cnxk_eventdev.c | 4 ++-- drivers/event/cnxk/cnxk_eventdev.h | 2 +- 4 files changed, 18 insertions(+), 4 deletions(-) diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c index a1aa4d0bfd..8ce75951c6 100644 --- a/drivers/event/cnxk/cn10k_eventdev.c +++ b/drivers/event/cnxk/cn10k_eventdev.c @@ -1304,7 +1304,7 @@ RTE_PMD_REGISTER_PARAM_STRING(event_cn10k, CNXK_SSO_XAE_CNT "=" CNXK_SSO_GGRP_QOS "=" CNXK_SSO_FORCE_BP "=1" CN10K_SSO_GW_MODE "=" - CN10K_SSO_STASH "=" + CNXK_SSO_STASH "=" CNXK_TIM_DISABLE_NPA "=1" CNXK_TIM_CHNK_SLOTS "=" CNXK_TIM_RINGS_LMT "=" diff --git a/drivers/event/cnxk/cn20k_eventdev.c b/drivers/event/cnxk/cn20k_eventdev.c index 753a976cd3..b876c36806 100644 --- a/drivers/event/cnxk/cn20k_eventdev.c +++ b/drivers/event/cnxk/cn20k_eventdev.c @@ -56,6 +56,12 @@ cn20k_sso_dev_configure(const struct rte_eventdev *event_dev) return -ENODEV; } + rc = cnxk_sso_xaq_allocate(dev); + if (rc < 0) + goto cnxk_rsrc_fini; + +cnxk_rsrc_fini: + roc_sso_rsrc_fini(&dev->sso); return rc; } @@ -64,6 +70,10 @@ static struct eventdev_ops cn20k_sso_dev_ops = { .dev_configure = cn20k_sso_dev_configure, .queue_def_conf = cnxk_sso_queue_def_conf, + .queue_setup = cnxk_sso_queue_setup, + .queue_release = cnxk_sso_queue_release, + .queue_attr_set = cnxk_sso_queue_attribute_set, + .port_def_conf = cnxk_sso_port_def_conf, }; @@ -127,3 +137,7 @@ static struct rte_pci_driver cn20k_pci_sso = { RTE_PMD_REGISTER_PCI(event_cn20k, cn20k_pci_sso); RTE_PMD_REGISTER_PCI_TABLE(event_cn20k, cn20k_pci_sso_map); RTE_PMD_REGISTER_KMOD_DEP(event_cn20k, "vfio-pci"); +RTE_PMD_REGISTER_PARAM_STRING(event_cn20k, + CNXK_SSO_XAE_CNT "=" + CNXK_SSO_GGRP_QOS "=" + CNXK_SSO_STASH "="); diff --git a/drivers/event/cnxk/cnxk_eventdev.c b/drivers/event/cnxk/cnxk_eventdev.c index 4c5b2f7f59..5c02733863 100644 --- a/drivers/event/cnxk/cnxk_eventdev.c +++ b/drivers/event/cnxk/cnxk_eventdev.c @@ -626,8 +626,8 @@ cnxk_sso_parse_devargs(struct cnxk_sso_evdev *dev, struct rte_devargs *devargs) &single_ws); rte_kvargs_process(kvlist, CN10K_SSO_GW_MODE, &parse_kvargs_value, &dev->gw_mode); - rte_kvargs_process(kvlist, CN10K_SSO_STASH, - &parse_sso_kvargs_stash_dict, dev); + rte_kvargs_process(kvlist, CNXK_SSO_STASH, &parse_sso_kvargs_stash_dict, + dev); dev->dual_ws = !single_ws; rte_kvargs_free(kvlist); } diff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h index 811b2c5ba0..654ad225a0 100644 --- a/drivers/event/cnxk/cnxk_eventdev.h +++ b/drivers/event/cnxk/cnxk_eventdev.h @@ -28,7 +28,7 @@ #define CNXK_SSO_FORCE_BP "force_rx_bp" #define CN9K_SSO_SINGLE_WS "single_ws" #define CN10K_SSO_GW_MODE "gw_mode" -#define CN10K_SSO_STASH "stash" +#define CNXK_SSO_STASH "stash" #define CNXK_SSO_MAX_PROFILES 2 -- 2.25.1