From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E101F45AA0; Thu, 3 Oct 2024 15:23:36 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3E75840665; Thu, 3 Oct 2024 15:23:05 +0200 (CEST) Received: from mx0a-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 75C6440670 for ; Thu, 3 Oct 2024 15:23:03 +0200 (CEST) Received: from pps.filterd (m0431384.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 493BPYbK012138 for ; Thu, 3 Oct 2024 06:23:02 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=e IbzRICO2yrYiJ9a9Wq+1E5rbzYoq9Uye7b5/Oo3qVc=; b=CUVr3BYYXckJupKC6 NVFvmNyv8Rnkww75kIrAIZGgTuN4YJIvuYnxnwWHW/lyz7NYnN4IFaSKkcePzLW0 KXRDi7JK3jTemNRueA2lXCdi5VADmNa0h44njQbfWsymCmoDOUF2U0PjaKdfLl5p 5Jk8Y73O9nSrPXX0+UbOxM1gKuyy2blitDe89635SUkj8L2GdZyxjb0aty7nGY5o VjUqC11eUz0+Ws4ttEdDouoafeLxtvrrS7TFW69FdzdOd+U/z+mgKhUrrI7XoLFh HvqiRsxBi21lttvHAECdpaUspfWXTVtDqpmnqNup3mFzqvQGq/jDvGDw6TEuSwYT nmikQ== Received: from dc5-exch05.marvell.com ([199.233.59.128]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 421b3g1qnb-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 03 Oct 2024 06:23:02 -0700 (PDT) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 3 Oct 2024 06:23:01 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Thu, 3 Oct 2024 06:23:01 -0700 Received: from MININT-80QBFE8.corp.innovium.com (MININT-80QBFE8.marvell.com [10.28.164.106]) by maili.marvell.com (Postfix) with ESMTP id E938F5C704D; Thu, 3 Oct 2024 06:22:59 -0700 (PDT) From: To: , Pavan Nikhilesh , "Shijith Thotton" CC: Subject: [PATCH 08/20] event/cnxk: add CN20K event port quiesce Date: Thu, 3 Oct 2024 18:52:25 +0530 Message-ID: <20241003132237.20193-8-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241003132237.20193-1-pbhagavatula@marvell.com> References: <20241003132237.20193-1-pbhagavatula@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: Mp1lwBPfCsJAb2HRDn70H-g_V3r869Bf X-Proofpoint-GUID: Mp1lwBPfCsJAb2HRDn70H-g_V3r869Bf X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.687,Hydra:6.0.235,FMLib:17.0.607.475 definitions=2020-10-13_15,2020-10-13_02,2020-04-07_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Pavan Nikhilesh Add CN20K event port quiesce function. Signed-off-by: Pavan Nikhilesh --- drivers/event/cnxk/cn20k_eventdev.c | 60 +++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/drivers/event/cnxk/cn20k_eventdev.c b/drivers/event/cnxk/cn20k_eventdev.c index 277366aa82..4c146c1b32 100644 --- a/drivers/event/cnxk/cn20k_eventdev.c +++ b/drivers/event/cnxk/cn20k_eventdev.c @@ -208,6 +208,65 @@ cn20k_sso_port_release(void *port) rte_free(gws_cookie); } +static void +cn20k_sso_port_quiesce(struct rte_eventdev *event_dev, void *port, + rte_eventdev_port_flush_t flush_cb, void *args) +{ + struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev); + struct cn20k_sso_hws *ws = port; + struct rte_event ev; + uint64_t ptag; + bool is_pend; + + is_pend = false; + /* Work in WQE0 is always consumed, unless its a SWTAG. */ + ptag = plt_read64(ws->base + SSOW_LF_GWS_PENDSTATE); + if (ptag & (BIT_ULL(62) | BIT_ULL(54)) || ws->swtag_req) + is_pend = true; + do { + ptag = plt_read64(ws->base + SSOW_LF_GWS_PENDSTATE); + } while (ptag & (BIT_ULL(62) | BIT_ULL(58) | BIT_ULL(56) | BIT_ULL(54))); + + cn20k_sso_hws_get_work_empty(ws, &ev, 0); + if (is_pend && ev.u64) + if (flush_cb) + flush_cb(event_dev->data->dev_id, ev, args); + ptag = (plt_read64(ws->base + SSOW_LF_GWS_TAG) >> 32) & SSO_TT_EMPTY; + if (ptag != SSO_TT_EMPTY) + cnxk_sso_hws_swtag_flush(ws->base); + + do { + ptag = plt_read64(ws->base + SSOW_LF_GWS_PENDSTATE); + } while (ptag & BIT_ULL(56)); + + /* Check if we have work in PRF_WQE0, if so extract it. */ + switch (dev->gw_mode) { + case CNXK_GW_MODE_PREF: + case CNXK_GW_MODE_PREF_WFE: + while (plt_read64(ws->base + SSOW_LF_GWS_PRF_WQE0) & BIT_ULL(63)) + ; + break; + case CNXK_GW_MODE_NONE: + default: + break; + } + + if (CNXK_TT_FROM_TAG(plt_read64(ws->base + SSOW_LF_GWS_PRF_WQE0)) != SSO_TT_EMPTY) { + plt_write64(BIT_ULL(16) | 1, ws->base + SSOW_LF_GWS_OP_GET_WORK0); + cn20k_sso_hws_get_work_empty(ws, &ev, 0); + if (ev.u64) { + if (flush_cb) + flush_cb(event_dev->data->dev_id, ev, args); + } + cnxk_sso_hws_swtag_flush(ws->base); + do { + ptag = plt_read64(ws->base + SSOW_LF_GWS_PENDSTATE); + } while (ptag & BIT_ULL(56)); + } + ws->swtag_req = 0; + plt_write64(0, ws->base + SSOW_LF_GWS_OP_GWC_INVAL); +} + static int cn20k_sso_port_link_profile(struct rte_eventdev *event_dev, void *port, const uint8_t queues[], const uint8_t priorities[], uint16_t nb_links, uint8_t profile) @@ -265,6 +324,7 @@ static struct eventdev_ops cn20k_sso_dev_ops = { .port_def_conf = cnxk_sso_port_def_conf, .port_setup = cn20k_sso_port_setup, .port_release = cn20k_sso_port_release, + .port_quiesce = cn20k_sso_port_quiesce, .port_link = cn20k_sso_port_link, .port_unlink = cn20k_sso_port_unlink, .port_link_profile = cn20k_sso_port_link_profile, -- 2.25.1