From: Serhii Iliushyk <sil-plv@napatech.com>
To: dev@dpdk.org
Cc: mko-plv@napatech.com, sil-plv@napatech.com, ckm@napatech.com,
andrew.rybchenko@oktetlabs.ru, ferruh.yigit@amd.com,
Oleksandr Kolomeiets <okl-plv@napatech.com>
Subject: [PATCH v1 1/5] net/ntnic: update NT NiC PMD driver with FPGA version
Date: Fri, 4 Oct 2024 17:34:19 +0200 [thread overview]
Message-ID: <20241004153551.267935-2-sil-plv@napatech.com> (raw)
In-Reply-To: <20241004153551.267935-1-sil-plv@napatech.com>
From: Oleksandr Kolomeiets <okl-plv@napatech.com>
Update base FPGA files to the new version(39->49)
Fix code style problems
Signed-off-by: Oleksandr Kolomeiets <okl-plv@napatech.com>
---
drivers/net/ntnic/meson.build | 2 +-
.../net/ntnic/nthw/model/nthw_fpga_model.c | 11 +++---
...9_0000.c => nthw_fpga_9563_055_049_0000.c} | 34 +++++++++----------
.../nthw/supported/nthw_fpga_instances.c | 2 +-
.../nthw/supported/nthw_fpga_instances.h | 2 +-
5 files changed, 25 insertions(+), 26 deletions(-)
rename drivers/net/ntnic/nthw/supported/{nthw_fpga_9563_055_039_0000.c => nthw_fpga_9563_055_049_0000.c} (98%)
diff --git a/drivers/net/ntnic/meson.build b/drivers/net/ntnic/meson.build
index 9df2378f7c..e9f2110b8f 100644
--- a/drivers/net/ntnic/meson.build
+++ b/drivers/net/ntnic/meson.build
@@ -26,7 +26,7 @@ sources = files(
'link_mgmt/link_100g/nt4ga_link_100g.c',
'link_mgmt/nt4ga_link.c',
'nim/i2c_nim.c',
- 'nthw/supported/nthw_fpga_9563_055_039_0000.c',
+ 'nthw/supported/nthw_fpga_9563_055_049_0000.c',
'nthw/supported/nthw_fpga_instances.c',
'nthw/supported/nthw_fpga_mod_str_map.c',
'nthw/core/nt200a0x/clock_profiles/nthw_fpga_clk9563.c',
diff --git a/drivers/net/ntnic/nthw/model/nthw_fpga_model.c b/drivers/net/ntnic/nthw/model/nthw_fpga_model.c
index 8ed00248ea..f8e6da2d7f 100644
--- a/drivers/net/ntnic/nthw/model/nthw_fpga_model.c
+++ b/drivers/net/ntnic/nthw/model/nthw_fpga_model.c
@@ -31,8 +31,7 @@ static const char *get_bus_name(int n_bus_type_id)
if (n_bus_type_id >= 1 && n_bus_type_id <= (int)ARRAY_SIZE(sa_nthw_fpga_bus_type_str))
return sa_nthw_fpga_bus_type_str[n_bus_type_id];
- else
- return "ERR";
+ return "ERR";
}
/*
@@ -1146,16 +1145,16 @@ static int nthw_field_wait_cond32(const nthw_field_t *p, enum nthw_field_match e
while (true) {
uint32_t val = nthw_field_get_updated(p);
- if (e_match == NTHW_FIELD_MATCH_SET_ANY && val != 0) {
+ if (e_match == NTHW_FIELD_MATCH_SET_ANY && val != 0)
return 0;
- } else if (e_match == NTHW_FIELD_MATCH_SET_ALL && val == n_mask) {
+ if (e_match == NTHW_FIELD_MATCH_SET_ALL && val == n_mask)
return 0;
- } else if (e_match == NTHW_FIELD_MATCH_CLR_ALL && val == 0) {
+ if (e_match == NTHW_FIELD_MATCH_CLR_ALL && val == 0)
return 0;
- } else if (e_match == NTHW_FIELD_MATCH_CLR_ANY) {
+ if (e_match == NTHW_FIELD_MATCH_CLR_ANY) {
uint32_t mask = nthw_field_get_mask(p);
if (val != mask)
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_039_0000.c b/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_049_0000.c
similarity index 98%
rename from drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_039_0000.c
rename to drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_049_0000.c
index e26a275958..cbebcff541 100644
--- a/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_039_0000.c
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_049_0000.c
@@ -179,7 +179,7 @@ static nthw_fpga_register_init_s gpio_phy_registers[] = {
};
static nthw_fpga_field_init_s hif_build_time_fields[] = {
- { HIF_BUILD_TIME_TIME, 32, 0, 1713859545 },
+ { HIF_BUILD_TIME_TIME, 32, 0, 1726740521 },
};
static nthw_fpga_field_init_s hif_config_fields[] = {
@@ -202,7 +202,7 @@ static nthw_fpga_field_init_s hif_prod_id_ex_fields[] = {
static nthw_fpga_field_init_s hif_prod_id_lsb_fields[] = {
{ HIF_PROD_ID_LSB_GROUP_ID, 16, 16, 9563 },
- { HIF_PROD_ID_LSB_REV_ID, 8, 0, 39 },
+ { HIF_PROD_ID_LSB_REV_ID, 8, 0, 49 },
{ HIF_PROD_ID_LSB_VER_ID, 8, 8, 55 },
};
@@ -247,27 +247,27 @@ static nthw_fpga_field_init_s hif_test1_fields[] = {
};
static nthw_fpga_field_init_s hif_uuid0_fields[] = {
- { HIF_UUID0_UUID0, 32, 0, 1237800326 },
+ { HIF_UUID0_UUID0, 32, 0, 1021928912 },
};
static nthw_fpga_field_init_s hif_uuid1_fields[] = {
- { HIF_UUID1_UUID1, 32, 0, 3057550372 },
+ { HIF_UUID1_UUID1, 32, 0, 2998983545 },
};
static nthw_fpga_field_init_s hif_uuid2_fields[] = {
- { HIF_UUID2_UUID2, 32, 0, 2445752330 },
+ { HIF_UUID2_UUID2, 32, 0, 827210969 },
};
static nthw_fpga_field_init_s hif_uuid3_fields[] = {
- { HIF_UUID3_UUID3, 32, 0, 1864147557 },
+ { HIF_UUID3_UUID3, 32, 0, 462142918 },
};
static nthw_fpga_register_init_s hif_registers[] = {
- { HIF_BUILD_TIME, 16, 32, NTHW_FPGA_REG_TYPE_RO, 1713859545, 1, hif_build_time_fields },
+ { HIF_BUILD_TIME, 16, 32, NTHW_FPGA_REG_TYPE_RO, 1726740521, 1, hif_build_time_fields },
{ HIF_CONFIG, 24, 7, NTHW_FPGA_REG_TYPE_RW, 0, 3, hif_config_fields },
{ HIF_CONTROL, 40, 13, NTHW_FPGA_REG_TYPE_MIXED, 4097, 3, hif_control_fields },
{ HIF_PROD_ID_EX, 112, 32, NTHW_FPGA_REG_TYPE_RO, 1, 3, hif_prod_id_ex_fields },
- { HIF_PROD_ID_LSB, 0, 32, NTHW_FPGA_REG_TYPE_RO, 626734887, 3, hif_prod_id_lsb_fields },
+ { HIF_PROD_ID_LSB, 0, 32, NTHW_FPGA_REG_TYPE_RO, 626734897, 3, hif_prod_id_lsb_fields },
{ HIF_PROD_ID_MSB, 8, 22, NTHW_FPGA_REG_TYPE_RO, 200, 2, hif_prod_id_msb_fields },
{ HIF_SAMPLE_TIME, 96, 1, NTHW_FPGA_REG_TYPE_WO, 0, 1, hif_sample_time_fields },
{ HIF_STATUS, 32, 10, NTHW_FPGA_REG_TYPE_MIXED, 0, 3, hif_status_fields },
@@ -277,10 +277,10 @@ static nthw_fpga_register_init_s hif_registers[] = {
{ HIF_STAT_TX, 80, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, hif_stat_tx_fields },
{ HIF_TEST0, 48, 32, NTHW_FPGA_REG_TYPE_RW, 287454020, 1, hif_test0_fields },
{ HIF_TEST1, 56, 32, NTHW_FPGA_REG_TYPE_RW, 2864434397, 1, hif_test1_fields },
- { HIF_UUID0, 128, 32, NTHW_FPGA_REG_TYPE_RO, 1237800326, 1, hif_uuid0_fields },
- { HIF_UUID1, 144, 32, NTHW_FPGA_REG_TYPE_RO, 3057550372, 1, hif_uuid1_fields },
- { HIF_UUID2, 160, 32, NTHW_FPGA_REG_TYPE_RO, 2445752330, 1, hif_uuid2_fields },
- { HIF_UUID3, 176, 32, NTHW_FPGA_REG_TYPE_RO, 1864147557, 1, hif_uuid3_fields },
+ { HIF_UUID0, 128, 32, NTHW_FPGA_REG_TYPE_RO, 1021928912, 1, hif_uuid0_fields },
+ { HIF_UUID1, 144, 32, NTHW_FPGA_REG_TYPE_RO, 2998983545, 1, hif_uuid1_fields },
+ { HIF_UUID2, 160, 32, NTHW_FPGA_REG_TYPE_RO, 827210969, 1, hif_uuid2_fields },
+ { HIF_UUID3, 176, 32, NTHW_FPGA_REG_TYPE_RO, 462142918, 1, hif_uuid3_fields },
};
static nthw_fpga_field_init_s iic_adr_fields[] = {
@@ -1071,7 +1071,7 @@ static nthw_fpga_module_init_s fpga_modules[] = {
static nthw_fpga_prod_param_s product_parameters[] = {
{ NT_BUILD_NUMBER, 0 },
- { NT_BUILD_TIME, 1713859545 },
+ { NT_BUILD_TIME, 1726740521 },
{ NT_CATEGORIES, 64 },
{ NT_CAT_DCT_PRESENT, 0 },
{ NT_CAT_END_OFS_SUPPORT, 0 },
@@ -1101,7 +1101,7 @@ static nthw_fpga_prod_param_s product_parameters[] = {
{ NT_FLM_CACHE, 1 },
{ NT_FLM_CATEGORIES, 32 },
{ NT_FLM_ENTRY_SIZE, 64 },
- { NT_FLM_LOAD_APS_MAX, 260000000 },
+ { NT_FLM_LOAD_APS_MAX, 270000000 },
{ NT_FLM_LOAD_LPS_MAX, 300000000 },
{ NT_FLM_PRESENT, 1 },
{ NT_FLM_PRIOS, 4 },
@@ -1176,7 +1176,7 @@ static nthw_fpga_prod_param_s product_parameters[] = {
{ NT_QUEUES, 128 },
{ NT_RAC_RAB_INTERFACES, 3 },
{ NT_RAC_RAB_OB_UPDATE, 0 },
- { NT_REVISION_ID, 39 },
+ { NT_REVISION_ID, 49 },
{ NT_RMC_LAG_GROUPS, 1 },
{ NT_RMC_PRESENT, 1 },
{ NT_ROA_CATEGORIES, 1024 },
@@ -1225,6 +1225,6 @@ static nthw_fpga_prod_param_s product_parameters[] = {
{ 0, -1 }, /* END */
};
-nthw_fpga_prod_init_s nthw_fpga_9563_055_039_0000 = {
- 200, 9563, 55, 39, 0, 0, 1713859545, 152, product_parameters, 15, fpga_modules,
+nthw_fpga_prod_init_s nthw_fpga_9563_055_049_0000 = {
+ 200, 9563, 55, 49, 0, 0, 1726740521, 152, product_parameters, 15, fpga_modules,
};
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_instances.c b/drivers/net/ntnic/nthw/supported/nthw_fpga_instances.c
index 4fe7f7ea94..c8a310c415 100644
--- a/drivers/net/ntnic/nthw/supported/nthw_fpga_instances.c
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_instances.c
@@ -5,4 +5,4 @@
#include "nthw_fpga_instances.h"
-nthw_fpga_prod_init_s *nthw_fpga_instances[] = { &nthw_fpga_9563_055_039_0000, NULL };
+nthw_fpga_prod_init_s *nthw_fpga_instances[] = { &nthw_fpga_9563_055_049_0000, NULL };
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_instances.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_instances.h
index d0e6f7b429..3e5983f763 100644
--- a/drivers/net/ntnic/nthw/supported/nthw_fpga_instances.h
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_instances.h
@@ -6,4 +6,4 @@
#include "fpga_model.h"
extern nthw_fpga_prod_init_s *nthw_fpga_instances[];
-extern nthw_fpga_prod_init_s nthw_fpga_9563_055_039_0000;
+extern nthw_fpga_prod_init_s nthw_fpga_9563_055_049_0000;
--
2.45.0
next prev parent reply other threads:[~2024-10-04 15:54 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-04 15:34 [PATCH v1 00/50] Provide: flow filter init API, Enable virtual queues, fix ntnic issues for release 24.07 Serhii Iliushyk
2024-10-04 15:34 ` Serhii Iliushyk [this message]
2024-10-04 15:34 ` [PATCH v1 2/5] net/ntnic: fix coverity issues: Serhii Iliushyk
2024-10-04 15:34 ` [PATCH v1 3/5] net/ntnic: update documentation Serhii Iliushyk
2024-10-04 15:34 ` [PATCH v1 4/5] net/ntnic: remove extra calling of the API for release port Serhii Iliushyk
2024-10-04 15:34 ` [PATCH v1 5/5] net/ntnic: extend and fix logging implementation Serhii Iliushyk
2024-10-04 15:34 ` [PATCH v1 01/31] net/ntnic: add flow filter init API Serhii Iliushyk
2024-10-04 15:34 ` [PATCH v1 02/31] net/ntnic: add flow filter deinitialization API Serhii Iliushyk
2024-10-04 15:34 ` [PATCH v1 03/31] net/ntnic: add flow backend initialization API Serhii Iliushyk
2024-10-04 15:34 ` [PATCH v1 04/31] net/ntnic: add flow backend deinitialization API Serhii Iliushyk
2024-10-04 15:34 ` [PATCH v1 05/31] net/ntnic: add INFO flow module Serhii Iliushyk
2024-10-04 15:34 ` [PATCH v1 06/31] net/ntnic: add categorizer (CAT) " Serhii Iliushyk
2024-10-04 15:34 ` [PATCH v1 07/31] net/ntnic: add key match (KM) " Serhii Iliushyk
2024-10-04 15:34 ` [PATCH v1 08/31] net/ntnic: add flow matcher (FLM) " Serhii Iliushyk
2024-10-04 15:34 ` [PATCH v1 09/31] net/ntnic: add IP fragmenter (IFR) " Serhii Iliushyk
2024-10-04 15:34 ` [PATCH v1 10/31] net/ntnic: add hasher (HSH) " Serhii Iliushyk
2024-10-04 15:34 ` [PATCH v1 11/31] net/ntnic: add queue select (QSL) " Serhii Iliushyk
2024-10-04 15:34 ` [PATCH v1 12/31] net/ntnic: add slicer (SLC LR) " Serhii Iliushyk
2024-10-04 15:34 ` [PATCH v1 13/31] net/ntnic: add packet descriptor builder (PDB) " Serhii Iliushyk
2024-10-04 15:34 ` [PATCH v1 14/31] net/ntnic: add header field update (HFU) " Serhii Iliushyk
2024-10-04 15:34 ` [PATCH v1 15/31] net/ntnic: add RPP local retransmit (RPP LR) " Serhii Iliushyk
2024-10-04 15:34 ` [PATCH v1 16/31] net/ntnic: add copier (Tx CPY) " Serhii Iliushyk
2024-10-04 15:34 ` [PATCH v1 17/31] net/ntnic: add checksum update (CSU) " Serhii Iliushyk
2024-10-04 15:34 ` [PATCH v1 18/31] net/ntnic: add insert (Tx INS) " Serhii Iliushyk
2024-10-04 15:34 ` [PATCH v1 19/31] net/ntnic: add replacer (Tx RPL) " Serhii Iliushyk
2024-10-04 15:34 ` [PATCH v1 20/31] net/ntnic: add Tx Packet Editor (TPE) " Serhii Iliushyk
2024-10-04 15:34 ` [PATCH v1 21/31] net/ntnic: add base init and deinit of the NT flow API Serhii Iliushyk
2024-10-04 15:34 ` [PATCH v1 22/31] net/ntnic: add base init and deinit the NT flow backend Serhii Iliushyk
2024-10-04 15:34 ` [PATCH v1 23/31] net/ntnic: add categorizer (CAT) FPGA module Serhii Iliushyk
2024-10-04 15:34 ` [PATCH v1 24/31] net/ntnic: add key match (KM) " Serhii Iliushyk
2024-10-04 15:34 ` [PATCH v1 25/31] net/ntnic: add flow matcher (FLM) " Serhii Iliushyk
2024-10-04 15:34 ` [PATCH v1 26/31] net/ntnic: add hasher (HSH) " Serhii Iliushyk
2024-10-04 15:34 ` [PATCH v1 27/31] net/ntnic: add queue select (QSL) " Serhii Iliushyk
2024-10-04 15:34 ` [PATCH v1 28/31] net/ntnic: add slicer (SLC LR) " Serhii Iliushyk
2024-10-04 15:34 ` [PATCH v1 29/31] net/ntnic: add packet descriptor builder (PDB) " Serhii Iliushyk
2024-10-04 15:34 ` [PATCH v1 30/31] net/ntnic: add Tx Packet Editor (TPE) " Serhii Iliushyk
2024-10-04 15:34 ` [PATCH v1 31/31] net/ntnic: add receive MAC converter (RMC) core module Serhii Iliushyk
2024-10-04 15:34 ` [PATCH v1 01/14] net/ntnic: add basic queue operations Serhii Iliushyk
2024-10-04 15:34 ` [PATCH v1 02/14] net/ntnic: enhance Ethernet device configuration Serhii Iliushyk
2024-10-04 15:34 ` [PATCH v1 03/14] net/ntnic: add scatter-gather HW deallocation Serhii Iliushyk
2024-10-04 15:34 ` [PATCH v1 04/14] net/ntnic: add queue setup operations Serhii Iliushyk
2024-10-04 15:34 ` [PATCH v1 05/14] net/ntnic: add packet handler for virtio queues Serhii Iliushyk
2024-10-04 15:35 ` [PATCH v1 06/14] net/ntnic: add init for virt queues in the DBS Serhii Iliushyk
2024-10-04 15:35 ` [PATCH v1 07/14] net/ntnic: add split-queue support Serhii Iliushyk
2024-10-04 15:35 ` [PATCH v1 08/14] net/ntnic: add functions for availability monitor management Serhii Iliushyk
2024-10-04 15:35 ` [PATCH v1 09/14] net/ntnic: used writer data handling functions Serhii Iliushyk
2024-10-04 15:35 ` [PATCH v1 10/14] net/ntnic: add descriptor reader " Serhii Iliushyk
2024-10-04 15:35 ` [PATCH v1 11/14] net/ntnic: update FPGA registeris related to DBS Serhii Iliushyk
2024-10-04 15:35 ` [PATCH v1 12/14] net/ntnic: virtqueue setup managed packed-ring was added Serhii Iliushyk
2024-10-04 15:35 ` [PATCH v1 13/14] net/ntnic: add functions for releasing virt queues Serhii Iliushyk
2024-10-04 15:35 ` [PATCH v1 14/14] net/ntnic: add functions for retrieving and managing packets Serhii Iliushyk
-- strict thread matches above, loose matches on Subject: below --
2024-10-04 15:06 [PATCH v1 0/5] Fixes for release 24.07 Serhii Iliushyk
2024-10-04 15:06 ` [PATCH v1 1/5] net/ntnic: update NT NiC PMD driver with FPGA version Serhii Iliushyk
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