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Ip=[178.72.21.4]; Helo=[localhost.localdomain] X-MS-Exchange-CrossTenant-AuthSource: AM2PEPF0001C715.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: GV1P190MB1993 X-OriginatorOrg: napatech.com X-BESS-ID: 1728057054-305791-12644-36011-1 X-BESS-VER: 2019.1_20240924.1654 X-BESS-Apparent-Source-IP: 104.47.17.169 X-BESS-Parts: H4sIAAAAAAACA4uuVkqtKFGyUioBkjpK+cVKVoaGlhYWQGYGUNTY0twkOTnRxM jULDXVwDItOdHI1NgiydA82dzILNEoTak2FgBdJCESQgAAAA== X-BESS-Outbound-Spam-Score: 0.00 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.259494 [from cloudscan9-172.eu-central-1a.ess.aws.cudaops.com] Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.00 using account:ESS113687 scores of KILL_LEVEL=7.0 tests=BSF_BESS_OUTBOUND X-BESS-BRTS-Status: 1 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Oleksandr Kolomeiets The RX MAC Converter module is part of the control mechanism of the physical ports. Signed-off-by: Oleksandr Kolomeiets --- drivers/net/ntnic/adapter/nt4ga_adapter.c | 14 +++ drivers/net/ntnic/include/nt4ga_adapter.h | 1 + drivers/net/ntnic/include/ntnic_stat.h | 11 +++ drivers/net/ntnic/meson.build | 1 + .../net/ntnic/nthw/core/include/nthw_rmc.h | 49 ++++++++++ drivers/net/ntnic/nthw/core/nthw_rmc.c | 90 +++++++++++++++++++ .../supported/nthw_fpga_9563_055_049_0000.c | 29 +++++- .../ntnic/nthw/supported/nthw_fpga_mod_defs.h | 1 + .../ntnic/nthw/supported/nthw_fpga_reg_defs.h | 1 + .../nthw/supported/nthw_fpga_reg_defs_rmc.h | 36 ++++++++ 10 files changed, 232 insertions(+), 1 deletion(-) create mode 100644 drivers/net/ntnic/include/ntnic_stat.h create mode 100644 drivers/net/ntnic/nthw/core/include/nthw_rmc.h create mode 100644 drivers/net/ntnic/nthw/core/nthw_rmc.c create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rmc.h diff --git a/drivers/net/ntnic/adapter/nt4ga_adapter.c b/drivers/net/ntnic/adapter/nt4ga_adapter.c index fd90f31abd..5d9db3450d 100644 --- a/drivers/net/ntnic/adapter/nt4ga_adapter.c +++ b/drivers/net/ntnic/adapter/nt4ga_adapter.c @@ -212,6 +212,20 @@ static int nt4ga_adapter_init(struct adapter_info_s *p_adapter_info) } } + nthw_rmc_t *p_nthw_rmc = nthw_rmc_new(); + if (p_nthw_rmc == NULL) { + NT_LOG(ERR, NTNIC, "Failed to allocate memory for RMC module\n"); + return -1; + } + + res = nthw_rmc_init(p_nthw_rmc, p_fpga, 0); + if (res) { + NT_LOG(ERR, NTNIC, "Failed to initialize RMC module\n"); + return -1; + } + + nthw_rmc_unblock(p_nthw_rmc, false); + return 0; } diff --git a/drivers/net/ntnic/include/nt4ga_adapter.h b/drivers/net/ntnic/include/nt4ga_adapter.h index 93218fd45b..809135f130 100644 --- a/drivers/net/ntnic/include/nt4ga_adapter.h +++ b/drivers/net/ntnic/include/nt4ga_adapter.h @@ -27,6 +27,7 @@ typedef struct hw_info_s { * Services provided by the adapter module */ #include "nt4ga_filter.h" +#include "ntnic_stat.h" typedef struct adapter_info_s { struct nt4ga_filter_s nt4ga_filter; diff --git a/drivers/net/ntnic/include/ntnic_stat.h b/drivers/net/ntnic/include/ntnic_stat.h new file mode 100644 index 0000000000..148088fe1d --- /dev/null +++ b/drivers/net/ntnic/include/ntnic_stat.h @@ -0,0 +1,11 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#ifndef NTNIC_STAT_H_ +#define NTNIC_STAT_H_ + +#include "nthw_rmc.h" + +#endif /* NTNIC_STAT_H_ */ diff --git a/drivers/net/ntnic/meson.build b/drivers/net/ntnic/meson.build index e2eff3cf1e..66d2770da7 100644 --- a/drivers/net/ntnic/meson.build +++ b/drivers/net/ntnic/meson.build @@ -41,6 +41,7 @@ sources = files( 'nthw/core/nthw_iic.c', 'nthw/core/nthw_mac_pcs.c', 'nthw/core/nthw_pcie3.c', + 'nthw/core/nthw_rmc.c', 'nthw/core/nthw_sdc.c', 'nthw/core/nthw_si5340.c', 'nthw/flow_api/flow_api.c', diff --git a/drivers/net/ntnic/nthw/core/include/nthw_rmc.h b/drivers/net/ntnic/nthw/core/include/nthw_rmc.h new file mode 100644 index 0000000000..65fbd8cda0 --- /dev/null +++ b/drivers/net/ntnic/nthw/core/include/nthw_rmc.h @@ -0,0 +1,49 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#ifndef NTHW_RMC_H_ +#define NTHW_RMC_H_ + +#include "nthw_fpga_model.h" + +struct nthw_rmc { + nthw_fpga_t *mp_fpga; + nthw_module_t *mp_mod_rmc; + int mn_instance; + + int mn_ports; + int mn_nims; + + bool mb_administrative_block; + + /* RMC CTRL register */ + nthw_register_t *mp_reg_ctrl; + nthw_field_t *mp_fld_ctrl_block_stat_drop; + nthw_field_t *mp_fld_ctrl_block_keep_alive; + nthw_field_t *mp_fld_ctrl_block_mac_port; + + /* RMC Status register */ + nthw_register_t *mp_reg_status; + nthw_field_t *mp_fld_sf_ram_of; + nthw_field_t *mp_fld_descr_fifo_of; + + /* RMC DBG register */ + nthw_register_t *mp_reg_dbg; + nthw_field_t *mp_fld_dbg_merge; + + /* RMC MAC_IF register */ + nthw_register_t *mp_reg_mac_if; + nthw_field_t *mp_fld_mac_if_err; +}; + +typedef struct nthw_rmc nthw_rmc_t; +typedef struct nthw_rmc nthw_rmc; + +nthw_rmc_t *nthw_rmc_new(void); +int nthw_rmc_init(nthw_rmc_t *p, nthw_fpga_t *p_fpga, int n_instance); + +void nthw_rmc_unblock(nthw_rmc_t *p, bool b_is_slave); + +#endif /* NTHW_RMC_H_ */ diff --git a/drivers/net/ntnic/nthw/core/nthw_rmc.c b/drivers/net/ntnic/nthw/core/nthw_rmc.c new file mode 100644 index 0000000000..9604825be0 --- /dev/null +++ b/drivers/net/ntnic/nthw/core/nthw_rmc.c @@ -0,0 +1,90 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#include "ntlog.h" + +#include "nthw_drv.h" +#include "nthw_register.h" + +#include "nthw_rmc.h" + +nthw_rmc_t *nthw_rmc_new(void) +{ + nthw_rmc_t *p = malloc(sizeof(nthw_rmc_t)); + + if (p) + memset(p, 0, sizeof(nthw_rmc_t)); + + return p; +} + +int nthw_rmc_init(nthw_rmc_t *p, nthw_fpga_t *p_fpga, int n_instance) +{ + const char *const p_adapter_id_str = p_fpga->p_fpga_info->mp_adapter_id_str; + nthw_module_t *p_mod = nthw_fpga_query_module(p_fpga, MOD_RMC, n_instance); + + if (p == NULL) + return p_mod == NULL ? -1 : 0; + + if (p_mod == NULL) { + NT_LOG(ERR, NTHW, "%s: RMC %d: no such instance\n", p_adapter_id_str, n_instance); + return -1; + } + + p->mp_fpga = p_fpga; + p->mn_instance = n_instance; + p->mp_mod_rmc = p_mod; + + /* Params */ + p->mn_ports = + nthw_fpga_get_product_param(p_fpga, NT_RX_PORTS, + nthw_fpga_get_product_param(p_fpga, NT_PORTS, 0)); + p->mn_nims = nthw_fpga_get_product_param(p_fpga, NT_NIMS, 0); + p->mb_administrative_block = false; + + NT_LOG(DBG, NTHW, "%s: RMC %d\n", p_adapter_id_str, p->mn_instance); + + p->mp_reg_ctrl = nthw_module_get_register(p->mp_mod_rmc, RMC_CTRL); + + p->mp_fld_ctrl_block_stat_drop = + nthw_register_get_field(p->mp_reg_ctrl, RMC_CTRL_BLOCK_STATT); + p->mp_fld_ctrl_block_keep_alive = + nthw_register_get_field(p->mp_reg_ctrl, RMC_CTRL_BLOCK_KEEPA); + p->mp_fld_ctrl_block_mac_port = + nthw_register_get_field(p->mp_reg_ctrl, RMC_CTRL_BLOCK_MAC_PORT); + + p->mp_reg_status = nthw_module_query_register(p->mp_mod_rmc, RMC_STATUS); + + if (p->mp_reg_status) { + p->mp_fld_sf_ram_of = + nthw_register_get_field(p->mp_reg_status, RMC_STATUS_SF_RAM_OF); + p->mp_fld_descr_fifo_of = + nthw_register_get_field(p->mp_reg_status, RMC_STATUS_DESCR_FIFO_OF); + } + + p->mp_reg_dbg = nthw_module_query_register(p->mp_mod_rmc, RMC_DBG); + + if (p->mp_reg_dbg) + p->mp_fld_dbg_merge = nthw_register_get_field(p->mp_reg_dbg, RMC_DBG_MERGE); + + p->mp_reg_mac_if = nthw_module_query_register(p->mp_mod_rmc, RMC_MAC_IF); + + if (p->mp_reg_mac_if) + p->mp_fld_mac_if_err = nthw_register_get_field(p->mp_reg_mac_if, RMC_MAC_IF_ERR); + + return 0; +} + +void nthw_rmc_unblock(nthw_rmc_t *p, bool b_is_slave) +{ + uint32_t n_block_mask = ~0U << (b_is_slave ? p->mn_nims : p->mn_ports); + + /* BLOCK_STATT(0)=0 BLOCK_KEEPA(1)=0 BLOCK_MAC_PORT(8:11)=0 */ + if (!p->mb_administrative_block) { + nthw_field_clr_flush(p->mp_fld_ctrl_block_stat_drop); + nthw_field_clr_flush(p->mp_fld_ctrl_block_keep_alive); + nthw_field_set_val_flush32(p->mp_fld_ctrl_block_mac_port, n_block_mask); + } +} diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_049_0000.c b/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_049_0000.c index 9f821abf55..98b857158e 100644 --- a/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_049_0000.c +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_049_0000.c @@ -1468,6 +1468,32 @@ static nthw_fpga_register_init_s rac_registers[] = { { RAC_RAB_OB_DATA, 4168, 32, NTHW_FPGA_REG_TYPE_RC1, 0, 1, rac_rab_ob_data_fields }, }; +static nthw_fpga_field_init_s rmc_ctrl_fields[] = { + { RMC_CTRL_BLOCK_KEEPA, 1, 1, 1 }, { RMC_CTRL_BLOCK_MAC_PORT, 2, 8, 3 }, + { RMC_CTRL_BLOCK_RPP_SLICE, 8, 10, 0 }, { RMC_CTRL_BLOCK_STATT, 1, 0, 1 }, + { RMC_CTRL_LAG_PHY_ODD_EVEN, 1, 24, 0 }, +}; + +static nthw_fpga_field_init_s rmc_dbg_fields[] = { + { RMC_DBG_MERGE, 31, 0, 0 }, +}; + +static nthw_fpga_field_init_s rmc_mac_if_fields[] = { + { RMC_MAC_IF_ERR, 31, 0, 0 }, +}; + +static nthw_fpga_field_init_s rmc_status_fields[] = { + { RMC_STATUS_DESCR_FIFO_OF, 1, 16, 0 }, + { RMC_STATUS_SF_RAM_OF, 1, 0, 0 }, +}; + +static nthw_fpga_register_init_s rmc_registers[] = { + { RMC_CTRL, 0, 25, NTHW_FPGA_REG_TYPE_RW, 771, 5, rmc_ctrl_fields }, + { RMC_DBG, 2, 31, NTHW_FPGA_REG_TYPE_RO, 0, 1, rmc_dbg_fields }, + { RMC_MAC_IF, 3, 31, NTHW_FPGA_REG_TYPE_RO, 0, 1, rmc_mac_if_fields }, + { RMC_STATUS, 1, 17, NTHW_FPGA_REG_TYPE_RO, 0, 2, rmc_status_fields }, +}; + static nthw_fpga_field_init_s rst9563_ctrl_fields[] = { { RST9563_CTRL_PTP_MMCM_CLKSEL, 1, 2, 1 }, { RST9563_CTRL_TS_CLKSEL, 1, 1, 1 }, @@ -1550,6 +1576,7 @@ static nthw_fpga_module_init_s fpga_modules[] = { { MOD_PDB, 0, MOD_PDB, 0, 9, NTHW_FPGA_BUS_TYPE_RAB1, 2560, 3, pdb_registers }, { MOD_QSL, 0, MOD_QSL, 0, 7, NTHW_FPGA_BUS_TYPE_RAB1, 1792, 8, qsl_registers }, { MOD_RAC, 0, MOD_RAC, 3, 0, NTHW_FPGA_BUS_TYPE_PCI, 8192, 14, rac_registers }, + { MOD_RMC, 0, MOD_RMC, 1, 3, NTHW_FPGA_BUS_TYPE_RAB0, 12288, 4, rmc_registers }, { MOD_RST9563, 0, MOD_RST9563, 0, 5, NTHW_FPGA_BUS_TYPE_RAB0, 1024, 5, rst9563_registers }, }; @@ -1710,5 +1737,5 @@ static nthw_fpga_prod_param_s product_parameters[] = { }; nthw_fpga_prod_init_s nthw_fpga_9563_055_049_0000 = { - 200, 9563, 55, 49, 0, 0, 1726740521, 152, product_parameters, 20, fpga_modules, + 200, 9563, 55, 49, 0, 0, 1726740521, 152, product_parameters, 21, fpga_modules, }; diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h index 51b2d99c01..5d6aac122c 100644 --- a/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h @@ -34,6 +34,7 @@ #define MOD_PDB (0xa7771bffUL) #define MOD_QSL (0x448ed859UL) #define MOD_RAC (0xae830b42UL) +#define MOD_RMC (0x236444eUL) #define MOD_RPP_LR (0xba7f945cUL) #define MOD_RST9563 (0x385d6d1dUL) #define MOD_SDC (0xd2369530UL) diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h index 8fa41eb7ea..45f9794958 100644 --- a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h @@ -35,6 +35,7 @@ #include "nthw_fpga_reg_defs_pdb.h" #include "nthw_fpga_reg_defs_qsl.h" #include "nthw_fpga_reg_defs_rac.h" +#include "nthw_fpga_reg_defs_rmc.h" #include "nthw_fpga_reg_defs_rpl.h" #include "nthw_fpga_reg_defs_rpp_lr.h" #include "nthw_fpga_reg_defs_rst9563.h" diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rmc.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rmc.h new file mode 100644 index 0000000000..07a1c8f890 --- /dev/null +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rmc.h @@ -0,0 +1,36 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2024 Napatech A/S + */ + +/* + * nthw_fpga_reg_defs_rmc.h + * + * Auto-generated file - do *NOT* edit + * + */ + +#ifndef _NTHW_FPGA_REG_DEFS_RMC_ +#define _NTHW_FPGA_REG_DEFS_RMC_ + +/* RMC */ +#define NTHW_MOD_RMC (0x236444eUL) +#define RMC_CTRL (0x4c45f748UL) +#define RMC_CTRL_BLOCK_KEEPA (0x5e036c8UL) +#define RMC_CTRL_BLOCK_MAC_PORT (0x582a6486UL) +#define RMC_CTRL_BLOCK_RPP_SLICE (0x58c719cUL) +#define RMC_CTRL_BLOCK_STATT (0xb36d5342UL) +#define RMC_CTRL_LAG_PHY_ODD_EVEN (0xf4613c9UL) +#define RMC_DBG (0x578721f2UL) +#define RMC_DBG_MERGE (0xebfd6f00UL) +#define RMC_MAC_IF (0x806bb8b0UL) +#define RMC_MAC_IF_ERR (0xa79e974aUL) +#define RMC_STATUS (0x3c415d75UL) +#define RMC_STATUS_DESCR_FIFO_OF (0x7be968baUL) +#define RMC_STATUS_SF_RAM_OF (0x1832173dUL) + +#endif /* _NTHW_FPGA_REG_DEFS_RMC_ */ + +/* + * Auto-generated file - do *NOT* edit + */ -- 2.45.0