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Ip=[178.72.21.4]; Helo=[localhost.localdomain] X-MS-Exchange-CrossTenant-AuthSource: AM2PEPF0001C715.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBAP190MB0822 X-OriginatorOrg: napatech.com X-BESS-ID: 1728057043-302249-12644-33729-1 X-BESS-VER: 2019.1_20240924.1654 X-BESS-Apparent-Source-IP: 104.47.17.176 X-BESS-Parts: H4sIAAAAAAACA4uuVkqtKFGyUioBkjpK+cVKVoYmZuaWQGYGUDTVwMwk0TTZ2M zQwMLSxCDRyMjEzDjR0NLSIMnCMs3EQqk2FgA+0MfCQgAAAA== X-BESS-Outbound-Spam-Score: 0.00 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.259494 [from cloudscan21-181.eu-central-1b.ess.aws.cudaops.com] Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.00 using account:ESS113687 scores of KILL_LEVEL=7.0 tests=BSF_BESS_OUTBOUND X-BESS-BRTS-Status: 1 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Danylo Vodopianov DBS (DVIO Buffer System) module controls the scatter-gather buffer system that let's the host CPU interact with packets. Macros and Definitions: Defined constants for queue management and polling speeds. Data Structures: Added structures and arrays for RX and TX queue management. Procedures: Implemented initialization routines for setting up queues and configuring Direct Buffer Storage (DBS) in FPGA. Main Initialization: Allocates DBS modules, resets, and configures RX and TX queues. Signed-off-by: Danylo Vodopianov --- drivers/net/ntnic/dbsconfig/ntnic_dbsconfig.c | 154 ++++++++++++++++++ drivers/net/ntnic/include/ntnic_dbs.h | 71 +++++++- drivers/net/ntnic/meson.build | 2 + drivers/net/ntnic/nthw/dbs/nthw_dbs.c | 135 +++++++++++++++ .../ntnic/nthw/supported/nthw_fpga_mod_defs.h | 1 + drivers/net/ntnic/ntnic_mod_reg.c | 11 +- drivers/net/ntnic/ntnic_mod_reg.h | 2 + 7 files changed, 374 insertions(+), 2 deletions(-) create mode 100644 drivers/net/ntnic/dbsconfig/ntnic_dbsconfig.c create mode 100644 drivers/net/ntnic/nthw/dbs/nthw_dbs.c diff --git a/drivers/net/ntnic/dbsconfig/ntnic_dbsconfig.c b/drivers/net/ntnic/dbsconfig/ntnic_dbsconfig.c new file mode 100644 index 0000000000..fc1dab6c5f --- /dev/null +++ b/drivers/net/ntnic/dbsconfig/ntnic_dbsconfig.c @@ -0,0 +1,154 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#include + +#include "ntos_drv.h" +#include "ntnic_virt_queue.h" +#include "ntnic_mod_reg.h" +#include "ntlog.h" + +#define MAX_VIRT_QUEUES 128 + +#define LAST_QUEUE 127 +#define DISABLE 0 +#define ENABLE 1 +#define RX_AM_DISABLE DISABLE +#define RX_AM_ENABLE ENABLE +#define RX_UW_DISABLE DISABLE +#define RX_UW_ENABLE ENABLE +#define RX_Q_DISABLE DISABLE +#define RX_Q_ENABLE ENABLE +#define RX_AM_POLL_SPEED 5 +#define RX_UW_POLL_SPEED 9 +#define INIT_QUEUE 1 + +#define TX_AM_DISABLE DISABLE +#define TX_AM_ENABLE ENABLE +#define TX_UW_DISABLE DISABLE +#define TX_UW_ENABLE ENABLE +#define TX_Q_DISABLE DISABLE +#define TX_Q_ENABLE ENABLE +#define TX_AM_POLL_SPEED 5 +#define TX_UW_POLL_SPEED 8 + +enum nthw_virt_queue_usage { + NTHW_VIRTQ_UNUSED = 0 +}; + +struct nthw_virt_queue { + enum nthw_virt_queue_usage usage; +}; + +static struct nthw_virt_queue rxvq[MAX_VIRT_QUEUES]; +static struct nthw_virt_queue txvq[MAX_VIRT_QUEUES]; + +static void dbs_init_rx_queue(nthw_dbs_t *p_nthw_dbs, uint32_t queue, uint32_t start_idx, + uint32_t start_ptr) +{ + uint32_t busy; + uint32_t init; + uint32_t dummy; + + do { + get_rx_init(p_nthw_dbs, &init, &dummy, &busy); + } while (busy != 0); + + set_rx_init(p_nthw_dbs, start_idx, start_ptr, INIT_QUEUE, queue); + + do { + get_rx_init(p_nthw_dbs, &init, &dummy, &busy); + } while (busy != 0); +} + +static void dbs_init_tx_queue(nthw_dbs_t *p_nthw_dbs, uint32_t queue, uint32_t start_idx, + uint32_t start_ptr) +{ + uint32_t busy; + uint32_t init; + uint32_t dummy; + + do { + get_tx_init(p_nthw_dbs, &init, &dummy, &busy); + } while (busy != 0); + + set_tx_init(p_nthw_dbs, start_idx, start_ptr, INIT_QUEUE, queue); + + do { + get_tx_init(p_nthw_dbs, &init, &dummy, &busy); + } while (busy != 0); +} + +static int nthw_virt_queue_init(struct fpga_info_s *p_fpga_info) +{ + assert(p_fpga_info); + + nthw_fpga_t *const p_fpga = p_fpga_info->mp_fpga; + nthw_dbs_t *p_nthw_dbs; + int res = 0; + uint32_t i; + + p_fpga_info->mp_nthw_dbs = NULL; + + p_nthw_dbs = nthw_dbs_new(); + + if (p_nthw_dbs == NULL) + return -1; + + res = dbs_init(NULL, p_fpga, 0);/* Check that DBS exists in FPGA */ + + if (res) { + free(p_nthw_dbs); + return res; + } + + res = dbs_init(p_nthw_dbs, p_fpga, 0); /* Create DBS module */ + + if (res) { + free(p_nthw_dbs); + return res; + } + + p_fpga_info->mp_nthw_dbs = p_nthw_dbs; + + for (i = 0; i < MAX_VIRT_QUEUES; ++i) { + rxvq[i].usage = NTHW_VIRTQ_UNUSED; + txvq[i].usage = NTHW_VIRTQ_UNUSED; + } + + dbs_reset(p_nthw_dbs); + + for (i = 0; i < NT_DBS_RX_QUEUES_MAX; ++i) + dbs_init_rx_queue(p_nthw_dbs, i, 0, 0); + + for (i = 0; i < NT_DBS_TX_QUEUES_MAX; ++i) + dbs_init_tx_queue(p_nthw_dbs, i, 0, 0); + + set_rx_control(p_nthw_dbs, LAST_QUEUE, RX_AM_DISABLE, RX_AM_POLL_SPEED, RX_UW_DISABLE, + RX_UW_POLL_SPEED, RX_Q_DISABLE); + set_rx_control(p_nthw_dbs, LAST_QUEUE, RX_AM_ENABLE, RX_AM_POLL_SPEED, RX_UW_ENABLE, + RX_UW_POLL_SPEED, RX_Q_DISABLE); + set_rx_control(p_nthw_dbs, LAST_QUEUE, RX_AM_ENABLE, RX_AM_POLL_SPEED, RX_UW_ENABLE, + RX_UW_POLL_SPEED, RX_Q_ENABLE); + + set_tx_control(p_nthw_dbs, LAST_QUEUE, TX_AM_DISABLE, TX_AM_POLL_SPEED, TX_UW_DISABLE, + TX_UW_POLL_SPEED, TX_Q_DISABLE); + set_tx_control(p_nthw_dbs, LAST_QUEUE, TX_AM_ENABLE, TX_AM_POLL_SPEED, TX_UW_ENABLE, + TX_UW_POLL_SPEED, TX_Q_DISABLE); + set_tx_control(p_nthw_dbs, LAST_QUEUE, TX_AM_ENABLE, TX_AM_POLL_SPEED, TX_UW_ENABLE, + TX_UW_POLL_SPEED, TX_Q_ENABLE); + + return 0; +} + +static struct sg_ops_s sg_ops = { + .nthw_virt_queue_init = nthw_virt_queue_init +}; + +void sg_init(void) +{ + NT_LOG(INF, NTNIC, "SG ops initialized\n"); + register_sg_ops(&sg_ops); +} diff --git a/drivers/net/ntnic/include/ntnic_dbs.h b/drivers/net/ntnic/include/ntnic_dbs.h index 551c6ade43..a64d2a0aeb 100644 --- a/drivers/net/ntnic/include/ntnic_dbs.h +++ b/drivers/net/ntnic/include/ntnic_dbs.h @@ -8,12 +8,81 @@ #include "nthw_fpga_model.h" +#define NT_DBS_RX_QUEUES_MAX (128) +#define NT_DBS_TX_QUEUES_MAX (128) + /* * Struct for implementation of memory bank shadows */ -struct nthw_dbs_s; +struct nthw_dbs_s { + nthw_fpga_t *mp_fpga; + nthw_module_t *mp_mod_dbs; + int mn_instance; + + int mn_param_dbs_present; + + nthw_register_t *mp_reg_rx_control; + nthw_field_t *mp_fld_rx_control_last_queue; + nthw_field_t *mp_fld_rx_control_avail_monitor_enable; + nthw_field_t *mp_fld_rx_control_avail_monitor_scan_speed; + nthw_field_t *mp_fld_rx_control_used_write_enable; + nthw_field_t *mp_fld_rx_control_used_writer_update_speed; + nthw_field_t *mp_fld_rx_control_rx_queues_enable; + + nthw_register_t *mp_reg_tx_control; + nthw_field_t *mp_fld_tx_control_last_queue; + nthw_field_t *mp_fld_tx_control_avail_monitor_enable; + nthw_field_t *mp_fld_tx_control_avail_monitor_scan_speed; + nthw_field_t *mp_fld_tx_control_used_write_enable; + nthw_field_t *mp_fld_tx_control_used_writer_update_speed; + nthw_field_t *mp_fld_tx_control_tx_queues_enable; + + nthw_register_t *mp_reg_rx_init; + nthw_field_t *mp_fld_rx_init_init; + nthw_field_t *mp_fld_rx_init_queue; + nthw_field_t *mp_fld_rx_init_busy; + + nthw_register_t *mp_reg_rx_init_val; + nthw_field_t *mp_fld_rx_init_val_idx; + nthw_field_t *mp_fld_rx_init_val_ptr; + + nthw_register_t *mp_reg_tx_init; + nthw_field_t *mp_fld_tx_init_init; + nthw_field_t *mp_fld_tx_init_queue; + nthw_field_t *mp_fld_tx_init_busy; + + nthw_register_t *mp_reg_tx_init_val; + nthw_field_t *mp_fld_tx_init_val_idx; + nthw_field_t *mp_fld_tx_init_val_ptr; + +}; typedef struct nthw_dbs_s nthw_dbs_t; +nthw_dbs_t *nthw_dbs_new(void); +int dbs_init(nthw_dbs_t *p, nthw_fpga_t *p_fpga, int n_instance); +void dbs_reset(nthw_dbs_t *p); + +int set_rx_control(nthw_dbs_t *p, + uint32_t last_queue, + uint32_t avail_monitor_enable, + uint32_t avail_monitor_speed, + uint32_t used_write_enable, + uint32_t used_write_speed, + uint32_t rx_queue_enable); +int set_tx_control(nthw_dbs_t *p, + uint32_t last_queue, + uint32_t avail_monitor_enable, + uint32_t avail_monitor_speed, + uint32_t used_write_enable, + uint32_t used_write_speed, + uint32_t tx_queue_enable); +int set_rx_init(nthw_dbs_t *p, uint32_t start_idx, uint32_t start_ptr, uint32_t init, + uint32_t queue); +int get_rx_init(nthw_dbs_t *p, uint32_t *init, uint32_t *queue, uint32_t *busy); +int set_tx_init(nthw_dbs_t *p, uint32_t start_idx, uint32_t start_ptr, uint32_t init, + uint32_t queue); +int get_tx_init(nthw_dbs_t *p, uint32_t *init, uint32_t *queue, uint32_t *busy); + #endif /* _NTNIC_DBS_H_ */ diff --git a/drivers/net/ntnic/meson.build b/drivers/net/ntnic/meson.build index 66d2770da7..3d9566a52e 100644 --- a/drivers/net/ntnic/meson.build +++ b/drivers/net/ntnic/meson.build @@ -24,9 +24,11 @@ includes = [ # all sources sources = files( 'adapter/nt4ga_adapter.c', + 'dbsconfig/ntnic_dbsconfig.c', 'link_mgmt/link_100g/nt4ga_link_100g.c', 'link_mgmt/nt4ga_link.c', 'nim/i2c_nim.c', + 'nthw/dbs/nthw_dbs.c', 'nthw/supported/nthw_fpga_9563_055_049_0000.c', 'nthw/supported/nthw_fpga_instances.c', 'nthw/supported/nthw_fpga_mod_str_map.c', diff --git a/drivers/net/ntnic/nthw/dbs/nthw_dbs.c b/drivers/net/ntnic/nthw/dbs/nthw_dbs.c new file mode 100644 index 0000000000..853d7bc1ec --- /dev/null +++ b/drivers/net/ntnic/nthw/dbs/nthw_dbs.c @@ -0,0 +1,135 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#include +#include "ntlog.h" + +#include "nthw_drv.h" +#include "nthw_register.h" + +nthw_dbs_t *nthw_dbs_new(void) +{ + nthw_dbs_t *p = malloc(sizeof(nthw_dbs_t)); + + if (p) + memset(p, 0, sizeof(nthw_dbs_t)); + + return p; +} + +int dbs_init(nthw_dbs_t *p, nthw_fpga_t *p_fpga, int n_instance) +{ + nthw_module_t *mod = nthw_fpga_query_module(p_fpga, MOD_DBS, n_instance); + + if (p == NULL) + return mod == NULL ? -1 : 0; + + if (mod == NULL) { + NT_LOG(ERR, NTHW, "%s: DBS %d: no such instance\n", + p_fpga->p_fpga_info->mp_adapter_id_str, n_instance); + return -1; + } + + p->mp_fpga = p_fpga; + p->mn_instance = n_instance; + p->mp_mod_dbs = mod; + + p->mn_param_dbs_present = nthw_fpga_get_product_param(p_fpga, NT_DBS_PRESENT, 0); + + if (p->mn_param_dbs_present == 0) { + NT_LOG(WRN, NTHW, + "%s: DBS %d: logical error: module found but not flagged at present\n", + p->mp_fpga->p_fpga_info->mp_adapter_id_str, p->mn_instance); + } + + return 0; +} + +void dbs_reset(nthw_dbs_t *p) +{ + (void)p; +} + +int set_rx_control(nthw_dbs_t *p, + uint32_t last_queue, + uint32_t avail_monitor_enable, + uint32_t avail_monitor_speed, + uint32_t used_write_enable, + uint32_t used_write_speed, + uint32_t rx_queue_enable) +{ + nthw_field_set_val32(p->mp_fld_rx_control_last_queue, last_queue); + nthw_field_set_val32(p->mp_fld_rx_control_avail_monitor_enable, avail_monitor_enable); + nthw_field_set_val32(p->mp_fld_rx_control_avail_monitor_scan_speed, avail_monitor_speed); + nthw_field_set_val32(p->mp_fld_rx_control_used_write_enable, used_write_enable); + nthw_field_set_val32(p->mp_fld_rx_control_used_writer_update_speed, used_write_speed); + nthw_field_set_val32(p->mp_fld_rx_control_rx_queues_enable, rx_queue_enable); + nthw_register_flush(p->mp_reg_rx_control, 1); + return 0; +} + +int set_tx_control(nthw_dbs_t *p, + uint32_t last_queue, + uint32_t avail_monitor_enable, + uint32_t avail_monitor_speed, + uint32_t used_write_enable, + uint32_t used_write_speed, + uint32_t tx_queue_enable) +{ + nthw_field_set_val32(p->mp_fld_tx_control_last_queue, last_queue); + nthw_field_set_val32(p->mp_fld_tx_control_avail_monitor_enable, avail_monitor_enable); + nthw_field_set_val32(p->mp_fld_tx_control_avail_monitor_scan_speed, avail_monitor_speed); + nthw_field_set_val32(p->mp_fld_tx_control_used_write_enable, used_write_enable); + nthw_field_set_val32(p->mp_fld_tx_control_used_writer_update_speed, used_write_speed); + nthw_field_set_val32(p->mp_fld_tx_control_tx_queues_enable, tx_queue_enable); + nthw_register_flush(p->mp_reg_tx_control, 1); + return 0; +} + +int set_rx_init(nthw_dbs_t *p, uint32_t start_idx, uint32_t start_ptr, uint32_t init, + uint32_t queue) +{ + if (p->mp_reg_rx_init_val) { + nthw_field_set_val32(p->mp_fld_rx_init_val_idx, start_idx); + nthw_field_set_val32(p->mp_fld_rx_init_val_ptr, start_ptr); + nthw_register_flush(p->mp_reg_rx_init_val, 1); + } + + nthw_field_set_val32(p->mp_fld_rx_init_init, init); + nthw_field_set_val32(p->mp_fld_rx_init_queue, queue); + nthw_register_flush(p->mp_reg_rx_init, 1); + return 0; +} + +int get_rx_init(nthw_dbs_t *p, uint32_t *init, uint32_t *queue, uint32_t *busy) +{ + *init = nthw_field_get_val32(p->mp_fld_rx_init_init); + *queue = nthw_field_get_val32(p->mp_fld_rx_init_queue); + *busy = nthw_field_get_val32(p->mp_fld_rx_init_busy); + return 0; +} + +int set_tx_init(nthw_dbs_t *p, uint32_t start_idx, uint32_t start_ptr, uint32_t init, + uint32_t queue) +{ + if (p->mp_reg_tx_init_val) { + nthw_field_set_val32(p->mp_fld_tx_init_val_idx, start_idx); + nthw_field_set_val32(p->mp_fld_tx_init_val_ptr, start_ptr); + nthw_register_flush(p->mp_reg_tx_init_val, 1); + } + + nthw_field_set_val32(p->mp_fld_tx_init_init, init); + nthw_field_set_val32(p->mp_fld_tx_init_queue, queue); + nthw_register_flush(p->mp_reg_tx_init, 1); + return 0; +} + +int get_tx_init(nthw_dbs_t *p, uint32_t *init, uint32_t *queue, uint32_t *busy) +{ + *init = nthw_field_get_val32(p->mp_fld_tx_init_init); + *queue = nthw_field_get_val32(p->mp_fld_tx_init_queue); + *busy = nthw_field_get_val32(p->mp_fld_tx_init_busy); + return 0; +} diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h index 5d6aac122c..b6be02f45e 100644 --- a/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h @@ -16,6 +16,7 @@ #define MOD_UNKNOWN (0L)/* Unknown/uninitialized - keep this as the first element */ #define MOD_CAT (0x30b447c2UL) #define MOD_CSU (0x3f470787UL) +#define MOD_DBS (0x80b29727UL) #define MOD_FLM (0xe7ba53a4UL) #define MOD_GFG (0xfc423807UL) #define MOD_GMF (0x68b1d15aUL) diff --git a/drivers/net/ntnic/ntnic_mod_reg.c b/drivers/net/ntnic/ntnic_mod_reg.c index 8fe5193027..a03c97801b 100644 --- a/drivers/net/ntnic/ntnic_mod_reg.c +++ b/drivers/net/ntnic/ntnic_mod_reg.c @@ -5,9 +5,18 @@ #include "ntnic_mod_reg.h" +static struct sg_ops_s *sg_ops; + +void register_sg_ops(struct sg_ops_s *ops) +{ + sg_ops = ops; +} + const struct sg_ops_s *get_sg_ops(void) { - return NULL; + if (sg_ops == NULL) + sg_init(); + return sg_ops; } static struct link_ops_s *link_100g_ops; diff --git a/drivers/net/ntnic/ntnic_mod_reg.h b/drivers/net/ntnic/ntnic_mod_reg.h index e9dff51935..5b97b3d8ac 100644 --- a/drivers/net/ntnic/ntnic_mod_reg.h +++ b/drivers/net/ntnic/ntnic_mod_reg.h @@ -105,7 +105,9 @@ struct sg_ops_s { int (*nthw_virt_queue_init)(struct fpga_info_s *p_fpga_info); }; +void register_sg_ops(struct sg_ops_s *ops); const struct sg_ops_s *get_sg_ops(void); +void sg_init(void); struct link_ops_s { int (*link_init)(struct adapter_info_s *p_adapter_info, nthw_fpga_t *p_fpga); -- 2.45.0