From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8A81245AAF; Fri, 4 Oct 2024 17:54:11 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CE46C42E77; Fri, 4 Oct 2024 17:51:28 +0200 (CEST) Received: from egress-ip11a.ess.de.barracuda.com (egress-ip11a.ess.de.barracuda.com [18.184.203.234]) by mails.dpdk.org (Postfix) with ESMTP id DB17D42E90 for ; Fri, 4 Oct 2024 17:51:24 +0200 (CEST) Received: from EUR05-DB8-obe.outbound.protection.outlook.com (mail-db8eur05lp2105.outbound.protection.outlook.com [104.47.17.105]) by mx-outbound8-201.eu-central-1a.ess.aws.cudaops.com (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Fri, 04 Oct 2024 15:51:23 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=iheGQ+8jVziSsvDPactGxkNrHuOxFsndxp3AgYDIY48PLj50YGehCz8rjpGP7NOQd7ugskusLHm7be1jJdjFFUUgqN16PtaSPMq//gTuEJ0IUMI2HqXO45le+25ozp+Ij01uZavi6u9A/P4oO0vS+0gr3JKhsZ3GfcA58CeHkjZ2aGFDkjpe1VRrQT+NIH7UBTQbE3Hc2hFNDonykNe40EJZ6SUNcrAIaLQjVoWXXKIut/Kn9kTMrZ45Uc/Da9yYJ1T3lNUvVRSu9sAbXKAZGV7NbCTNbUNkbEr+1Krye6kRyT4oMLGWpAf94BD1ETWvgSCn23QVErQUeuoqpSdAPA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=4XLft5na3I04QiHjYdk5JW435J6vqBFNWzVKQZRDGTM=; b=OouYV2B/a9Xq6dyBvnJKRlyki5vGgm4I1Mzez0SjR0DVBwO0q4a5Skd/pWLHqZtnXp4RhOLSYDXvbIDMp0J/Wxo/2shZfrFClVULEqhu9guURVVVoLUFMmdw9SjFaDb+U11YUMFe5sFBUmKN4sRfDfUqJPBSRUL8XRkWRZNU5LZvAEaoaKlurcUxnOZ59CLbpj67LNXuYdnOQEojwNTiKK0NggkCiAuP1TW1e+PixJnbYSrH7t6/p8zRFhKKVENLnmOAjPciZ6vYeUomi8/J9wqRt9t3eqBur2pp/01cuIDiWKoPXTCqEycuePnc2+wogFMBBnuuvfZw96t87VEIYw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=fail (sender ip is 178.72.21.4) smtp.rcpttodomain=dpdk.org smtp.mailfrom=napatech.com; dmarc=fail (p=reject sp=reject pct=100) action=oreject header.from=napatech.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=napatech.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=4XLft5na3I04QiHjYdk5JW435J6vqBFNWzVKQZRDGTM=; b=Dxgk9u82+mODz0A1B6EAL76I979QI8b5+51voPWu6St1vtqx+P5Xbm+bA2HWXihk6SjiOTdgMuu8ys0EddTlbPFIAcomqDCQ4/58pDlL07v+l/54DzIQxvtRSyLXZSZuimei8uud6Xfq4sLnnZXTP2zAwtRq1T9Kn+F67aLNzug= Received: from AM0PR10CA0106.EURPRD10.PROD.OUTLOOK.COM (2603:10a6:208:e6::23) by DBAP190MB0920.EURP190.PROD.OUTLOOK.COM (2603:10a6:10:1a7::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7962.17; Fri, 4 Oct 2024 15:36:38 +0000 Received: from AM2PEPF0001C715.eurprd05.prod.outlook.com (2603:10a6:208:e6:cafe::af) by AM0PR10CA0106.outlook.office365.com (2603:10a6:208:e6::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8026.18 via Frontend Transport; Fri, 4 Oct 2024 15:36:38 +0000 X-MS-Exchange-Authentication-Results: spf=fail (sender IP is 178.72.21.4) smtp.mailfrom=napatech.com; dkim=none (message not signed) header.d=none;dmarc=fail action=oreject header.from=napatech.com; Received-SPF: Fail (protection.outlook.com: domain of napatech.com does not designate 178.72.21.4 as permitted sender) receiver=protection.outlook.com; client-ip=178.72.21.4; helo=localhost.localdomain; Received: from localhost.localdomain (178.72.21.4) by AM2PEPF0001C715.mail.protection.outlook.com (10.167.16.185) with Microsoft SMTP Server id 15.20.7918.13 via Frontend Transport; Fri, 4 Oct 2024 15:36:38 +0000 From: Serhii Iliushyk To: dev@dpdk.org Cc: mko-plv@napatech.com, sil-plv@napatech.com, ckm@napatech.com, andrew.rybchenko@oktetlabs.ru, ferruh.yigit@amd.com Subject: [PATCH v1 11/14] net/ntnic: update FPGA registeris related to DBS Date: Fri, 4 Oct 2024 17:35:05 +0200 Message-ID: <20241004153551.267935-48-sil-plv@napatech.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20241004153551.267935-1-sil-plv@napatech.com> References: <20241004153551.267935-1-sil-plv@napatech.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM2PEPF0001C715:EE_|DBAP190MB0920:EE_ Content-Type: text/plain X-MS-Office365-Filtering-Correlation-Id: a66f0fff-f8b6-4e7b-80b4-08dce48a562d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|376014|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?DJdB0wFznldgmmumKwNKT2I1VGm/BONjYO8LkjjI/C/ysIdKB6gl6adhddGU?= =?us-ascii?Q?e9g9HM2es5ytKxN4TZUK1Wme1DSSIoeHqoqTB/iQ1WjJBS+gJ1++XAVNP7Oq?= =?us-ascii?Q?Cz25V7+Ev5+Hrt24DSZuiDTSptXsFdUFpp3bWYF0qKxCBL5qa/ZarsN3p2qI?= =?us-ascii?Q?dVB6eP46uQTOUEhuVykfph0Yd68WV6RSCwFPL+TtuWLXJoIvjIT8XcmCvJiL?= =?us-ascii?Q?yqg5WcpZuiviVGPCGvGPQ6ZxhLw3rx9b0k604Ijp5xjtY1dNf171y+EqddwP?= =?us-ascii?Q?CsYWqrYOrlBb7iinDae8FsJARgq3/kF4hV/1j1mkGHRu0EMR+KStcaibXWil?= =?us-ascii?Q?W5rPDFJ+OV3G/rohfmlGGiS1WXaCRwfzhH4xmEsLhQgaXMVwDgsUG28RQoD1?= =?us-ascii?Q?UXI6GJAEQk2uJgaG5NpDljCrgxIPpv7oHxhPJOGSXyolNd+JDpTYGPl3FMqS?= =?us-ascii?Q?MsonHWtNGcLDVr7wpN0+pUhzsdwVDezHI5eSQWG+hf1HN4fGseZIX1lng9Ii?= =?us-ascii?Q?ZGVk5Uy2Z3FSYHvHjIpBr+EsFoR5NDTuQVzDf7Mye6wyjC9+siyoUjSLMb1U?= =?us-ascii?Q?zzc2on/VGJ3GocjjT95L3tw/Quxey3v1wK27NFgpeXfqwopzqODiwT9K+NB6?= =?us-ascii?Q?a6R56XYp7e+3X8guRgPGi9GJcorfd8YZo4NWQaDhZAinkZsQ9sXxTmSyDr3D?= =?us-ascii?Q?qvAopDgrjJXMn3xm+jO8YzLw49YeMYkkPTxDeRUaNJ9p3RSUfae7pB1dpAgw?= =?us-ascii?Q?MYN05D4tguowpd4aYLRZBi4nhbuQg9XaLhRKnoZ2Xepg/Zs2boSL8HvXFq1G?= =?us-ascii?Q?D9L2GUgzSbuM8jCn/mxFr6suLqmLtu3ZBRPcZVpGaUKzHEKa2/4H8rp30h6O?= =?us-ascii?Q?IZTfDWL3HKLVxu3nngg5Sp5aTh/4ITX+VhKF+dM7Bb9AyBOFywIbdeqfU41l?= =?us-ascii?Q?qgaxG45/euwZTlqVzClcrEJ0LhOloEyDDhyXo9bzyANR2WUrwZDcJrgwapvz?= =?us-ascii?Q?rsgDkoIJPOiOyeUWnMM7YFiNivZvDsp/fmzoGm3nd1Zh8sjsOe/J/HyeZVbA?= =?us-ascii?Q?TxIC/Gt5SBBsiU4KKKNOra0WgacJUP1RYaJUWwndzQ8+sR6hANspBBPs/z3M?= =?us-ascii?Q?WOBEno4DhSRWXEciNi3NOcZnAVunpRNMUZAZRXE3RTK/NcreOVsnAX3Jar0+?= =?us-ascii?Q?eC8mpPD7jvMW/T8KEEJns/ieISbkjW+jZq4Wc9jOgPlh+XU2hd9Tyt+Vrat1?= =?us-ascii?Q?6sTBwSbsxl/FMBvTe6hO/ypehA98hOOE1WoLKcIE1WPzr1XZBti8NMeqFbDQ?= =?us-ascii?Q?Gbf8dU/DT9HoNj1HCw20eDUW6ptP1BqDwjGzwDtS6wtJ3uuZDZdAMjRBAEjY?= =?us-ascii?Q?KGZbzCr/pxxa3OCtqt2OnoHC2aoy?= X-Forefront-Antispam-Report: CIP:178.72.21.4; CTRY:DK; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:localhost.localdomain; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(1800799024)(376014)(36860700013)(82310400026); DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-ExternalHop-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-ExternalHop-MessageData-0: UYR3kIc9yiXsLZ1iJhUnopkV0r60gLccAMEBxyf5clPZeuaWaNgTD0ME93iwtZprJLNF43oC5AglIhQ3LXLHIZiI1wByNbw0+JABGWjkkhPqGJRqIr5GFB0mUp7O9UfQd8ysUE1M4eVq5va/Bt7nRxKNlCW+Qh61NizUPZGLvGx9GpSIJQKVl/CnK4GqbNaXqm1fNRCxcITYullrt13MSGqAgzV+psNxtV4fCxZe0c+08hFav7K3ImuWJre2tgVb4PQLz3W9EFYoI4BuMsd6lmJ9iRi+kdHOtByfkla4AOxvP48PlmJO5apwgcx6aNIVOHK4k7ukDf2Xc7HJVMyJqAJ5iByQ8wAgVyGrRBFjZ/ON91qT+aklhGEja+eDX1t+AdfGmAe16XIDmbiE32nZjKFCoKPwkRSxrfbf+fhVGjDhd+eqgZnWuZNqL09hpodtyxEEg6orCuGC7KVS/XPHyP9HvkPiiit2UVl93FHYpBTCCjUtcz/uArDfD+AXJ25ZHx7klznCv9cYK+2ug84frheJ78aoXacdFnlQdgo601NU1Nuhkzz5RaH+6Ek2h52gqGBNfHTl9i+CwY3QgJ9BSDhkG3Puc/Wr2pGvMPPRUkD+OnL56eeNxiH7NeTDfUY0ix2oBHedRR15sAyaW7s5aA== X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Oct 2024 15:36:38.0647 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a66f0fff-f8b6-4e7b-80b4-08dce48a562d X-MS-Exchange-CrossTenant-Id: c4540d0b-728a-4233-9da5-9ea30c7ec3ed X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=c4540d0b-728a-4233-9da5-9ea30c7ec3ed; Ip=[178.72.21.4]; Helo=[localhost.localdomain] X-MS-Exchange-CrossTenant-AuthSource: AM2PEPF0001C715.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBAP190MB0920 X-OriginatorOrg: napatech.com X-BESS-ID: 1728057083-302249-12642-33886-1 X-BESS-VER: 2019.1_20240924.1654 X-BESS-Apparent-Source-IP: 104.47.17.105 X-BESS-Parts: H4sIAAAAAAACA4uuVkqtKFGyUioBkjpK+cVKVpaGZhZAVgZQMNXUItksxdDc0C TVwtjSwiDJLNHIJM0wOcXYNNE0Jc1QqTYWAOuCi1NBAAAA X-BESS-Outbound-Spam-Score: 0.00 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.259494 [from cloudscan9-172.eu-central-1a.ess.aws.cudaops.com] Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.00 using account:ESS113687 scores of KILL_LEVEL=7.0 tests=BSF_BESS_OUTBOUND X-BESS-BRTS-Status: 1 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org DBS - DVIO Buffer System Signed-off-by: Serhii Iliushyk --- .../supported/nthw_fpga_9563_055_049_0000.c | 184 +++++++++++++++++- 1 file changed, 183 insertions(+), 1 deletion(-) diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_049_0000.c b/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_049_0000.c index 98b857158e..6df7208649 100644 --- a/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_049_0000.c +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_049_0000.c @@ -1541,10 +1541,192 @@ static nthw_fpga_register_init_s rst9563_registers[] = { { RST9563_STICKY, 3, 6, NTHW_FPGA_REG_TYPE_RC1, 0, 6, rst9563_sticky_fields }, }; +static nthw_fpga_field_init_s dbs_rx_am_ctrl_fields[] = { + { DBS_RX_AM_CTRL_ADR, 7, 0, 0x0000 }, + { DBS_RX_AM_CTRL_CNT, 16, 16, 0x0000 }, +}; + +static nthw_fpga_field_init_s dbs_rx_am_data_fields[] = { + { DBS_RX_AM_DATA_ENABLE, 1, 72, 0x0000 }, { DBS_RX_AM_DATA_GPA, 64, 0, 0x0000 }, + { DBS_RX_AM_DATA_HID, 8, 64, 0x0000 }, { DBS_RX_AM_DATA_INT, 1, 74, 0x0000 }, + { DBS_RX_AM_DATA_PCKED, 1, 73, 0x0000 }, +}; + +static nthw_fpga_field_init_s dbs_rx_control_fields[] = { + { DBS_RX_CONTROL_AME, 1, 7, 0 }, { DBS_RX_CONTROL_AMS, 4, 8, 8 }, + { DBS_RX_CONTROL_LQ, 7, 0, 0 }, { DBS_RX_CONTROL_QE, 1, 17, 0 }, + { DBS_RX_CONTROL_UWE, 1, 12, 0 }, { DBS_RX_CONTROL_UWS, 4, 13, 5 }, +}; + +static nthw_fpga_field_init_s dbs_rx_dr_ctrl_fields[] = { + { DBS_RX_DR_CTRL_ADR, 7, 0, 0x0000 }, + { DBS_RX_DR_CTRL_CNT, 16, 16, 0x0000 }, +}; + +static nthw_fpga_field_init_s dbs_rx_dr_data_fields[] = { + { DBS_RX_DR_DATA_GPA, 64, 0, 0x0000 }, { DBS_RX_DR_DATA_HDR, 1, 88, 0x0000 }, + { DBS_RX_DR_DATA_HID, 8, 64, 0x0000 }, { DBS_RX_DR_DATA_PCKED, 1, 87, 0x0000 }, + { DBS_RX_DR_DATA_QS, 15, 72, 0x0000 }, +}; + +static nthw_fpga_field_init_s dbs_rx_idle_fields[] = { + { DBS_RX_IDLE_BUSY, 1, 8, 0 }, + { DBS_RX_IDLE_IDLE, 1, 0, 0x0000 }, + { DBS_RX_IDLE_QUEUE, 7, 1, 0x0000 }, +}; + +static nthw_fpga_field_init_s dbs_rx_init_fields[] = { + { DBS_RX_INIT_BUSY, 1, 8, 0 }, + { DBS_RX_INIT_INIT, 1, 0, 0x0000 }, + { DBS_RX_INIT_QUEUE, 7, 1, 0x0000 }, +}; + +static nthw_fpga_field_init_s dbs_rx_init_val_fields[] = { + { DBS_RX_INIT_VAL_IDX, 16, 0, 0x0000 }, + { DBS_RX_INIT_VAL_PTR, 15, 16, 0x0000 }, +}; + +static nthw_fpga_field_init_s dbs_rx_ptr_fields[] = { + { DBS_RX_PTR_PTR, 16, 0, 0x0000 }, + { DBS_RX_PTR_QUEUE, 7, 16, 0x0000 }, + { DBS_RX_PTR_VALID, 1, 23, 0x0000 }, +}; + +static nthw_fpga_field_init_s dbs_rx_uw_ctrl_fields[] = { + { DBS_RX_UW_CTRL_ADR, 7, 0, 0x0000 }, + { DBS_RX_UW_CTRL_CNT, 16, 16, 0x0000 }, +}; + +static nthw_fpga_field_init_s dbs_rx_uw_data_fields[] = { + { DBS_RX_UW_DATA_GPA, 64, 0, 0x0000 }, { DBS_RX_UW_DATA_HID, 8, 64, 0x0000 }, + { DBS_RX_UW_DATA_INT, 1, 88, 0x0000 }, { DBS_RX_UW_DATA_ISTK, 1, 92, 0x0000 }, + { DBS_RX_UW_DATA_PCKED, 1, 87, 0x0000 }, { DBS_RX_UW_DATA_QS, 15, 72, 0x0000 }, + { DBS_RX_UW_DATA_VEC, 3, 89, 0x0000 }, +}; + +static nthw_fpga_field_init_s dbs_tx_am_ctrl_fields[] = { + { DBS_TX_AM_CTRL_ADR, 7, 0, 0x0000 }, + { DBS_TX_AM_CTRL_CNT, 16, 16, 0x0000 }, +}; + +static nthw_fpga_field_init_s dbs_tx_am_data_fields[] = { + { DBS_TX_AM_DATA_ENABLE, 1, 72, 0x0000 }, { DBS_TX_AM_DATA_GPA, 64, 0, 0x0000 }, + { DBS_TX_AM_DATA_HID, 8, 64, 0x0000 }, { DBS_TX_AM_DATA_INT, 1, 74, 0x0000 }, + { DBS_TX_AM_DATA_PCKED, 1, 73, 0x0000 }, +}; + +static nthw_fpga_field_init_s dbs_tx_control_fields[] = { + { DBS_TX_CONTROL_AME, 1, 7, 0 }, { DBS_TX_CONTROL_AMS, 4, 8, 5 }, + { DBS_TX_CONTROL_LQ, 7, 0, 0 }, { DBS_TX_CONTROL_QE, 1, 17, 0 }, + { DBS_TX_CONTROL_UWE, 1, 12, 0 }, { DBS_TX_CONTROL_UWS, 4, 13, 8 }, +}; + +static nthw_fpga_field_init_s dbs_tx_dr_ctrl_fields[] = { + { DBS_TX_DR_CTRL_ADR, 7, 0, 0x0000 }, + { DBS_TX_DR_CTRL_CNT, 16, 16, 0x0000 }, +}; + +static nthw_fpga_field_init_s dbs_tx_dr_data_fields[] = { + { DBS_TX_DR_DATA_GPA, 64, 0, 0x0000 }, { DBS_TX_DR_DATA_HDR, 1, 88, 0x0000 }, + { DBS_TX_DR_DATA_HID, 8, 64, 0x0000 }, { DBS_TX_DR_DATA_PCKED, 1, 87, 0x0000 }, + { DBS_TX_DR_DATA_PORT, 1, 89, 0x0000 }, { DBS_TX_DR_DATA_QS, 15, 72, 0x0000 }, +}; + +static nthw_fpga_field_init_s dbs_tx_idle_fields[] = { + { DBS_TX_IDLE_BUSY, 1, 8, 0 }, + { DBS_TX_IDLE_IDLE, 1, 0, 0x0000 }, + { DBS_TX_IDLE_QUEUE, 7, 1, 0x0000 }, +}; + +static nthw_fpga_field_init_s dbs_tx_init_fields[] = { + { DBS_TX_INIT_BUSY, 1, 8, 0 }, + { DBS_TX_INIT_INIT, 1, 0, 0x0000 }, + { DBS_TX_INIT_QUEUE, 7, 1, 0x0000 }, +}; + +static nthw_fpga_field_init_s dbs_tx_init_val_fields[] = { + { DBS_TX_INIT_VAL_IDX, 16, 0, 0x0000 }, + { DBS_TX_INIT_VAL_PTR, 15, 16, 0x0000 }, +}; + +static nthw_fpga_field_init_s dbs_tx_ptr_fields[] = { + { DBS_TX_PTR_PTR, 16, 0, 0x0000 }, + { DBS_TX_PTR_QUEUE, 7, 16, 0x0000 }, + { DBS_TX_PTR_VALID, 1, 23, 0x0000 }, +}; + +static nthw_fpga_field_init_s dbs_tx_qos_ctrl_fields[] = { + { DBS_TX_QOS_CTRL_ADR, 1, 0, 0x0000 }, + { DBS_TX_QOS_CTRL_CNT, 16, 16, 0x0000 }, +}; + +static nthw_fpga_field_init_s dbs_tx_qos_data_fields[] = { + { DBS_TX_QOS_DATA_BS, 27, 17, 0x0000 }, + { DBS_TX_QOS_DATA_EN, 1, 0, 0x0000 }, + { DBS_TX_QOS_DATA_IR, 16, 1, 0x0000 }, +}; + +static nthw_fpga_field_init_s dbs_tx_qos_rate_fields[] = { + { DBS_TX_QOS_RATE_DIV, 19, 16, 2 }, + { DBS_TX_QOS_RATE_MUL, 16, 0, 1 }, +}; + +static nthw_fpga_field_init_s dbs_tx_qp_ctrl_fields[] = { + { DBS_TX_QP_CTRL_ADR, 7, 0, 0x0000 }, + { DBS_TX_QP_CTRL_CNT, 16, 16, 0x0000 }, +}; + +static nthw_fpga_field_init_s dbs_tx_qp_data_fields[] = { + { DBS_TX_QP_DATA_VPORT, 1, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s dbs_tx_uw_ctrl_fields[] = { + { DBS_TX_UW_CTRL_ADR, 7, 0, 0x0000 }, + { DBS_TX_UW_CTRL_CNT, 16, 16, 0x0000 }, +}; + +static nthw_fpga_field_init_s dbs_tx_uw_data_fields[] = { + { DBS_TX_UW_DATA_GPA, 64, 0, 0x0000 }, { DBS_TX_UW_DATA_HID, 8, 64, 0x0000 }, + { DBS_TX_UW_DATA_INO, 1, 93, 0x0000 }, { DBS_TX_UW_DATA_INT, 1, 88, 0x0000 }, + { DBS_TX_UW_DATA_ISTK, 1, 92, 0x0000 }, { DBS_TX_UW_DATA_PCKED, 1, 87, 0x0000 }, + { DBS_TX_UW_DATA_QS, 15, 72, 0x0000 }, { DBS_TX_UW_DATA_VEC, 3, 89, 0x0000 }, +}; + +static nthw_fpga_register_init_s dbs_registers[] = { + { DBS_RX_AM_CTRL, 10, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, dbs_rx_am_ctrl_fields }, + { DBS_RX_AM_DATA, 11, 75, NTHW_FPGA_REG_TYPE_WO, 0, 5, dbs_rx_am_data_fields }, + { DBS_RX_CONTROL, 0, 18, NTHW_FPGA_REG_TYPE_RW, 43008, 6, dbs_rx_control_fields }, + { DBS_RX_DR_CTRL, 18, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, dbs_rx_dr_ctrl_fields }, + { DBS_RX_DR_DATA, 19, 89, NTHW_FPGA_REG_TYPE_WO, 0, 5, dbs_rx_dr_data_fields }, + { DBS_RX_IDLE, 8, 9, NTHW_FPGA_REG_TYPE_MIXED, 0, 3, dbs_rx_idle_fields }, + { DBS_RX_INIT, 2, 9, NTHW_FPGA_REG_TYPE_MIXED, 0, 3, dbs_rx_init_fields }, + { DBS_RX_INIT_VAL, 3, 31, NTHW_FPGA_REG_TYPE_WO, 0, 2, dbs_rx_init_val_fields }, + { DBS_RX_PTR, 4, 24, NTHW_FPGA_REG_TYPE_MIXED, 0, 3, dbs_rx_ptr_fields }, + { DBS_RX_UW_CTRL, 14, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, dbs_rx_uw_ctrl_fields }, + { DBS_RX_UW_DATA, 15, 93, NTHW_FPGA_REG_TYPE_WO, 0, 7, dbs_rx_uw_data_fields }, + { DBS_TX_AM_CTRL, 12, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, dbs_tx_am_ctrl_fields }, + { DBS_TX_AM_DATA, 13, 75, NTHW_FPGA_REG_TYPE_WO, 0, 5, dbs_tx_am_data_fields }, + { DBS_TX_CONTROL, 1, 18, NTHW_FPGA_REG_TYPE_RW, 66816, 6, dbs_tx_control_fields }, + { DBS_TX_DR_CTRL, 20, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, dbs_tx_dr_ctrl_fields }, + { DBS_TX_DR_DATA, 21, 90, NTHW_FPGA_REG_TYPE_WO, 0, 6, dbs_tx_dr_data_fields }, + { DBS_TX_IDLE, 9, 9, NTHW_FPGA_REG_TYPE_MIXED, 0, 3, dbs_tx_idle_fields }, + { DBS_TX_INIT, 5, 9, NTHW_FPGA_REG_TYPE_MIXED, 0, 3, dbs_tx_init_fields }, + { DBS_TX_INIT_VAL, 6, 31, NTHW_FPGA_REG_TYPE_WO, 0, 2, dbs_tx_init_val_fields }, + { DBS_TX_PTR, 7, 24, NTHW_FPGA_REG_TYPE_MIXED, 0, 3, dbs_tx_ptr_fields }, + { DBS_TX_QOS_CTRL, 24, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, dbs_tx_qos_ctrl_fields }, + { DBS_TX_QOS_DATA, 25, 44, NTHW_FPGA_REG_TYPE_WO, 0, 3, dbs_tx_qos_data_fields }, + { DBS_TX_QOS_RATE, 26, 35, NTHW_FPGA_REG_TYPE_RW, 131073, 2, dbs_tx_qos_rate_fields }, + { DBS_TX_QP_CTRL, 22, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, dbs_tx_qp_ctrl_fields }, + { DBS_TX_QP_DATA, 23, 1, NTHW_FPGA_REG_TYPE_WO, 0, 1, dbs_tx_qp_data_fields }, + { DBS_TX_UW_CTRL, 16, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, dbs_tx_uw_ctrl_fields }, + { DBS_TX_UW_DATA, 17, 94, NTHW_FPGA_REG_TYPE_WO, 0, 8, dbs_tx_uw_data_fields }, +}; + static nthw_fpga_module_init_s fpga_modules[] = { { MOD_CAT, 0, MOD_CAT, 0, 21, NTHW_FPGA_BUS_TYPE_RAB1, 768, 34, cat_registers }, { MOD_GFG, 0, MOD_GFG, 1, 1, NTHW_FPGA_BUS_TYPE_RAB2, 8704, 10, gfg_registers }, { MOD_GMF, 0, MOD_GMF, 2, 5, NTHW_FPGA_BUS_TYPE_RAB2, 9216, 12, gmf_registers }, + { MOD_DBS, 0, MOD_DBS, 0, 11, NTHW_FPGA_BUS_TYPE_RAB2, 12832, 27, dbs_registers}, { MOD_GMF, 1, MOD_GMF, 2, 5, NTHW_FPGA_BUS_TYPE_RAB2, 9728, 12, gmf_registers }, { MOD_GPIO_PHY, 0, MOD_GPIO_PHY, 1, 0, NTHW_FPGA_BUS_TYPE_RAB0, 16386, 2, @@ -1737,5 +1919,5 @@ static nthw_fpga_prod_param_s product_parameters[] = { }; nthw_fpga_prod_init_s nthw_fpga_9563_055_049_0000 = { - 200, 9563, 55, 49, 0, 0, 1726740521, 152, product_parameters, 21, fpga_modules, + 200, 9563, 55, 49, 0, 0, 1726740521, 152, product_parameters, 22, fpga_modules, }; -- 2.45.0