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[204.195.96.226]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20c138aff3dsm57381425ad.1.2024.10.08.08.35.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Oct 2024 08:35:50 -0700 (PDT) Date: Tue, 8 Oct 2024 08:35:48 -0700 From: Stephen Hemminger To: =?UTF-8?B?U3RhbmlzxYJhdw==?= Kardach Cc: Morten =?UTF-8?B?QnLDuHJ1cA==?= , Bruce Richardson , dev@dpdk.org, Liang Ma , Punit Agrawal , Pengcheng Wang , Chunsong Feng Subject: Re: [PATCH 1/5] config/riscv: add flag for using Zbc extension Message-ID: <20241008083548.0958196c@hermes.local> In-Reply-To: References: <20240618174133.33457-1-daniel.gregory@bytedance.com> <20240618174133.33457-2-daniel.gregory@bytedance.com> <20240618130318.0efacceb@hermes.local> <98CBD80474FA8B44BF855DF32C47DC35E9F53C@smartserver.smartshare.dk> <20240619164114.GA88106@ste-uk-lab-gw> <20241007082019.55d64b3b@hermes.local> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org On Tue, 8 Oct 2024 07:52:42 +0200 Stanis=C5=82aw Kardach wrote: > On Mon, Oct 7, 2024 at 5:20=E2=80=AFPM Stephen Hemminger > wrote: > > > > On Mon, 7 Oct 2024 10:14:22 +0200 > > Stanis=C5=82aw Kardach wrote: > > =20 > > > > > > > > > > > > Please do not add more config options via compile flags. > > > > > > It makes it impossible for distros to ship one version. =20 > > > That is a problem with RISC-V in general. Since all features are > > > "extensions" and there is no limit (up to a point) on the permutation > > > of those, we cannot statically build the code for all extensions. > > > Fortunately instructions tend to resolve to nops if an instruction is > > > not present but that still increases the code size for no benefit on > > > platforms without a given extension. =20 > > > > X86 already has the cpu feature flag infrastructure, why not use similar > > mechanism on RiscV? =20 > We can and some further patches I've seen on the list implemented > that. However if that has to be applied in basic intrinsics like > rte_prefetch() which means we'd have to pay a conditional or an > indirect call. It'd be best to test it on a real dataplane platform to > which I don't have access. That makes sense, is there some config file per cpu type like Arm?