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From: Tomasz Duszynski <tduszynski@marvell.com>
To: <tduszynski@marvell.com>, Wathsala Vithanage <wathsala.vithanage@arm.com>
CC: <Ruifeng.Wang@arm.com>, <bruce.richardson@intel.com>,
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Subject: [PATCH v14 2/4] pmu: support reading ARM PMU events in runtime
Date: Fri, 11 Oct 2024 11:49:42 +0200
Message-ID: <20241011094944.3586051-3-tduszynski@marvell.com>
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Add support for reading ARM PMU events in runtime.
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
---
app/test/test_pmu.c | 4 ++
lib/pmu/meson.build | 8 ++++
lib/pmu/pmu_arm64.c | 94 +++++++++++++++++++++++++++++++++++++
lib/pmu/rte_pmu.h | 4 ++
lib/pmu/rte_pmu_pmc_arm64.h | 30 ++++++++++++
5 files changed, 140 insertions(+)
create mode 100644 lib/pmu/pmu_arm64.c
create mode 100644 lib/pmu/rte_pmu_pmc_arm64.h
diff --git a/app/test/test_pmu.c b/app/test/test_pmu.c
index 79376ea2e8..e0809a0f93 100644
--- a/app/test/test_pmu.c
+++ b/app/test/test_pmu.c
@@ -13,6 +13,10 @@ test_pmu_read(void)
int tries = 10, event;
uint64_t val = 0;
+#if defined(RTE_ARCH_ARM64)
+ name = "cpu_cycles";
+#endif
+
if (name == NULL) {
printf("PMU not supported on this arch\n");
return TEST_SKIPPED;
diff --git a/lib/pmu/meson.build b/lib/pmu/meson.build
index 386232e5c7..0d9270eaca 100644
--- a/lib/pmu/meson.build
+++ b/lib/pmu/meson.build
@@ -9,4 +9,12 @@ endif
sources = files('rte_pmu.c')
+indirect_headers += files(
+ 'rte_pmu_pmc_arm64.h',
+)
+
+if dpdk_conf.has('RTE_ARCH_ARM64')
+ sources += files('pmu_arm64.c')
+endif
+
deps += ['log']
diff --git a/lib/pmu/pmu_arm64.c b/lib/pmu/pmu_arm64.c
new file mode 100644
index 0000000000..3b72009cff
--- /dev/null
+++ b/lib/pmu/pmu_arm64.c
@@ -0,0 +1,94 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2024 Marvell International Ltd.
+ */
+
+#include <errno.h>
+#include <fcntl.h>
+#include <stdlib.h>
+#include <unistd.h>
+
+#include <rte_bitops.h>
+#include <rte_common.h>
+
+#include "pmu_private.h"
+
+#define PERF_USER_ACCESS_PATH "/proc/sys/kernel/perf_user_access"
+
+static int restore_uaccess;
+
+static int
+read_attr_int(const char *path, int *val)
+{
+ char buf[BUFSIZ];
+ int ret, fd;
+
+ fd = open(path, O_RDONLY);
+ if (fd == -1)
+ return -errno;
+
+ ret = read(fd, buf, sizeof(buf));
+ if (ret == -1) {
+ close(fd);
+
+ return -errno;
+ }
+
+ *val = strtol(buf, NULL, 10);
+ close(fd);
+
+ return 0;
+}
+
+static int
+write_attr_int(const char *path, int val)
+{
+ char buf[BUFSIZ];
+ int num, ret, fd;
+
+ fd = open(path, O_WRONLY);
+ if (fd == -1)
+ return -errno;
+
+ num = snprintf(buf, sizeof(buf), "%d", val);
+ ret = write(fd, buf, num);
+ if (ret == -1) {
+ close(fd);
+
+ return -errno;
+ }
+
+ close(fd);
+
+ return 0;
+}
+
+int
+pmu_arch_init(void)
+{
+ int ret;
+
+ ret = read_attr_int(PERF_USER_ACCESS_PATH, &restore_uaccess);
+ if (ret)
+ return ret;
+
+ /* user access already enabled */
+ if (restore_uaccess == 1)
+ return 0;
+
+ return write_attr_int(PERF_USER_ACCESS_PATH, 1);
+}
+
+void
+pmu_arch_fini(void)
+{
+ write_attr_int(PERF_USER_ACCESS_PATH, restore_uaccess);
+}
+
+void
+pmu_arch_fixup_config(uint64_t config[3])
+{
+ /* select 64 bit counters */
+ config[1] |= RTE_BIT64(0);
+ /* enable userspace access */
+ config[1] |= RTE_BIT64(1);
+}
diff --git a/lib/pmu/rte_pmu.h b/lib/pmu/rte_pmu.h
index 09238ee33d..771fad31d0 100644
--- a/lib/pmu/rte_pmu.h
+++ b/lib/pmu/rte_pmu.h
@@ -31,6 +31,10 @@ extern "C" {
#include <rte_branch_prediction.h>
#include <rte_spinlock.h>
+#if defined(RTE_ARCH_ARM64)
+#include "rte_pmu_pmc_arm64.h"
+#endif
+
/** Maximum number of events in a group */
#define RTE_MAX_NUM_GROUP_EVENTS 8
diff --git a/lib/pmu/rte_pmu_pmc_arm64.h b/lib/pmu/rte_pmu_pmc_arm64.h
new file mode 100644
index 0000000000..39165bbc20
--- /dev/null
+++ b/lib/pmu/rte_pmu_pmc_arm64.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2024 Marvell.
+ */
+#ifndef _RTE_PMU_PMC_ARM64_H_
+#define _RTE_PMU_PMC_ARM64_H_
+
+#include <rte_common.h>
+
+static __rte_always_inline uint64_t
+rte_pmu_pmc_read(int index)
+{
+ uint64_t val;
+
+ if (index == 31) {
+ /* CPU Cycles (0x11) must be read via pmccntr_el0 */
+ asm volatile("mrs %0, pmccntr_el0" : "=r" (val));
+ } else {
+ asm volatile(
+ "msr pmselr_el0, %x0\n"
+ "mrs %0, pmxevcntr_el0\n"
+ : "=r" (val)
+ : "rZ" (index)
+ );
+ }
+
+ return val;
+}
+#define rte_pmu_pmc_read rte_pmu_pmc_read
+
+#endif /* _RTE_PMU_PMC_ARM64_H_ */
--
2.34.1