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[204.195.96.226]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20e7f0e0104sm32578935ad.234.2024.10.21.18.52.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Oct 2024 18:52:26 -0700 (PDT) Date: Mon, 21 Oct 2024 18:49:34 -0700 From: Stephen Hemminger To: Cc: , "Shijith Thotton" , Subject: Re: [PATCH 07/20] event/cnxk: add CN20K SSO dequeue fast path Message-ID: <20241021184934.402be7ce@hermes.local> In-Reply-To: <20241003132237.20193-7-pbhagavatula@marvell.com> References: <20241003132237.20193-1-pbhagavatula@marvell.com> <20241003132237.20193-7-pbhagavatula@marvell.com> MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org On Thu, 3 Oct 2024 18:52:24 +0530 wrote: > +static __rte_always_inline uint16_t > +cn20k_sso_hws_get_work(struct cn20k_sso_hws *ws, struct rte_event *ev, const uint32_t flags) > +{ > + union { > + __uint128_t get_work; > + uint64_t u64[2]; > + } gw; > + > + gw.get_work = ws->gw_wdata; > +#if defined(RTE_ARCH_ARM64) > +#if defined(__clang__) > + register uint64_t x0 __asm("x0") = (uint64_t)gw.u64[0]; > + register uint64_t x1 __asm("x1") = (uint64_t)gw.u64[1]; > +#if defined(RTE_ARM_USE_WFE) > + plt_write64(gw.u64[0], ws->base + SSOW_LF_GWS_OP_GET_WORK0); > + asm volatile(PLT_CPU_FEATURE_PREAMBLE > + " ldp %[x0], %[x1], [%[tag_loc]] \n" > + " tbz %[x0], %[pend_gw], done%= \n" > + " sevl \n" > + "rty%=: wfe \n" > + " ldp %[x0], %[x1], [%[tag_loc]] \n" > + " tbnz %[x0], %[pend_gw], rty%= \n" > + "done%=: \n" > + " dmb ld \n" > + : [x0] "+r" (x0), [x1] "+r" (x1) > + : [tag_loc] "r"(ws->base + SSOW_LF_GWS_WQE0), > + [pend_gw] "i"(SSOW_LF_GWS_TAG_PEND_GET_WORK_BIT) > + : "memory"); > +#else > + asm volatile(".arch armv8-a+lse\n" > + "caspal %[x0], %[x1], %[x0], %[x1], [%[dst]]\n" > + : [x0] "+r" (x0), [x1] "+r" (x1) > + : [dst] "r"(ws->base + SSOW_LF_GWS_OP_GET_WORK0) > + : "memory"); > +#endif > + gw.u64[0] = x0; > + gw.u64[1] = x1; > +#else > +#if defined(RTE_ARM_USE_WFE) > + plt_write64(gw.u64[0], ws->base + SSOW_LF_GWS_OP_GET_WORK0); > + asm volatile(PLT_CPU_FEATURE_PREAMBLE > + " ldp %[wdata], %H[wdata], [%[tag_loc]] \n" > + " tbz %[wdata], %[pend_gw], done%= \n" > + " sevl \n" > + "rty%=: wfe \n" > + " ldp %[wdata], %H[wdata], [%[tag_loc]] \n" > + " tbnz %[wdata], %[pend_gw], rty%= \n" > + "done%=: \n" > + " dmb ld \n" > + : [wdata] "=&r"(gw.get_work) > + : [tag_loc] "r"(ws->base + SSOW_LF_GWS_WQE0), > + [pend_gw] "i"(SSOW_LF_GWS_TAG_PEND_GET_WORK_BIT) > + : "memory"); > +#else > + asm volatile(PLT_CPU_FEATURE_PREAMBLE > + "caspal %[wdata], %H[wdata], %[wdata], %H[wdata], [%[gw_loc]]\n" > + : [wdata] "+r"(gw.get_work) > + : [gw_loc] "r"(ws->base + SSOW_LF_GWS_OP_GET_WORK0) > + : "memory"); > +#endif > +#endif This generates lots of warnings like: WARNING:QUOTED_WHITESPACE_BEFORE_NEWLINE: unnecessary whitespace before a quoted newline #131: FILE: drivers/event/cnxk/cn20k_worker.h:39: + " ldp %[x0], %[x1], [%[tag_loc]] \n" But the bigger problem is burying assembly in a driver is a bad idea. The use of ARM primitives should be done in EAL, not down in the PMD.