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From: Dariusz Sosnowski <dsosnowski@nvidia.com>
To: Viacheslav Ovsiienko <viacheslavo@nvidia.com>, Bing Zhao
<bingz@nvidia.com>, Ori Kam <orika@nvidia.com>, Suanming Mou
<suanmingm@nvidia.com>, Matan Azrad <matan@nvidia.com>
CC: <dev@dpdk.org>
Subject: [PATCH v2 01/10] net/mlx5: track unicast DMAC control flow rules
Date: Tue, 22 Oct 2024 14:06:09 +0200
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All control flow rules in NIC Rx domain, created by HWS flow engine,
were assigned MLX5_HW_CTRL_FLOW_TYPE_DEFAULT_RX_RSS type.
To allow checking if a flow rule with given DMAC or VLAN were created,
the list of associated types is extended with:
- type for unicast DMAC flow rules,
- type for unicast DMAC with VLAN flow rules.
These will be used in the follow up commit,
which adds functions for checking if a given control flow rule exists.
Signed-off-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
---
drivers/net/mlx5/mlx5.h | 15 +++++++++++++++
drivers/net/mlx5/mlx5_flow_hw.c | 11 +++++++----
2 files changed, 22 insertions(+), 4 deletions(-)
diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h
index 18b4c15a26..80829be5b4 100644
--- a/drivers/net/mlx5/mlx5.h
+++ b/drivers/net/mlx5/mlx5.h
@@ -1796,6 +1796,8 @@ enum mlx5_hw_ctrl_flow_type {
MLX5_HW_CTRL_FLOW_TYPE_TX_REPR_MATCH,
MLX5_HW_CTRL_FLOW_TYPE_LACP_RX,
MLX5_HW_CTRL_FLOW_TYPE_DEFAULT_RX_RSS,
+ MLX5_HW_CTRL_FLOW_TYPE_DEFAULT_RX_RSS_UNICAST_DMAC,
+ MLX5_HW_CTRL_FLOW_TYPE_DEFAULT_RX_RSS_UNICAST_DMAC_VLAN,
};
/** Additional info about control flow rule. */
@@ -1813,6 +1815,19 @@ struct mlx5_hw_ctrl_flow_info {
* then fields contains matching SQ number.
*/
uint32_t tx_repr_sq;
+ /** Contains data relevant for unicast control flow rules. */
+ struct {
+ /**
+ * If control flow is a unicast DMAC (or with VLAN) flow rule,
+ * then this field contains DMAC.
+ */
+ struct rte_ether_addr dmac;
+ /**
+ * If control flow is a unicast DMAC with VLAN flow rule,
+ * then this field contains VLAN ID.
+ */
+ uint16_t vlan;
+ } uc;
};
};
diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c
index 0084f81980..fbc56497ae 100644
--- a/drivers/net/mlx5/mlx5_flow_hw.c
+++ b/drivers/net/mlx5/mlx5_flow_hw.c
@@ -15906,7 +15906,7 @@ __flow_hw_ctrl_flows_unicast(struct rte_eth_dev *dev,
{ .type = RTE_FLOW_ACTION_TYPE_END },
};
struct mlx5_hw_ctrl_flow_info flow_info = {
- .type = MLX5_HW_CTRL_FLOW_TYPE_DEFAULT_RX_RSS,
+ .type = MLX5_HW_CTRL_FLOW_TYPE_DEFAULT_RX_RSS_UNICAST_DMAC,
};
const struct rte_ether_addr cmp = {
.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
@@ -15930,7 +15930,8 @@ __flow_hw_ctrl_flows_unicast(struct rte_eth_dev *dev,
if (!memcmp(mac, &cmp, sizeof(*mac)))
continue;
- memcpy(ð_spec.hdr.dst_addr.addr_bytes, mac->addr_bytes, RTE_ETHER_ADDR_LEN);
+ eth_spec.hdr.dst_addr = *mac;
+ flow_info.uc.dmac = *mac;
if (flow_hw_create_ctrl_flow(dev, dev,
tbl, items, 0, actions, 0, &flow_info, false))
return -rte_errno;
@@ -15952,7 +15953,7 @@ __flow_hw_ctrl_flows_unicast_vlan(struct rte_eth_dev *dev,
{ .type = RTE_FLOW_ACTION_TYPE_END },
};
struct mlx5_hw_ctrl_flow_info flow_info = {
- .type = MLX5_HW_CTRL_FLOW_TYPE_DEFAULT_RX_RSS,
+ .type = MLX5_HW_CTRL_FLOW_TYPE_DEFAULT_RX_RSS_UNICAST_DMAC_VLAN,
};
const struct rte_ether_addr cmp = {
.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
@@ -15977,13 +15978,15 @@ __flow_hw_ctrl_flows_unicast_vlan(struct rte_eth_dev *dev,
if (!memcmp(mac, &cmp, sizeof(*mac)))
continue;
- memcpy(ð_spec.hdr.dst_addr.addr_bytes, mac->addr_bytes, RTE_ETHER_ADDR_LEN);
+ eth_spec.hdr.dst_addr = *mac;
+ flow_info.uc.dmac = *mac;
for (j = 0; j < priv->vlan_filter_n; ++j) {
uint16_t vlan = priv->vlan_filter[j];
struct rte_flow_item_vlan vlan_spec = {
.hdr.vlan_tci = rte_cpu_to_be_16(vlan),
};
+ flow_info.uc.vlan = vlan;
items[1].spec = &vlan_spec;
if (flow_hw_create_ctrl_flow(dev, dev, tbl, items, 0, actions, 0,
&flow_info, false))
--
2.39.5