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From: Serhii Iliushyk <sil-plv@napatech.com>
To: dev@dpdk.org
Cc: mko-plv@napatech.com, sil-plv@napatech.com, ckm@napatech.com,
andrew.rybchenko@oktetlabs.ru, ferruh.yigit@amd.com,
Oleksandr Kolomeiets <okl-plv@napatech.com>
Subject: [PATCH v3 51/73] net/ntnic: add Tx RPL module
Date: Wed, 23 Oct 2024 18:59:59 +0200
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From: Oleksandr Kolomeiets <okl-plv@napatech.com>
The TX Replacer module can replace a range of bytes in a packet.
The replacing data is stored in a table in the module
and will often contain tunnel data.
Signed-off-by: Oleksandr Kolomeiets <okl-plv@napatech.com>
---
.../supported/nthw_fpga_9563_055_049_0000.c | 41 ++++++++++++++++++-
.../ntnic/nthw/supported/nthw_fpga_mod_defs.h | 3 +-
2 files changed, 42 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_049_0000.c b/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_049_0000.c
index c8841b1dc2..a3d9f94fc6 100644
--- a/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_049_0000.c
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_049_0000.c
@@ -2355,6 +2355,44 @@ static nthw_fpga_register_init_s rmc_registers[] = {
{ RMC_STATUS, 1, 17, NTHW_FPGA_REG_TYPE_RO, 0, 2, rmc_status_fields },
};
+static nthw_fpga_field_init_s rpl_ext_ctrl_fields[] = {
+ { RPL_EXT_CTRL_ADR, 10, 0, 0x0000 },
+ { RPL_EXT_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s rpl_ext_data_fields[] = {
+ { RPL_EXT_DATA_RPL_PTR, 12, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s rpl_rcp_ctrl_fields[] = {
+ { RPL_RCP_CTRL_ADR, 4, 0, 0x0000 },
+ { RPL_RCP_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s rpl_rcp_data_fields[] = {
+ { RPL_RCP_DATA_DYN, 5, 0, 0x0000 }, { RPL_RCP_DATA_ETH_TYPE_WR, 1, 36, 0x0000 },
+ { RPL_RCP_DATA_EXT_PRIO, 1, 35, 0x0000 }, { RPL_RCP_DATA_LEN, 8, 15, 0x0000 },
+ { RPL_RCP_DATA_OFS, 10, 5, 0x0000 }, { RPL_RCP_DATA_RPL_PTR, 12, 23, 0x0000 },
+};
+
+static nthw_fpga_field_init_s rpl_rpl_ctrl_fields[] = {
+ { RPL_RPL_CTRL_ADR, 12, 0, 0x0000 },
+ { RPL_RPL_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s rpl_rpl_data_fields[] = {
+ { RPL_RPL_DATA_VALUE, 128, 0, 0x0000 },
+};
+
+static nthw_fpga_register_init_s rpl_registers[] = {
+ { RPL_EXT_CTRL, 2, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, rpl_ext_ctrl_fields },
+ { RPL_EXT_DATA, 3, 12, NTHW_FPGA_REG_TYPE_WO, 0, 1, rpl_ext_data_fields },
+ { RPL_RCP_CTRL, 0, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, rpl_rcp_ctrl_fields },
+ { RPL_RCP_DATA, 1, 37, NTHW_FPGA_REG_TYPE_WO, 0, 6, rpl_rcp_data_fields },
+ { RPL_RPL_CTRL, 4, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, rpl_rpl_ctrl_fields },
+ { RPL_RPL_DATA, 5, 128, NTHW_FPGA_REG_TYPE_WO, 0, 1, rpl_rpl_data_fields },
+};
+
static nthw_fpga_field_init_s rpp_lr_ifr_rcp_ctrl_fields[] = {
{ RPP_LR_IFR_RCP_CTRL_ADR, 4, 0, 0x0000 },
{ RPP_LR_IFR_RCP_CTRL_CNT, 16, 16, 0x0000 },
@@ -2498,6 +2536,7 @@ static nthw_fpga_module_init_s fpga_modules[] = {
{ MOD_SLC_LR, 0, MOD_SLC, 0, 2, NTHW_FPGA_BUS_TYPE_RAB1, 2048, 2, slc_registers },
{ MOD_TX_CPY, 0, MOD_CPY, 0, 4, NTHW_FPGA_BUS_TYPE_RAB1, 9216, 26, cpy_registers },
{ MOD_TX_INS, 0, MOD_INS, 0, 2, NTHW_FPGA_BUS_TYPE_RAB1, 8704, 2, ins_registers },
+ { MOD_TX_RPL, 0, MOD_RPL, 0, 4, NTHW_FPGA_BUS_TYPE_RAB1, 8960, 6, rpl_registers },
};
static nthw_fpga_prod_param_s product_parameters[] = {
@@ -2656,5 +2695,5 @@ static nthw_fpga_prod_param_s product_parameters[] = {
};
nthw_fpga_prod_init_s nthw_fpga_9563_055_049_0000 = {
- 200, 9563, 55, 49, 0, 0, 1726740521, 152, product_parameters, 34, fpga_modules,
+ 200, 9563, 55, 49, 0, 0, 1726740521, 152, product_parameters, 35, fpga_modules,
};
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h
index 8c0c727e16..2b059d98ff 100644
--- a/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h
@@ -40,6 +40,7 @@
#define MOD_QSL (0x448ed859UL)
#define MOD_RAC (0xae830b42UL)
#define MOD_RMC (0x236444eUL)
+#define MOD_RPL (0x6de535c3UL)
#define MOD_RPP_LR (0xba7f945cUL)
#define MOD_RST9563 (0x385d6d1dUL)
#define MOD_SDC (0xd2369530UL)
@@ -48,7 +49,7 @@
#define MOD_TX_CPY (0x60acf217UL)
#define MOD_TX_INS (0x59afa100UL)
#define MOD_TX_RPL (0x1095dfbbUL)
-#define MOD_IDX_COUNT (35)
+#define MOD_IDX_COUNT (36)
/* aliases - only aliases go below this point */
#endif /* _NTHW_FPGA_MOD_DEFS_H_ */
--
2.45.0