From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2264945BD6; Fri, 25 Oct 2024 14:32:40 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 62150402EF; Fri, 25 Oct 2024 14:31:48 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 2EDA3402F1 for ; Fri, 25 Oct 2024 14:30:50 +0200 (CEST) Received: from pps.filterd (m0431383.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 49PBrhhr012668; Fri, 25 Oct 2024 05:30:49 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=/ 9lhvmT6sVKE9JN9DB3tvZyqiNUpCTrciAmeh+YHhT8=; b=ZzRHkAVF3nvk4Ahl3 VttR7SEK5cLyZYKvhtcYWQUiExZ3V9TjMm5GYwHKVDhRtAABlDoN4Z4SRreRfZqP 0u/PrQoipYsXixEe5uZfq2kdAsCT9aHhA/S2yEWeDvqaEQx7p6lHGbadyrviF5Ks yfGRP5WpvmWn3BKi0HCFYx81UaD9ALtKzvQ2uhlh+e4eKkPdD3SVS52Nmu4qN2Zg /rymEd7TSAGVW+SJgsG+iL285NMgdzZkLYH20Qofw5nb9WV0IMcHINru8cGN/2IB kzLkKda4LLvNUg1FOi78NnUvpAGGtz7/Vyf7ejF3JWKD5lENcs0CoOZKdqJY9+UW AfzBA== Received: from dc5-exch05.marvell.com ([199.233.59.128]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 42gauyg2b3-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 25 Oct 2024 05:30:49 -0700 (PDT) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 25 Oct 2024 05:30:48 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Fri, 25 Oct 2024 05:30:47 -0700 Received: from MININT-80QBFE8.corp.innovium.com (MININT-80QBFE8.marvell.com [10.28.164.106]) by maili.marvell.com (Postfix) with ESMTP id 27BFE3F7090; Fri, 25 Oct 2024 05:30:43 -0700 (PDT) From: To: , , , Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Harman Kalra , Pavan Nikhilesh , "Shijith Thotton" CC: Subject: [PATCH v6 21/22] common/cnxk: update timer base code Date: Fri, 25 Oct 2024 17:59:43 +0530 Message-ID: <20241025122944.27745-21-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241025122944.27745-1-pbhagavatula@marvell.com> References: <20241025081353.25759-1-pbhagavatula@marvell.com> <20241025122944.27745-1-pbhagavatula@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: DVAG0mMo7Igerd_CTf_gKZV9VH8nbslI X-Proofpoint-ORIG-GUID: DVAG0mMo7Igerd_CTf_gKZV9VH8nbslI X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.687,Hydra:6.0.235,FMLib:17.0.607.475 definitions=2020-10-13_15,2020-10-13_02,2020-04-07_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Pavan Nikhilesh Update event timer base code to support configuring HW accelerated timer arm and cancel. Signed-off-by: Pavan Nikhilesh --- drivers/common/cnxk/hw/tim.h | 5 ++ drivers/common/cnxk/roc_mbox.h | 38 ++++++++++++- drivers/common/cnxk/roc_tim.c | 84 ++++++++++++++++++++++++++--- drivers/common/cnxk/roc_tim.h | 20 +++++-- drivers/common/cnxk/version.map | 1 + drivers/event/cnxk/cnxk_tim_evdev.h | 5 -- 6 files changed, 135 insertions(+), 18 deletions(-) diff --git a/drivers/common/cnxk/hw/tim.h b/drivers/common/cnxk/hw/tim.h index 82b094e3dc..75700a11b8 100644 --- a/drivers/common/cnxk/hw/tim.h +++ b/drivers/common/cnxk/hw/tim.h @@ -47,10 +47,15 @@ #define TIM_LF_RAS_INT_ENA_W1S (0x310) #define TIM_LF_RAS_INT_ENA_W1C (0x318) #define TIM_LF_RING_REL (0x400) +#define TIM_LF_SCHED_TIMER0 (0x480) +#define TIM_LF_RING_FIRST_EXPIRY (0x558) #define TIM_MAX_INTERVAL_TICKS ((1ULL << 32) - 1) +#define TIM_MAX_INTERVAL_EXT_TICKS ((1ULL << 34) - 1) #define TIM_MAX_BUCKET_SIZE ((1ULL << 20) - 2) #define TIM_MIN_BUCKET_SIZE 1 #define TIM_BUCKET_WRAP_SIZE 3 +#define TIM_BUCKET_MIN_GAP 1 +#define TIM_NPA_TMO 0xFFFF #endif /* __TIM_HW_H__ */ diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h index db6e8f07b3..8c0e274684 100644 --- a/drivers/common/cnxk/roc_mbox.h +++ b/drivers/common/cnxk/roc_mbox.h @@ -164,6 +164,9 @@ struct mbox_msghdr { tim_intvl_rsp) \ M(TIM_CAPTURE_COUNTERS, 0x806, tim_capture_counters, msg_req, \ tim_capture_rsp) \ + M(TIM_CONFIG_HWWQE, 0x807, tim_config_hwwqe, tim_cfg_hwwqe_req, \ + msg_rsp) \ + M(TIM_GET_HW_INFO, 0x808, tim_get_hw_info, msg_req, tim_hw_info) \ /* CPT mbox IDs (range 0xA00 - 0xBFF) */ \ M(CPT_LF_ALLOC, 0xA00, cpt_lf_alloc, cpt_lf_alloc_req_msg, msg_rsp) \ M(CPT_LF_FREE, 0xA01, cpt_lf_free, msg_req, msg_rsp) \ @@ -2803,6 +2806,7 @@ enum tim_af_status { TIM_AF_INVALID_ENABLE_DONTFREE = -815, TIM_AF_ENA_DONTFRE_NSET_PERIODIC = -816, TIM_AF_RING_ALREADY_DISABLED = -817, + TIM_AF_LF_START_SYNC_FAIL = -818, }; enum tim_clk_srcs { @@ -2895,13 +2899,43 @@ struct tim_config_req { uint8_t __io enabledontfreebuffer; uint32_t __io bucketsize; uint32_t __io chunksize; - uint32_t __io interval; + uint32_t __io interval_lo; uint8_t __io gpioedge; - uint8_t __io rsvd[7]; + uint8_t __io rsvd[3]; + uint32_t __io interval_hi; uint64_t __io intervalns; uint64_t __io clockfreq; }; +struct tim_cfg_hwwqe_req { + struct mbox_msghdr hdr; + uint16_t __io ring; + uint8_t __io grp_ena; + uint8_t __io hwwqe_ena; + uint8_t __io ins_min_gap; + uint8_t __io flw_ctrl_ena; + uint8_t __io wqe_rd_clr_ena; + uint16_t __io grp_tmo_cntr; + uint16_t __io npa_tmo_cntr; + uint16_t __io result_offset; + uint16_t __io event_count_offset; + uint64_t __io rsvd[2]; +}; + +struct tim_feat_info { + uint16_t __io rings; + uint8_t __io engines; + uint8_t __io hwwqe : 1; + uint8_t __io intvl_ext : 1; + uint8_t __io rsvd8[4]; + uint64_t __io rsvd[2]; +}; + +struct tim_hw_info { + struct mbox_msghdr hdr; + struct tim_feat_info feat; +}; + struct tim_lf_alloc_rsp { struct mbox_msghdr hdr; uint64_t __io tenns_clk; diff --git a/drivers/common/cnxk/roc_tim.c b/drivers/common/cnxk/roc_tim.c index 83228fb2b6..e326ea0122 100644 --- a/drivers/common/cnxk/roc_tim.c +++ b/drivers/common/cnxk/roc_tim.c @@ -5,6 +5,8 @@ #include "roc_api.h" #include "roc_priv.h" +#define LF_ENABLE_RETRY_CNT 8 + static int tim_fill_msix(struct roc_tim *roc_tim, uint16_t nb_ring) { @@ -86,8 +88,11 @@ tim_err_desc(int rc) case TIM_AF_RING_ALREADY_DISABLED: plt_err("Ring already stopped"); break; + case TIM_AF_LF_START_SYNC_FAIL: + plt_err("Ring start sync failed."); + break; default: - plt_err("Unknown Error."); + plt_err("Unknown Error: %d", rc); } } @@ -123,10 +128,12 @@ roc_tim_lf_enable(struct roc_tim *roc_tim, uint8_t ring_id, uint64_t *start_tsc, struct sso *sso = roc_sso_to_sso_priv(roc_tim->roc_sso); struct dev *dev = &sso->dev; struct mbox *mbox = mbox_get(dev->mbox); + uint8_t retry_cnt = LF_ENABLE_RETRY_CNT; struct tim_enable_rsp *rsp; struct tim_ring_req *req; int rc = -ENOSPC; +retry: req = mbox_alloc_msg_tim_enable_ring(mbox); if (req == NULL) goto fail; @@ -134,6 +141,9 @@ roc_tim_lf_enable(struct roc_tim *roc_tim, uint8_t ring_id, uint64_t *start_tsc, rc = mbox_process_msg(dev->mbox, (void **)&rsp); if (rc) { + if (rc == TIM_AF_LF_START_SYNC_FAIL && retry_cnt--) + goto retry; + tim_err_desc(rc); rc = -EIO; goto fail; @@ -183,10 +193,9 @@ roc_tim_lf_base_get(struct roc_tim *roc_tim, uint8_t ring_id) } int -roc_tim_lf_config(struct roc_tim *roc_tim, uint8_t ring_id, - enum roc_tim_clk_src clk_src, uint8_t ena_periodic, - uint8_t ena_dfb, uint32_t bucket_sz, uint32_t chunk_sz, - uint32_t interval, uint64_t intervalns, uint64_t clockfreq) +roc_tim_lf_config(struct roc_tim *roc_tim, uint8_t ring_id, enum roc_tim_clk_src clk_src, + uint8_t ena_periodic, uint8_t ena_dfb, uint32_t bucket_sz, uint32_t chunk_sz, + uint64_t interval, uint64_t intervalns, uint64_t clockfreq) { struct sso *sso = roc_sso_to_sso_priv(roc_tim->roc_sso); struct dev *dev = &sso->dev; @@ -204,7 +213,8 @@ roc_tim_lf_config(struct roc_tim *roc_tim, uint8_t ring_id, req->clocksource = clk_src; req->enableperiodic = ena_periodic; req->enabledontfreebuffer = ena_dfb; - req->interval = interval; + req->interval_lo = interval; + req->interval_hi = interval >> 32; req->intervalns = intervalns; req->clockfreq = clockfreq; req->gpioedge = TIM_GPIO_LTOH_TRANS; @@ -220,6 +230,41 @@ roc_tim_lf_config(struct roc_tim *roc_tim, uint8_t ring_id, return rc; } +int +roc_tim_lf_config_hwwqe(struct roc_tim *roc_tim, uint8_t ring_id, struct roc_tim_hwwqe_cfg *cfg) +{ + struct sso *sso = roc_sso_to_sso_priv(roc_tim->roc_sso); + struct dev *dev = &sso->dev; + struct mbox *mbox = mbox_get(dev->mbox); + struct tim_cfg_hwwqe_req *req; + int rc = -ENOSPC; + + req = mbox_alloc_msg_tim_config_hwwqe(mbox); + if (req == NULL) + goto fail; + req->ring = ring_id; + req->hwwqe_ena = cfg->hwwqe_ena; + req->grp_ena = cfg->grp_ena; + req->grp_tmo_cntr = cfg->grp_tmo_cyc; + req->flw_ctrl_ena = cfg->flw_ctrl_ena; + req->result_offset = cfg->result_offset; + req->event_count_offset = cfg->event_count_offset; + + req->wqe_rd_clr_ena = 1; + req->npa_tmo_cntr = TIM_NPA_TMO; + req->ins_min_gap = TIM_BUCKET_MIN_GAP; + + rc = mbox_process(mbox); + if (rc) { + tim_err_desc(rc); + rc = -EIO; + } + +fail: + mbox_put(mbox); + return rc; +} + int roc_tim_lf_interval(struct roc_tim *roc_tim, enum roc_tim_clk_src clk_src, uint64_t clockfreq, uint64_t *intervalns, @@ -353,6 +398,31 @@ tim_free_lf_count_get(struct dev *dev, uint16_t *nb_lfs) return 0; } +static int +tim_hw_info_get(struct roc_tim *roc_tim) +{ + struct dev *dev = &roc_sso_to_sso_priv(roc_tim->roc_sso)->dev; + struct mbox *mbox = mbox_get(dev->mbox); + struct tim_hw_info *rsp; + int rc; + + mbox_alloc_msg_tim_get_hw_info(mbox); + rc = mbox_process_msg(mbox, (void **)&rsp); + if (rc && rc != MBOX_MSG_INVALID) { + plt_err("Failed to get SSO HW info"); + rc = -EIO; + goto exit; + } + + if (rc != MBOX_MSG_INVALID) + mbox_memcpy(&roc_tim->feat, &rsp->feat, sizeof(roc_tim->feat)); + + rc = 0; +exit: + mbox_put(mbox); + return rc; +} + int roc_tim_init(struct roc_tim *roc_tim) { @@ -372,6 +442,8 @@ roc_tim_init(struct roc_tim *roc_tim) PLT_STATIC_ASSERT(sizeof(struct tim) <= TIM_MEM_SZ); nb_lfs = roc_tim->nb_lfs; + rc = tim_hw_info_get(roc_tim); + rc = tim_free_lf_count_get(dev, &nb_free_lfs); if (rc) { plt_tim_dbg("Failed to get TIM resource count"); diff --git a/drivers/common/cnxk/roc_tim.h b/drivers/common/cnxk/roc_tim.h index f9a9ad1887..2eb6e6962b 100644 --- a/drivers/common/cnxk/roc_tim.h +++ b/drivers/common/cnxk/roc_tim.h @@ -19,10 +19,20 @@ enum roc_tim_clk_src { ROC_TIM_CLK_SRC_INVALID, }; +struct roc_tim_hwwqe_cfg { + uint8_t grp_ena; + uint8_t hwwqe_ena; + uint8_t flw_ctrl_ena; + uint16_t grp_tmo_cyc; + uint16_t result_offset; + uint16_t event_count_offset; +}; + struct roc_tim { struct roc_sso *roc_sso; /* Public data. */ uint16_t nb_lfs; + struct tim_feat_info feat; /* Private data. */ #define TIM_MEM_SZ (1 * 1024) uint8_t reserved[TIM_MEM_SZ] __plt_cache_aligned; @@ -36,11 +46,11 @@ int __roc_api roc_tim_lf_enable(struct roc_tim *roc_tim, uint8_t ring_id, uint64_t *start_tsc, uint32_t *cur_bkt); int __roc_api roc_tim_lf_disable(struct roc_tim *roc_tim, uint8_t ring_id); int __roc_api roc_tim_lf_config(struct roc_tim *roc_tim, uint8_t ring_id, - enum roc_tim_clk_src clk_src, - uint8_t ena_periodic, uint8_t ena_dfb, - uint32_t bucket_sz, uint32_t chunk_sz, - uint32_t interval, uint64_t intervalns, - uint64_t clockfreq); + enum roc_tim_clk_src clk_src, uint8_t ena_periodic, uint8_t ena_dfb, + uint32_t bucket_sz, uint32_t chunk_sz, uint64_t interval, + uint64_t intervalns, uint64_t clockfreq); +int __roc_api roc_tim_lf_config_hwwqe(struct roc_tim *roc_tim, uint8_t ring_id, + struct roc_tim_hwwqe_cfg *cfg); int __roc_api roc_tim_lf_interval(struct roc_tim *roc_tim, enum roc_tim_clk_src clk_src, uint64_t clockfreq, uint64_t *intervalns, diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 14ee6031e2..e7381ae8b2 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -528,6 +528,7 @@ INTERNAL { roc_tim_lf_alloc; roc_tim_lf_base_get; roc_tim_lf_config; + roc_tim_lf_config_hwwqe; roc_tim_lf_disable; roc_tim_lf_enable; roc_tim_lf_free; diff --git a/drivers/event/cnxk/cnxk_tim_evdev.h b/drivers/event/cnxk/cnxk_tim_evdev.h index f4c61dfb44..c5b3d67eb8 100644 --- a/drivers/event/cnxk/cnxk_tim_evdev.h +++ b/drivers/event/cnxk/cnxk_tim_evdev.h @@ -16,11 +16,6 @@ #include #include -#include "hw/tim.h" - -#include "roc_model.h" -#include "roc_tim.h" - #define NSECPERSEC 1E9 #define USECPERSEC 1E6 #define TICK2NSEC(__tck, __freq) (((__tck)*NSECPERSEC) / (__freq)) -- 2.25.1