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From: Soumyadeep Hore <soumyadeep.hore@intel.com>
To: dev@dpdk.org, bruce.richardson@intel.com
Cc: aman.deep.singh@intel.com, Paul Greenwalt <paul.greenwalt@intel.com>
Subject: [PATCH v1 2/3] net/intel: add E830 ETF offload timestamp resolution
Date: Fri,  7 Feb 2025 12:42:59 +0000	[thread overview]
Message-ID: <20250207124300.1022523-3-soumyadeep.hore@intel.com> (raw)
In-Reply-To: <20250207124300.1022523-1-soumyadeep.hore@intel.com>

From: Paul Greenwalt <paul.greenwalt@intel.com>

Update E830 ETF offload time stamp resolution to 128ns.

Signed-off-by: Soumyadeep Hore <soumyadeep.hore@intel.com>
Signed-off-by: Paul Greenwalt <paul.greenwalt@intel.com>
---
 drivers/net/intel/ice/base/ice_lan_tx_rx.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/intel/ice/base/ice_lan_tx_rx.h b/drivers/net/intel/ice/base/ice_lan_tx_rx.h
index 15aabf321d..940c6843d9 100644
--- a/drivers/net/intel/ice/base/ice_lan_tx_rx.h
+++ b/drivers/net/intel/ice/base/ice_lan_tx_rx.h
@@ -1306,6 +1306,7 @@ struct ice_txtime_ctx {
 #define ICE_TXTIME_CTX_DRBELL_MODE_32	1
 	u8 ts_res;
 #define ICE_TXTIME_CTX_FETCH_PROF_ID_0 0
+#define ICE_TXTIME_CTX_RESOLUTION_128NS 7
 	u8 ts_round_type;
 	u8 ts_pacing_slot;
 	u8 merging_ena;
-- 
2.43.0


  parent reply	other threads:[~2025-02-07 20:49 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-07 12:42 [PATCH v1 0/3] Implement TXPP Support in ICE PMD Soumyadeep Hore
2025-02-07 12:42 ` [PATCH v1 1/3] net/intel: add support for timestamp ring HW workaround Soumyadeep Hore
2025-02-07 12:42 ` Soumyadeep Hore [this message]
2025-02-07 12:43 ` [PATCH v1 3/3] net/intel: add Tx time queue Soumyadeep Hore
2025-02-07 21:36   ` Stephen Hemminger

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