From: Stephen Hemminger <stephen@networkplumber.org>
To: Soumyadeep Hore <soumyadeep.hore@intel.com>
Cc: dev@dpdk.org, bruce.richardson@intel.com, aman.deep.singh@intel.com
Subject: Re: [PATCH v1 3/3] net/intel: add Tx time queue
Date: Fri, 7 Feb 2025 13:36:48 -0800 [thread overview]
Message-ID: <20250207133648.4436473d@hermes.local> (raw)
In-Reply-To: <20250207124300.1022523-4-soumyadeep.hore@intel.com>
On Fri, 7 Feb 2025 12:43:00 +0000
Soumyadeep Hore <soumyadeep.hore@intel.com> wrote:
> diff --git a/drivers/net/intel/common/tx.h b/drivers/net/intel/common/tx.h
> index d9cf4474fc..f3777fa9e7 100644
> --- a/drivers/net/intel/common/tx.h
> +++ b/drivers/net/intel/common/tx.h
> @@ -35,6 +35,7 @@ struct ci_tx_queue {
> volatile struct i40e_tx_desc *i40e_tx_ring;
> volatile struct iavf_tx_desc *iavf_tx_ring;
> volatile struct ice_tx_desc *ice_tx_ring;
> + volatile struct ice_ts_desc *ice_tstamp_ring;
> volatile union ixgbe_adv_tx_desc *ixgbe_tx_ring;
> };
> volatile uint8_t *qtx_tail; /* register address of tail */
> @@ -76,6 +77,10 @@ struct ci_tx_queue {
Why so heavy use of volatile here? Volatile generates worst case code is there something
odd about the hardware or driver?
prev parent reply other threads:[~2025-02-07 21:36 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-07 12:42 [PATCH v1 0/3] Implement TXPP Support in ICE PMD Soumyadeep Hore
2025-02-07 12:42 ` [PATCH v1 1/3] net/intel: add support for timestamp ring HW workaround Soumyadeep Hore
2025-02-07 12:42 ` [PATCH v1 2/3] net/intel: add E830 ETF offload timestamp resolution Soumyadeep Hore
2025-02-07 12:43 ` [PATCH v1 3/3] net/intel: add Tx time queue Soumyadeep Hore
2025-02-07 21:36 ` Stephen Hemminger [this message]
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