[PATCH 1/8] net/mlx5/hws: introduce capability for unified mode

[Hamdan Igbaria <hamdani@nvidia.com>]

From: Erez Shitrit <erezsh@nvidia.com>

Till now the FDB processing domain is split into two mutually
exclusive sub domains FDB_RX and FDB_TX.
Packets originating from the Uplink(s) are processed in the FDB_RX
sub domain, while packets originating from all other Vports are
processed in the FDB_TX sub domain.

Now adding new sub domain: FDB_UNIFIED which can process packets
originated by any VPORT / WIRE.
This new domain will process actions only that allowed on both RX
and TX domains.
That way the user can define specifically the domain he wants the
packet to be processed, whenever it is RX/TX only he will use
FDB_RX/TX, or whenever it can by FDB_UNIFIED.

Signed-off-by: Erez Shitrit <erezsh@nvidia.com>
Signed-off-by: Hamdan Igbaria <hamdani@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
 drivers/common/mlx5/mlx5_prm.h    | 4 +++-
 drivers/net/mlx5/hws/mlx5dr_cmd.c | 4 ++++
 drivers/net/mlx5/hws/mlx5dr_cmd.h | 1 +
 3 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index d0cb0131f6..6e141b6520 100644
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -2478,7 +2478,9 @@ struct mlx5_ifc_wqe_based_flow_table_cap_bits {
 	u8 ste_format_gen_wqe[0x10];
 	u8 linear_match_definer_reg_c3[0x20];
 	u8 fdb_jump_to_tir_stc[0x1];
-	u8 reserved_at_1c1[0x1f];
+	u8 reserved_at_1c1[0x1];
+	u8 fdb_unified_en[0x1];
+	u8 reserved_at_1c3[0x1d];
 };
 
 union mlx5_ifc_hca_cap_union_bits {
diff --git a/drivers/net/mlx5/hws/mlx5dr_cmd.c b/drivers/net/mlx5/hws/mlx5dr_cmd.c
index a4f778a8a4..8a788709b5 100644
--- a/drivers/net/mlx5/hws/mlx5dr_cmd.c
+++ b/drivers/net/mlx5/hws/mlx5dr_cmd.c
@@ -1276,6 +1276,10 @@ int mlx5dr_cmd_query_caps(struct ibv_context *ctx,
 		caps->fdb_tir_stc = MLX5_GET(query_hca_cap_out, out,
 					     capability.wqe_based_flow_table_cap.
 					     fdb_jump_to_tir_stc);
+
+		caps->fdb_unified_en = MLX5_GET(query_hca_cap_out, out,
+						capability.wqe_based_flow_table_cap.
+						fdb_unified_en);
 	}
 
 	if (caps->eswitch_manager) {
diff --git a/drivers/net/mlx5/hws/mlx5dr_cmd.h b/drivers/net/mlx5/hws/mlx5dr_cmd.h
index 54840ec445..3c615b8925 100644
--- a/drivers/net/mlx5/hws/mlx5dr_cmd.h
+++ b/drivers/net/mlx5/hws/mlx5dr_cmd.h
@@ -250,6 +250,7 @@ struct mlx5dr_cmd_query_caps {
 	bool roce;
 	uint16_t roce_max_src_udp_port;
 	uint16_t roce_min_src_udp_port;
+	bool fdb_unified_en;
 };
 
 int mlx5dr_cmd_destroy_obj(struct mlx5dr_devx_obj *devx_obj);
-- 
2.21.0