From: Serhii Iliushyk <sil-plv@napatech.com>
To: dev@dpdk.org
Cc: mko-plv@napatech.com, sil-plv@napatech.com, ckm@napatech.com,
stephen@networkplumber.org,
Danylo Vodopianov <dvo-plv@napatech.com>
Subject: [PATCH v1 22/32] net/ntnic: add HIF clock test
Date: Thu, 20 Feb 2025 23:03:46 +0100 [thread overview]
Message-ID: <20250220220406.3925597-23-sil-plv@napatech.com> (raw)
In-Reply-To: <20250220220406.3925597-1-sil-plv@napatech.com>
From: Danylo Vodopianov <dvo-plv@napatech.com>
Add HIF clock test with write/read verification.
Signed-off-by: Danylo Vodopianov <dvo-plv@napatech.com>
---
.../net/ntnic/nthw/core/include/nthw_hif.h | 3 +
.../nt400dxx/reset/nthw_fpga_rst_nt400dxx.c | 20 +++++
drivers/net/ntnic/nthw/core/nthw_hif.c | 82 +++++++++++++++++++
3 files changed, 105 insertions(+)
diff --git a/drivers/net/ntnic/nthw/core/include/nthw_hif.h b/drivers/net/ntnic/nthw/core/include/nthw_hif.h
index c8f4669f83..deb9ed04e8 100644
--- a/drivers/net/ntnic/nthw/core/include/nthw_hif.h
+++ b/drivers/net/ntnic/nthw/core/include/nthw_hif.h
@@ -148,4 +148,7 @@ int nthw_hif_get_stat_rate(nthw_hif_t *p, uint64_t *p_pci_rx_rate, uint64_t *p_p
int nthw_hif_end_point_counters_sample(nthw_hif_t *p, struct nthw_hif_end_point_counters *epc);
+int nthw_hif_read_test_reg(nthw_hif_t *p, uint8_t test_reg, uint32_t *p_value);
+int nthw_hif_write_test_reg(nthw_hif_t *p, uint8_t test_reg, uint32_t value);
+
#endif /* __NTHW_HIF_H__ */
diff --git a/drivers/net/ntnic/nthw/core/nt400dxx/reset/nthw_fpga_rst_nt400dxx.c b/drivers/net/ntnic/nthw/core/nt400dxx/reset/nthw_fpga_rst_nt400dxx.c
index 1d93474cff..60e7714283 100644
--- a/drivers/net/ntnic/nthw/core/nt400dxx/reset/nthw_fpga_rst_nt400dxx.c
+++ b/drivers/net/ntnic/nthw/core/nt400dxx/reset/nthw_fpga_rst_nt400dxx.c
@@ -24,6 +24,26 @@ static int nthw_fpga_rst_nt400dxx_init(struct fpga_info_s *p_fpga_info)
if (res == 0)
NT_LOG(DBG, NTHW, "%s: Hif module found", p_fpga_info->mp_adapter_id_str);
+ /* (A) Test HIF clock is running by performing simple write/read test of HIF registers */
+ const uint32_t test_pattern[2] = { 0x11223344, 0x55667788 };
+
+ for (uint8_t i = 0; i < 2; ++i) {
+ uint32_t test_data = 0;
+ nthw_hif_write_test_reg(p_nthw_hif, i, test_pattern[i]);
+ nthw_hif_read_test_reg(p_nthw_hif, i, &test_data);
+
+ if (test_data != test_pattern[i]) {
+ NT_LOG(ERR,
+ NTHW,
+ "%s: %s: Test sys 250 clock failed",
+ p_fpga_info->mp_adapter_id_str,
+ __func__);
+ return -1;
+ }
+ }
+
+ nthw_hif_delete(p_nthw_hif);
+
/* Create PCM */
p_fpga_info->mp_nthw_agx.p_pcm = nthw_pcm_nt400dxx_new();
res = nthw_pcm_nt400dxx_init(p_fpga_info->mp_nthw_agx.p_pcm, p_fpga, 0);
diff --git a/drivers/net/ntnic/nthw/core/nthw_hif.c b/drivers/net/ntnic/nthw/core/nthw_hif.c
index 9f699e4f94..92a2348bbb 100644
--- a/drivers/net/ntnic/nthw/core/nthw_hif.c
+++ b/drivers/net/ntnic/nthw/core/nthw_hif.c
@@ -298,3 +298,85 @@ int nthw_hif_end_point_counters_sample(nthw_hif_t *p, struct nthw_hif_end_point_
return 0;
}
+
+int nthw_hif_read_test_reg(nthw_hif_t *p, uint8_t test_reg, uint32_t *p_value)
+{
+ uint32_t data;
+
+ switch (test_reg) {
+ case 0:
+ data = nthw_field_get_updated(p->mp_fld_pci_test0);
+ break;
+
+ case 1:
+ data = nthw_field_get_updated(p->mp_fld_pci_test1);
+ break;
+
+ case 2:
+ if (p->mp_fld_pci_test2)
+ data = nthw_field_get_updated(p->mp_fld_pci_test2);
+
+ else
+ return -1;
+
+ break;
+
+ case 3:
+ if (p->mp_fld_pci_test3)
+ data = nthw_field_get_updated(p->mp_fld_pci_test3);
+
+ else
+ return -1;
+
+ break;
+
+ default:
+ assert(false);
+ return -1;
+ }
+
+ if (p_value)
+ *p_value = data;
+
+ else
+ return -1;
+
+ return 0;
+}
+
+int nthw_hif_write_test_reg(nthw_hif_t *p, uint8_t test_reg, uint32_t value)
+{
+ switch (test_reg) {
+ case 0:
+ nthw_field_set_val_flush32(p->mp_fld_pci_test0, value);
+ break;
+
+ case 1:
+ nthw_field_set_val_flush32(p->mp_fld_pci_test1, value);
+ break;
+
+ case 2:
+ if (p->mp_fld_pci_test2)
+ nthw_field_set_val_flush32(p->mp_fld_pci_test2, value);
+
+ else
+ return -1;
+
+ break;
+
+ case 3:
+ if (p->mp_fld_pci_test3)
+ nthw_field_set_val_flush32(p->mp_fld_pci_test3, value);
+
+ else
+ return -1;
+
+ break;
+
+ default:
+ assert(false);
+ return -1;
+ }
+
+ return 0;
+}
--
2.45.0
next prev parent reply other threads:[~2025-02-20 22:06 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-20 22:03 [PATCH v1 00/32] add new adapter NT400D13 Serhii Iliushyk
2025-02-20 22:03 ` [PATCH v1 01/32] net/ntnic: add link agx 100g Serhii Iliushyk
2025-02-20 22:03 ` [PATCH v1 02/32] net/ntnic: add link state machine Serhii Iliushyk
2025-02-20 22:03 ` [PATCH v1 03/32] net/ntnic: add rpf and gfg init Serhii Iliushyk
2025-02-20 22:03 ` [PATCH v1 04/32] net/ntnic: add agx setup for port Serhii Iliushyk
2025-02-20 22:03 ` [PATCH v1 05/32] net/ntnic: add host loopback init Serhii Iliushyk
2025-02-20 22:03 ` [PATCH v1 06/32] net/ntnic: add line " Serhii Iliushyk
2025-02-20 22:03 ` [PATCH v1 07/32] net/ntnic: add 100 gbps port init Serhii Iliushyk
2025-02-20 22:03 ` [PATCH v1 08/32] net/ntnic: add port post init Serhii Iliushyk
2025-02-20 22:03 ` [PATCH v1 09/32] net/ntnic: add nim low power API Serhii Iliushyk
2025-02-20 22:03 ` [PATCH v1 10/32] net/ntnic: add link handling API Serhii Iliushyk
2025-02-20 22:03 ` [PATCH v1 11/32] net/ntnic: add port init to the state machine Serhii Iliushyk
2025-02-20 22:03 ` [PATCH v1 12/32] net/ntnic: add port disable API Serhii Iliushyk
2025-02-20 22:03 ` [PATCH v1 13/32] net/ntnic: add minimal initialization new NIC NT400D13 Serhii Iliushyk
2025-02-20 22:03 ` [PATCH v1 14/32] net/ntnic: add minimal reset FPGA Serhii Iliushyk
2025-02-20 22:03 ` [PATCH v1 15/32] net/ntnic: add FPGA modules and registers Serhii Iliushyk
2025-02-20 22:03 ` [PATCH v1 16/32] net/ntnic: add setup for fpga reset Serhii Iliushyk
2025-02-20 22:03 ` [PATCH v1 17/32] net/ntnic: add default reset setting for NT400D13 Serhii Iliushyk
2025-02-20 22:03 ` [PATCH v1 18/32] net/ntnic: add DDR calibration to reset stage Serhii Iliushyk
2025-02-20 22:03 ` [PATCH v1 19/32] net/ntnic: add PHY ftile reset Serhii Iliushyk
2025-02-20 22:03 ` [PATCH v1 20/32] net/ntnic: add clock init Serhii Iliushyk
2025-02-20 22:03 ` [PATCH v1 21/32] net/ntnic: add nt400d13 pcm init Serhii Iliushyk
2025-02-20 22:03 ` Serhii Iliushyk [this message]
2025-02-20 22:03 ` [PATCH v1 23/32] net/ntnic: add nt400d13 PRM module init Serhii Iliushyk
2025-02-20 22:03 ` [PATCH v1 24/32] net/ntnic: add nt400d13 PRM module reset Serhii Iliushyk
2025-02-20 22:03 ` [PATCH v1 25/32] net/ntnic: add SPI v3 support for FPGA Serhii Iliushyk
2025-02-20 22:03 ` [PATCH v1 26/32] net/ntnic: add i2cm init Serhii Iliushyk
2025-02-20 22:03 ` [PATCH v1 27/32] net/ntnic: add pca init Serhii Iliushyk
2025-02-20 22:03 ` [PATCH v1 28/32] net/ntnic: add pcal init Serhii Iliushyk
2025-02-20 22:03 ` [PATCH v1 29/32] net/ntnic: add reset PHY init Serhii Iliushyk
2025-02-20 22:03 ` [PATCH v1 30/32] net/ntnic: add igam module init Serhii Iliushyk
2025-02-20 22:03 ` [PATCH v1 31/32] net/ntnic: init IGAM and config PLL for FPGA Serhii Iliushyk
2025-02-20 22:03 ` [PATCH v1 32/32] net/ntnic: revert untrusted loop bound Serhii Iliushyk
2025-02-20 22:31 ` Stephen Hemminger
2025-02-20 23:49 ` [PATCH v1 00/32] add new adapter NT400D13 Stephen Hemminger
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