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Signed-off-by: Danylo Vodopianov --- .../ntnic/nthw/core/include/nthw_phy_tile.h | 39 ++ .../nt400dxx/reset/nthw_fpga_rst_nt400dxx.c | 16 + drivers/net/ntnic/nthw/core/nthw_phy_tile.c | 598 ++++++++++++++++++ 3 files changed, 653 insertions(+) diff --git a/drivers/net/ntnic/nthw/core/include/nthw_phy_tile.h b/drivers/net/ntnic/nthw/core/include/nthw_phy_tile.h index 68d8455b8d..ba044a5091 100644 --- a/drivers/net/ntnic/nthw/core/include/nthw_phy_tile.h +++ b/drivers/net/ntnic/nthw/core/include/nthw_phy_tile.h @@ -9,12 +9,16 @@ #include "nthw_fpga_model.h" enum mac_pcs_mode_e { + MAC_PCS_MODE_8x10_25, + MAC_PCS_MODE_2X40, MAC_PCS_MODE_2X100 }; struct nt_phy_tile { nthw_fpga_t *mp_fpga; + nthw_module_t *m_mod_phy_tile; + int mn_phy_tile_instance; int mn_fpga_version; @@ -27,6 +31,7 @@ struct nt_phy_tile { nthw_field_t *mp_fld_port_xcvr_base_busy[2][4]; nthw_field_t *mp_fld_port_xcvr_base_cmd[2][4]; + nthw_register_t *mp_reg_port_xcvr_data[2][4]; nthw_field_t *mp_fld_port_xcvr_data_data[2][4]; nthw_register_t *mp_reg_port_eth_base[2]; @@ -34,27 +39,44 @@ struct nt_phy_tile { nthw_field_t *mp_fld_port_eth_base_busy[2]; nthw_field_t *mp_fld_port_eth_base_cmd[2]; + nthw_register_t *mp_reg_port_eth_data[2]; nthw_field_t *mp_fld_port_eth_data_data[2]; nthw_register_t *mp_reg_link_summary[2]; nthw_field_t *mp_fld_link_summary_nt_phy_link_state[2]; nthw_field_t *mp_fld_link_summary_ll_nt_phy_link_state[2]; nthw_field_t *mp_fld_link_summary_link_down_cnt[2]; + nthw_field_t *mp_fld_link_summary_ll_rx_block_lock[2]; + nthw_field_t *mp_fld_link_summary_ll_rx_am_lock[2]; + nthw_field_t *mp_fld_link_summary_lh_rx_high_bit_error_rate[2]; nthw_field_t *mp_fld_link_summary_lh_received_local_fault[2]; nthw_field_t *mp_fld_link_summary_lh_remote_fault[2]; + nthw_register_t *mp_reg_port_status[2]; + nthw_field_t *mp_fld_port_status_rx_pcs_fully_aligned[2]; nthw_field_t *mp_fld_port_status_rx_hi_ber[2]; + nthw_field_t *mp_fld_port_status_rx_remote_fault[2]; + nthw_field_t *mp_fld_port_status_rx_local_fault[2]; nthw_field_t *mp_fld_port_status_rx_am_lock[2]; nthw_field_t *mp_fld_port_status_reset_ackn[2]; nthw_field_t *mp_fld_port_status_tx_lanes_stable[2]; + nthw_field_t *mp_fld_port_status_tx_pll_locked[2]; + nthw_field_t *mp_fld_port_status_sys_pll_locked[2]; nthw_field_t *mp_fld_port_status_tx_reset_ackn[2]; nthw_field_t *mp_fld_port_status_rx_reset_ackn[2]; + nthw_register_t *mp_reg_port_config[2]; + nthw_field_t *mp_fld_port_config_dyn_reset; nthw_field_t *mp_fld_port_config_reset[2]; nthw_field_t *mp_fld_port_config_rx_reset[2]; nthw_field_t *mp_fld_port_config_tx_reset[2]; + nthw_field_t *mp_fld_port_config_nt_linkup_latency[2]; + nthw_field_t *mp_fld_port_config_nt_force_linkdown[2]; + nthw_field_t *mp_fld_port_config_nt_auto_force_linkdown[2]; + nthw_register_t *mp_reg_port_comp[2]; nthw_field_t *mp_fld_port_comp_rx_compensation[2]; + nthw_field_t *mp_fld_port_comp_tx_compensation[2]; nthw_register_t *mp_reg_dyn_reconfig_base; nthw_field_t *mp_fld_dyn_reconfig_base_ptr; @@ -64,17 +86,34 @@ struct nt_phy_tile { nthw_register_t *mp_reg_dyn_reconfig_data; nthw_field_t *mp_fld_dyn_reconfig_data_data; + nthw_register_t *mp_reg_scratch; nthw_field_t *mp_fld_scratch_data; + nthw_register_t *mp_reg_dr_cfg; + nthw_field_t *mp_fld_reg_dr_cfg_features; + nthw_field_t *mp_fld_reg_dr_cfg_tx_flush_level; + nthw_register_t *mp_reg_dr_cfg_status; nthw_field_t *mp_fld_dr_cfg_status_curr_profile_id; nthw_field_t *mp_fld_dr_cfg_status_in_progress; nthw_field_t *mp_fld_dr_cfg_status_error; + + nthw_register_t *mp_reg_sys_pll; + nthw_field_t *mp_fld_sys_pll_set_rdy; + nthw_field_t *mp_fld_sys_pll_get_rdy; + nthw_field_t *mp_fld_sys_pll_system_pll_lock; + nthw_field_t *mp_fld_sys_pll_en_ref_clk_fgt; + nthw_field_t *mp_fld_sys_pll_disable_ref_clk_monitor; + nthw_field_t *mp_fld_sys_pll_ref_clk_fgt_enabled; + nthw_field_t *mp_fld_sys_pll_forward_rst; + nthw_field_t *mp_fld_sys_pll_force_rst; }; typedef struct nt_phy_tile nthw_phy_tile_t; typedef struct nt_phy_tile nt_phy_tile; +nthw_phy_tile_t *nthw_phy_tile_new(void); +int nthw_phy_tile_init(nthw_phy_tile_t *p, nthw_fpga_t *p_fpga, int mn_phy_tile_instance); void nthw_phy_tile_set_tx_pol_inv(nthw_phy_tile_t *p, uint8_t intf_no, uint8_t lane, bool invert); void nthw_phy_tile_set_rx_pol_inv(nthw_phy_tile_t *p, uint8_t intf_no, uint8_t lane, bool invert); void nthw_phy_tile_set_host_loopback(nthw_phy_tile_t *p, uint8_t intf_no, uint8_t lane, diff --git a/drivers/net/ntnic/nthw/core/nt400dxx/reset/nthw_fpga_rst_nt400dxx.c b/drivers/net/ntnic/nthw/core/nt400dxx/reset/nthw_fpga_rst_nt400dxx.c index c8fd37d0ff..35cbaea81e 100644 --- a/drivers/net/ntnic/nthw/core/nt400dxx/reset/nthw_fpga_rst_nt400dxx.c +++ b/drivers/net/ntnic/nthw/core/nt400dxx/reset/nthw_fpga_rst_nt400dxx.c @@ -181,7 +181,23 @@ static int nthw_fpga_rst_nt400dxx_init(struct fpga_info_s *p_fpga_info) static int nthw_fpga_rst_nt400dxx_reset(struct fpga_info_s *p_fpga_info) { + const char *const p_adapter_id_str = p_fpga_info->mp_adapter_id_str; + nthw_fpga_t *p_fpga = NULL; + + p_fpga = p_fpga_info->mp_fpga; + assert(p_fpga_info); + + NT_LOG(DBG, NTHW, "%s: %s: BEGIN", p_adapter_id_str, __PRETTY_FUNCTION__); + + /* Create Phy Tile module */ + p_fpga_info->mp_nthw_agx.p_phy_tile = nthw_phy_tile_new(); + + if (nthw_phy_tile_init(p_fpga_info->mp_nthw_agx.p_phy_tile, p_fpga, 0)) { + NT_LOG(ERR, NTHW, "%s: Failed to create Phy Tile Module", p_adapter_id_str); + return -1; + } + return 0; } diff --git a/drivers/net/ntnic/nthw/core/nthw_phy_tile.c b/drivers/net/ntnic/nthw/core/nthw_phy_tile.c index a8c2d03be9..f78d8263f5 100644 --- a/drivers/net/ntnic/nthw/core/nthw_phy_tile.c +++ b/drivers/net/ntnic/nthw/core/nthw_phy_tile.c @@ -44,6 +44,604 @@ static const uint32_t eth_soft_csr1 = 0x200; static const uint32_t eth_soft_csr2 = 0x204; static const uint32_t eth_soft_csr3 = 0x208; +nthw_phy_tile_t *nthw_phy_tile_new(void) +{ + nthw_phy_tile_t *p = malloc(sizeof(nthw_phy_tile_t)); + + if (p) + memset(p, 0, sizeof(nthw_phy_tile_t)); + + return p; +} + +int nthw_phy_tile_init(nthw_phy_tile_t *p, nthw_fpga_t *p_fpga, int mn_phy_tile_instance) +{ + const char *const p_adapter_id_str = p_fpga->p_fpga_info->mp_adapter_id_str; + nthw_module_t *mod = nthw_fpga_query_module(p_fpga, MOD_PHY_TILE, mn_phy_tile_instance); + + if (p == NULL) + return mod == NULL ? -1 : 0; + + if (mod == NULL) { + NT_LOG(ERR, NTHW, "%s: PHY_TILE %d: no such instance", p_adapter_id_str, + mn_phy_tile_instance); + return -1; + } + + p->mp_fpga = p_fpga; + p->mn_phy_tile_instance = mn_phy_tile_instance; + + p->m_mod_phy_tile = mod; + + p->mn_fpga_revision = p_fpga->mn_fpga_revision; + p->mn_fpga_version = p_fpga->mn_fpga_version; + + switch (p_fpga->mn_product_id) { + case 9569: + case 9574: + p->mac_pcs_mode = MAC_PCS_MODE_2X100; + break; + + default: + NT_LOG_DBG(DBG, NTHW, "unknown product ID: %u", p_fpga->mn_product_id); + break; + } + + /* Port 0 Base 0..3 */ + p->mp_reg_port_xcvr_base[0][0] = + nthw_module_get_register(p->m_mod_phy_tile, PHY_TILE_PORT_0_XCVR_0_BASE); + p->mp_fld_port_xcvr_base_ptr[0][0] = + nthw_register_get_field(p->mp_reg_port_xcvr_base[0][0], + PHY_TILE_PORT_0_XCVR_0_BASE_PTR); + p->mp_fld_port_xcvr_base_busy[0][0] = + nthw_register_get_field(p->mp_reg_port_xcvr_base[0][0], + PHY_TILE_PORT_0_XCVR_0_BASE_BUSY); + p->mp_fld_port_xcvr_base_cmd[0][0] = + nthw_register_get_field(p->mp_reg_port_xcvr_base[0][0], + PHY_TILE_PORT_0_XCVR_0_BASE_CMD); + + p->mp_reg_port_xcvr_base[0][1] = + nthw_module_get_register(p->m_mod_phy_tile, PHY_TILE_PORT_0_XCVR_1_BASE); + p->mp_fld_port_xcvr_base_ptr[0][1] = + nthw_register_get_field(p->mp_reg_port_xcvr_base[0][1], + PHY_TILE_PORT_0_XCVR_1_BASE_PTR); + p->mp_fld_port_xcvr_base_busy[0][1] = + nthw_register_get_field(p->mp_reg_port_xcvr_base[0][1], + PHY_TILE_PORT_0_XCVR_1_BASE_BUSY); + p->mp_fld_port_xcvr_base_cmd[0][1] = + nthw_register_get_field(p->mp_reg_port_xcvr_base[0][1], + PHY_TILE_PORT_0_XCVR_1_BASE_CMD); + + p->mp_reg_port_xcvr_base[0][2] = + nthw_module_get_register(p->m_mod_phy_tile, PHY_TILE_PORT_0_XCVR_2_BASE); + p->mp_fld_port_xcvr_base_ptr[0][2] = + nthw_register_get_field(p->mp_reg_port_xcvr_base[0][2], + PHY_TILE_PORT_0_XCVR_2_BASE_PTR); + p->mp_fld_port_xcvr_base_busy[0][2] = + nthw_register_get_field(p->mp_reg_port_xcvr_base[0][2], + PHY_TILE_PORT_0_XCVR_2_BASE_BUSY); + p->mp_fld_port_xcvr_base_cmd[0][2] = + nthw_register_get_field(p->mp_reg_port_xcvr_base[0][2], + PHY_TILE_PORT_0_XCVR_2_BASE_CMD); + + p->mp_reg_port_xcvr_base[0][3] = + nthw_module_get_register(p->m_mod_phy_tile, PHY_TILE_PORT_0_XCVR_3_BASE); + p->mp_fld_port_xcvr_base_ptr[0][3] = + nthw_register_get_field(p->mp_reg_port_xcvr_base[0][3], + PHY_TILE_PORT_0_XCVR_3_BASE_PTR); + p->mp_fld_port_xcvr_base_busy[0][3] = + nthw_register_get_field(p->mp_reg_port_xcvr_base[0][3], + PHY_TILE_PORT_0_XCVR_3_BASE_BUSY); + p->mp_fld_port_xcvr_base_cmd[0][3] = + nthw_register_get_field(p->mp_reg_port_xcvr_base[0][3], + PHY_TILE_PORT_0_XCVR_3_BASE_CMD); + + /* Port 0 Data 0..3 */ + p->mp_reg_port_xcvr_data[0][0] = + nthw_module_get_register(p->m_mod_phy_tile, PHY_TILE_PORT_0_XCVR_0_DATA); + p->mp_fld_port_xcvr_data_data[0][0] = + nthw_register_get_field(p->mp_reg_port_xcvr_data[0][0], + PHY_TILE_PORT_0_XCVR_0_DATA_DATA); + + p->mp_reg_port_xcvr_data[0][1] = + nthw_module_get_register(p->m_mod_phy_tile, PHY_TILE_PORT_0_XCVR_1_DATA); + p->mp_fld_port_xcvr_data_data[0][1] = + nthw_register_get_field(p->mp_reg_port_xcvr_data[0][1], + PHY_TILE_PORT_0_XCVR_1_DATA_DATA); + + p->mp_reg_port_xcvr_data[0][2] = + nthw_module_get_register(p->m_mod_phy_tile, PHY_TILE_PORT_0_XCVR_2_DATA); + p->mp_fld_port_xcvr_data_data[0][2] = + nthw_register_get_field(p->mp_reg_port_xcvr_data[0][2], + PHY_TILE_PORT_0_XCVR_2_DATA_DATA); + + p->mp_reg_port_xcvr_data[0][3] = + nthw_module_get_register(p->m_mod_phy_tile, PHY_TILE_PORT_0_XCVR_3_DATA); + p->mp_fld_port_xcvr_data_data[0][3] = + nthw_register_get_field(p->mp_reg_port_xcvr_data[0][3], + PHY_TILE_PORT_0_XCVR_3_DATA_DATA); + + /* Port 1 Base 0..3 */ + p->mp_reg_port_xcvr_base[1][0] = + nthw_module_get_register(p->m_mod_phy_tile, PHY_TILE_PORT_1_XCVR_0_BASE); + p->mp_fld_port_xcvr_base_ptr[1][0] = + nthw_register_get_field(p->mp_reg_port_xcvr_base[1][0], + PHY_TILE_PORT_1_XCVR_0_BASE_PTR); + p->mp_fld_port_xcvr_base_busy[1][0] = + nthw_register_get_field(p->mp_reg_port_xcvr_base[1][0], + PHY_TILE_PORT_1_XCVR_0_BASE_BUSY); + p->mp_fld_port_xcvr_base_cmd[1][0] = + nthw_register_get_field(p->mp_reg_port_xcvr_base[1][0], + PHY_TILE_PORT_1_XCVR_0_BASE_CMD); + + p->mp_reg_port_xcvr_base[1][1] = + nthw_module_get_register(p->m_mod_phy_tile, PHY_TILE_PORT_1_XCVR_1_BASE); + p->mp_fld_port_xcvr_base_ptr[1][1] = + nthw_register_get_field(p->mp_reg_port_xcvr_base[1][1], + PHY_TILE_PORT_1_XCVR_1_BASE_PTR); + p->mp_fld_port_xcvr_base_busy[1][1] = + nthw_register_get_field(p->mp_reg_port_xcvr_base[1][1], + PHY_TILE_PORT_1_XCVR_1_BASE_BUSY); + p->mp_fld_port_xcvr_base_cmd[1][1] = + nthw_register_get_field(p->mp_reg_port_xcvr_base[1][1], + PHY_TILE_PORT_1_XCVR_1_BASE_CMD); + + p->mp_reg_port_xcvr_base[1][2] = + nthw_module_get_register(p->m_mod_phy_tile, PHY_TILE_PORT_1_XCVR_2_BASE); + p->mp_fld_port_xcvr_base_ptr[1][2] = + nthw_register_get_field(p->mp_reg_port_xcvr_base[1][2], + PHY_TILE_PORT_1_XCVR_2_BASE_PTR); + p->mp_fld_port_xcvr_base_busy[1][2] = + nthw_register_get_field(p->mp_reg_port_xcvr_base[1][2], + PHY_TILE_PORT_1_XCVR_2_BASE_BUSY); + p->mp_fld_port_xcvr_base_cmd[1][2] = + nthw_register_get_field(p->mp_reg_port_xcvr_base[1][2], + PHY_TILE_PORT_1_XCVR_2_BASE_CMD); + + p->mp_reg_port_xcvr_base[1][3] = + nthw_module_get_register(p->m_mod_phy_tile, PHY_TILE_PORT_1_XCVR_3_BASE); + p->mp_fld_port_xcvr_base_ptr[1][3] = + nthw_register_get_field(p->mp_reg_port_xcvr_base[1][3], + PHY_TILE_PORT_1_XCVR_3_BASE_PTR); + p->mp_fld_port_xcvr_base_busy[1][3] = + nthw_register_get_field(p->mp_reg_port_xcvr_base[1][3], + PHY_TILE_PORT_1_XCVR_3_BASE_BUSY); + p->mp_fld_port_xcvr_base_cmd[1][3] = + nthw_register_get_field(p->mp_reg_port_xcvr_base[1][3], + PHY_TILE_PORT_1_XCVR_3_BASE_CMD); + + /* Port 1 Data 0..3 */ + p->mp_reg_port_xcvr_data[1][0] = + nthw_module_get_register(p->m_mod_phy_tile, PHY_TILE_PORT_1_XCVR_0_DATA); + p->mp_fld_port_xcvr_data_data[1][0] = + nthw_register_get_field(p->mp_reg_port_xcvr_data[1][0], + PHY_TILE_PORT_1_XCVR_0_DATA_DATA); + + p->mp_reg_port_xcvr_data[1][1] = + nthw_module_get_register(p->m_mod_phy_tile, PHY_TILE_PORT_1_XCVR_1_DATA); + p->mp_fld_port_xcvr_data_data[1][1] = + nthw_register_get_field(p->mp_reg_port_xcvr_data[1][1], + PHY_TILE_PORT_1_XCVR_1_DATA_DATA); + + p->mp_reg_port_xcvr_data[1][2] = + nthw_module_get_register(p->m_mod_phy_tile, PHY_TILE_PORT_1_XCVR_2_DATA); + p->mp_fld_port_xcvr_data_data[1][2] = + nthw_register_get_field(p->mp_reg_port_xcvr_data[1][2], + PHY_TILE_PORT_1_XCVR_2_DATA_DATA); + + p->mp_reg_port_xcvr_data[1][3] = + nthw_module_get_register(p->m_mod_phy_tile, PHY_TILE_PORT_1_XCVR_3_DATA); + p->mp_fld_port_xcvr_data_data[1][3] = + nthw_register_get_field(p->mp_reg_port_xcvr_data[1][3], + PHY_TILE_PORT_1_XCVR_3_DATA_DATA); + + if (nthw_module_is_version_newer(p->m_mod_phy_tile, 0, 3)) { + if (p->mac_pcs_mode == MAC_PCS_MODE_2X100 || + p->mac_pcs_mode == MAC_PCS_MODE_8x10_25) { + /* DYN_RECONFIG */ + p->mp_reg_dyn_reconfig_base = + nthw_module_get_register(p->m_mod_phy_tile, + PHY_TILE_DYN_RECONFIG_BASE); + p->mp_fld_dyn_reconfig_base_ptr = + nthw_register_get_field(p->mp_reg_dyn_reconfig_base, + PHY_TILE_DYN_RECONFIG_BASE_PTR); + p->mp_fld_dyn_reconfig_base_busy = + nthw_register_get_field(p->mp_reg_dyn_reconfig_base, + PHY_TILE_DYN_RECONFIG_BASE_BUSY); + p->mp_fld_dyn_reconfig_base_cmd = + nthw_register_get_field(p->mp_reg_dyn_reconfig_base, + PHY_TILE_DYN_RECONFIG_BASE_CMD); + + p->mp_reg_dyn_reconfig_data = + nthw_module_get_register(p->m_mod_phy_tile, + PHY_TILE_DYN_RECONFIG_DATA); + p->mp_fld_dyn_reconfig_data_data = + nthw_register_get_field(p->mp_reg_dyn_reconfig_data, + PHY_TILE_DYN_RECONFIG_DATA_DATA); + } + + /* Port 0 Eth Base */ + p->mp_reg_port_eth_base[0] = + nthw_module_get_register(p->m_mod_phy_tile, PHY_TILE_PORT_0_ETH_0_BASE); + p->mp_fld_port_eth_base_ptr[0] = + nthw_register_get_field(p->mp_reg_port_eth_base[0], + PHY_TILE_PORT_0_ETH_0_BASE_PTR); + p->mp_fld_port_eth_base_busy[0] = + nthw_register_get_field(p->mp_reg_port_eth_base[0], + PHY_TILE_PORT_0_ETH_0_BASE_BUSY); + p->mp_fld_port_eth_base_cmd[0] = + nthw_register_get_field(p->mp_reg_port_eth_base[0], + PHY_TILE_PORT_0_ETH_0_BASE_CMD); + + /* Port 1 Eth Base */ + p->mp_reg_port_eth_base[1] = + nthw_module_get_register(p->m_mod_phy_tile, PHY_TILE_PORT_1_ETH_0_BASE); + p->mp_fld_port_eth_base_ptr[1] = + nthw_register_get_field(p->mp_reg_port_eth_base[1], + PHY_TILE_PORT_1_ETH_0_BASE_PTR); + p->mp_fld_port_eth_base_busy[1] = + nthw_register_get_field(p->mp_reg_port_eth_base[1], + PHY_TILE_PORT_1_ETH_0_BASE_BUSY); + p->mp_fld_port_eth_base_cmd[1] = + nthw_register_get_field(p->mp_reg_port_eth_base[1], + PHY_TILE_PORT_1_ETH_0_BASE_CMD); + + /* Port 0 Eth Data */ + p->mp_reg_port_eth_data[0] = + nthw_module_get_register(p->m_mod_phy_tile, PHY_TILE_PORT_0_ETH_0_DATA); + p->mp_fld_port_eth_data_data[0] = + nthw_register_get_field(p->mp_reg_port_eth_data[0], + PHY_TILE_PORT_0_ETH_0_DATA_DATA); + + /* Port 1 Eth Data 0..3 */ + p->mp_reg_port_eth_data[1] = + nthw_module_get_register(p->m_mod_phy_tile, PHY_TILE_PORT_1_ETH_0_DATA); + p->mp_fld_port_eth_data_data[1] = + nthw_register_get_field(p->mp_reg_port_eth_data[1], + PHY_TILE_PORT_1_ETH_0_DATA_DATA); + } + + p->mp_reg_link_summary[0] = + nthw_module_get_register(p->m_mod_phy_tile, PHY_TILE_LINK_SUMMARY_0); + p->mp_fld_link_summary_nt_phy_link_state[0] = + nthw_register_get_field(p->mp_reg_link_summary[0], + PHY_TILE_LINK_SUMMARY_0_NT_PHY_LINK_STATE); + p->mp_fld_link_summary_ll_nt_phy_link_state[0] = + nthw_register_get_field(p->mp_reg_link_summary[0], + PHY_TILE_LINK_SUMMARY_0_LL_PHY_LINK_STATE); + p->mp_fld_link_summary_link_down_cnt[0] = + nthw_register_get_field(p->mp_reg_link_summary[0], + PHY_TILE_LINK_SUMMARY_0_LINK_DOWN_CNT); + p->mp_fld_link_summary_ll_rx_block_lock[0] = + nthw_register_get_field(p->mp_reg_link_summary[0], + PHY_TILE_LINK_SUMMARY_0_LL_RX_BLOCK_LOCK); + p->mp_fld_link_summary_ll_rx_am_lock[0] = + nthw_register_get_field(p->mp_reg_link_summary[0], + PHY_TILE_LINK_SUMMARY_0_LL_RX_AM_LOCK); + p->mp_fld_link_summary_lh_rx_high_bit_error_rate[0] = + nthw_register_get_field(p->mp_reg_link_summary[0], + PHY_TILE_LINK_SUMMARY_0_LH_RX_HIGH_BIT_ERROR_RATE); + p->mp_fld_link_summary_lh_received_local_fault[0] = + nthw_register_get_field(p->mp_reg_link_summary[0], + PHY_TILE_LINK_SUMMARY_0_LH_RECEIVED_LOCAL_FAULT); + p->mp_fld_link_summary_lh_remote_fault[0] = + nthw_register_get_field(p->mp_reg_link_summary[0], + PHY_TILE_LINK_SUMMARY_0_LH_REMOTE_FAULT); + + p->mp_reg_link_summary[1] = + nthw_module_get_register(p->m_mod_phy_tile, PHY_TILE_LINK_SUMMARY_1); + p->mp_fld_link_summary_nt_phy_link_state[1] = + nthw_register_get_field(p->mp_reg_link_summary[1], + PHY_TILE_LINK_SUMMARY_1_NT_PHY_LINK_STATE); + p->mp_fld_link_summary_ll_nt_phy_link_state[1] = + nthw_register_get_field(p->mp_reg_link_summary[1], + PHY_TILE_LINK_SUMMARY_1_LL_PHY_LINK_STATE); + p->mp_fld_link_summary_link_down_cnt[1] = + nthw_register_get_field(p->mp_reg_link_summary[1], + PHY_TILE_LINK_SUMMARY_1_LINK_DOWN_CNT); + p->mp_fld_link_summary_ll_rx_block_lock[1] = + nthw_register_get_field(p->mp_reg_link_summary[1], + PHY_TILE_LINK_SUMMARY_1_LL_RX_BLOCK_LOCK); + p->mp_fld_link_summary_ll_rx_am_lock[1] = + nthw_register_get_field(p->mp_reg_link_summary[1], + PHY_TILE_LINK_SUMMARY_1_LL_RX_AM_LOCK); + p->mp_fld_link_summary_lh_rx_high_bit_error_rate[1] = + nthw_register_get_field(p->mp_reg_link_summary[1], + PHY_TILE_LINK_SUMMARY_1_LH_RX_HIGH_BIT_ERROR_RATE); + p->mp_fld_link_summary_lh_received_local_fault[1] = + nthw_register_get_field(p->mp_reg_link_summary[1], + PHY_TILE_LINK_SUMMARY_1_LH_RECEIVED_LOCAL_FAULT); + p->mp_fld_link_summary_lh_remote_fault[1] = + nthw_register_get_field(p->mp_reg_link_summary[1], + PHY_TILE_LINK_SUMMARY_1_LH_REMOTE_FAULT); + + if (nthw_module_is_version_newer(p->m_mod_phy_tile, 0, 4)) { + p->mp_reg_port_status[0] = + nthw_module_get_register(p->m_mod_phy_tile, PHY_TILE_PORT_STATUS_0); + p->mp_fld_port_status_rx_pcs_fully_aligned[0] = + nthw_register_get_field(p->mp_reg_port_status[0], + PHY_TILE_PORT_STATUS_0_RX_PCS_FULLY_ALIGNED); + p->mp_fld_port_status_rx_hi_ber[0] = + nthw_register_get_field(p->mp_reg_port_status[0], + PHY_TILE_PORT_STATUS_0_RX_HI_BER); + p->mp_fld_port_status_rx_remote_fault[0] = + nthw_register_get_field(p->mp_reg_port_status[0], + PHY_TILE_PORT_STATUS_0_RX_REMOTE_FAULT); + p->mp_fld_port_status_rx_local_fault[0] = + nthw_register_get_field(p->mp_reg_port_status[0], + PHY_TILE_PORT_STATUS_0_RX_LOCAL_FAULT); + p->mp_fld_port_status_rx_am_lock[0] = + nthw_register_get_field(p->mp_reg_port_status[0], + PHY_TILE_PORT_STATUS_0_RX_AM_LOCK); + p->mp_fld_port_status_reset_ackn[0] = + nthw_register_get_field(p->mp_reg_port_status[0], + PHY_TILE_PORT_STATUS_0_RESET_ACK_N); + p->mp_fld_port_status_tx_lanes_stable[0] = + nthw_register_get_field(p->mp_reg_port_status[0], + PHY_TILE_PORT_STATUS_0_TX_LANES_STABLE); + p->mp_fld_port_status_tx_pll_locked[0] = + nthw_register_get_field(p->mp_reg_port_status[0], + PHY_TILE_PORT_STATUS_0_TX_PLL_LOCKED); + p->mp_fld_port_status_sys_pll_locked[0] = + nthw_register_get_field(p->mp_reg_port_status[0], + PHY_TILE_PORT_STATUS_0_SYS_PLL_LOCKED); + p->mp_fld_port_status_tx_reset_ackn[0] = + nthw_register_get_field(p->mp_reg_port_status[0], + PHY_TILE_PORT_STATUS_0_TX_RESET_ACK_N); + p->mp_fld_port_status_rx_reset_ackn[0] = + nthw_register_get_field(p->mp_reg_port_status[0], + PHY_TILE_PORT_STATUS_0_RX_RESET_ACK_N); + + p->mp_reg_port_status[1] = + nthw_module_get_register(p->m_mod_phy_tile, PHY_TILE_PORT_STATUS_1); + p->mp_fld_port_status_rx_pcs_fully_aligned[1] = + nthw_register_get_field(p->mp_reg_port_status[1], + PHY_TILE_PORT_STATUS_1_RX_PCS_FULLY_ALIGNED); + p->mp_fld_port_status_rx_hi_ber[1] = + nthw_register_get_field(p->mp_reg_port_status[1], + PHY_TILE_PORT_STATUS_1_RX_HI_BER); + p->mp_fld_port_status_rx_remote_fault[1] = + nthw_register_get_field(p->mp_reg_port_status[1], + PHY_TILE_PORT_STATUS_1_RX_REMOTE_FAULT); + p->mp_fld_port_status_rx_local_fault[1] = + nthw_register_get_field(p->mp_reg_port_status[1], + PHY_TILE_PORT_STATUS_1_RX_LOCAL_FAULT); + p->mp_fld_port_status_rx_am_lock[1] = + nthw_register_get_field(p->mp_reg_port_status[1], + PHY_TILE_PORT_STATUS_1_RX_AM_LOCK); + p->mp_fld_port_status_reset_ackn[1] = + nthw_register_get_field(p->mp_reg_port_status[1], + PHY_TILE_PORT_STATUS_1_RESET_ACK_N); + p->mp_fld_port_status_tx_lanes_stable[1] = + nthw_register_get_field(p->mp_reg_port_status[1], + PHY_TILE_PORT_STATUS_1_TX_LANES_STABLE); + p->mp_fld_port_status_tx_pll_locked[1] = + nthw_register_get_field(p->mp_reg_port_status[1], + PHY_TILE_PORT_STATUS_1_TX_PLL_LOCKED); + p->mp_fld_port_status_sys_pll_locked[1] = + nthw_register_get_field(p->mp_reg_port_status[1], + PHY_TILE_PORT_STATUS_1_SYS_PLL_LOCKED); + p->mp_fld_port_status_tx_reset_ackn[1] = + nthw_register_get_field(p->mp_reg_port_status[1], + PHY_TILE_PORT_STATUS_1_TX_RESET_ACK_N); + p->mp_fld_port_status_rx_reset_ackn[1] = + nthw_register_get_field(p->mp_reg_port_status[1], + PHY_TILE_PORT_STATUS_1_RX_RESET_ACK_N); + + } else { + p->mp_reg_port_status[0] = + nthw_module_get_register(p->m_mod_phy_tile, PHY_TILE_PORT_STATUS); + p->mp_fld_port_status_rx_pcs_fully_aligned[0] = + nthw_register_get_field(p->mp_reg_port_status[0], + PHY_TILE_PORT_STATUS_RX_PCS_FULLY_ALIGNED_0); + p->mp_fld_port_status_rx_hi_ber[0] = + nthw_register_get_field(p->mp_reg_port_status[0], + PHY_TILE_PORT_STATUS_RX_HI_BER_0); + p->mp_fld_port_status_rx_remote_fault[0] = + nthw_register_get_field(p->mp_reg_port_status[0], + PHY_TILE_PORT_STATUS_RX_REMOTE_FAULT_0); + p->mp_fld_port_status_rx_local_fault[0] = + nthw_register_get_field(p->mp_reg_port_status[0], + PHY_TILE_PORT_STATUS_RX_LOCAL_FAULT_0); + p->mp_fld_port_status_rx_am_lock[0] = + nthw_register_get_field(p->mp_reg_port_status[0], + PHY_TILE_PORT_STATUS_RX_AM_LOCK_0); + + p->mp_fld_port_status_rx_pcs_fully_aligned[1] = + nthw_register_get_field(p->mp_reg_port_status[0], + PHY_TILE_PORT_STATUS_RX_PCS_FULLY_ALIGNED_1); + p->mp_fld_port_status_rx_hi_ber[1] = + nthw_register_get_field(p->mp_reg_port_status[0], + PHY_TILE_PORT_STATUS_RX_HI_BER_1); + p->mp_fld_port_status_rx_remote_fault[1] = + nthw_register_get_field(p->mp_reg_port_status[0], + PHY_TILE_PORT_STATUS_RX_REMOTE_FAULT_1); + p->mp_fld_port_status_rx_local_fault[1] = + nthw_register_get_field(p->mp_reg_port_status[0], + PHY_TILE_PORT_STATUS_RX_LOCAL_FAULT_1); + p->mp_fld_port_status_rx_am_lock[1] = + nthw_register_get_field(p->mp_reg_port_status[0], + PHY_TILE_PORT_STATUS_RX_AM_LOCK_1); + + p->mp_fld_port_status_reset_ackn[0] = NULL; + p->mp_fld_port_status_tx_lanes_stable[0] = NULL; + p->mp_fld_port_status_tx_pll_locked[0] = NULL; + p->mp_fld_port_status_sys_pll_locked[0] = NULL; + p->mp_fld_port_status_tx_reset_ackn[0] = NULL; + p->mp_fld_port_status_rx_reset_ackn[0] = NULL; + + p->mp_fld_port_status_reset_ackn[1] = NULL; + p->mp_fld_port_status_tx_lanes_stable[1] = NULL; + p->mp_fld_port_status_tx_pll_locked[1] = NULL; + p->mp_fld_port_status_sys_pll_locked[1] = NULL; + p->mp_fld_port_status_tx_reset_ackn[1] = NULL; + p->mp_fld_port_status_rx_reset_ackn[1] = NULL; + } + + if (nthw_module_is_version_newer(p->m_mod_phy_tile, 0, 4)) { + p->mp_reg_port_config[0] = + nthw_module_get_register(p->m_mod_phy_tile, PHY_TILE_PORT_CONFIG_0); + p->mp_fld_port_config_reset[0] = + nthw_register_query_field(p->mp_reg_port_config[0], + PHY_TILE_PORT_CONFIG_0_RST); + p->mp_fld_port_config_rx_reset[0] = + nthw_register_query_field(p->mp_reg_port_config[0], + PHY_TILE_PORT_CONFIG_0_RX_RST); + p->mp_fld_port_config_tx_reset[0] = + nthw_register_query_field(p->mp_reg_port_config[0], + PHY_TILE_PORT_CONFIG_0_TX_RST); + p->mp_fld_port_config_nt_linkup_latency[0] = + nthw_register_query_field(p->mp_reg_port_config[0], + PHY_TILE_PORT_CONFIG_0_NT_LINKUP_LATENCY); + p->mp_fld_port_config_nt_force_linkdown[0] = + nthw_register_query_field(p->mp_reg_port_config[0], + PHY_TILE_PORT_CONFIG_0_NT_FORCE_LINK_DOWN); + + if (nthw_module_is_version_newer(p->m_mod_phy_tile, 0, 10)) { + p->mp_fld_port_config_nt_auto_force_linkdown[0] = + nthw_register_query_field(p->mp_reg_port_config[0], + PHY_TILE_PORT_CONFIG_0_NT_AUTO_FORCE_LINK_DOWN); + } + + p->mp_reg_port_config[1] = + nthw_module_get_register(p->m_mod_phy_tile, PHY_TILE_PORT_CONFIG_1); + p->mp_fld_port_config_reset[1] = + nthw_register_query_field(p->mp_reg_port_config[1], + PHY_TILE_PORT_CONFIG_1_RST); + p->mp_fld_port_config_rx_reset[1] = + nthw_register_query_field(p->mp_reg_port_config[1], + PHY_TILE_PORT_CONFIG_1_RX_RST); + p->mp_fld_port_config_tx_reset[1] = + nthw_register_query_field(p->mp_reg_port_config[1], + PHY_TILE_PORT_CONFIG_1_TX_RST); + p->mp_fld_port_config_nt_linkup_latency[1] = + nthw_register_query_field(p->mp_reg_port_config[1], + PHY_TILE_PORT_CONFIG_1_NT_LINKUP_LATENCY); + p->mp_fld_port_config_nt_force_linkdown[1] = + nthw_register_query_field(p->mp_reg_port_config[1], + PHY_TILE_PORT_CONFIG_1_NT_FORCE_LINK_DOWN); + + if (nthw_module_is_version_newer(p->m_mod_phy_tile, 0, 10)) { + p->mp_fld_port_config_nt_auto_force_linkdown[1] = + nthw_register_query_field(p->mp_reg_port_config[1], + PHY_TILE_PORT_CONFIG_1_NT_AUTO_FORCE_LINK_DOWN); + } + + } else { + p->mp_reg_port_config[0] = + nthw_module_get_register(p->m_mod_phy_tile, PHY_TILE_PORT_CONFIG); + p->mp_fld_port_config_dyn_reset = + nthw_register_query_field(p->mp_reg_port_config[0], + PHY_TILE_PORT_CONFIG_DYN_RESET); + p->mp_fld_port_config_reset[0] = + nthw_register_query_field(p->mp_reg_port_config[0], + PHY_TILE_PORT_CONFIG_RESET_0); + p->mp_fld_port_config_rx_reset[0] = + nthw_register_get_field(p->mp_reg_port_config[0], + PHY_TILE_PORT_CONFIG_RX_RESET_0); + p->mp_fld_port_config_tx_reset[0] = + nthw_register_get_field(p->mp_reg_port_config[0], + PHY_TILE_PORT_CONFIG_TX_RESET_0); + p->mp_fld_port_config_reset[1] = + nthw_register_query_field(p->mp_reg_port_config[0], + PHY_TILE_PORT_CONFIG_RESET_1); + p->mp_fld_port_config_rx_reset[1] = + nthw_register_get_field(p->mp_reg_port_config[0], + PHY_TILE_PORT_CONFIG_RX_RESET_1); + p->mp_fld_port_config_tx_reset[1] = + nthw_register_get_field(p->mp_reg_port_config[0], + PHY_TILE_PORT_CONFIG_TX_RESET_1); + } + + p->mp_reg_port_comp[0] = nthw_module_get_register(p->m_mod_phy_tile, PHY_TILE_PORT_COMP_0); + p->mp_fld_port_comp_rx_compensation[0] = + nthw_register_get_field(p->mp_reg_port_comp[0], + PHY_TILE_PORT_COMP_0_RX_COMPENSATION); + p->mp_fld_port_comp_tx_compensation[0] = + nthw_register_get_field(p->mp_reg_port_comp[0], + PHY_TILE_PORT_COMP_0_TX_COMPENSATION); + p->mp_reg_port_comp[1] = nthw_module_get_register(p->m_mod_phy_tile, PHY_TILE_PORT_COMP_1); + p->mp_fld_port_comp_rx_compensation[1] = + nthw_register_get_field(p->mp_reg_port_comp[1], + PHY_TILE_PORT_COMP_1_RX_COMPENSATION); + p->mp_fld_port_comp_tx_compensation[1] = + nthw_register_get_field(p->mp_reg_port_comp[1], + PHY_TILE_PORT_COMP_1_TX_COMPENSATION); + + p->mp_reg_scratch = nthw_module_query_register(p->m_mod_phy_tile, PHY_TILE_SCRATCH); + + if (p->mp_reg_scratch) { + p->mp_fld_scratch_data = + nthw_register_query_field(p->mp_reg_scratch, PHY_TILE_SCRATCH_DATA); + } + + if (nthw_module_is_version_newer(p->m_mod_phy_tile, 0, 4)) { + p->mp_reg_dr_cfg = nthw_module_get_register(p->m_mod_phy_tile, PHY_TILE_DR_CFG); + p->mp_fld_port_config_dyn_reset = + nthw_register_get_field(p->mp_reg_dr_cfg, PHY_TILE_DR_CFG_DYN_RST); + + if (!p->mp_reg_scratch) { + p->mp_fld_scratch_data = + nthw_register_get_field(p->mp_reg_dr_cfg, PHY_TILE_DR_CFG_SCRATCH); + } + + p->mp_fld_reg_dr_cfg_features = + nthw_register_get_field(p->mp_reg_dr_cfg, PHY_TILE_DR_CFG_FEATURES); + + if (nthw_module_is_version_newer(p->m_mod_phy_tile, 0, 10)) { + p->mp_fld_reg_dr_cfg_tx_flush_level = + nthw_register_get_field(p->mp_reg_dr_cfg, + PHY_TILE_DR_CFG_TX_FLUSH_LEVEL); + } + } + + p->mp_reg_dr_cfg_status = + nthw_module_get_register(p->m_mod_phy_tile, PHY_TILE_DR_CFG_STATUS); + p->mp_fld_dr_cfg_status_curr_profile_id = + nthw_register_get_field(p->mp_reg_dr_cfg_status, + PHY_TILE_DR_CFG_STATUS_CURR_PROFILE_ID); + p->mp_fld_dr_cfg_status_in_progress = + nthw_register_get_field(p->mp_reg_dr_cfg_status, + PHY_TILE_DR_CFG_STATUS_IN_PROGRESS); + p->mp_fld_dr_cfg_status_error = + nthw_register_get_field(p->mp_reg_dr_cfg_status, PHY_TILE_DR_CFG_STATUS_ERROR); + + if (nthw_module_is_version_newer(p->m_mod_phy_tile, 0, 7)) { + p->mp_reg_sys_pll = nthw_module_get_register(p->m_mod_phy_tile, PHY_TILE_SYS_PLL); + p->mp_fld_sys_pll_set_rdy = + nthw_register_get_field(p->mp_reg_sys_pll, PHY_TILE_SYS_PLL_SET_RDY); + p->mp_fld_sys_pll_get_rdy = + nthw_register_get_field(p->mp_reg_sys_pll, PHY_TILE_SYS_PLL_GET_RDY); + p->mp_fld_sys_pll_system_pll_lock = + nthw_register_get_field(p->mp_reg_sys_pll, + PHY_TILE_SYS_PLL_SYSTEMPLL_LOCK); + p->mp_fld_sys_pll_en_ref_clk_fgt = + nthw_register_get_field(p->mp_reg_sys_pll, PHY_TILE_SYS_PLL_EN_REFCLK_FGT); + p->mp_fld_sys_pll_disable_ref_clk_monitor = + nthw_register_get_field(p->mp_reg_sys_pll, + PHY_TILE_SYS_PLL_DISABLE_REFCLK_MONITOR); + p->mp_fld_sys_pll_ref_clk_fgt_enabled = + nthw_register_get_field(p->mp_reg_sys_pll, + PHY_TILE_SYS_PLL_REFCLK_FGT_ENABLED); + p->mp_fld_sys_pll_forward_rst = + nthw_register_get_field(p->mp_reg_sys_pll, PHY_TILE_SYS_PLL_FORWARD_RST); + p->mp_fld_sys_pll_force_rst = + nthw_register_get_field(p->mp_reg_sys_pll, PHY_TILE_SYS_PLL_FORCE_RST); + + } else { + p->mp_fld_sys_pll_set_rdy = NULL; + p->mp_fld_sys_pll_get_rdy = NULL; + p->mp_fld_sys_pll_system_pll_lock = NULL; + p->mp_fld_sys_pll_en_ref_clk_fgt = NULL; + p->mp_fld_sys_pll_disable_ref_clk_monitor = NULL; + p->mp_fld_sys_pll_ref_clk_fgt_enabled = NULL; + p->mp_fld_sys_pll_forward_rst = NULL; + p->mp_fld_sys_pll_force_rst = NULL; + } + + return 0; +} + uint8_t nthw_phy_tile_get_no_intfs(nthw_phy_tile_t *p) { switch (p->mac_pcs_mode) { -- 2.45.0